WorldWideScience

Sample records for fpga basis entwicklung

  1. Der ATLAS LVL2-Trigger mit FPGA-Prozessoren : Entwicklung, Aufbau und Funktionsnachweis des hybriden FPGA/CPU-basierten Prozessorsystems ATLANTIS

    CERN Document Server

    Singpiel, Holger

    2000-01-01

    This thesis describes the conception and implementation of the hybrid FPGA/CPU based processing system ATLANTIS as trigger processor for the proposed ATLAS experiment at CERN. CompactPCI provides the close coupling of a multi FPGA system and a standard CPU. The system is scalable in computing power and flexible in use due to its partitioning into dedicated FPGA boards for computation, I/O tasks and a private communication. Main focus of the research activities based on the usage of the ATLANTIS system are two areas in the second level trigger (LVL2). First, the acceleration of time critical B physics trigger algorithms is the major aim. The execution of the full scan TRT algorithm on ATLANTIS, which has been used as a demonstrator, results in a speedup of 5.6 compared to a standard CPU. Next, the ATLANTIS system is used as a hardware platform for research work in conjunction with the ATLAS readout systems. For further studies a permanent installation of the ATLANTIS system in the LVL2 application testbed is f...

  2. Entwicklung, Implementierung and Test eines FPGA-Designs für die Level-1-Frontend-Elektronik des Äusseren Spurkammersystems im LHCb-Detektor

    CERN Document Server

    Nedos, Mirco

    For measurements of CP-violation in the B-meson system, as well as the search for new physics, the LHCb-experiment has been built at the Large Hadron Collider at CERN. One component of the sophisticated LHCb-detector is the Outer Tracker. Its measured data is transmitted serially via optical links into the readout network. For the interface between the frontend electronics on the detector and the data acquisition network a common readout board is used. This FPGA-based board, dubbed the TELL1, preprocesses the data. In this thesis the developments of the detector specific parts of the TELL1 firmware and the integration of the TELL1 board into the readout chain of the Outer Tracker are described. It covers the synchronisation and the error detection of the data received, as well as the generation of the Outer Tracker DAQ data format. In addition a zero-suppression algorithm has been implemented in the FPGA in order to reduce the network payload and guarantee operation at maximum trigger rate.

  3. Force to Rebalance Control of HRG and Suppression of Its Errors on the Basis of FPGA

    Directory of Open Access Journals (Sweden)

    Qingan Jiang

    2011-12-01

    Full Text Available A novel design of force to rebalance control for a hemispherical resonator gyro (HRG based on FPGA is demonstrated in this paper. The proposed design takes advantage of the automatic gain control loop and phase lock loop configuration in the drive mode while making full use of the quadrature control loop and rebalance control loop in controlling the oscillating dynamics in the sense mode. First, the math model of HRG with inhomogeneous damping and frequency split is theoretically analyzed. In addition, the major drift mechanisms in the HRG are described and the methods that can suppress the gyro drift are mentioned. Based on the math model and drift mechanisms suppression method, four control loops are employed to realize the manipulation of the HRG by using a FPGA circuit. The reference-phase loop and amplitude control loop are used to maintain the vibration of primary mode at its natural frequency with constant amplitude. The frequency split is readily eliminated by the quadrature loop with a DC voltage feedback from the quadrature component of the node. The secondary mode response to the angle rate input is nullified by the rebalance control loop. In order to validate the effect of the digital control of HRG, experiments are carried out with a turntable. The experimental results show that the design is suitable for the control of HRG which has good linearity scale factor and bias stability.

  4. Force to rebalance control of HRG and suppression of its errors on the basis of FPGA.

    Science.gov (United States)

    Wang, Xu; Wu, Wenqi; Luo, Bing; Fang, Zhen; Li, Yun; Jiang, Qingan

    2011-01-01

    A novel design of force to rebalance control for a hemispherical resonator gyro (HRG) based on FPGA is demonstrated in this paper. The proposed design takes advantage of the automatic gain control loop and phase lock loop configuration in the drive mode while making full use of the quadrature control loop and rebalance control loop in controlling the oscillating dynamics in the sense mode. First, the math model of HRG with inhomogeneous damping and frequency split is theoretically analyzed. In addition, the major drift mechanisms in the HRG are described and the methods that can suppress the gyro drift are mentioned. Based on the math model and drift mechanisms suppression method, four control loops are employed to realize the manipulation of the HRG by using a FPGA circuit. The reference-phase loop and amplitude control loop are used to maintain the vibration of primary mode at its natural frequency with constant amplitude. The frequency split is readily eliminated by the quadrature loop with a DC voltage feedback from the quadrature component of the node. The secondary mode response to the angle rate input is nullified by the rebalance control loop. In order to validate the effect of the digital control of HRG, experiments are carried out with a turntable. The experimental results show that the design is suitable for the control of HRG which has good linearity scale factor and bias stability.

  5. FPGA design

    CERN Document Server

    Simpson, Philip

    2010-01-01

    This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

  6. Entwicklung einer Methodik zur Generierung einer Datenbasis für Optimierungssysteme in der maritimen Leercontainerlogistik

    OpenAIRE

    Vojdani, Nina; Rösner, René

    2013-01-01

    Dieser Beitrag stellt ein Vorgehen zur Entwicklung einer Methodik zur Generierung einer praxisnahen Datenbasis für numerische Untersuchungen im Rahmen der maritimen Leercontainerlogistik vor. Das Vorgehen wird an einem exemplarischen Anwendungsfall verdeutlicht. Die Resultate sollen Testläufe für Szenarien der Leercontainerlogistik unterstützen und somit eine Basis für die Entwicklung und Bewertung organisatorischer Verbesserungsansätze, mathematischer Optimierungsmodelle, entsprechender Lösu...

  7. Development of biodegradable materials on the basis of renewable materials, starch, vegetable oils and natural fibres. Part 3: Derivation of starch of DS = 0.3 to 2.5. Final report; Entwicklung biologisch abbaubarer Werkstoffe auf der Basis nachwachsender Rohstoffe, Staerke, Pflanzenoel und Naturfasern. T. 3: Derivatisierung der Staerke von DS=0,3 bis 2,5. Abschlussbericht

    Energy Technology Data Exchange (ETDEWEB)

    Engelmann, G.; Lang, J.; Rafler, G.

    2002-01-01

    The last few years have seen rapid developments in the field of starch use in the polymer sector. Destructured starch, with suitable modifiers, can be processed into foils and formed parts by thermoplastic methods. Their properties during processing and use differ from those of conventional plastics, however. The main reason for this is the structural hydrophilia of starch and starch products, which reduces their technical applications. In this project, the fundamentals for starch-based materials with better material characteristics are to be developed in order to improve the chances of these economically and ecologically attractive materials on the market and enhance their range of applications. [German] In den letzten Jahren haben die Entwicklungen auf dem Gebiet des Staerkeeinsatzes im Polymersektor erhebliche Fortschritte gemacht. Destrukturierte Staerken lassen sich heute unter Zusatz geeigneter Modifikatoren nach bekannten Formgebungsverfahren thermoplastisch zu Folien und Formkoerpern verarbeiten. Das Eigenschaftsprofil der staerkebasierenden Materialien entspricht jedoch nicht demjenigen konventioneller Kunststoffe. Dies betrifft sowohl die Gebrauchs- als auch die Verarbeitungseigenschaften. Wesentliche Ursache dieser fuer viele Applikationen unzureichenden Materialeigenschaften ist die strukturbedingte Hydrophilie von Staerken und daraus hergestellten Produkten. Diese Hydrophilie fuehrt dann zu einer hohen Feuchtigkeitsempfindlichkeit von staerkebasierenden Materialien, die ihre Einsatzmoeglichkeiten in technischen Bereichen erheblich einschraenkt. In dem durch die Fachagentur Nachwachsende Rohstoffe gefoerderten Verbundprojekt ''Entwicklung bioabbaubarer Werkstoffe auf der Basis nachwachsender Rohstoffe, Staerke und Pflanzenoel'' sollen deshalb Grundlagen fuer staerkebasierende Werkstoffe bzw. Werkstoffkomponenten mit deutlich verbesserten Materialeigenschaften erarbeitet werden, um die Chancen dieser wirtschaftlich und oekologisch

  8. Aircraft Research Guideline 1999 - 2002: High pressure compressor - preliminary design as a basis for the development of an efficient and environmentally friendly core engine. Final report; Leitlinie Luftfahrtforschung 1999 - 2002: Hochdruckverdichter-Vorauslegung als Grundlagenuntersuchung zur Entwicklung eines Kerntriebwerkes fuer einen effizienten und umweltfreundlichen Antrieb. Schlussbericht

    Energy Technology Data Exchange (ETDEWEB)

    Klinger, H.

    2001-08-01

    This report completes the documentation for the research project 'High Pressure Compressor - Preliminary Design as Basis for the Development of an Efficient and Environmentally Friendly Core Engine' which was funded by the Ministry of Economics of State Brandenburg. The objective of the project is to deliver a preliminary compressor aerodynamic design as well as design studies for an efficient, weight and cost improved compressor. The increase of stage pressure ratio and improved efficiency, whilst stage and blade count is reduced, has been achieved by advanced 3D methods. Compressor stability also at off-design conditions will be retained. The mechanical design focusses on a cost and weight optimised rotor not only for a conventional bladed discs but also for Blish stages. Various options for split casings have been developed and assessed. Alternative vortex reducers based on different design options have been carried out. The results from this project will be directly exploited in a follow-on project for a new nine-stage compressor. The new high pressure compressor will be a key element of the future two-shaft-engine architecture. (orig.) [German] Der vorliegende Bericht schliesst das vom Land Brandenburg im Rahmen der Leitlinie Luftfahrtforschung gefoerderte Vorhaben 'Hochdruckverdichter - Vorauslegung als Grundlagenuntersuchung zur Entwicklung eines Kerntriebwerkes fuer einen effizienten und umweltfreundlichen Antrieb' ab. Ziel dieses Vorhabens ist es, im Rahmen einer aerodynamischen Vorauslegung sowie Designstudien die notwendigen Technologien zu erarbeiten, um einen hinsichtlich Effizienz, Kosten, Gewicht und Wartungsintervallen verbesserten Hochdruckverdichter auszulegen. Die Erhoehung des Druckverhaeltnisses und des Wirkungsgrads bei verringerter Stufen- und Schaufelzahl sowie ein stabiles Betriebsverhalten auch ausserhalb des Auslegungspunktes wurde dabei durch eine aeusserst fortschrittliche 3D Schaufelauslegung erreicht. Auf der

  9. Development of scientific and technological basis for the fabrication of thin film solar cells on the basis of a-Si:H and {mu}c-Si:H using the 'hot-wire' deposition technique. Final report; Entwicklung wissenschaftlicher und technischer Grundlagen fuer die Herstellung von Duennschichtsolarzellen auf der Basis des a-Si:H und {mu}c-Si:H mit der 'Hot-Wire'-Depositionstechnik. Abschlussbericht

    Energy Technology Data Exchange (ETDEWEB)

    Schroeder, B.

    2002-01-22

    - and p-type emitters have been fabricated. After a very short development time conversion efficiencies have been obtained ({eta}{sub max} = 15.2%) which are reported for PECVD emitters. (orig.) [German] Zwei neue Anlagen zur vollstaendigen bzw. grossflaechigen Abscheidung von a-Si:H basierenden Solarzellen mit der sog. 'Hot-Wire (HW)' CVD wurden aufgebaut. Die Abscheidebedingungen fuer geeignete n- und p-dotierte a-Si:H- bzw. {mu}c-Si:H-Schichten wurden ermittelt. Weltweit wurde erstmals eine a-Si:H-pin-Zelle vollstaendig mit der HWCVD-Methode hergestellt, ein Anfangswirkungsgrad von {eta}{sub initial} = 8,9% wurde erreicht. Nach Entwicklung eines p/n-Tunnel- bzw. Rekombinationsueberganges ist es weltweit ebenfalls erstmals gelungen, pin-pin-Tandemstrukturen mit a-Si:H-Absorbern vollstaendig mit der HWCVD-Methode abzuscheiden. Nach Teilalterung wurden noch Wirkungsgrade von {eta}{approx}7% ermittelt. Generell ist die Stabilitaet der all-HWCVD-Zellen noch unbedriedigend, was auf strukturell instabile p-Schichten zurueckgefuehrt werden konnte. Erste nip-Solarzellen auf Edelstahlsubstraten wurden ebenfalls vollstaendig mit der HWCVD praepariert ({eta}{sub initial}>6%). Der Einbau von {mu}c-Si:H-Absorberschichten die mit HWCVD bzw. ECWR-PECVD hergestellt wurden, in pin-Solarzellen war bisher wenig erfolgreich. In einer Anlage zur grossflaechigen HWCVD-Abscheidung wurden a-Si:H-Schichten mit guter Qualitaet und einer Schichtdickenuniformitaet von {delta}d = {+-}2,5% hergestellt. Fuer sog. 'Huepfzellen', nur die i-Schicht wurde in der Anlage abgeschieden, wurden auch sehr uniforme Anfangswirkungsgrade {eta}{sub initial}=6,1{+-}0,2% fuer kleinflaechige Zellen auf einer Flaeche von 20 x 20 cm{sup 2} erreicht. Diese Ergebnisse koennen als 'proof of concept' fuer die grossflaechige HWCVD-Abscheidung fuer a-Si:H-basierende Solarzellen betrachtet werden. Erstmals wurde die HWCVD zur Abscheidung von Emitter-Schichten fuer Hetero-Solarzellen auf c-Si-Wafer-Basis

  10. FPGA Vision Data Architecture

    Science.gov (United States)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  11. From OO to FPGA :

    Energy Technology Data Exchange (ETDEWEB)

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  12. FPGA programming using FX3

    CERN Document Server

    Calleja, Stefano

    2014-01-01

    An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

  13. FPGA communications based on Gigabit Ethernet

    International Nuclear Information System (INIS)

    Doolittle, L.R.; Serrano, C.

    2012-01-01

    The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

  14. The FPGA Pixel Array Detector

    International Nuclear Information System (INIS)

    Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

    2013-01-01

    A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

  15. FPGA-Based Sonar Processing

    National Research Council Canada - National Science Library

    Graham, Paul; Nelson, Brent

    1998-01-01

    This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays...

  16. FPGA Boot Loader and Scrubber

    Science.gov (United States)

    Wade, Randall S.; Jones, Bailey

    2009-01-01

    A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

  17. Exploration of Heterogeneous FPGA Architectures

    Directory of Open Access Journals (Sweden)

    Umer Farooq

    2011-01-01

    mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

  18. FPGA-RR: A Novel FPGA Architecture with RRAM-Based Reconfigurable Interconnects

    OpenAIRE

    Xiao, Bingjun

    2012-01-01

    In this paper we introduce a novel FPGA architecture with RRAM-based reconfiguration (FPGA-RR). This architecture focuses on the redesign of programmable interconnects, the dominant part of FPGA. By renovating the routing structure of FPGA using RRAMs, the architecture achieves significant benefits concerning area, performance and energy consumption. The implementation of FPGA-RR can be realized by the existing CMOS-compatible RRAM fabrication process. A customized CAD flow is provided for FP...

  19. Flexible experimental FPGA based platform

    DEFF Research Database (Denmark)

    Andersen, Karsten Holm; Nymand, Morten

    2016-01-01

    interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...... has a synchronized load change mechanism and build-in acquisition memory, which makes it possible to, easily compare and verify different control strategies. Besides the main controller tasks, the logic also contains a digital to analog module, that can be used for eq. outputting a controller...

  20. Entwicklung und Evolution dienstorientierter Anwendungen im Web Engineering

    OpenAIRE

    Nußbaumer, Martin

    2008-01-01

    Die vorliegende Abhandlung untersucht die methodische und systematische Herangehensweise an die Entwicklung dienstorientierter Anwendungen im Web Engineering. Dabei wird deren architekturelle Betrachtung in den Vordergrund gerückt, die auf der Grundlage autonomer, wiederverwendbarer Komponenten in Form von Web Services basiert. Dazu werden dedizierte Modelle, Methoden und Werkzeuge entlang dieser - an Web-Standards orientierten - Architektur entwickelt.

  1. Intelligent FPGA Data Acquisition Framework

    Science.gov (United States)

    Bai, Yunpeng; Gaisbauer, Dominic; Huber, Stefan; Konorov, Igor; Levit, Dmytro; Steffen, Dominik; Paul, Stephan

    2017-06-01

    In this paper, we present the field programmable gate arrays (FPGA)-based framework intelligent FPGA data acquisition (IFDAQ), which is used for the development of DAQ systems for detectors in high-energy physics. The framework supports Xilinx FPGA and provides a collection of IP cores written in very high speed integrated circuit hardware description language, which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of Serializer/Deserializer (SERDES)-based time-to-digital conversion channels, an interface to a multichannel 80-MS/s 10-b analog-digital conversion, data transmission, and synchronization protocol between FPGAs, event builder, and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front end and data concentrator. This modular design also helps to scale and adapt the DAQ system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the drift chambers and the electromagnetic calorimeters (ECALs) of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this paper.

  2. Die Entwicklung von Kindern: eine Einführung

    OpenAIRE

    Siegler, Robert; DeLoache, Judy; Eisenberg, Nancy

    2005-01-01

    Das Kapitel behandelt zunächst die Gründe für die Untersuchung der Kindesentwicklung und ihre historischen Wurzeln. Es werden anschließend Leitfragen der Kindesentwicklung sowie Methoden der Untersuchung kindlicher Entwicklung erläutert. Eine Zusammenfassung stellt schließlich die Kernthesen der einzelnen Abschnitte in einer kompakten Übersicht dar.(DIPF/paul)

  3. Development of new layer systems for sliding bearings under high mechanical and tribological stress. Final report; Entwicklung neuer Schichtsysteme fuer den Einsatz bei mechanisch-tribologisch hochbeanspruchten Gleitlagern. Abschlussbericht

    Energy Technology Data Exchange (ETDEWEB)

    Mathias, M.; Herrmann, B.

    1995-12-31

    The report describes the sputtering technique as a coating method for sliding bearings of high-speed diesel engines. The project aimed at the development of a heavy-duty, wear-resistant sputtered layer on a copper-lead basis for sliding bearings. (HW) [Deutsch] Es wird berichtet ueber die Einfuehrung der Sputtertechnik als Beschichtungsverfahren fuer Gleitlager fuer schnell laufende Dieselmotoren. Ziel des Projektes war die Entwicklung einer hochbelastbaren, verschleissfesten Gleitlager-Sputterschicht auf Kupfer-Blei-Basis. (HW)

  4. Autonomous Lawnmower using FPGA implementation.

    Science.gov (United States)

    Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

    2016-11-01

    Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

  5. Die Entwicklung der Konzeption der Nachhaltigkeitsanalyse

    OpenAIRE

    Janno Reiljan

    2013-01-01

    This article concerns limits and development possibilities of the sustainability analysis concept. Discussed are the qualitative sustainability measurement, and connections to the methodological basis of development assessment and the essence of evaluating sustainability. At first the sustainability definition is tackled, followed by an analysis of the nature of sustainability. The third section highlights the requirements for decision making that guarantees sustainability

  6. Spatial and color clustering on an FPGA-based computer system

    Science.gov (United States)

    Leeser, Miriam E.; Kitaryeva, Natalya V.; Crisman, Jill D.

    1998-10-01

    We are mapping an image clustering algorithm onto an FPGA- based computer system. Our approach processes raw pixel data in the red, green, blue color space and generates an output image where all pixels are assigned to classes. A class is a group of pixels with similar color and location. These classes are then used as the basis of further processing to generate tags. The tags, in turn, are used to generate queries for searching libraries of digital images. We run our image tagging approach on an FPGA-based computing machine. The image clustering algorithm is run on an FPGA board, and only the classified image is communicated to the host PC. Further processing is run on the host. Our experimental system consists of an Annapolis Wildforce board with four Xilinx XC4000 chips and a PCI connection to a host PC. Our implementation allows the raw image data to stay local to the FPGAs, and only the class image is communicated to the host PC. The classified pixels are then used to generate tags which can be used for searching a digital library. This approach allows us to parallelize the image processing on the FPGA board, and to minimize the data handled by the PC. FPGA platforms are ideally suited for this sort of initial processing of images. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures, keeping unnecessary data off the host processor. The result of our algorithm is a reduction by up to a factor of six in the number of bits required to represent each pixel. The output data is passed to the host PC, thus reducing the processing and memory resources needed compared to handling the raw data on the PC. The process of generating tags of images is simplified by first classifying pixels on an FPGA-based system, and digital library search is accelerated.

  7. Nutzergerechte Entwicklung der Mensch-Maschine-Interaktion von Fahrerassistenzsystemen

    Science.gov (United States)

    König, Winfried

    Durch langjährige Forschungen bei Kfz-Herstellern, Zulieferfirmen und an Hochschulen sind umfangreiche, aber dennoch lückenhafte Erkenntnisse über das Zusammenspiel zwischen FAS und Nutzer gewonnen worden. In deutschen und internationalen Projekten wie z. B. PROMETHEUS, DRIVE, MOTIV, INVENT, RESPONSE und AKTIV haben sich Kfz-Hersteller, Zulieferfirmen, Hochschulen und weitere staatliche und private Forschungseinrichtungen zusammengefunden, um die vorwettbewerbliche Forschung für derartige Systeme voranzutreiben. Im folgenden Kapitel sollen einige der gewonnenen Kenntnisse dargelegt werden, um die Entwicklung des HMI von FAS zu erleichtern.

  8. Wissensbasierte Entwicklung in Singapur und Malaysia

    OpenAIRE

    Menkhoff, Thomas; Gerke, Solvay; Evers, Hans-Dieter; Chay, Yue Wah

    2009-01-01

    This paper addresses the question how knowledge is used to benefit the economic development of Singapore and Malaysia. Both countries have followed strict science policies to establish knowledge governance regimes for a knowledge-based economy. On the basis of empirical studies in both countries we show, how ethnic and religious diversity impact on the ability to develop an epistemic culture of knowledge sharing and ultimately an innovative knowledge-based economy.

  9. Multichannel analyzer embedded in FPGA

    International Nuclear Information System (INIS)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Bravo M, I.

    2017-10-01

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  10. Welding data adquisition based on FPGA

    OpenAIRE

    Millán Vázquez de la Torre, Rafael Luis; Quero Reboul, José Manuel; García Franquelo, Leopoldo

    1997-01-01

    This paper presents the use of FPGA in data acquisition and digital preprocessing of the electric current signal of resistance welding stations. This work demonstrates that electric current has enough information to classify this kind of welds in mass production industries. Parameters extracted with the FPGA excite a classifier that accept o reject the welding junction. This system has been developed using a neural classifier and installed in a welding station of General Motors in Cádiz (Spai...

  11. Protection and Control with FPGA technology

    International Nuclear Information System (INIS)

    Sohn, K. Y.; Yi, W. J.; Koo, I. S.

    2012-01-01

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper

  12. Protection and Control with FPGA technology

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-03-15

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

  13. Tethered Forth system for FPGA applications

    Science.gov (United States)

    Goździkowski, Paweł; Zabołotny, Wojciech M.

    2013-10-01

    This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

  14. Entwicklung einer Testumgebung für das WebDAV-Modul Catacomb

    OpenAIRE

    Steger, Rudolf

    2009-01-01

    Das DLR entwickelt im eigenen Hause das Produkt DataFinder. Der Datafinder ist eine Software zur Verwaltung technisch-wissenschaftlicher Daten. Ein wesentlicher Bestandteil des Backends dieser Software ist das Opensource Apache WebDAV Modul Catacomb. Das DLR ist maßgeblich an der Entwicklung von Catacomb beteiligt. Diese Diplomarbeit soll helfen die Qualität dieses Produkts zu sichern. Das DLR ist maßgeblich an der Entwicklung von Catacomb beteiligt. Diese Diplomarbeit so...

  15. Renewable energies in Germany. Data on the development in 2016; Erneuerbare Energien in Deutschland. Daten zur Entwicklung im Jahr 2016

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2017-03-15

    The Working Group on Renewable Energy Statistics (AGEE-Stat), which regularly evaluates the use of renewable energies on behalf of the German Federal Ministry of Economics and Energy, has made an initial assessment of the development of renewable energies in Germany on the basis of available, mostly provisional data of 2016. The present background paper describes the previous findings for the areas of electricity, heat and transport, supplemented by figures on economic significance as well as on emission reductions through renewable energies. [German] Die Arbeitsgruppe Erneuerbare Energien-Statistik (AGEE-Stat), die im Auftrag des Bundesministeriums fuer Wirtschaft und Energie regelmaessig die Nutzung der erneuerbaren Energien bilanziert, hat auf der Grundlage verfuegbarer, zumeist vorlaeufiger Daten eine erste Abschaetzung zur Entwicklung der erneuerbaren Energien in Deutschland im Jahr 2016 erstellt. Das vorliegende Hintergrundpapier beschreibt die bisherigen Erkenntnisse fuer die Bereiche Strom, Waerme und Verkehr, ergaenzt um Zahlen zur wirtschaftlichen Bedeutung sowie zur Emissionsvermeidung durch erneuerbare Energien.

  16. Der Weg zum Java-Profi Konzepte und Techniken für die professionelle Java-Entwicklung

    CERN Document Server

    Inden, Michael

    2015-01-01

    Sie haben bereits Einiges an Erfahrung mit Java und möchten Ihre Entwicklungstätigkeit nun professionalisieren? Oder sind Sie schon auf dem Weg zum Profi, benötigen aber ein Nachschlagewerk, das Ihnen die wichtigen Themen aus der Java-Welt kompakt und kompetent vermittelt? Dieses Buch bietet eine umfassende Einführung in die professionelle Entwicklung und vermittelt Ihnen das notwendige Wissen, um stabile und erweiterbare Softwaresysteme auf Java-SE-Basis zu bauen. Praxisnahe Beispiele helfen dabei, das Gelernte rasch umzusetzen. Neben der Praxis wird viel Wert auf das Verständnis zugrunde liegender Konzepte gelegt. Dabei kommen dem Autor Michael Inden seine umfangreichen Schulungs- und Entwicklererfahrungen zugute - und Ihnen als Leser damit ebenso. Diese Neuauflage wurde durchgehend überarbeitet, aktualisiert und erweitert. Natürlich darf das aktuelle Java 8 nicht fehlen. Verschiedene Kapitel sind Java 8 und seinen Neuerungen gewidmet. Dort wird ein fundierter Einstieg in die umfangreichen Erweit...

  17. Cyber-Physical Systems - Wissenschaftliche Herausforderungen Bei Der Entwicklung

    Science.gov (United States)

    Broy, Manfred

    Cyber-Physical Systems adressieren die enge Verbindung eingebetteter Systeme zur Überwachung und Steuerung physikalischer Vorgänge mittels Sensoren und Aktuatoren über Kommunikationseinrichtungen mit den globalen digitalen Netzen (dem Cyberspace"). Dieser Typus von Systemen ermöglicht über Wirkketten eine Verbindung zwischen Vorgängen der physischen Realität und den heute verfügbaren digitalen Netzinfrastrukturen. Dies erlaubt vielfältige Applikationen mit hohem wirtschaftlichen Potential, und mit starker Innovationskraft. Die vollständige Ausschöpfung des Potentials erfordert aber gezielte wissenschaftliche Anstrengungen bei der Entwicklung solcher Systeme im Hinblick auf Methodik, Technologie, Kostenbeherrschung und funktionale Angemessenheit.

  18. Evaluation of existing assessment approaches and development of a concept for the integrated assessment of the effects of priority pollutants across all pathways on the basis of their bioavailability; Evaluierung vorhandener Bewertungsansaetze und Entwicklung eines Konzeptes zur integrierten Wirkungsbewertung prioritaerer Schadstoffe ueber alle Pfade auf der Grundlage der Bioverfuegbarkeit

    Energy Technology Data Exchange (ETDEWEB)

    Macholz, Rainer M.; Kaiser, David B. [Prof. Dr. Macholz Umweltprojekte GmbH, Stahnsdorf (Germany); Koerdel, Werner; Hund-Rinke, Kerstin; Derz, Kerstin; Bernhardt, Cornelia [Fraunhofer-Institut fuer Molekularbiologie und Angewandte Oekologie (IME), Schmallenberg (Germany)

    2011-09-15

    (A) The problem: There is an urgent need to further develop investigation and assessment systems for the assessment of pollutant concentrations in soil and their potential effects on relevant protected assets on the basis of bioavailability. A concept for integrated effect analysis has to be developed which considers the distribution behaviour of a contaminant on the basis of its physicochemical properties and focuses especially on that fraction that may actually exert an effect. The inclusion of bioavailability is in keeping with the regulatory framework set by the Federal Soil Protection Act (BBodSchG) and the Federal Soil Protection and Contaminated Sites Ordinance (BBodSchV). Implementation requires the development of a concept and of guidance facilitating its application in enforcement practice. (B) Need for action: Case-by-case investigations achieve their objective only partially with the methods referred to in Article 9 BBodSchG and Annex 1 BBodSchV. In particular, no suitable methods have been identified so far which consider the bioavailability of soil contaminants via all pathways. In addition, guidance on how to integrate the bioavailability of soil contaminants needs to be developed which can be used, especially by enforcement authorities, to determine the actual hazards which harmful soil changes presents to individuals and the general public. This should include a review of different combinations of approached applied in relevant legislation. (C) The purpose of the project is to compile and evaluate existing concepts for the evaluation of soil quality taking different forms of use into account. Based on this evaluation, a concept for the integration of bioavailability into soil assessment as well as a guidance document are to be developed, taking all pathways into account. The results shall be presented and discussed at an international workshop. (orig.)

  19. FPGA based Smart Wireless MIMO Control System

    International Nuclear Information System (INIS)

    Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-01-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

  20. FPGA based Smart Wireless MIMO Control System

    Science.gov (United States)

    Usman Ali, Syed M.; Hussain, Sajid; Akber Siddiqui, Ali; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-12-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input & Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively.

  1. FPGA controlled artificial vascular system

    Directory of Open Access Journals (Sweden)

    Laqua D.

    2015-09-01

    Full Text Available Monitoring the oxygen saturation of an unborn child is an invasive procedure, so far. Transabdominal fetal pulse oximetry is a promising method under research, used to estimate the oxygen saturation of a fetus noninvasively. Due to the nature of the method, the fetal information needs to be extracted from a mixed signal. To properly evaluate signal processing algorithms, a phantom modeling fetal and maternal blood circuits and tissue layers is necessary. This paper presents an improved hardware concept for an artificial vascular system, utilizing an FPGA based CompactRIO System from National Instruments. The experimental model to simulate the maternal and fetal blood pressure curve consists of two identical hydraulic circuits. Each of these circuits consists of a pre-pressure system and an artificial vascular system. Pulse curves are generated by proportional valves, separating these two systems. The dilation of the fetal and maternal artificial vessels in tissue substitutes is measured by transmissive and reflective photoplethysmography. The measurement results from the pressure sensors and the transmissive optical sensors are visualized to show the functionality of the pulse generating systems. The trigger frequency for the maternal valve was set to 1 per second, the fetal valve was actuated at 0.7 per second for validation. The reflective curve, capturing pulsations of the fetal and maternal circuit, was obtained with a high power LED (905 nm as light source. The results show that the system generates pulse curves, similar to its physiological equivalent. Further, the acquired reflective optical signal is modulated by the alternating diameter of the tubes of both circuits, allowing for tests of signal processing algorithms.

  2. FPGA Implementation of the stepwise shutdown system

    International Nuclear Information System (INIS)

    Lotjonen, L.

    2012-01-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and standards can be used to some extent but the hardware aspects bring new challenges that cannot be tackled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation process from the requirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  3. FPGA Implementation of the stepwise shutdown system

    Energy Technology Data Exchange (ETDEWEB)

    Lotjonen, L.

    2012-07-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  4. FPGA Based Acceleration of Decimal Operations

    DEFF Research Database (Denmark)

    Nannarelli, Alberto

    2011-01-01

    Field Programmable Gate-Arrays (FPGAs) can efficiently implement application specific processors in nonconventional number systems, such as the decimal (Binary- Coded Decimal, or BCD) number system required for accounting accuracy in financial applications. The main purpose of this work is to show...... that applications requiring several decimal (BCD) operations can be accelerated by a processor implemented on a FPGA board connected to the computer by a standard bus. For the case of a telephone billing application, we demonstrate that even a basic implementation of the decimal processor on the FPGA, without...

  5. Burst-Mode Asynchronous Controllers on FPGA

    Directory of Open Access Journals (Sweden)

    Duarte L. Oliveira

    2008-01-01

    Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

  6. FPGA Implementation of Metastability-Based True Random Number Generator

    Science.gov (United States)

    Hata, Hisashi; Ichikawa, Shuichi

    True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in free-running ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5Mbps throughput.

  7. OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

  8. Qualification of FPGA-Based Safety-Related PRM System

    International Nuclear Information System (INIS)

    Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

    2011-01-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

  9. Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

    Science.gov (United States)

    Xia, Fei; Jin, Guoqing

    2014-06-01

    PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

  10. Commercial FPGA based multipurpose controller: implementation perspective

    International Nuclear Information System (INIS)

    Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

    2012-01-01

    This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

  11. Sustainable development caught in the globalisation trap?; Nachhaltige Entwicklung in der Globalisierungsfalle?

    Energy Technology Data Exchange (ETDEWEB)

    Mueller-Kraenner, S. [Deutscher Naturschutzring (DNR), Berlin (Germany)

    2001-07-01

    In the light of the current major paradigms and issues of economies and societies worldwide, which are globalisation and competitiveness in national and international markets, the author raises the question of whether the concept of sustainable development has any chance at all to gain a foothold in this political environment. (orig./CB) [German] Nicht das Leitbild der nachhaltigen Entwicklung praegt die weltweite Tagesordnung, sondern auf internationaler Ebene die Auseinandersetzung um Globalisierung, auf nationaler Ebene die Debatte um Standort- und Wettbewerbsvorteile. Fuenf Jahre nach Rio lautet die Frage: Ist nachhaltige Entwicklung unter den Bedingungen der Globalisierung moeglich? (orig.)

  12. Guide to FPGA Implementation of Arithmetic Functions

    CERN Document Server

    Deschamps, Jean-Pierre; Cantó, Enrique

    2012-01-01

    This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components.  The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption.  This is not a book on algorithms.  It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others.  Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

  13. An FPGA-Based Electronic Cochlea

    Directory of Open Access Journals (Sweden)

    M. P. Leong

    2003-06-01

    Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

  14. An Improved Rotary Interpolation Based on FPGA

    Directory of Open Access Journals (Sweden)

    Mingyu Gao

    2014-08-01

    Full Text Available This paper presents an improved rotary interpolation algorithm, which consists of a standard curve interpolation module and a rotary process module. Compared to the conventional rotary interpolation algorithms, the proposed rotary interpolation algorithm is simpler and more efficient. The proposed algorithm was realized on a FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe, which uses rotary ellipse and rotary parabolic as an example. According to the theoretical analysis and practical process validation, the algorithm has the following advantages: firstly, less arithmetic items is conducive for interpolation operation; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

  15. FPGA Flash Memory High Speed Data Acquisition

    Science.gov (United States)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  16. Adaptive Hardware Cryptography Engine Based on FPGA

    International Nuclear Information System (INIS)

    Afify, M.A.A.

    2011-01-01

    In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

  17. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  18. FPGA-Based Pulse Pileup Correction.

    Science.gov (United States)

    Haselman, M D; Hauck, S; Lewellen, T K; Miyaoka, R S

    2010-01-01

    Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper we report on an all-digital pulse pileup correction algorithm that is being developed for the FPGA. The pileup mitigation algorithm will allow the scanner to run at higher count rates without incurring large data losses due to the overlapping of scintillation signals. This correction technique utilizes a reference pulse to extract timing and energy information for most pileup events. Using pulses were acquired from a Zecotech Photonics MAPDN with an LFS-3 scintillator, we show that good timing and energy information can be achieved in the presence of pileup.

  19. FPGA Implementation of Heart Rate Monitoring System.

    Science.gov (United States)

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  20. Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

    Directory of Open Access Journals (Sweden)

    P. Fiala

    2015-09-01

    Full Text Available This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed.

  1. Automatic generation of application specific FPGA multicore accelerators

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

    2014-01-01

    High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

  2. FPGA based Control of a Production Cell System

    NARCIS (Netherlands)

    Groothuis, M.A.; van Zuijlen, Jasper J.P.; Broenink, Johannes F.

    Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control

  3. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA...

  4. STRS SpaceWire FPGA Module

    Science.gov (United States)

    Lux, James P.; Taylor, Gregory H.; Lang, Minh; Stern, Ryan A.

    2011-01-01

    An FPGA module leverages the previous work from Goddard Space Flight Center (GSFC) relating to NASA s Space Telecommunications Radio System (STRS) project. The STRS SpaceWire FPGA Module is written in the Verilog Register Transfer Level (RTL) language, and it encapsulates an unmodified GSFC core (which is written in VHDL). The module has the necessary inputs/outputs (I/Os) and parameters to integrate seamlessly with the SPARC I/O FPGA Interface module (also developed for the STRS operating environment, OE). Software running on the SPARC processor can access the configuration and status registers within the SpaceWire module. This allows software to control and monitor the SpaceWire functions, but it is also used to give software direct access to what is transmitted and received through the link. SpaceWire data characters can be sent/received through the software interface, as well as through the dedicated interface on the GSFC core. Similarly, SpaceWire time codes can be sent/received through the software interface or through a dedicated interface on the core. This innovation is designed for plug-and-play integration in the STRS OE. The SpaceWire module simplifies the interfaces to the GSFC core, and synchronizes all I/O to a single clock. An interrupt output (with optional masking) identifies time-sensitive events within the module. Test modes were added to allow internal loopback of the SpaceWire link and internal loopback of the client-side data interface.

  5. FPGA Realization of Memory 10 Viterbi Decoder

    DEFF Research Database (Denmark)

    Paaske, Erik; Bach, Thomas Bo; Andersen, Jakob Dahl

    1997-01-01

    A feasibility study for a low cost, iterative, serially concatenated coding system is performed. The system uses outer (255,223) Reed-Solomon codes and convolutional inner codes with memory 10 and rates 1/4 or 1/6. The corresponding inner decoder is a Viterbi decoder, which can operate in a forced...... sequence mode when feedback from the Reed-Solomon decoder is available. The Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's. The overall operating speed is 30 kbit/s, and since up to three iterations are performed for each frame and only one decoder is used, the operating speed...

  6. Hyperchaotic Chameleon: Fractional Order FPGA Implementation

    Directory of Open Access Journals (Sweden)

    Karthikeyan Rajagopal

    2017-01-01

    Full Text Available There are many recent investigations on chaotic hidden attractors although hyperchaotic hidden attractor systems and their relationships have been less investigated. In this paper, we introduce a hyperchaotic system which can change between hidden attractor and self-excited attractor depending on the values of parameters. Dynamic properties of these systems are investigated. Fractional order models of these systems are derived and their bifurcation with fractional orders is discussed. Field programmable gate array (FPGA implementations of the systems with their power and resource utilization are presented.

  7. Evaluation of FPGA to PC feedback loop

    Science.gov (United States)

    Linczuk, Pawel; Zabolotny, Wojciech M.; Wojenski, Andrzej; Krawczyk, Rafal D.; Pozniak, Krzysztof T.; Chernyshova, Maryna; Czarski, Tomasz; Gaska, Michal; Kasprowicz, Grzegorz; Kowalska-Strzeciwilk, Ewa; Malinowski, Karol

    2017-08-01

    The paper presents the evaluation study of the performance of the data transmission subsystem which can be used in High Energy Physics (HEP) and other High-Performance Computing (HPC) systems. The test environment consisted of Xilinx Artix-7 FPGA and server-grade PC connected via the PCIe 4xGen2 bus. The DMA engine was based on the Xilinx DMA for PCI Express Subsystem1 controlled by the modified Xilinx XDMA kernel driver.2 The research is focused on the influence of the system configuration on achievable throughput and latency of data transfer.

  8. Control de acceso usando FPGA y RFID

    Directory of Open Access Journals (Sweden)

    Dora Luz Almanza Ojeda

    2012-10-01

    Full Text Available Este trabajo presenta el diseño e implementación de un sistema de control de acceso mediante Identificación por Radiofrecuencia (RFID, Radio Frequency Identification controlado por una Matriz de compuertas programables (FPGA, Field Programmable Gate Array. El sistema está constituido por un par de dispositivos de adquisición de radiofrecuencia, una FPGA, un juego de etiquetas y tarjetas pasivas de identificación. Mediante una interfaz gráfica de usuario es posible controlar todo movimiento dentro de una zona determinada, desde los accesos hasta la disponibilidad de equipo; utilizando los dispositivos de adquisición de radiofrecuencia se puede acceder a la información de los usuarios autorizados, así como al control del equipo. Con este sistema es posible monitorear, administrar y reportar todo acceso de personal, movimiento de equipo o plagio de manera eficiente y evitando un gran número de errores humanos.  

  9. An FPGA-Based People Detection System

    Directory of Open Access Journals (Sweden)

    James J. Clark

    2005-05-01

    Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

  10. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  11. Automated Metabolic P System Placement in FPGA

    Directory of Open Access Journals (Sweden)

    Kulakovskis Darius

    2016-07-01

    Full Text Available An original Very High Speed Integrated Circuit Hardware Description Language (VHDL code generation tool that can be used to automate Metabolic P (MP system implementation in hardware such as Field Programmable Gate Arrays (FPGA is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT, and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP, slice, and 4-input LUT usage.

  12. Superconducting cavity driving with FPGA controller

    Energy Technology Data Exchange (ETDEWEB)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland); Simrock, S.; Brand, A. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Chase, B.; Carcagno, R.; Cancelo, G. [Fermi National Accelerator Lab., Batavia, IL (United States); Koeth, T.W. [Rutgers - the State Univ. of New Jersey, NJ (United States)

    2006-07-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

  13. Fpga As A Part Of Ms Windows Control Environment

    Directory of Open Access Journals (Sweden)

    Krzysztof Kołek

    2007-01-01

    Full Text Available The attention is focused on the Windows operating system (OS used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS.Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

  14. Long-distance configuration of FPGA based on serial communication

    International Nuclear Information System (INIS)

    Liu Xiang; Song Kezhu; Zhang Sifeng

    2010-01-01

    To solve FPGA configuration in some nuclear electronics, which works in radioactivity environment, the article introduces a way of long-distance configuration with PC and CPLD, based on serial communication. Taking CYCLONE series FPGA and EPCS configuration chip from ALTERA for example, and using the AS configuration mode, we described our design from the aspects of basic theory, hardware connection, software function and communication protocol. With this design, we could configure several FPGAs in the distance of 100 meters, or we could configure on FPGA in the distance of 150 meters. (authors)

  15. Design of image processing operation machine by FPGA

    OpenAIRE

    山部, 選; 堀田, 厚生

    2007-01-01

    An image processing system with a FPGA has been developed. the system has the following functions.1) BMP images taken with a digital camera and stored in a PC are transferred to a SDRAM on a board including a FPGA through a PCI bus.2) Two images are read from the SDRAM and are processed by background subtraction method in the FPGA, and the resulted image is stored into the SDRAM.3) The result image are transferred to the PC via a PCI bus, and displayed. Processing time of background subtracti...

  16. Entwicklung und Evaluation computerbasierter Trainingsaufgaben für das wissenschaftliche Schreiben

    OpenAIRE

    Proske, Antje

    2006-01-01

    Wissenschaftliches Schreiben ist eine sehr komplexe Aufgabe, die eine Vielzahl unterschiedlicher Aktivitäten umfasst. Viele Studierende haben jedoch Schwierigkeiten, die damit verbundenen Anforderungen selbständig zu bewältigen. Im Mittelpunkt des Interesses der vorliegenden Arbeit stand daher die Entwicklung und Evaluation interaktiver computerbasierter Trainingsaufgaben, die Studienanfänger beim Erwerb von Grundkompetenzen des wissenschaftlichen Schreibens unterstützen. Zentrale Anliegen di...

  17. Entwicklung von flexiblen Zelllinien für die Produktion rekombinanter Proteine und Retroviren

    OpenAIRE

    Schucht, Roland

    2006-01-01

    Die vorhersagbare und stabile Expression rekombinanter Proteine in Säugerzellen ist von großem Interesse für viele Anwendungen in der Biotechnologie. Konventionelle Methoden zur Etablierung von Klonen mit guten Produktionseigenschaften sind mit hohem Screeningaufwand verbunden. Das Ziel dieser Arbeit war die Entwicklung einer Austauschstrategie, welche die Etablierung von Masterzelllinien mit einer austauschbaren Expressionskassette beinhaltet. Dazu wurden chromosomale Loci in HEK293, CHO-K1 ...

  18. Knowledgebase Erwachsenenbildung: aktuelle Entwicklung und Geschichte der österreichischen Erwachsenenbildung. Erfahrbar, erforschbar und anwendbar

    OpenAIRE

    Vater, Stefan

    2007-01-01

    Die Knowledgebase Erwachsenenbildung ist eine umfassende Online-Plattform der österreichischen Erwachsenenbildung, die vom Verband Österreichischer Volkshochschulen und dem Österreichischen Volkshochschularchiv erstellt wurde. Das Projekt wurde vom Bundesministerium für Bildung, Wissenschaft und Kunst und dem Europäischen Sozialfond gefördert. In 42 verschiedenen Datenbanken wird eine breite Palette an Fachliteratur, Informationen zur Geschichte und Entwicklung der Erwachsenenbildung, Statist...

  19. Wire Position Monitoring with FPGA based Electronics

    International Nuclear Information System (INIS)

    Eddy, N.; Lysenko, O.

    2009-01-01

    This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. An FPGA based digitizer

  20. FPGA fabric specific optimization for RLT design

    International Nuclear Information System (INIS)

    Perwaiz, A.; Khan, S.A.

    2010-01-01

    This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced re configurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned Index Terms: Field Programmable Gate Arrays (FPGA), Compression Tree, Bit Width Reduction, Look Ahead Pipelining. (author)

  1. FPGA for Power Control of MSL Avionics

    Science.gov (United States)

    Wang, Duo; Burke, Gary R.

    2011-01-01

    A PLGT FPGA (Field Programmable Gate Array) is included in the LCC (Load Control Card), GID (Guidance Interface & Drivers), TMC (Telemetry Multiplexer Card), and PFC (Pyro Firing Card) boards of the Mars Science Laboratory (MSL) spacecraft. (PLGT stands for PFC, LCC, GID, and TMC.) It provides the interface between the backside bus and the power drivers on these boards. The LCC drives power switches to switch power loads, and also relays. The GID drives the thrusters and latch valves, as well as having the star-tracker and Sun-sensor interface. The PFC drives pyros, and the TMC receives digital and analog telemetry. The FPGA is implemented both in Xilinx (Spartan 3- 400) and in Actel (RTSX72SU, ASX72S). The Xilinx Spartan 3 part is used for the breadboard, the Actel ASX part is used for the EM (Engineer Module), and the pin-compatible, radiation-hardened RTSX part is used for final EM and flight. The MSL spacecraft uses a FC (Flight Computer) to control power loads, relays, thrusters, latch valves, Sun-sensor, and star-tracker, and to read telemetry such as temperature. Commands are sent over a 1553 bus to the MREU (Multi-Mission System Architecture Platform Remote Engineering Unit). The MREU resends over a remote serial command bus c-bus to the LCC, GID TMC, and PFC. The MREU also sends out telemetry addresses via a remote serial telemetry address bus to the LCC, GID, TMC, and PFC, and the status is returned over the remote serial telemetry data bus.

  2. High-Performance Linear Algebra Processor using FPGA

    National Research Council Canada - National Science Library

    Johnson, J

    2004-01-01

    With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

  3. Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

    National Research Council Canada - National Science Library

    Bardouleau, Graham; Kulp, James

    2005-01-01

    In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment...

  4. Application-specific mesh-based heterogeneous FPGA architectures

    CERN Document Server

    Parvez, Husain

    2011-01-01

    This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

  5. Architecture Analysis of an FPGA-Based Hopfield Neural Network

    Directory of Open Access Journals (Sweden)

    Miguel Angelo de Abreu de Sousa

    2014-01-01

    Full Text Available Interconnections between electronic circuits and neural computation have been a strongly researched topic in the machine learning field in order to approach several practical requirements, including decreasing training and operation times in high performance applications and reducing cost, size, and energy consumption for autonomous or embedded developments. Field programmable gate array (FPGA hardware shows some inherent features typically associated with neural networks, such as, parallel processing, modular executions, and dynamic adaptation, and works on different types of FPGA-based neural networks were presented in recent years. This paper aims to address different aspects of architectural characteristics analysis on a Hopfield Neural Network implemented in FPGA, such as maximum operating frequency and chip-area occupancy according to the network capacity. Also, the FPGA implementation methodology, which does not employ multipliers in the architecture developed for the Hopfield neural model, is presented, in detail.

  6. FPGA Implementation of Uniform Random Number based on Residue Method

    Directory of Open Access Journals (Sweden)

    Zulfikar .

    2014-04-01

    Full Text Available This paper presents the implementation and comparisons of uniform random number on Field Programable Gate Array (FPGA. Uniform random numbers are generated based on residue method. The circuit of generating uniform random number is presented in general view. The circuit is constructed from a multiplexer, a multiplier, buffers and some basic gates. FPGA implementation of the designed circuit has been done into various Xilinx chips. Simulation results are viewed clearly in the paper. Random numbers are generated based on different parameters. Comparisons upon occupied area and maximum frequency from different Xilinx chip are examined. Virtex 7 is the fastest chip and Virtex 4 is the best choice in terms of occupied area. Finally, Uniform random numbers have been generated successfully on FPGA using residue method.Keywords: FPGA implementation, random number, uniform random number, residue method, Xilinx chips

  7. Technologies for faults diagnosis of FPGA logic blocks

    Directory of Open Access Journals (Sweden)

    C. U. Ngene

    2012-08-01

    Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

  8. A software radio platform based on ARM and FPGA

    Directory of Open Access Journals (Sweden)

    Yang Xin.

    2016-01-01

    Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

  9. High speed numerical integration algorithm using FPGA | Razak ...

    African Journals Online (AJOL)

    RRS), Middle Riemann Sum (MRS) and Trapezoidal Sum (TS) algorithms. The system performance is evaluated based on target chip Altera Cyclone IV FPGA in the metrics of resources utilization, clock latency, execution time, power consumption ...

  10. Implementation of Digital Video Broadcasting Codec Using FPGA

    Directory of Open Access Journals (Sweden)

    Sameer Jasim Mohammad

    2017-03-01

    Full Text Available This paper is concerned with transmitting signals of Digital Video Broadcasting (DVB properties using Field Programmable Gate Array (FPGA using Verilog code to achieve this goal. DVB is a technique used an outer code (Reed-Solomon, inner code (convolutional code and interleaver in between them. the properties of Reed-Solomon is (204, 188, convolutional code is a 1/2 and interleaver of depth I=12. The method used to programming the FPGA is schematic and Verilog code

  11. A Model of FPGA-based Direct Torque Controller

    OpenAIRE

    Auzani Jidin; Aiman Zakwan Jidin; Nik Rumzi Nik Idris; Tole Sutikno

    2013-01-01

    This paper presents a generic model of a fully FPGA-based direct torque controller. This model is developed using two’s-complement fixed-point format approaches, in register-transfer-level (RTL) VHDL abstraction for minimizing calculation errors and consuming hardware resource usage. Therefore, the model is universal and can be implemented for all FPGA types. The model is prepared for fast computation, without using of CORDIC algorithm, a soft-core CPU, a transformation from Cartesian-to-pola...

  12. FPGA Architecture for Multi-Style Asynchronous Logic

    OpenAIRE

    Huot, N.; Dubreuil, H.; Fesquet, L.; Renaudin, M.

    2007-01-01

    Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative aspects of the architecture are described. Moreover the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions thanks to the archi...

  13. Two IP Protection Schemes for Multi-FPGA Systems

    OpenAIRE

    Gaspar, Lubos; Fischer, Viktor; Guneysu, Tim; Cherif, Zouha

    2012-01-01

    International audience; This paper proposes two novel protection schemes for multi-FPGA systems providing high security of IP designs licensed by IP vendors to system integrators and installed remotely in a hostile environment. In the first scheme, these useful properties are achieved by storing two different configuration keys inside an FPGA, while in the second scheme, they are obtained using a hardware white-box cipher for creating a trusted environment. Thanks to the proposed principles, ...

  14. FPGA based control of a walking piezo motor

    OpenAIRE

    Uzunovic, Tarik; Golubovic, Edin; Şabanoviç, Asif; Sabanovic, Asif

    2014-01-01

    This paper describes FPGA based control system for a piezoelectric motor, commercially available Piezo LEGS motor. Driving voltages waveforms are defined as a combination of linear functions. This definition provides possibility for easy implementation on very simple hardware. Linear functions parameters allow forming of the driving voltages according to desired trajectory of motor's legs. Considering that FPGA technology offers many advantages over the classical microprocessor based systems,...

  15. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-05-23

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

  16. Development of FPGA-Based Control Board

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Yoon Hee; Jeong, See Chae; Choi, Woong Seock; Lee, Chang Jae; Jeong, Jin Kwon; Ha, Jae Hong [Korea Power Engineering Company Inc., Daejeon (Korea, Republic of)

    2009-10-15

    It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a FPGAbased control board performing user-defined control functions. An Actel ProASIC{sup plus} FPGA platform is implemented as the comparator of Plant Protection System (PPS). Functional simulation is implemented for the comparator.

  17. Development of FPGA-Based Bistable Unit

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Yoon Hee; Jeong, See Chae; Ha, Jae Hong [Korea Power Engineering Company, Daejeon (Korea, Republic of)

    2010-05-15

    It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a bistable unit which executes protection functions realized in FPGAs. Functional test is performed to verify its function. An Actel ProASIC3 FPGA platform is implemented as the bistable unit for Plant Protection System (PPS).

  18. Fpga-based control of piezoelectric actuators

    Directory of Open Access Journals (Sweden)

    Juhász László

    2011-01-01

    Full Text Available In many industrial applications like semiconductor production and optical inspection systems, the availability of positioning systems capable to follow trajectory paths in the range of several centimetres, featuring at the same time a nanometre-range precision, is demanding. Pure piezoelectric stages and standard positioning systems with motor and spindle are not able to meet such requirements, because of the small operation range and inadequacies like backlash and friction. One concept for overcoming these problems consists of a hybrid positioning system built through the integration of a DC-drive in series with a piezoelectric actuator. The wide range of potential applications enables a considerable market potential for such an actuator, but due to the high variety of possible positioned objects and dynamic requirements, the required control complexity may be significant. In this paper, a real-time capable state-space control concept for the piezoelectric actuators, embedded in such a hybrid micropositioning system, is presented. The implementation of the controller together with a real-time capable hysteresis compensation measure is performed using a low-budget FPGA-board, whereas the superimposed integrated controller is realized with a dSPACE RCP-system. The advantages of the designed control over a traditional proportional-integral control structure are proven through experimental results using a commercially available hybrid micropositioning system. Positioning results by different dynamic requirements featuring positioning velocities from 1 μm/s up to 5 cm/s are given.

  19. FPGA Congestion-Driven Placement Refinement

    Energy Technology Data Exchange (ETDEWEB)

    Vicente de, J.

    2005-07-01

    The routing congestion usually limits the complete proficiency of the FPGA logic resources. A key question can be formulated regarding the benefits of estimating the congestion at placement stage. In the last years, it is gaining acceptance the idea of a detailed placement taking into account congestion. In this paper, we resort to the Thermodynamic Simulated Annealing (TSA) algorithm to perform a congestion-driven placement refinement on the top of the common Bounding-Box pre optimized solution. The adaptive properties of TSA allow the search to preserve the solution quality of the pre optimized solution while improving other fine-grain objectives. Regarding the cost function two approaches have been considered. In the first one Expected Occupation (EO), a detailed probabilistic model to account for channel congestion is evaluated. We show that in spite of the minute detail of EO, the inherent uncertainty of this probabilistic model impedes to relieve congestion beyond the sole application of the Bounding-Box cost function. In the second approach we resort to the fast Rectilinear Steiner Regions algorithm to perform not an estimation but a measurement of the global routing congestion. This second strategy allows us to successfully reduce the requested channel width for a set of benchmark circuits with respect to the widespread Versatile Place and Route (VPR) tool. (Author) 31 refs.

  20. Stego on FPGA: An IWT Approach

    Directory of Open Access Journals (Sweden)

    Balakrishnan Ramalingam

    2014-01-01

    Full Text Available A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8×8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE and the highest peak signal-to-noise ratio (PSNR. The fixated random walk’s verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA.

  1. Greening the NetFPGA Reference Router

    Directory of Open Access Journals (Sweden)

    Feng Guo

    2016-06-01

    Full Text Available Energy efficiency is an important criterion in the design of next generation networks for both economic and environmental concerns. This paper presents an energy-efficient router that is able to dynamically adapt its routing capability in response to real-time traffic load, achieving energy proportional routing. The NetFPGA reference router, which operates at one of two frequencies (125 MHz or 62.5 MHz, requires a board reset to switch frequencies. We have modified the reference router to allow dynamic switching among five operating frequencies. Experiments with real traces indicate that, compared to the reference router, a 10% power reduction can be achieved through dynamic frequency scaling. When the router is further modified to support green traffic engineering and Ethernet port shut-down, power consumption can be reduced by 46% while maintaining the required quality of service. This allows the router to meet the instantaneous performance requirements while minimizing power dissipation. Similar results can be expected when these general power-saving principles are applied in future commercial routers.

  2. Video Watermarking Implementation Based on FPGA

    International Nuclear Information System (INIS)

    EL-ARABY, W.S.M.S.

    2012-01-01

    The sudden increase in watermarking interest is most likely due to the increase in concern over copyright protection of content. With the rapid growth of the Internet and the multimedia systems in distributed environments, digital data owners are now easier to transfer multimedia documents across the Internet. However, current technology does not protect their copyrights properly. This leads to wide interest of multimedia security and multimedia copyright protection and it has become a great concern to the public in recent years. In the early days, encryption and control access techniques were used to protect the ownership of media. Recently, the watermarking techniques are utilized to keep safely the copyrights. In this thesis, a fast and secure invisible video watermark technique has been introduced. The technique based mainly on DCT and Low Frequency using pseudo random number (PN) sequence generator for embedding algorithm. The system has been realized using VHDL and the results have been verified using MATLAB. The implementation of the introduced watermark system done using Xilinx chip (XCV800). The implementation results show that the total area of watermark technique is 45% of total FPGA area with maximum delay equals 16.393ns. The experimental results show that the two techniques have mean square error (MSE) equal to 0.0133 and peak signal to noise ratio (PSNR) equal to 66.8984db. The results have been demonstrated and compared with conventional watermark technique using DCT.

  3. IMPLEMENTATION OF NEURAL - CRYPTOGRAPHIC SYSTEM USING FPGA

    Directory of Open Access Journals (Sweden)

    KARAM M. Z. OTHMAN

    2011-08-01

    Full Text Available Modern cryptography techniques are virtually unbreakable. As the Internet and other forms of electronic communication become more prevalent, electronic security is becoming increasingly important. Cryptography is used to protect e-mail messages, credit card information, and corporate data. The design of the cryptography system is a conventional cryptography that uses one key for encryption and decryption process. The chosen cryptography algorithm is stream cipher algorithm that encrypt one bit at a time. The central problem in the stream-cipher cryptography is the difficulty of generating a long unpredictable sequence of binary signals from short and random key. Pseudo random number generators (PRNG have been widely used to construct this key sequence. The pseudo random number generator was designed using the Artificial Neural Networks (ANN. The Artificial Neural Networks (ANN providing the required nonlinearity properties that increases the randomness statistical properties of the pseudo random generator. The learning algorithm of this neural network is backpropagation learning algorithm. The learning process was done by software program in Matlab (software implementation to get the efficient weights. Then, the learned neural network was implemented using field programmable gate array (FPGA.

  4. Multi-Softcore Architecture on FPGA

    Directory of Open Access Journals (Sweden)

    Mouna Baklouti

    2014-01-01

    Full Text Available To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication.

  5. Incorporating Probability Models of Complex Test Structures to Perform Technology Independent FPGA Single Event Upset Analysis

    Science.gov (United States)

    Berg, M. D.; Kim, H. S.; Friendlich, M. A.; Perez, C. E.; Seidlick, C. M.; LaBel, K. A.

    2011-01-01

    We present SEU test and analysis of the Microsemi ProASIC3 FPGA. SEU Probability models are incorporated for device evaluation. Included is a comparison to the RTAXS FPGA illustrating the effectiveness of the overall testing methodology.

  6. Embedded system in FPGA-based LLRF controller for FLASH

    Science.gov (United States)

    Szewinski, Jaroslaw; Pucyk, Piotr; Jalmuzna, Wojciech; Fafara, Przemyslaw; Pieciukiewicz, Marcin; Romaniuk, Ryszard; Pozniak, Krzysztof T.

    2006-10-01

    FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

  7. FPGA-Based Pulse Parameter Discovery for Positron Emission Tomography.

    Science.gov (United States)

    Haselman, Michael; Hauck, Scott; Lewellen, Thomas K; Miyaoka, Robert S

    2009-10-24

    Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex digital signal processing algorithms with clock rates well above 100MHz. This, combined with FPGA's low expense and ease of use make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a series of high-resolution, small-animal PET scanners that utilize FPGAs as the core of the front-end electronics. For these next generation scanners, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper we report how we utilize the reconfigurable property of an FPGA to self-calibrate itself to determine pulse parameters necessary for some of the pulse processing steps. Specifically, we show how the FPGA can generate a reference pulse based on actual pulse data instead of a model. We also report how other properties of the photodetector pulse (baseline, pulse length, average pulse energy and event triggers) can be determined automatically by the FPGA.

  8. FPGA design and implementation for EIT data acquisition.

    Science.gov (United States)

    Yue, Xicai; McLeod, Chris

    2008-10-01

    OXBACT-5 was designed to meet the challenges involved in working in the intensive care hospital environment focussed particularly on thoracic imaging of patients with respiratory distress and chronic heart failure (CHF). The FPGA-based wireless LAN linked multi-channel EIT data acquisition system (DAS) providing 16 programmable excitation current channels and 64 voltage measurement channels is presented. It contains function modules of a PCI bus interface, direct digital synthesizers, dual-port memory blocks, digital demodulation and all the command and control logic in the FPGA. The whole EIT data acquisition system is fully programmable and reconfigurable from the host PC. The excitation frequency, excitation patterns, the measuring sequence and the gain of each measurement channel can be set from the host PC before each measurement. The demodulation is implemented in the FPGA chip to reduce the data rate between the DAS and the host PC. In addition, measurement process management is achieved in this FPGA chip. Complemented by analogue devices such as ADCs, DACs, analogue buffers and analogue multiplexers, the new FPGA-based EIT DAS system is implemented in a very compact way for bedside use in intensive care units of hospitals. It is intended for applications such as continuous respiration monitoring with data collection at 25 frames per second. Image reconstruction times depend on the choice of 2D or 3D imaging algorithms and the available processing power.

  9. FPGA design and implementation for EIT data acquisition

    International Nuclear Information System (INIS)

    Yue, Xicai; McLeod, Chris

    2008-01-01

    OXBACT-5 was designed to meet the challenges involved in working in the intensive care hospital environment focussed particularly on thoracic imaging of patients with respiratory distress and chronic heart failure (CHF). The FPGA-based wireless LAN linked multi-channel EIT data acquisition system (DAS) providing 16 programmable excitation current channels and 64 voltage measurement channels is presented. It contains function modules of a PCI bus interface, direct digital synthesizers, dual-port memory blocks, digital demodulation and all the command and control logic in the FPGA. The whole EIT data acquisition system is fully programmable and reconfigurable from the host PC. The excitation frequency, excitation patterns, the measuring sequence and the gain of each measurement channel can be set from the host PC before each measurement. The demodulation is implemented in the FPGA chip to reduce the data rate between the DAS and the host PC. In addition, measurement process management is achieved in this FPGA chip. Complemented by analogue devices such as ADCs, DACs, analogue buffers and analogue multiplexers, the new FPGA-based EIT DAS system is implemented in a very compact way for bedside use in intensive care units of hospitals. It is intended for applications such as continuous respiration monitoring with data collection at 25 frames per second. Image reconstruction times depend on the choice of 2D or 3D imaging algorithms and the available processing power

  10. Prospektive Entwicklung des postoperativen Sprachverstehens nach Tympanoplastik bei chronischer Otitis media

    OpenAIRE

    Knof, B; Plotz, K; Krack, A; Stumper, J; Schönfeld, R

    2013-01-01

    Einleitung: Tympanoplastiken I/III bei chron. Otitis media COM (mesotympanalis CMOM und epitympanalis CEOM). In der Literatur werden erfolgreiche operative Behandlungen mit Verringerung der Schallleitungskomponente (air-bone gap) belegt (Gierke et al. 2011). Aus Sicht des Patienten steht die Verbesserung des Hörvermögens und des Sprachverstehens im Alltag im Vordergrund. Das Ziel war die Untersuchung der Entwicklung des Hörvermögens in Ruhe sowie im Störgeräusch.Methoden: An den Hör- und Sp...

  11. Die Entwicklung des Verhaltens bei der Nahrungsaufnahme, der Pflege und dem Spielen bei Kindern im 2. und 3. Lebensjahr in Tageseinrichtungen

    OpenAIRE

    Sporrer, Tobias

    2013-01-01

    Die vorliegende Arbeit beschäftigt sich mit einem Teil des Dokumentationsbogens der kindlichen Entwicklung, der im Lóczy-Institut in Budapest unter der Leitung der Kinderärztin Emmi Pikler erarbeitet wurde. Mit ihm können außerhäuslich betreute Kinder in ihrer Entwicklung beobachtet und diese dokumentiert werden. Das Ziel ist, differenzierte Aussagen zur Entwicklung der betreuten Kinder machen zu können. Die Normierung des Bogens erfolgte erstmals in den 1960er Jahren in Ungarn. Wir führen in...

  12. FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

    Directory of Open Access Journals (Sweden)

    Tomyslav Sledevič

    2013-05-01

    Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

  13. Simple generation of threshold for images binarization on FPGA

    Directory of Open Access Journals (Sweden)

    Egidio Ieno

    2015-09-01

    Full Text Available This paper proposes the FPGA implementation of a threshold algorithm used in the process of image binarization by simple mathematical calculations. The implementation need only one image iteration and its processing time depends on the size of the image. The threshold values of different images obtained through the FPGA implementation are compared with those obtained by Otsu’s method, showing the differences and the visual results of binarization using both methods. The hardware implementation of the algorithm is performed by model-based design supported by the MATLAB®/Simulink® and Xilinx System Generator® tools. The results of the implementation proposal are presented in terms of resource consumption and maximum operating frequency in a Spartan-6 FPGA-based development board. The experimental results are obtained in co-simulation system and show the effectiveness of the proposed method.

  14. FPGA-based implementation of sorting networks in MMC applications

    DEFF Research Database (Denmark)

    Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

    2016-01-01

    In this paper an implementation technique for Field Programmable Gate Array (FPGA) devices of two Sorting Networks (SNs) used for control of Modular Multilevel Converter (MMC) is presented. In such applications, the classical sorting algorithms are based on repetitive/recursive loops, and they ar......In this paper an implementation technique for Field Programmable Gate Array (FPGA) devices of two Sorting Networks (SNs) used for control of Modular Multilevel Converter (MMC) is presented. In such applications, the classical sorting algorithms are based on repetitive/recursive loops......, and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance...

  15. A low-power wave union TDC implemented in FPGA

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

    2011-01-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  16. A low-power Wave Union TDC implemented in FPGA

    International Nuclear Information System (INIS)

    Wu, J; Shi, Y; Zhu, D

    2012-01-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field-programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  17. Porting VIRTEX4 data acquisition design to SPARTAN6 FPGA

    International Nuclear Information System (INIS)

    Suetoe, J.; Hegyesi, G.

    2012-01-01

    Complete text of publication follows. The Atomki's Virtex 4 based 4 channel data acquisition card (LIR) card was used in many applications (miniPET-II, miniPET-III, data acquisition system for the multichannel plate installed at the ECR lab). The goal of the work was to improve the LIR using a higher performance FPGA (Spartan6 Trenz module). The Trenz module based system also supports ADC channels up to 16 channels. This work also implied the porting of the Virtex4 based VHDL code to Spartan 6. Further advantage of the proposed system, besides the improvement in the number of ADC channels, that the Spartan6 FPGA is able to run more complex digital signal processing algorithms than the Virtex 4 FPGA. Easy access to the control parameters (via serial interface or Ethernet), flexibility and high performance were considered during the development. SPARTAN6 FPGA based data acquisition provides more facilities than the VIRTEX4 based. SPARTAN6 is a newer generation of XILINX’s FPGAs, which excellent into the high-speed data acquisition. We ported the HDL code, which runs on LIR module (VIRTEX4 based), to the Trenz module (SPARTAN6 based). The main parts of the whole program code are the command line interpreter, GMII interface, DHCP process, ARP process and the data read out. Those parts were implemented by picoblaze embedded system. Figure 1 shows the command line interpreter process in the Hyper Terminal. The command line interpreter communicates with the PC via serial port. In addition, the AdamIOSetting software also use the serial communication, which was created to the VIRTEX FPGA based data collector. In the Wireshark network analyzer software we examined the DHCP and ARP process and using the AdamIOSettings software we tested the data read out from the flash memory of FPGA board. Figure 2 shows the AdamIOSettings program. Acknowledgements. This work was supported by the ENIAC CSI Project (No.120209).

  18. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    Hardware acceleration is a viable solution to obtain energy efficiency in data intensive computation. In this work, we present a hardware framework to dynamically load hardware libraries, HLL, on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on......-the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

  19. Logic synthesis for FPGA-based finite state machines

    CERN Document Server

    Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

    2016-01-01

    This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

  20. Radiation Tolerant, FPGA-Based SmallSat Computer System

    Science.gov (United States)

    LaMeres, Brock J.; Crum, Gary A.; Martinez, Andres; Petro, Andrew

    2015-01-01

    The Radiation Tolerant, FPGA-based SmallSat Computer System (RadSat) computing platform exploits a commercial off-the-shelf (COTS) Field Programmable Gate Array (FPGA) with real-time partial reconfiguration to provide increased performance, power efficiency and radiation tolerance at a fraction of the cost of existing radiation hardened computing solutions. This technology is ideal for small spacecraft that require state-of-the-art on-board processing in harsh radiation environments but where using radiation hardened processors is cost prohibitive.

  1. Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

    Directory of Open Access Journals (Sweden)

    Bhattacharyya Shuvra S

    2003-01-01

    Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

  2. FPGA prototyping by Verilog examples Xilinx Spartan-3 version

    CERN Document Server

    Chu, Pong P

    2008-01-01

    FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a "learn by doing" approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

  3. FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications

    Directory of Open Access Journals (Sweden)

    S. Tsakiris

    2009-09-01

    Full Text Available This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.

  4. A highly integrated FPGA-based nuclear magnetic resonance spectrometer.

    Science.gov (United States)

    Takeda, Kazuyuki

    2007-03-01

    The digital circuits required for a nuclear magnetic resonance (NMR) spectrometer, including a pulse programmer, a direct digital synthesizer, a digital receiver, and a PC interface, have been built inside a single chip of the field-programmable gate-array (FPGA). By combining the FPGA chip with peripheral analog components, a compact, laptop-sized homebuilt spectrometer has been developed, which is capable of a rf output of up to 400 MHz with amplitude-, phase-, frequency-, and pulse-modulation. The number of rf channels is extendable up to three without further increase in size.

  5. Using FPGA coprocessor for ATLAS level 2 trigger application

    International Nuclear Information System (INIS)

    Khomich, Andrei; Hinkelbein, Christian; Kugel, Andreas; Maenner, Reinhard; Mueller, Matthias

    2006-01-01

    Tracking has a central role in the event selection for the High-Level Triggers of ATLAS. It is particularly important to have fast tracking algorithms in the trigger system. This paper investigates the feasibility of using FPGA coprocessor for speeding up of the TRT LUT algorithm-one of the tracking algorithms for second level trigger for ATLAS experiment (CERN). Two realisations of the same algorithm have been compared: one in C++ and a hybrid C++/VHDL implementation. Using a FPGA coprocessor gives an increase of speed by a factor of two compared to a CPU-only implementation

  6. Software layer for FPGA-based TESLA cavity control system

    Science.gov (United States)

    Koprek, Waldemar; Kaleta, Pawel; Szewinski, Jaroslaw; Pozniak, Krzysztof T.; Czarski, Tomasz; Romaniuk, Ryszard S.

    2005-02-01

    The paper describes design and practical realization of software for laboratory purposes to control FPGA-based photonic and electronic equipment. There is presented a universal solution for all relevant devices with FPGA chips and gigabit optical links. The paper describes architecture of the software layers and program solutions of hardware communication based on Internal Interface (II) technology. Such a solution was used for superconducting Cavity Controller and Simulator (SIMCON) for the TESLA experiment in DESY (Hamburg). A number of practical examples of the software solutions for the SIMCON system were given in this paper.

  7. The hardware design of digital MCA based on FPGA and USB

    International Nuclear Information System (INIS)

    Fang Fei; Li Zhen; Wei Yixiang; Wang Ke

    2012-01-01

    An digital MCA (multi-channel analyzer) based on FPGA and USB2.0 technology is introduced. FPGA is the main processor. The nuclear signal through the amplifier circuit and AD converter is processed in FPGA. then the result is transferred to host computer through USB2.0 interface. The design achieves full digital control. Verilog HDL is used for FPGA programming and the interface software on the host computer is written in QT. The software on the host computer accomplishes the acquisition and display of the input signal and the MCA spectrum. The MCA pulse-amplitude analysis is achieved digitally in FPGA. (authors)

  8. CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

    CERN Document Server

    Zhu, Yu

    2010-01-01

    Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

  9. Random number generators for large-scale parallel Monte Carlo simulations on FPGA

    Science.gov (United States)

    Lin, Y.; Wang, F.; Liu, B.

    2018-05-01

    Through parallelization, field programmable gate array (FPGA) can achieve unprecedented speeds in large-scale parallel Monte Carlo (LPMC) simulations. FPGA presents both new constraints and new opportunities for the implementations of random number generators (RNGs), which are key elements of any Monte Carlo (MC) simulation system. Using empirical and application based tests, this study evaluates all of the four RNGs used in previous FPGA based MC studies and newly proposed FPGA implementations for two well-known high-quality RNGs that are suitable for LPMC studies on FPGA. One of the newly proposed FPGA implementations: a parallel version of additive lagged Fibonacci generator (Parallel ALFG) is found to be the best among the evaluated RNGs in fulfilling the needs of LPMC simulations on FPGA.

  10. N queens on an fpga: mathematics,programming, or both?

    NARCIS (Netherlands)

    Kuper, Jan; Wester, Rinse

    2014-01-01

    This paper presents a design methodology for deriving an FPGA implementation directly from a mathematical specification, thus avoiding the switch in semantic perspective as is present in widely applied methods which include an imperative implementation as an intermediate step. The first step in the

  11. Junction Temperature Aware Energy Efficient Router Design on FPGA

    DEFF Research Database (Denmark)

    Thind, Vandana; Sharma, Shivani; Minwer, M H

    2015-01-01

    Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature...

  12. Programovatelná hradlová pole - FPGA

    Czech Academy of Sciences Publication Activity Database

    Daněk, Martin

    2006-01-01

    Roč. 12, č. 2 (2006), s. 9-13 ISSN 1210-9592 R&D Projects: GA ČR GA102/04/2137 Institutional research plan: CEZ:AV0Z10750506 Keywords : FPGA architecture * physical design * design flow Subject RIV: JC - Computer Hardware ; Software

  13. fpga controller design and simulation of a portable dough mixing

    African Journals Online (AJOL)

    time simulation system for modeling electric motors based on a FPGA chip (Altera FLEX. 10KEPF10K70). ... the estimated speed. A prototyping board is the central piece with a PC and motor drive circuit attached [36]. 2.1. .... Dough can be mixed by an electric mixer. [27]. Lindley has proposed a detailed review of mixing ...

  14. Exploring Sequence Alignment Algorithms on FPGA-based Heterogeneous Architectures

    NARCIS (Netherlands)

    Chang, Xin; Escobar, Fernando A.; Valderrama, Carlos; Robert, Vincent; Ortuno, F.; Rojas, I.

    2014-01-01

    With the rapid development of DNA sequencer, the rate of data generation is rapidly outpacing the rate at which it can be computationally processed. Traditional sequence alignment based on PC cannot fulfill the increasing demand. Accelerating the algorithm using FPGA provides the better performance

  15. FPGA based VME boards for Indus-2 timing control system

    International Nuclear Information System (INIS)

    Lulani, Nitin; Barpande, K.; Fatnani, P.; Sheth, Y.

    2009-01-01

    FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards. (author)

  16. Test of Gb Ethernet with FPGA for HADES upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Gilardi, C. [II. Physikalisches Inst., Giessen Univ. (Germany)

    2007-07-01

    Within the HADES experiment, we are investigating a trigger upgrade in order to run heavier systems (Au + Au). We investigate Gigabit Ethernet transfers with Xilinx Virtex II FPGA on the commercial board Celoxica RC300E. We implement the transfer protocols (UDP, ICMP, ARP) with Handel-C. First results of bandwidth and latency will be presented. (orig.)

  17. FPGA based fast synchronous serial multi-wire links synchronization

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2013-10-01

    The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

  18. Single Event Effects in FPGA Devices 2015-2016

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  19. SEU mitigation exploratory tests in a ITER related FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

    2017-05-15

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  20. Entwicklung von Extraktions- und Absorptionssystemen auf Basis ionischer Flüssigkeiten für die Entschwefelung von Kohlenwasserstoffen

    OpenAIRE

    Kuhlmann, Esther

    2008-01-01

    Da die Anforderungen an den Schwefelgehalt der fossilen Brennstoffe - nicht zuletzt durch gesetzliche Richtlinien bezüglich der Schadstoffemissionen - im Laufe der Zeit ständig gestiegen sind, sind effektive Entschwefelungsverfahren für fossile Brennstoffe von hohem Interesse. Die derzeitige Entschwefelungstechnologie basiert auf dem HDS-Verfahren, alternative Verfahren sind aber wünschenswert, insbesondere wenn Anwendungen einen Schwefelgehalt von weit unter 10 ppm erforderlich machen. Daher...

  1. Development of highly efficient large-area a-Si PV module. Final report; Entwicklung hocheffizienter grossflaechiger a-Si-Photovoltaikmodule. Abschlussbericht

    Energy Technology Data Exchange (ETDEWEB)

    Ruebel, H.; Frammelsberger, W.; Lechner, P.; Geyer, R.; Schade, H.; Psyk, W.

    1998-06-01

    This project was focused on the development of stable PV modules based on a-Si, and on the process transfer from a laboratory scale to a large-area production level. Central to these efforts is the economic relevance that requires reasonable module efficiencies obtained with high throughput and yield. Our modules contain p-i-n/p-i-n (a-Si/a-Si) cell structures that are based on deposition procedures developed at ISI, i.e. low-temperature deposition and high hydrogen dilution for the top cell, and microdoping between the p-layer and the buffer layer for the cottom cell. The maximum stabilized (1800 h) module efficiency obtained by production-relevant processes is 6.5% for the aperture area of 5445 cm{sup 2}. (orig.) [Deutsch] Die Arbeiten im Rahmen des Projekts konzentrierten sich auf die Entwicklung moeglicht stabiler a-Si-PV-Module und auf die Umsetzung vorhandener Labortechniken in einen industriellen Fertigungsmassstab. Mitbestimmend fuer die Entwicklungsarbeiten war die kommerzielle Relevanz, die brauchbare Modulleistungen verknuepft mit hohem Durchsatz bei hoher Ausbeute. Die Basis fuer unsere jetzige Zellstruktur im Modul sind die a-Si/a-Si-(p-i-n/p-i-n)-Technologie und die Technologiekonzepte des ISI (Tieftemperaturabscheidung bei hoher H-Verduennung fuer die Topzelle sowie Feindotierung des Uebergangs von der p-Schicht in den Puffer hinein fuer die Bottomzelle). Das beste mit einem fertigungsrelevanten Prozess hergestellte Modul erreicht nach 1800 h Lichtalterung einen stabilisierten Aperturwirkungsgrad von 6.5%. (orig.)

  2. Entwicklung eines computergestützten Assessment-Tools zur Erfassung des Ernährungszustandes von Senioren

    OpenAIRE

    Ott-Renzer, Cornelia

    2011-01-01

    Einleitung: Weltweit ist ein demografischer Wandel der Bevölkerung zu beobachten, so auch in Deutschland. Spezielle Kenntnisse auf dem Gebiet der geriatrischen Diagnostik und Therapie werden an Wichtigkeit gewinnen. Dabei kommt der Bestimmung des Ernährungszustandes durch entsprechendes Screening- und Assessment eine besondere Bedeutung zu. Herkömmliches Assessment entspricht meist Fragebogenmethoden. Ziel/Fragestellung: Im Fokus stand die Entwicklung einer Software (geroMAT-Malnutriti...

  3. Entwicklung von Methoden zur selektiven Trennung von Scandium, Zirkonium und Zinn für radiopharmazeutische Anwendungen

    OpenAIRE

    Dirks-Fandrei, Carina

    2014-01-01

    Die vorliegende Arbeit befasst sich mit der Entwicklung von schnellen und hoch selektiven Methoden für die Trennung und Aufreinigung von Scandium, Zirkonium und Zinn. Diese Radionuklide können aus potentiellen Targetmaterialien gewonnen werden und können Anwendung in der Nuklearmedizin finden. Es wurden verschiedene Resins (von TrisKem International) auf ihre Extraktionsfähigkeit im Hinblick auf eine breite Anzahl von Kat...

  4. Entwicklung und Validierung eines Fragebogens zum Erleben von Computerspielen : Untersuchung von Transfereffekten zwischen virtueller und realer Welt

    OpenAIRE

    Luthman, Stefanie

    2008-01-01

    In der vorliegenden Arbeit wird die Entwicklung und Validierung eines Fragebogens vorgestellt, der auf den Überlegungen von Fritz (1997) zu einem Wirkungsmodell virtueller Welten basiert. Dieses Selbstbeurteilungsinstrument erfasst mit 40 Items Transferprozesse im Zusammenhang mit dem Spielen von Computer- und Videospielen. Die fünf Skalen des Fragebogens zum Erleben von Computerspielen (FEC) wurden durch faktorenanalytische Untersuchungen an einer repräsentativen Stichprobe von insgesamt 597...

  5. FPGA Implementation of a SAR Two-dimensional Autofocus Approach

    Directory of Open Access Journals (Sweden)

    Guo Jiangzhe

    2016-08-01

    Full Text Available For real-time autofocus of defocused images produced by Synthetic Aperture Radar (SAR, the twodimensional autofocus approach proposed in this study is used to correct the residual range cell migration and compensate for the phase error. Next, a block-wise Phase Gradient Autofocus (PGA is used to correct the space-variant phase error. The Field-Programmable Gate Array (FPGA design procedures, resource utilization, processing speed, accuracy, and autofocus are discussed in detail. The system is able to autofocus an 8K × 8K complex image with single precision within 5.7 s when the FPGA works at 200 MHz. The processing of the measured data verifies the effectiveness and real-time capability of the proposed method.

  6. Circuit design of a novel FPGA chip FDP2008

    International Nuclear Information System (INIS)

    Wu Fang; Wang Yabin; Chen Liguang; Wang Jian; Lai Jinmei; Wang Yuan; Tong Jiarong

    2009-01-01

    A novel FPGA chip FDP2008 (Fudan Programmable Logic) has been designed and implemented with the SMIC 0.18 μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX + Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 x 30 logic TILEs, 200 programmable IOBs and 10 x 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently. (semiconductor integrated circuits)

  7. Flexible, fpga-based electronics for modular robots

    DEFF Research Database (Denmark)

    Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

    2008-01-01

    In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...... the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible...

  8. Intermediate Frequency Digital Receiver Based on Multi-FPGA System

    Directory of Open Access Journals (Sweden)

    Chengchang Zhang

    2016-01-01

    Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

  9. FPGA-based digital convolution for wireless applications

    CERN Document Server

    Guan, Lei

    2017-01-01

    This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

  10. Energy Detector Implementaton in FPGA for Estimation of Word Boundaries

    Directory of Open Access Journals (Sweden)

    Liudas Stašionis

    2013-05-01

    Full Text Available This paper describes implementation of the word boundary estimation module in FPGA. The boundary estimation module is based on energy detector. This module is optimized for implementation in FPGA. It occupies 54 logical elements “Slice” and uses only 0.7% of “Spartan-6 LX45” resources. Experiments with this module were performed at different signal/noise (S/N ratio. For S/N of 20 dB and 15 dB word boundaries were estimated with 100% accuracy. Acceptable results were also achieved, for S/N ratio of 10 dB and 5 dB, as the estimation accuracy was 95% and 93%, respectively.Article in Lithuanian

  11. FPGA-Based Instrumentation for the Fermilab Antiproton Source

    CERN Document Server

    Ashmanskas, Bill; Kiper, Terry; Peterson, David

    2005-01-01

    We have designed and built low-cost, low-power, ethernet-based circuit boards to apply DSP techniques to several instrumentation upgrades in the Fermilab Antiproton Source. Commodity integrated circuits such as direct digital synthesizers, D/A and A/D converters, and quadrature demodulators enable digital manipulation of RF waveforms. A low cost FPGA implements a variety of signal processing algorithms in a manner that is easily adapted to new applications. An embedded microcontroller provides FPGA configuration, control of data acquisition, and command-line interface. A small commercial daughter board provides an ethernet-based TCP/IP interface between the microcontroller and the Fermilab accelerator control network. The board is packaged as a standard NIM module. Applications include Low Level RF control for the Debuncher, readout of transfer-line Beam Position Monitors, and narrow-band spectral analysis of diagnostic signals from Schottky pickups.

  12. High Performance FPGA-Based DMA Interface for PCIe

    Science.gov (United States)

    Kavianipour, Hossein; Muschter, Steffen; Bohm, Christian

    2014-04-01

    We present a data communication suite developed for use in the Track Engine Trigger for the IceCube Neutrino Observatory at the South Pole. The suite is applicable to any bidirectional Direct Memory Access (DMA) transfer between FPGA logic and system memory on a host PC via PCIe. The suite contains a DMA controller firmware, test benches, a Linux driver and a user application for DMA and Peripheral Input/Output transfers (PIO) into on-FPGA memory modules and FIFOs. The DMA which is based on the Xilinx' bus master DMA, produces measured transfer speeds up to 748 MB/s (read) and 784 MB/s (write) using the Xilinx VC707 Virtex-7 board. The hardware part of the suite has been verified on different circuit boards with different FPGAs.

  13. Towards a FPGA-controlled deep phase modulation interferometer

    Science.gov (United States)

    Terán, M.; Martín, V.; Gesa, Ll; Mateos, I.; Gibert, F.; Karnesis, N.; Ramos-Castro, J.; Schwarze, T. S.; Gerberding, O.; Heinzel, G.; Guzmán, F.; Nofrarias, M.

    2015-05-01

    Deep phase modulation interferometry was proposed as a method to enhance homodyne interferometers to work over many fringes. In this scheme, a sinusoidal phase modulation is applied in one arm while the demodulation takes place as a post-processing step. In this contribution we report on the development to implement this scheme in a fiber coupled interferometer controlled by means of a FPGA, which includes a LEON3 soft-core processor. The latter acts as a CPU and executes a custom made application to communicate with a host PC. In contrast to usual FPGA-based designs, this implementation allows a real-time fine tuning of the parameters involved in the setup, from the control to the post-processing parameters.

  14. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  15. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Pierre Chalimbaud

    2006-12-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  16. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Chalimbaud Pierre

    2007-01-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  17. Development, application and licensing of FPGA based safety systems

    Energy Technology Data Exchange (ETDEWEB)

    Tuite, T.C.; Carvajal, J.V., E-mail: tuitetc@westinghouse.com, E-mail: carvajjv@westinghouse.com [Westinghouse Electric Company, Pennsylvania, (United States)

    2015-07-01

    Westinghouse has developed the Advanced Logic System (ALS) platform. The ALS platform was recently approved by the US NRC. In addition, ALS was successfully installed and declared operational as a Thermocouple/Core Cooling Monitor upgrade at the Wolf Creek Generating Station. The ALS has also been installed at the AP1000 Sanmen and Haiyang unit sites as the Diverse Actuation System. The ALS platform is based on FPGA technology. FPGA safety system designs are simpler than comparable CPU based system designs in that they do not require an Operating System or instruction set. The ALS platform provides inherent diversity in redundant cores and diverse core designs. In addition, the ALS provides extensive self-testing and diagnostics which allows for extension of plant surveillance intervals. (author)

  18. Architecture exploration of FPGA based accelerators for bioinformatics applications

    CERN Document Server

    Varma, B Sharat Chandra; Balakrishnan, M

    2016-01-01

    This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.

  19. FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

    Science.gov (United States)

    Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

    2017-06-01

    A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

  20. A new FPGA architecture suitable for DSP applications

    International Nuclear Information System (INIS)

    Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan

    2011-01-01

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 x 4.5 mm 2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

  1. FPGA-based network data transmission scheme for CSNS

    International Nuclear Information System (INIS)

    Wang Xiuku; Zhang Hongyu; Gu Minhao; Xiao Liang

    2012-01-01

    This paper presents the FPGA-based network data transmission solutions for the Data Acquisition System of China Spallation Neutron Source (CSNS). The board with FPGA as the core is used as the hardware platform to realize the transmission of network data. A SOPC system is built and an embedded Linux is transplanted on PowerPC Core. An application program based on Linux has been finished to realize the data transmission via embedded Gigabit Ethernet. The relationship between network transfer performance and packet size was obtained by a test program. In addition, the paper also tried to realize some other ways to transfer data: transplanting PetaLinux on Microblaze, transplanting Lwip protocol stack on PowerPC Core and Microblaze. Their advantages and disadvantages are analyzed and compared in this paper, so that different options and recommendations can be given to meet the actual needs of different projects in the future. (authors)

  2. Estimating the circuit delay of FPGA with a transfer learning method

    Science.gov (United States)

    Cui, Xiuhai; Liu, Datong; Peng, Yu; Peng, Xiyuan

    2017-10-01

    With the increase of FPGA (Field Programmable Gate Array, FPGA) functionality, FPGA has become an on-chip system platform. Due to increase the complexity of FPGA, estimating the delay of FPGA is a very challenge work. To solve the problems, we propose a transfer learning estimation delay (TLED) method to simplify the delay estimation of different speed grade FPGA. In fact, the same style different speed grade FPGA comes from the same process and layout. The delay has some correlation among different speed grade FPGA. Therefore, one kind of speed grade FPGA is chosen as a basic training sample in this paper. Other training samples of different speed grade can get from the basic training samples through of transfer learning. At the same time, we also select a few target FPGA samples as training samples. A general predictive model is trained by these samples. Thus one kind of estimation model is used to estimate different speed grade FPGA circuit delay. The framework of TRED includes three phases: 1) Building a basic circuit delay library which includes multipliers, adders, shifters, and so on. These circuits are used to train and build the predictive model. 2) By contrasting experiments among different algorithms, the forest random algorithm is selected to train predictive model. 3) The target circuit delay is predicted by the predictive model. The Artix-7, Kintex-7, and Virtex-7 are selected to do experiments. Each of them includes -1, -2, -2l, and -3 different speed grade. The experiments show the delay estimation accuracy score is more than 92% with the TLED method. This result shows that the TLED method is a feasible delay assessment method, especially in the high-level synthesis stage of FPGA tool, which is an efficient and effective delay assessment method.

  3. Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research

    Directory of Open Access Journals (Sweden)

    Burgess Shane C

    2008-04-01

    Full Text Available Abstract Background This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences. Results This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs. Conclusion Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.

  4. FPGA based, modular, configurable controller with fast synchronous optical network

    Energy Technology Data Exchange (ETDEWEB)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

    2006-07-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  5. Teaching Computer Organization and Architecture Using Simulation and FPGA Applications

    OpenAIRE

    D. K.M. Al-Aubidy

    2007-01-01

    This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemente...

  6. FPGA applications for single dish activity at Medicina radio telescopes

    Science.gov (United States)

    Bartolin, M.; Nald, G.; Mattan, A.; Maccaferr, A.; De Biagg, M.

    FPGA technologies are gaining major attention in the recent years in the field of radio astronomy. At Medicina radio telescopes, FPGAs have been used in the last ten years for a number of purposes and in this article we will take into exam the applications developed and installed for the Medicina Single Dish 32m Antenna: these range from high performance digital signal processing to instrument control developed on top of smaller FPGAs.

  7. A CMOS high speed imaging system design based on FPGA

    Science.gov (United States)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  8. Spacecraft Neural Network Control System Design using FPGA

    OpenAIRE

    Hanaa T. El-Madany; Faten H. Fahmy; Ninet M. A. El-Rahman; Hassen T. Dorrah

    2011-01-01

    Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffer...

  9. VHDL resolved function based inner communication bus for FPGA

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2017-08-01

    This article discusses a method of building an internal, universal and parametric bus. The solution was designed for a variety of FPGA families and popular VHDL compilers. The algorithm of automatic configuration of address space and methods of receiving and sending addressed data are discussed. The basic solution realized in VHDL language in a behavioral form and chosen examples of practical use of the internal bus are presented in detail.

  10. FPGA based, modular, configurable controller with fast synchronous optical network

    International Nuclear Information System (INIS)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S.

    2006-01-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  11. FPGA based mixed-signal circuit novel testing techniques

    International Nuclear Information System (INIS)

    Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

    2013-01-01

    Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

  12. FPGA-based klystron linearization implementations in scope of ILC

    Energy Technology Data Exchange (ETDEWEB)

    Omet, M., E-mail: momet@post.kek.jp [The Graduate University for Advanced Studies, Hayama (Japan); Michizono, S.; Matsumoto, T.; Miura, T.; Qiu, F. [The Graduate University for Advanced Studies/High Energy Accelerator Research Organization, Tsukuba (Japan); Chase, B.; Varghese, P. [Fermi National Accelerator Laboratory, Batavia (United States); Schlarb, H.; Branlard, J. [Deutsches Elektronen-Synchrotron, Hamburg (Germany); Cichalewski, W. [Lodz University of Technology, Lodz (Poland)

    2014-12-21

    We report the development and implementation of four FPGA-based predistortion-type klystron linearization algorithms. Klystron linearization is essential for the realization of ILC, since it is required to operate the klystrons 7% in power below their saturation. The work presented was performed in international collaborations at the Fermi National Accelerator Laboratory (FNAL), USA and the Deutsches Elektronen Synchrotron (DESY), Germany. With the newly developed algorithms, the generation of correction factors on the FPGA was improved compared to past algorithms, avoiding quantization and decreasing memory requirements. At FNAL, three algorithms were tested at the Advanced Superconducting Test Accelerator (ASTA), demonstrating a successful implementation for one algorithm and a proof of principle for two algorithms. The functionality of the algorithm implemented at DESY was demonstrated successfully in a simulation. Besides this, a proof of principle of an FPGA-based klystron and cavity simulator implemented at the High Energy Accelerator Research Organization (KEK), Japan, was demonstrated. Its purpose is to allow the development and test of digital LLRF control systems including klystron linearization algorithms when no actual klystron and cavity are available.

  13. The current state of FPGA technology in the nuclear domain

    Energy Technology Data Exchange (ETDEWEB)

    Ranta, J.

    2012-07-01

    Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

  14. An FPGA Implementation to Detect Selective Cationic Antibacterial Peptides

    Science.gov (United States)

    Polanco González, Carlos; Nuño Maganda, Marco Aurelio; Arias-Estrada, Miguel; del Rio, Gabriel

    2011-01-01

    Exhaustive prediction of physicochemical properties of peptide sequences is used in different areas of biological research. One example is the identification of selective cationic antibacterial peptides (SCAPs), which may be used in the treatment of different diseases. Due to the discrete nature of peptide sequences, the physicochemical properties calculation is considered a high-performance computing problem. A competitive solution for this class of problems is to embed algorithms into dedicated hardware. In the present work we present the adaptation, design and implementation of an algorithm for SCAPs prediction into a Field Programmable Gate Array (FPGA) platform. Four physicochemical properties codes useful in the identification of peptide sequences with potential selective antibacterial activity were implemented into an FPGA board. The speed-up gained in a single-copy implementation was up to 108 times compared with a single Intel processor cycle for cycle. The inherent scalability of our design allows for replication of this code into multiple FPGA cards and consequently improvements in speed are possible. Our results show the first embedded SCAPs prediction solution described and constitutes the grounds to efficiently perform the exhaustive analysis of the sequence-physicochemical properties relationship of peptides. PMID:21738652

  15. Design of video interface conversion system based on FPGA

    Science.gov (United States)

    Zhao, Heng; Wang, Xiang-jun

    2014-11-01

    This paper presents a FPGA based video interface conversion system that enables the inter-conversion between digital and analog video. Cyclone IV series EP4CE22F17C chip from Altera Corporation is used as the main video processing chip, and single-chip is used as the information interaction control unit between FPGA and PC. The system is able to encode/decode messages from the PC. Technologies including video decoding/encoding circuits, bus communication protocol, data stream de-interleaving and de-interlacing, color space conversion and the Camera Link timing generator module of FPGA are introduced. The system converts Composite Video Broadcast Signal (CVBS) from the CCD camera into Low Voltage Differential Signaling (LVDS), which will be collected by the video processing unit with Camera Link interface. The processed video signals will then be inputted to system output board and displayed on the monitor.The current experiment shows that it can achieve high-quality video conversion with minimum board size.

  16. Komunikace USB3.0 čipu s FPGA

    OpenAIRE

    Špeťko, Matej

    2015-01-01

    SEC6NET je zkrácený název pro projekt Moderní prostředky pro boj s kybernetickou kriminalitou na Internetu nové generace. Projekt je zaměřen na výzkum a vývoj prostředků monitorování síťového provozu a analýzu jeho záznamu. V rámci tohoto projektu jsou vyvíjená zařízení - sondy pro monitorování IPv6 sítí. Sondy využívají hardwarovou akceleraci pomocí FPGA. Moje práce spojuje dvě technologie: FPGA a USB. Cílem mojí práce je zabezpečení přenosu dat z FPGA čipu sondy do PC prostřednictvím mikrok...

  17. Reconfigurable Network Stream Processing on Virtualized FPGA Resources

    Directory of Open Access Journals (Sweden)

    Qianqiao Chen

    2018-01-01

    Full Text Available The software defined network and network function virtualization are proposed to address the network ossification issue in current Internet infrastructure. Network functions and services are implemented as software applications to increase the programmability of network. However, involving general purpose processors in data plane restricts the bandwidth of network services. Therefore, to keep both the bandwidth and flexibility, a FPGA platform is suggested as a reconfigurable platform to deliver high bandwidth virtual network functions on data plane. In this paper, the FPGA resource has been virtualized by interconnecting partial reconfigurable regions to deliver high bandwidth reconfigurable processing on network streams. With the help of partial reconfiguration technology, network functions on our platform can be configured without affecting other functions on the same FPGA device. The on-chip interconnect system is further evaluated by comparing with existing network-on-chip system. A reconfiguration process is also proposed and demonstrated that it can be performed on our platform. The process can happen in the real time of network services and it is able to keep the original function working during the download of partial bitstream.

  18. FPGA-based network intrusion detection for IEC 61850-based industrial network

    Directory of Open Access Journals (Sweden)

    Junsik Kim

    2018-03-01

    Full Text Available This paper proposes an FPGA-based network intrusion detection system for the IEC 61850-based industrial network that is specially designed for substation automation. The proposed system uses the Shift-And algorithm for detecting malicious network packets within IEC 61850 messages. To implement a complex rule matching module with a limited memory size of FPGA, a specially designed rule matching module was proposed in this paper. For feasibility evaluation, a prototype with 265 regular expression matching modules was implemented using Xilinx Zynq-7030 FPGA and its performance is presented in this paper. Keywords: Network intrusion detection system (NIDS, IEC 61850, Regular expression, Substation automation, FPGA

  19. New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie D.; Label, Kenneth A.; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  20. New Developments in FPGA Devices: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  1. New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project

    CERN Document Server

    Mendez, Julian Maxime; Caratelli, Alessandro; Leitao, Pedro Vicente

    2018-01-01

    The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

  2. An innovative modular device and wireless control system enabling thermal and pressure sensors using FPGA on real-time fault diagnostics of steam turbine functional deterioration

    Science.gov (United States)

    Devi, S.; Saravanan, M.

    2018-03-01

    It is necessary that the condition of the steam turbines is continuously monitored on a scheduled basis for the safe operation of the steam turbines. The review showed that steam turbine fault detection and operation maintenance system (STFDOMS) is gaining importance recently. In this paper, novel hardware architecture is proposed for STFDOMS that can be communicated through the GSM network. Arduino is interfaced with the FPGA so as to transfer the message. The design has been simulated using the Verilog programming language and implemented in hardware using FPGA. The proposed system is shown to be a simple, cost effective and flexible and thereby making it suitable for the maintenance of steam turbines. This system forewarns the experts to access to data messages and take necessary action in a short period with great accuracy. The hardware developed is promised as a real-time test bench, specifically for investigations of long haul effects with different parameter settings.

  3. Assessment of Proper Bonding Methods and Mechanical Characterization FPGA CQFPs

    Science.gov (United States)

    Davis, Milton C.

    2008-01-01

    This presentation discusses fractured leads on field-programmable gate array (FPGA) during flight vibration. Actions taken to determine root cause and resolution of the failure include finite element analysis (FEA) and vibration testing and scanning electron microscopy (with X-ray microanalysis) and energy dispersive spectrometry (SEM/EDS) failure assessment. Bonding methods for surface mount parts is assessed, including critical analysis and assessment of random fatigue damage. Regarding ceramic quad flat pack (CQFP) lead fracture, after disassembling the attitude control electronics (ACE) configuration, photographs showed six leads cracked on FPGA RTSX72SU-1 CQ208B package located on the RWIC card. An identical package (FPGA RTSX32SU-1 CQ208B) mounted on the RWIC did not results in cracked pins due to vibration. FPGA lead failure theories include workmanship issues in the lead-forming, material defect in the leads of the FPGA packages, and the insecure mounting of the board in the card guides, among other theories. Studies were conducted using simple calculations to determine the response and fatigue life of the package. Shorter packages exhibited more response when loaded by out-of-plane displacement of PCB while taller packages exhibit more response when loaded by in-plane acceleration of PCB. Additionally, under-fill did not contribute to reducing stress in leads due to out-of-plane PCB loading or from component twisting, as much as corner bonding. The combination of corner bond and under-fill is best to address mechanical and thermal S/C environment. Test results of bonded parts showed reduced (dampened) amplitude and slightly shifted peaks at the un-bonded natural frequency and an additional response at the bonded frequency. Stress due to PCBB out-of-plane loading was decreased on in the corners when only a corner bond was used. Future work may address CQFP fatigue assessment, including the investigation of discrepancy in predicted fatigue damage, as well as

  4. Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

    Science.gov (United States)

    Du, Hongtao; Qi, Hairong; Szu, Harold H.

    2005-03-01

    Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called jitter effect in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application

  5. Design and demonstration of a multitechnology FPGA for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Hawk, Chris; Toshniwal, Kavita; Beyette, Fred R., Jr.

    2003-11-01

    We present here a novel architecture for a multi-technology field programmabler gate array (MT-FPGA). Implemented with a conventional CMOS VLSI technology the architecture is suitable for prototyping photonic information processing systems. We report here that this new FPGA architecture will enable the design of reconfigurable systems that incorporate technologies outside the traditional electronic domain.

  6. Compute bound and I/O bound Cellular Automata simulations on FPGA logic

    NARCIS (Netherlands)

    Murtaza, S.; Hoekstra, A.G.; Sloot, P.M.A.

    2009-01-01

    FPGA-based computation engines have been used as Cellular Automata accelerators in the scientific community for some time now. With the recent availability of more advanced FPGA logic it becomes necessary to better understand the mapping of Cellular Automata to these systems. There are many

  7. Analysis of Thermal Stability of Different Counter on 28nm FPGA

    DEFF Research Database (Denmark)

    Gupta, Daizy; Yadav, Amit; Hussain, Dil muhammed Akbar

    2016-01-01

    In this paper we are presenting the power analysis for thermal awareness of different counters. The technique we are using to do the analysis is based on 28 nm FPGA tech-nique. In this work during implementation on FPGA, we are going to analyze thermal stability of different counters in temperature...

  8. Development of a multi-purpose logic module with the FPGA

    International Nuclear Information System (INIS)

    Nanbu, K.; Ishikawa, T.; Shimizu, H.

    2008-01-01

    We have developed a multi-purpose logic module (MPLM) with an FPGA. The internal circuit of this module can be modified easily with the FPGA. This kind of module enables trigger pulse processing for nuclear science. As a first step, the MPLM is used as an event tag generator in experiments with the FOREST detector system. (author)

  9. A programmable controller based on CAN field bus embedded microprocessor and FPGA

    Science.gov (United States)

    Cai, Qizhong; Guo, Yifeng; Chen, Wenhei; Wang, Mingtao

    2008-10-01

    One kind of new programmable controller(PLC) is introduced in this paper. The advanced embedded microprocessor and Field-Programmable Gate Array (FPGA) device are applied in the PLC system. The PLC system structure was presented in this paper. It includes 32 bits Advanced RISC Machines (ARM) embedded microprocessor as control core, FPGA as control arithmetic coprocessor and CAN bus as data communication criteria protocol connected the host controller and its various extension modules. It is detailed given that the circuits and working principle, IiO interface circuit between ARM and FPGA and interface circuit between ARM and FPGA coprocessor. Furthermore the interface circuit diagrams between various modules are written. In addition, it is introduced that ladder chart program how to control the transfer info of control arithmetic part in FPGA coprocessor. The PLC, through nearly two months of operation to meet the design of the basic requirements.

  10. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

    Science.gov (United States)

    Asaad, Sameth W.; Kapur, Mohit

    2016-01-05

    A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

  11. Quasar Absorptionslinienverteilung und die Entwicklung der großräumigen Strukturen im Kosmos

    Science.gov (United States)

    Riediger, R.

    1999-06-01

    In der vorliegenden Arbeit wird ein Modell, basierend auf einem modifizierten Particle-Mesh (PM) Code, vorgestellt, das die Verteilung der baryonischen Dichte entlang der großräumigen Strukturen im Kosmos im Dichtebereich der Lyman-alpha-Forest Absorbersysteme gut wiedergibt. Im Kapitel 1 wird ein Überblick über die geschichtliche Entwicklung der Beobachtungen des Lyman-alpha-Forest und dessen statistischer Analysen gegeben. Weiterhin werden lokale Modelle für die Absorptionswolken vorgestellt. In Kapitel 2 werden das dieser Arbeit zugrundeliegende Modell und die durchgeführten Simulationen beschrieben. Weiterhin wird eine Methode zur Erstellung synthetischer Spektren aus den Simulationen eingeführt. Kapitel 3 beschäftigt sich mit den Auswertung der aus den Simulationen erhaltenen statistischen Verteilungen. Diese werden mit den Ergebnissen der Beobachtungen verglichen und es werden die Einflüsse der Analysemethode des Voigt-Profil-Fittens diskutiert. Die Ergebnisse werden dann im Kapitel 4 zusammengefaßt und es wird ein Ausblick auf mögliche Weiterführungen der Arbeit gegeben.

  12. Review: Gerd Jüttemann (Hrsg. (2013. Die Entwicklung der Psyche in der Geschichte der Menschheit

    Directory of Open Access Journals (Sweden)

    Uwe Krebs

    2015-03-01

    Full Text Available Der Vorbereitungsband für die Reihe "Die Psychogenese der Menschheit" – ein Sammelband aus 32 Beiträgen, betitelt "Die Entwicklung der Psyche in der Geschichte der Menschheit" und 2013 herausgegeben von Gerd JÜTTEMANN – wird in dieser Besprechung in mehreren Schritten vorgestellt und bewertet. Zunächst wird kontextuell argumentiert, dass die bewährte, empirisch-experimentelle Methodologie der Psychologie zur Vernachlässigung weiterer Erkenntnisverfahren führte, die bei Themen wie dem hier zu besprechenden Werk allein verbleiben und die kurz angesprochen werden. Sodann wird das Werk im Überblick knapp dargestellt und die außergewöhnliche Heterogenität in Inhalten und Methoden betont. Die Besprechung einzelner Beiträge, die nach dem Gesichtspunkt großer Unterschiedlichkeit ausgewählt wurden, schließt sich an. Die abschließende Gesamtbewertung betont den lückenhaften Forschungsstand, die Notwendigkeit der allein verbleibenden qualitativen Methodik mit ihren verschiedenen Möglichkeiten und nennt Desiderata künftigen Vorgehens für diesen thematisch und methodisch interessanten Auftakt-Band, der insbesondere durch Dichte und Verschiedenheit der Beiträge beeindruckt. URN: http://nbn-resolving.de/urn:nbn:de:0114-fqs1502219

  13. Multirate Digital Filters Based on FPGA and Its Applications

    International Nuclear Information System (INIS)

    Sharaf El-Din, R.M.A.

    2013-01-01

    Digital Signal Processing (DSP) is one of the fastest growing techniques in the electronics industry. It is used in a wide range of application fields such as, telecommunications, data communications, image enhancement and processing, video signals, digital TV broadcasting, and voice synthesis and recognition. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high performance DSP systems. The focus of this thesis is on one of the basic DSP functions, namely filtering signals to remove unwanted frequency bands. Multi rate Digital Filters (MDFs) are the main theme here. Theory and implementation of MDF, as a special class of digital filters, will be discussed. Multi rate digital filters represent a class of digital filters having a number of attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. This thesis introduces an efficient FPGA realization of a multi rate decimation filter with narrow pass-band and narrow transition band to reduce the frequency sample rate by factor of 64 for noise thermometer applications. The proposed multi rate decimation filter is composed of three stages; the first stage is a Cascaded Integrator Comb (CIC) decimation filter, the second stage is a two-coefficient Half-Band (HB) filter and the last stage is a sharper transition HB filter. The frequency responses of individual stages as well as the overall filter response have been demonstrated with full simulation using MATLAB. The design and implementation of the proposed MDF on FPGA (XILINX Virtex XCV800 BG432-4), using VHSIC Hardware Description Language (VHDL), has been introduced. The implementation areas of the proposed filter stages are compared. Using CIC-HB technique saves 18% of the design area, compared to using six stages HB decimation filters.

  14. Real-time windowing in imaging radar using FPGA technique

    Science.gov (United States)

    Ponomaryov, Volodymyr I.; Escamilla-Hernandez, Enrique

    2005-02-01

    The imaging radar uses the high frequency electromagnetic waves reflected from different objects for estimating of its parameters. Pulse compression is a standard signal processing technique used to minimize the peak transmission power and to maximize SNR, and to get a better resolution. Usually the pulse compression can be achieved using a matched filter. The level of the side-lobes in the imaging radar can be reduced using the special weighting function processing. There are very known different weighting functions: Hamming, Hanning, Blackman, Chebyshev, Blackman-Harris, Kaiser-Bessel, etc., widely used in the signal processing applications. Field Programmable Gate Arrays (FPGAs) offers great benefits like instantaneous implementation, dynamic reconfiguration, design, and field programmability. This reconfiguration makes FPGAs a better solution over custom-made integrated circuits. This work aims at demonstrating a reasonably flexible implementation of FM-linear signal and pulse compression using Matlab, Simulink, and System Generator. Employing FPGA and mentioned software we have proposed the pulse compression design on FPGA using classical and novel windows technique to reduce the side-lobes level. This permits increasing the detection ability of the small or nearly placed targets in imaging radar. The advantage of FPGA that can do parallelism in real time processing permits to realize the proposed algorithms. The paper also presents the experimental results of proposed windowing procedure in the marine radar with such the parameters: signal is linear FM (Chirp); frequency deviation DF is 9.375MHz; the pulse width T is 3.2μs taps number in the matched filter is 800 taps; sampling frequency 253.125*106 MHz. It has been realized the reducing of side-lobes levels in real time permitting better resolution of the small targets.

  15. Energy Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Kenn Toft, Jakob; Nannarelli, Alberto

    2014-01-01

    Field Programmable Gate Arrays (FPGAs) based accelerators are very suitable to implement application-specific processors using uncommon operations or number systems. In this work, we design FPGA-based accelerators for two financial computations with different characteristics and we compare...... the accelerator performance and energy consumption to a software execution of the application. The experimental results show that significant speed-up and energy savings, can be obtained for large data sets by using the accelerator at expenses of a longer development time....

  16. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  17. Phase correction on FPGA for TOTEM clock distribution system

    CERN Document Server

    Bellina, Alessandra

    2017-01-01

    A phase correction module has been implemented on FPGA, to control the delay of the clock at TOTEM timing detectors. The module consists of two parts: a phase shifter and a phase detector. The design of the phase shifter has been completed and was tested in the laboratory. The output jitter was measured and met the requirements. The phase detector design has also been completed and tested with a behavioural simulation, which outlined some weaknesses due to intrinsic limitations of FPGAs. The obtained resolution, although below ns scale, could not satisfy the requirements. A discussion on how to improve the performance of the phase detector is included.

  18. An FPGA-based JPEG 2000 Demonstration Board

    OpenAIRE

    Woolston, Tom; Holt, Niel; Bingham, Gail; Wada, Glen

    2005-01-01

    The Space Dynamics Laboratory has developed a hardware-based JPEG 2000 image compression solution and packaged it in a demonstration board. The board implements both Tier1 and Tier2 JPEG 2000 encoding in two Xilinx Virtex II FPGAs. The FPGA design was built as a first step toward developing JPEG 2000 image compression hardware that could be used for remote sensing on the ground, in the air, or in Earth orbit. This board has been used to demonstrate the power and flexibility of the JPEG 2000 s...

  19. FPGA Implementation of Decimal Processors for Hardware Acceleration

    DEFF Research Database (Denmark)

    Borup, Nicolas; Dindorp, Jonas; Nannarelli, Alberto

    2011-01-01

    Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial...... transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its...

  20. LAPACKrc: Fast linear algebra kernels/solvers for FPGA accelerators

    International Nuclear Information System (INIS)

    Gonzalez, Juan; Nunez, Rafael C

    2009-01-01

    We present LAPACKrc, a family of FPGA-based linear algebra solvers able to achieve more than 100x speedup per commodity processor on certain problems. LAPACKrc subsumes some of the LAPACK and ScaLAPACK functionalities, and it also incorporates sparse direct and iterative matrix solvers. Current LAPACKrc prototypes demonstrate between 40x-150x speedup compared against top-of-the-line hardware/software systems. A technology roadmap is in place to validate current performance of LAPACKrc in HPC applications, and to increase the computational throughput by factors of hundreds within the next few years.

  1. FPGA Implementation of Video Transmission System Based on LTE

    Directory of Open Access Journals (Sweden)

    Lu Yan

    2015-01-01

    Full Text Available In order to support high-definition video transmission, an implementation of video transmission system based on Long Term Evolution is designed. This system is developed on Xilinx Virtex-6 FPGA ML605 Evaluation Board. The paper elaborates the features of baseband link designed in Xilinx ISE and protocol stack designed in Xilinx SDK, and introduces the process of setting up hardware and software platform in Xilinx XPS. According to test, this system consumes less hardware resource and is able to transmit bidirectional video clearly and stably.

  2. FPGA implementation of adaptive beamforming in hearing aids.

    Science.gov (United States)

    Samtani, Kartik; Thomas, Jobin; Varma, G Abhinav; Sumam, David S; Deepu, S P

    2017-07-01

    Beamforming is a spatial filtering technique used in hearing aids to improve target sound reception by reducing interference from other directions. In this paper we propose improvements in an existing architecture present for two omnidirectional microphone array based adaptive beamforming for hearing aid applications and implement the same on Xilinx Artix 7 FPGA using VHDL coding and Xilinx Vivado ® 2015.2. The nulls are introduced in particular directions by combination of two fixed polar patterns. This combination can be adaptively controlled to steer the null in the direction of noise. The beamform patterns and improvements in SNR values obtained from experiments in a conference room environment are analyzed.

  3. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    . Zulfikar

    2012-10-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  4. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    Zulfikar Zulfikar

    2015-05-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  5. Enhanced Temperature Control Method Using ANFIS with FPGA

    Directory of Open Access Journals (Sweden)

    Chiung-Wei Huang

    2014-01-01

    Full Text Available Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS using a field-programmable gate array (FPGA to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV inductively-coupled plasma- (ICP- type etcher.

  6. IMPLEMENTATION OF SERIAL AND PARALLEL BUBBLE SORT ON FPGA

    Directory of Open Access Journals (Sweden)

    Dwi Marhaendro Jati Purnomo

    2016-06-01

    Full Text Available Sorting is common process in computational world. Its utilization are on many fields from research to industry. There are many sorting algorithm in nowadays. One of the simplest yet powerful is bubble sort. In this study, bubble sort is implemented on FPGA. The implementation was taken on serial and parallel approach. Serial and parallel bubble sort then compared by means of its memory, execution time, and utility which comprises slices and LUTs. The experiments show that serial bubble sort required smaller memory as well as utility compared to parallel bubble sort. Meanwhile, parallel bubble sort performed faster than serial bubble sort

  7. SRF cavity testing using a FPGA Self Excited Loop

    Energy Technology Data Exchange (ETDEWEB)

    Ben-Zvi, I. [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2017-08-30

    Various authors have previously studied the theory and practice of cavity testing, notably an extensive treatment by Powers [1] and Padamsee [2]. The advent of the digital Low Level RF (LLRF) electronics based on Field Programmable Logic Arrays (FPGA) provides various improvements over the rather complex systems used in the past as well as enabling new measurement techniques.In this document we reintroduce a technique that seems to have fallen out of practice in recent times, that is obtaining the coupling constant β through measurements from just one port, the reflected power port, of the directional coupler placed in front of the cavity.

  8. VERMEIL. Methods for knowledge based development of reliable process controll system. Final report; VERMEIL. Verfahren und Methoden zur wissensbasierten Entwicklung zuverlaessiger Leitsysteme. Abschlussbericht

    Energy Technology Data Exchange (ETDEWEB)

    Goetze, B.; Plessow, M.; Pocher, M.

    1998-12-29

    The goal of the VERMEIL project was to increase the quality of process control systems by using knowledge based methods. One important aspect therein is the quality of the documentation describing the control system. The research done in the subproject of the Society for the Promotion of Applied Computerscience (GFal) produced a basis for the development of graphical editors of a special kind. These graphical editors can be used to create classes of schematic drawings. There were two major aspects concerning the development of graphical editors. First, the editors should provide advanced graphical support. That includes automation of the layout of schematic drawings. Second, the editors should automatically lead to correct structures within the schematics, therefore making certain that the created document is semantically correct, also. Apart from the theoretical and conceptional research, some automated layout algorithms were created in the project. A new prototype of an intelligent graphical editor came into existence, that proves the results of the VERMEIL project and shows the necessity of such a project. (orig.) [Deutsch] Das Ziel des Projektes VERMEIL bestand darin, die Qualitaet von Prozessleittechnik durch den Einsatz von wissensbasierten Methoden waehrend ihrer Projektierung zu erhoehen. Ein Aspekt dabei ist die Qualitaet der Dokumentation, die eine Anlage beschreibt. Im Teilprojekt der GFal wurden deshalb Untersuchungen durchgefuehrt, die die methodischen Grundlagen fuer die Entwicklung spezieller grafischer Editoren fuer die Herstellung von Klassen schematischer Darstellungen schufen. Dabei spielen zwei Aspekte eine grosse Rolle. Einmal sollen diese Editoren in der Lage sein, dem Benutzer weitgehende grafische Unterstuetzungen zu geben. Das dabei erreichte Ziel beinhaltet eine umfassende automatisierte Layoutunterstuetzung beim Erstellen von grafischen Dokumenten. Ferner ist dafuer zu sorgen, dass die entstehenden Zeichnungen zu strukturell korrekten

  9. Development of a dynamic short-term test method for installed thermal solar systems; Entwicklung eines dynamischen Kurzzeittestverfahrens fuer installierte thermische Solaranlagen

    Energy Technology Data Exchange (ETDEWEB)

    Beikircher, T.; Gut, M.; Kronthaler, P.; Oberdorf, C.; Schoelkopf, W. [Bayerisches Zentrum fuer Angewandte Energieforschung, Muenchen (Germany). Abt. Solarthermie und Biomasse

    1998-12-31

    A short-term test method for in-situ measurement of the collector field, pipelines and heat exchanger of large-surface solar systems was developed at ZAE Bayern, together with the necessary technical systems (mobile acquisition of meteorological data via telemetering, non-invasive surface temperature sensors and ultrasonic volume flow measuring instruments). Dynamic measurements were made for 11 days in a large-surface solar system of the ``Solarthermie 2000`` programme using the new measuring system. In order to optimize the evaluation procedure, the plant was simulated, and the influence of different models and operating conditions during the measurements on the prediction quality was investigated in detail. On this basis, it was possible to predict the long-term collector yield of the ZfS Hilden, which was measured for a period of 7 months, with an error of less than 5%. The method will be validated in two further industrial-scale systems. [Deutsch] Am ZAE Bayern wurde ein Kurzzeittestverfahren zur insitu-Vermessung des Kollektorkreises (Kollektorfeld, Rohrleitungen, Waermetauscher) grosser Solaranlagen entwickelt. Hierzu wurde eine der Aufgabenstellung angepasste Messtechnik entwickelt (Mobile meteorologische Datenerfassung mit Funkbetrieb, nicht-invasive Oberflaechen-Temperaturfuehler und Ultraschall-Volumenstrommessgeraete). Der Kollektorkreis einer grossen Solaranlage aus dem Programm Solarthermie 2000 wurde dynamisch ueber 11 Tage (29.10.-8.11.1997) mit der neuen Messtechnik vermessen. Zur Entwicklung eines geeigneten Auswerteverfahrens wurde die Anlage simulatorisch abgebildet und der Einfluss verschiedener Modellansaetze und der Betriebsbedingungen waehrend des Mess- und Vorhersagezeitraums auf die Vorhersageguete im Detail untersucht. Mit dem entwickelten Verfahren konnte aus der dynamischen Kurzzeitvermessung der in einer Langzeitmessung der ZfS Hilden ueber 7 Monate ermittelte Kollektorertrag nach dem solaren Waermetauscher auf deutlich besser als 5

  10. Development with DMU. Options in the modern product life cycle; Entwicklung mit DMU. Moeglichkeiten im modernen Produktlebenszyklus

    Energy Technology Data Exchange (ETDEWEB)

    Hoehn, H.; Moser, H. [Competent Engineering GmbH, Graz (Austria)

    2005-02-01

    In this contribution, the Graz-based development company Competent Engineering outlines the advantages of digital mock-ups for efficient product development. The focus is on a uniform product and data structure that is to ensure early availability of DMU for all stages of the product life cycle. (orig.) [German] Der Grazer Entwicklungsdienstleister Competent Engineering beschreibt in diesem Beitrag anhand der Entwicklung eines Ottomotors, welche Vorteile der Einsatz von Digital Mock-Ups fuer eine effiziente Produktentwicklung hat. Besondere Bedeutung hat dabei eine moeglichst durchgaengige Produkt- und Datenstruktur, um eine fruehe Verfuegbarkeit der DMUs fuer alle Bereiche innerhalb des Produktlebenszyklus zu ermoeglichen. (orig.)

  11. Grey relational clustering associated with CAPRI applied to FPGA placement

    Science.gov (United States)

    Wu, Jan-Ou; Fan, Yang-Hsin; Wang, San-Fu

    2016-04-01

    Grey relational clustering is used to minimise wire length during field programmable gate arrays (FPGA) placement and routing. The proposed Grey Relational Clustering Apply to Placement (GRAP) algorithm combines grey relational clustering and convex assigned placement for regular ICs method to construct a placement netlist, which was successfully used to solve the problem of minimising wire length in an FPGA placement. Upon calculating the grey relational grade, GRAP can rank the sequence and analyse the minimal distance in configuration logic blocks based on the grey relational sequence and combined connection-based approaches. The experimental results demonstrate that the GRAP effectively compares the Hibert, Z and Snake with bounding box (BB) cost function in the space-filling curve. The GRAP improved BB cost by 0.753%, 0.324% and 0.096% for the Hilbert, Z and Snake, respectively. This study also compares the critical path with the space-filling curve. The GRAP approach improved the critical path for Snake by 1.3% in the space-filling curve; however, the GRAP increased critical path wire by 1.38% and 0.03% over that of the Hilbert and Z of space-filling curve, respectively.

  12. Optimizing latency in Xilinx FPGA implementations of the GBT

    CERN Document Server

    Muschter, S; Bohm, C; Cachemiche, J-P; Baron, S

    2010-01-01

    The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation {[}3]. This code was optimized for resource utilization {[}4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The la...

  13. Smart Capture Modules for Direct Sensor-to-FPGA Interfaces.

    Science.gov (United States)

    Oballe-Peinado, Óscar; Vidal-Verdú, Fernando; Sánchez-Durán, José A; Castellanos-Ramos, Julián; Hidalgo-López, José A

    2015-12-16

    Direct sensor-digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor.

  14. Smart Capture Modules for Direct Sensor-to-FPGA Interfaces

    Directory of Open Access Journals (Sweden)

    Óscar Oballe-Peinado

    2015-12-01

    Full Text Available Direct sensor–digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor.

  15. An FPGA Implementation of Secured Steganography Communication System

    Directory of Open Access Journals (Sweden)

    Ahlam Mahmood

    2014-04-01

    Full Text Available Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.  In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.  This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secure data transmission applications

  16. An FPGA based Preprocessor for the ALICE high level trigger

    Energy Technology Data Exchange (ETDEWEB)

    Alt, T.; Lindenstruth, V.; Painke, F.; Peschek, J.; Steinbeck, T.M. [Kirchhoff Inst. of Physics, Ruprecht-Karls-Univ., Heidelberg (Germany)

    2007-07-01

    The H-RORC (High Level Trigger ReadOut Receiver Card) is an FPGA based PCI card designed to receive raw detector data from ALICE, transfer it into the online processing framework of the HLT cluster farm and transmit the processed data out of the HLT to the DAQ. Each RORC can be equipped with two optical receiver/transmitter units and transfer up to 400 Mbyte/s via PCI. For online processing in hardware the Virtex4 LX40 FPGA is supported by four independent modules of fast DDR-SDRAM providing up to 512 Mbyte total storage at a bandwidth of 2.3 Gbyte/s and two fast serial, full-duplex links which can be used as an direct interconnect in order to exchange data between several RORCs. In replay mode the onboard memory can be loaded with real or simulated events thus giving a real-time test-bench for the HLT framework. A special configuration scheme suits the requirements of a cluster environment and allows a safe and remote upgrade of the firmware. The H-RORC was used successfully in the first time run of the HLT during the TPC commissioning 2006. (orig.)

  17. A Sea-of-Gates Style FPGA Placement Algorithm

    Directory of Open Access Journals (Sweden)

    Kalapi Roy

    1996-01-01

    Full Text Available Field Programmable Gate Arrays (FPGAs have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool developed specifically for this architecture.

  18. An FPGA Implementation of Secured Steganography Communication System

    Directory of Open Access Journals (Sweden)

    Ahlam Fadhil Mahmood

    2013-04-01

    Full Text Available     Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.        In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.      This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secures data transmission applications

  19. Design of extensible meteorological data acquisition system based on FPGA

    Science.gov (United States)

    Zhang, Wen; Liu, Yin-hua; Zhang, Hui-jun; Li, Xiao-hui

    2015-02-01

    In order to compensate the tropospheric refraction error generated in the process of satellite navigation and positioning. Temperature, humidity and air pressure had to be used in concerned models to calculate the value of this error. While FPGA XC6SLX16 was used as the core processor, the integrated silicon pressure sensor MPX4115A and digital temperature-humidity sensor SHT75 are used as the basic meteorological parameter detection devices. The core processer was used to control the real-time sampling of ADC AD7608 and to acquire the serial output data of SHT75. The data was stored in the BRAM of XC6SLX16 and used to generate standard meteorological parameters in NEMA format. The whole design was based on Altium hardware platform and ISE software platform. The system was described in the VHDL language and schematic diagram to realize the correct detection of temperature, humidity, air pressure. The 8-channel synchronous sampling characteristics of AD7608 and programmable external resources of FPGA laid the foundation for the increasing of analog or digital meteorological element signal. The designed meteorological data acquisition system featured low cost, high performance, multiple expansions.

  20. Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform

    Directory of Open Access Journals (Sweden)

    Vishwa Seneviratne

    2017-07-01

    Full Text Available Antenna array-based multi-dimensional infinite-impulse response (IIR digital beamformers are employed in a multitude of radio frequency (RF applications ranging from electronically-scanned radar, radio telescopes, long-range detection and target tracking. A method to design 3D IIR beam filters using 2D IIR beam filters is described. A cascaded 2D IIR beam filter architecture is proposed based on systolic array architecture as an alternative for an existing radar application. Differential-form transfer function and polyphase structures are employed in the design to gain an increase in the speed of operation to gigahertz range. The feasibility of practical implementation of a 4-phase polyphase 2D IIR beam filter is explored. A digital hardware prototype is designed, implemented and tested using a ROACH-2 Field Programmable Gate Array (FPGA platform fitted with a Xilinx Virtex-6 SX475T FPGA chip and multi-input analog-to-digital converters (ADC boards set to a maximum sampling rate of 960 MHz. The article describes a method to build a 3D IIR beamformer using polyphase structures. A comparison of technical specifications of an existing radar application based on phased-array and the proposed 3D IIR beamformer is also explained to illustrate the proposed method to be a better alternative for such applications.

  1. A shared synapse architecture for efficient FPGA implementation of autoencoders.

    Science.gov (United States)

    Suzuki, Akihiro; Morie, Takashi; Tamukoh, Hakaru

    2018-01-01

    This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers' units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.

  2. A Correctness Verification Technique for Commercial FPGA Synthesis Tools

    International Nuclear Information System (INIS)

    Kim, Eui Sub; Yoo, Jun Beom; Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo

    2014-01-01

    Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

  3. Logic qualification of FPGA-based safety-related I and C systems

    International Nuclear Information System (INIS)

    Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

    2009-01-01

    We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

  4. An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

    International Nuclear Information System (INIS)

    Jung, Sejin; Kim, Eui-Sub; Yoo, Junbeom; Kim, Jang-Yeol; Choi, Jong Gyun

    2016-01-01

    Highlights: • All direct/indirect COTS SW should be dedicated. • FPGA synthesis tools are important for the safety of new digital I&Cs. • No standards/reports are yet available to deal with the indirect SW – FPGA synthesis tools. • This paper proposes a new evaluation/acceptance process and criteria for indirect SW. - Abstract: FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

  5. Development of genomic instability after irradiation; Entwicklung einer genomischen Instabilitaet nach Bestrahlung

    Energy Technology Data Exchange (ETDEWEB)

    Streffer, C. [Essen Univ. (Gesamthochschule) (Germany). Universitaetsklinikum

    2001-07-01

    It has been shown for various endpoints, both in vitro and in vivo, that genomic instability can be induced by low as well as by high LET radiation. Genomic instability in this case is not limited to a specific chromosome or gene. It can be passed on over many cell generations and in mammals can even be inherited to the next generation. It is capable of being induced in gametes. A dose dependence of the development of genomic instability has been found to exist in the range from 0.5 to 2.0 Gy. However, there are no data available in the low dose range. The mechanisms by which genomic instability is induced are still not understood at present. Various possibilities have been suggested. An understanding of these mechanisms will contribute to developing a deepened knowledge of processes such as stochastic radiation effects with multi-step mutation processes, and in particular carcinogenesis. It will facilitate the evaluation of radiation risks in the low-dose range. [German] Die Induktion einer genomischen Instabilitaet durch niedrige ebenso wie Hoch-LET-Strahlung ist fuer verschiedene Endpunkte gezeigt worden. Dieses ist sowohl in vitro als auch in vivo beobachtet worden. Die genomische Instabilitaet ist nicht auf ein spezifisches Chromosom oder Gen begrenzt. Sie kann ueber viele Zellgenerationen weitergegeben und auf die naechste Generation bei Saeugetieren vererbt werden. Eine Induktion in Keimzellen ist moeglich. Eine Dosisabhaengigkeit der Entwicklung genomischer Instabilitaet ist fuer den Dosisbereich von 0,5-2,0 Gy beobachtet worden. Daten im niedrigen Dosisbereich fehlen. Die Mechanismen der Induktion der genomischen Instabilitaet werden bisher nicht verstanden. Eine Anzahl verschiedener Moeglichkeiten ist vorgeschlagen worden. Die genomische Instabilitaet und das Verstaendnis der Mechanismen wird helfen, ein besseres Wissen ueber die Prozesse, wie stochastische Strahleneffekte mit Mehrschrittmutationsprozessen, besonders die Karzinogenese, zu entwickeln

  6. FPGA-Based Approach to Level-1 Track Finding at CMS for the HL-LHC

    CERN Document Server

    Bartz, Edward Hugo; Gershtein, Yury; Halkiadakis, Eva; Hildreth, Michael; Kyriacou, Savvas; Lannon, Kevin Patrick; Lefeld, Anthony James; Ryd, Anders Per Erik; Skinnari, Louise; Stone, Robert; Strohman, Charles Ralph; Tao, Zhengcheng; Winer, Brian; Wittich, Peter; Zientek, Margaret Eldridge

    2017-01-01

    During the High Luminosity LHC, to maintain a manageable trigger rate and achieve its physics goals, the CMS detector will need charged particle tracking at the hardware trigger level. The tracklet approach is a track-finding algorithm based on a road-search algorithm that has been implemented on commercially available FPGA technology. This algorithm has achieved high performance in track-finding and completes tracking within 3.4 $\\mu$s on a Xilinx Virtex-7 FPGA. An overview of the algorithm and its implementation on an FPGA is given, results are shown from a demonstrator test stand and system performance studies are presented.

  7. High Performance and Energy Efficient Traffic Light Controller Design Using FPGA

    DEFF Research Database (Denmark)

    Pandey, Sujeet; Shrivastav, Vivek Kumar; Sharma, Rashmi

    2017-01-01

    In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA...... and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER...

  8. Development of an FPGA-Based Motion Control IC for Caving Machine

    Directory of Open Access Journals (Sweden)

    Chiu-Keng Lai

    2014-03-01

    Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

  9. Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    International Nuclear Information System (INIS)

    Pappas, I; Kalenteridis, V; Vassiliadis, N; Pournara, H; Siozios, K; Koutroumpezis, G; Tatas, K; Nikolaidis, S; Siskos, S; Soudris, D J; Thanailakis, A

    2005-01-01

    A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 μm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools

  10. Carry-chain propagation delay impacts on resolution of FPGA-based TDC

    International Nuclear Information System (INIS)

    Dong Lei; Yang Junfeng; Song Kezhu

    2014-01-01

    The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy. (authors)

  11. Development of a two-phase, two-component jet pump refrigerator for utilization of low-temperature solar heat. Final report; Entwicklung einer Zweiphasen-/Zweikomponenten-Strahlpumpenkaelteanlage zur Nutzung solarer Niedertemperaturwaerme. Abschlussbericht

    Energy Technology Data Exchange (ETDEWEB)

    Mostofizadeh, C.; Bohne, D.

    2001-08-01

    A solar refrigerator for air conditioning and cooling was developed. The key component is a two-phase, two-component jet pump with ammonia and water as working fluid. Both the pump flow and the suction flow can be two-phase flows. This way, the advantages of both the absorption and the compression principle will be utilized, and a compact size will be achieved. Upon termination of the calculations, the function of the pump will be investigated in a 0 W pilot plant. For this, various geometries were calculated and tested for their potential efficiencies. A prototype will be constructed on the basis of the results. [German] Das Ziel des Vorhabens besteht in der Entwicklung einer solarbetriebenen Kaelteanlage fuer Klimatisierungs- und Kuehlungszwecke. Die Hauptkomponente der Kaelteanlage ist eine Zweiphasen-/Zweikomponenten-Strahlpumpe, die mit dem Arbeitsgemisch Ammoniak/Wasser betrieben wird. Sowohl der Treib- als auch der Saugstrom koennen zweiphasig sein. Dadurch sollen einerseits die Vorteile des Absorptions- und des Kompressionsprinzips miteinander verknuepft und andererseits ein kompakter Aufbau erreicht werden. Nach Abschluss der thermodynamischen und kinetischen Berechnungen soll die Funktion der Zweiphasen-/Zweikomponenten-Strahlpumpe mit Hilfe einer Pilotanlage mit ca. 20 kW Kaelteleistung untersucht werden. Dazu werden nach Vorausberechnungen verschiedene Geometrien in Bezug auf erzielbare Wirkungsgrade getestet. Die Ergebnisse bilden die Basis fuer den Bau eines Prototyps. (orig.)

  12. Controlador empotrado en FPGA para Sistema Inteligente de Transporte

    Directory of Open Access Journals (Sweden)

    Alejandro José Cabrera Sarmiento

    2011-11-01

    Full Text Available 1024x768 Normal 0 21 false false false ES X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;} En el presente trabajo se expone la concepción, desarrollo e implementación de un controlador empotrado en un FPGA de Xilinx para ser utilizado en un Sistema Inteligente de Transporte (SIT. La estructura hardware del controlador está basada en la utilización de diversos módulos de propiedad intelectual del sistema de procesamiento MicroBlaze y el soporte de software está basado en la utilización del sistema operativo Petalinux. El controlador empotrado dispone de interfaces Ethernet, USB, UART, SPI e I2C para la comunicación con los diferentes niveles jerárquicos del SIT. Ha sido implementado sobre una placa de desarrollo basada en un FPGA Spartan3E de 1.200 k compuertas, ocupando un 59% de sus recursos configurables. El resto de los recursos disponibles en el FPGA permite, además de la posible actualización del controlador, la implementación hardware de algoritmos que requieren una alta velocidad de procesamiento.

  13. Image denoising method based on FPGA in digital video transmission

    Science.gov (United States)

    Xiahou, Yaotao; Wang, Wanping; Huang, Tao

    2017-11-01

    In the image acquisition and transmission link, due to the acquisition of equipment and methods, the image would suffer some different degree of interference ,and the interference will reduce the quality of image which would influence the subsequent processing. Therefore, the image filtering and image enhancement are particularly important.The traditional image denoising algorithm smoothes the image while removing the noise, so that the details of the image are lost. In order to improve image quality and save image detail, this paper proposes an improved filtering algorithm based on edge detection, Gaussian filter and median filter. This method can not only reduce the noise effectively, but also the image details are saved relatively well, and the FPGA implementation scheme of this filter algorithm is also given in this paper.

  14. Implementation of FPGA-Based Diverse Protection System

    Energy Technology Data Exchange (ETDEWEB)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

    2015-10-15

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

  15. A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

    Directory of Open Access Journals (Sweden)

    Kevin R. Townsend

    2015-01-01

    Full Text Available On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

  16. Validation of a Real-time AVS Encoder on FPGA

    Directory of Open Access Journals (Sweden)

    Qun Fang Yuan

    2014-01-01

    Full Text Available A whole I frame AVS real-time video encoder is designed and implemented on FPGA platform in this paper. The system uses the structure of the flow calculation, coupled with a dual-port RAM memory between/among the various functional modules. Reusable design and pipeline design are used to optimize various encoding module and to ensure the efficient operation of the pipeline. Through the simulation of ISE software and the verification of Xilinx Vritex-4 pro platform, it can be seen that the highest working frequency can be up to 110 MHz, meeting the requirements of the whole I frame real- time encoding of AVS in CIF resolution.

  17. Implementace OFDM demodulátoru v obvodu FPGA

    OpenAIRE

    Solar, Pavel

    2010-01-01

    Diplomová práce stručně rozebírá princip OFDM modulace, možnosti synchronizace a odhadu frekvenční charakteristiky kanálu v OFDM. Je vytvořen jednoduchý model OFDM systému v programu MATLAB. Kombinací schématického popisu a popisu v jazyce VHDL je vytvořen ve vývojovém prostředí ISE behaviorální popis OFDM demodulátoru pro implementaci do FPGA. The master's thesis briefly analyses the principle of OFDM modulation, possibilities of the synchronization and channel estimation in OFDM. The sim...

  18. FPGA implementation of predictive degradation model for engine oil lifetime

    Science.gov (United States)

    Idros, M. F. M.; Razak, A. H. A.; Junid, S. A. M. Al; Suliman, S. I.; Halim, A. K.

    2018-03-01

    This paper presents the implementation of linear regression model for degradation prediction on Register Transfer Logic (RTL) using QuartusII. A stationary model had been identified in the degradation trend for the engine oil in a vehicle in time series method. As for RTL implementation, the degradation model is written in Verilog HDL and the data input are taken at a certain time. Clock divider had been designed to support the timing sequence of input data. At every five data, a regression analysis is adapted for slope variation determination and prediction calculation. Here, only the negative value are taken as the consideration for the prediction purposes for less number of logic gate. Least Square Method is adapted to get the best linear model based on the mean values of time series data. The coded algorithm has been implemented on FPGA for validation purposes. The result shows the prediction time to change the engine oil.

  19. An FPGA-based rapid prototyping platform for wavelet coprocessors

    Science.gov (United States)

    Vera, Alonzo; Meyer-Baese, Uwe; Pattichis, Marios

    2007-04-01

    MatLab/Simulink-based design flows are being used by DSP designers to improve time-to-market of FPGA implementations. 1 Commonly, digital signal processing cores are integrated in an embedded system as coprocessors. Existing CAD tools do not fully address the integration of a DSP coprocessor into an embedded system design. This integration might prove to be time consuming and error prone. It also requires that the DSP designer has an excellent knowledge of embedded systems and computer architecture details. We present a prototyping platform and design flow that allows rapid integration of embedded systems with a wavelet coprocessor. The platform comprises of software and hardware modules that allow a DSP designer a painless integration of a coprocessor with a PowerPC-based embedded system. The platform has a wide range of applications, from industrial to educational environments.

  20. FPGA-based protein sequence alignment : A review

    Science.gov (United States)

    Isa, Mohd. Nazrin Md.; Muhsen, Ku Noor Dhaniah Ku; Saiful Nurdin, Dayana; Ahmad, Muhammad Imran; Anuar Zainol Murad, Sohiful; Nizam Mohyar, Shaiful; Harun, Azizi; Hussin, Razaidi

    2017-11-01

    Sequence alignment have been optimized using several techniques in order to accelerate the computation time to obtain the optimal score by implementing DP-based algorithm into hardware such as FPGA-based platform. During hardware implementation, there will be performance challenges such as the frequent memory access and highly data dependent in computation process. Therefore, investigation in processing element (PE) configuration where involves more on memory access in load or access the data (substitution matrix, query sequence character) and the PE configuration time will be the main focus in this paper. There are various approaches to enhance the PE configuration performance that have been done in previous works such as by using serial configuration chain and parallel configuration chain i.e. the configuration data will be loaded into each PEs sequentially and simultaneously respectively. Some researchers have proven that the performance using parallel configuration chain has optimized both the configuration time and area.

  1. A minimal SATA III Host Controller based on FPGA

    Science.gov (United States)

    Liu, Hailiang

    2018-03-01

    SATA (Serial Advanced Technology Attachment) is an advanced serial bus which has a outstanding performance in transmitting high speed real-time data applied in Personal Computers, Financial Industry, astronautics and aeronautics, etc. In this express, a minimal SATA III Host Controller based on Xilinx Kintex 7 serial FPGA is designed and implemented. Compared to the state-of-art, registers utilization are reduced 25.3% and LUTs utilization are reduced 65.9%. According to the experimental results, the controller works precisely and steady with the reading bandwidth of up to 536 MB per second and the writing bandwidth of up to 512 MB per second, both of which are close to the maximum bandwidth of the SSD(Solid State Disk) device. The host controller is very suitable for high speed data transmission and mass data storage.

  2. A FPGA Implementation of the CAR-FAC Cochlear Model

    Directory of Open Access Journals (Sweden)

    Ying Xu

    2018-04-01

    Full Text Available This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC cochlear model. The CAR part simulates the basilar membrane's (BM response to sound. The FAC part models the outer hair cell (OHC, the inner hair cell (IHC, and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  3. A FPGA Implementation of the CAR-FAC Cochlear Model.

    Science.gov (United States)

    Xu, Ying; Thakur, Chetan S; Singh, Ram K; Hamilton, Tara Julia; Wang, Runchun M; van Schaik, André

    2018-01-01

    This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  4. A Chip of Counter and Parallel Interface Port Using FPGA

    International Nuclear Information System (INIS)

    Setyadi WS; Dewita Triyono

    2002-01-01

    A chip contained two 16 bit counters and parallel interface port has been constructed by using Field Programmable Gate Array (FPGA) made by Altera. One of the aim of this activity was to replace the interfacing card which were using Programmable Logic Device (PLD) and others supporting components placed on personal computer expansion slot ISA or EISA, with a compatible Chip. The result was a 44 pin Chip with a single 5 V supply. The experiment test showed that the input output ports were working properly. The Simulation timing showed suitably as the requirement. The Chip was designed for the instruments which needed a counter, timer and connected to the computer as data acquisition and control. The advantage of this Chip was the compatibility of the pin parallel port standard, it can be connected with any computers type. (author)

  5. FPGA Implementation of Real-Time Ethernet for Motion Control

    Directory of Open Access Journals (Sweden)

    Chen Youdong

    2013-01-01

    Full Text Available This paper provides an applicable implementation of real-time Ethernet named CASNET, which modifies the Ethernet medium access control (MAC to achieve the real-time requirement for motion control. CASNET is the communication protocol used for motion control system. Verilog hardware description language (VHDL has been used in the MAC logic design. The designed MAC serves as one of the intellectual properties (IPs and is applicable to various industrial controllers. The interface of the physical layer is RJ45. The other layers have been implemented by using C programs. The real-time Ethernet has been implemented by using field programmable gate array (FPGA technology and the proposed solution has been tested through the cycle time, synchronization accuracy, and Wireshark testing.

  6. A Digitalized Silicon Microgyroscope Based on Embedded FPGA

    Science.gov (United States)

    Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

    2012-01-01

    This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system. PMID:23201990

  7. FPGA Implementations of Bireciprocal Lattice Wave Discrete Wavelet Filter Banks

    Directory of Open Access Journals (Sweden)

    Jassim M. Abdul-Jabbar

    2012-06-01

    Full Text Available In this paper, a special type of IIR filter banks; that is the bireciprocal lattice wave digital filter (BLWDF bank, is presented to simulate scaling and wavelet functions of six-level wavelet transform. 1st order all-pass sections are utilized for the realization of such filter banks in wave lattice structures. The resulting structures are a bireciprocal lattice wave discrete wavelet filter banks (BLW-DWFBs. Implementation of these BLW-DWFBs are accomplished on Spartan-3E FPGA kit. Implementation complexity and operating frequency characteristics of such discrete wavelet 5th order filter bank is proved to be comparable to the corresponding characteristics of the lifting scheme implementation of Bio. 5/3 wavelet filter bank. On the other hand, such IIR filter banks possess superior band discriminations and perfect roll-off frequency characteristics when compared to their Bio. 5/3 wavelet FIR counterparts.

  8. Time-delayed chameleon: Analysis, synchronization and FPGA implementation

    Science.gov (United States)

    Rajagopal, Karthikeyan; Jafari, Sajad; Laarem, Guessas

    2017-12-01

    In this paper we report a time-delayed chameleon-like chaotic system which can belong to different families of chaotic attractors depending on the choices of parameters. Such a characteristic of self-excited and hidden chaotic flows in a simple 3D system with time delay has not been reported earlier. Dynamic analysis of the proposed time-delayed systems are analysed in time-delay space and parameter space. A novel adaptive modified functional projective lag synchronization algorithm is derived for synchronizing identical time-delayed chameleon systems with uncertain parameters. The proposed time-delayed systems and the synchronization algorithm with controllers and parameter estimates are then implemented in FPGA using hardware-software co-simulation and the results are presented.

  9. Rigid Molecule Docking: FPGA Reconfiguration for Alternative Force Laws

    Directory of Open Access Journals (Sweden)

    VanCourt Tom

    2006-01-01

    Full Text Available Molecular docking is one of the primary computational methods used by pharmaceutical companies to try to reduce the cost of drug discovery. A common docking technique, used for low-resolution screening or as an intermediate step, performs a three-dimensional correlation between two molecules to test for favorable interactions between them. We extend our previous work on FPGA-based docking accelerators, using reconfigurability for customization of the physical laws and geometric models that describe molecule interaction. Our approach, based on direct summation, allows straightforward combination of multiple forces and enables nonlinear force models; the latter, in particular, are incompatible with the transform-based techniques typically used. Our approach has the further advantage of supporting spatially oriented values in molecule models, as well as the detection of multiple positions representing favorable interactions. We report performance measurements on several different models of chemical behavior and show speedups of from to over a PC.

  10. Power Efficient Gurumukhi Unicode Reader Design and Implementation on FPGA

    DEFF Research Database (Denmark)

    Kaur, Amanpreet; Singh, Sunny; Pandey, Bishwajeet

    2017-01-01

    Gurumukhi is found to be the most widely used language of Pakistan, and it is ranked 3rd in Canada, 7th in India and almost 4th most spoken language in U.K. This Unicode Reader is cost effective solution for learning as well as understanding the Punjabi language by the people across the globe .Th...... Impedance) logic families to make this design more energy efficient. It is concluded that using LVDCI_DV2_15 rather than SSTL18_II_DCI, the total power can be saved up to 51.22% with the device operating at a frequency of 1MHz.......) and is implemented on Virtex-6 FPGA on Xilinx software. This GUR design is tested on different frequencies by applying frequency scaling techniques .The reader is also observed on different IO Standards of two logic families i.e. on SSTL (Stub-Series Terminated Logic) and LVDCI (Low Voltage Digitally Controlled...

  11. Design and tuning of FPGA implementations of neural networks

    Science.gov (United States)

    Clare, Peter J. C.; Gulley, J. W.; Hickman, Duncan; Smith, Moira I.

    1997-06-01

    Artificial neural network (ANN) algorithms are applicable in a variety of roles for image processing in infrared search and track (IRST) systems. Achieving a high throughput is a key objective in developing ANNs for processing large numbers of pixels at high frame rates. Previous work has investigated the use of a neural core supported by configurable logic to achieve a versatile technology applicable to a variety of systems. The implementation of multi-layer perceptron (MLP) ANNs, using field programmable gate array (FPGA) technology to ensure upgradability and reconfigurability, is the focus of this research. Approximations to the MLP algorithms are needed to ensure that a high throughput can be achieved with a sufficiently low gate count.

  12. improvement of digital image watermarking techniques based on FPGA implementation

    International Nuclear Information System (INIS)

    EL-Hadedy, M.E

    2006-01-01

    digital watermarking provides the ownership of a piece of digital data by marking the considered data invisibly or visibly. this can be used to protect several types of multimedia objects such as audio, text, image and video. this thesis demonstrates the different types of watermarking techniques such as (discrete cosine transform (DCT) and discrete wavelet transform (DWT) and their characteristics. then, it classifies these techniques declaring their advantages and disadvantages. an improved technique with distinguished features, such as peak signal to noise ratio ( PSNR) and similarity ratio (SR) has been introduced. the modified technique has been compared with the other techniques by measuring heir robustness against differ attacks. finally, field programmable gate arrays (FPGA) based implementation and comparison, for the proposed watermarking technique have been presented and discussed

  13. Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping

    Energy Technology Data Exchange (ETDEWEB)

    Ceriani, Marco; Palermo, Gianluca; Secchi, Simone; Tumeo, Antonino; Villa, Oreste

    2013-04-29

    We present a prototype of a multi-core architecture implemented on FPGA, designed to enable efficient execution of irregular applications on distributed shared memory machines, while maintaining high performance on regular workloads. The architecture is composed of off-the-shelf soft-core cores, local interconnection and memory interface, integrated with custom components that optimize it for irregular applications. It relies on three key elements: a global address space, multithreading, and fine-grained synchronization. Global addresses are scrambled to reduce the formation of network hot-spots, while the latency of the transactions is covered by integrating an hardware scheduler within the custom load/store buffers to take advantage from the availability of multiple executions threads, increasing the efficiency in a transparent way to the application. We evaluated a dual node system irregular kernels showing scalability in the number of cores and threads.

  14. Real-time particle image velocimetry based on FPGA technology

    International Nuclear Information System (INIS)

    Iriarte Munoz, Jose Miguel

    2008-01-01

    Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach. [es

  15. Hardware Implementation Of Line Clipping A lgorithm By Using FPGA

    Directory of Open Access Journals (Sweden)

    Amar Dawod

    2013-04-01

    Full Text Available The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance the clipping is still a bottleneck of any graphical system. So its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA. The designed hardware unit consists of two parts : the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the  designed unit is capable of clipping (232524 line segments per second.       

  16. FPGA IMPLEMENTATION OF ROAD NETWORK EXTRACTION USING MORPHOLOGICAL OPERATOR

    Directory of Open Access Journals (Sweden)

    Sujatha Chinnathevar

    2016-07-01

    Full Text Available In the remote sensing analysis, automatic extraction of road network from satellite or aerial images is the most needed approach for efficient road database creation, refinement, and updating. Mathematical morphology is a tool for extracting the features of an image that are useful in the representation and description of region shape. Morphological operator plays a significant role in the extraction of road network from satellite images. Most of the image processing algorithms need to handle large amounts of data, high repeatability, and general software is relatively slow to implement, so the system cannot achieve real-time requirements. In this paper, field programmable gate array (FPGA architecture designed for automatic extraction of road centerline using morphological operator is proposed. Based on simulation and implementation, results are discussed in terms of register transfer level (RTL design, FPGA editor and resource estimation. For synthesis and implementation of the above architecture, Spartan 3 XC3S400TQ144-4 device is used. The hardware implementation results are compared with software implementation results. The performance of proposed method is evaluated by comparing the results with ground truth road map as reference data and performance measures such as completeness, correctness and quality are calculated. In the software imple-mentation, the average value of completeness, correctness, and quality of various images are 90%, 96%, and 87% respectively. In the hardware implementation, the average value of completeness, correctness, and quality of various images are 87%, 94%, and 85% respectively. These measures prove that the proposed work yields road network very closer to reference road map.

  17. An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator

    Directory of Open Access Journals (Sweden)

    Runchun M. Wang

    2018-04-01

    Full Text Available This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons. This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

  18. Advanced Image Processing Package for FPGA-Based Re-Programmable Miniature Electronics

    National Research Council Canada - National Science Library

    Ovod, Vladimir I; Baxter, Christopher R; Massie, Mark A; McCarley, Paul L

    2005-01-01

    .... An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical background...

  19. Efficient and side-channel resistant authenticated encryption of FPGA bitstreams

    DEFF Research Database (Denmark)

    Bogdanov, Andrey; Moradi, Amir; Yalcin, Tolga

    2013-01-01

    State-of-the-art solutions for FPGA bitstream protection rely on encryption and authentication of the bitstream to both ensure its confidentiality, thwarting unauthorized copying and reverse engineering, and prevent its unauthorized modification, maintaining a root of trust in the field. Adequate...... protection of the FPGA bitstream is of paramount importance to sustain the central functionality of dynamic reconfiguration in a hostile environment. In this work, we propose a new solution for authenticated encryption (AE) tailored for FPGA bitstream protection. It is based on the recent proposal presented...... AE modes of operation with the same countermeasure. We conclude that the deployment of dedicated AE schemes such as ALE significantly facilitates the real-world efficiency and security of FPGA bitstream protection in practice: Not only our solution enables authenticated encryption for bitstream...

  20. Dynamic Reconfiguration Of FPGA Nodes In A Distributed Computing System: A Preliminary Investigation

    National Research Council Canada - National Science Library

    Nixon, Patrick

    2002-01-01

    This report results from a contract tasking Trinity College, Dublin to investigate a specialized portion of a heterogeneous information system, specifically, Field Programmable Gate Array (FPGA)-based nodes...

  1. 160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA

    Directory of Open Access Journals (Sweden)

    Truong Kevin

    2007-06-01

    Full Text Available Abstract Background To infer homology and subsequently gene function, the Smith-Waterman (SW algorithm is used to find the optimal local alignment between two sequences. When searching sequence databases that may contain hundreds of millions of sequences, this algorithm becomes computationally expensive. Results In this paper, we focused on accelerating the Smith-Waterman algorithm by using FPGA-based hardware that implemented a module for computing the score of a single cell of the SW matrix. Then using a grid of this module, the entire SW matrix was computed at the speed of field propagation through the FPGA circuit. These modifications dramatically accelerated the algorithm's computation time by up to 160 folds compared to a pure software implementation running on the same FPGA with an Altera Nios II softprocessor. Conclusion This design of FPGA accelerated hardware offers a new promising direction to seeking computation improvement of genomic database searching.

  2. Extreme environment, rad hard, high performance, low power FPGA for space applications, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — To enable NASA's next-generation missions, there is a critical need for a reconfigurable FPGA that can withstand the wide temperatures ranges and radiation of the...

  3. Variable Correlation Digital Noise Source on FPGA — A Versatile Tool for Debugging Radio Telescope Backends

    Science.gov (United States)

    Buch, Kaushal D.; Gupta, Yashwant; Ajith Kumar, B.

    Contemporary wideband radio telescope backends are generally developed on Field Programmable Gate Arrays (FPGA) or hybrid (FPGA+GPU) platforms. One of the challenges faced while developing such instruments is the functional verification of the signal processing backend at various stages of development. In the case of an interferometer or pulsar backend, the typical requirement is for one independent noise source per input, with provision for a common, correlated signal component across all the inputs, with controllable level of correlation. This paper describes the design of a FPGA-based variable correlation Digital Noise Source (DNS), and its applications to built-in testing and debugging of correlators and beamformers. This DNS uses the Central Limit Theorem-based approach for generation of Gaussian noise, and the architecture is optimized for resource requirements and ease of integration with existing signal processing blocks on FPGA.

  4. A FPGA Approach in a Motorised Linear Stage Remote Controlled Experiment

    Directory of Open Access Journals (Sweden)

    Stamen Gadzhanov

    2013-04-01

    Full Text Available In recent years, an advanced motion control software for rapid development has been introduced by National Instruments, accompanied by innovative and improved FPGA-based hardware platforms. Compared to the well-known standard NI DAQ PCI/USB board solutions, this new approach offers robust stability in a deterministic real-time environment combined with the highest possible performance and re-configurability of the FPGA core. The NI Compact RIO (cRIO Real Time Controller utilises two distinctive interface modes of functionality: Scan and FPGA modes. This paper presents an application of a motion control flexible workbench based on the FPGA module, and analyses the advantages and disadvantages in comparison to another approach - the LabVIEW NI SoftMotion module run in scan interface mode. The workbench replicates real industrial applications and is very useful for experimentation with Brushless DC/ Permanent Magnet Synchronous motors and drives, and feedback devices.

  5. Timing measurements of some tracking algorithms and suitability of FPGA's to improve the execution speed

    CERN Document Server

    Khomich, A; Kugel, A; Männer, R; Müller, M; Baines, J T M

    2003-01-01

    Some of track reconstruction algorithms which are common to all B-physics channels and standard RoI processing have been tested for execution time and assessed for suitability for speed-up by using FPGA coprocessor. The studies presented in this note were performed in the C/C++ framework, CTrig, which was the fullest set of algorithms available at the time of study For investigation of possible speed-up of algorithms most time consuming parts of TRT-LUT was implemented in VHDL for running in FPGA coprocessor board MPRACE. MPRACE (Reconfigurable Accelerator / Computing Engine) is an FPGA-Coprocessor based on Xilinx Virtex-2 FPGA and made as 64Bit/66MHz PCI card developed at the University of Mannheim. Timing measurements results for a TRT Full Scan algorithm executed on the MPRACE are presented here as well. The measurement results show a speed-up factor of ~2 for this algorithm.

  6. Innovative approach to implementation of FPGA-based NPP instrumentation and control systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Siora, Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper. (author)

  7. Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

    Directory of Open Access Journals (Sweden)

    He Chen

    2011-12-01

    Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

  8. Rad-Hard and ULP FPGA with "Full" Functionality, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

  9. A natural-color mapping for single-band night-time image based on FPGA

    Science.gov (United States)

    Wang, Yilun; Qian, Yunsheng

    2018-01-01

    A natural-color mapping for single-band night-time image method based on FPGA can transmit the color of the reference image to single-band night-time image, which is consistent with human visual habits and can help observers identify the target. This paper introduces the processing of the natural-color mapping algorithm based on FPGA. Firstly, the image can be transformed based on histogram equalization, and the intensity features and standard deviation features of reference image are stored in SRAM. Then, the real-time digital images' intensity features and standard deviation features are calculated by FPGA. At last, FPGA completes the color mapping through matching pixels between images using the features in luminance channel.

  10. Energy report for Bavaria, 1996/97. Data on the development of the Bavarian energy industry, with an energy balance; Energiebericht Bayern 1996/97. Daten zur Entwicklung der bayerischen Energiewirtschaft mit Energiebilanz

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1998-04-01

    The report presents the energy balance for Bavaria and provides information on: Bavarian energy industry; structure and development of primary and end-use energy consumption; situation and development of energy sources (electricity, gas, mineral oil, coal, district heating). (orig.) [Deutsch] Der Bericht enthaelt die Energiebilanz Bayern fuer das Berichtsjahr und bietet Informationen zur Energiewirtschaft in Bayern, zur Struktur und Entwicklung des Primaer- und Endenergieverbrauchs und zur Situation und Entwicklung bei den einzelnen Energietraegern (Elektrizitaet, Gas, Mineraloel, Kohle, Fernwaerme). (orig.)

  11. Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Hegner, Jonas Stenbæk; Sindholt, Joakim; Nannarelli, Alberto

    2012-01-01

    Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation...... to the execution on a CPU. The experimental results show that impressive results, in terms of speed-up and energy savings, can be obtained by using FPGA-based accelerators at expenses of a longer development time....

  12. Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Jain, Vishal; Sharma, Rashmi

    2017-01-01

    In this work, we are going to analyze the effect of main supply voltage, auxiliary supply voltage, local voltage of different power bank, and supply voltage in GTX transceiver and BRAM on power dissipation of our FIR design using Verilog during implementation on 28nm FPGA. We have also taken three.......33%, 86%, 90.67%, 65.33%, 52%, and 48.67% reduction in IO power dissipation of FIR Filter design on CSG324 package of Artix-7 FPGA family....

  13. Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine

    DEFF Research Database (Denmark)

    El-Sayed, Mohammad; Koch, Peter; Le Moullec, Yannick

    2015-01-01

    We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full......-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz....

  14. Fabrication and Benchmarking of a Stratix V FPGA with Monolithic Integrated Microfluidic Cooling

    Science.gov (United States)

    2017-03-01

    heat sink directly into the silicon die , conductive thermal resistance between the heat source and heat sink is minimized. Figure 1. (a...hypothetical high performance air cooled heat sink would Figure 6. Maximum FPGA clock speed without glitches vs. maximum die temperature have a...representing the heat generating circuitry. In this work, a micropin-fin heat sink is etched into the back side of an Altera Stratix V FPGA, built

  15. FPGA hardware acceleration for high performance neutron transport computation based on agent methodology - 318

    International Nuclear Information System (INIS)

    Shanjie, Xiao; Tatjana, Jevremovic

    2010-01-01

    The accurate, detailed and 3D neutron transport analysis for Gen-IV reactors is still time-consuming regardless of advanced computational hardware available in developed countries. This paper introduces a new concept in addressing the computational time while persevering the detailed and accurate modeling; a specifically designed FPGA co-processor accelerates robust AGENT methodology for complex reactor geometries. For the first time this approach is applied to accelerate the neutronics analysis. The AGENT methodology solves neutron transport equation using the method of characteristics. The AGENT methodology performance was carefully analyzed before the hardware design based on the FPGA co-processor was adopted. The most time-consuming kernel part is then transplanted into the FPGA co-processor. The FPGA co-processor is designed with data flow-driven non von-Neumann architecture and has much higher efficiency than the conventional computer architecture. Details of the FPGA co-processor design are introduced and the design is benchmarked using two different examples. The advanced chip architecture helps the FPGA co-processor obtaining more than 20 times speed up with its working frequency much lower than the CPU frequency. (authors)

  16. A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

    Science.gov (United States)

    Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

    2015-10-01

    Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

  17. FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

    Directory of Open Access Journals (Sweden)

    Swapnil Mhaske

    2017-01-01

    Full Text Available We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

  18. Programming and Runtime Support toBlazeFPGA Accelerator Deployment at Datacenter Scale.

    Science.gov (United States)

    Huang, Muhuan; Wu, Di; Yu, Cody Hao; Fang, Zhenman; Interlandi, Matteo; Condie, Tyson; Cong, Jason

    2016-10-01

    With the end of CPU core scaling due to dark silicon limitations, customized accelerators on FPGAs have gained increased attention in modern datacenters due to their lower power, high performance and energy efficiency. Evidenced by Microsoft's FPGA deployment in its Bing search engine and Intel's 16.7 billion acquisition of Altera, integrating FPGAs into datacenters is considered one of the most promising approaches to sustain future datacenter growth. However, it is quite challenging for existing big data computing systems-like Apache Spark and Hadoop-to access the performance and energy benefits of FPGA accelerators. In this paper we design and implement Blaze to provide programming and runtime support for enabling easy and efficient deployments of FPGA accelerators in datacenters. In particular, Blaze abstracts FPGA accelerators as a service (FaaS) and provides a set of clean programming APIs for big data processing applications to easily utilize those accelerators. Our Blaze runtime implements an FaaS framework to efficiently share FPGA accelerators among multiple heterogeneous threads on a single node, and extends Hadoop YARN with accelerator-centric scheduling to efficiently share them among multiple computing tasks in the cluster. Experimental results using four representative big data applications demonstrate that Blaze greatly reduces the programming efforts to access FPGA accelerators in systems like Apache Spark and YARN, and improves the system throughput by 1.7 × to 3× (and energy efficiency by 1.5× to 2.7×) compared to a conventional CPU-only cluster.

  19. Functional analysis of DSP blocks in FPGA chips for applications in TESLA LLRF system

    Science.gov (United States)

    Pozniak, Krzysztof T.; Czarski, Tomasz; Romaniuk, Ryszard S.

    2004-07-01

    The paper contains the analysis of the application possibilities offered by the new generation of the FPGA chips. The new generation of the FPGA chips contain DSP blocks. The new functionalities are well suited for the application in the TESLA LLRF cavity simulation and control system (SIMCON). A debate on the programming methods of the new chips and the algorithm parameterization was presented. The aim of the, FPGA chip based, system analysis is the optimal chip usage to increase the maximum frequency at which the system can work efficiently, and the optimal usage of the accessible chip resources (DSP blocks). The exemplary results for a few practical calculated implementations were presented and analyzed. The implementations included some basic DSP operations performed in the FPGA chips of Altera and Xilinx. There were compared the results for a few different chips. The TESLA superconducting cavity simulator was efficiently implemented. The results were presented for the first time, for the pure FPGA/VHDL solution. The realization costs were debated in the dependence of given system parameters and the applied type of the FPGA chip.

  20. Intelligent Motion Control for Four-Wheeled Holonomic Mobile Robots Using FPGA-Based Artificial Immune System Algorithm

    Directory of Open Access Journals (Sweden)

    Hsu-Chih Huang

    2013-01-01

    Full Text Available This paper presents an intelligent motion controller for four-wheeled holonomic mobile robots with four driving omnidirectional wheels equally spaced at 90 degrees from one another by using field-programmable gate array (FPGA-based artificial immune system (AIS algorithm. Both the nature-inspired AIS computational approach and motion controller are implemented in one FPGA chip to address the optimal control problem of real-world mobile robotics application. The proposed FPGA-based AIS method takes the advantages of artificial intelligence and FPGA technology by using system-on-a-programmable chip (SoPC methodology. Experimental results are conducted to show the effectiveness and merit of the proposed FPGA-based AIS intelligent motion controller for four-wheeled omnidirectional mobile robots. This FPGA-based AIS autotuning intelligent controller outperforms the conventional nonoptimal controllers, the genetic algorithm (GA controller, and the particle swarm optimization (PSO controller.

  1. Intelligent Motion Control for Four-Wheeled Holonomic Mobile Robots Using FPGA-Based Artificial Immune System Algorithm

    OpenAIRE

    Hsu-Chih Huang

    2013-01-01

    This paper presents an intelligent motion controller for four-wheeled holonomic mobile robots with four driving omnidirectional wheels equally spaced at 90 degrees from one another by using field-programmable gate array (FPGA)-based artificial immune system (AIS) algorithm. Both the nature-inspired AIS computational approach and motion controller are implemented in one FPGA chip to address the optimal control problem of real-world mobile robotics application. The proposed FPGA-based AIS metho...

  2. Design av arkitektur for evolusjonær maskinvare basert på intern rekonfigurering av FPGA

    OpenAIRE

    Senland, Geir Aarstad

    2008-01-01

    Det ble i denne oppgaven designet en arkitektur for evolusjonær maskinvare basert på intern rekonfigurering av FPGA. Til å utføre intern rekonfigurasjonen av FPGA-en ble internal configuration access port (ICAP) brukt. Programmet PlanAhead fra Xilinx ble brukt til å designe den interne rekonfigurasjonsdelen av arkitekturen. Motivasjonen for oppgaven var å introdusere fleksibilitet til et signal- og klassifikasjonssystem, ved å bruke intern rekonfigurasjon av FPGA. Klassifikasjonssystemet ...

  3. Development of an automatic embossing and punching machine with a high energy saving and waste reduction potential. Final report; Entwicklung einer Praege- und Stanzmaschine mit hohem Energie- und Abfalleinsparungspotential. Abschlussbericht

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1996-07-01

    A new embossing and punching machine is described. The machine, with the working name FBR 104, combines maximum quality with high speed. Details are presented. [German] Ein Foliendruck dient der Veredelung von Drucksachen durch Gold-, Silber- und Farbfolien. Auch im Security-Bereich wird der Foliendruck in Zukunft mehr eingesetzt werden. Spezielle Folienoberflaechen und Hologramme sind wegen der hohen Faelschungssicherheit gefragt. Um mit den am haeufigsten fuer eine hohe Auflage (10.000 Bogen pro Stunde) eingesetzten Maschinen, den Offset-Rotationen, Schritt halten zu koennen, musste es eine Rotation sein. Die Idee einer schnellen Foliendruck-Bogen-Rotation mit dem Prinzip rund/rund war damit geboren. Es wurde der Arbeitstitel FBR 104 gewaehlt, diese Bezeichnung beinhaltet Foliendruck-Bogen-Rotation, Arbeitsbreite 104 cm. Zwei Jahre Forschung, Entwicklung und das Sammeln von Ideen waren die ersten Schritte, die zur Konstruktion, dem Bau von Prototypen, dem Erstellen von Programmen und schliesslich der monatelangen Versuche dienten. Im Folienbereich konnte nichts von den bisher bekannten Arbeitsablaeufen uebernommen werden. Alles war neu zu erarbeiten. So entstand die FBR 104. Die Basis der FBR 104 ist eine moderne Bogenrotation, gebaut im hoechsten Qualitaetsstandard, entwickelt und konstruiert fuer eine voellig neue Hochgeschwindigkeits-Folientechnik. Als Realisation des Gesamtkonzepts steht jetzt eine High-Tech-Maschine vor, leistungsstark wie zweckmaessig. (orig.)

  4. Development of a regional concept for energy management for the region of Karlsruhe. Final report; Entwicklung eines regionalen Energiemanagement-Konzeptes und Anwendung auf die TechnologieRegion Karlsruhe. Endbericht

    Energy Technology Data Exchange (ETDEWEB)

    Rentz, O.; Fichtner, W.; Frank, M. [Karlsruhe Univ. (T.H.) (Germany). Inst. fuer Industriebetriebslehre und Industrielle Produktion; Wolf, M.A.; Rejman, M.; Eyerer, P. [Fraunhofer-Institut fuer Chemische Technologie (ICT) (Germany); Reimert, R.; Schulz, A.; Buren, V. v. [Karlsruhe Univ. (T.H.) (Germany). Engler-Bunte-Institut Bereich 1 - Gas, Erdoel und Kohle; Schaefers, B.; Bernart, Y. [Karlsruhe Univ. (T.H.) (DE). Institut fuer Soziologie (IfSoz) (Germany)

    2002-09-01

    Major objectives of this project are: to prepare a cross-disciplinary analysis of all characteristic aspects of the energy supply and demand patterns of a group of selected energy-intensive companies in the Karlsruhe and Rhine harbour area (5 industrial power consumers, 1 utility), to identify practical approaches for optimization and integration of energy and material flows, (networking), and to develop optimised investment and energy supply options within the framework of given conditions. The basis of the optimal solution and energy network presented and explained in detail is a new combined-cycle power plant running as a gas-fired CHP plant, substituting about 50% of the systems formerly used. (orig./CB) [German] Fragestellungen der Effizienzsteigerung und der Verwertung von Abfaellen und Abwaerme gewinnen an Relevanz vor dem Hintergrund der begrenzten Aufnahmekapazitaet der Umweltmedien fuer Schadstoffe. Im Rahmen des Projektes wurde am Beispiel der Region Karlsruhe (5 Industrieunternehmen und 1 EVU) die Entwicklung betriebsuebergreifender Energieversorgungssysteme (Netzwerke) interdisziplinaer analysiert und beschrieben. Zielsetzungen des Projekts waren unter anderem: Bestimmung von zukunftsfaehigen Optionen, intelligente Vernetzung von Energiestroemen, wirtschaftliche Optimierung betriebsuebergreifender Energiemanagement-Loesungen. Die optimale vorgestellte Loesung ist charakterisiert durch den Neubau einer zentralen, gasgefeuerten GuD-Anlage, die etwa die Haelfte der bisherigen Anlagen ersetzt und zusammen mit den weiterhin genutzten Anlagen die Energieversorgung der Unternehmen sicherstellt. (orig./CB)

  5. The design and implementation of VME-based FPGA on-line configuration in slave serial mode

    International Nuclear Information System (INIS)

    Wei Shujun; Liu Zhen'an; Zhao Dixin; Guo Yanan

    2007-01-01

    The paper introduces the hardware design and work principle of FPGA on-line configuration. Firstly, we put the FPGA configuration data to a Flash Memory chip through VME bus; when the module is power on or received a configuration command from VME bus, the system begin to configure the FPGA from Flash Memory. In addition, the configuration data can also keep in a PC terminal, and not in Flash Memory, when necessary, which can be send to FPGA directly to perform the configuration. (authors)

  6. Status reports on the development and application of acoustic emission analysis. Proceedings; Statusberichte zur Entwicklung und Anwendung der Schallemissionsanalyse. Beitraege

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2017-08-01

    The colloquium lectures represent the wide range of applications in acoustic emission analysis and testing in the areas of damage development and damage mechanisms, testing of components, condition monitoring, development of new measuring systems and sensors as well as software development regarding locating methods and signal analysis. One focus of the colloquium is on current hardware and software developments for status monitoring by means of AE monitoring. One of the papers was separately analyzed for this database. [German] Die Vortraege des Kolloquiums repraesentieren das breite Spektrum der Anwendungen der Schallemissionsanalyse und -pruefung in den Bereichen der Schadensentwicklung und Schadensmechanismen, Pruefung von Bauteilen, Zustandsueberwachung, Entwicklung neuer Messsysteme und Sensoren sowie Softwareentwicklung bezueglich Ortungsverfahren und Signalanalyse. Ein Schwerpunkt des Kolloquiums betrifft aktuelle Hard- und Softwareentwicklungen zur Zustandsueberwachung durch AE-Monitoring.

  7. From eco-efficiency in overall sustainable development in enterprises; Von Oekoeffizienz zu nachhaltiger Entwicklung in Unternehmen

    Energy Technology Data Exchange (ETDEWEB)

    Weizsaecker, E.U. von; Stigson, B.; Seiler-Hausmann, J.D. (eds.)

    2001-07-01

    Eco-efficiency is achieved when goods and services satisfy human needs, increase the quality of life, at prices which are competitive and when environmental impacts and resource intensity are decreased to a degree that they are in accordance with the expected capacities of the Earth. Eco-efficiency is a management approach that allows enterprises to carry out environmental protection measures from a market-oriented point of view. Eco-efficiency shows that ecology and economy do not contradict each other. On the contrary, in combination, they present a gain for enterprises. The motto is: To produce more with less. The WBCSD and its member enterprises have agreed to make economic growth and sustainable development the guideline for their economic entrepreneurial actions. The WBCSD supports the close co-operation of the economy, government and other organizations, as it is only together that we can help sustainable development to achieve a breakthrough. (orig.) [German] Oekoeffizienz ist dann erreicht, wenn Gueter und Dienstleistungen die menschlichen Beduerfnisse befriedigen, die Lebensqualitaet erhoehen und wettbewerbsfaehige Preise aufweisen, und die oekologischen Auswirkungen und die Ressourcenintensitaet waehrend des Lebenszyklus soweit verringert werden, dass eine Uebereinstimmung mit der voraussichtlichen Belastbarkeit der Erde besteht. Oekoeffizienz steht fuer einen Managementansatz, der Unternehmen erlaubt, Umweltschutzmassnahmen unter Marktgesichtspunkten durchzufuehren. Mit Oekoeffizienz wird zum Ausdruck gebracht, dass Oekonomie und Oekologie sich nicht ausschliessen, sondern in Kombination einen Gewinn fuer Unternehmen darstellen. Das Motto lautet: Mehr mit weniger produzieren. Der WBCSD und seine Mitgliedsunternehmen haben sich darauf verstaendigt, ihr Handeln von den Prinzipien des oekonomischen Wachstums und der nachhaltigen Entwicklung leiten zu lassen. Der WBCSD unterstuetzt die enge Zusammenarbeit von Wirtschaft, Staat und anderen Organisationen

  8. Analysis of FPGA filter in Computed Tomography Images for Radioactive Dose Reduction; Analisis del Filtro FPGA en Imagenes de Tomografia Computarizada para la Reduccion de Dosis Radiactiva

    Energy Technology Data Exchange (ETDEWEB)

    Parcero, E.; Vidal, V.; Verdu, G.; Arnal, J.; Mayo, P.

    2014-07-01

    In this study, different filtering methods are compared on an image of mini-MIAS database (consisting of a collection of mammographic images). Methods employees are PGFM (Peer Group Fuzzy Metric), NDF (Non-linear Diffusion Method) a combination of these two, and FPGA (Fuzzy Peer Group Average). (Author)

  9. Functional verification of dynamically reconfigurable FPGA-based systems

    CERN Document Server

    Gong, Lingkan

    2015-01-01

    This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric.  Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an i...

  10. An FPGA- Based General-Purpose Data Acquisition Controller

    Science.gov (United States)

    Robson, C. C. W.; Bousselham, A.; Bohm

    2006-08-01

    System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems

  11. Design and FPGA implementation for MAC layer of Ethernet PON

    Science.gov (United States)

    Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao

    2004-04-01

    Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.

  12. FPGA implementation of image dehazing algorithm for real time applications

    Science.gov (United States)

    Kumar, Rahul; Kaushik, Brajesh Kumar; Balasubramanian, R.

    2017-09-01

    Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K_BRAM, 97 DSP_48, 6508 FFs and 8159 LUTs.

  13. FPGA design of correlation-based pattern recognition

    Science.gov (United States)

    Jridi, Maher; Alfalou, Ayman

    2017-05-01

    Optical/Digital pattern recognition and tracking based on optical/digital correlation are a well-known techniques to detect, identify and localize a target object in a scene. Despite the limited number of treatments required by the correlation scheme, computational time and resources are relatively high. The most computational intensive treatment required by the correlation is the transformation from spatial to spectral domain and then from spectral to spatial domain. Furthermore, these transformations are used on optical/digital encryption schemes like the double random phase encryption (DRPE). In this paper, we present a VLSI architecture for the correlation scheme based on the fast Fourier transform (FFT). One interesting feature of the proposed scheme is its ability to stream image processing in order to perform correlation for video sequences. A trade-off between the hardware consumption and the robustness of the correlation can be made in order to understand the limitations of the correlation implementation in reconfigurable and portable platforms. Experimental results obtained from HDL simulations and FPGA prototype have demonstrated the advantages of the proposed scheme.

  14. An FPGA computing demo core for space charge simulation

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; Huang, Yifei; /Fermilab

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  15. Families of FPGA-Based Accelerators for Approximate String Matching.

    Science.gov (United States)

    Van Court, Tom; Herbordt, Martin C

    2007-03-05

    Dynamic programming for approximate string matching is a large family of different algorithms, which vary significantly in purpose, complexity, and hardware utilization. Many implementations have reported impressive speed-ups, but have typically been point solutions - highly specialized and addressing only one or a few of the many possible options. The problem to be solved is creating a hardware description that implements a broad range of behavioral options without losing efficiency due to feature bloat. We report a set of three component types that address different parts of the approximate string matching problem. This allows each application to choose the feature set required, then make maximum use of the FPGA fabric according to that application's specific resource requirements. Multiple, interchangeable implementations are available for each component type. We show that these methods allow the efficient generation of a large, if not complete, family of accelerators for this application. This flexibility was obtained while retaining high performance: We have evaluated a sample against serial reference codes and found speed-ups of from 150× to 400× over a high-end PC.

  16. FPGA-accelerated algorithm for the regular expression matching system

    Science.gov (United States)

    Russek, P.; Wiatr, K.

    2015-01-01

    This article describes an algorithm to support a regular expressions matching system. The goal was to achieve an attractive performance system with low energy consumption. The basic idea of the algorithm comes from a concept of the Bloom filter. It starts from the extraction of static sub-strings for strings of regular expressions. The algorithm is devised to gain from its decomposition into parts which are intended to be executed by custom hardware and the central processing unit (CPU). The pipelined custom processor architecture is proposed and a software algorithm explained accordingly. The software part of the algorithm was coded in C and runs on a processor from the ARM family. The hardware architecture was described in VHDL and implemented in field programmable gate array (FPGA). The performance results and required resources of the above experiments are given. An example of target application for the presented solution is computer and network security systems. The idea was tested on nearly 100,000 body-based viruses from the ClamAV virus database. The solution is intended for the emerging technology of clusters of low-energy computing nodes.

  17. Reliability Tests of the LHC Beam Loss Monitoring FPGA Firmware

    CERN Document Server

    Hajdu, C F; Dehning, B; Jackson, S

    2010-01-01

    The LHC Beam Loss Monitoring (BLM) system is one of the most complex instrumentation systems deployed in the LHC. In addition to protecting the collider, the system also needs to provide a means of diagnosing machine faults and deliver a feedback of losses to the control room as well as to several systems for their setup and analysis. It has to transmit and process signals from almost 4’000 monitors, and has nearly 3 million configurable parameters. In a system of such complexity, firmware reliability is a critical issue. The integrity of the signal chain of the LHC BLM system and its ability to correctly detect unwanted scenarios and thus provide the required protection level must be ensured. In order to analyze the reliability and functionality, an advanced verification environment has been developed to evaluate the performance and response of the FPGA-based data analysis firmware. This paper will report on the numerous tests that have been performed and on how the results are used to quantify the reliabi...

  18. FPGA-based prototype storage system with phase change memory

    Science.gov (United States)

    Li, Gezi; Chen, Xiaogang; Chen, Bomy; Li, Shunfen; Zhou, Mi; Han, Wenbing; Song, Zhitang

    2016-10-01

    With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

  19. Entwicklung und lmplementierung von Analysemethoden zum Erfassen vonGeschwindigkeitsfeldem mit dem PIV Verfahren (Development and Implementation of Analytical Methods for Detecting Velocity Fields using PIV- Method)

    Science.gov (United States)

    2016-04-26

    FUNDING NUMBERS Entwicklung und lmplementierung von Analysemethoden zum Erfassen von Geschwindigkeitsfeldem mit dem PIY-Yerfahren (Development and...thesis presents two new analysis methods for the measurement of flow fields using Particle -Image-Yelocimetry (PlY). PlY gives the opportunity of...two photograph ies of the patiicles are taken within a short period of time. In today’s evaluation the translationally shift of the particles is

  20. Am Puls des Wandels - Veränderungskommunikation messen und steuern : Entwicklung und Anwendung eines Controllingansatzes für Veränderungskommunikation.

    OpenAIRE

    Heyder, Daniela

    2014-01-01

    Die Zielsetzung der Arbeit liegt in der Entwicklung und empirischen Anwendung eines Controllingansatzes speziell für die Veränderungskommunikation. Für den Erfolg eines Unternehmens ist kontinuierlicher Wandel von zentraler Bedeutung. So schnell wie sich die Umwelt durch z.B. zunehmenden Wettbewerb, neue Wertvorstellungen oder innovative Technologien verändert, müssen sich die Strategien, Strukturen und Prozesse in Unternehmen sowie immer auch die Mitarbeiter, ihre Denk- und Verhaltensweis...

  1. Krankheitsbewältigung und Juckreizkognition bei Kindern und Jugendlichen mit atopischem Ekzem : Entwicklung und Evaluation zweier Fragebögen

    OpenAIRE

    Debus, Dirk

    2003-01-01

    In der vorliegenden Arbeit wird zunächst eine Übersicht über das Krankheitsbild des atopischen Ekzems gegeben, es werden aktuelle Erkenntnisse zu Psychosomatik und Krankheitsverarbeitung der Neurodermitis dargestellt. Im Speziellen wird auf die Bewältigung der Neurodermitis als chronische Erkrankung mit hoher psychosozialer Belastung und auf die Situation von Familien mit neurodermitiskranken Kindern eingegangen. Anschließend wird die Entwicklung und Evaluierung zweier Fragebögen für Kinder u...

  2. FPGA-based distributed computing microarchitecture for complex physical dynamics investigation.

    Science.gov (United States)

    Borgese, Gianluca; Pace, Calogero; Pantano, Pietro; Bilotta, Eleonora

    2013-09-01

    In this paper, we present a distributed computing system, called DCMARK, aimed at solving partial differential equations at the basis of many investigation fields, such as solid state physics, nuclear physics, and plasma physics. This distributed architecture is based on the cellular neural network paradigm, which allows us to divide the differential equation system solving into many parallel integration operations to be executed by a custom multiprocessor system. We push the number of processors to the limit of one processor for each equation. In order to test the present idea, we choose to implement DCMARK on a single FPGA, designing the single processor in order to minimize its hardware requirements and to obtain a large number of easily interconnected processors. This approach is particularly suited to study the properties of 1-, 2- and 3-D locally interconnected dynamical systems. In order to test the computing platform, we implement a 200 cells, Korteweg-de Vries (KdV) equation solver and perform a comparison between simulations conducted on a high performance PC and on our system. Since our distributed architecture takes a constant computing time to solve the equation system, independently of the number of dynamical elements (cells) of the CNN array, it allows us to reduce the elaboration time more than other similar systems in the literature. To ensure a high level of reconfigurability, we design a compact system on programmable chip managed by a softcore processor, which controls the fast data/control communication between our system and a PC Host. An intuitively graphical user interface allows us to change the calculation parameters and plot the results.

  3. Design for an IO block array in a tile-based FPGA

    International Nuclear Information System (INIS)

    Ding Guangxin; Chen Lingdou; Liu Zhongli

    2009-01-01

    A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 μm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process. (semiconductor integrated circuits)

  4. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    Energy Technology Data Exchange (ETDEWEB)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I. [Research and Production Corporation Radiy, 29 Geroev Stalingrada Str., Kirovograd 25006 (Ukraine); Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A., E-mail: marketing@radiy.co [Center for Safety Infrastructure-Oriented Research and Analysis, 37 Astronomicheskaya Str., Kharkiv 61085 (Ukraine)

    2010-10-15

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY{sup TM} platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY{sup TM} platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY{sup TM} platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  5. OPENCORE NMR: open-source core modules for implementing an integrated FPGA-based NMR spectrometer.

    Science.gov (United States)

    Takeda, Kazuyuki

    2008-06-01

    A tool kit for implementing an integrated FPGA-based NMR spectrometer [K. Takeda, A highly integrated FPGA-based nuclear magnetic resonance spectrometer, Rev. Sci. Instrum. 78 (2007) 033103], referred to as the OPENCORE NMR spectrometer, is open to public. The system is composed of an FPGA chip and several peripheral boards for USB communication, direct-digital synthesis (DDS), RF transmission, signal acquisition, etc. Inside the FPGA chip have been implemented a number of digital modules including three pulse programmers, the digital part of DDS, a digital quadrature demodulator, dual digital low-pass filters, and a PC interface. These FPGA core modules are written in VHDL, and their source codes are available on our website. This work aims at providing sufficient information with which one can, given some facility in circuit board manufacturing, reproduce the OPENCORE NMR spectrometer presented here. Also, the users are encouraged to modify the design of spectrometer according to their own specific needs. A home-built NMR spectrometer can serve complementary roles to a sophisticated commercial spectrometer, should one comes across such new ideas that require heavy modification to hardware inside the spectrometer. This work can lower the barrier of building a handmade NMR spectrometer in the laboratory, and promote novel and exciting NMR experiments.

  6. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    International Nuclear Information System (INIS)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I.; Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A.

    2010-10-01

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY TM platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY TM platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY TM platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  7. Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

    International Nuclear Information System (INIS)

    Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

    2016-01-01

    The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

  8. Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

    DEFF Research Database (Denmark)

    Singh, Ritu; Kalia, Kartik; Minver, M. H.

    2016-01-01

    Abstract-In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobile...

  9. Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

  10. Input/output Buffer based Vedic Multiplier Design for Thermal Aware Energy Efficient Digital Signal Processing on 28nm FPGA

    DEFF Research Database (Denmark)

    Goswami, Kavita; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar

    2016-01-01

    Programmable Gate Array (FPGA) in order to reduce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy...

  11. Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.

  12. Implementation and integration of a systematic DBPM calibration with PLL frequency synthesis and FPGA

    International Nuclear Information System (INIS)

    Sun Xudong; Leng Yongbin

    2014-01-01

    Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM (Beam Position Monitor) processor deteriorates the BPM performance. A systematic solution based on signal source calibration tactics has been carried out to rectify this defect. It is optimized for implementation in FPGA. Mathematical illustrations of the calibration method, hardware and software design and implementation are presented. A signal source circuit using frequency synthesis technique is designed as calibration standard. Data acquisition system using JAVA web technology and Ethernet is introduced. Integrated FPGA implementation code architecture is presented, and experimental test results show that the method implemented in FPGA is feasible. Compared to other methods, our approach can rectify the nonlinearity and asymmetry simultaneously. The whole solution is integrated into the DBPM processor and can be executed online. (authors)

  13. An Integrated Software Testing Framework for FPGA-Based Controllers in Nuclear Power Plants

    Directory of Open Access Journals (Sweden)

    Jaeyeob Kim

    2016-04-01

    Full Text Available Field-programmable gate arrays (FPGAs have received much attention from the nuclear industry as an alternative platform to programmable logic controllers for digital instrumentation and control. The software aspect of FPGA development consists of several steps of synthesis and refinement, and also requires verification activities, such as simulations that are performed individually at each step. This study proposed an integrated software-testing framework for simulating all artifacts of the FPGA software development simultaneously and evaluating whether all artifacts work correctly using common oracle programs. This method also generates a massive number of meaningful simulation scenarios that reflect reactor shutdown logics. The experiment, which was performed on two FPGA software implementations, showed that it can dramatically save both time and costs.

  14. FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool

    Directory of Open Access Journals (Sweden)

    Mohammed Bahoura

    2016-02-01

    Full Text Available In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA using Xilinx System Generator (XSG and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls.

  15. Direct Measurement of Power Dissipated by Monte Carlo Simulations on CPU and FPGA Platforms

    DEFF Research Database (Denmark)

    Albicocco, Pietro; Papini, Davide; Nannarelli, Alberto

    In this technical report, we describe how power dissipation measurements on different computing platforms (a desktop computer and an FPGA board) are performed by using a Hall effectbased current sensor. The chosen application is a Monte Carlo simulation for European option pricing which is a popu......In this technical report, we describe how power dissipation measurements on different computing platforms (a desktop computer and an FPGA board) are performed by using a Hall effectbased current sensor. The chosen application is a Monte Carlo simulation for European option pricing which...... is a popular algorithm used in financial computations. The Hall effect probe measurements complement the measurements performed on the core of the FPGA by a built-in Xilinx power monitoring system....

  16. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    James Millar

    2006-10-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  17. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    Millar James

    2006-01-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  18. A low delay transmission method of multi-channel video based on FPGA

    Science.gov (United States)

    Fu, Weijian; Wei, Baozhi; Li, Xiaobin; Wang, Quan; Hu, Xiaofei

    2018-03-01

    In order to guarantee the fluency of multi-channel video transmission in video monitoring scenarios, we designed a kind of video format conversion method based on FPGA and its DMA scheduling for video data, reduces the overall video transmission delay.In order to sace the time in the conversion process, the parallel ability of FPGA is used to video format conversion. In order to improve the direct memory access (DMA) writing transmission rate of PCIe bus, a DMA scheduling method based on asynchronous command buffer is proposed. The experimental results show that this paper designs a low delay transmission method based on FPGA, which increases the DMA writing transmission rate by 34% compared with the existing method, and then the video overall delay is reduced to 23.6ms.

  19. An FPGA Based General Purpose DAQ Module for the KLOE-2 Experiment

    Science.gov (United States)

    Aloisio, A.; Branchini, P.; Budano, A.; Balla, A.; Beretta, M.; Ciambrone, P.; De Lucia, E.

    2011-12-01

    A general purpose FPGA based DAQ module has been developed based on a Virtex-4 FPGA. It is able to acquire up to 1024 different channels distributed over 10 slave cards. The module has an optical interface a RS-232 a USB and a Gigabit Interface. The KLOE-2 experiment is going to use it to collect data from the Inner tracker and the QCALT. An embedded processor (power pc 604) is present on the FPGA and a telnet server has been developed and installed. A new general purpose data taking system has been based on this module to acquire the Inner Tracker. The system is at the moment working at LNF (Laboratori Nazionali di Frascati).

  20. An FPGA Based General Purpose DAQ Module for the KLOE-2 Experiment

    International Nuclear Information System (INIS)

    Aloisio, A; Branchini, P; Budano, A; Balla, A; Beretta, M; Ciambrone, P; De Lucia, E

    2011-01-01

    A general purpose FPGA based DAQ module has been developed based on a Virtex-4 FPGA. It is able to acquire up to 1024 different channels distributed over 10 slave cards. The module has an optical interface a RS-232 a USB and a Gigabit Interface. The KLOE-2 experiment is going to use it to collect data from the Inner tracker and the QCALT. An embedded processor (power pc 604) is present on the FPGA and a telnet server has been developed and installed. A new general purpose data taking system has been based on this module to acquire the Inner Tracker. The system is at the moment working at LNF (Laboratori Nazionali di Frascati).

  1. Diversity for security: case assessment for FPGA-based safety-critical systems

    Directory of Open Access Journals (Sweden)

    Kharchenko Vyacheslav

    2016-01-01

    Full Text Available Industrial safety critical instrumentation and control systems (I&Cs are facing more with information (in general and cyber, in particular security threats and attacks. The application of programmable logic, first of all, field programmable gate arrays (FPGA in critical systems causes specific safety deficits. Security assessment techniques for such systems are based on heuristic knowledges and the expert judgment. Main challenge is how to take into account features of FPGA technology for safety critical I&Cs including systems in which are applied diversity approach to minimize risks of common cause failure. Such systems are called multi-version (MV systems. The goal of the paper is in description of the technique and tool for case-based security assessment of MV FPGA-based I&Cs.

  2. FPGA implementation of hardware processing modules as coprocessors in brain-machine interfaces.

    Science.gov (United States)

    Wang, Dong; Hao, Yaoyao; Zhu, Xiaoping; Zhao, Ting; Wang, Yiwen; Chen, Yaowu; Chen, Weidong; Zheng, Xiaoxiang

    2011-01-01

    Real-time computation, portability and flexibility are crucial for practical brain-machine interface (BMI) applications. In this work, we proposed Hardware Processing Modules (HPMs) as a method for accelerating BMI computation. Two HPMs have been developed. One is the field-programmable gate array (FPGA) implementation of spike sorting based on probabilistic neural network (PNN), and the other is the FPGA implementation of neural ensemble decoding based on Kalman filter (KF). These two modules were configured under the same framework and tested with real data from motor cortex recording in rats performing a lever-pressing task for water rewards. Due to the parallelism feature of FPGA, the computation time was reduced by several dozen times, while the results are almost the same as those from Matlab implementations. Such HPMs provide a high performance coprocessor for neural signal computation.

  3. Improved Approach for Utilization of FPGA Technology into DAQ, DSP, and Computing Applications

    Energy Technology Data Exchange (ETDEWEB)

    Isenhower, Larry Donald

    2009-01-28

    Innovation Partners proposed and successfully demonstrated in this SBIR Phase I grant a software/hardware co-design approach to reduce both the difficulty and time to implement Field Programmable Gate Array (FPGA) solutions to data acquisition and specialized computational applications. FPGAs can require excessive time for programming and require specialized knowledge that will be greatly reduced by the company's solution. Not only are FPGAs ideal for DAQ and embedded solutions, they can also be the best solution to specialized signal processing to replace Digital Signal Processors (DSPs). By allowing FPGA programming to be done in C with the equivalent of a simple compilation, algorithm changes and improvements can be implemented decreasing the life-cycle costs and allow subsitution of new FPGA designs staying above the technological details.

  4. FPGA-Based Networked Phasemeter for a Heterodyne Interferometer

    Science.gov (United States)

    Rao, Shanti

    2009-01-01

    A document discusses a component of a laser metrology system designed to measure displacements along the line of sight with precision on the order of a tenth the diameter of an atom. This component, the phasemeter, measures the relative phase of two electrical signals and transfers that information to a computer. Because the metrology system measures the differences between two optical paths, the phasemeter has two inputs, called measure and reference. The reference signal is nominally a perfect square wave with a 50- percent duty cycle (though only rising edges are used). As the metrology system detects motion, the difference between the reference and measure signal phases is proportional to the displacement of the motion. The phasemeter, therefore, counts the elapsed time between rising edges in the two signals, and converts the time into an estimate of phase delay. The hardware consists of a circuit board that plugs into a COTS (commercial, off-the- shelf) Spartan-III FPGA (field-programmable gate array) evaluation board. It has two BNC inputs, (reference and measure), a CMOS logic chip to buffer the inputs, and an Ethernet jack for transmitting reduced-data to a PC. Two extra BNC connectors can be attached for future expandability, such as external synchronization. Each phasemeter handles one metrology channel. A bank of six phasemeters (and two zero-crossing detector cards) with an Ethernet switch can monitor the rigid body motion of an object. This device is smaller and cheaper than existing zero-crossing phasemeters. Also, because it uses Ethernet for communication with a computer, instead of a VME bridge, it is much easier to use. The phasemeter is a key part of the Precision Deployable Apertures and Structures strategic R&D effort to design large, deployable, segmented space telescopes.

  5. Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-06-01

    Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

  6. Optimization on fixed low latency implementation of the GBT core in FPGA

    Science.gov (United States)

    Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

    2017-07-01

    In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

  7. Optimization on fixed low latency implementation of the GBT core in FPGA

    International Nuclear Information System (INIS)

    Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

    2017-01-01

    In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

  8. An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

    Energy Technology Data Exchange (ETDEWEB)

    Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun [KAERI, Daejeon (Korea, Republic of)

    2014-08-15

    NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity.

  9. Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device

    Science.gov (United States)

    Picone, Rico A. R.; Davis, Solomon; Devine, Cameron; Garbini, Joseph L.; Sidles, John A.

    2017-04-01

    We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

  10. Compact FPGA-based beamformer using oversampled 1-bit A/D converters

    DEFF Research Database (Denmark)

    Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

    2005-01-01

    reconstruction is done using finite impulse response (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50......% of the available logic resources in a commercially available midrange FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz....

  11. A Labview based FPGA data acquisition with integrated stage and beam transport control

    International Nuclear Information System (INIS)

    Laird, J.S.; Szymanski, R.; Ryan, C.G.; Gonzalez-Alvarez, I.

    2013-01-01

    We report on a new FPGA based data acquisition system developed for the CSIRO Nuclear Microprobe (NMP) which is tightly integrated with both target positioning and beam transport. The data acquisition system called MicrodaQ is based on National Instruments Labview FPGA and numerous instrumentation modules spread over several PC’s. Beam transport uses a feedback control loop to optimise current on target for long unmanned experiments. These upgrades are discussed in detail and an example of the systems use for μ-Particle Induced X-ray Emission (PIXE) analysis on a Doriri apatite is briefly described

  12. The FPGA realization of the general cellular automata based cryptographic hash functions: Performance and effectiveness

    Directory of Open Access Journals (Sweden)

    P. G. Klyucharev

    2014-01-01

    Full Text Available In the paper the author considers hardware implementation of the GRACE-H family general cellular automata based cryptographic hash functions. VHDL is used as a language and Altera FPGA as a platform for hardware implementation. Performance and effectiveness of the FPGA implementations of GRACE-H hash functions were compared with Keccak (SHA-3, SHA-256, BLAKE, Groestl, JH, Skein hash functions. According to the performed tests, performance of the hardware implementation of GRACE-H family hash functions significantly (up to 12 times exceeded performance of the hardware implementation of previously known hash functions, and effectiveness of that hardware implementation was also better (up to 4 times.

  13. Design of the device of auto-measuring radon continuously based on FPGA

    International Nuclear Information System (INIS)

    Wang Yan; Shen Zhengqin; Chen Qiong

    2004-01-01

    This paper introduces the design of the device of auto-measuring radon continuously. The core of the system is the design of controlling system by FPGA, which consists of preset module, electrical calendar module and driving module. The system can automatically measure the consistence of the radon and the separating out rate of it. The information data is displayed by LCD. The high speed micro printer is used to print the measuring result. It adopts FPGA to design the measuring system of the device, which can improve the precision and stability of the system. (authors)

  14. SEU mitigation technique by Dynamic Reconfiguration method in FPGA based DSP application

    International Nuclear Information System (INIS)

    Dey, Madhusudan; Singh, Abhishek; Roy, Amitava

    2012-01-01

    Field Programmable Gate Array (FPGA), an SRAM based configurable devices meant for implementation of any digital circuits is susceptible to malfunction in the harsh radiation environment. It causes the corruption of the configuration memory of FPGA and the digital circuits starts malfunctioning. There is a need to restore the system as early as possible. This paper discusses about one such technique named dynamic partial reconfiguration (DPR) method. This paper also touches upon the signal processing by DPR method. The framework consisting of ADC, DAC and ICAP controllers designed using dedicated state machines to study the best possible downtime also for verifying the performance of digital filters for signal processing

  15. A Labview based FPGA data acquisition with integrated stage and beam transport control

    Science.gov (United States)

    Laird, J. S.; Szymanski, R.; Ryan, C. G.; Gonzalez-Alvarez, I.

    2013-07-01

    We report on a new FPGA based data acquisition system developed for the CSIRO Nuclear Microprobe (NMP) which is tightly integrated with both target positioning and beam transport. The data acquisition system called MicrodaQ is based on National Instruments Labview FPGA and numerous instrumentation modules spread over several PC's. Beam transport uses a feedback control loop to optimise current on target for long unmanned experiments. These upgrades are discussed in detail and an example of the systems use for μ-Particle Induced X-ray Emission (PIXE) analysis on a Doriri apatite is briefly described.

  16. Radiation tolerance and mitigation strategies for FPGA:s in the ATLAS TileCal Demonstrator

    CERN Document Server

    Akerstedt, H; The ATLAS collaboration

    2013-01-01

    During 2014, demonstrator electronics will be installed in a Tile calorimeter "drawer" to get long term experience with the inherently redundant electronics proposed for a full upgrade scheduled for 2022. The new system, being FPGA-based, uses dense programmable logic which must be proven to be sufficently radiation tolerant. It must be protected against radiation induced single event upsets that corrupt memory and logic functions. Radiation induced errors need to be found and compensated for in time, to minimize data loss but also to avoid permanent damage. Strategies for detecting and correcting radiation induced errors in the Kintex-7 FPGA:s of the demonstrator are evaluated and discussed.

  17. TESLA cavity modeling and digital implementation in FPGA technology for control system development

    Energy Technology Data Exchange (ETDEWEB)

    Czarski, T.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland); Simrock, S. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany)

    2006-07-01

    The electromechanical model of the TESLA cavity has been implemented in FPGA technology for real-time testing of the control system. The model includes Lorentz force detuning and beam loading effects. Step operation and vector stimulus operation modes are applied for the evaluation of a FPGA cavity simulator operated by a digital controller. The performance of the cavity hardware model is verified by comparing with a software model of the cavity implemented in the MATLAB system. The numerical aspects are considered for an optimal DSP calculation. Some experimental results are presented for different cavity operational conditions. (orig.)

  18. Software layer for FPGA-based TESLA cavity control system. Part I

    Energy Technology Data Exchange (ETDEWEB)

    Koprek, W.; Kaleta, P.; Szewinski, J.; Pozniak, K.T.; Czarski, T.; Romaniuk, R.S. [Institute of Electronic Systems, WUT, Warsaw (Poland)

    2004-07-01

    The paper describes design and practical realization of software for laboratory purposes to control FPGA-based photonic and electronic equipment. There is presented a universal solution for all relevant devices with FPGA chips and gigabit optical links. The paper describes architecture of the software layers and program solutions of hardware communication based on internal interface (II) technology. Such a solution was used for superconducting cavity controller and simulator (SIMCON) for the TESLA experiment in DESY (Hamburg). A number of practical examples of the software solutions for the SIMCON system were given in this paper. (orig.)

  19. From the components to the stack. Developing and designing 5kW HT-PEFC stacks; Von der Komponente zum Stack. Entwicklung und Auslegung von HT-PEFC-Stacks der 5 kW-Klasse

    Energy Technology Data Exchange (ETDEWEB)

    Bendzulla, Anne

    2010-12-22

    The aim of the present project is to develop a stack design for a 5-kW HTPEFC system. First, the state of the art of potential materials and process designs will be discussed for each component. Then, using this as a basis, three potential stack designs with typical attributes will be developed and assessed in terms of practicality with the aid of a specially derived evaluation method. Two stack designs classified as promising will be discussed in detail, constructed and then characterized using short stack tests. Comparing the stack designs reveals that both designs are fundamentally suitable for application in a HT-PEFC system with on-board supply. However, some of the performance data differ significantly for the two stack designs. The preferred stack design for application in a HT-PEFC system is characterized by robust operating behaviour and reproducible high-level performance data. Moreover, in compact constructions (120 W/l at 60 W/kg), the stack design allows flexible cooling with thermal oil or air, which can be adapted to suit specific applications. Furthermore, a defined temperature gradient can be set during operation, allowing the CO tolerance to be increased by up to 10 mV. The short stack design developed within the scope of the present work therefore represents an ideal basis for developing a 5-kW HT-PEFC system. Topics for further research activities include improving the performance by reducing weight and/or volume, as well as optimizing the heat management. The results achieved within the framework of this work clearly show that HTPEFC stacks have the potential to play a decisive role in increasing efficiency in the future, particularly when combined with an on-board supply system. (orig.) [German] Ziel der vorliegenden Arbeit ist die Entwicklung eines Stackkonzeptes fuer ein 5 kW-HT-PEFC System. Dazu wird zunaechst fuer jede Komponente der Stand der Technik moeglicher Materialien und Prozesskonzepte diskutiert. Darauf aufbauend werden drei

  20. Normal values in growth and development. Base for diagnostics and therapy. 2. tot. rev. ed.; Normalwerte in Wachstum und Entwicklung. Die Basis fuer Diagnostik und Therapie

    Energy Technology Data Exchange (ETDEWEB)

    Exner, G.U. [Abt. Kinderorthopaedie und Tumororthopaedie, Orthopaedische Universitaetsklinik Balgrist, Zurich (Switzerland)

    2003-07-01

    This compendium provides reference values and probability distributions on the following parameters: clinical and radiological measured values relating to the growing skeleton including: growth; hand skeleton development stages with Central European deviations; hip sonography; psychomotor development; performance physiology; and lung function. Newly incorporated in this edition are, amongst other features, explanations on the clinical significance of the measured values.

  1. A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

    Directory of Open Access Journals (Sweden)

    Eduardo Magdaleno

    2013-12-01

    Full Text Available This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI. The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A. Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

  2. A Research on Seamless Platform Change of Reactor Protection System From PLC to FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Yoo, Junbeom; Lee, Jonghoon [Konkuk Univ., Seoul (Korea, Republic of); Lee, Jangsoo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2013-08-15

    The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

  3. A FPGA embedded web server for remote monitoring and control of smart sensors networks.

    Science.gov (United States)

    Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

    2013-12-27

    This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

  4. Feasibility analysis of real-time physical modeling using WaveCore processor technology on FPGA

    NARCIS (Netherlands)

    Verstraelen, Martinus Johannes Wilhelmina; Pfeifle, Florian; Bader, Rolf

    2015-01-01

    WaveCore is a scalable many-core processor technology. This technology is specifically developed and optimized for real-time acoustical modeling applications. The programmable WaveCore soft-core processor is silicon-technology independent and hence can be targeted to ASIC or FPGA technologies. The

  5. Timing Constraints Based High Performance Des Design And Implementation On 28nm FPGA

    DEFF Research Database (Denmark)

    Thind, Vandana; Pandey, Sujeet; Hussain, Dil muhammed Akbar

    2018-01-01

    in this work, we are going to implement DES Algorithm on 28nm Artix-7 FPGA. To achieve high performance design goal, we are using minimum period, maximum frequency, minimum low pulse, minimum high pulse for different cases of worst case slack, maximum delay, setup time, hold time and data skew path...

  6. A high-level power model for MPSoC on FPGA

    NARCIS (Netherlands)

    Piscitelli, R.; Pimentel, A.D.

    2011-01-01

    This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, e.g., commonly-used instruction-set

  7. Using an FPGA for Fast Bit Accurate SoC Simulation

    NARCIS (Netherlands)

    Wolkotte, P.T.; Holzenspies, P.K.F.; Smit, Gerardus Johannes Maria

    In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit

  8. A signature-based power model for MPSoC on FPGA

    NARCIS (Netherlands)

    Piscitelli, R.; Pimentel, A.D.

    2012-01-01

    This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used

  9. A high-level power model for MPSoC on FPGA

    NARCIS (Netherlands)

    Piscitelli, R.; Pimentel, A.D.

    2012-01-01

    This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures. As a result, it is capable of achieving good evaluation performance, thereby making the

  10. A configurable FPGA FEC unit for Tb/s optical communication

    DEFF Research Database (Denmark)

    Andersen, Jakob Dahl; Larsen, Knud J.; Bering Bøgh, Christian

    2017-01-01

    Decoding of FEC (forward error correction) for optical communication beyond 1 Tb/s is investigated. A configurable single FPGA solution is presented having configurations supporting bit-rates in the range from 40 Gb/s to 1.6 Tb/s. The design allows for trade-offs of bit-rate, footprint, and latency...

  11. An Automated Design-flow for FPGA-based Sequential Simulation

    NARCIS (Netherlands)

    Wolkotte, P.T.; Rutgers, J.H.; Holzenspies, P.K.F.; Westmijze, M.; Westmijze, M.; Blumink, R.; Smit, Gerardus Johannes Maria

    In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard

  12. A high powered radar interference mitigation technique for communications signal recovery with fpga implementation

    Science.gov (United States)

    2017-03-01

    Showing Nearly Identical SER Performance .......................19 Figure 11. The Received Interference Phase Cycle Estimate Is Aligned with the...fixed-phase offset for each sample. Figure 11. The Received Interference Phase Cycle Estimate Is Aligned with the Corresponding Phase in the...RADAR INTERFERENCE MITIGATION TECHNIQUE FOR COMMUNICATIONS SIGNAL RECOVERY WITH FPGA IMPLEMENTATION by Geoffrey R. Meager March 2017

  13. A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

    NARCIS (Netherlands)

    Homulle, H.A.R.; Charbon, E.E.E.

    2016-01-01

    We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide

  14. FPGA-Based Pulse Pile-Up Correction With Energy and Timing Recovery.

    Science.gov (United States)

    Haselman, M D; Pasko, J; Hauck, S; Lewellen, T K; Miyaoka, R S

    2012-10-01

    Modern field programmable gate arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates well above 100 MHz. This, combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilized to add significant signal processing power to produce higher quality images. In this paper we report on an all-digital pulse pile-up correction algorithm that has been developed for the FPGA. The pile-up mitigation algorithm will allow the scanner to run at higher count rates without incurring large data losses due to the overlapping of scintillation signals. This correction technique utilizes a reference pulse to extract timing and energy information for most pile-up events. Using pulses acquired from a Zecotech Photonics MAPD-N with an LFS-3 scintillator, we show that good timing and energy information can be achieved in the presence of pile-up utilizing a moderate amount of FPGA resources.

  15. An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

    Directory of Open Access Journals (Sweden)

    Lai Chiu-Keng

    2016-01-01

    Full Text Available A Field Programmable Gate Array based system is a great hardware platform to support the implementation of hardware controllers such as PID controller and fuzzy controller. It is also programmed as hardware accelerator to speed up the mathematic calculation and greatly enhance the performance as applied to motor drive and motion control. Furthermore, the open structure of FPGA-based system is suitable for those designs with the ability of parallel processing or soft code processor embedded. In this paper, we apply the FPGA to a multi-axis velocity controller design. The developed system integrated three functions inside the FPGA chip, which are respectively the stepping motor drive, the multi-axis motion controller and the motion planning. Furthermore, an embedded controller with a soft code processor compatible to 8051 micro-control unit (MCU is built to handle the data transfer between the FPGA board and host PC. The MCU is also used to initialize the motion control and run the interpolator. The designed system is practically applied to a XYZ motion platform which is driven by stepping motors to verify its performance.

  16. A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

    Science.gov (United States)

    Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

    2014-01-01

    This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. PMID:24379047

  17. FPGA-based trigger system for the Fermilab SeaQuest experimentz

    Energy Technology Data Exchange (ETDEWEB)

    Shiu, Shiuan-Hal, E-mail: shshiu@phys.sinica.edu.tw [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Department of Physics, National Central University, No. 300, Jhongda Rd., Jhongli District, Taoyuan City 32001, Taiwan (China); Wu, Jinyuan [Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); McClellan, Randall Evan [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Gilman, Ron [Rutgers, The State University of New Jersey, 136 Frelinghuysen Rd., Piscataway, NJ 08854 (United States); Nakano, Kenichi [Department of Physics, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550 (Japan); Peng, Jen-Chieh [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Wang, Su-Yin [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); Department of Physics, National Kaohsiung Normal University, No. 62, Shenjhong Rd.,Yanchao Township, Kaohsiung County 824, Taiwan (China)

    2015-12-01

    The SeaQuest experiment (Fermilab E906) detects pairs of energetic μ{sup +} and μ{sup −} produced in 120 GeV/c proton–nucleon interactions in a high rate environment. The trigger system consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined against pre-determined trigger matrices to identify candidate muon tracks. Information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.

  18. Using Multiple FPGA Architectures for Real-time Processing of Low-level Machine Vision Functions

    Science.gov (United States)

    Thomas H. Drayer; William E. King; Philip A. Araman; Joseph G. Tront; Richard W. Conners

    1995-01-01

    In this paper, we investigate the use of multiple Field Programmable Gate Array (FPGA) architectures for real-time machine vision processing. The use of FPGAs for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented...

  19. Perspektivy dynamické rekonfigurace programovatelných polí FPGA

    Czech Academy of Sciences Publication Activity Database

    Matoušek, Rudolf; Daněk, Martin; Kubátová, H.

    2006-01-01

    Roč. 54, č. 4 (2006), s. 3-6 ISSN 0036-9942 R&D Projects: GA ČR GA102/04/2137 Grant - others:Evropská komise(BE) IST-2001-34016 Institutional research plan: CEZ:AV0Z10750506 Keywords : FPGA * dynamic reconfiguration * digital design Subject RIV: JC - Computer Hardware ; Software

  20. Parallel Hough Transform-Based Straight Line Detection and Its FPGA Implementation in Embedded Vision

    Directory of Open Access Journals (Sweden)

    Nam Ling

    2013-07-01

    Full Text Available Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

  1. A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration

    DEFF Research Database (Denmark)

    Cardarilli, Gian Carlo; Di Carlo, Leonardo; Nannarelli, Alberto

    2016-01-01

    of the accelerators preliminarily requires also the profiling of both the SW (ARM CPU + NEON Units) and HW (FPGA) performance, an evaluation of the partial reconfiguration times and the development of an applicationspecific IP-cores library. This paper focuses on the profiling aspect of both the SW and HW...

  2. Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Jain, Vishal; Sharma, Rashmi

    2017-01-01

    In this work, we are going to analyze the effect of main supply voltage, auxiliary supply voltage, local voltage of different power bank, and supply voltage in GTX transceiver and BRAM on power dissipation of our FIR design using Verilog during implementation on 28nm FPGA. We have also taken three...

  3. Analysis of FPGA filter in Computed Tomography Images for Radioactive Dose Reduction

    International Nuclear Information System (INIS)

    Parcero, E.; Vidal, V.; Verdu, G.; Arnal, J.; Mayo, P.

    2014-01-01

    In this study, different filtering methods are compared on an image of mini-MIAS database (consisting of a collection of mammographic images). Methods employees are PGFM (Peer Group Fuzzy Metric), NDF (Non-linear Diffusion Method) a combination of these two, and FPGA (Fuzzy Peer Group Average). (Author)

  4. ModelSim/Simulink Cosimulation and FPGA Realization of a Multiaxis Motion Controller

    Directory of Open Access Journals (Sweden)

    Ying-Shieh Kung

    2015-01-01

    Full Text Available This paper is to implement a multiaxis servo controller and a motion trajectory planning within one chip. At first, SoPC (system on a programmable chip technology which is composed of an Altera FPGA (field programmable gate arrays chip and an embedded soft-core Nios II processor is taken as the development of a multiaxis motion control IC. The multiaxis motion control IC has two modules. The first module is Nios II processor which realizes the motion trajectory planning by software. It includes the step, circular, window, star, and helical motion trajectory. The second module presents a function of the multiaxis position/speed/current controller IP (intellectual property by hardware. And VHDL (VHSIC Hardware Description Language is applied to describe the multiaxis servo controller behavior. Before the FPGA realization, a cosimulation work by ModelSim/Simulink is applied to test the VHDL code. Then, this IP combined by Nios II processor will be downloaded to FPGA. Therefore, a fully digital multiaxis motion controller can be realized by a single FPGA chip. Finally, to verify the effectiveness and correctness of the proposed multiaxis motion control IP, a three-axis motion platform (XYZ table is constructed and some experimental results are presented.

  5. FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG

    Science.gov (United States)

    2014-06-01

    is normalized to π. The proposed burst-mode architecture is written in VHDL and verified using Modelsim. The VHDL design is implemented on a Xilinx...FPGA synchronization has almost identical performance to the MATLAB results. This validates our simplifications and choice of proper bit-widths in VHDL

  6. Design and Implementation of Radar Cross-Section Models on a Virtex-6 FPGA

    Directory of Open Access Journals (Sweden)

    B. U. V. Prashanth

    2014-01-01

    Full Text Available The simulation of radar cross-section (RCS models in FPGA is illustrated. The models adopted are the Swerling ones. Radar cross-section (RCS which is also termed as echo area gives the amount of scattered power from a target towards the radar. This paper elucidates the simulation of RCS to represent the specified targets under different conditions, namely, aspect angle and frequency. This model is used for the performance evaluation of radar. RCS models have been developed for various targets like simple objects to complex objects like aircrafts, missiles, tanks, and so forth. First, the model was developed in MATLAB real time simulation environment and after successful verification, the same was implemented in FPGA. Xilinx ISE software was used for VHDL coding. This simulation model was used for the testing of a radar system. The results were compared with MATLAB simulations and FPGA based timing diagrams and RTL synthesis. The paper illustrates the simulation of various target radar cross-section (RCS models. These models are simulated in MATLAB and in FPGA, with the aim of implementing them efficiently on a radar system. This method can be generalized to apply to objects of arbitrary geometry for the two configurations of transmitter and receiver in the same as well as different locations.

  7. FPGA Based Efficient Design of Traffic Light Controller using Frequency Scaling for Family of HSTL

    DEFF Research Database (Denmark)

    Sharma, Shivani; Khan, Sadiq; Das, Bhagwan

    2016-01-01

    utilizes least amount of power and is well tested in hardware using Xilinx Virtex6 Field Programmable gate array. FPGA designs are not only cheaper than ASIC designs but have many positive features like speed and performance. So the factors that contribute to power consumption for family of HSTL...

  8. FPGA Based High Speed Data Acquisition System for Electrical Impedance Tomography

    Science.gov (United States)

    Khan, S.; Borsic, A.; Manwaring, Preston; Hartov, Alexander; Halter, Ryan

    2013-04-01

    Electrical Impedance Tomography (EIT) systems are used to image tissue bio-impedance. EIT provides a number of features making it attractive for use as a medical imaging device including the ability to image fast physiological processes (>60 Hz), to meet a range of clinical imaging needs through varying electrode geometries and configurations, to impart only non-ionizing radiation to a patient, and to map the significant electrical property contrasts present between numerous benign and pathological tissues. To leverage these potential advantages for medical imaging, we developed a modular 32 channel data acquisition (DAQ) system using National Instruments' PXI chassis, along with FPGA, ADC, Signal Generator and Timing and Synchronization modules. To achieve high frame rates, signal demodulation and spectral characteristics of higher order harmonics were computed using dedicated FFT-hardware built into the FPGA module. By offloading the computing onto FPGA, we were able to achieve a reduction in throughput required between the FPGA and PC by a factor of 32:1. A custom designed analog front end (AFE) was used to interface electrodes with our system. Our system is wideband, and capable of acquiring data for input signal frequencies ranging from 100 Hz to 12 MHz. The modular design of both the hardware and software will allow this system to be flexibly configured for the particular clinical application.

  9. FPGA Based Low Power DES Algorithm Design And Implementation using HTML Technology

    DEFF Research Database (Denmark)

    Thind, Vandana; Pandey, Bishwajeet; Kalia, Kartik

    2016-01-01

    In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL...

  10. Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system

    Science.gov (United States)

    Chen, Yi-Pin; Chang, Chia-Yuan; Chen, Shean-Jen

    2018-02-01

    In this study, a field programmable gate array (FPGA)-based Shack-Hartmann wavefront sensor (SHWS) programmed on LabVIEW can be highly integrated into customized applications such as adaptive optics system (AOS) for performing real-time wavefront measurement. Further, a Camera Link frame grabber embedded with FPGA is adopted to enhance the sensor speed reacting to variation considering its advantage of the highest data transmission bandwidth. Instead of waiting for a frame image to be captured by the FPGA, the Shack-Hartmann algorithm are implemented in parallel processing blocks design and let the image data transmission synchronize with the wavefront reconstruction. On the other hand, we design a mechanism to control the deformable mirror in the same FPGA and verify the Shack-Hartmann sensor speed by controlling the frequency of the deformable mirror dynamic surface deformation. Currently, this FPGAbead SHWS design can achieve a 266 Hz cyclic speed limited by the camera frame rate as well as leaves 40% logic slices for additionally flexible design.

  11. General method of synthesis by PLIC/FPGA digital devices to ...

    African Journals Online (AJOL)

    A general method is proposed to synthesize digital devices in order to perform discrete orthogonal transformations (DOT) on programmable logic integrated circuits (PLIC) of FPGA class. The basic and the most "slow" operation during DOT performance is the operation of multiplying by a constant factor (constant) - OMC.

  12. Development of a prototype acquisition and data processing system based on FPGA

    International Nuclear Information System (INIS)

    Romero, L; Bellino, P

    2012-01-01

    We present the first stage of the expansion and improvement of a signal acquisition system based on FPGA. This system will acquire and process signals from nuclear detectors working in both pulse and current mode. The aim of this development is to unify all the actual systems for physical measurements in nuclear facilities and reactors (author)

  13. Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications

    Science.gov (United States)

    2013-12-01

    Board PAL programmable array logic PCB printed circuit board PLA programmable logic array PLD programmable logic device PLL phase -locked...FPGA Resources used for three different sequencer designs Sequencer Design Type Resource Single Manual TMR Software TMR Inverters 6 6 6 Two...using a three -input LUT. ........................................................84 Figure 62. RTL schematic produced following synthesis of a timer

  14. Erkundungen im Spannungsfeld von Pädagogik, Spielspass und technischer Machbarkeit. Gedanken zur Konzeption und Entwicklung spielbasierter digitaler Lernumgebung

    Directory of Open Access Journals (Sweden)

    Florian Berger

    2009-02-01

    Full Text Available Computerspiele sind heute aus der digitalen Medienwelt nicht mehr wegzudenken. Ihre rasante technische Entwicklung sowie ihre hohe Akzeptanz in der Jugendkultur werfen Fragen nach pädagogischer Verwertbarkeit dieses Mediums auf. Auf diesem Gebiet besteht Forschungsbedarf: Für den Einsatz aktueller Spielkonzepte als Lehrmittel existieren keine fundierten Theorien oder Konzepte. Der schöpferische Umgang mit Spielen durch Anwender («Emergent Gameplay» bietet hier durch sein hohes Motivationspotential einen vielversprechenden Ansatz. Die oft wenig beachtete Rolle der digitalen Spielen zugrunde liegenden Softwaretechnik sollte stärkere Berücksichtigung finden: Es existiert einerseits ein für die Akzeptanz beim Anwender notwendiges Minimum, andererseits ist der Einsatz des aktuellen technischen «state of the art» für die Umsetzung pädagogischer und didaktischer Ambitionen durch seine enormen Anforderungen wenig zielführend. Im Ergebnis sind Idee und Spielspass das Mass auch für Anwendungen des Game Based Learn­ing.

  15. ICE: A Scalable, Low-Cost FPGA-Based Telescope Signal Processing and Networking System

    Science.gov (United States)

    Bandura, K.; Bender, A. N.; Cliche, J. F.; de Haan, T.; Dobbs, M. A.; Gilbert, A. J.; Griffin, S.; Hsyu, G.; Ittah, D.; Parra, J. Mena; Montgomery, J.; Pinsonneault-Marotte, T.; Siegel, S.; Smecher, G.; Tang, Q. Y.; Vanderlinde, K.; Whitehorn, N.

    2016-03-01

    We present an overview of the ‘ICE’ hardware and software framework that implements large arrays of interconnected field-programmable gate array (FPGA)-based data acquisition, signal processing and networking nodes economically. The system was conceived for application to radio, millimeter and sub-millimeter telescope readout systems that have requirements beyond typical off-the-shelf processing systems, such as careful control of interference signals produced by the digital electronics, and clocking of all elements in the system from a single precise observatory-derived oscillator. A new generation of telescopes operating at these frequency bands and designed with a vastly increased emphasis on digital signal processing to support their detector multiplexing technology or high-bandwidth correlators — data rates exceeding a terabyte per second — are becoming common. The ICE system is built around a custom FPGA motherboard that makes use of an Xilinx Kintex-7 FPGA and ARM-based co-processor. The system is specialized for specific applications through software, firmware and custom mezzanine daughter boards that interface to the FPGA through the industry-standard FPGA mezzanine card (FMC) specifications. For high density applications, the motherboards are packaged in 16-slot crates with ICE backplanes that implement a low-cost passive full-mesh network between the motherboards in a crate, allow high bandwidth interconnection between crates and enable data offload to a computer cluster. A Python-based control software library automatically detects and operates the hardware in the array. Examples of specific telescope applications of the ICE framework are presented, namely the frequency-multiplexed bolometer readout systems used for the South Pole Telescope (SPT) and Simons Array and the digitizer, F-engine, and networking engine for the Canadian Hydrogen Intensity Mapping Experiment (CHIME) and Hydrogen Intensity and Real-time Analysis eXperiment (HIRAX) radio

  16. FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods

    Directory of Open Access Journals (Sweden)

    Bakos Jason D

    2010-04-01

    Full Text Available Abstract Background Likelihood (ML-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a Field Programmable Gate Array (FPGA-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. Results We use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10× speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture. Conclusions Heterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs 1.

  17. Bio-Inspired Controller on an FPGA Applied to Closed-Loop Diaphragmatic Stimulation.

    Science.gov (United States)

    Zbrzeski, Adeline; Bornat, Yannick; Hillen, Brian; Siu, Ricardo; Abbas, James; Jung, Ranu; Renaud, Sylvie

    2016-01-01

    Cervical spinal cord injury can disrupt connections between the brain respiratory network and the respiratory muscles which can lead to partial or complete loss of ventilatory control and require ventilatory assistance. Unlike current open-loop technology, a closed-loop diaphragmatic pacing system could overcome the drawbacks of manual titration as well as respond to changing ventilation requirements. We present an original bio-inspired assistive technology for real-time ventilation assistance, implemented in a digital configurable Field Programmable Gate Array (FPGA). The bio-inspired controller, which is a spiking neural network (SNN) inspired by the medullary respiratory network, is as robust as a classic controller while having a flexible, low-power and low-cost hardware design. The system was simulated in MATLAB with FPGA-specific constraints and tested with a computational model of rat breathing; the model reproduced experimentally collected respiratory data in eupneic animals. The open-loop version of the bio-inspired controller was implemented on the FPGA. Electrical test bench characterizations confirmed the system functionality. Open and closed-loop paradigm simulations were simulated to test the FPGA system real-time behavior using the rat computational model. The closed-loop system monitors breathing and changes in respiratory demands to drive diaphragmatic stimulation. The simulated results inform future acute animal experiments and constitute the first step toward the development of a neuromorphic, adaptive, compact, low-power, implantable device. The bio-inspired hardware design optimizes the FPGA resource and time costs while harnessing the computational power of spike-based neuromorphic hardware. Its real-time feature makes it suitable for in vivo applications.

  18. Bio-Inspired Controller on an FPGA Applied to Closed-Loop Diaphragmatic Stimulation

    Science.gov (United States)

    Zbrzeski, Adeline; Bornat, Yannick; Hillen, Brian; Siu, Ricardo; Abbas, James; Jung, Ranu; Renaud, Sylvie

    2016-01-01

    Cervical spinal cord injury can disrupt connections between the brain respiratory network and the respiratory muscles which can lead to partial or complete loss of ventilatory control and require ventilatory assistance. Unlike current open-loop technology, a closed-loop diaphragmatic pacing system could overcome the drawbacks of manual titration as well as respond to changing ventilation requirements. We present an original bio-inspired assistive technology for real-time ventilation assistance, implemented in a digital configurable Field Programmable Gate Array (FPGA). The bio-inspired controller, which is a spiking neural network (SNN) inspired by the medullary respiratory network, is as robust as a classic controller while having a flexible, low-power and low-cost hardware design. The system was simulated in MATLAB with FPGA-specific constraints and tested with a computational model of rat breathing; the model reproduced experimentally collected respiratory data in eupneic animals. The open-loop version of the bio-inspired controller was implemented on the FPGA. Electrical test bench characterizations confirmed the system functionality. Open and closed-loop paradigm simulations were simulated to test the FPGA system real-time behavior using the rat computational model. The closed-loop system monitors breathing and changes in respiratory demands to drive diaphragmatic stimulation. The simulated results inform future acute animal experiments and constitute the first step toward the development of a neuromorphic, adaptive, compact, low-power, implantable device. The bio-inspired hardware design optimizes the FPGA resource and time costs while harnessing the computational power of spike-based neuromorphic hardware. Its real-time feature makes it suitable for in vivo applications. PMID:27378844

  19. FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods.

    Science.gov (United States)

    Zierke, Stephanie; Bakos, Jason D

    2010-04-12

    Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF) is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a Field Programmable Gate Array (FPGA)-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. We use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10x speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture. Heterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs).

  20. Test results of an ITER relevant FPGA when irradiated with neutrons

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J. N.; Santos, Bruno; Fernandes, Ana; Goncalves, Bruno [Instituto de Plasmas e Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Leong, Carlos; Teixeira, Joao P. [Instituto de Engenharia de Sistemas e Computadores - Investigacao e Desenvolvimento, 1000-029 Lisboa, (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, Jose G. [Centro de Ciencias e Tecnologias Nucleares, Instituto Superior Tecnico, Universidade de Lisboa, 2695-066 Bobadela, (Portugal)

    2015-07-01

    The data acquisition and control instrumentation cubicles room of the ITER tokamak will be irradiated with neutrons during the fusion reactor operation. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of I and C products - Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), functional data stored in dedicated Block RAM (BRAM) and functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons causes soft errors, unintended changes (bit-flips) to the values stored in state elements of the FPGA. The SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA configuration memory. Novel SEU sensors with Error Correction Code (ECC) detect and repair the BRAM memories. Proper management of SEU can increase reliability and availability of control instrumentation hardware for nuclear applications. The results of the tests performed using the SEM controller and the BRAM SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU errors in the configuration and BRAM memories. (authors)

  1. Entwicklung der Körpermaße von Zuchtsauen – Konsequenzen für die Maße von Kastenständen

    Directory of Open Access Journals (Sweden)

    Eckhard Meyer

    2015-02-01

    Full Text Available Der Platz­anspruch für das Liegen im Kastenstand wurde anhand der körperlichen Entwicklung von 128 Sauen abgeleitet, die jeweils kurz vor der Abferkelung durchschnittlich über 2,5 Würfe hinweg gewogen und vermessen wurden. Die altersabhängige relative Entwicklung des Körpergewichtes (+47 % ist zwangsläufig deutlich höher als die Entwicklung der Körpermaße (+10 bis 18 %. Absolut und relativ gesehen, wachsen die Sauen mehr in die Länge und Höhe als in die Körperbreite. Auch ist die gemessene Streuung der Körperbreite geringer als die der anderen Körpermaße. Während die gesetzliche Vorgabe für den Kastenstand von 200 cm Länge bei 65 cm Breite für die Jungsauen eher reichlich ist und zu Verletzungen und Problemen mit der Buchtensauberkeit führen kann, ist die gesetzlich Vorgabe von 200 cm Länge und 70 cm Breite für ausgewachsene Altsauen knapp. Dabei ist der zusätzliche Platzanspruch nicht berücksichtigt, der sich aus der Dynamik der Körperbewegungen ergibt (+10 bis 14 %. Beim Neubau von Ställen für vergleichbar großrahmige genetische Herkünfte ergibt sich daraus für große Sauen ein lichtes Maß von etwa 80 cm Breite. Für kleinere bzw. jüngere Sauen sollte dieses mindestens einmal, besser zweimal (70 und 60 cm differenziert werden.

  2. Einfluss von Ernährungsfaktoren im ersten Lebensjahr auf die Entwicklung von Diabetes- und Zöliakie-assoziierter Autoimmunität

    OpenAIRE

    Huber, Doris

    2005-01-01

    Eine Modulation von Ernährungsfaktoren wurde als möglicher Einflussfaktor auf das Risiko für Typ 1 Diabetes-assoziierte Autoimmunität vermutet. Ziel der Arbeit war es, festzustellen, ob die Stilldauer, die Einführung von industriell hergestellter Säuglingsmilchnahrung, das Zufüttern von Beikost oder der Zeitpunkt der erstmaligen Gabe glutenhaltiger Nahrungsmittel Einfluss auf die Entwicklung von Diabetes- oder Zöliakie-assoziierten Autoantikörper haben. Als Studienkollektiv dienten 1610 Kinde...

  3. Scalable Normal Basis Arithmetic Unit for Elliptic Curve Cryptography

    Directory of Open Access Journals (Sweden)

    J. Schmidt

    2005-01-01

    Full Text Available The design of a scalable arithmetic unit for operations over elements of GF(2m represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in a single arithmetic unit. We discuss optimum design of the shifter with respect to the inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA.We present implementation data for various digit widths which exhibit a time minimum for digit width D = 15.

  4. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  5. Development of plans for retrofitting Russian housing, taking into account European competences for increasing its energy efficiency; Entwicklung von Planungs- und Sanierungskonzepten fuer den russischen Wohnungsbau

    Energy Technology Data Exchange (ETDEWEB)

    Ezhov, Andrey; Himburg, Stefan [Hochschule fuer Technik Berlin (Germany)

    2010-02-15

    There are various options for retrofitting Russian prefabricated concrete-slab buildings of the first period of industrial construction, so-called khrushchevki, with the object of bringing them up to European standards of thermal insulation technology. In the given case the basis of calculations was the German EnEV 2007 (Building Energy Conservation Ordinance). The analysis of sample building data opened up a large range of possibilities for increasing its energy efficiency. For instance, calculations ascertained that relatively inexpensive methods of enhancing a buildings thermal insulation can achieve a significant decrease in energy consumption for heating. In addition, this thesis analyzes possible variations of retrofitting and reconstruction using different types of materials and heating systems. The results clearly illustrate that residential houses e.g. type series 1-507 have a future as comfortable and functional housing space. In fact, and in contrast to common prejudices, their fate is far from hopeless. Even the climatic circumstances of a northern city such as St. Petersburg do not preclude the use of alternative energy sources such as solar energy. On the contrary, it is a conceivable method of support for heating systems. In summary, the investigations show that the retrofitting of prefabricated concrete-slab buildings of the first construction period is a sensible project, especially when taking into account the further development of fossil energy prices. In its most sophisticated form (the passive house), retrofitting will result in energy savings of up to 90 %. [German] Fuer russische Wohnhaeuser der ersten Periode des industriellen Bauens, so genannte ''Chruschtschowki'', besteht ein hoher Sanierungsbedarf. Im Rahmen der nachfolgenden Betrachtungen werden moegliche energetische Sanierungsmassnahmen fuer diese typischen russischen Wohngebaeude vorgestellt. Das Ziel ist eine Angleichung an das europaeische Waermeschutzniveau

  6. Migration of a Real-Time Optimal-Control Algorithm: From MATLAB (Trademark) to Field Programmable Gate Array (FPGA)

    National Research Council Canada - National Science Library

    Moon, II, Ron L

    2005-01-01

    ...) development environment into an FPGA-based embedded-platform development board. Research at the Naval Postgraduate School has produced a revolutionary time-optimal spacecraft control algorithm based upon the Legendre Pseudospectral method...

  7. Modeling and Simulation of a Non-Coherent Frequency Shift Keying Transceiver Using a Field Programmable Gate Array (FPGA)

    National Research Council Canada - National Science Library

    Voskakis, Konstantinos

    2008-01-01

    ...) receiver-transmitter in a Field Programmable Gate Array (FPGA). After introducing the theory behind the Non- Coherent BFSK demodulation implemented at the receiver, the design of transmitter and receiver is illustrated...

  8. Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs

    Science.gov (United States)

    Ladbury, R. L.; Berg, M. D.; Wilcox, E. P.; LaBel, K. A.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2013-01-01

    We investigate the use of commercial FPGA based evaluation boards for radiation testing DDR2 and DDR3 SDRAMs. We evaluate the resulting data quality and the tradeoffs involved in the use of these boards.

  9. FPGA Implementation of Block Parallel DF-MPIC Detectors for DS-CDMA Systems in Frequency-Nonselective Channels

    Directory of Open Access Journals (Sweden)

    Adel Omar Dahmane

    2008-01-01

    Full Text Available Multistage parallel interference cancellation- (MPIC- based detectors allow to mitigate multiple-access interference in direct-sequence code-division multiple-access (DS-CDMA systems. They are considered serious candidates for practical implementation showing a good tradeoff between performance and complexity. Better performance is obtained when decision feedback (DF is employed. Although MPIC and DF-MPIC have the same arithmetic complexity, DF-MPIC needs much more FPGA resources when compared to MPIC without decision feedback. In this letter, FPGA implementation of block parallel DF-MPIC (BP-DF-MPIC is proposed allowing better tradeoff between performance and FPGA area occupancy. To reach an uncoded bit-error rate of 10−3, BP-DF-MPIC shows a 1.5 dB improvement over the MPIC without decision feedback with only 8% increase in FPGA resources compared to 69% for DF-MPIC.

  10. Entwicklung einer Transportnäherung für das reaktordynamische Rechenprogramm DYN3D

    OpenAIRE

    Beckert, Carsten; Grundmann, Ulrich

    2010-01-01

    Es wurde eine SP3-Transportmethode entwickelt, die neutronenkinetische Rechnungen für die Kerne von Leichtwasserreaktoren mit höherer Genauigkeit als die gegenwärtig in der Kernauslegung angewandten Standardmethoden auf Basis der Zweigruppendiffusionsnäherung er-laubt. Eine Verbesserung der Genauigkeit von Abbrandrechnungen und der Berechnung von Tran-sienten ist für heterogene Kerne notwendig, in denen neben UO2-Brennelementen auch Mischoxyd – Brennelemente eingesetzt werden. In einem erste...

  11. Performance enhancement of multi-core fiber transmission using real-time FPGA based pre-emphasis

    DEFF Research Database (Denmark)

    Hasanuzzaman, G. K.M.; Spolitis, Sandis; Salgals, T.

    2017-01-01

    We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA.......We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA....

  12. FPGA implementation of a hybrid on-line process monitoring in PC based real-time systems

    Directory of Open Access Journals (Sweden)

    Jovanović Bojan

    2011-01-01

    Full Text Available This paper presents one way of FPGA implementation of hybrid (hardware-software based on-line process monitoring in Real-Time systems (RTS. The reasons for RTS monitoring are presented at the beginning. The summary of different RTS monitoring approaches along with its advantages and drawbacks are also exposed. Finally, monitoring module is described in details. Also, FPGA implementation results and some useful monitoring system applications are mentioned.

  13. Re-Form: FPGA-Powered True Codesign Flow for High-Performance Computing In The Post-Moore Era

    Energy Technology Data Exchange (ETDEWEB)

    Cappello, Franck; Yoshii, Kazutomo; Finkel, Hal; Cong, Jason

    2016-11-14

    Multicore scaling will end soon because of practical power limits. Dark silicon is becoming a major issue even more than the end of Moore’s law. In the post-Moore era, the energy efficiency of computing will be a major concern. FPGAs could be a key to maximizing the energy efficiency. In this paper we address severe challenges in the adoption of FPGA in HPC and describe “Re-form,” an FPGA-powered codesign flow.

  14. Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support

    Directory of Open Access Journals (Sweden)

    Burhan Khurshid

    2015-05-01

    Full Text Available Modern Field Programmable Gate Arrays (FPGA are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC primarily because of the low Non-recurring Engineering (NRE costs associated with FPGA platforms. This has prompted FPGA vendors to improve the capacity and flexibility of the underlying primitive fabric and include specialized macro support and intellectual property (IP cores in their offerings. However, most of the work related to FPGA implementations does not take full advantage of these offerings. This is primarily because designers rely mainly on the technology-independent optimization to enhance the performance of the system and completely neglect the speed-up that is achievable using these embedded primitives and macro support. In this paper, we consider the technology-dependent optimization of fixed-point bit-parallel multipliers by carrying out their implementations using embedded primitives and macro support that are inherent in modern day FPGAs. Our implementation targets three different FPGA families viz. Spartan-6, Virtex-4 and Virtex-5. The implementation results indicate that a considerable speed up in performance is achievable using these embedded FPGA resources.

  15. Long-term perspectives of technical and social development in Germany. Visions for research and technology policy; Langfristige Perspektiven technischer und gesellschaftlicher Entwicklung in Deutschland. Visionen fuer die Forschungs- und Technologiepolitik

    Energy Technology Data Exchange (ETDEWEB)

    Baron, W.; Zweck, A.

    1995-12-01

    This publication contains six contributions discussing the medium- and long-term perspectives of technical, social and economic development in Germany. (UA) [Deutsch] Die vorliegende Publikation enthaelt 6 Vortraege, die sich mit mittel- und langfristigen Perspektiven der technischen, sozialen und wirtschaftlichen Entwicklung in Deutschland befassen. (UA)

  16. [St. Petersburg und Livland - und die Entwicklung der estnischen Literatur : Anton Schiefner (1817-1879) und Friedrich R. Kreutzwald (1803-1882) im Briefwechsel (1853-1879)] / Felix Köther

    Index Scriptorium Estoniae

    Köther, Felix

    2015-01-01

    Arvustus: St. Petersburg und Livland - und die Entwicklung der estnischen Literatur : Anton Schiefner (1817-1879) und Friedrich R. Kreutzwald (1803-1882) im Briefwechsel (1853-1879) / bearbeitet von Hartmut Walravens. Wiesbaden : Harrassowitz, 2013. (Orientalistik-Bibliographien und Dokumentationen ; Bd. 22)

  17. Unterrichtsentwurf: Die Entwicklung eines nationalen Identitätsbewusstseins in den von Napoleon besetzten Ländern

    Directory of Open Access Journals (Sweden)

    Natalie Fridrich

    2012-05-01

    Full Text Available Nathalie Friedrichs proposes the following lesson plan for the senior classes of the German Gymnasium (grammar-school: „Die Entwicklung eines nationalen Identitätsbewusstseins in den von Napoleon besetzten Ländern“ (The Development of a National Sense of Identity in the Countries Occupied by Napeoleon.The central question, however, is whether this new German national consciousness at the dawn of the 19th century can be traced back to Napoleon’s reign in the Rhineland region or whether it emerged during the wars of liberation as a result of a firm rejection of Napoleon.The following materials will be given to the pupils beforhand: A short preparatory text with essential background information, a pithy quote , and two historical sources, namely the appeal of Ludwig Adolf Peter Graf von Sayn-Wittgenstein to support the war of liberation, and another more francophile source by the physician Adolf Kußmaul. The latter source points in the direction of a positive experience during the time of French occupation and therefore relativises the claim of a German patriotism as a direct result of the war against France. From a didactical viewpoint, the lesson aims to develop the prerequisites for a critical analysis of historical source texts and different points of view on the topic. Finally, a table listing the respective pros and cons of the Napoleonic arguments is sketched out, visualising the perspectives of the students and leading to the final discussion, which should produce answers to the questions of the role of Napoleon for the Germans.

  18. Using Simulated Partial Dynamic Run-Time Reconfiguration to Share Embedded FPGA Compute and Power Resources across a Swarm of Unpiloted Airborne Vehicles

    Directory of Open Access Journals (Sweden)

    Kearney David

    2007-01-01

    Full Text Available We show how the limited electrical power and FPGA compute resources available in a swarm of small UAVs can be shared by moving FPGA tasks from one UAV to another. A software and hardware infrastructure that supports the mobility of embedded FPGA applications on a single FPGA chip and across a group of networked FPGA chips is an integral part of the work described here. It is shown how to allocate a single FPGA's resources at run time and to share a single device through the use of application checkpointing, a memory controller, and an on-chip run-time reconfigurable network. A prototype distributed operating system is described for managing mobile applications across the swarm based on the contents of a fuzzy rule base. It can move applications between UAVs in order to equalize power use or to enable the continuous replenishment of fully fueled planes into the swarm.

  19. FPGA and optical-network-based LLRF distributed control system for TESLA-XFEL linear accelerator

    Science.gov (United States)

    Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Czarski, Tomasz; Giergusiewicz, Wojciech; Jalmuzna, Wojciech; Olowski, Krysztof; Perkuszewski, Karol; Zielinski, Jerzy; Simrock, Stefan

    2005-02-01

    The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control system for the TESLA-XFEL accelerator. The design of a system basing on the FPGA chips and multi-gigabit optical network was debated. The system design approach was fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of the, DSP enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. Initial parameters of the system model under the design are presented.

  20. Study on FPGA SEU Mitigation for the Readout Electronics of DAMPE BGO Calorimeter in Space

    Science.gov (United States)

    Shen, Zhongtao; Feng, Changqing; Gao, Shanshan; Zhang, Deliang; Jiang, Di; Liu, Shubin; An, Qi

    2015-06-01

    The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of the Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based field-programmable gate array (FPGA), of which the design-level flip-flops and embedded block random access memories (RAM) are single event upset (SEU) sensitive in the harsh space environment. To comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.

  1. Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

    Czech Academy of Sciences Publication Activity Database

    Pohl, Zdeněk; Tichý, Milan; Kadlec, Jiří

    2008-01-01

    Roč. 2008, č. 2008 (2008), s. 1-11 ISSN 1687-6172 R&D Projects: GA MŠk(CZ) 1M0567 EU Projects: European Commission(XE) 027611 - AETHER Program:FP6 Institutional research plan: CEZ:AV0Z10750506 Keywords : DSP * Least-squares lattice * order estimation * exponential forgetting factor estimation * FPGA implementation * scheduling * dynamic reconfiguration * microblaze Subject RIV: IN - Informatics, Computer Science Impact factor: 1.055, year: 2008 http://library.utia.cas.cz/separaty/2008/ZS/pohl-tichy-kadlec-implementation%20of%20the%20least-squares%20lattice%20with%20order%20and%20forgetting%20factor%20estimation%20for%20fpga.pdf

  2. A low power flash-FPGA based brain implant micro-system of PID control.

    Science.gov (United States)

    Lijuan Xia; Fattah, Nabeel; Soltan, Ahmed; Jackson, Andrew; Chester, Graeme; Degenaar, Patrick

    2017-07-01

    In this paper, we demonstrate that a low power flash FPGA based micro-system can provide a low power programmable interface for closed-loop brain implant inter- faces. The proposed micro-system receives recording local field potential (LFP) signals from an implanted probe, performs closed-loop control using a first order control system, then converts the signal into an optogenetic control stimulus pattern. Stimulus can be implemented through optoelectronic probes. The long term target is for both fundamental neuroscience applications and for clinical use in treating epilepsy. Utilizing our device, closed-loop processing consumes only 14nJ of power per PID cycle compared to 1.52μJ per cycle for a micro-controller implementation. Compared to an application specific digital integrated circuit, flash FPGA's are inherently programmable.

  3. Design and FPGA implementation of real-time automatic image enhancement algorithm

    Science.gov (United States)

    Dong, GuoWei; Hou, ZuoXun; Tang, Qi; Pan, Zheng; Li, Xin

    2016-11-01

    In order to improve image processing quality and boost processing rate, this paper proposes an real-time automatic image enhancement algorithm. It is based on the histogram equalization algorithm and the piecewise linear enhancement algorithm, and it calculate the relationship of the histogram and the piecewise linear function by analyzing the histogram distribution for adaptive image enhancement. Furthermore, the corresponding FPGA processing modules are designed to implement the methods. Especially, the high-performance parallel pipelined technology and inner potential parallel processing ability of the modules are paid more attention to ensure the real-time processing ability of the complete system. The simulations and the experimentations show that the algorithm is based on the design and implementation of FPGA hardware circuit less cost on hardware, high real-time performance, the good processing performance in different sceneries. The algorithm can effectively improve the image quality, and would have wide prospect on imaging processing field.

  4. Optimization of high speed pipelining in FPGA-based FIR filter design using genetic algorithm

    Science.gov (United States)

    Meyer-Baese, Uwe; Botella, Guillermo; Romero, David E. T.; Kumm, Martin

    2012-06-01

    This paper compares FPGA-based full pipelined multiplierless FIR filter design options. Comparison of Distributed Arithmetic (DA), Common Sub-Expression (CSE) sharing and n-dimensional Reduced Adder Graph (RAG-n) multiplierless filter design methods in term of size, speed, and A*T product are provided. Since DA designs are table-based and CSE/RAG-n designs are adder-based, FPGA synthesis design data are used for a realistic comparison. Superior results of a genetic algorithm based optimization of pipeline registers and non-output fundamental coefficients are shown. FIR filters (posted as open source by Kastner et al.) for filters in the length from 6 to 151 coefficients are used.

  5. FPGA implementation of adaptive ANN controller for speed regulation of permanent magnet stepper motor drives

    International Nuclear Information System (INIS)

    Hasanien, Hany M.

    2011-01-01

    This paper presents a novel adaptive artificial neural network (ANN) controller, which applies on permanent magnet stepper motor (PMSM) for regulating its speed. The dynamic response of the PMSM with the proposed controller is studied during the starting process under the full load torque and under load disturbance. The effectiveness of the proposed adaptive ANN controller is then compared with that of the conventional PI controller. The proposed methodology solves the problem of nonlinearities and load changes of PMSM drives. The proposed controller ensures fast and accurate dynamic response with an excellent steady state performance. Matlab/Simulink tool is used for this dynamic simulation study. The main contribution of this work is the implementation of the proposed controller on field programmable gate array (FPGA) hardware to drive the stepper motor. The driver is built on FPGA Spartan-3E Starter from Xilinx. Experimental results are presented to demonstrate the validity and effectiveness of the proposed control scheme.

  6. An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC

    CERN Document Server

    Ballester, F J; Gras, J J; Lewis, J; Savioz, J J; Serrano, J

    2003-01-01

    The Beam Synchronous Timing system (BST) will be used around the LHC and its injector, the SPS, to broadcast timing meassages and synchronize actions with the beam in different receivers. To achieve beam synchronization, the BST Master card encodes messages using the bunch clock, with a nominal value of 40.079 MHz for the LHC. These messages are produced by a set of tasks every revolution period, which is every 89 us for the LHC and every 23 us for the SPS, therefore imposing a hard real-time constraint on the system. To achieve determinism, the BST Master uses a dedicated CPU inside its main Field Programmable Gate Array (FPGA) featuring zero-delay hardware task switching and a reduced instruction set. This paper describes the BST Master card, stressing the main FPGA design, as well as the associated software, including the LynxOS driver and the tailor-made assembler.

  7. An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

    Directory of Open Access Journals (Sweden)

    Y. H. Lee

    2016-01-01

    Full Text Available Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

  8. An FPGA-Based Pulse Pile-up Rejection Technique for Photon Counting Imaging Detectors

    International Nuclear Information System (INIS)

    Hu Kun; Li Feng; Chen Lian; Jin Ge; Liang Fu-Tian

    2015-01-01

    A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. The method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are introduced in detail. The photon counting imaging detector comprises a micro-channel plate (MCP) stack, and a wedge and strip anode (WSA). The resolution mask pattern in front of the MCP can be reconstructed after data processing in the FPGA. For high count rates, the rejection design can effectively reduce the impact of the pulse pile-up on the image. The resolution can reach up to 140 μm. The pulse pile-up rejection design can also be applied to high-energy physics and particle detection. (paper)

  9. Design Navigation Computer System Based on Double Digital Signal Process and FPGA

    Directory of Open Access Journals (Sweden)

    Jie Yan

    2013-03-01

    Full Text Available The article describes the design and implementation of integrated navigation embedded computer system based on double DSP and FPGA. In the system, TMS320C6727 (C6727 and TMS320C6713 (C6713 digital signal processor (DSP, which produced by TI are used as the core processing chip. C6727 is responsibility to de-noising the inertial measurement unit (IMU original signal, and send the IMU data to C6713. C6713 is responsibility to collect the IMU and GNSS data, run navigation algorithm and send the navigation information to other implements. The I/0 interface, timing control, data buffering and address bus decoding modes are implemented in FPGA. This design can improve the system real-time performance and reliability.

  10. Ternary and Multi-Bit FIR Filter Area-Performance Tradeoffs in FPGA

    Directory of Open Access Journals (Sweden)

    Khalil-Ur-Rahman Dayo

    2013-01-01

    Full Text Available In this paper, performance and area of conventional FIR (Finite Impulse Responce filters versus ternary sigma delta modulated FIR filter is compared in FPGA (Field Programmable Gate Arrays using VHDL (Verilog Description Language. Two different approaches were designed and synthesized at same spectral performance by obtaining a TIR (Target Impulse Response. Both filters were synthesized on adaptive LUT (Look Up Table FPGA device in pipelined and non-pipelined modes. It is shown that the Ternary FIR filter occupies approximately the same area as the corresponding multi-bit filter, but for a given specification, the ternary FIR filter has 32% better performance in non-pipelined and 72% in pipelined mode, compared to its equivalent Multi-Bit filter at its optimum 12-bit coefficient quantization. These promising results shows that ternary logic based (i.e. +1,0,-1 filters can be used for huge chip area savings and higher performance.

  11. FPGA based hardware optimized implementation of signal processing system for LFM pulsed radar

    Science.gov (United States)

    Azim, Noor ul; Jun, Wang

    2016-11-01

    Signal processing is one of the main parts of any radar system. Different signal processing algorithms are used to extract information about different parameters like range, speed, direction etc, of a target in the field of radar communication. This paper presents LFM (Linear Frequency Modulation) pulsed radar signal processing algorithms which are used to improve target detection, range resolution and to estimate the speed of a target. Firstly, these algorithms are simulated in MATLAB to verify the concept and theory. After the conceptual verification in MATLAB, the simulation is converted into implementation on hardware using Xilinx FPGA. Chosen FPGA is Xilinx Virtex-6 (XC6LVX75T). For hardware implementation pipeline optimization is adopted and also other factors are considered for resources optimization in the process of implementation. Focusing algorithms in this work for improving target detection, range resolution and speed estimation are hardware optimized fast convolution processing based pulse compression and pulse Doppler processing.

  12. Comparing an FPGA to a Cell for an Image Processing Application

    Directory of Open Access Journals (Sweden)

    Robert W. Ives

    2010-01-01

    Full Text Available Modern advancements in configurable hardware, most notably Field-Programmable Gate Arrays (FPGAs, have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. On the other hand, PlayStation3 (PS3 game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high performance. In this research project, our aim is to study the differences in performance of a modern image processing algorithm on these two hardware platforms. In particular, Iris Recognition Systems have recently become an attractive identification method because of their extremely high accuracy. Iris matching, a repeatedly executed portion of a modern iris recognition algorithm, is parallelized on an FPGA system and a Cell processor. We demonstrate a 2.5 times speedup of the parallelized algorithm on the FPGA system when compared to a Cell processor-based version.

  13. 10~Gbps TCP/IP streams from the FPGA for High Energy Physics

    CERN Document Server

    Bauer, Gerry; Branson, James; Chaze, Olivier; Cittolin, Sergio; Coarasa Perez, Jose Antonio; Darlea, Georgiana Lavinia; Deldicque, Christian; Dobson, Marc; Dupont, Aymeric; Erhan, Samim; Gigi, Dominique; Glege, Frank; Gomez Ceballos, Guillelmo; Gomez-Reino Garrido, Robert; Hartl, Christian; Hegeman, Jeroen Guido; Holzner, Andre Georg; Masetti, Lorenzo; Meijers, Franciscus; Meschi, Emilio; Mommsen, Remigius; Morovic, Srecko; Nunez Barranco Fernandez, Carlos; O'Dell, Vivian; Orsini, Luciano; Ozga, Wojciech Andrzej; Paus, Christoph Maria Ernst; Petrucci, Andrea; Pieri, Marco; Racz, Attila; Raginel, Olivier; Sakulin, Hannes; Sani, Matteo; Schwick, Christoph; Spataru, Andrei Cristian; Stieger, Benjamin Bastian; Sumorok, Konstanty; Veverka, Jan; Wakefield, Christopher Colin; Zejdl, Petr

    2014-01-01

    The DAQ system of the CMS experiment at CERN collects data from more than 600 custom detector Front-End Drivers (FEDs). During 2013 and 2014 the CMS DAQ system will undergo a major upgrade to address the obsolescence of current hardware and the requirements posed by the upgrade of the LHC accelerator and various detector components. For a loss-less data collection from the FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. To limit the TCP hardware implementation complexity the DAQ group developed a simplified and unidirectional but RFC~793 compliant version of the TCP protocol. This allows to use a PC with the standard Linux TCP/IP stack as a receiver. We present the challenges and protocol modifications made to TCP in order to simplify its FPGA implementation. We also describe the interaction between the simplified TCP and Linux TCP/IP stack including the performance measurements.

  14. 10 Gbps TCP/IP streams from the FPGA for High Energy Physics

    Science.gov (United States)

    Bauer, Gerry; Bawej, Tomasz; Behrens, Ulf; Branson, James; Chaze, Olivier; Cittolin, Sergio; Coarasa, Jose Antonio; Darlea, Georgiana-Lavinia; Deldicque, Christian; Dobson, Marc; Dupont, Aymeric; Erhan, Samim; Gigi, Dominique; Glege, Frank; Gomez-Ceballos, Guillelmo; Gomez-Reino, Robert; Hartl, Christian; Hegeman, Jeroen; Holzner, Andre; Masetti, Lorenzo; Meijers, Frans; Meschi, Emilio; Mommsen, Remigius K.; Morovic, Srecko; Nunez-Barranco-Fernandez, Carlos; O'Dell, Vivian; Orsini, Luciano; Ozga, Wojciech; Paus, Christoph; Petrucci, Andrea; Pieri, Marco; Racz, Attila; Raginel, Olivier; Sakulin, Hannes; Sani, Matteo; Schwick, Christoph; Cristian Spataru, Andrei; Stieger, Benjamin; Sumorok, Konstanty; Veverka, Jan; Wakefield, Christopher Colin; Zejdl, Petr

    2014-06-01

    The DAQ system of the CMS experiment at CERN collects data from more than 600 custom detector Front-End Drivers (FEDs). During 2013 and 2014 the CMS DAQ system will undergo a major upgrade to address the obsolescence of current hardware and the requirements posed by the upgrade of the LHC accelerator and various detector components. For a loss-less data collection from the FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. To limit the TCP hardware implementation complexity the DAQ group developed a simplified and unidirectional but RFC 793 compliant version of the TCP protocol. This allows to use a PC with the standard Linux TCP/IP stack as a receiver. We present the challenges and protocol modifications made to TCP in order to simplify its FPGA implementation. We also describe the interaction between the simplified TCP and Linux TCP/IP stack including the performance measurements.

  15. 10 Gbps TCP/IP streams from the FPGA for High Energy Physics

    International Nuclear Information System (INIS)

    Bauer, Gerry; Darlea, Georgiana-Lavinia; Gomez-Ceballos, Guillelmo; Bawej, Tomasz; Chaze, Olivier; Coarasa, Jose Antonio; Deldicque, Christian; Dobson, Marc; Dupont, Aymeric; Gigi, Dominique; Glege, Frank; Gomez-Reino, Robert; Hartl, Christian; Hegeman, Jeroen; Masetti, Lorenzo; Behrens, Ulf; Branson, James; Cittolin, Sergio; Holzner, Andre; Erhan, Samim

    2014-01-01

    The DAQ system of the CMS experiment at CERN collects data from more than 600 custom detector Front-End Drivers (FEDs). During 2013 and 2014 the CMS DAQ system will undergo a major upgrade to address the obsolescence of current hardware and the requirements posed by the upgrade of the LHC accelerator and various detector components. For a loss-less data collection from the FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10 Gbps Ethernet has been developed. To limit the TCP hardware implementation complexity the DAQ group developed a simplified and unidirectional but RFC 793 compliant version of the TCP protocol. This allows to use a PC with the standard Linux TCP/IP stack as a receiver. We present the challenges and protocol modifications made to TCP in order to simplify its FPGA implementation. We also describe the interaction between the simplified TCP and Linux TCP/IP stack including the performance measurements.

  16. Embedded Linux on FPGA instruments for control interface and remote management

    International Nuclear Information System (INIS)

    Huang, B.K.; Naylor, G.; Cunningham, G.; Goudard, O.; Harrison, J.; Myers, R.M.; Sharples, R.M.; Vann, R.G.L.

    2012-01-01

    FPGAs are now large enough that they can easily accommodate an embedded 32-bit processor which can be used to significantly extend the capability of an FPGA system. Running embedded Linux gives the user many more options for interfacing to their FPGA-based instrument, and in some cases this enables removal of the middle-person PC. It is possible to manage the instrument directly by ModBus (130 Hz poll rate and 6.6 ms latency) and Stark-Stream (42 MB/s transfer and 83 MB/s raw throughput), and use these protocols as a low level layer to communicate with EPICS or TANGO. Additionally it is possible to use the embedded processor to facilitate remote updating of firmware which, in combination with a watchdog and network booting ensures that full remote management over Ethernet is possible. (authors)

  17. Detection of Small Sized GEO Debris Using FPGA Based Stacking Method

    Science.gov (United States)

    Yanagisawa, Toshifumi; Hanada, Toshiya; Kurosaki, Hirohisa; Kitazawa, Yukihito; Uetsuhara, Masahiko; Kinoshita, Daisuke

    2012-07-01

    In order to detect faint moving objects such as space debris, asteroids and comet, a FPGA based analysis method has been developed. The original stacking method, which uses multiple images to improve signal-to-noise ratio and runs as a software on PC, has a disadvantage of taking enormous time to analyze. A new algorithm and its installation into a FPGA board solved the problem by reducing analysis time about one thousandth. A collaborative observation between Japan and Taiwan was conducted to search for undiscovered debris fragments generated from a breakup event of US Titan IIIC Transtage. A lot of fragments that may be related to the breakup were discovered by analyzing with the method which verifies the effectiveness of the method.

  18. Fuzzy logic type 1 and type 2 based on LabVIEW FPGA

    CERN Document Server

    Ponce-Cruz, Pedro; MacCleery, Brian

    2016-01-01

    This book is a comprehensive introduction to LabVIEW FPGA™, a package allowing the programming of intelligent digital controllers in field programmable gate arrays (FPGAs) using graphical code. It shows how both potential difficulties with understanding and programming in VHDL and the consequent difficulty and slowness of implementation can be sidestepped. The text includes a clear theoretical explanation of fuzzy logic (type 1 and type 2) with case studies that implement the theory and systematically demonstrate the implementation process. It goes on to describe basic and advanced levels of programming LabVIEW FPGA and show how implementation of fuzzy-logic control in FPGAs improves system responses. A complete toolkit for implementing fuzzy controllers in LabVIEW FPGA has been developed with the book so that readers can generate new fuzzy controllers and deploy them immediately. Problems and their solutions allow readers to practice the techniques and to absorb the theoretical ideas as they arise. Fuzzy L...

  19. MIMO Fading Emulator Development with FPGA and Its Application to Performance Evaluation of Mobile Radio Systems

    Directory of Open Access Journals (Sweden)

    Yoshio Karasawa

    2017-01-01

    Full Text Available We present four new developments for a multiple-input multiple-output (MIMO over-the-air measurement system based on our previous studies. The first two developments relate to the channel model for multipath environment generation. One is a further simplification of the circuit configuration without performance degradation by reducing the number of delay generation units, which dominate the performance limit when implementing the circuit on a field-programmable gate array (FPGA. The other is to realize spatial correlation characteristics among the input ports on the transmission side, whereas the previously proposed channel model did not consider this correlation. The third development involves the details of implementing the MIMO fading emulator on an FPGA as a two-stage scheme. The fourth is the demonstration of application examples of the developed system.

  20. Design of RF Heat Therapy System Based on DS18B20 and FPGA

    Directory of Open Access Journals (Sweden)

    Liangyu Su

    2014-09-01

    Full Text Available In the process of research and development of this subject, it compares the three major heat physics technology. According to the organizational characteristics of glioma, it uses radiofrequency capacitive heating method. For conventional temperature sensor’s interchangeability and unstable control method faults, it designed an implement RF heat treatment temperature field measure and temperature control system which use high precision digital temperature sensor DS18B20 and programmable logic device FPGA. This system contains temperature setting, temperature display, control algorithm, the FPGA chip configuration, signal power amplifier and the control of DS18B20 function. Finally, this system is used for pork to record the temperature field of heating experiments of center, edge and surface temperature.

  1. Design issues on using FPGA-based I and C systems in nuclear reactors

    Energy Technology Data Exchange (ETDEWEB)

    Farias, Marcos S.; Carvalho, Paulo Victor R. de; Santos, Isaac Jose A.L. dos; Lacerda, Fabio de, E-mail: msantana@ien.gov.br, E-mail: paulov@ien.gov.br, E-mail: luquetti@ien.gov.br, E-mail: acerda@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Div. de Engenharia Nuclear

    2015-07-01

    The FPGA (field programmable gate array) is widely used in various fields of industry. FPGAs can be used to perform functions that are safety critical and require high reliability, like in automobiles, aircraft control and assistance and mission-critical applications in the aerospace industry. With these merits, FPGAs are receiving increased attention worldwide for application in nuclear plant instrumentation and control (I and C) systems, mainly for Reactor Protection System (RPS). Reasons for this include the fact that conventional analog electronics technologies are become obsolete. I and C systems of new Reactors have been designed to adopt the digital equipment such as PLC (Programmable Logic Controller) and DCS (Distributed Control System). But microprocessors-based systems may not be simply qualified because of its complex characteristics. For example, microprocessor cores execute one instruction at a time, and an operating system is needed to manage the execution of programs. In turn, FPGAs can run without an operating system and the design architecture is inherently parallel. In this paper we aim to assess these and other advantages, and the limitations, on FPGA-based solutions, considering the design guidelines and regulations on the use of FPGAs in Nuclear Plant I and C Systems. We will also examine some circuit design techniques in FPGA to help mitigate failures and provide redundancy. The objective is to show how FPGA-based systems can provide cost-effective options for I and C systems in modernization projects and to the RMB (Brazilian Multipurpose Reactor), ensuring safe and reliable operation, meeting licensing requirements, such as separation, redundancy and diversity. (author)

  2. Digital Component Separator for future W-CDMA-LINC Transmitters implemented on an FPGA

    OpenAIRE

    Gerhard, W.; Knöchel, R.

    2005-01-01

    This paper presents the implementation of a Digital-Component-Separator (DCS) for a LINC-transmitter (linear amplification using nonlinear components) on an FPGA (field programmable gate array). It investigates and estimates the bandwidth requirements for such a LINC system. The influence of bandwidth limitations on a digitally based LINC-transmitter for W-CDMA utilization is studied by simulations. Furthermore a LINC transmitter is proposed which employs a flexible image-reject- or a direct ...

  3. Efficient Design and Implementation of a Multivariate Takagi-Sugeno Fuzzy Controller on an FPGA

    OpenAIRE

    Aguilar, Abiel; Pérez, Madaín; Camas, Jorge,; Hernández, Héctor,; Ríos, Carlos

    2014-01-01

    International audience; his article describes the design and efficient implementation of a Takagi Sugeno multivariable Fuzzy Logic Controller. The application selected is a temperature and humidity controller for a chicken incubator. This design was elaborated using VHDL applying intermediate simulations in order to check for functional verification of all modules integrating the controller. The created circuit was implemented on FPGA Cyclone II EP2C35F672C6 assembled in breadboard Altera DE2...

  4. A Real-Time Embedded System for Stereo Vision Preprocessing Using an FPGA

    DEFF Research Database (Denmark)

    Kjær-Nielsen, Anders; Jensen, Lars Baunegaard With; Sørensen, Anders Stengaard

    2008-01-01

    In this paper a low level vision processing node for use in existing IEEE 1394 camera setups is presented. The processing node is a small embedded system, that utilizes an FPGA to perform stereo vision preprocessing at rates limited by the bandwidth of IEEE 1394a (400Mbit). The system is used...... extraction, and undistortion and rectification. The latency of the system when running at 2x15fps is 30ms....

  5. FPGA implementation of high-frequency multiple PWM for variable voltage variable frequency controller

    Energy Technology Data Exchange (ETDEWEB)

    Boumaaraf, Abdelâali, E-mail: aboumaaraf@yahoo.fr [Université Abbès Laghrour, Laboratoire des capteurs, Instrumentations et procédés (LCIP), Khenchela (Algeria); University of Farhat Abbas Setif1, Sétif, 19000 (Algeria); Mohamadi, Tayeb [University of Farhat Abbas Setif1, Sétif, 19000 (Algeria); Gourmat, Laïd [Université Abbès Laghrour, Khenchela, 40000 (Algeria)

    2016-07-25

    In this paper, we present the FPGA implementation of the multiple pulse width modulation (MPWM) signal generation with repetition of data segments, applied to the variable frequency variable voltage systems and specially at to the photovoltaic water pumping system, in order to generate a signal command very easily between 10 Hz to 60 Hz with a small frequency and reduce the cost of the control system.

  6. FPGA implementation of high-frequency multiple PWM for variable voltage variable frequency controller

    International Nuclear Information System (INIS)

    Boumaaraf, Abdelâali; Mohamadi, Tayeb; Gourmat, Laïd

    2016-01-01

    In this paper, we present the FPGA implementation of the multiple pulse width modulation (MPWM) signal generation with repetition of data segments, applied to the variable frequency variable voltage systems and specially at to the photovoltaic water pumping system, in order to generate a signal command very easily between 10 Hz to 60 Hz with a small frequency and reduce the cost of the control system.

  7. Design, development and characterisation of a FPGA platform for multi-motor electric vehicle control

    OpenAIRE

    de castro, r; araujo, re; oliveira, h

    2009-01-01

    Two three-phase squirrel-cage induction motors are used as a propulsion system of an electric vehicle (EV). A simple XC3S1000 FPGA is used to simultaneously control both electric motors, with field oriented control and space vector modulation techniques. To electronically distribute the torque between the two electric motors, a simple, yet effective, strategy based on a uniform torque distribution has been implemented. Experimental results obtained with a multi-motor EV prototype demonstrate ...

  8. BJT detector with FPGA-based read-out for alpha particle monitoring

    Energy Technology Data Exchange (ETDEWEB)

    Tyzhnevyi, V; Dalla Betta, G-F [Universita di Trento, via Sommarive, 14, 38123 Trento (Italy); Rovati, L [Universita di Modena e Reggio Emilia, via Vignolese 905, 41125 Modena (Italy); Verzellesi, G [Universita di Modena e Reggio Emilia, via Amendola 2, Pad. Morselli, 42100 Reggio Emilia (Italy); Zorzi, N, E-mail: tyzhnevyi@disi.unitn.it [Fondazione Bruno Kessler, via Sommarive, 18, 38123 Trento (Italy)

    2011-01-15

    In this work we introduce a new prototype of readout electronics (ALPHADET), which was designed for an {alpha}-particle detection system based on a bipolar junction transistor (BJT) detector. The system uses an FPGA, which provides many advantages at the stage of prototyping and testing the detector. The main design and electrical features of the board are discussed in this paper, along with selected results from the characterization of ALPHADET coupled to BJT detectors.

  9. DDR3 memory integration for a softcore in a new radiation hardened FPGA technology

    OpenAIRE

    Castro Leiva, Luis Alfonso

    2017-01-01

    New and more capable electronics are required to push forward future space missions, and to pursue this goal the first step is the evaluation of novel technologies. The present thesis tackles the problem of evaluating new FPGA and memory technologies for spaceborne missions, while assessing its benefits and improvements. In this project, a novel soft SoC design based on the existing MDPA device was proposed and implemented. The new design includes a memory controller for the DDR3 technology, ...

  10. A Translator Verification Technique for FPGA Software Development in Nuclear Power Plants

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Jae Yeob; Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of)

    2014-10-15

    Although the FPGAs give a high performance than PLC (Programmable Logic Controller), the platform change from PLC to FPGA impose all PLC software engineers give up their experience, knowledge and practices accumulated over decades, and start a new FPGA-based hardware development from scratch. We have researched to fine the solution to this problem reducing the risk and preserving the experience and knowledge. One solution is to use the FBDtoVerilog translator, which translates the FBD programs into behavior-preserving Verilog programs. In general, the PLCs are usually designed with an FBD, while the FPGAs are described with a HDL (Hardware Description Language) such as Verilog or VHDL. Once PLC designer designed the FBD programs, the FBDtoVerilog translates the FBD into Verilog, mechanically. The designers, therefore, need not consider the rest of FPGA development process (e.g., Synthesis and Place and Routing) and can preserve the accumulated experience and knowledge. Even if we assure that the translation from FBD to Verilog is correct, it must be verified rigorously and thoroughly since it is used in nuclear power plants, which is one of the most safety critical systems. While the designer develops the FPGA software with the FBD program translated by the translator, there are other translation tools such as synthesis tool and place and routing tool. This paper also focuses to verify them rigorously and thoroughly. There are several verification techniques for correctness of translator, but they are hard to apply because of the outrageous cost and performance time. Instead, this paper tries to use an indirect verification technique for demonstrating the correctness of translator using the co-simulation technique. We intend to prove only against specific inputs which are under development for a target I and C system, not against all possible input cases.

  11. Design and Implementation of Radar Cross-Section Models on a Virtex-6 FPGA

    OpenAIRE

    Prashanth, B. U. V.

    2014-01-01

    The simulation of radar cross-section (RCS) models in FPGA is illustrated. The models adopted are the Swerling ones. Radar cross-section (RCS) which is also termed as echo area gives the amount of scattered power from a target towards the radar. This paper elucidates the simulation of RCS to represent the specified targets under different conditions, namely, aspect angle and frequency. This model is used for the performance evaluation of radar. RCS models have been developed for various targ...

  12. A novel integrated renewable energy system modelling approach, allowing fast FPGA controller prototyping

    DEFF Research Database (Denmark)

    Teodorescu, Remus; Ruiz, Alberto Parera; Cirstea, Marcian

    2008-01-01

    The paper describes a new holistic approach to the modeling of integrated renewable energy systems. The method is using the DK5 modeling/design environment from Celoxica and is based on the new Handel-C programming language. The goal of the work carried out was to achieve a combined model...... containing a Xilinx Spartan II FPGA and was successfully experimentally tested. This approach enables the design and fast hardware implementation of efficient controllers for Distributed Energy Resource (DER) hybrid systems....

  13. FPGA-based voltage and current dual drive system for high frame rate electrical impedance tomography.

    Science.gov (United States)

    Khan, Shadab; Manwaring, Preston; Borsic, Andrea; Halter, Ryan

    2015-04-01

    Electrical impedance tomography (EIT) is used to image the electrical property distribution of a tissue under test. An EIT system comprises complex hardware and software modules, which are typically designed for a specific application. Upgrading these modules is a time-consuming process, and requires rigorous testing to ensure proper functioning of new modules with the existing ones. To this end, we developed a modular and reconfigurable data acquisition (DAQ) system using National Instruments' (NI) hardware and software modules, which offer inherent compatibility over generations of hardware and software revisions. The system can be configured to use up to 32-channels. This EIT system can be used to interchangeably apply current or voltage signal, and measure the tissue response in a semi-parallel fashion. A novel signal averaging algorithm, and 512-point fast Fourier transform (FFT) computation block was implemented on the FPGA. FFT output bins were classified as signal or noise. Signal bins constitute a tissue's response to a pure or mixed tone signal. Signal bins' data can be used for traditional applications, as well as synchronous frequency-difference imaging. Noise bins were used to compute noise power on the FPGA. Noise power represents a metric of signal quality, and can be used to ensure proper tissue-electrode contact. Allocation of these computationally expensive tasks to the FPGA reduced the required bandwidth between PC, and the FPGA for high frame rate EIT. In 16-channel configuration, with a signal-averaging factor of 8, the DAQ frame rate at 100 kHz exceeded 110 frames s (-1), and signal-to-noise ratio exceeded 90 dB across the spectrum. Reciprocity error was found to be for frequencies up to 1 MHz. Static imaging experiments were performed on a high-conductivity inclusion placed in a saline filled tank; the inclusion was clearly localized in the reconstructions obtained for both absolute current and voltage mode data.

  14. Adaptation of a Fault-Tolerant Fpga-Based Launch Sequencer as a Cubesat Payload Processor

    Science.gov (United States)

    2014-06-01

    ns shown in Figure 42. In the BEQ instruction, both ALU operands are compared to determine the branch conditions have been met. These outputs are...130  3.  Second ALU Operand Multiplexer (multiplex_2to1_nbit) ..........130  4.  Immediate Offset Shifting Module (shift_left2... conditions within the design. Like GTMR, ITMR requires additional FPGA resources for voting but effectively eliminates SEUs and SETs in the

  15. FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm

    OpenAIRE

    BLOCK, Henry; MARUYAMA, Tsutomu

    2017-01-01

    In this paper, we present an FPGA hardware implementation for a phylogenetic tree reconstruction with a maximum parsimony algorithm. We base our approach on a particular stochastic local search algorithm that uses the Progressive Neighborhood and the Indirect Calculation of Tree Lengths method. This method is widely used for the acceleration of the phylogenetic tree reconstruction algorithm in software. In our implementation, we define a tree structure and accelerate the search by parallel an...

  16. BJT detector with FPGA-based read-out for alpha particle monitoring

    International Nuclear Information System (INIS)

    Tyzhnevyi, V; Dalla Betta, G-F; Rovati, L; Verzellesi, G; Zorzi, N

    2011-01-01

    In this work we introduce a new prototype of readout electronics (ALPHADET), which was designed for an α-particle detection system based on a bipolar junction transistor (BJT) detector. The system uses an FPGA, which provides many advantages at the stage of prototyping and testing the detector. The main design and electrical features of the board are discussed in this paper, along with selected results from the characterization of ALPHADET coupled to BJT detectors.

  17. Deep-pipelined FPGA implementation of ellipse estimation for eye tracking

    OpenAIRE

    Dohi, Keisuke; Hatanaka, Yuma; Negi, Kazuhiro; Shibata, Yuichiro; Oguri, Kiyoshi

    2012-01-01

    This paper presents a deep-pipelined FPGA implementation of real-time ellipse estimation for eye tracking. The system is constructed by the Starburst algorithm on a stream-oriented architecture and the RANSAC algorithm without any external memories. In particular, the paper presents comparative results between three different hypothesis generators for the RANSAC algorithm based on Cramer's rule, Gauss-Jordan elimination and LU decomposition. Comparison criteria include resource usage, through...

  18. Design and implementation of STD32-BUS based reactor protection trip unit on FPGA imbaby

    International Nuclear Information System (INIS)

    Mahmoud, I.; Elnokity, O.A.; Refai, M.K.

    2007-01-01

    This paper presents a way to design and implement the Trip Unit of a Reactor Protection System (RPS) using a Field Programmable Gate Arrays (FPGA). Instead of the traditional embedded Microprocessor based interface design method, a proposed tailor made FPGA based circuit is built to substitute the Trip Unit (TL1) existing in Egypt's 2' ' Research reactor ETRR-2. The existing embedded system is built around the STD32 field Computer Bus which used in industrial and process control applications. It is modular, rugged, reliable, and easy-to-use and is able to support a large mix of I/O cards and to easily change its configuration in the future. Therefore, the state machine of this bus is extracted from its timing diagrams and implemented in VHDL to interface the designed TU circuit. The proposed designed circuit implemented using ALTERA EPF10K10LC84-3 chip replaces the Single Board Computer which have the embedded SAY program of the TU providing the same integrated HAV and SAV functions implemented in FPGA Chip housed in an printed circuit board, which uses the same shape and specifications of STD32 boards. H/W implementation of both TU and STD32 Bus in VHDL addresses the issues of safety and reusability

  19. Rapid Prototyping of Sub-band Acoustic Echo Cancellers on FPGA Platforms

    Directory of Open Access Journals (Sweden)

    TOPA, M. D.

    2013-08-01

    Full Text Available The paper focuses on a rapid prototyping technique of an acoustic echo canceller implemented on an FPGA platform. The goal is to reduce design, optimization and implementation cost and execution time. In complex signal processing applications, high-order adaptive filter structures suffer from decreased convergence speed and high computational complexity. The sub-band adaptive filtering technique is able to eliminate these disadvantages. The execution time of the echo cancellation in an acoustic enclosure is decreased using multi-rate digital signal processing. To speed-up the execution time of a common acoustic echo canceller, the sub-band decomposition of the source signal is proposed. Here, this procedure is implemented using the Xilinx System Generator library. The hardware implementation of the well-known NLMS adaptive algorithm was carried out. Moreover, the FIR filters in the analysis and synthesis banks are designed with the window method (using the Kaiser window, as the determination of the filter's coefficients is an important procedure to eliminate the alias. The alias occurs due to the usage of multi-rate systems. Hardware implementations that test the behavior of the proposed system were tested for nonstationary input signals. Results show superior tracking abilities of the designed system. Also, an estimation of the FPGA resources is established in each case. The ML501 Xilinx FPGA development board was used for its specific digital signal processing facilities.

  20. Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

    Directory of Open Access Journals (Sweden)

    Sanjay Singh

    2017-06-01

    Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

  1. A fast improved fat tree encoder for wave union TDC in an FPGA

    International Nuclear Information System (INIS)

    Shen Qi; Zhao Lei; Liu Shubin; Qi Binxiang; Hu Xueye; An Qi; Liao Shengkai; Peng Chengzhi

    2013-01-01

    Up to now, the wave union method can achieve the best timing performance in FPGA-based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands that the encoder convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder (IFTE) to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constraints were required; therefore, this IFTE structure could also be further applied in other delay-chain-based FPGA TDCs. (authors)

  2. Study on modulation amplitude stabilization method for PEM based on FPGA in atomic magnetometer

    Science.gov (United States)

    Wang, Qinghua; Quan, Wei; Duan, Lihong

    2017-10-01

    Atomic magnetometer which uses atoms as sensitive elements have ultra-high precision and has wide applications in scientific researches. The photoelastic modulation method based on photoelastic modulator (PEM) is used in the atomic magnetometer to detect the small optical rotation angle of a linearly polarized light. However, the modulation amplitude of the PEM will drift due to the environmental factors, which reduces the precision and long-term stability of the atomic magnetometer. Consequently, stabilizing the PEM's modulation amplitude is essential to precision measurement. In this paper, a modulation amplitude stabilization method for PEM based on Field Programmable Gate Array (FPGA) is proposed. The designed control system contains an optical setup and an electrical part. The optical setup is used to measure the PEM's modulation amplitude. The FPGA chip, with the PID control algorithm implemented in it, is used as the electrical part's micro controller. The closed loop control method based on the photoelastic modulation detection system can directly measure the PEM's modulation amplitude in real time, without increasing the additional optical devices. In addition, the operating speed of the modulation amplitude stabilization control system can be greatly improved because of the FPGA's parallel computing feature, and the PID control algorithm ensures flexibility to meet different needs of the PEM's modulation amplitude set values. The Modelsim simulation results show the correctness of the PID control algorithm, and the long-term stability of the PEM's modulation amplitude reaches 0.35% in a 3-hour continuous measurement.

  3. Multichannel FPGA based MVT system for high precision time (20 ps RMS) and charge measurement

    Science.gov (United States)

    Pałka, M.; Strzempek, P.; Korcyl, G.; Bednarski, T.; Niedźwiecki, Sz.; Białas, P.; Czerwiński, E.; Dulski, K.; Gajos, A.; Głowacz, B.; Gorgol, M.; Jasińska, B.; Kamińska, D.; Kajetanowicz, M.; Kowalski, P.; Kozik, T.; Krzemień, W.; Kubicz, E.; Mohhamed, M.; Raczyński, L.; Rudy, Z.; Rundel, O.; Salabura, P.; Sharma, N. G.; Silarski, M.; Smyrski, J.; Strzelecki, A.; Wieczorek, A.; Wiślicki, W.; Zieliński, M.; Zgardzińska, B.; Moskal, P.

    2017-08-01

    In this article it is presented an FPGA based Multi-Voltage Threshold (MVT) system which allows of sampling fast signals (1-2 ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time measurement of 20 ps RMS and reconstruct charge of signals, using a simple approach, with deviation from real value smaller than 10%. Utilization of the differential inputs of an FPGA chip as comparators together with an implementation of a TDC inside an FPGA allowed us to achieve a compact multi-channel system characterized by low power consumption and low production costs. This paper describes realization and functioning of the system comprising 192-channel TDC board and a four mezzanine cards which split incoming signals and discriminate them. The boards have been used to validate a newly developed Time-of-Flight Positron Emission Tomography system based on plastic scintillators. The achieved full system time resolution of σ(TOF) ≈ 68 ps is by factor of two better with respect to the current TOF-PET systems.

  4. Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System

    Directory of Open Access Journals (Sweden)

    Douglas L. Maskell

    2007-01-01

    Full Text Available A method of constructing prerouted FPGA cores, which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing systems, is presented. Two major challenges are considered: how to manage the wires crossing a core's borders; and how to maintain an acceptable level of flexibility for system construction with only a minimum of overhead. In order to maintain FPGA computing performance, it is crucial to thoroughly analyze the issues at the lowest level of device detail in order to ensure that computing circuit encapsulation is as efficient as possible. We present the first methodology that allows a core to scale its interface bandwidth to the maximum available in a routing channel. Cores can be constructed independently from the rest of the system using a framework that is independent of the method used to place and route primitive components within the core. We use an abstract FPGA model and CAD tools that mirror those used in industry. An academic design flow has been modified to include a wire policy and an interface constraints framework that tightly constrains the use of the wires that cross a core's boundaries. Using this tool set we investigate the effect of prerouting on overall system optimality. Abutting cores are instantly connected by colocation of interface wires. Eliminating run-time routing drastically reduces the time taken to construct a system using a set of cores.

  5. FPGA based phase detection technique for electron density measurement in SST-1 tokamak

    Energy Technology Data Exchange (ETDEWEB)

    Pramila, E-mail: pramila@ipr.res.in; Mandaliya, Hitesh; Rajpal, Rachana; Kaur, Rajwinder

    2016-11-15

    A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper.

  6. FPGA BASED ASYNCHRONOUS PIPELINED MB-OFDM UWB TRANSMITTER BACKEND MODULES

    Directory of Open Access Journals (Sweden)

    M. Santhi

    2010-03-01

    Full Text Available In this paper, a novel scheme is proposed which comprises the advantages of asynchronous pipelining techniques and the advantages of FPGAs for implementing a 200Mbps MB-OFDM UWB transmitter digital backend modules. In asynchronous pipelined system, registers are used as in synchronous system. But they are controlled by handshaking signals. Since FPGAs are rich in registers, design and implementation of asynchronous pipelined MBOFDM UWB transmitter on FPGA using four-phase bundled-data protocol is considered in this paper. Novel ideas have also been proposed for designing asynchronous OFDM using Modified Radix-24 SDF and asynchronous interleaver using two RAM banks. Implementation has been performed on ALTERA STRATIX II EP2S60F1020C4 FPGA and it is operating at a speed of 350MHz. It is assured that the proposed MB-OFDM UWB system can be made to work on STRATIX III device with the operating frequency of 528MHz in compliance to the ECMA-368 standard. The proposed scheme is also applicable for FPGA from other vendors and ASIC.

  7. Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

    Directory of Open Access Journals (Sweden)

    Chiung-Wei Huang

    2018-01-01

    Full Text Available We propose a prototype of field programmable gate array (FPGA implementation for optimal pixel adjustment process (OPAP algorithm of image steganography. In the proposed scheme, the cover image and the secret message are transmitted from a personal computer (PC to an FPGA board using RS232 interface for hardware processing. We firstly embed k-bit secret message into each pixel of the cover image by the last-significant-bit (LSB substitution method, followed by executing associated OPAP calculations to construct a stego pixel. After all pixels of the cover image have been embedded, a stego image is created and transmitted from FPGA back to the PC and stored in the PC. Moreover, we have extended the basic pixel-wise structure to a parallel structure which can fully use the hardware devices to speed up the embedding process and embed several bits of secret message at the same time. Through parallel mechanism of the hardware based design, the data hiding process can be completed in few clock cycles to produce steganography outcome. Experimental results show the effectiveness and correctness of the proposed scheme.

  8. Fine-grained parallel RNAalifold algorithm for RNA secondary structure prediction on FPGA.

    Science.gov (United States)

    Xia, Fei; Dou, Yong; Zhou, Xingming; Yang, Xuejun; Xu, Jiaqing; Zhang, Yang

    2009-01-30

    In the field of RNA secondary structure prediction, the RNAalifold algorithm is one of the most popular methods using free energy minimization. However, general-purpose computers including parallel computers or multi-core computers exhibit parallel efficiency of no more than 50%. Field Programmable Gate-Array (FPGA) chips provide a new approach to accelerate RNAalifold by exploiting fine-grained custom design. RNAalifold shows complicated data dependences, in which the dependence distance is variable, and the dependence direction is also across two dimensions. We propose a systolic array structure including one master Processing Element (PE) and multiple slave PEs for fine grain hardware implementation on FPGA. We exploit data reuse schemes to reduce the need to load energy matrices from external memory. We also propose several methods to reduce energy table parameter size by 80%. To our knowledge, our implementation with 16 PEs is the only FPGA accelerator implementing the complete RNAalifold algorithm. The experimental results show a factor of 12.2 speedup over the RNAalifold (ViennaPackage - 1.6.5) software for a group of aligned RNA sequences with 2981-residue running on a Personal Computer (PC) platform with Pentium 4 2.6 GHz CPU.

  9. Design of area array CCD image acquisition and display system based on FPGA

    Science.gov (United States)

    Li, Lei; Zhang, Ning; Li, Tianting; Pan, Yue; Dai, Yuming

    2014-09-01

    With the development of science and technology, CCD(Charge-coupled Device) has been widely applied in various fields and plays an important role in the modern sensing system, therefore researching a real-time image acquisition and display plan based on CCD device has great significance. This paper introduces an image data acquisition and display system of area array CCD based on FPGA. Several key technical challenges and problems of the system have also been analyzed and followed solutions put forward .The FPGA works as the core processing unit in the system that controls the integral time sequence .The ICX285AL area array CCD image sensor produced by SONY Corporation has been used in the system. The FPGA works to complete the driver of the area array CCD, then analog front end (AFE) processes the signal of the CCD image, including amplification, filtering, noise elimination, CDS correlation double sampling, etc. AD9945 produced by ADI Corporation to convert analog signal to digital signal. Developed Camera Link high-speed data transmission circuit, and completed the PC-end software design of the image acquisition, and realized the real-time display of images. The result through practical testing indicates that the system in the image acquisition and control is stable and reliable, and the indicators meet the actual project requirements.

  10. Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

    Directory of Open Access Journals (Sweden)

    Manuel Saldaña

    2012-01-01

    Full Text Available Partial reconfiguration (PR is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the system continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this paper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to allow hardware designers to create template bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused for multiple applications. As an example of the generality of this approach, four different applications that use the same template bitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired application engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines. PR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by some examples and preliminary PR overhead measurements.

  11. Three-dimensional design methodologies for tree-based FPGA architecture

    CERN Document Server

    Pangracious, Vinod; Mehrez, Habib

    2015-01-01

    This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

  12. FPGA - Based Technology and Systems for I and C of Existing and Advanced Reactors

    International Nuclear Information System (INIS)

    Bachmach, E.; Siora, O.; Tokarev, V.; Reshetytsky, S.; Kharchenko, V.; Bezsalyi, V.

    2011-01-01

    Control systems of modern nuclear installations (including water-cooled, WCR) are based on programmable technologies. Most of control systems modernizations which are implemented at operating nuclear installations are also based on application of programmable technologies. Besides, a range of features and properties is defied for programmable technologies. These features and properties make licensing process more complicated, facilitate appearance of common cause failures, make safety evaluation procedures more complicated, etc. Also it is known that programmable technologies significantly extend the time periods for project realization of new power units construction and modernization of the existing power units, and also it involves rise of its value. Company RADIY has developed the Platform of digital equipment RADIY on FPGA-based technology. In the article there is a description of the features of FPGA-technology developed and applied by Company RADIY, features of the Platform RADIY and systems realized on its base, which allow to minimize significantly above-mentioned negative features and properties of programmable technologies. Technology which realized in Platform RADIY allows to solve the whole set of tasks of control (including regulation) and protection of nuclear installations. Platform RADIY is a combination of the best features of traditional programmable technologies and FPGA-technology. According to the opinion of the authors of this article the technology which is realized in Platform RADIY is the key factor for solving of control and protection tasks of nuclear installations in the nearest future. (author)

  13. FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations

    Directory of Open Access Journals (Sweden)

    KAZMI, M.

    2015-02-01

    Full Text Available Image processing systems based on neighborhood operations i.e. Neighborhood Processing Systems (NPSs are computationally expensive and memory intensive. Field Programmable Gate Array (FPGA based parallel processing architectures accelerate calculations of NPS provided if they have fast external-memory data access by using on-chip data buffers. The conventional data buffers namely full Row Buffers (RBs implemented with FPGA embedded memory resources i.e. Block RAMs (BRAMs are resource inefficient. It makes overall NPS implementation on FPGA expensive and infeasible especially for resource-constraint environment. This paper presents compact and efficient image buffering architecture with an additional feature of pre-fetching. Proposed design fits in minimal BRAMs by using small yet efficient Main Control Unit (MCU. Its optimal multi-rated BRAM data accessing technique reduces BRAM cost to provide multiple pixels of pre-fetched data/clock to NPS in a fixed pattern. It controls and synchronizes BRAMs operations to attain throughput of 1 clock/pixel. Thus our buffer architecture with 66% reduction in BRAM requirement as compared to conventional RBs is capable to support buffering for real time systems with high resolution (1080x1920@62fps. Therefore proposed buffer architecture can suitably replace conventional RB in any real time NPS application.

  14. Design and implementation of a programming circuit in radiation-hardened FPGA

    International Nuclear Information System (INIS)

    Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Chen, Stanley L.

    2011-01-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 x 10 5 rad(Si), dose rate survivability of 1.5 x 10 11 rad(Si)/s and neutron fluence immunity of 1 x 10 14 n/cm 2 .

  15. Implementing a real-time chain of segmentation of images on a multi-FPGA architecture

    Science.gov (United States)

    Akil, Mohamed; Zahirazami, Shahram

    1998-03-01

    In this paper we present the study and the implementation of an optimized chain of segmentation operators. We implemented this chain in real time, consisting of a Deriche contour detection, double threshold, closing of contours and finally region labeling, on a multi-FPGA architecture. This architecture has four processing FPGAs and four memory modules. Deriche operator, closing of contours and labeling occupy each one an FPGA. Double threshold and detection of the extremities filled partially the forth FPGA. The slowest component of the chain is Deriche operator which can go up to 11.4 Mhz, assuring the process of an image every 40 ms. Deriche operator tries to extract the contours by assuming that a contour is a step super positioned by a white gaussian noise. Our implementation consists of a smoothing part of four second order filters and a Sobel as a derivation part. The second order filters are causal and non-causal horizontal and vertical operators. The gradient image passes through a double threshold filter to select the real contours and the crests and the background pixels. Closing of contours eliminates the false crests and finally the labeling gives a unique label to each closed region. The latency of the chain is in the order of three images. This implementation shows the efficiency of the chain and also it demonstrates the capabilities of our architecture as a prototyping system.

  16. V&V Plan for FPGA-based ESF-CCS Using System Engineering Approach.

    Science.gov (United States)

    Maerani, Restu; Mayaka, Joyce; El Akrat, Mohamed; Cheon, Jung Jae

    2018-02-01

    Instrumentation and Control (I&C) systems play an important role in maintaining the safety of Nuclear Power Plant (NPP) operation. However, most current I&C safety systems are based on Programmable Logic Controller (PLC) hardware, which is difficult to verify and validate, and is susceptible to software common cause failure. Therefore, a plan for the replacement of the PLC-based safety systems, such as the Engineered Safety Feature - Component Control System (ESF-CCS), with Field Programmable Gate Arrays (FPGA) is needed. By using a systems engineering approach, which ensures traceability in every phase of the life cycle, from system requirements, design implementation to verification and validation, the system development is guaranteed to be in line with the regulatory requirements. The Verification process will ensure that the customer and stakeholder’s needs are satisfied in a high quality, trustworthy, cost efficient and schedule compliant manner throughout a system’s entire life cycle. The benefit of the V&V plan is to ensure that the FPGA based ESF-CCS is correctly built, and to ensure that the measurement of performance indicators has positive feedback that “do we do the right thing” during the re-engineering process of the FPGA based ESF-CCS.

  17. Hazard Analysis of Software Requirements Specification for Process Module of FPGA-based Controllers in NPP

    Energy Technology Data Exchange (ETDEWEB)

    Jung; Sejin; Kim, Eui-Sub; Yoo, Junbeom [Konkuk University, Seoul (Korea, Republic of); Keum, Jong Yong; Lee, Jang-Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2016-10-15

    Software in PLC, FPGA which are used to develop I and C system also should be analyzed to hazards and risks before used. NUREG/CR-6430 proposes the method for performing software hazard analysis. It suggests analysis technique for software affected hazards and it reveals that software hazard analysis should be performed with the aspects of software life cycle such as requirements analysis, design, detailed design, implements. It also provides the guide phrases for applying software hazard analysis. HAZOP (Hazard and operability analysis) is one of the analysis technique which is introduced in NUREG/CR-6430 and it is useful technique to use guide phrases. HAZOP is sometimes used to analyze the safety of software. Analysis method of NUREG/CR-6430 had been used in Korea nuclear power plant software for PLC development. Appropriate guide phrases and analysis process are selected to apply efficiently and NUREG/CR-6430 provides applicable methods for software hazard analysis is identified in these researches. We perform software hazard analysis of FPGA software requirements specification with two approaches which are NUREG/CR-6430 and HAZOP with using general GW. We also perform the comparative analysis with them. NUREG/CR-6430 approach has several pros and cons comparing with the HAZOP with general guide words and approach. It is enough applicable to analyze the software requirements specification of FPGA.

  18. A Spartan 6 FPGA-based data acquisition system for dedicated imagers in nuclear medicine

    International Nuclear Information System (INIS)

    Fysikopoulos, E; Matsopoulos, G; Loudos, G; Georgiou, M; David, S

    2012-01-01

    We present the development of a four-channel low-cost hardware system for data acquisition, with application in dedicated nuclear medicine imagers. A 12 bit octal channel high-speed analogue to digital converter, with up to 65 Msps sampling rate, was used for the digitization of analogue signals. The digitized data are fed into a field programmable gate array (FPGA), which contains an interface to a bank of double data rate 2 (DDR2)-type memory. The FPGA processes the digitized data and stores the results into the DDR2. An ethernet link was used for data transmission to a personal computer. The embedded system was designed using Xilinx's embedded development kit (EDK) and was based on Xilinx's Microblaze soft-core processor. The system has been evaluated using two different discrete optical detector arrays (a position-sensitive photomultiplier tube and a silicon photomultiplier) with two different pixelated scintillator arrays (BGO, LSO:Ce). The energy resolution for both detectors was approximately 25%. A clear identification of all crystal elements was achieved in all cases. The data rate of the system with this implementation can reach 60 Mbits s −1 . The results have shown that this FPGA data acquisition system is a compact and flexible solution for single-photon-detection applications. (paper)

  19. Packet based serial link realized in FPGA dedicated for high resolution infrared image transmission

    Science.gov (United States)

    Bieszczad, Grzegorz

    2015-05-01

    In article the external digital interface specially designed for thermographic camera built in Military University of Technology is described. The aim of article is to illustrate challenges encountered during design process of thermal vision camera especially related to infrared data processing and transmission. Article explains main requirements for interface to transfer Infra-Red or Video digital data and describes the solution which we elaborated based on Low Voltage Differential Signaling (LVDS) physical layer and signaling scheme. Elaborated link for image transmission is built using FPGA integrated circuit with built-in high speed serial transceivers achieving up to 2500Gbps throughput. Image transmission is realized using proprietary packet protocol. Transmission protocol engine was described in VHDL language and tested in FPGA hardware. The link is able to transmit 1280x1024@60Hz 24bit video data using one signal pair. Link was tested to transmit thermal-vision camera picture to remote monitor. Construction of dedicated video link allows to reduce power consumption compared to solutions with ASIC based encoders and decoders realizing video links like DVI or packed based Display Port, with simultaneous reduction of wires needed to establish link to one pair. Article describes functions of modules integrated in FPGA design realizing several functions like: synchronization to video source, video stream packeting, interfacing transceiver module and dynamic clock generation for video standard conversion.

  20. FPGA-based TESLA cavity SIMCON DOOCS server design, implementation, and application

    Science.gov (United States)

    Rutkowski, Piotr Z.; Romaniuk, Ryszard S.; Pozniak, Krzysztof T.; Jezynski, Tomasz; Pucyk, Piotr D.; Pietrusinski, Michal; Simrock, Stefan

    2004-07-01

    A concise overview of the laboratory solution of the FPGA based TESLA cavity simulator and controller (SIMCON) is presented. The major emphasis is put in this paper on the high level part of the system. There were described the following steps of the system design and realization: solution choice, design of system components, implementing the solutions, introduction of the application, initial analysis of the working application. The paper is a first description of the working DOOCS server for the FPGA based TESLA cavity SIMCON (which is a part of the LLRF subsystem). The data gathered from the work of the DOOCS server promise for the system optimization possibilities. The server will be supplemented with the GUI in the next step of this effort. Throughout the work we will refer to the debated system as to the TESLA SIMCON DOOCS server or in short the "simcon server." The hardware layer of the TESLA cavity SIMCON (to which the designed software refers to) was realized in a single FPGA Virtex chip by Xilinx (XC2V3000 development board by Nallatech).

  1. Safety Basis Report

    International Nuclear Information System (INIS)

    R.J. Garrett

    2002-01-01

    As part of the internal Integrated Safety Management Assessment verification process, it was determined that there was a lack of documentation that summarizes the safety basis of the current Yucca Mountain Project (YMP) site characterization activities. It was noted that a safety basis would make it possible to establish a technically justifiable graded approach to the implementation of the requirements identified in the Standards/Requirements Identification Document. The Standards/Requirements Identification Documents commit a facility to compliance with specific requirements and, together with the hazard baseline documentation, provide a technical basis for ensuring that the public and workers are protected. This Safety Basis Report has been developed to establish and document the safety basis of the current site characterization activities, establish and document the hazard baseline, and provide the technical basis for identifying structures, systems, and components (SSCs) that perform functions necessary to protect the public, the worker, and the environment from hazards unique to the YMP site characterization activities. This technical basis for identifying SSCs serves as a grading process for the implementation of programs such as Conduct of Operations (DOE Order 5480.19) and the Suspect/Counterfeit Items Program. In addition, this report provides a consolidated summary of the hazards analyses processes developed to support the design, construction, and operation of the YMP site characterization facilities and, therefore, provides a tool for evaluating the safety impacts of changes to the design and operation of the YMP site characterization activities

  2. Safety Basis Report

    Energy Technology Data Exchange (ETDEWEB)

    R.J. Garrett

    2002-01-14

    As part of the internal Integrated Safety Management Assessment verification process, it was determined that there was a lack of documentation that summarizes the safety basis of the current Yucca Mountain Project (YMP) site characterization activities. It was noted that a safety basis would make it possible to establish a technically justifiable graded approach to the implementation of the requirements identified in the Standards/Requirements Identification Document. The Standards/Requirements Identification Documents commit a facility to compliance with specific requirements and, together with the hazard baseline documentation, provide a technical basis for ensuring that the public and workers are protected. This Safety Basis Report has been developed to establish and document the safety basis of the current site characterization activities, establish and document the hazard baseline, and provide the technical basis for identifying structures, systems, and components (SSCs) that perform functions necessary to protect the public, the worker, and the environment from hazards unique to the YMP site characterization activities. This technical basis for identifying SSCs serves as a grading process for the implementation of programs such as Conduct of Operations (DOE Order 5480.19) and the Suspect/Counterfeit Items Program. In addition, this report provides a consolidated summary of the hazards analyses processes developed to support the design, construction, and operation of the YMP site characterization facilities and, therefore, provides a tool for evaluating the safety impacts of changes to the design and operation of the YMP site characterization activities.

  3. Symmetry Adapted Basis Sets

    DEFF Research Database (Denmark)

    Avery, John Scales; Rettrup, Sten; Avery, James Emil

    In theoretical physics, theoretical chemistry and engineering, one often wishes to solve partial differential equations subject to a set of boundary conditions. This gives rise to eigenvalue problems of which some solutions may be very difficult to find. For example, the problem of finding...... in such problems can be much reduced by making use of symmetry-adapted basis functions. The conventional method for generating symmetry-adapted basis sets is through the application of group theory, but this can be difficult. This book describes an easier method for generating symmetry-adapted basis sets...

  4. Fpga based L-band pulse doppler radar design and implementation

    Science.gov (United States)

    Savci, Kubilay

    As its name implies RADAR (Radio Detection and Ranging) is an electromagnetic sensor used for detection and locating targets from their return signals. Radar systems propagate electromagnetic energy, from the antenna which is in part intercepted by an object. Objects reradiate a portion of energy which is captured by the radar receiver. The received signal is then processed for information extraction. Radar systems are widely used for surveillance, air security, navigation, weather hazard detection, as well as remote sensing applications. In this work, an FPGA based L-band Pulse Doppler radar prototype, which is used for target detection, localization and velocity calculation has been built and a general-purpose Pulse Doppler radar processor has been developed. This radar is a ground based stationary monopulse radar, which transmits a short pulse with a certain pulse repetition frequency (PRF). Return signals from the target are processed and information about their location and velocity is extracted. Discrete components are used for the transmitter and receiver chain. The hardware solution is based on Xilinx Virtex-6 ML605 FPGA board, responsible for the control of the radar system and the digital signal processing of the received signal, which involves Constant False Alarm Rate (CFAR) detection and Pulse Doppler processing. The algorithm is implemented in MATLAB/SIMULINK using the Xilinx System Generator for DSP tool. The field programmable gate arrays (FPGA) implementation of the radar system provides the flexibility of changing parameters such as the PRF and pulse length therefore it can be used with different radar configurations as well. A VHDL design has been developed for 1Gbit Ethernet connection to transfer digitized return signal and detection results to PC. An A-Scope software has been developed with C# programming language to display time domain radar signals and detection results on PC. Data are processed both in FPGA chip and on PC. FPGA uses fixed

  5. Optical network and FPGA/DSP based control system for free electron laser

    International Nuclear Information System (INIS)

    Romaniuk, R.S.; Pozniak, K.T.; Czarski, T.; Czuba, K.; Giergusiewicz, W.; Kasprowicz, G.; Koprek, W.

    2005-01-01

    The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to

  6. Realisation of politically desired projects on the basis of an insufficient development. A consequence of the acceptance discussion on wase incineration; Realisierung politisch erwuenschter Projekte auf Basis unzureichender Entwicklung. Eine Konsequenz der Akzeptanzdiskussion um die Abfallverbrennung

    Energy Technology Data Exchange (ETDEWEB)

    Thome-Kozmiensky, Karl J. [vivis Consult GmbH, Nietwerder (Germany)

    2008-07-01

    Despite all efforts toward waste avoidance, re-use and material utilization residual wastes remains. These residual wastes have to be treated before the deposition. This regularly is accomplished thermally after a mechanical or biological pretreatment. In Germany, the present refuse disposal exhibits an optimization potential. The well-known procedures for the refuse disposal exhibit lacks regarding its technical performance and environmental compatibility. A further development of these procedures was required. Under this aspect, the author of the contribution under consideration describes the procedures for the treatment of residual wastes, and evaluates these procedures critically.

  7. The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

    International Nuclear Information System (INIS)

    Ren, Y J; Zhu, J G; Yang, X Y; Ye, S H

    2006-01-01

    The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent

  8. Fault injection as a test method for an FPGA in charge of data readout for a large tracking detector

    International Nuclear Information System (INIS)

    Roed, K.; Alme, J.; Fehlker, D.; Helstrup, H.; Richter, M.; Roehrich, D.; Ullaland, K.

    2011-01-01

    This paper describes how fault injection has been implemented as a test method for an FPGA in an existing hardware configuration setup. As this FPGA is in charge of data readout for a large tracking detector, the reliability of this FPGA is of high importance. Due to the complexity of the readout electronics, irradiation testing is technically difficult at this stage of the system commissioning. The work presented in this paper is therefore motivated by introducing fault injection as an alternative method to characterize failures caused by SEUs. It is a method to study the effect that a configuration upset may have on the operation of the FPGA. The target platform consists of two independent modules for data acquisition and detector control functionality. Fault injection to test the response of the data acquisition module is made possible by implementing the solution as part of the detector control functionality. Correct implementation is validated by a simple shift register design. Our results demonstrate that fault injection can assist in measuring the effect of an implemented mitigation technique in the final design of the FPGA.

  9. An efficient HW and SW design of H.264 video compression, storage and playback on FPGA devices for handheld thermal imaging systems

    Science.gov (United States)

    Gunay, Omer; Ozsarac, Ismail; Kamisli, Fatih

    2017-05-01

    Video recording is an essential property of new generation military imaging systems. Playback of the stored video on the same device is also desirable as it provides several operational benefits to end users. Two very important constraints for many military imaging systems, especially for hand-held devices and thermal weapon sights, are power consumption and size. To meet these constraints, it is essential to perform most of the processing applied to the video signal, such as preprocessing, compression, storing, decoding, playback and other system functions on a single programmable chip, such as FPGA, DSP, GPU or ASIC. In this work, H.264/AVC (Advanced Video Coding) compatible video compression, storage, decoding and playback blocks are efficiently designed and implemented on FPGA platforms using FPGA fabric and Altera NIOS II soft processor. Many subblocks that are used in video encoding are also used during video decoding in order to save FPGA resources and power. Computationally complex blocks are designed using FPGA fabric, while blocks such as SD card write/read, H.264 syntax decoding and CAVLC decoding are done using NIOS processor to benefit from software flexibility. In addition, to keep power consumption low, the system was designed to require limited external memory access. The design was tested using 640x480 25 fps thermal camera on CYCLONE V FPGA, which is the ALTERA's lowest power FPGA family, and consumes lower than 40% of CYCLONE V 5CEFA7 FPGA resources on average.

  10. Development of a low-level radon reference chamber; Entwicklung einer Low-Level-Radon-Referenzkammer

    Energy Technology Data Exchange (ETDEWEB)

    Linzmaier, Diana

    2013-01-04

    The naturally occurring, radioactive noble gas radon-222 exists worldwide in different activity concentrations in the air. During the decay of radon-222, decay products are generated which are electrically charged and attach to aerosols in the air. Together with the aerosols, the radon is inhaled and exhaled by humans. While the radon is nearly completely exhaled, ca. 20 % of the inhaled aerosols remain in the lungs in one breath cycle. Due to ionizing radiation, in a chain of events, lung cancer might occur. Consequently, radon and its decay products are according to the current findings the second leading cause of lung cancer. At the workplace and in the home measurements of radon activity concentration are performed to determine the radiation exposition of humans. All measurement devices for the determination of radon activity concentration are calibrated above 1000 Bq/m{sup 3}, even though the mean value of the present investigation in Germany shows only 50 Bq/m{sup 3}. For the calibration of measurement devices in the range below 1000 Bq/m{sup 3} over a long time period, the generation of a stable reference atmosphere is presented in this work. Due to a long term calibration (t>5 days) of the measurement devices, smaller uncertainties result for the calibration factor. For the calibration procedure, a so-called low-level radon reference chamber was set up and started operation. The generation of a stable reference atmosphere is effected by means of emanation sources which consist of a radium-226 activity standard. On the basis of {gamma}-spectrometry, the effective emanation coefficient ofthe emanation sources is determined. The traceability of the activity concentration in the reference volume is realized via the activity ofthe radium-226, the emanation coefficient and the volume. With the emanation sources produced, stable reference atmospheres within the range of 150 Bq/m{sup 3} to 1900 Bq/m{sup 3} are achieved. For the realization, maintenance and

  11. Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments

    International Nuclear Information System (INIS)

    Brusati, M.; Camplani, A.; Cannon, M.; Chen, H.; Citterio, M.

    2017-01-01

    SRAM-ba8ed Field Programmable Gate Array (FPGA) logic devices arc very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. :!\\litigation techniques such as Triple Modular Redundancy (T:t\\IR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).

  12. Implementation of High Performance Microstepping Driver Using FPGA with the Aim of Realizing Accurate Control on a Linear Motion System

    Directory of Open Access Journals (Sweden)

    Farid Alidoust Aghdam

    2013-01-01

    Full Text Available This paper presents an FPGA-based microstepping driver which drives a linear motion system with a smooth and precise way. Proposed driver built on a Spartan3 FPGA (XC3S400 core development board from Xilinx. Implementation of driver realized by an FPGA and using Verilog hardware description language in the Xilinx ISE environment. The driver’s control behavior can be adapted just by altering Verilog scripts. In addition, a linear motion system developed (with 4 mm movement per motor revolution and coupled it to the stepper motor. The performance of the driver is tested by measuring the distance traveled on linear motion system. The experimental results verified using hardware-in-loop Matlab and Xilinx cosimulation method. This driver accomplishes a firm and accurate control and is responsive.

  13. Configuration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.

    CERN Document Server

    Zahid Rasheed, Awais

    2016-01-01

    First, a hardware design is created using Qsys in Quartus 16.0. Creation of the hardware design consists of configuring Hard Processor System (HPS) inside FPGA and adding necessary hardware blocks to the design. After generating the Qsys design, it is then instantiated in top level module in Verilog or VHDL. After setting up all pin assignments and adding all necessary files in the design, project is compiled to have a complete hardware design. Second part comprises full software design in correspondence with the hardware design and booting the HPS from SD card. Software includes enabling the different bridges used by HPS to communicate with FPGA, configuring FPGA from HPS and embedded application itself. Finally, everything is added in the SD card to get a complete automatic bare metal application running on the host board without any configuration what so ever.

  14. Explicit Design of FPGA-Based Coprocessors for Short-Range Force Computations in Molecular Dynamics Simulations *†

    Science.gov (United States)

    Gu, Yongfeng; VanCourt, Tom; Herbordt, Martin C.

    2008-01-01

    FPGA-based acceleration of molecular dynamics simulations (MD) has been the subject of several recent studies. The short-range force computation, which dominates the execution time, is the primary focus. Here we combine: a high level of FPGA-specific design including cell lists, systematically determined interpolation and precision, handling of exclusion, and support for MD simulations of up to 256K particles. The target system consists of a standard PC with a 2004-era COTS FPGA board. There are several innovations: new microarchitectures for several major components, including the cell list processor and the off-chip memory controller; and a novel arithmetic mode. Extensive experimentation was required to optimize precision, interpolation order, interpolation mode, table sizes, and simulation quality. We obtain a substantial speed-up over a highly tuned production MD code. PMID:19412319

  15. Explicit Design of FPGA-Based Coprocessors for Short-Range Force Computations in Molecular Dynamics Simulations.

    Science.gov (United States)

    Gu, Yongfeng; Vancourt, Tom; Herbordt, Martin C

    2008-05-01

    FPGA-based acceleration of molecular dynamics simulations (MD) has been the subject of several recent studies. The short-range force computation, which dominates the execution time, is the primary focus. Here we combine: a high level of FPGA-specific design including cell lists, systematically determined interpolation and precision, handling of exclusion, and support for MD simulations of up to 256K particles. The target system consists of a standard PC with a 2004-era COTS FPGA board. There are several innovations: new microarchitectures for several major components, including the cell list processor and the off-chip memory controller; and a novel arithmetic mode. Extensive experimentation was required to optimize precision, interpolation order, interpolation mode, table sizes, and simulation quality. We obtain a substantial speed-up over a highly tuned production MD code.

  16. From BASIS to MIRACLES

    DEFF Research Database (Denmark)

    Tsapatsaris, Nikolaos; Willendrup, Peter Kjær; E. Lechner, Ruep

    2015-01-01

    Results based on virtual instrument models for the first high-flux, high-resolution, spallation based, backscattering spectrometer, BASIS are presented in this paper. These were verified using the Monte Carlo instrument simulation packages McStas and VITESS. Excellent agreement of the neutron count...... are pivotal to the conceptual design of the next generation backscattering spectrometer, MIRACLES at the European Spallation Source....

  17. FPGA wavelet processor design using language for instruction-set architectures (LISA)

    Science.gov (United States)

    Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

    2007-04-01

    The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

  18. FPGA based Fuzzy Logic Controller for plasma position control in ADITYA Tokamak

    Energy Technology Data Exchange (ETDEWEB)

    Suratia, Pooja, E-mail: poojasuratia@yahoo.com [Electrical Engineering Department, Faculty of Technology and Engineering, The Maharaja Sayajirao University of Baroda, Kalabhavan, Vadodara 390001, Gujarat (India); Patel, Jigneshkumar, E-mail: jjp@ipr.res.in [Institute for Plasma Research, Bhat, Gandhinagar 382428, Gujarat (India); Rajpal, Rachana, E-mail: rachana@ipr.res.in [Institute for Plasma Research, Bhat, Gandhinagar 382428, Gujarat (India); Kotia, Sorum, E-mail: smkotia-eed@msubaroda.ac.in [Electrical Engineering Department, Faculty of Technology and Engineering, The Maharaja Sayajirao University of Baroda, Kalabhavan, Vadodara 390001, Gujarat (India); Govindarajan, J., E-mail: govindarajan@ipr.res.in [Institute for Plasma Research, Bhat, Gandhinagar 382428, Gujarat (India)

    2012-11-15

    Highlights: Black-Right-Pointing-Pointer Evaluation and comparison of the working performance of FLC is done with that of PID Controller. Black-Right-Pointing-Pointer FLC is designed using MATLAB Fuzzy Logic Toolbox, and validated on ADITYA RZIP model. Black-Right-Pointing-Pointer FLC was implemented on a FPGA. The close-loop testing is done by interfacing FPGA to MATLAB/Simulink. Black-Right-Pointing-Pointer Developed FLC controller is able to maintain the plasma column within required range of {+-}0.05 m and was found to give robust control against various disturbances and faster and smoother response compared to PID Controller. - Abstract: Tokamaks are the most promising devices for obtaining nuclear fusion energy from high-temperature, ionized gas termed as Plasma. The successful operation of tokamak depends on its ability to confine plasma at the geometric center of vacuum vessel with sufficient stability. The quality of plasma discharge in ADITYA Tokamak is strongly related to the radial position of the plasma column in the vacuum vessel. If the plasma column approaches too near to the wall of vacuum vessel, it leads to minor or complete disruption of plasma. Hence the control of plasma position throughout the entire plasma discharge duration is a fundamental requirement. This paper describes Fuzzy Logic Controller (FLC) which is designed for radial plasma position control. This controller is tested and evaluated on the ADITYA RZIP control model. The performance of this FLC was compared with that of Proportional-Integral-Derivative (PID) Controller and the response was found to be faster and smoother. FLC was implemented on a Field Programmable Gate Array (FPGA) chip with the use of a Very High-Speed Integrated-Circuits Hardware Description-Language (VHDL).

  19. Design and implementation of projects with Xilinx Zynq FPGA: a practical case

    Science.gov (United States)

    Travaglini, R.; D'Antone, I.; Meneghini, S.; Rignanese, L.; Zuffa, M.

    The main advantage when using FPGAs with embedded processors is the availability of additional several high-performance resources in the same physical device. Moreover, the FPGA programmability allows for connect custom peripherals. Xilinx have designed a programmable device named Zynq-7000 (simply called Zynq in the following), which integrates programmable logic (identical to the other Xilinx "serie 7" devices) with a System on Chip (SOC) based on two embedded ARM processors. Since both parts are deeply connected, the designers benefit from performance of hardware SOC and flexibility of programmability as well. In this paper a design developed by the Electronic Design Department at the Bologna Division of INFN will be presented as a practical case of project based on Zynq device. It is developed by using a commercial board called ZedBoard hosting a FMC mezzanine with a 12-bit 500 MS/s ADC. The Zynq FPGA on the ZedBoard receives digital outputs from the ADC and send them to the acquisition PC, after proper formatting, through a Gigabit Ethernet link. The major focus of the paper will be about the methodology to develop a Zynq-based design with the Xilinx Vivado software, enlightening how to configure the SOC and connect it with the programmable logic. Firmware design techniques will be presented: in particular both VHDL and IP core based strategies will be discussed. Further, the procedure to develop software for the embedded processor will be presented. Finally, some debugging tools, like the embedded Logic Analyzer, will be shown. Advantages and disadvantages with respect to adopting FPGA without embedded processors will be discussed.

  20. FPGA Coprocessor Design for an Onboard Multi-Angle Spectro-Polarimetric Imager

    Science.gov (United States)

    Pingree, Paula J.; Werne, Thomas A.

    2010-01-01

    A multi-angle spectro-polarimetric imager (MSPI) is an advanced camera system currently under development at JPL for possible future consideration on a satellite-based Aerosol-Cloud-Environ - ment (ACE) interaction study. The light in the optical system is subjected to a complex modulation designed to make the overall system robust against many instrumental artifacts that have plagued such measurements in the past. This scheme involves two photoelastic modulators that are beating in a carefully selected pattern against each other. In order to properly sample this modulation pattern, each of the proposed nine cameras in the system needs to read out its imager array about 1,000 times per second. The onboard processing required to compress this data involves least-squares fits (LSFs) of Bessel functions to data from every pixel in realtime, thus requiring an onboard computing system with advanced data processing capabilities in excess of those commonly available for space flight. As a potential solution to meet the MSPI onboard processing requirements, an LSF algorithm was developed on the Xilinx Virtex-4FX60 field programmable gate array (FPGA). In addition to configurable hardware capability, this FPGA includes Power -PC405 microprocessors, which together enable a combination hardware/ software processing system. A laboratory demonstration was carried out based on a hardware/ software co-designed processing architecture that includes hardware-based data collection and least-squares fitting (computationally), and softwarebased transcendental function computation (algorithmically complex) on the FPGA. Initial results showed that these calculations can be handled using a combination of the Virtex- 4TM Power-PC core and the hardware fabric.

  1. FPGA accelerator for protein secondary structure prediction based on the GOR algorithm.

    Science.gov (United States)

    Xia, Fei; Dou, Yong; Lei, Guoqing; Tan, Yusong

    2011-02-15

    Protein is an important molecule that performs a wide range of functions in biological systems. Recently, the protein folding attracts much more attention since the function of protein can be generally derived from its molecular structure. The GOR algorithm is one of the most successful computational methods and has been widely used as an efficient analysis tool to predict secondary structure from protein sequence. However, the execution time is still intolerable with the steep growth in protein database. Recently, FPGA chips have emerged as one promising application accelerator to accelerate bioinformatics algorithms by exploiting fine-grained custom design. In this paper, we propose a complete fine-grained parallel hardware implementation on FPGA to accelerate the GOR-IV package for 2D protein structure prediction. To improve computing efficiency, we partition the parameter table into small segments and access them in parallel. We aggressively exploit data reuse schemes to minimize the need for loading data from external memory. The whole computation structure is carefully pipelined to overlap the sequence loading, computing and back-writing operations as much as possible. We implemented a complete GOR desktop system based on an FPGA chip XC5VLX330. The experimental results show a speedup factor of more than 430x over the original GOR-IV version and 110x speedup over the optimized version with multi-thread SIMD implementation running on a PC platform with AMD Phenom 9650 Quad CPU for 2D protein structure prediction. However, the power consumption is only about 30% of that of current general-propose CPUs.

  2. FPGA based data processing in the ALICE High Level Trigger in LHC Run 2

    Science.gov (United States)

    Engel, Heiko; Alt, Torsten; Kebschull, Udo; ALICE Collaboration

    2017-10-01

    The ALICE High Level Trigger (HLT) is a computing cluster dedicated to the online compression, reconstruction and calibration of experimental data. The HLT receives detector data via serial optical links into FPGA based readout boards that process the data on a per-link level already inside the FPGA and provide it to the host machines connected with a data transport framework. FPGA based data pre-processing is enabled for the biggest detector of ALICE, the Time Projection Chamber (TPC), with a hardware cluster finding algorithm. This algorithm was ported to the Common Read-Out Receiver Card (C-RORC) as used in the HLT for RUN 2. It was improved to handle double the input bandwidth and adjusted to the upgraded TPC Readout Control Unit (RCU2). A flexible firmware implementation in the HLT handles both the old and the new TPC data format and link rates transparently. Extended protocol and data error detection, error handling and the enhanced RCU2 data ordering scheme provide an improved physics performance of the cluster finder. The performance of the cluster finder was verified against large sets of reference data both in terms of throughput and algorithmic correctness. Comparisons with a software reference implementation confirm significant savings on CPU processing power using the hardware implementation. The C-RORC hardware with the cluster finder for RCU1 data is in use in the HLT since the start of RUN 2. The extended hardware cluster finder implementation for the RCU2 with doubled throughput is active since the upgrade of the TPC readout electronics in early 2016.

  3. A new delay line loops shrinking time-to-digital converter in low-cost FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Jie, E-mail: zhangjie071063@163.com [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China); University of Chinese Academy of Sciences, Beijing, China, 100049 (China); Zhou, Dongming [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China)

    2015-01-21

    The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage.

  4. Modeling and control of isolated full bridge boost DC-DC converter implemented in FPGA

    DEFF Research Database (Denmark)

    Taeed, Fazel; Nymand, M.

    2013-01-01

    In this paper an isolated full bridge boost converter (IFBC) firstly is modeled. In the modeling part, a small signal equivalent of the converter is developed. From the small signal model, the converter transfer function is derived. Based on the obtained transfer function, challenges of controller...... design are discussed. In the next step a digital PI controller is designed and implemented in a FPGA to control the output voltage. Using the injection transformer method the open loop transfer function in closed loop is measured and modeling results are verified by experimental results....

  5. FPGA-based implementation of a cavity field controller for FLASH and X-FEL

    Science.gov (United States)

    Fafara, Przemyslaw; Jalmuzna, Wojciech; Koprek, Waldemar; Pozniak, Krzysztof; Romaniuk, Ryszard; Szewinski, Jaroslaw; Cichalewski, Wojciech

    2007-08-01

    The subject of this paper is the design and construction of a new generation of superconducting cavity accelerator measurement and control system. The old system is based on a single digital signal processor (DSP). The new system uses a large programmable array circuit (FPGA) instead, with a multi-gigabit optical link. Both systems now work in parallel in the Free Electron Laser in Hamburg (FLASH). The differences between the systems are shown, based on the measurement results of the working machine. The major advantage of the new system is a bigger area of stability of the machine control loop.

  6. FPGA-based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    Science.gov (United States)

    Perkuszewski, Karol; Pozniak, Krzysztof T.; Jalmuzna, Wojciech; Koprek, Waldemar; Szewinski, Jaroslaw; Romaniuk, Ryszard S.; Simrock, Stefan

    2006-10-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented.

  7. FPGA based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    Energy Technology Data Exchange (ETDEWEB)

    Perkuszewski, K.; Pozniak, K.T.; Jalmuzna, W.; Koprek, W.; Szewinski, J.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems; Simrock, S. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany)

    2006-07-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented. (orig.)

  8. A pattern recognition scheme for large curvature circular tracks and an FPGA implementation using hash sorter

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jin-Yuan; Shi, Z.; /Fermilab

    2004-12-01

    Strong magnetic field in today's colliding detectors causes track recognition more difficult due to large track curvatures. In this document, we present a global track recognition scheme based on track angle measurements for circular tracks passing the collision point. It uses no approximations in the track equation and therefore is suitable for both large and small curvature tracks. The scheme can be implemented both in hardware for lower-level trigger or in software for higher-level trigger or offline analysis codes. We will discuss an example of FPGA implementations using ''hash sorter''.

  9. Sharon Tseng Final Summer Student Report: Monitoring Vibrations Using an FPGA

    CERN Document Server

    Tseng, Sharon

    2016-01-01

    My CERN Summer Student project consisted of designing and implementing a vibration monitoring system using an accelerometer and an FPGA with a built in ARM processor. This vibration monitoring system will be used on the LHCb Event Filter Farm, 1,820 server nodes holding 5000 TB of hard-disk space that temporarily holds the collision detector data. The hard-disks have observed an unusually high failing rate that causes loss of data. Researchers suspect vibrations cause this so my system will be implemented to test this hypothesis.

  10. Real time polarization sensor image processing on an embedded FPGA/multi-core DSP system

    Science.gov (United States)

    Bednara, Marcus; Chuchacz-Kowalczyk, Katarzyna

    2015-05-01

    Most embedded image processing SoCs available on the market are highly optimized for typical consumer applications like video encoding/decoding, motion estimation or several image enhancement processes as used in DSLR or digital video cameras. For non-consumer applications, on the other hand, optimized embedded hardware is rarely available, so often PC based image processing systems are used. We show how a real time capable image processing system for a non-consumer application - namely polarization image data processing - can be efficiently implemented on an FPGA and multi-core DSP based embedded hardware platform.

  11. An FPGA-based nuclear pulse generator with a prescribed amplitude distribution

    Science.gov (United States)

    Ponikvar, Dušan

    2018-01-01

    A design of a low-cost electrical pulse generator capable of producing random pulses with exponentially decaying tail as coming from a nuclear detector is described. The generator can generate periodic single or double pulses of a user-defined amplitude and decay time, or randomly occurring pulses with amplitudes drawn at random from a user-prescribed probability density function. The electronics is based on a low power consumption Spartan-6 field-programmable gate array (FPGA) and a 14-bit digital to analog converter (DAC) running at frequency of 40 MHz, and a complete technical documentation to build the generator is available online.

  12. FPGA-based fused smart sensor for dynamic and vibration parameter extraction in industrial robot links.

    Science.gov (United States)

    Rodriguez-Donate, Carlos; Morales-Velazquez, Luis; Osornio-Rios, Roque Alfredo; Herrera-Ruiz, Gilberto; de Jesus Romero-Troncoso, Rene

    2010-01-01

    Intelligent robotics demands the integration of smart sensors that allow the controller to efficiently measure physical quantities. Industrial manipulator robots require a constant monitoring of several parameters such as motion dynamics, inclination, and vibration. This work presents a novel smart sensor to estimate motion dynamics, inclination, and vibration parameters on industrial manipulator robot links based on two primary sensors: an encoder and a triaxial accelerometer. The proposed smart sensor implements a new methodology based on an oversampling technique, averaging decimation filters, FIR filters, finite differences and linear interpolation to estimate the interest parameters, which are computed online utilizing digital hardware signal processing based on field programmable gate arrays (FPGA).

  13. FPGA-Based Fused Smart Sensor for Dynamic and Vibration Parameter Extraction in Industrial Robot Links

    Directory of Open Access Journals (Sweden)

    Rene de Jesus Romero-Troncoso

    2010-04-01

    Full Text Available Intelligent robotics demands the integration of smart sensors that allow the controller to efficiently measure physical quantities. Industrial manipulator robots require a constant monitoring of several parameters such as motion dynamics, inclination, and vibration. This work presents a novel smart sensor to estimate motion dynamics, inclination, and vibration parameters on industrial manipulator robot links based on two primary sensors: an encoder and a triaxial accelerometer. The proposed smart sensor implements a new methodology based on an oversampling technique, averaging decimation filters, FIR filters, finite differences and linear interpolation to estimate the interest parameters, which are computed online utilizing digital hardware signal processing based on field programmable gate arrays (FPGA.

  14. FPGA-Based Fused Smart Sensor for Dynamic and Vibration Parameter Extraction in Industrial Robot Links

    Science.gov (United States)

    Rodriguez-Donate, Carlos; Morales-Velazquez, Luis; Osornio-Rios, Roque Alfredo; Herrera-Ruiz, Gilberto; de Jesus Romero-Troncoso, Rene

    2010-01-01

    Intelligent robotics demands the integration of smart sensors that allow the controller to efficiently measure physical quantities. Industrial manipulator robots require a constant monitoring of several parameters such as motion dynamics, inclination, and vibration. This work presents a novel smart sensor to estimate motion dynamics, inclination, and vibration parameters on industrial manipulator robot links based on two primary sensors: an encoder and a triaxial accelerometer. The proposed smart sensor implements a new methodology based on an oversampling technique, averaging decimation filters, FIR filters, finite differences and linear interpolation to estimate the interest parameters, which are computed online utilizing digital hardware signal processing based on field programmable gate arrays (FPGA). PMID:22319345

  15. LVTTL Based Energy Efficient Watermark Generator Design and Implementation on FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Kaur, Amanpreet; Kumar, Tanesh

    2014-01-01

    In print image, a watermark is an identifiable pattern which when viewed by reflected light seems to have different shades of lightness. In digital image, a watermark is a pattern, which is embedded in image to ensure the security and quality of an image. In this work, our main concern is design......-transistor logic (LVTTL) IO standard is used in this design to make it power optimized. This design is implemented on Kintex-7 FPGA, Device XC7K70T and -3 speed grades. When we are scaling the device operating frequency from 100GHz to 5GHz, there is 94.93% saving in total power of the watermark generator...

  16. Design of a dedicated processor for AC motor control implemented in a low cost FPGA

    DEFF Research Database (Denmark)

    Jakobsen, Uffe; Matzen, Torben N.

    2008-01-01

    Motor control for small series sometimes requires specialized control logic, requiring rewiring if new logic needs to be added. This paper describes a different approach to hardware and software co-design, namely designing a softcore processor with an instruction set to fit the purpose of control...... of drives. Furthermore the softcore processor is designed with a system for plug in of external logic. Doing so shortens development time, since functionality is simply added to or removed from the softcore. The designer can then choose between resource usage on the FPGA and execution speed in more degrees...

  17. A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

    OpenAIRE

    Monson, Joshua S.; Wirthlin, Mike; Hutchings, Brad

    2012-01-01

    An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed consists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test (DUT) consists of the “hard core” PowerPC, running the Linux OS and several peripherals implemented in “soft” (programmable) logic. Faults were injected via the Internal Configuration Access Port (ICAP). The experiments performed...

  18. Research and Implementation of Automatic Fuzzy Garage Parking System Based on FPGA

    Directory of Open Access Journals (Sweden)

    Wang Kaiyu

    2016-01-01

    Full Text Available Because of many common scenes of reverse parking in real life, this paper presents a fuzzy controller which accommodates front and back adjustment of vehicle’s body attitude, and based on chaotic-genetic arithmetic to optimize the membership function of this controller, and get a vertical parking fuzzy controller whose simulation result is good .The paper makes the hardware-software embedded design for system based on Field-Programmable Gate Array (FPGA, and set up a 1:10 verification platform of smart car to verify the fuzzy garage parking system with real car. Verification results show that, the system can complete the parking task very well.

  19. Interação entre computadores e placas baseadas em FPGA

    OpenAIRE

    Soares, Pedro Miguel dos Santos

    2012-01-01

    Esta Dissertação é dedicada ao projeto, implementação e avaliação de ferramentas que permitem a transferência de dados entre FPGA presentes em placas de prototipagem Digilent (no caso a Nexys 2 e a Atlys) e um computador de uso geral. Esta problemática é relevante para diversos propósitos, tais como: 1) a verificação expedita de projetos para aplicações de processamento intensivo de dados; 2) para possibilitar a separação do projeto num núcleo hardware de elevado desempenho, que cumpra os obj...

  20. High-Speed Computation using FPGA for Excellent Performance of Direct Torque Control of Induction Machines

    Directory of Open Access Journals (Sweden)

    Tole Sutikno

    2016-03-01

    Full Text Available The major problems in hysteresis-based DTC are high torque ripple and variable switching frequency. In order to minimize the torque ripple, high sampling time and fast digital realization should be applied. The high sampling and fast digital realization time can be achieved by utilizing high-speed processor where the operation of the discrete hysteresis regulator is becoming similar to the operation of analog-based comparator. This can be achieved by utilizing field programmable gate array (FPGA which can perform a sampling at a very high speed, compared to the fact that developing an ASIC chip is expensive and laborious.