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Sample records for fpga based node-on-chip

  1. An FPGA based Node-on-Chip Architecture, for Rapid Robotics Research

    DEFF Research Database (Denmark)

    Falsig, Simon; Sørensen, Anders Stengaard

    2010-01-01

    One of the major costs and inhibitors to practical robotics research is the time invested in design, implementation, integration, adjusting and debugging of the embedded control systems, that implement the discrete event control in experimental robots and robot systems. Usually researchers can...... with the compactness and integration associated with customized hardware. In this paper we present an FPGA based architecture and a framework of template modules for modular embedded control that has: • Dramatically reduced the time we spend on instrumentation of experimental robots. • Increased the quality...

  2. Flexible experimental FPGA based platform

    DEFF Research Database (Denmark)

    Andersen, Karsten Holm; Nymand, Morten

    2016-01-01

    This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

  3. The MCD circuit based on FPGA

    International Nuclear Information System (INIS)

    Vu Quoc Trong

    2003-01-01

    Two MCD circuits based on different FPGA are presented as results of the study of the MAX+PLUS II software and FPGA devices. An external memory like 62256 and programmed EPM7064S will be able to form a MCD with 8 kilo channels. (NHA)

  4. FPGA-Based Sonar Processing

    National Research Council Canada - National Science Library

    Graham, Paul; Nelson, Brent

    1998-01-01

    This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays...

  5. FPGA based Smart Wireless MIMO Control System

    International Nuclear Information System (INIS)

    Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-01-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

  6. Qualification of FPGA-Based Safety-Related PRM System

    International Nuclear Information System (INIS)

    Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

    2011-01-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

  7. Commercial FPGA based multipurpose controller: implementation perspective

    International Nuclear Information System (INIS)

    Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

    2012-01-01

    This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

  8. An FPGA-Based Electronic Cochlea

    Directory of Open Access Journals (Sweden)

    M. P. Leong

    2003-06-01

    Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

  9. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  10. An FPGA-Based People Detection System

    Directory of Open Access Journals (Sweden)

    James J. Clark

    2005-05-01

    Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

  11. FPGA-Based Embedded Motion Estimation Sensor

    Directory of Open Access Journals (Sweden)

    Zhaoyi Wei

    2008-01-01

    Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

  12. FPGA based Control of a Production Cell System

    NARCIS (Netherlands)

    Groothuis, M.A.; van Zuijlen, Jasper J.P.; Broenink, Johannes F.

    Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control

  13. Wire Position Monitoring with FPGA based Electronics

    International Nuclear Information System (INIS)

    Eddy, N.; Lysenko, O.

    2009-01-01

    This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. An FPGA based digitizer

  14. Algorithmic strategies for FPGA-based vision

    OpenAIRE

    Lim, Yoong Kang

    2016-01-01

    As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

  15. Long-distance configuration of FPGA based on serial communication

    International Nuclear Information System (INIS)

    Liu Xiang; Song Kezhu; Zhang Sifeng

    2010-01-01

    To solve FPGA configuration in some nuclear electronics, which works in radioactivity environment, the article introduces a way of long-distance configuration with PC and CPLD, based on serial communication. Taking CYCLONE series FPGA and EPCS configuration chip from ALTERA for example, and using the AS configuration mode, we described our design from the aspects of basic theory, hardware connection, software function and communication protocol. With this design, we could configure several FPGAs in the distance of 100 meters, or we could configure on FPGA in the distance of 150 meters. (authors)

  16. Application-specific mesh-based heterogeneous FPGA architectures

    CERN Document Server

    Parvez, Husain

    2011-01-01

    This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

  17. Video Watermarking Implementation Based on FPGA

    International Nuclear Information System (INIS)

    EL-ARABY, W.S.M.S.

    2012-01-01

    The sudden increase in watermarking interest is most likely due to the increase in concern over copyright protection of content. With the rapid growth of the Internet and the multimedia systems in distributed environments, digital data owners are now easier to transfer multimedia documents across the Internet. However, current technology does not protect their copyrights properly. This leads to wide interest of multimedia security and multimedia copyright protection and it has become a great concern to the public in recent years. In the early days, encryption and control access techniques were used to protect the ownership of media. Recently, the watermarking techniques are utilized to keep safely the copyrights. In this thesis, a fast and secure invisible video watermark technique has been introduced. The technique based mainly on DCT and Low Frequency using pseudo random number (PN) sequence generator for embedding algorithm. The system has been realized using VHDL and the results have been verified using MATLAB. The implementation of the introduced watermark system done using Xilinx chip (XCV800). The implementation results show that the total area of watermark technique is 45% of total FPGA area with maximum delay equals 16.393ns. The experimental results show that the two techniques have mean square error (MSE) equal to 0.0133 and peak signal to noise ratio (PSNR) equal to 66.8984db. The results have been demonstrated and compared with conventional watermark technique using DCT.

  18. A software radio platform based on ARM and FPGA

    Directory of Open Access Journals (Sweden)

    Yang Xin.

    2016-01-01

    Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

  19. An FPGA-based torus communication network

    Energy Technology Data Exchange (ETDEWEB)

    Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

    2011-02-15

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  20. Moessbauer spectrometric data acquisition based on FPGA

    International Nuclear Information System (INIS)

    Zhang Yuan; Li Shimin; Chen Nan; Zhu Jingbo; Xia Yuanfu

    2008-01-01

    FPGA(Field Programmable Gate Array) is a programmable device with strong logical function and timing control ability. It is extremely potent in acquiring and processing timing signals. By replacing the traditional used SCM (Single-Chip Microcomputer) with FPGA, counting speed of Moessbauer spectrometric data acquisition can be improved markedly with significantly decreased size of the spectrometer. The counter, RAM and RS-232 communication of the module are developed on Altera Cyclone series chip EP1C6T144C8 with Quartus II. EP1C6T144C8 has 5980 logical units accompanied by 92160 bits of memory space. It is so powerful that all needs in data acquisition of the Moessbauer spectrometer can be perfectly satisfied while allowing modifications in functions and parameters. (authors)

  1. An Improved Rotary Interpolation Based on FPGA

    Directory of Open Access Journals (Sweden)

    Mingyu Gao

    2014-08-01

    Full Text Available This paper presents an improved rotary interpolation algorithm, which consists of a standard curve interpolation module and a rotary process module. Compared to the conventional rotary interpolation algorithms, the proposed rotary interpolation algorithm is simpler and more efficient. The proposed algorithm was realized on a FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe, which uses rotary ellipse and rotary parabolic as an example. According to the theoretical analysis and practical process validation, the algorithm has the following advantages: firstly, less arithmetic items is conducive for interpolation operation; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

  2. An FPGA-based torus communication network

    International Nuclear Information System (INIS)

    Pivanti, Marcello; Schifano, Sebastiano Fabio; Simma, Hubert

    2011-02-01

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  3. Adaptive Hardware Cryptography Engine Based on FPGA

    International Nuclear Information System (INIS)

    Afify, M.A.A.

    2011-01-01

    In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

  4. An FPGA-based reconfigurable DDC algorithm

    Science.gov (United States)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  5. FPGA communications based on Gigabit Ethernet

    International Nuclear Information System (INIS)

    Doolittle, L.R.; Serrano, C.

    2012-01-01

    The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

  6. Flexible, fpga-based electronics for modular robots

    DEFF Research Database (Denmark)

    Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

    2008-01-01

    In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

  7. Multifunctional data acquisition system based on USB and FPGA

    International Nuclear Information System (INIS)

    Huang Tuchen; Gong Hui; Shao Beibei

    2013-01-01

    A multifunctional data acquisition system based on USB and FPGA was developed. The system has four analog inputs digitalized by fast ADC. Based on flexibility of FPGA, different functions can be implemented such as waveform sampling, pulse counting, multi-channel pulse height analysis, and charge division readout process. The hardware communicates with host PC via USB interface. The Labview based user soft ware initializes the hardware, configures the running parameters, reads and processes the data as well as displays the result online. (authors)

  8. Embedded system in FPGA-based LLRF controller for FLASH

    Science.gov (United States)

    Szewinski, Jaroslaw; Pucyk, Piotr; Jalmuzna, Wojciech; Fafara, Przemyslaw; Pieciukiewicz, Marcin; Romaniuk, Ryszard; Pozniak, Krzysztof T.

    2006-10-01

    FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

  9. Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

    Directory of Open Access Journals (Sweden)

    Bhattacharyya Shuvra S

    2003-01-01

    Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

  10. FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

    Directory of Open Access Journals (Sweden)

    Tomyslav Sledevič

    2013-05-01

    Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

  11. An FPGA-based heterogeneous image fusion system design method

    Science.gov (United States)

    Song, Le; Lin, Yu-chi; Chen, Yan-hua; Zhao, Mei-rong

    2011-08-01

    Taking the advantages of FPGA's low cost and compact structure, an FPGA-based heterogeneous image fusion platform is established in this study. Altera's Cyclone IV series FPGA is adopted as the core processor of the platform, and the visible light CCD camera and infrared thermal imager are used as the image-capturing device in order to obtain dualchannel heterogeneous video images. Tailor-made image fusion algorithms such as gray-scale weighted averaging, maximum selection and minimum selection methods are analyzed and compared. VHDL language and the synchronous design method are utilized to perform a reliable RTL-level description. Altera's Quartus II 9.0 software is applied to simulate and implement the algorithm modules. The contrast experiments of various fusion algorithms show that, preferably image quality of the heterogeneous image fusion can be obtained on top of the proposed system. The applied range of the different fusion algorithms is also discussed.

  12. FPGA based VME boards for Indus-2 timing control system

    International Nuclear Information System (INIS)

    Lulani, Nitin; Barpande, K.; Fatnani, P.; Sheth, Y.

    2009-01-01

    FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards. (author)

  13. Photoelectric radar servo control system based on ARM+FPGA

    Science.gov (United States)

    Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

    2016-01-01

    In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

  14. Fpga-based control of piezoelectric actuators

    Directory of Open Access Journals (Sweden)

    Juhász László

    2011-01-01

    Full Text Available In many industrial applications like semiconductor production and optical inspection systems, the availability of positioning systems capable to follow trajectory paths in the range of several centimetres, featuring at the same time a nanometre-range precision, is demanding. Pure piezoelectric stages and standard positioning systems with motor and spindle are not able to meet such requirements, because of the small operation range and inadequacies like backlash and friction. One concept for overcoming these problems consists of a hybrid positioning system built through the integration of a DC-drive in series with a piezoelectric actuator. The wide range of potential applications enables a considerable market potential for such an actuator, but due to the high variety of possible positioned objects and dynamic requirements, the required control complexity may be significant. In this paper, a real-time capable state-space control concept for the piezoelectric actuators, embedded in such a hybrid micropositioning system, is presented. The implementation of the controller together with a real-time capable hysteresis compensation measure is performed using a low-budget FPGA-board, whereas the superimposed integrated controller is realized with a dSPACE RCP-system. The advantages of the designed control over a traditional proportional-integral control structure are proven through experimental results using a commercially available hybrid micropositioning system. Positioning results by different dynamic requirements featuring positioning velocities from 1 μm/s up to 5 cm/s are given.

  15. Development of FPGA-Based Control Board

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Yoon Hee; Jeong, See Chae; Choi, Woong Seock; Lee, Chang Jae; Jeong, Jin Kwon; Ha, Jae Hong [Korea Power Engineering Company Inc., Daejeon (Korea, Republic of)

    2009-10-15

    It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a FPGAbased control board performing user-defined control functions. An Actel ProASIC{sup plus} FPGA platform is implemented as the comparator of Plant Protection System (PPS). Functional simulation is implemented for the comparator.

  16. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Chalimbaud Pierre

    2007-01-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  17. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Pierre Chalimbaud

    2006-12-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  18. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  19. FPGA-based network data transmission scheme for CSNS

    International Nuclear Information System (INIS)

    Wang Xiuku; Zhang Hongyu; Gu Minhao; Xiao Liang

    2012-01-01

    This paper presents the FPGA-based network data transmission solutions for the Data Acquisition System of China Spallation Neutron Source (CSNS). The board with FPGA as the core is used as the hardware platform to realize the transmission of network data. A SOPC system is built and an embedded Linux is transplanted on PowerPC Core. An application program based on Linux has been finished to realize the data transmission via embedded Gigabit Ethernet. The relationship between network transfer performance and packet size was obtained by a test program. In addition, the paper also tried to realize some other ways to transfer data: transplanting PetaLinux on Microblaze, transplanting Lwip protocol stack on PowerPC Core and Microblaze. Their advantages and disadvantages are analyzed and compared in this paper, so that different options and recommendations can be given to meet the actual needs of different projects in the future. (authors)

  20. Embedded active vision system based on an FPGA architecture

    OpenAIRE

    Chalimbaud , Pierre; Berry , François

    2006-01-01

    International audience; In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision) is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks,...

  1. Intermediate Frequency Digital Receiver Based on Multi-FPGA System

    Directory of Open Access Journals (Sweden)

    Chengchang Zhang

    2016-01-01

    Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

  2. Architecture exploration of FPGA based accelerators for bioinformatics applications

    CERN Document Server

    Varma, B Sharat Chandra; Balakrishnan, M

    2016-01-01

    This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.

  3. Fault tolerance based on serial communication of FPGA

    International Nuclear Information System (INIS)

    Peng Jing; Fang Zongliang; Xu Quanzhou; Hu Jiewei; Ma Guizhen

    2012-01-01

    There maybe appear mistake in serial communication. This paper was described the intellectual detector of γ dose ratemeter communication with FPGA. The software of FPGA designed the code about fault tolerance, prevented mistake effectively. (authors)

  4. Energy Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Kenn Toft, Jakob; Nannarelli, Alberto

    2014-01-01

    Field Programmable Gate Arrays (FPGAs) based accelerators are very suitable to implement application-specific processors using uncommon operations or number systems. In this work, we design FPGA-based accelerators for two financial computations with different characteristics and we compare...... the accelerator performance and energy consumption to a software execution of the application. The experimental results show that significant speed-up and energy savings, can be obtained for large data sets by using the accelerator at expenses of a longer development time....

  5. HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

    DEFF Research Database (Denmark)

    Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

    2015-01-01

    standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

  6. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  7. FPGA Implementation of Video Transmission System Based on LTE

    Directory of Open Access Journals (Sweden)

    Lu Yan

    2015-01-01

    Full Text Available In order to support high-definition video transmission, an implementation of video transmission system based on Long Term Evolution is designed. This system is developed on Xilinx Virtex-6 FPGA ML605 Evaluation Board. The paper elaborates the features of baseband link designed in Xilinx ISE and protocol stack designed in Xilinx SDK, and introduces the process of setting up hardware and software platform in Xilinx XPS. According to test, this system consumes less hardware resource and is able to transmit bidirectional video clearly and stably.

  8. FPGA-Based Plant Protection System

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Yoon Hee; Ha, Jae Hong; Kim, Hang Bae [KEPCO E and C, Daejeon (Korea, Republic of)

    2011-08-15

    This paper relates to a plant protection system which detects non-permissible conditions and determines initiation of protective actions for nuclear power plants (NPPs). Conventional plant protection systems were designed based on analog technologies. It is well known that existing protection systems for NPPs contain many components which are becoming obsolete at an increasing rate. Nowadays maintenance and repair for analog-based plant protection systems may be difficult as analog parts become obsolete or difficult to obtain. Accordingly, as an alternative to the analog technology, the digitalisation of the plant protection system was required. Recently digital plant protection systems which include programmable logic controllers (PLCs) and/or computers have been introduced. However PLC or computer-based plant protection systems use an operating system and application software, and so they may result in a common mode failure when a problem occurs in the operating system or application software. Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative to conventional protection or control systems. The paper presents the design of a four-channel plant protection system whose protection functions are implemented in FPGAs without any central processing unit or operating system.

  9. FPGA-Based Plant Protection System

    International Nuclear Information System (INIS)

    Lee, Yoon Hee; Ha, Jae Hong; Kim, Hang Bae

    2011-01-01

    This paper relates to a plant protection system which detects non-permissible conditions and determines initiation of protective actions for nuclear power plants (NPPs). Conventional plant protection systems were designed based on analog technologies. It is well known that existing protection systems for NPPs contain many components which are becoming obsolete at an increasing rate. Nowadays maintenance and repair for analog-based plant protection systems may be difficult as analog parts become obsolete or difficult to obtain. Accordingly, as an alternative to the analog technology, the digitalisation of the plant protection system was required. Recently digital plant protection systems which include programmable logic controllers (PLCs) and/or computers have been introduced. However PLC or computer-based plant protection systems use an operating system and application software, and so they may result in a common mode failure when a problem occurs in the operating system or application software. Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative to conventional protection or control systems. The paper presents the design of a four-channel plant protection system whose protection functions are implemented in FPGAs without any central processing unit or operating system

  10. FPGA based accelerators for financial applications

    CERN Document Server

    2015-01-01

    This book covers the latest approaches and results from reconfigurable computing architectures employed in the finance domain. So-called field-programmable gate arrays (FPGAs) have already shown to outperform standard CPU- and GPU-based computing architectures by far, saving up to 99% of energy depending on the compute tasks. Renowned authors from financial mathematics, computer architecture, and finance business introduce the readers into today’s challenges in finance IT, illustrate the most advanced approaches and use cases, and present currently known methodologies for integrating FPGAs in finance systems together with latest results. The complete algorithm-to-hardware flow is covered holistically, so this book serves as a hands-on guide for IT managers, researchers, and quants/programmers who think about integrating FPGAs into their current IT systems.

  11. FPGA based algorithms for data reduction at Belle II

    Energy Technology Data Exchange (ETDEWEB)

    Muenchow, David; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liu, Ming; Spruck, Bjoern [II. Physikalisches Institut, Universitaet Giessen (Germany)

    2011-07-01

    Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e{sup +}e{sup -} collider with a design luminosity of 8.10{sup 35}cm{sup -2}s{sup -1}. At Belle II the estimated event rate is {<=}30 kHz. The resulting data rate at the Pixel Detector (PXD) will be {<=}7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for buffering and storing the data. The status of the implementation and performance tests of the memory manager and data reduction algorithm is presented.

  12. An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator.

    Science.gov (United States)

    Wang, Runchun M; Thakur, Chetan S; van Schaik, André

    2018-01-01

    This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF) neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons). This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

  13. An FPGA bridge preserving traffing quality of service for on-chip network-based systems

    NARCIS (Netherlands)

    Nejad, A.B.; Escudero Martinez, M.; Goossens, K.G.W.

    2011-01-01

    FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into

  14. Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

    NARCIS (Netherlands)

    Becher, Andreas; Bauer, Florian; Ziener, Daniel; Teich, Jürgen

    2014-01-01

    In this paper, we propose an approach for energy-aware FPGA-based query acceleration for databases on embedded devices. After the analysis of an incoming query, a query-specific hardware accelerator is generated on-the-fly and loaded on the FPGA for subsequent query execution using partial dynamic

  15. New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project

    CERN Document Server

    Mendez, Julian Maxime; Caratelli, Alessandro; Leitao, Pedro Vicente

    2018-01-01

    The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

  16. Real-time particle image velocimetry based on FPGA technology

    International Nuclear Information System (INIS)

    Iriarte Munoz, Jose Miguel

    2008-01-01

    Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach. [es

  17. An FPGA-based rapid prototyping platform for wavelet coprocessors

    Science.gov (United States)

    Vera, Alonzo; Meyer-Baese, Uwe; Pattichis, Marios

    2007-04-01

    MatLab/Simulink-based design flows are being used by DSP designers to improve time-to-market of FPGA implementations. 1 Commonly, digital signal processing cores are integrated in an embedded system as coprocessors. Existing CAD tools do not fully address the integration of a DSP coprocessor into an embedded system design. This integration might prove to be time consuming and error prone. It also requires that the DSP designer has an excellent knowledge of embedded systems and computer architecture details. We present a prototyping platform and design flow that allows rapid integration of embedded systems with a wavelet coprocessor. The platform comprises of software and hardware modules that allow a DSP designer a painless integration of a coprocessor with a PowerPC-based embedded system. The platform has a wide range of applications, from industrial to educational environments.

  18. Development of FPGA-based safety-related instrumentation and control systems

    Energy Technology Data Exchange (ETDEWEB)

    Oda, N.; Tanaka, A.; Izumi, M.; Tarumi, T.; Sato, T. [Toshiba Corporation, Isogo Nuclear Engineering Center, Yokohama (Japan)

    2004-07-01

    Toshiba has developed systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related instrumentation and control systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  19. Development of FPGA-based safety-related I and C systems

    Energy Technology Data Exchange (ETDEWEB)

    Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S. [08, Shinsugita-cho, Isogo-ku, Yokohama 235-8523 (Japan); 1, Toshiba-cho, Fuchu, Tokyo 183-8511 (Japan)

    2006-07-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  20. improvement of digital image watermarking techniques based on FPGA implementation

    International Nuclear Information System (INIS)

    EL-Hadedy, M.E

    2006-01-01

    digital watermarking provides the ownership of a piece of digital data by marking the considered data invisibly or visibly. this can be used to protect several types of multimedia objects such as audio, text, image and video. this thesis demonstrates the different types of watermarking techniques such as (discrete cosine transform (DCT) and discrete wavelet transform (DWT) and their characteristics. then, it classifies these techniques declaring their advantages and disadvantages. an improved technique with distinguished features, such as peak signal to noise ratio ( PSNR) and similarity ratio (SR) has been introduced. the modified technique has been compared with the other techniques by measuring heir robustness against differ attacks. finally, field programmable gate arrays (FPGA) based implementation and comparison, for the proposed watermarking technique have been presented and discussed

  1. A minimal SATA III Host Controller based on FPGA

    Science.gov (United States)

    Liu, Hailiang

    2018-03-01

    SATA (Serial Advanced Technology Attachment) is an advanced serial bus which has a outstanding performance in transmitting high speed real-time data applied in Personal Computers, Financial Industry, astronautics and aeronautics, etc. In this express, a minimal SATA III Host Controller based on Xilinx Kintex 7 serial FPGA is designed and implemented. Compared to the state-of-art, registers utilization are reduced 25.3% and LUTs utilization are reduced 65.9%. According to the experimental results, the controller works precisely and steady with the reading bandwidth of up to 536 MB per second and the writing bandwidth of up to 512 MB per second, both of which are close to the maximum bandwidth of the SSD(Solid State Disk) device. The host controller is very suitable for high speed data transmission and mass data storage.

  2. FPGA based compute nodes for high level triggering in PANDA

    International Nuclear Information System (INIS)

    Kuehn, W; Gilardi, C; Kirschner, D; Lang, J; Lange, S; Liu, M; Perez, T; Yang, S; Schmitt, L; Jin, D; Li, L; Liu, Z; Lu, Y; Wang, Q; Wei, S; Xu, H; Zhao, D; Korcyl, K; Otwinowski, J T; Salabura, P

    2008-01-01

    PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10 7 /s and data rates of several 100 Gb/s. FPGA based compute nodes with multi-Gb/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Data connectivity is provided via optical links as well as multiple Gb Ethernet ports. The boards will support trigger algorithms such us pattern recognition for RICH detectors, EM shower analysis, fast tracking algorithms and global event characterization. Besides VHDL, high level C-like hardware description languages will be considered to implement the firmware

  3. Method to implement the CCD timing generator based on FPGA

    Science.gov (United States)

    Li, Binhua; Song, Qian; He, Chun; Jin, Jianhui; He, Lin

    2010-07-01

    With the advance of the PFPA technology, the design methodology of digital systems is changing. In recent years we develop a method to implement the CCD timing generator based on FPGA and VHDL. This paper presents the principles and implementation skills of the method. Taking a developed camera as an example, we introduce the structure, input and output clocks/signals of a timing generator implemented in the camera. The generator is composed of a top module and a bottom module. The bottom one is made up of 4 sub-modules which correspond to 4 different operation modes. The modules are implemented by 5 VHDL programs. Frame charts of the architecture of these programs are shown in the paper. We also describe implementation steps of the timing generator in Quartus II, and the interconnections between the generator and a Nios soft core processor which is the controller of this generator. Some test results are presented in the end.

  4. Implementation of FPGA-Based Diverse Protection System

    International Nuclear Information System (INIS)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

    2015-01-01

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

  5. Implementation of FPGA-Based Diverse Protection System

    Energy Technology Data Exchange (ETDEWEB)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

    2015-10-15

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

  6. FPGA-based prototype of portable environmental radiation monitor

    Energy Technology Data Exchange (ETDEWEB)

    Benahmed, A.; Elkarch, H. [CNESTEN -Centre National de l' Energie des Sciences et Techniques Nucleaires (Morocco)

    2015-07-01

    This new portable radiological environmental monitor consists of 2 main components, Gamma ionization chamber and a FPGA-based electronic enclosure linked to convivial software for treatment and analyzing. The HPIC ion chamber is the heart of this radiation measurement system and is running in range from 0 to 100 mR/h, so that the sensitivity at the output is 20 mV/μR/h, with a nearly flat energy response from 0,07 to 10 MEV. This paper presents a contribution for developing a new nuclear measurement data acquisition system based on Cyclone III FPGA Starter Kit ALTERA, and a user-friendly software to run real-time control and data processing. It was developed to substitute the older radiation monitor RSS-112 PIC installed in CNESTEN's Laboratory in order to improve some of its functionalities related to acquisition time and data memory capacity. As for the associated acquisition software, it was conceived under the virtual LabView platform from National Instrument, and offers a variety of system setup for radiation environmental monitoring. It gives choice to display both the statistical data and the dose rate. Statistical data shows a summary of current data, current time/date and dose integrator values, and the dose rate displays the current dose rate in large numbers for viewing from a distance as well as the date and time. The prototype version of this new instrument and its data processing software has been successfully tested and validated for viewing and monitoring the environmental radiation of Moroccan nuclear center. (authors)

  7. Verification of FPGA-based NPP I and C systems. General approach and techniques

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Reva, Lubov; Siora, Alexander

    2011-01-01

    This paper presents a general approach and techniques for design and verification of Field Programmable Gates Arrays (FPGA)-based Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP). Appropriate regulatory documents used for I and C systems design, development, verification and validation (V and V) are discussed considering the latest international standards and guidelines. Typical development and V and V processes of FPGA electronic design for FPGA-based NPP I and C systems are presented. Some safety-related features of implementation process are discussed. Corresponding development artifacts, related to design and implementation activities are outlined. An approach to test-based verification of FPGA electronic design algorithms, used in FPGA-based reactor trip systems is proposed. The results of application of test-based techniques for assessment of FPGA electronic design algorithms for reactor trip system (RTS) produced by Research and Production Corporation (RPC) 'Radiy' are presented. Some principles of invariant-oriented verification for FPGA-based safety-critical systems are outlined. (author)

  8. Logic qualification of FPGA-based safety-related I and C systems

    International Nuclear Information System (INIS)

    Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

    2009-01-01

    We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

  9. An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator

    Directory of Open Access Journals (Sweden)

    Runchun M. Wang

    2018-04-01

    Full Text Available This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons. This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

  10. FPGA-based RF spectrum merging and adaptive hopset selection

    Science.gov (United States)

    McLean, R. K.; Flatley, B. N.; Silvius, M. D.; Hopkinson, K. M.

    The radio frequency (RF) spectrum is a limited resource. Spectrum allotment disputes stem from this scarcity as many radio devices are confined to a fixed frequency or frequency sequence. One alternative is to incorporate cognition within a reconfigurable radio platform, therefore enabling the radio to adapt to dynamic RF spectrum environments. In this way, the radio is able to actively sense the RF spectrum, decide, and act accordingly, thereby sharing the spectrum and operating in more flexible manner. In this paper, we present a novel solution for merging many distributed RF spectrum maps into one map and for subsequently creating an adaptive hopset. We also provide an example of our system in operation, the result of which is a pseudorandom adaptive hopset. The paper then presents a novel hardware design for the frequency merger and adaptive hopset selector, both of which are written in VHDL and implemented as a custom IP core on an FPGA-based embedded system using the Xilinx Embedded Development Kit (EDK) software tool. The design of the custom IP core is optimized for area, and it can process a high-volume digital input via a low-latency circuit architecture. The complete embedded system includes the Xilinx PowerPC microprocessor, UART serial connection, and compact flash memory card IP cores, and our custom map merging/hopset selection IP core, all of which are targeted to the Virtex IV FPGA. This system is then incorporated into a cognitive radio prototype on a Rice University Wireless Open Access Research Platform (WARP) reconfigurable radio.

  11. An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

    International Nuclear Information System (INIS)

    Jung, Sejin; Kim, Eui-Sub; Yoo, Junbeom; Kim, Jang-Yeol; Choi, Jong Gyun

    2016-01-01

    Highlights: • All direct/indirect COTS SW should be dedicated. • FPGA synthesis tools are important for the safety of new digital I&Cs. • No standards/reports are yet available to deal with the indirect SW – FPGA synthesis tools. • This paper proposes a new evaluation/acceptance process and criteria for indirect SW. - Abstract: FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

  12. Realise of PWM-generating based on FPGA

    International Nuclear Information System (INIS)

    Su Rongfeng; Xu Ruinian; Huang Maomao

    2012-01-01

    The power supply digital controllers of Shanghai Synchrotron Radiation Facility(SSRF) make use of the PWM (pulse width modulation) wave as the feedback to the power-electrical devices, so as to obtain constant current of high accuracy and stability. The design of PWM wave generation structure in FPGA is good for a compact controller,and the reduction of the usage of Integrated Circuits (ICs) decreases the interference from the noise among the ICs, hence better performance of the controller. In addition, FPGA can be programmed circularly at any time,so as to optimize the structure design and make a maximum use of the advantage of FPGA. As a part of transplanting the complete function of the DSP (digital signal processor/processing), realizing the generation of PWM wave in FPGA is feasible. In this paper, we report progress in this regard at SSRF. (authors)

  13. Note: Design of FPGA based system identification module with application to atomic force microscopy

    Science.gov (United States)

    Ghosal, Sayan; Pradhan, Sourav; Salapaka, Murti

    2018-05-01

    The science of system identification is widely utilized in modeling input-output relationships of diverse systems. In this article, we report field programmable gate array (FPGA) based implementation of a real-time system identification algorithm which employs forgetting factors and bias compensation techniques. The FPGA module is employed to estimate the mechanical properties of surfaces of materials at the nano-scale with an atomic force microscope (AFM). The FPGA module is user friendly which can be interfaced with commercially available AFMs. Extensive simulation and experimental results validate the design.

  14. Development of an FPGA-based controller for safety critical application

    International Nuclear Information System (INIS)

    Xing, A.; De Grosbois, J.; Sklyar, V.; Archer, P.; Awwal, A.

    2011-01-01

    In implementing safety functions, Field Programmable Gate Arrays (FPGA) technology offers a distinct combination of benefits and advantages over microprocessor-based systems. FPGAs can be designed such that the final product is purely hardware, without any overhead runtime software, bringing the design closer to a conventional hardware-based solution. On the other hand, FPGAs can implement more complex safety logic that would generally require microprocessor-based safety systems. There are now qualified FPGA-based platforms available on the market with a credible use history in safety applications in nuclear power plants. Atomic Energy of Canada (AECL), in collaboration with RPC Radiy, has initiated a development program to define a vigorous FPGA engineering process suitable for implementing safety critical functions at the application development level. This paper provides an update on the FPGA development program along with the proposed design model using function block diagrams for the development of safety controllers in CANDU applications. (author)

  15. Advanced Image Processing Package for FPGA-Based Re-Programmable Miniature Electronics

    National Research Council Canada - National Science Library

    Ovod, Vladimir I; Baxter, Christopher R; Massie, Mark A; McCarley, Paul L

    2005-01-01

    .... An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical background...

  16. Innovative approach to implementation of FPGA-based NPP instrumentation and control systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Siora, Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper. (author)

  17. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; SIORA Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper

  18. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    Energy Technology Data Exchange (ETDEWEB)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir [Centre for Safety Infrastructure-Oriented Research and Analysis, Kharkov (Ukraine); SIORA Alexander [Research and Production Corporation Radiy, Kirovograd (Ukraine)

    2011-08-15

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper.

  19. A natural-color mapping for single-band night-time image based on FPGA

    Science.gov (United States)

    Wang, Yilun; Qian, Yunsheng

    2018-01-01

    A natural-color mapping for single-band night-time image method based on FPGA can transmit the color of the reference image to single-band night-time image, which is consistent with human visual habits and can help observers identify the target. This paper introduces the processing of the natural-color mapping algorithm based on FPGA. Firstly, the image can be transformed based on histogram equalization, and the intensity features and standard deviation features of reference image are stored in SRAM. Then, the real-time digital images' intensity features and standard deviation features are calculated by FPGA. At last, FPGA completes the color mapping through matching pixels between images using the features in luminance channel.

  20. FPGA-based prototype storage system with phase change memory

    Science.gov (United States)

    Li, Gezi; Chen, Xiaogang; Chen, Bomy; Li, Shunfen; Zhou, Mi; Han, Wenbing; Song, Zhitang

    2016-10-01

    With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

  1. Electronic readout for THGEM detectors based on FPGA TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Koenigsmann, Kay; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany); Collaboration: COMPASS-II RICH upgrade Group

    2013-07-01

    In the framework of the RD51 programme the characteristics of a new detector design, called THGEM, which is based on multi-layer arrangements of printed circuit board material, is investigated. The THGEMs combine the advantages for covering gains up to 10{sup 6} in electron multiplication at large detector areas and low material budget. Studies are performed by extending the design to a hybrid gas detector by adding a Micromega layer, which significantly improves the ion back flow ratio of the chamber. With the upgrade of the COMPASS experiment at CERN a MWPC plane of the RICH-1 detector will be replaced by installing THGEM chambers. This summarizes to 40k channels of electronic readout, including amplification, discrimination and time-to-digital conversion of the anode signals. Due to the expected hit rate of the detector we design a cost-efficient TDC, based on Artix7 FPGA technology, with time resolution below 100 ps and sufficient hit buffer depth. To cover the large readout area the data is transferred via optical fibres to a central readout system which is part of the GANDALF framework.

  2. Implementation of Wireless Communications Systems on FPGA-Based Platforms

    Directory of Open Access Journals (Sweden)

    Voros NS

    2007-01-01

    Full Text Available Wireless communications are a very popular application domain. The efficient implementation of their components (access points and mobile terminals/network interface cards in terms of hardware cost and design time is of great importance. This paper describes the design and implementation of the HIPERLAN/2 WLAN system on a platform including general purpose microprocessors and FPGAs. Detailed implementation results (performance, code size, and FPGA resources utilization are presented. The main goal of the design case presented is to provide insight into the design aspects of a complex system based on FPGAs. The results prove that an implementation based on microprocessors and FPGAs is adequate for the access point part of the system where the expected volumes are rather small. At the same time, such an implementation serves as a prototyping of an integrated implementation (System-on-Chip, which is necessary for the mobile terminals of a HIPERLAN/2 system. Finally, firmware upgrades were developed allowing the implementation of an outdoor wireless communication system on the same platform.

  3. Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

    2012-01-01

    This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

  4. Design Verification Enhancement of FPGA-based Plant Protection System Trip Logics for Nuclear Power Plant

    International Nuclear Information System (INIS)

    Ahmed, Ibrahim; Jung, Jae Cheon; Heo, Gyun Young

    2016-01-01

    As part of strengthening the application of FPGA technology and find solution to its challenges in NPPs, international atomic energy agency (IAEA) has indicated interest by joining sponsorship of Topical Group on FPGA Applications in NPPs (TG-FAN) that hold meetings up to 7th times until now, in form of workshop (International workshop on the application of FPGAs in NPPs) annually since 2008. The workshops attracted a significant interest and had a broad representation of stakeholders such as regulators, utilities, research organizations, system designers, and vendors, from various countries that converge to discuss the current issues regarding instrumentation and control (I and C) systems as well as FPGA applications. Two out of many technical issues identified by the group are lifecycle of FPGA-based platforms, systems, and applications; and methods and tools for V and V. Therefore, in this work, several design steps that involved the use of model-based systems engineering process as well as MATLAB/SIMULINK model which lead to the enhancement of design verification are employed. The verified and validated design output works correctly and effectively. Conclusively, the model-based systems engineering approach and the structural step-by-step design modeling techniques including SIMULINK model utilized in this work have shown how FPGA PPS trip logics design verification can be enhanced. If these design approaches are employ in the design of FPGA-based I and C systems, the design can be easily verified and validated

  5. An FPGA- Based General-Purpose Data Acquisition Controller

    Science.gov (United States)

    Robson, C. C. W.; Bousselham, A.; Bohm

    2006-08-01

    System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems

  6. Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

    Directory of Open Access Journals (Sweden)

    He Chen

    2011-12-01

    Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

  7. A FPGA-based architecture for real-time image matching

    Science.gov (United States)

    Wang, Jianhui; Zhong, Sheng; Xu, Wenhui; Zhang, Weijun; Cao, Zhiguo

    2013-10-01

    Image matching is a fundamental task in computer vision. It is used to establish correspondence between two images taken at different viewpoint or different time from the same scene. However, its large computational complexity has been a challenge to most embedded systems. This paper proposes a single FPGA-based image matching system, which consists of SIFT feature detection, BRIEF descriptor extraction and BRIEF matching. It optimizes the FPGA architecture for the SIFT feature detection to reduce the FPGA resources utilization. Moreover, we implement BRIEF description and matching on FPGA also. The proposed system can implement image matching at 30fps (frame per second) for 1280x720 images. Its processing speed can meet the demand of most real-life computer vision applications.

  8. FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

    Directory of Open Access Journals (Sweden)

    Swapnil Mhaske

    2017-01-01

    Full Text Available We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

  9. Logic synthesis for FPGA-based finite state machines

    CERN Document Server

    Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

    2016-01-01

    This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

  10. FPGA hardware acceleration for high performance neutron transport computation based on agent methodology - 318

    International Nuclear Information System (INIS)

    Shanjie, Xiao; Tatjana, Jevremovic

    2010-01-01

    The accurate, detailed and 3D neutron transport analysis for Gen-IV reactors is still time-consuming regardless of advanced computational hardware available in developed countries. This paper introduces a new concept in addressing the computational time while persevering the detailed and accurate modeling; a specifically designed FPGA co-processor accelerates robust AGENT methodology for complex reactor geometries. For the first time this approach is applied to accelerate the neutronics analysis. The AGENT methodology solves neutron transport equation using the method of characteristics. The AGENT methodology performance was carefully analyzed before the hardware design based on the FPGA co-processor was adopted. The most time-consuming kernel part is then transplanted into the FPGA co-processor. The FPGA co-processor is designed with data flow-driven non von-Neumann architecture and has much higher efficiency than the conventional computer architecture. Details of the FPGA co-processor design are introduced and the design is benchmarked using two different examples. The advanced chip architecture helps the FPGA co-processor obtaining more than 20 times speed up with its working frequency much lower than the CPU frequency. (authors)

  11. A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

    Science.gov (United States)

    Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

    2015-10-01

    Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

  12. FPGA design best practices for team-based reuse

    CERN Document Server

    Simpson, Philip Andrew

    2015-01-01

    This book describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book’s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expand...

  13. FPGA based fast synchronous serial multi-wire links synchronization

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2013-10-01

    The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

  14. FPGA-based implementation of sorting networks in MMC applications

    DEFF Research Database (Denmark)

    Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

    2016-01-01

    , and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance...

  15. STAR: FPGA-based software defined satellite transponder

    Science.gov (United States)

    Davalle, Daniele; Cassettari, Riccardo; Saponara, Sergio; Fanucci, Luca; Cucchi, Luca; Bigongiari, Franco; Errico, Walter

    2013-05-01

    This paper presents STAR, a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites, developed in collaboration with INTECS and SITAEL companies. With respect to state-of-the-art EO transponders, STAR includes the possibility of scientific data transfer thanks to the 40 Mbps downlink data-rate. This feature represents an important optimization in terms of hardware mass, which is important for EO small satellites. Furthermore, in-flight re-configurability of communication parameters via telecommand is important for in-orbit link optimization, which is especially useful for low orbit satellites where visibility can be as short as few hundreds of seconds. STAR exploits the principles of digital radio to minimize the analog section of the transceiver. 70MHz intermediate frequency (IF) is the interface with an external S/X band radio-frequency front-end. The system is composed of a dedicated configurable high-speed digital signal processing part, the Signal Processor (SP), described in technology-independent VHDL working with a clock frequency of 184.32MHz and a low speed control part, the Control Processor (CP), based on the 32-bit Gaisler LEON3 processor clocked at 32 MHz, with SpaceWire and CAN interfaces. The quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss which is less than 0.5 dB at BER = 10-5 for the RX chain. The IF ports require 8-bit precision. The system prototype is fitted on the Xilinx Virtex 6 VLX75T-FF484 FPGA of which a space-qualified version has been announced. The total device occupation is 82 %.

  16. Spatial and color clustering on an FPGA-based computer system

    Science.gov (United States)

    Leeser, Miriam E.; Kitaryeva, Natalya V.; Crisman, Jill D.

    1998-10-01

    We are mapping an image clustering algorithm onto an FPGA- based computer system. Our approach processes raw pixel data in the red, green, blue color space and generates an output image where all pixels are assigned to classes. A class is a group of pixels with similar color and location. These classes are then used as the basis of further processing to generate tags. The tags, in turn, are used to generate queries for searching libraries of digital images. We run our image tagging approach on an FPGA-based computing machine. The image clustering algorithm is run on an FPGA board, and only the classified image is communicated to the host PC. Further processing is run on the host. Our experimental system consists of an Annapolis Wildforce board with four Xilinx XC4000 chips and a PCI connection to a host PC. Our implementation allows the raw image data to stay local to the FPGAs, and only the class image is communicated to the host PC. The classified pixels are then used to generate tags which can be used for searching a digital library. This approach allows us to parallelize the image processing on the FPGA board, and to minimize the data handled by the PC. FPGA platforms are ideally suited for this sort of initial processing of images. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures, keeping unnecessary data off the host processor. The result of our algorithm is a reduction by up to a factor of six in the number of bits required to represent each pixel. The output data is passed to the host PC, thus reducing the processing and memory resources needed compared to handling the raw data on the PC. The process of generating tags of images is simplified by first classifying pixels on an FPGA-based system, and digital library search is accelerated.

  17. An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

    International Nuclear Information System (INIS)

    Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah; Choi, Jong Gyun

    2014-01-01

    NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity

  18. An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

    Energy Technology Data Exchange (ETDEWEB)

    Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun [KAERI, Daejeon (Korea, Republic of)

    2014-08-15

    NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity.

  19. FPGA-based digital convolution for wireless applications

    CERN Document Server

    Guan, Lei

    2017-01-01

    This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

  20. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    Energy Technology Data Exchange (ETDEWEB)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I. [Research and Production Corporation Radiy, 29 Geroev Stalingrada Str., Kirovograd 25006 (Ukraine); Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A., E-mail: marketing@radiy.co [Center for Safety Infrastructure-Oriented Research and Analysis, 37 Astronomicheskaya Str., Kharkiv 61085 (Ukraine)

    2010-10-15

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY{sup TM} platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY{sup TM} platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY{sup TM} platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  1. Design for an IO block array in a tile-based FPGA

    International Nuclear Information System (INIS)

    Ding Guangxin; Chen Lingdou; Liu Zhongli

    2009-01-01

    A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 μm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process. (semiconductor integrated circuits)

  2. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    International Nuclear Information System (INIS)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I.; Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A.

    2010-10-01

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY TM platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY TM platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY TM platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  3. FPGA based, modular, configurable controller with fast synchronous optical network

    Energy Technology Data Exchange (ETDEWEB)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

    2006-07-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  4. FPGA based, modular, configurable controller with fast synchronous optical network

    International Nuclear Information System (INIS)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S.

    2006-01-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  5. FPGA based mixed-signal circuit novel testing techniques

    International Nuclear Information System (INIS)

    Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

    2013-01-01

    Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

  6. VHDL resolved function based inner communication bus for FPGA

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2017-08-01

    This article discusses a method of building an internal, universal and parametric bus. The solution was designed for a variety of FPGA families and popular VHDL compilers. The algorithm of automatic configuration of address space and methods of receiving and sending addressed data are discussed. The basic solution realized in VHDL language in a behavioral form and chosen examples of practical use of the internal bus are presented in detail.

  7. A low delay transmission method of multi-channel video based on FPGA

    Science.gov (United States)

    Fu, Weijian; Wei, Baozhi; Li, Xiaobin; Wang, Quan; Hu, Xiaofei

    2018-03-01

    In order to guarantee the fluency of multi-channel video transmission in video monitoring scenarios, we designed a kind of video format conversion method based on FPGA and its DMA scheduling for video data, reduces the overall video transmission delay.In order to sace the time in the conversion process, the parallel ability of FPGA is used to video format conversion. In order to improve the direct memory access (DMA) writing transmission rate of PCIe bus, a DMA scheduling method based on asynchronous command buffer is proposed. The experimental results show that this paper designs a low delay transmission method based on FPGA, which increases the DMA writing transmission rate by 34% compared with the existing method, and then the video overall delay is reduced to 23.6ms.

  8. Diversity for security: case assessment for FPGA-based safety-critical systems

    Directory of Open Access Journals (Sweden)

    Kharchenko Vyacheslav

    2016-01-01

    Full Text Available Industrial safety critical instrumentation and control systems (I&Cs are facing more with information (in general and cyber, in particular security threats and attacks. The application of programmable logic, first of all, field programmable gate arrays (FPGA in critical systems causes specific safety deficits. Security assessment techniques for such systems are based on heuristic knowledges and the expert judgment. Main challenge is how to take into account features of FPGA technology for safety critical I&Cs including systems in which are applied diversity approach to minimize risks of common cause failure. Such systems are called multi-version (MV systems. The goal of the paper is in description of the technique and tool for case-based security assessment of MV FPGA-based I&Cs.

  9. Design of optical axis jitter control system for multi beam lasers based on FPGA

    Science.gov (United States)

    Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

    2018-02-01

    A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

  10. An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm

    Directory of Open Access Journals (Sweden)

    Peter Irgens

    2017-04-01

    Full Text Available We present an field programmable gate arrays (FPGA based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping.

  11. Motion camera based on a custom vision sensor and an FPGA architecture

    Science.gov (United States)

    Arias-Estrada, Miguel

    1998-09-01

    A digital camera for custom focal plane arrays was developed. The camera allows the test and development of analog or mixed-mode arrays for focal plane processing. The camera is used with a custom sensor for motion detection to implement a motion computation system. The custom focal plane sensor detects moving edges at the pixel level using analog VLSI techniques. The sensor communicates motion events using the event-address protocol associated to a temporal reference. In a second stage, a coprocessing architecture based on a field programmable gate array (FPGA) computes the time-of-travel between adjacent pixels. The FPGA allows rapid prototyping and flexible architecture development. Furthermore, the FPGA interfaces the sensor to a compact PC computer which is used for high level control and data communication to the local network. The camera could be used in applications such as self-guided vehicles, mobile robotics and smart surveillance systems. The programmability of the FPGA allows the exploration of further signal processing like spatial edge detection or image segmentation tasks. The article details the motion algorithm, the sensor architecture, the use of the event- address protocol for velocity vector computation and the FPGA architecture used in the motion camera system.

  12. Application of the Information Encryption Technology in the Industrial Control Network Based on FPGA

    Directory of Open Access Journals (Sweden)

    Guo Yao-Hua

    2014-07-01

    Full Text Available With the rapid development of information technology industry, Information encryption is an effective means of information security. Data encryption system based on FPGA in the field of industry is elaborated in this paper, and the data acquisition module, the basic principle of 3DES algorithm, its implementation in FPGA and PMC bus interface module are introduced. Based on the function simulation, test and analysis of the design results, this scheme has the characteristics of high reliability, fast algorithm and less hardware resources, and it can be widely used in industrial networks.

  13. Multirate Digital Filters Based on FPGA and Its Applications

    International Nuclear Information System (INIS)

    Sharaf El-Din, R.M.A.

    2013-01-01

    Digital Signal Processing (DSP) is one of the fastest growing techniques in the electronics industry. It is used in a wide range of application fields such as, telecommunications, data communications, image enhancement and processing, video signals, digital TV broadcasting, and voice synthesis and recognition. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high performance DSP systems. The focus of this thesis is on one of the basic DSP functions, namely filtering signals to remove unwanted frequency bands. Multi rate Digital Filters (MDFs) are the main theme here. Theory and implementation of MDF, as a special class of digital filters, will be discussed. Multi rate digital filters represent a class of digital filters having a number of attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. This thesis introduces an efficient FPGA realization of a multi rate decimation filter with narrow pass-band and narrow transition band to reduce the frequency sample rate by factor of 64 for noise thermometer applications. The proposed multi rate decimation filter is composed of three stages; the first stage is a Cascaded Integrator Comb (CIC) decimation filter, the second stage is a two-coefficient Half-Band (HB) filter and the last stage is a sharper transition HB filter. The frequency responses of individual stages as well as the overall filter response have been demonstrated with full simulation using MATLAB. The design and implementation of the proposed MDF on FPGA (XILINX Virtex XCV800 BG432-4), using VHSIC Hardware Description Language (VHDL), has been introduced. The implementation areas of the proposed filter stages are compared. Using CIC-HB technique saves 18% of the design area, compared to using six stages HB decimation filters.

  14. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    Millar James

    2006-01-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  15. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    James Millar

    2006-10-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  16. RADIOMETRIC CALIBRATION OF MARS HiRISE HIGH RESOLUTION IMAGERY BASED ON FPGA

    Directory of Open Access Journals (Sweden)

    Y. Hou

    2016-06-01

    Full Text Available Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

  17. Data acquisition system for charge-division mechanism based on FPGA

    International Nuclear Information System (INIS)

    Yang Litao; Li Dongcang; Yang Lei; Wu Huaiyi; Qi Zhong

    2010-01-01

    Design a system of Peak value acquisition, data processing and data output for 4 channels nuclear signal at the same time by FPGA that base on the basic principle of position information readout for particle through Charger-division Mechanism. In view of the randomness of nuclear signal, so insert asynchronous FIFO in the system, which greatly improve the sampling rate of system. In the article has produced the conjunctive relation and inner circuit structure and give out simulation. From here, you can see the great power of FPGA which used in nuclear data acquisition and processing system. (authors)

  18. SEU mitigation technique by Dynamic Reconfiguration method in FPGA based DSP application

    International Nuclear Information System (INIS)

    Dey, Madhusudan; Singh, Abhishek; Roy, Amitava

    2012-01-01

    Field Programmable Gate Array (FPGA), an SRAM based configurable devices meant for implementation of any digital circuits is susceptible to malfunction in the harsh radiation environment. It causes the corruption of the configuration memory of FPGA and the digital circuits starts malfunctioning. There is a need to restore the system as early as possible. This paper discusses about one such technique named dynamic partial reconfiguration (DPR) method. This paper also touches upon the signal processing by DPR method. The framework consisting of ADC, DAC and ICAP controllers designed using dedicated state machines to study the best possible downtime also for verifying the performance of digital filters for signal processing

  19. Implementation of FPGA based PID Controller for DC Motor Speed Control System

    Directory of Open Access Journals (Sweden)

    Savita SONOLI

    2010-03-01

    Full Text Available In this paper, the implementation of software module using ‘VHDL’ for Xilinx FPGA (XC3S400 based PID controller for DC motor speed control system is presented. The tools used for building and testing the software modules are Xilinx ISE 9.2i and ModelSim XE III 6.3c. Before verifying the design on FPGA the complete design is simulated using Modelsim Simulation tool. A test bench is written where the set speed can be changed for the motor. It is observed that the motor speed gradually changes to the set speed and locks to the set speed.

  20. The FPGA realization of the general cellular automata based cryptographic hash functions: Performance and effectiveness

    Directory of Open Access Journals (Sweden)

    P. G. Klyucharev

    2014-01-01

    Full Text Available In the paper the author considers hardware implementation of the GRACE-H family general cellular automata based cryptographic hash functions. VHDL is used as a language and Altera FPGA as a platform for hardware implementation. Performance and effectiveness of the FPGA implementations of GRACE-H hash functions were compared with Keccak (SHA-3, SHA-256, BLAKE, Groestl, JH, Skein hash functions. According to the performed tests, performance of the hardware implementation of GRACE-H family hash functions significantly (up to 12 times exceeded performance of the hardware implementation of previously known hash functions, and effectiveness of that hardware implementation was also better (up to 4 times.

  1. The implementing of high resolution time measuring circuit based on FPGA

    International Nuclear Information System (INIS)

    Zhang Ji; Zeng Yun; Wang Zheng; Li Quiju; Lu Jifang; Wu Jinyuan

    2011-01-01

    It presents the implementing of TDC based on FPGA. The fine timing function part is accomplished through the time interpolators that are composed of the carry chain of intrinsic adders in FPGA. This architecture dates back to the latest technology-WUTDC (Wave Union TDC) that is developed to sub-divide the ultra-wide bins and improve the measure resolution. The board and the online test have been proved that the linearity of converters is satisfying and the time resolution is better than 40 ps. (authors)

  2. Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

    DEFF Research Database (Denmark)

    Singh, Ritu; Kalia, Kartik; Minver, M. H.

    2016-01-01

    Abstract-In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobile...

  3. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

  4. Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Hegner, Jonas Stenbæk; Sindholt, Joakim; Nannarelli, Alberto

    2012-01-01

    Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation...

  5. Development of a prototype acquisition and data processing system based on FPGA

    International Nuclear Information System (INIS)

    Romero, L; Bellino, P

    2012-01-01

    We present the first stage of the expansion and improvement of a signal acquisition system based on FPGA. This system will acquire and process signals from nuclear detectors working in both pulse and current mode. The aim of this development is to unify all the actual systems for physical measurements in nuclear facilities and reactors (author)

  6. FPGA Based Low Power Router Design Using High Speed Transeceiver Logic IO Standard

    DEFF Research Database (Denmark)

    Thind, Vandana; Hussain, Dil muhammed Akbar

    2015-01-01

    and information. Router is main component of computer networks is an intelligent device uses to transfer data packets between various computer networks. Router must consume low power to perform its work in an efficient manner. To achieve the same the work has been done to make a FPGA based low power design using...

  7. A signature-based power model for MPSoC on FPGA

    NARCIS (Netherlands)

    Piscitelli, R.; Pimentel, A.D.

    2012-01-01

    This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used

  8. Remote monitoring and fault recovery for FPGA-based field controllers of telescope and instruments

    Science.gov (United States)

    Zhu, Yuhua; Zhu, Dan; Wang, Jianing

    2012-09-01

    As the increasing size and more and more functions, modern telescopes have widely used the control architecture, i.e. central control unit plus field controller. FPGA-based field controller has the advantages of field programmable, which provide a great convenience for modifying software and hardware of control system. It also gives a good platform for implementation of the new control scheme. Because of multi-controlled nodes and poor working environment in scattered locations, reliability and stability of the field controller should be fully concerned. This paper mainly describes how we use the FPGA-based field controller and Ethernet remote to construct monitoring system with multi-nodes. When failure appearing, the new FPGA chip does self-recovery first in accordance with prerecovery strategies. In case of accident, remote reconstruction for the field controller can be done through network intervention if the chip is not being restored. This paper also introduces the network remote reconstruction solutions of controller, the system structure and transport protocol as well as the implementation methods. The idea of hardware and software design is given based on the FPGA. After actual operation on the large telescopes, desired results have been achieved. The improvement increases system reliability and reduces workload of maintenance, showing good application and popularization.

  9. FPGA-based trigger system for the Fermilab SeaQuest experimentz

    Energy Technology Data Exchange (ETDEWEB)

    Shiu, Shiuan-Hal, E-mail: shshiu@phys.sinica.edu.tw [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Department of Physics, National Central University, No. 300, Jhongda Rd., Jhongli District, Taoyuan City 32001, Taiwan (China); Wu, Jinyuan [Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); McClellan, Randall Evan [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Gilman, Ron [Rutgers, The State University of New Jersey, 136 Frelinghuysen Rd., Piscataway, NJ 08854 (United States); Nakano, Kenichi [Department of Physics, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550 (Japan); Peng, Jen-Chieh [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Wang, Su-Yin [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); Department of Physics, National Kaohsiung Normal University, No. 62, Shenjhong Rd.,Yanchao Township, Kaohsiung County 824, Taiwan (China)

    2015-12-01

    The SeaQuest experiment (Fermilab E906) detects pairs of energetic μ{sup +} and μ{sup −} produced in 120 GeV/c proton–nucleon interactions in a high rate environment. The trigger system consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined against pre-determined trigger matrices to identify candidate muon tracks. Information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.

  10. A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

    Directory of Open Access Journals (Sweden)

    Kevin R. Townsend

    2015-01-01

    Full Text Available On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

  11. CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

    CERN Document Server

    Zhu, Yu

    2010-01-01

    Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

  12. On the speed of response of an FPGA-based shutdown system in CANDU nuclear power plants

    Energy Technology Data Exchange (ETDEWEB)

    She Jingke, E-mail: jshe2@uwo.ca [Department of Electrical and Computer Engineering, The University of Western Ontario, London, Ontario, N6A 5B9 (Canada); Jiang Jin, E-mail: jjiang@eng.uwo.ca [Department of Electrical and Computer Engineering, The University of Western Ontario, London, Ontario, N6A 5B9 (Canada)

    2011-06-15

    Highlights: > Design and implementation of an FPGA-based CANDU SDS1. > Hardware-in-the-loop simulation for performance evaluation involved with an NPP simulator. > Comparison of the response time between FPGA-based trip channel and software-based PLC. - Abstract: Several issues in an FPGA based implementation of shutdown systems in CANDU nuclear power plants have been investigated in this paper. A particular attention is on the response time of an FPGA implementation of safety shutdown systems in comparison with operating system based software solutions as in existing CANDU plants. The trip decision logic under 'steam generator (SG) level low' condition has been examined in detail. The design and implementation of this logic on an FPGA platform have been carried out. The functionality tests are performed in a hardware-in-the-loop (HIL) environment by connecting the FPGA based system to an NPP simulator, and replacing one channel of Shutdown System Number 1 (SDS1) in the simulator by the FPGA implementation. The response time of the designed system is also measured through multiple tests under different conditions, and statistical data analysis has been performed. The results of the response time tests are compared against those of a software-based implementation of the same trip logic.

  13. An Intelligent FPGA Based Anti-Sweating System for Bed Sore Prevention in a Clinical Environment

    Directory of Open Access Journals (Sweden)

    K. S. Jaichandar

    2011-01-01

    Full Text Available Bed sores, a common problem among immobile patients occur as a result of continuous sweating due to increase in skin to bed surface temperature in patients lying on same posture for prolonged period. If left untreated, the skin can break open and become infected. Currently adopted methods for bed sores prevention include: use of two hourly flip chat for repositioning patient or use of air fluidized beds. However, the setbacks of these preventive measures include either use of costly equipment or wastage of human resources. This paper introduces an intelligent low cost FPGA based anti-sweating system for bed sores prevention in a clinical environment. The developed system consists of bed surface implanted temperature sensors interfaced with an FPGA chip for sensing the temperature change in patient’s skin to bed surface. Based on the temperature change, the FPGA chip select the - mode (heater/cooler and speed of the fan module. Furthermore, an alarm module was implemented to alert the nurse to reposition the patient only if patient’s skin to bed surface temperature exceeds a predefined threshold thereby saving human resources. By integrating the whole system into a single FPGA chip, we were able to build a low cost compact system without sacrificing processing power and flexibility.

  14. LDPC decoder with a limited-precision FPGA-based floating-point multiplication coprocessor

    Science.gov (United States)

    Moberly, Raymond; O'Sullivan, Michael; Waheed, Khurram

    2007-09-01

    Implementing the sum-product algorithm, in an FPGA with an embedded processor, invites us to consider a tradeoff between computational precision and computational speed. The algorithm, known outside of the signal processing community as Pearl's belief propagation, is used for iterative soft-decision decoding of LDPC codes. We determined the feasibility of a coprocessor that will perform product computations. Our FPGA-based coprocessor (design) performs computer algebra with significantly less precision than the standard (e.g. integer, floating-point) operations of general purpose processors. Using synthesis, targeting a 3,168 LUT Xilinx FPGA, we show that key components of a decoder are feasible and that the full single-precision decoder could be constructed using a larger part. Soft-decision decoding by the iterative belief propagation algorithm is impacted both positively and negatively by a reduction in the precision of the computation. Reducing precision reduces the coding gain, but the limited-precision computation can operate faster. A proposed solution offers custom logic to perform computations with less precision, yet uses the floating-point format to interface with the software. Simulation results show the achievable coding gain. Synthesis results help theorize the the full capacity and performance of an FPGA-based coprocessor.

  15. A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

    International Nuclear Information System (INIS)

    Quinn, Heather M.; Graham, Paul S.; Morgan, Keith S.; Caffrey, Michael P.

    2008-01-01

    Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

  16. An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

    Directory of Open Access Journals (Sweden)

    Lai Chiu-Keng

    2016-01-01

    Full Text Available A Field Programmable Gate Array based system is a great hardware platform to support the implementation of hardware controllers such as PID controller and fuzzy controller. It is also programmed as hardware accelerator to speed up the mathematic calculation and greatly enhance the performance as applied to motor drive and motion control. Furthermore, the open structure of FPGA-based system is suitable for those designs with the ability of parallel processing or soft code processor embedded. In this paper, we apply the FPGA to a multi-axis velocity controller design. The developed system integrated three functions inside the FPGA chip, which are respectively the stepping motor drive, the multi-axis motion controller and the motion planning. Furthermore, an embedded controller with a soft code processor compatible to 8051 micro-control unit (MCU is built to handle the data transfer between the FPGA board and host PC. The MCU is also used to initialize the motion control and run the interpolator. The designed system is practically applied to a XYZ motion platform which is driven by stepping motors to verify its performance.

  17. A single FPGA-based portable ultrasound imaging system for point-of-care applications.

    Science.gov (United States)

    Kim, Gi-Duck; Yoon, Changhan; Kye, Sang-Bum; Lee, Youngbae; Kang, Jeeun; Yoo, Yangmo; Song, Tai-kyong

    2012-07-01

    We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

  18. Development, verification and validation of an FPGA-based core heat removal protection system for a PWR

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Yichun, E-mail: ycwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China); Shui, Xuanxuan, E-mail: 807001564@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Cai, Yuanfeng, E-mail: 1056303902@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Zhou, Junyi, E-mail: 1032133755@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Wu, Zhiqiang, E-mail: npic_wu@126.com [State Key Laboratory of Reactor System Design Technology, Nuclear Power Institute of China, Chengdu 610041 (China); Zheng, Jianxiang, E-mail: zwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China)

    2016-05-15

    Highlights: • An example on life cycle development process and V&V on FPGA-based I&C is presented. • Software standards and guidelines are used in FPGA-based NPP I&C system logic V&V. • Diversified FPGA design and verification languages and tools are utilized. • An NPP operation principle simulator is used to simulate operation scenarios. - Abstract: To reach high confidence and ensure reliability of nuclear FPGA-based safety system, life cycle processes of discipline specification and implementation of design as well as regulations verification and validation (V&V) are needed. A specific example on how to conduct life cycle development process and V&V on FPGA-based core heat removal (CHR) protection system for CPR1000 pressure water reactor (PWR) is presented in this paper. Using the existing standards and guidelines for life cycle development and V&V, a simplified FPGA-based CHR protection system for PWR has been designed, implemented, verified and validated. Diversified verification and simulation languages and tools are used by the independent design team and the V&V team. In the system acceptance testing V&V phase, a CPR1000 NPP operation principle simulator (OPS) model is utilized to simulate normal and abnormal operation scenarios, and provide input data to the under-test FPGA-based CHR protection system and a verified C code CHR function module. The evaluation results are applied to validate the under-test FPGA-based CHR protection system. The OPS model operation outputs also provide reasonable references for the tests. Using an OPS model in the system acceptance testing V&V is cost-effective and high-efficient. A dedicated OPS, as a commercial-off-the-shelf (COTS) item, would contribute as an important tool in the V&V process of NPP I&C systems, including FPGA-based and microprocessor-based systems.

  19. Embedded algorithms within an FPGA-based system to process nonlinear time series data

    Science.gov (United States)

    Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

    2008-03-01

    This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better

  20. Parallel Hough Transform-Based Straight Line Detection and Its FPGA Implementation in Embedded Vision

    Directory of Open Access Journals (Sweden)

    Nam Ling

    2013-07-01

    Full Text Available Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

  1. Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

    Science.gov (United States)

    Xia, Fei; Jin, Guoqing

    2014-06-01

    PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

  2. EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER

    International Nuclear Information System (INIS)

    HOFF, L.T.

    2005-01-01

    The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control

  3. A novel FPGA-based bunch purity monitor system at the APS storage ring

    International Nuclear Information System (INIS)

    Norum, W.E.

    2008-01-01

    Bunch purity is an important source quality factor for the magnetic resonance experiments at the Advanced Photon Source. Conventional bunch-purity monitors utilizing time-to-amplitude converters are subject to dead time. We present a novel design based on a single field- programmable gate array (FPGA) that continuously processes pulses at the full speed of the detector and front-end electronics. The FPGA provides 7778 single-channel analyzers (six per rf bucket). The starting time and width of each single-channel analyzer window can be set to a resolution of 178 ps. A detector pulse arriving inside the window of a single-channel analyzer is recorded in an associated 32-bit counter. The analyzer makes no contribution to the system dead time. Two channels for each rf bucket count pulses originating from the electrons in the bucket. The other four channels on the early and late side of the bucket provide estimates of the background. A single-chip microcontroller attached to the FPGA acts as an EPICS IOC to make the information in the FPGA available to the EPICS clients.

  4. Parallel Hough Transform-based straight line detection and its FPGA implementation in embedded vision.

    Science.gov (United States)

    Lu, Xiaofeng; Song, Li; Shen, Sumin; He, Kang; Yu, Songyu; Ling, Nam

    2013-07-17

    Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA) provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT) and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

  5. Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system

    Science.gov (United States)

    Chen, Yi-Pin; Chang, Chia-Yuan; Chen, Shean-Jen

    2018-02-01

    In this study, a field programmable gate array (FPGA)-based Shack-Hartmann wavefront sensor (SHWS) programmed on LabVIEW can be highly integrated into customized applications such as adaptive optics system (AOS) for performing real-time wavefront measurement. Further, a Camera Link frame grabber embedded with FPGA is adopted to enhance the sensor speed reacting to variation considering its advantage of the highest data transmission bandwidth. Instead of waiting for a frame image to be captured by the FPGA, the Shack-Hartmann algorithm are implemented in parallel processing blocks design and let the image data transmission synchronize with the wavefront reconstruction. On the other hand, we design a mechanism to control the deformable mirror in the same FPGA and verify the Shack-Hartmann sensor speed by controlling the frequency of the deformable mirror dynamic surface deformation. Currently, this FPGAbead SHWS design can achieve a 266 Hz cyclic speed limited by the camera frame rate as well as leaves 40% logic slices for additionally flexible design.

  6. Design and development of VHDL based IP core for coincidence analyzer for FPGA based TDCR system

    International Nuclear Information System (INIS)

    Agarwal, Shivam; Gupta, Ashutosh; Chaudhury, Probal; Sharma, M.K.; Kulkarni, M.S.

    2018-01-01

    The coincidence counting technique is used in activity measurement methods to determine the activity of radionuclide e.g. 4πβ-γ method and Triple to Double Coincidence Ratio (TDCR) method etc. The 4πβ-γ method requires two inputs Coincidence Analyzer (CA) whereas; TDCR method requires three inputs CA. A VHDL (Very High Speed Integrated Circuit Hardware Description Language) based IP (Intellectual Property) core for coincidence analyzer has been designed and implemented in FPGA (Field Programmable Gate Array) for TDCR system. The developed IP not only facilitates the coincidence counting of three channels simultaneously but also provides an extendable dead time feature

  7. High-definition video display based on the FPGA and THS8200

    Science.gov (United States)

    Qian, Jia; Sui, Xiubao

    2014-11-01

    This paper presents a high-definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data-storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high-definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I2C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high-definition video display, which conforms to the input requirements of the new high-definition display devices.

  8. Functional verification of dynamically reconfigurable FPGA-based systems

    CERN Document Server

    Gong, Lingkan

    2015-01-01

    This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric.  Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an i...

  9. Design of FPGA-based radiation tolerant quench detectors for LHC

    Science.gov (United States)

    Steckert, J.; Skoczen, A.

    2017-04-01

    The Large Hadron Collider (LHC) comprises many superconducting circuits. Most elements of these circuits require active protection. The functionality of the quench detectors was initially implemented as microcontroller based equipment. After the initial stage of the LHC operation with beams the introduction of a new type of quench detector began. This article presents briefly the main ideas and architectures applied to the design and the validation of FPGA-based quench detectors.

  10. Design of FPGA-based radiation tolerant quench detectors for LHC

    International Nuclear Information System (INIS)

    Steckert, J.; Skoczen, A.

    2017-01-01

    The Large Hadron Collider (LHC) comprises many superconducting circuits. Most elements of these circuits require active protection. The functionality of the quench detectors was initially implemented as microcontroller based equipment. After the initial stage of the LHC operation with beams the introduction of a new type of quench detector began. This article presents briefly the main ideas and architectures applied to the design and the validation of FPGA-based quench detectors.

  11. Clock Gating Based Energy Efficient and Thermal Aware Design for Vedic Equation Solver on 28nm and 40nm FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Pandey, Sujeet; Sharma, Shivani

    2016-01-01

    In this paper, we are integrating clock gating in design of energy efficient equation solver circuits based on Vedic mathematics. Clock gating is one of the best energy efficient techniques. The Sutra 'SunyamSamyasamuccaye' says thatif sum of numerator and sum of denominator is same then we can e......, 94.54% for 1800MHz, and 94.02% for 2.2GHz, when we use gated clock instead of un gated one on 40nm FPGA and temperature is 329.85K. Power consumption in 28nm FPGA is less than 40nm FPGA....

  12. Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs

    Science.gov (United States)

    Ladbury, R. L.; Berg, M. D.; Wilcox, E. P.; LaBel, K. A.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2013-01-01

    We investigate the use of commercial FPGA based evaluation boards for radiation testing DDR2 and DDR3 SDRAMs. We evaluate the resulting data quality and the tradeoffs involved in the use of these boards.

  13. Performance enhancement of multi-core fiber transmission using real-time FPGA based pre-emphasis

    NARCIS (Netherlands)

    Hasanuzzaman, G. K.M.; Spolitis, S.; Salgals, T.; Braunfelds, J.; Morales, A.; Gonzalez, L. E.; Rommel, S.; Puerta, R.; Asensio, P.; Bobrovs, V.; Iezekiel, S.; Tafur Monroy, I.

    2017-01-01

    We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA.

  14. Performance enhancement of multi-core fiber transmission using real-time FPGA based pre-emphasis

    DEFF Research Database (Denmark)

    Hasanuzzaman, G. K.M.; Spolitis, Sandis; Salgals, T.

    2017-01-01

    We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA.......We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA....

  15. Implementation of T-box/T/sup -1/-box based AES design on latest xilinx fpga

    International Nuclear Information System (INIS)

    Kundi, D.E.; Aziz, A.

    2015-01-01

    This work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption. (author)

  16. A FPGA-based signal processing unit for a GEM array detector

    International Nuclear Information System (INIS)

    Yen, W.W.; Chou, H.P.

    2013-06-01

    in the present study, a signal processing unit for a GEM one-dimensional array detector is presented to measure the trajectory of photoelectrons produced by cosmic X-rays. The present GEM array detector system has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies. The prototype of the processing unit is implemented using commercial field programmable gate array circuit boards. The FPGA based system is linked to a personal computer for testing and data analysis. Tests using simulated signals indicated that the FPGA-based signal processing unit has a good linearity and is flexible for parameter adjustment for various experimental conditions (authors)

  17. Study on Method of Ultrasonic Gas Temperature Measure Based on FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Wen, S H; Xu, F R [Institute of Electrical Engineering, Yanshan University, Qinhuangdao, 066004 (China)

    2006-10-15

    It is always a problem to measure instantaneous temperature of high-temperature and high-pressure gas. There is difficulty for the conventional method of measuring temperature to measure quickly and exactly, and the measuring precision is low, the ability of anti-jamming is bad, etc. So the article introduces a method of measuring burning gas temperature using ultrasonic based on Field-Programmable Gate Array (FPGA). The mathematic model of measuring temperature is built with the relation of velocity of ultrasonic transmitting and gas Kelvin in the ideal gas. The temperature can be figured out by measuring the difference of ultrasonic frequency {delta}f. FPGA is introduced and a high-precision data acquisition system based on digital phase-shift technology is designed. The feasibility of proposed above is confirmed more by measuring pressure of burning gas timely. Experimental result demonstrates that the error is less than 12.. and the precision is heightened to 0.8%.

  18. Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

    Directory of Open Access Journals (Sweden)

    P. Fiala

    2015-09-01

    Full Text Available This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed.

  19. A Signature-Based Power Model for MPSoC on FPGA

    Directory of Open Access Journals (Sweden)

    Roberta Piscitelli

    2012-01-01

    Full Text Available This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

  20. FPGA - Based Technology and Systems for I and C of Existing and Advanced Reactors

    International Nuclear Information System (INIS)

    Bachmach, E.; Siora, O.; Tokarev, V.; Reshetytsky, S.; Kharchenko, V.; Bezsalyi, V.

    2011-01-01

    Control systems of modern nuclear installations (including water-cooled, WCR) are based on programmable technologies. Most of control systems modernizations which are implemented at operating nuclear installations are also based on application of programmable technologies. Besides, a range of features and properties is defied for programmable technologies. These features and properties make licensing process more complicated, facilitate appearance of common cause failures, make safety evaluation procedures more complicated, etc. Also it is known that programmable technologies significantly extend the time periods for project realization of new power units construction and modernization of the existing power units, and also it involves rise of its value. Company RADIY has developed the Platform of digital equipment RADIY on FPGA-based technology. In the article there is a description of the features of FPGA-technology developed and applied by Company RADIY, features of the Platform RADIY and systems realized on its base, which allow to minimize significantly above-mentioned negative features and properties of programmable technologies. Technology which realized in Platform RADIY allows to solve the whole set of tasks of control (including regulation) and protection of nuclear installations. Platform RADIY is a combination of the best features of traditional programmable technologies and FPGA-technology. According to the opinion of the authors of this article the technology which is realized in Platform RADIY is the key factor for solving of control and protection tasks of nuclear installations in the nearest future. (author)

  1. V&V Plan for FPGA-based ESF-CCS Using System Engineering Approach.

    Science.gov (United States)

    Maerani, Restu; Mayaka, Joyce; El Akrat, Mohamed; Cheon, Jung Jae

    2018-02-01

    Instrumentation and Control (I&C) systems play an important role in maintaining the safety of Nuclear Power Plant (NPP) operation. However, most current I&C safety systems are based on Programmable Logic Controller (PLC) hardware, which is difficult to verify and validate, and is susceptible to software common cause failure. Therefore, a plan for the replacement of the PLC-based safety systems, such as the Engineered Safety Feature - Component Control System (ESF-CCS), with Field Programmable Gate Arrays (FPGA) is needed. By using a systems engineering approach, which ensures traceability in every phase of the life cycle, from system requirements, design implementation to verification and validation, the system development is guaranteed to be in line with the regulatory requirements. The Verification process will ensure that the customer and stakeholder’s needs are satisfied in a high quality, trustworthy, cost efficient and schedule compliant manner throughout a system’s entire life cycle. The benefit of the V&V plan is to ensure that the FPGA based ESF-CCS is correctly built, and to ensure that the measurement of performance indicators has positive feedback that “do we do the right thing” during the re-engineering process of the FPGA based ESF-CCS.

  2. A 32-channel 840Msps TDC based on Altera Cyclone III FPGA

    International Nuclear Information System (INIS)

    Grigoriev, D.N.; Kasyanenko, P.V.; Kravchenko, E.A.; Shamov, A.G.; Talyshev, A.A.

    2017-01-01

    In this work we present a newly developed TDC (Time-to-Digital Converter) board in the VME-32 standard. The 32-channel TDC board is based on a single FPGA Altera Cyclone III chip. The main parameters of the TDC are as follows: a resolution of 1.19 ns, a dead time of 4.76 ns, and a maximal time interval of 19 504 ns.

  3. The characterization and application of a low resource FPGA-based time to digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Balla, Alessandro; Mario Beretta, Matteo; Ciambrone, Paolo; Gatta, Maurizio; Gonnella, Francesco [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); Iafolla, Lorenzo, E-mail: lorenzo.iafolla@lnf.infn.it [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); University of Rome “Tor Vergata” – Electronic Engineering Department (Italy); Mascolo, Matteo; Messi, Roberto [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); University of Rome “Tor Vergata” – Physics Department (Italy); Moricciani, Dario [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); Riondino, Domenico [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy)

    2014-03-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of “off-the-shelf” TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured. - Highlights: • We need to measure the Time of Flight of the detected particles to reconstruct physics events. • We looked for an embedded solution based on an FPGA to implement a TDC with its DAQ system. • The solution is based on the 4xOversampling technique which employs very effectively the FPGA. • The 4×Oversampling technique was characterized and the results and comparisons with the state of the art are presented.

  4. A design of high resolution one-clock-cycle TDC based on FPGA

    International Nuclear Information System (INIS)

    Qi Ji; Deng Zhi; Liu Yinong

    2011-01-01

    It describes an FPGA-based high resolution TDC. Using delay chain and Wave Union methods, this TDC has a resolution of 9 ps, which is comparable to ASIC TDC. The design uses XORs and MUXs to implement a quick 1 -cycle encoder, which reduces the dead time. Self-calibration method makes the design easy to be migrated into other FPGAs. This TDC can be used in TOF experiment, medical imaging system, etc (authors)

  5. BJT detector with FPGA-based read-out for alpha particle monitoring

    International Nuclear Information System (INIS)

    Tyzhnevyi, V; Dalla Betta, G-F; Rovati, L; Verzellesi, G; Zorzi, N

    2011-01-01

    In this work we introduce a new prototype of readout electronics (ALPHADET), which was designed for an α-particle detection system based on a bipolar junction transistor (BJT) detector. The system uses an FPGA, which provides many advantages at the stage of prototyping and testing the detector. The main design and electrical features of the board are discussed in this paper, along with selected results from the characterization of ALPHADET coupled to BJT detectors.

  6. BJT detector with FPGA-based read-out for alpha particle monitoring

    Energy Technology Data Exchange (ETDEWEB)

    Tyzhnevyi, V; Dalla Betta, G-F [Universita di Trento, via Sommarive, 14, 38123 Trento (Italy); Rovati, L [Universita di Modena e Reggio Emilia, via Vignolese 905, 41125 Modena (Italy); Verzellesi, G [Universita di Modena e Reggio Emilia, via Amendola 2, Pad. Morselli, 42100 Reggio Emilia (Italy); Zorzi, N, E-mail: tyzhnevyi@disi.unitn.it [Fondazione Bruno Kessler, via Sommarive, 18, 38123 Trento (Italy)

    2011-01-15

    In this work we introduce a new prototype of readout electronics (ALPHADET), which was designed for an {alpha}-particle detection system based on a bipolar junction transistor (BJT) detector. The system uses an FPGA, which provides many advantages at the stage of prototyping and testing the detector. The main design and electrical features of the board are discussed in this paper, along with selected results from the characterization of ALPHADET coupled to BJT detectors.

  7. Study on modulation amplitude stabilization method for PEM based on FPGA in atomic magnetometer

    Science.gov (United States)

    Wang, Qinghua; Quan, Wei; Duan, Lihong

    2017-10-01

    Atomic magnetometer which uses atoms as sensitive elements have ultra-high precision and has wide applications in scientific researches. The photoelastic modulation method based on photoelastic modulator (PEM) is used in the atomic magnetometer to detect the small optical rotation angle of a linearly polarized light. However, the modulation amplitude of the PEM will drift due to the environmental factors, which reduces the precision and long-term stability of the atomic magnetometer. Consequently, stabilizing the PEM's modulation amplitude is essential to precision measurement. In this paper, a modulation amplitude stabilization method for PEM based on Field Programmable Gate Array (FPGA) is proposed. The designed control system contains an optical setup and an electrical part. The optical setup is used to measure the PEM's modulation amplitude. The FPGA chip, with the PID control algorithm implemented in it, is used as the electrical part's micro controller. The closed loop control method based on the photoelastic modulation detection system can directly measure the PEM's modulation amplitude in real time, without increasing the additional optical devices. In addition, the operating speed of the modulation amplitude stabilization control system can be greatly improved because of the FPGA's parallel computing feature, and the PID control algorithm ensures flexibility to meet different needs of the PEM's modulation amplitude set values. The Modelsim simulation results show the correctness of the PID control algorithm, and the long-term stability of the PEM's modulation amplitude reaches 0.35% in a 3-hour continuous measurement.

  8. Design issues on using FPGA-based I and C systems in nuclear reactors

    Energy Technology Data Exchange (ETDEWEB)

    Farias, Marcos S.; Carvalho, Paulo Victor R. de; Santos, Isaac Jose A.L. dos; Lacerda, Fabio de, E-mail: msantana@ien.gov.br, E-mail: paulov@ien.gov.br, E-mail: luquetti@ien.gov.br, E-mail: acerda@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Div. de Engenharia Nuclear

    2015-07-01

    The FPGA (field programmable gate array) is widely used in various fields of industry. FPGAs can be used to perform functions that are safety critical and require high reliability, like in automobiles, aircraft control and assistance and mission-critical applications in the aerospace industry. With these merits, FPGAs are receiving increased attention worldwide for application in nuclear plant instrumentation and control (I and C) systems, mainly for Reactor Protection System (RPS). Reasons for this include the fact that conventional analog electronics technologies are become obsolete. I and C systems of new Reactors have been designed to adopt the digital equipment such as PLC (Programmable Logic Controller) and DCS (Distributed Control System). But microprocessors-based systems may not be simply qualified because of its complex characteristics. For example, microprocessor cores execute one instruction at a time, and an operating system is needed to manage the execution of programs. In turn, FPGAs can run without an operating system and the design architecture is inherently parallel. In this paper we aim to assess these and other advantages, and the limitations, on FPGA-based solutions, considering the design guidelines and regulations on the use of FPGAs in Nuclear Plant I and C Systems. We will also examine some circuit design techniques in FPGA to help mitigate failures and provide redundancy. The objective is to show how FPGA-based systems can provide cost-effective options for I and C systems in modernization projects and to the RMB (Brazilian Multipurpose Reactor), ensuring safe and reliable operation, meeting licensing requirements, such as separation, redundancy and diversity. (author)

  9. Research on acceleration method of reactor physics based on FPGA platforms

    International Nuclear Information System (INIS)

    Li, C.; Yu, G.; Wang, K.

    2013-01-01

    The physical designs of the new concept reactors which have complex structure, various materials and neutronic energy spectrum, have greatly improved the requirements to the calculation methods and the corresponding computing hardware. Along with the widely used parallel algorithm, heterogeneous platforms architecture has been introduced into numerical computations in reactor physics. Because of the natural parallel characteristics, the CPU-FPGA architecture is often used to accelerate numerical computation. This paper studies the application and features of this kind of heterogeneous platforms used in numerical calculation of reactor physics through practical examples. After the designed neutron diffusion module based on CPU-FPGA architecture achieves a 11.2 speed up factor, it is proved to be feasible to apply this kind of heterogeneous platform into reactor physics. (authors)

  10. FPGA and optical-network-based LLRF distributed control system for TESLA-XFEL linear accelerator

    Science.gov (United States)

    Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Czarski, Tomasz; Giergusiewicz, Wojciech; Jalmuzna, Wojciech; Olowski, Krysztof; Perkuszewski, Karol; Zielinski, Jerzy; Simrock, Stefan

    2005-02-01

    The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control system for the TESLA-XFEL accelerator. The design of a system basing on the FPGA chips and multi-gigabit optical network was debated. The system design approach was fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of the, DSP enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. Initial parameters of the system model under the design are presented.

  11. FPGA based hardware optimized implementation of signal processing system for LFM pulsed radar

    Science.gov (United States)

    Azim, Noor ul; Jun, Wang

    2016-11-01

    Signal processing is one of the main parts of any radar system. Different signal processing algorithms are used to extract information about different parameters like range, speed, direction etc, of a target in the field of radar communication. This paper presents LFM (Linear Frequency Modulation) pulsed radar signal processing algorithms which are used to improve target detection, range resolution and to estimate the speed of a target. Firstly, these algorithms are simulated in MATLAB to verify the concept and theory. After the conceptual verification in MATLAB, the simulation is converted into implementation on hardware using Xilinx FPGA. Chosen FPGA is Xilinx Virtex-6 (XC6LVX75T). For hardware implementation pipeline optimization is adopted and also other factors are considered for resources optimization in the process of implementation. Focusing algorithms in this work for improving target detection, range resolution and speed estimation are hardware optimized fast convolution processing based pulse compression and pulse Doppler processing.

  12. A low power flash-FPGA based brain implant micro-system of PID control.

    Science.gov (United States)

    Lijuan Xia; Fattah, Nabeel; Soltan, Ahmed; Jackson, Andrew; Chester, Graeme; Degenaar, Patrick

    2017-07-01

    In this paper, we demonstrate that a low power flash FPGA based micro-system can provide a low power programmable interface for closed-loop brain implant inter- faces. The proposed micro-system receives recording local field potential (LFP) signals from an implanted probe, performs closed-loop control using a first order control system, then converts the signal into an optogenetic control stimulus pattern. Stimulus can be implemented through optoelectronic probes. The long term target is for both fundamental neuroscience applications and for clinical use in treating epilepsy. Utilizing our device, closed-loop processing consumes only 14nJ of power per PID cycle compared to 1.52μJ per cycle for a micro-controller implementation. Compared to an application specific digital integrated circuit, flash FPGA's are inherently programmable.

  13. FPGA implementation of a hybrid on-line process monitoring in PC based real-time systems

    Directory of Open Access Journals (Sweden)

    Jovanović Bojan

    2011-01-01

    Full Text Available This paper presents one way of FPGA implementation of hybrid (hardware-software based on-line process monitoring in Real-Time systems (RTS. The reasons for RTS monitoring are presented at the beginning. The summary of different RTS monitoring approaches along with its advantages and drawbacks are also exposed. Finally, monitoring module is described in details. Also, FPGA implementation results and some useful monitoring system applications are mentioned.

  14. Design of area array CCD image acquisition and display system based on FPGA

    Science.gov (United States)

    Li, Lei; Zhang, Ning; Li, Tianting; Pan, Yue; Dai, Yuming

    2014-09-01

    With the development of science and technology, CCD(Charge-coupled Device) has been widely applied in various fields and plays an important role in the modern sensing system, therefore researching a real-time image acquisition and display plan based on CCD device has great significance. This paper introduces an image data acquisition and display system of area array CCD based on FPGA. Several key technical challenges and problems of the system have also been analyzed and followed solutions put forward .The FPGA works as the core processing unit in the system that controls the integral time sequence .The ICX285AL area array CCD image sensor produced by SONY Corporation has been used in the system. The FPGA works to complete the driver of the area array CCD, then analog front end (AFE) processes the signal of the CCD image, including amplification, filtering, noise elimination, CDS correlation double sampling, etc. AD9945 produced by ADI Corporation to convert analog signal to digital signal. Developed Camera Link high-speed data transmission circuit, and completed the PC-end software design of the image acquisition, and realized the real-time display of images. The result through practical testing indicates that the system in the image acquisition and control is stable and reliable, and the indicators meet the actual project requirements.

  15. Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

    Directory of Open Access Journals (Sweden)

    Manuel Saldaña

    2012-01-01

    Full Text Available Partial reconfiguration (PR is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the system continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this paper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to allow hardware designers to create template bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused for multiple applications. As an example of the generality of this approach, four different applications that use the same template bitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired application engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines. PR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by some examples and preliminary PR overhead measurements.

  16. Multichannel FPGA based MVT system for high precision time (20 ps RMS) and charge measurement

    Science.gov (United States)

    Pałka, M.; Strzempek, P.; Korcyl, G.; Bednarski, T.; Niedźwiecki, Sz.; Białas, P.; Czerwiński, E.; Dulski, K.; Gajos, A.; Głowacz, B.; Gorgol, M.; Jasińska, B.; Kamińska, D.; Kajetanowicz, M.; Kowalski, P.; Kozik, T.; Krzemień, W.; Kubicz, E.; Mohhamed, M.; Raczyński, L.; Rudy, Z.; Rundel, O.; Salabura, P.; Sharma, N. G.; Silarski, M.; Smyrski, J.; Strzelecki, A.; Wieczorek, A.; Wiślicki, W.; Zieliński, M.; Zgardzińska, B.; Moskal, P.

    2017-08-01

    In this article it is presented an FPGA based Multi-Voltage Threshold (MVT) system which allows of sampling fast signals (1-2 ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time measurement of 20 ps RMS and reconstruct charge of signals, using a simple approach, with deviation from real value smaller than 10%. Utilization of the differential inputs of an FPGA chip as comparators together with an implementation of a TDC inside an FPGA allowed us to achieve a compact multi-channel system characterized by low power consumption and low production costs. This paper describes realization and functioning of the system comprising 192-channel TDC board and a four mezzanine cards which split incoming signals and discriminate them. The boards have been used to validate a newly developed Time-of-Flight Positron Emission Tomography system based on plastic scintillators. The achieved full system time resolution of σ(TOF) ≈ 68 ps is by factor of two better with respect to the current TOF-PET systems.

  17. A low-cost, FPGA-based servo controller with lock-in amplifier

    International Nuclear Information System (INIS)

    Yang, G; Barry, J F; Shuman, E S; Steinecker, M H; DeMille, D

    2012-01-01

    We describe the design and implementation of a low-cost, FPGA-based servo controller with an integrated waveform synthesizer and lock-in amplifier. This system has been designed with the specific application of laser frequency locking in mind but should be adaptable to a variety of other purposes as well. The system incorporates an onboard waveform synthesizer, a lock-in amplifier, two channels of proportional-integral (PI) servo control, and a ramp generator on a single FPGA chip. The system is based on an inexpensive, off-the-shelf FPGA evaluation board with a wide variety of available accessories, allowing the system to interface with standard laser controllers and detectors while minimizing the use of custom hardware and electronics. Gains, filter constants, and other relevant parameters are adjustable via onboard knobs and switches. These parameters and other information are displayed to the user via an integrated LCD, allowing full operation of the device without an accompanying computer. We demonstrate the performance of the system in a test setup, in which the frequency of a tunable external-cavity diode laser (ECDL) is locked to a resonant optical transmission peak of a Fabry-Perot cavity. In this setup, we achieve a total servo-loop bandwidth of ∼ 7 kHz and achieve locking of the ECDL to the cavity with a full-width-at-half-maximum (FWHM) linewidth of ∼ 200 kHz.

  18. Development of FPGA-based digital signal processing system for radiation spectroscopy

    International Nuclear Information System (INIS)

    Lee, Pil Soo; Lee, Chun Sik; Lee, Ju Hahn

    2013-01-01

    We have developed an FPGA-based digital signal processing system that performs both online digital signal filtering and pulse-shape analysis for both particle and gamma-ray spectroscopy. Such functionalities were made possible by a state-of-the-art programmable logic device and system architectures employed. The system performance as measured, for example, in the system dead time and accuracy for pulse-height and rise-time determination, was evaluated with standard alpha- and gamma-ray sources using a CsI(Tl) scintillation detector. It is resulted that the present system has shown its potential application to various radiation-related fields such as particle identification, radiography, and radiation imaging. - Highlights: ► An FPGA-based digital processing system was developed for radiation spectroscopy. ► Our digital system has a 14-bit resolution and a 100-MHz sampling rate. ► The FPGA implements the online digital filtering and pulse-shape analysis. ► The pileup rejection is implemented in trigger logic before digital filtering process. ► Our digital system was verified in alpha-gamma measurements using a CsI detector

  19. Three-dimensional design methodologies for tree-based FPGA architecture

    CERN Document Server

    Pangracious, Vinod; Mehrez, Habib

    2015-01-01

    This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

  20. Design and implementation of STD32-BUS based reactor protection trip unit on FPGA imbaby

    International Nuclear Information System (INIS)

    Mahmoud, I.; Elnokity, O.A.; Refai, M.K.

    2007-01-01

    This paper presents a way to design and implement the Trip Unit of a Reactor Protection System (RPS) using a Field Programmable Gate Arrays (FPGA). Instead of the traditional embedded Microprocessor based interface design method, a proposed tailor made FPGA based circuit is built to substitute the Trip Unit (TL1) existing in Egypt's 2' ' Research reactor ETRR-2. The existing embedded system is built around the STD32 field Computer Bus which used in industrial and process control applications. It is modular, rugged, reliable, and easy-to-use and is able to support a large mix of I/O cards and to easily change its configuration in the future. Therefore, the state machine of this bus is extracted from its timing diagrams and implemented in VHDL to interface the designed TU circuit. The proposed designed circuit implemented using ALTERA EPF10K10LC84-3 chip replaces the Single Board Computer which have the embedded SAY program of the TU providing the same integrated HAV and SAV functions implemented in FPGA Chip housed in an printed circuit board, which uses the same shape and specifications of STD32 boards. H/W implementation of both TU and STD32 Bus in VHDL addresses the issues of safety and reusability

  1. Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

    Directory of Open Access Journals (Sweden)

    Paolo Meloni

    2012-01-01

    Full Text Available Application Specific Instruction-set Processors (ASIPs expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

  2. Real-time distortion correction for visual inspection systems based on FPGA

    Science.gov (United States)

    Liang, Danhua; Zhang, Zhaoxia; Chen, Xiaodong; Yu, Daoyin

    2008-03-01

    Visual inspection is a kind of new technology based on the research of computer vision, which focuses on the measurement of the object's geometry and location. It can be widely used in online measurement, and other real-time measurement process. Because of the defects of the traditional visual inspection, a new visual detection mode -all-digital intelligent acquisition and transmission is presented. The image processing, including filtering, image compression, binarization, edge detection and distortion correction, can be completed in the programmable devices -FPGA. As the wide-field angle lens is adopted in the system, the output images have serious distortion. Limited by the calculating speed of computer, software can only correct the distortion of static images but not the distortion of dynamic images. To reach the real-time need, we design a distortion correction system based on FPGA. The method of hardware distortion correction is that the spatial correction data are calculated first under software circumstance, then converted into the address of hardware storage and stored in the hardware look-up table, through which data can be read out to correct gray level. The major benefit using FPGA is that the same circuit can be used for other circularly symmetric wide-angle lenses without being modified.

  3. Input/output Buffer based Vedic Multiplier Design for Thermal Aware Energy Efficient Digital Signal Processing on 28nm FPGA

    DEFF Research Database (Denmark)

    Goswami, Kavita; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar

    2016-01-01

    Multiplier is used for multiplication of a signal and a constant in digital signal processing (DSP). 28nm technology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and XPower Analyzer. Vedic multiplier gain speed improvements by parallelizing the generation...... Programmable Gate Array (FPGA) in order to reduce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy...... efficient Vedic multiplier.There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7oC, 53.5oC, 40oC and 21oC respectively....

  4. FPGA-based Upgrade to RITS-6 Control System, Designed with EMP Considerations

    International Nuclear Information System (INIS)

    Anderson, Harold D.; Williams, John T.

    2009-01-01

    The existing control system for the RITS-6, a 20-MA 3-MV pulsed-power accelerator located at Sandia National Laboratories, was built as a system of analog switches because the operators needed to be close enough to the machine to hear pulsed-power breakdowns, yet the electromagnetic pulse (EMP) emitted would disable any processor-based solutions. The resulting system requires operators to activate and deactivate a series of 110-V relays manually in a complex order. The machine is sensitive to both the order of operation and the time taken between steps. A mistake in either case would cause a misfire and possible machine damage. Based on these constraints, a field-programmable gate array (FPGA) was chosen as the core of a proposed upgrade to the control system. An FPGA is a series of logic elements connected during programming. Based on their connections, the elements can mimic primitive logic elements, a process called synthesis. The circuit is static; all paths exist simultaneously and do not depend on a processor. This should make it less sensitive to EMP. By shielding it and using good electromagnetic interference-reduction practices, it should continue to operate well in the electrically noisy environment. The FPGA has two advantages over the existing system. In manual operation mode, the synthesized logic gates keep the operators in sequence. In addition, a clock signal and synthesized countdown circuit provides an automated sequence, with adjustable delays, for quickly executing the time-critical portions of charging and firing. The FPGA is modeled as a set of states, each state being a unique set of values for the output signals. The state is determined by the input signals, and in the automated segment by the value of the synthesized countdown timer, with the default mode placing the system in a safe configuration. Unlike a processor-based system, any system stimulus that results in an abort situation immediately executes a shutdown, with only a tens

  5. Fpga based L-band pulse doppler radar design and implementation

    Science.gov (United States)

    Savci, Kubilay

    As its name implies RADAR (Radio Detection and Ranging) is an electromagnetic sensor used for detection and locating targets from their return signals. Radar systems propagate electromagnetic energy, from the antenna which is in part intercepted by an object. Objects reradiate a portion of energy which is captured by the radar receiver. The received signal is then processed for information extraction. Radar systems are widely used for surveillance, air security, navigation, weather hazard detection, as well as remote sensing applications. In this work, an FPGA based L-band Pulse Doppler radar prototype, which is used for target detection, localization and velocity calculation has been built and a general-purpose Pulse Doppler radar processor has been developed. This radar is a ground based stationary monopulse radar, which transmits a short pulse with a certain pulse repetition frequency (PRF). Return signals from the target are processed and information about their location and velocity is extracted. Discrete components are used for the transmitter and receiver chain. The hardware solution is based on Xilinx Virtex-6 ML605 FPGA board, responsible for the control of the radar system and the digital signal processing of the received signal, which involves Constant False Alarm Rate (CFAR) detection and Pulse Doppler processing. The algorithm is implemented in MATLAB/SIMULINK using the Xilinx System Generator for DSP tool. The field programmable gate arrays (FPGA) implementation of the radar system provides the flexibility of changing parameters such as the PRF and pulse length therefore it can be used with different radar configurations as well. A VHDL design has been developed for 1Gbit Ethernet connection to transfer digitized return signal and detection results to PC. An A-Scope software has been developed with C# programming language to display time domain radar signals and detection results on PC. Data are processed both in FPGA chip and on PC. FPGA uses fixed

  6. Optical network and FPGA/DSP based control system for free electron laser

    International Nuclear Information System (INIS)

    Romaniuk, R.S.; Pozniak, K.T.; Czarski, T.; Czuba, K.; Giergusiewicz, W.; Kasprowicz, G.; Koprek, W.

    2005-01-01

    The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to

  7. Central FPGA-based destination and load control in the LHCb MHz event readout

    Science.gov (United States)

    Jacobsson, R.

    2012-10-01

    The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

  8. Central FPGA-based destination and load control in the LHCb MHz event readout

    International Nuclear Information System (INIS)

    Jacobsson, R.

    2012-01-01

    The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

  9. FPGA-based implementation of a cavity field controller for FLASH and X-FEL

    Science.gov (United States)

    Fafara, Przemyslaw; Jalmuzna, Wojciech; Koprek, Waldemar; Pozniak, Krzysztof; Romaniuk, Ryszard; Szewinski, Jaroslaw; Cichalewski, Wojciech

    2007-08-01

    The subject of this paper is the design and construction of a new generation of superconducting cavity accelerator measurement and control system. The old system is based on a single digital signal processor (DSP). The new system uses a large programmable array circuit (FPGA) instead, with a multi-gigabit optical link. Both systems now work in parallel in the Free Electron Laser in Hamburg (FLASH). The differences between the systems are shown, based on the measurement results of the working machine. The major advantage of the new system is a bigger area of stability of the machine control loop.

  10. Research and Implementation of Automatic Fuzzy Garage Parking System Based on FPGA

    OpenAIRE

    Wang Kaiyu; Yu Zongmin; Guan Sanghai; Yang Xing; Sheng Menglin; Tang Zhenan

    2016-01-01

    Because of many common scenes of reverse parking in real life, this paper presents a fuzzy controller which accommodates front and back adjustment of vehicle’s body attitude, and based on chaotic-genetic arithmetic to optimize the membership function of this controller, and get a vertical parking fuzzy controller whose simulation result is good .The paper makes the hardware-software embedded design for system based on Field-Programmable Gate Array (FPGA), and set up a 1:10 verification platfo...

  11. Research and Implementation of Automatic Fuzzy Garage Parking System Based on FPGA

    Directory of Open Access Journals (Sweden)

    Wang Kaiyu

    2016-01-01

    Full Text Available Because of many common scenes of reverse parking in real life, this paper presents a fuzzy controller which accommodates front and back adjustment of vehicle’s body attitude, and based on chaotic-genetic arithmetic to optimize the membership function of this controller, and get a vertical parking fuzzy controller whose simulation result is good .The paper makes the hardware-software embedded design for system based on Field-Programmable Gate Array (FPGA, and set up a 1:10 verification platform of smart car to verify the fuzzy garage parking system with real car. Verification results show that, the system can complete the parking task very well.

  12. DOOCS environment for FPGA-based cavity control system and control algorithms development

    International Nuclear Information System (INIS)

    Pucyk, P.; Koprek, W.; Kaleta, P.; Szewinski, J.; Pozniak, K.T.; Czarski, T.; Romaniuk, R.S.

    2005-01-01

    The paper describes the concept and realization of the DOOCS control software for FPGAbased TESLA cavity controller and simulator (SIMCON). It bases on universal software components, created for laboratory purposes and used in MATLAB based control environment. These modules have been recently adapted to the DOOCS environment to ensure a unified software to hardware communication model. The presented solution can be also used as a general platform for control algorithms development. The proposed interfaces between MATLAB and DOOCS modules allow to check the developed algorithm in the operation environment before implementation in the FPGA. As the examples two systems have been presented. (orig.)

  13. Embedded 3D Graphics Core for FPGA-based System-on-Chip Applications

    DEFF Research Database (Denmark)

    Holten-Lund, Hans Erik

    2005-01-01

    This paper presents a 3D graphics accelerator core for an FPGA based system, and illustrates how to build a System-on-Chip containing a Xilinx MicroBlaze soft-core CPU and our 3D graphics accelerator core. The system is capable of running uClinux and hardware accelerated 3D graphics applications......, and the video display which periodically reads from memory to display the final rendered graphics. The graphics core uses internal scratch-pad memory to reduce its external bandwidth requirement, this is achieved by implementing a tile-based rendering algorithm. Reduced external bandwidth means that the power...

  14. Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

    International Nuclear Information System (INIS)

    Abbas, Syed Haider; Lee, Jung-Ryul; Jang, Jae-Kyeong; Kim, Zaeill

    2016-01-01

    Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

  15. Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

    Energy Technology Data Exchange (ETDEWEB)

    Abbas, Syed Haider; Lee, Jung-Ryul [Department of Aerospace Engineering, Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); Jang, Jae-Kyeong [The Engineering Institute-Korea, Chonbuk National University, Jeonju (Korea, Republic of); Kim, Zaeill [The 4th R& D Institute-1st directorate, Agency for Defense Development, Daejeon (Korea, Republic of)

    2016-07-15

    Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

  16. FPGA-based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    Science.gov (United States)

    Perkuszewski, Karol; Pozniak, Krzysztof T.; Jalmuzna, Wojciech; Koprek, Waldemar; Szewinski, Jaroslaw; Romaniuk, Ryszard S.; Simrock, Stefan

    2006-10-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented.

  17. FPGA based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    International Nuclear Information System (INIS)

    Perkuszewski, K.; Pozniak, K.T.; Jalmuzna, W.; Koprek, W.; Szewinski, J.; Romaniuk, R.S.

    2006-01-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented. (orig.)

  18. FPGA based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    Energy Technology Data Exchange (ETDEWEB)

    Perkuszewski, K.; Pozniak, K.T.; Jalmuzna, W.; Koprek, W.; Szewinski, J.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems; Simrock, S. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany)

    2006-07-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented. (orig.)

  19. Design and implementation of FPGA-based phase modulation ...

    Indian Academy of Sciences (India)

    Section 3 deals with the implementation process of the digital con- .... To aid the analysis of the SRC, a simulation model based on the state-space technique is ... compensator designed using 'SISO' tool in Matlab, is a PI compensator which ...

  20. FPGA Implementation for GMM-Based Speaker Identification

    Directory of Open Access Journals (Sweden)

    Phaklen EhKan

    2011-01-01

    Full Text Available In today's society, highly accurate personal identification systems are required. Passwords or pin numbers can be forgotten or forged and are no longer considered to offer a high level of security. The use of biological features, biometrics, is becoming widely accepted as the next level for security systems. Biometric-based speaker identification is a method of identifying persons from their voice. Speaker-specific characteristics exist in speech signals due to different speakers having different resonances of the vocal tract. These differences can be exploited by extracting feature vectors such as Mel-Frequency Cepstral Coefficients (MFCCs from the speech signal. A well-known statistical modelling process, the Gaussian Mixture Model (GMM, then models the distribution of each speaker's MFCCs in a multidimensional acoustic space. The GMM-based speaker identification system has features that make it promising for hardware acceleration. This paper describes the hardware implementation for classification of a text-independent GMM-based speaker identification system. The aim was to produce a system that can perform simultaneous identification of large numbers of voice streams in real time. This has important potential applications in security and in automated call centre applications. A speedup factor of ninety was achieved compared to a software implementation on a standard PC.

  1. Real-time particle image velocimetry based on FPGA technology;Velocimetria PIV en tiempo real basada en logica programable FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Iriarte Munoz, Jose Miguel [Universidad Nacional de Cuyo, Instituto Balseiro, Centro Atomico Bariloche (Argentina)

    2008-07-01

    Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach.;La velocimetria por imagenes de particulas (PIV), basada en plano laser, es una potente herramienta de medicion en dinamica de fluidos, capaz de medir sin grandes errores, un campo de velocidades distribuido en liquidos, gases y flujo multifase.Los altos requerimientos computacionales de los algoritmos PIV dificultan su empleo en tiempo-real.En este trabajo presentamos el diseno de una plataforma basada en tecnologia FPGA para capturar video y procesar en tiempo real el algoritmo de correlacion cruzada bidimensional.Mostramos resultados de un primer abordaje de la captura de imagenes y procesamiento de un campo fisico de velocidades en tiempo real.

  2. FPGA Based Intelligent Co-operative Processor in Memory Architecture

    DEFF Research Database (Denmark)

    Ahmed, Zaki; Sotudeh, Reza; Hussain, Dil Muhammad Akbar

    2011-01-01

    benefits of PIM, a concept of Co-operative Intelligent Memory (CIM) was developed by the intelligent system group of University of Hertfordshire, based on the previously developed Co-operative Pseudo Intelligent Memory (CPIM). This paper provides an overview on previous works (CPIM, CIM) and realization......In a continuing effort to improve computer system performance, Processor-In-Memory (PIM) architecture has emerged as an alternative solution. PIM architecture incorporates computational units and control logic directly on the memory to provide immediate access to the data. To exploit the potential...

  3. A radiation-hardened SOI-based FPGA

    International Nuclear Information System (INIS)

    Han Xiaowei; Wu Lihua; Zhao Yan; Li Yan; Zhang Qianli; Chen Liang; Zhang Guoquan; Li Jianzhong; Yang Bo; Gao Jiantou; Wang Jian; Li Ming; Liu Guizhai; Zhang Feng; Guo Xufeng; Chen, Stanley L.; Liu Zhongli; Yu Fang; Zhao Kai

    2011-01-01

    A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 x 10 11 rad(Si)/s and a neutron fluence immunity of 1 x 10 14 n/cm 2 . (semiconductor integrated circuits)

  4. FPGA Accelerator for Wavelet-Based Automated Global Image Registration

    Directory of Open Access Journals (Sweden)

    Baofeng Li

    2009-01-01

    Full Text Available Wavelet-based automated global image registration (WAGIR is fundamental for most remote sensing image processing algorithms and extremely computation-intensive. With more and more algorithms migrating from ground computing to onboard computing, an efficient dedicated architecture of WAGIR is desired. In this paper, a BWAGIR architecture is proposed based on a block resampling scheme. BWAGIR achieves a significant performance by pipelining computational logics, parallelizing the resampling process and the calculation of correlation coefficient and parallel memory access. A proof-of-concept implementation with 1 BWAGIR processing unit of the architecture performs at least 7.4X faster than the CL cluster system with 1 node, and at least 3.4X than the MPM massively parallel machine with 1 node. Further speedup can be achieved by parallelizing multiple BWAGIR units. The architecture with 5 units achieves a speedup of about 3X against the CL with 16 nodes and a comparative speed with the MPM with 30 nodes. More importantly, the BWAGIR architecture can be deployed onboard economically.

  5. FPGA Accelerator for Wavelet-Based Automated Global Image Registration

    Directory of Open Access Journals (Sweden)

    Li Baofeng

    2009-01-01

    Full Text Available Abstract Wavelet-based automated global image registration (WAGIR is fundamental for most remote sensing image processing algorithms and extremely computation-intensive. With more and more algorithms migrating from ground computing to onboard computing, an efficient dedicated architecture of WAGIR is desired. In this paper, a BWAGIR architecture is proposed based on a block resampling scheme. BWAGIR achieves a significant performance by pipelining computational logics, parallelizing the resampling process and the calculation of correlation coefficient and parallel memory access. A proof-of-concept implementation with 1 BWAGIR processing unit of the architecture performs at least 7.4X faster than the CL cluster system with 1 node, and at least 3.4X than the MPM massively parallel machine with 1 node. Further speedup can be achieved by parallelizing multiple BWAGIR units. The architecture with 5 units achieves a speedup of about 3X against the CL with 16 nodes and a comparative speed with the MPM with 30 nodes. More importantly, the BWAGIR architecture can be deployed onboard economically.

  6. High speed FPGA-based Phasemeter for the far-infrared laser interferometers on EAST

    Science.gov (United States)

    Yao, Y.; Liu, H.; Zou, Z.; Li, W.; Lian, H.; Jie, Y.

    2017-12-01

    The far-infrared laser-based HCN interferometer and POlarimeter/INTerferometer\\break (POINT) system are important diagnostics for plasma density measurement on EAST tokamak. Both HCN and POINT provide high spatial and temporal resolution of electron density measurement and used for plasma density feedback control. The density is calculated by measuring the real-time phase difference between the reference beams and the probe beams. For long-pulse operations on EAST, the calculation of density has to meet the requirements of Real-Time and high precision. In this paper, a Phasemeter for far-infrared laser-based interferometers will be introduced. The FPGA-based Phasemeter leverages fast ADCs to obtain the three-frequency signals from VDI planar-diode Mixers, and realizes digital filters and an FFT algorithm in FPGA to provide real-time, high precision electron density output. Implementation of the Phasemeter will be helpful for the future plasma real-time feedback control in long-pulse discharge.

  7. Evaluation of radiation tolerance of TMR designs in SRAM-based FPGA.

    CERN Document Server

    Shibin, Konstantin

    2016-01-01

    During the Summer Student program in CERN I was working in the CMS Muon Drift Tube group, building a setup for evaluating the radiation tolerance of the drift tube signal encoding hardware (Time-to-Digital Converter, TDC) implemented in SRAM-based FPGA using Triple Modular Redundancy (TMR). While commercially available SRAM-based FPGAs have more computational power, are more advanced in general than flash-based FPGAs and are the most suitable technology for implementing the TDC logic (also taking into account the performance requirements), in the context of operation inside an environment with high levels of ionizing radiation (such as inside CMS DT detector) they are more susceptible to configuration memory bit flips – Single Event Upsets (SEUs) - due to lower required energy for a memory bit being flipped. The effect of a SEU inside the configuration memory might change the functionality of the underlying building blocks of FPGA and if the respective blocks were involved in implementing the desired custom...

  8. Design of a system based on DSP and FPGA for video recording and replaying

    Science.gov (United States)

    Kang, Yan; Wang, Heng

    2013-08-01

    This paper brings forward a video recording and replaying system with the architecture of Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The system achieved encoding, recording, decoding and replaying of Video Graphics Array (VGA) signals which are displayed on a monitor during airplanes and ships' navigating. In the architecture, the DSP is a main processor which is used for a large amount of complicated calculation during digital signal processing. The FPGA is a coprocessor for preprocessing video signals and implementing logic control in the system. In the hardware design of the system, Peripheral Device Transfer (PDT) function of the External Memory Interface (EMIF) is utilized to implement seamless interface among the DSP, the synchronous dynamic RAM (SDRAM) and the First-In-First-Out (FIFO) in the system. This transfer mode can avoid the bottle-neck of the data transfer and simplify the circuit between the DSP and its peripheral chips. The DSP's EMIF and two level matching chips are used to implement Advanced Technology Attachment (ATA) protocol on physical layer of the interface of an Integrated Drive Electronics (IDE) Hard Disk (HD), which has a high speed in data access and does not rely on a computer. Main functions of the logic on the FPGA are described and the screenshots of the behavioral simulation are provided in this paper. In the design of program on the DSP, Enhanced Direct Memory Access (EDMA) channels are used to transfer data between the FIFO and the SDRAM to exert the CPU's high performance on computing without intervention by the CPU and save its time spending. JPEG2000 is implemented to obtain high fidelity in video recording and replaying. Ways and means of acquiring high performance for code are briefly present. The ability of data processing of the system is desirable. And smoothness of the replayed video is acceptable. By right of its design flexibility and reliable operation, the system based on DSP and FPGA

  9. FPGA design

    CERN Document Server

    Simpson, Philip

    2010-01-01

    This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

  10. FPGA-based real-time simulation of power converters of renewable energy sources

    Energy Technology Data Exchange (ETDEWEB)

    Kokenyesi, Tamas; Varjasi, Istvan [Budapest University of Technology and Economics, Department of Automation and Applied Informatics (Hungary)], e-mail: kokenyesi.tamas@gmail.com, email: varjasi@aut.bme.hu

    2011-07-01

    This paper presents a hardware-in-the-loop testing (HIL) approach based on a field programmable gate array (FPGA) real-time simulation with real measured signals designed to reduce the cost and time for testing the main circuit of a power converter significantly. This method allows the control unit to measure its outputs on the same signal level in a completely transparent way, unlike other computer based simulation methods. As an example, a simulator for a three-phase inverter used for DC/AC conversion or frequency control is described and the simulated network illustrated. The calculation procedure and relative equations are also detailed, with simulation parameters and some measurement results being presented. It was found that the main advantage of this method is speed, which was only limited by the actual capabilities of the FPGA used. This method can be applied to a wide variety of analog circuits, reducing time to market. More complex circuits and higher frequencies could be simulated in the future with the evolution of FPGAs.

  11. An Update on ConSys Including a New LabVIEW FPGA Based LLRF System

    DEFF Research Database (Denmark)

    Worm, Torben; Nielsen, Jørgen S.

    . This system use a National Instruments NI-PCIe7852R DAQ card, which includes an on-board FPGA and are hosted in a standard PC. The fast (50 kHz) amplitude loop has been implemented on the FPGA, whereas the slower tuning and phase loops are implemented in the real-time system. An operator interface including......ConSys, the Windows based control system for ASTRID and ASTRID2, is now a mature system, having been in operation for more than 15 years. All the standard programs (Console, plots, data logging, control setting store/restore etc.) are fully general and are configured through a database or file. Con......Sys is a standard publisher/subscriber system, where all nodes can act both as client and server. One very strong feature is the easy ability to make virtual devices (devices which do not depend on hardware directly, but combine hardware parameters.) For ASTRID2 a new LabVIEW based Low-Level RF system has been made...

  12. Study of FPGA and GPU based pixel calibration for ATLAS IBL

    CERN Document Server

    Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Grosse-Knetter, J; Krieger, N; Kugel, A; Polini, A; Schroer, N

    2010-01-01

    The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASIC and simplified control. For calibration defined charges are applied to all pixels and the resulting time-over-threshold values are evaluated. In the present system multiple sets of two custom VME cards which employ a combination of FPGA and DSP technology are used for I/O interfacing, formatting and processing. The execution time of 51s to perform a threshold scan on a FE-I3 module of 46080 pixel is composed of 8s control, 29s transfer, 7.5s histogramming and 7s analysis. Extrapolating to FE-I4 the times per module of 53760 pixels are 12ms, 5.8s, 9.4s and 8.3s, a total of 23.5s. We present a proposal for a novel approach to the dominant tasks for FE-I4: histogramming and ananlysis. An FPGA-based histogramming uni...

  13. Development of FPGA-based High Speed Serial Links for High Energy Physics Experiments

    CERN Document Server

    Perrella, Sabrina; Giordano, Raffaele; Izzo, Vincenzo

    Ricerca Simple Search Advanced Search Ultime accessioni Browse Browse by Author Browse by Subject Browse by Year Browse by Type Browse by Accessibilità del full-text Informazioni Policy About FAQ Contatti Perrella, Sabrina (2016) Development of FPGA-based High-Speed serial links for High Energy Physics Experiments. [Tesi di dottorato] [img] Text Perrella_Sabrina_28.pdf Download (59MB) | Preview [error in script] [error in script] Item Type: Tesi di dottorato Lingua: English Title: Development of FPGA-based High-Speed serial links for High Energy Physics Experiments Creators: Creators\tEmail Perrella, Sabrina\tsa.perrella@gmail.com Date: 31 March 2016 Number of Pages: 113 Institution: Università degli Studi di Napoli Federico II Department: Fisica Scuola di dottorato: Scienze fisiche Dottorato: Fisica fondamentale ed applicata Ciclo di dottorato: 28 Coordinatore del Corso di dottorato: nome\temail Velotta, Raffaele\tvelotta@na.infn.it Tutor: nome\temail Alviggi, Mariagrazia\tUNSPECIFIED Giordano, ...

  14. Multichannel FPGA-Based Data-Acquisition-System for Time-Resolved Synchrotron Radiation Experiments

    Science.gov (United States)

    Choe, Hyeokmin; Gorfman, Semen; Heidbrink, Stefan; Pietsch, Ullrich; Vogt, Marco; Winter, Jens; Ziolkowski, Michael

    2017-06-01

    The aim of this contribution is to describe our recent development of a novel compact field-programmable gatearray (FPGA)-based data acquisition (DAQ) system for use with multichannel X-ray detectors at synchrotron radiation facilities. The system is designed for time resolved counting of single photons arriving from several-currently 12-independent detector channels simultaneously. Detector signals of at least 2.8 ns duration are latched by asynchronous logic and then synchronized with the system clock of 100 MHz. The incoming signals are subsequently sorted out into 10 000 time-bins where they are counted. This occurs according to the arrival time of photons with respect to the trigger signal. Repeatable mode of triggered operation is used to achieve high statistic of accumulated counts. The time-bin width is adjustable from 10 ns to 1 ms. In addition, a special mode of operation with 2 ns time resolution is provided for two detector channels. The system is implemented in a pocketsize FPGA-based hardware of 10 cm × 10 cm × 3 cm and thus can easily be transported between synchrotron radiation facilities. For setup of operation and data read-out, the hardware is connected via USB interface to a portable control computer. DAQ applications are provided in both LabVIEW and MATLAB environments.

  15. VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

    Directory of Open Access Journals (Sweden)

    Esteban Tlelo-Cuautle

    Full Text Available Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL. In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

  16. VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

    Science.gov (United States)

    Tlelo-Cuautle, Esteban; Quintas-Valles, Antonio de Jesus; de la Fraga, Luis Gerardo; Rangel-Magdaleno, Jose de Jesus

    2016-01-01

    Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

  17. DNA Processing and Reassembly on General Purpose FPGA-based Development Boards

    Directory of Open Access Journals (Sweden)

    SZÁSZ Csaba

    2017-05-01

    Full Text Available The great majority of researchers involved in microelectronics generally agree that many scientific challenges in life sciences have associated with them a powerful computational requirement that must be solved before scientific progress can be made. The current trend in Deoxyribonucleic Acid (DNA computing technologies is to develop special hardware platforms capable to provide the needed processing performance at lower cost. In this endeavor the FPGA-based (Field Programmable Gate Arrays configurations aimed to accelerate genome sequencing and reassembly plays a leading role. This paper emphasizes benefits and advantages using general purpose FPGA-based development boards in DNA reassembly applications beside the special hardware architecture solutions. An original approach is unfolded which outlines the versatility of high performance ready-to-use manufacturer development platforms endowed with powerful hardware resources fully optimized for high speed processing applications. The theoretical arguments are supported via an intuitive implementation example where the designer it is discharged from any hardware development effort and completely assisted in exclusive concentration only on software design issues providing greatly reduced application development cycles. The experiments prove that such boards available on the market are suitable to fulfill in all a wide range of DNA sequencing and reassembly applications.

  18. Online data reduction with FPGA-based track reconstruction for the Belle II DEPFET pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Deschamps, Bruno; Wessel, Christian; Marinas, Carlos; Dingfelder, Jochen [Physikalisches Institut, Universitaet Bonn (Germany)

    2016-07-01

    The innermost two layers of the Belle II vertex detector at the KEK facility in Tsukuba, Japan, will be covered by high-granularity DEPFET pixel sensors (PXD). The large number of pixels leads to a maximum data rate of 256 Gbps, which has to be significantly reduced by the Data Acquisition System (DATCON). For the data reduction the hit information of the surrounding Silicon strip Vertex Detector (SVD) is utilized to define so-called Regions of Interest (ROI). Only hit information of the pixels located inside these ROIs are saved. The ROIs for the PXD are computed by reconstructing track segments from SVD data and extrapolation to the PXD. The goal is to achieve a data reduction of at least a factor of 10 with this ROI selection. All the necessary processing stages, the receiving, decoding and multiplexing of SVD data on 48 optical fibers, the track reconstruction and the definition of the ROIs, will be performed by the presented system. The planned hardware design is based on a distributed set of Advanced Mezzanine Cards (AMC) each equipped with a Field Programmable Gate Array (FPGA) and 4 optical transceivers. In this talk, the status and plans for the DATCON prototype and the FPGA-based tracking algorithm are introduced as well as the plans for their test in the upcoming test beam at DESY.

  19. An FPGA-based sampling-ADC readout for the crystal barrel calorimeter

    Energy Technology Data Exchange (ETDEWEB)

    Muellers, Johannes [Helmholtz-Institut fuer Strahlen- und Kernphysik, Bonn (Germany); Marciniewski, Pawel [Angstroemlaboratoriet, Uppsala (Sweden); Collaboration: CBELSA/TAPS-Collaboration

    2015-07-01

    The CBELSA/TAPS experiment at the electron accelerator ELSA (Bonn) investigates the photoproduction of mesons off protons and neutrons. Presently the readout of the CsI(Tl)-crystals of the Crystal Barrel calorimeter is being upgraded from a PIN-diode readout to an APD readout to create a fast signal for first-level-triggering. This will increase the trigger efficiency especially for final states with only neutral particles substantially. To increase the possible data readout rate, which is currently limited by the digitization stage (LeCroy QDC 1885F) to ∼ 2 kHz, the implementation of a new Sampling-ADC (SADC) readout is being prepared. Based on the 64-channel PANDA-SADC, the CB-SADC design was modified and adapted to the needs of the CBELSA/TAPS experiment. It offers 64 channels in one NIM module, together with modular analog or FPGA-based digital shaping. The data transfer will be realized by two standard gigabit links. Using an FPGA together with SADCs provides a multitude of possibilities for online feature extraction, such as the determination of the energy deposited in the crystal, TDC capabilities and pile-up detection and recovery.

  20. DSP+FPGA-based real-time histogram equalization system of infrared image

    Science.gov (United States)

    Gu, Dongsheng; Yang, Nansheng; Pi, Defu; Hua, Min; Shen, Xiaoyan; Zhang, Ruolan

    2001-10-01

    Histogram Modification is a simple but effective method to enhance an infrared image. There are several methods to equalize an infrared image's histogram due to the different characteristics of the different infrared images, such as the traditional HE (Histogram Equalization) method, and the improved HP (Histogram Projection) and PE (Plateau Equalization) method and so on. If to realize these methods in a single system, the system must have a mass of memory and extremely fast speed. In our system, we introduce a DSP + FPGA based real-time procession technology to do these things together. FPGA is used to realize the common part of these methods while DSP is to do the different part. The choice of methods and the parameter can be input by a keyboard or a computer. By this means, the function of the system is powerful while it is easy to operate and maintain. In this article, we give out the diagram of the system and the soft flow chart of the methods. And at the end of it, we give out the infrared image and its histogram before and after the process of HE method.

  1. FPGA based, DSP board for LLRF 8-Channel SIMCON 3.0 Part I: Hardware

    Science.gov (United States)

    Giergusiewicz, Wojciech; Koprek, Waldemar; Jalmuzna, Wojciech; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.

    2005-09-01

    The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the VUV-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layers, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACC1 module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0 encouraged us to enter the design of SIMCON 3.1 possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0 is a modular solution, while SIMCON 3.1 will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one, after branching off in this version of the SIMCON, will be continued.

  2. Overview and future developments of the FPGA-based DAQ of COMPASS

    Energy Technology Data Exchange (ETDEWEB)

    Bai, Yunpeng; Huber, Stefan; Konorov, Igor; Levit, Dmytro [Physik-Department E18, Technische Universitaet Muenchen (Germany); Bodlak, Martin [Department of Low-Temperature Physics, Charles University Prague (Czech Republic); Frolov, Vladimir [European Organization for Nuclear Research - CERN (Switzerland); Jary, Vladimir; Virius, Miroslav [Faculty of Nuclear Sciences and Physical Engineering, Czech Technical University (Czech Republic); Novy, Josef [European Organization for Nuclear Research - CERN (Switzerland); Faculty of Nuclear Sciences and Physical Engineering, Czech Technical University (Czech Republic); Steffen, Dominik [Physik-Department E18, Technische Universitaet Muenchen (Germany); European Organization for Nuclear Research - CERN (Switzerland)

    2016-07-01

    COMPASS is a fixed-target experiment at the SPS accelerator at CERN dedicated to the study of hadron structure and spectroscopy. In 2014, an FPGA-based data acquisition system (FDAQ) was deployed. Its hardware event builder consisting of nine custom designed FPGA-cards replaced 30 distributed online computers and around 100 PCI cards. As a result, the new DAQ provides higher bandwidth and better reliability. By buffering the data, the system exploits the spill structure of the SPS averaging the maximum on-spill data rate of 1.5 GB/s over the whole SPS duty cycle. A modern run control software allows user-friendly monitoring and configuration of the hardware nodes of the event builder. From 2016, it is planned to wire all point-to-point high-speed links via a fully programmable crosspoint switch. The crosspoint switch will provide a fully customizable DAQ network topology between front-end electronics, the event building hardware, and the readout computers. It will therefore simplify compensation for hardware failure and improve load balancing.

  3. Implementation of FPGA-based Level-1 Tracking at CMS for the HL-LHC

    CERN Document Server

    Chaves, Jorge Enrique

    2014-01-01

    A new approach for track reconstruction is presented to be used in the all-hardware first level of the CMS trigger. The application of the approach is intended for the upgraded all-silicon tracker, which is to be installed for the High Luminosity era of the LHC (HL-LHC). The upgraded LHC machine is expected to deliver a luminosity on the order of $5\\times10^{34} $cm$^{-2}$s$^{-1}$. This expected luminosity means there would be about 125 pileup events in each bunch crossing at a frequency of 40 MHz. To keep the CMS trigger rate at a manageable level under these conditions, it is necessary to make quick decisions on the events that will be processed. The timing estimates for the algorithm are expected to be below 5 $\\mu$s, well within the requirements of the L1 trigger at CMS for track identification. The algorithm is integer-based, allowing it to be implemented on an FPGA. Currently we are working on a demonstrator hardware implementation using a Xilinx Virtex 6 FPGA. Results from simulations in C++ and Verilo...

  4. Generic FPGA-Based Platform for Distributed IO in Proton Therapy Patient Safety Interlock System

    Science.gov (United States)

    Eichin, Michael; Carmona, Pablo Fernandez; Johansen, Ernst; Grossmann, Martin; Mayor, Alexandre; Erhardt, Daniel; Gomperts, Alexander; Regele, Harald; Bula, Christian; Sidler, Christof

    2017-06-01

    At the Paul Scherrer Institute (PSI) in Switzerland, cancer patients are treated with protons. Proton therapy at PSI has a long history and started in the 1980s. More than 30 years later, a new gantry has recently been installed in the existing facility. This new machine has been delivered by an industry partner. A big challenge is the integration of the vendor's safety system into the existing PSI environment. Different interface standards and the complexity of the system made it necessary to find a technical solution connecting an industry system to the existing PSI infrastructure. A novel very flexible distributed IO system based on field-programmable gate array (FPGA) technology was developed, supporting many different IO interface standards and high-speed communication links connecting the device to a PSI standard versa module eurocard-bus input output controller. This paper summarizes the features of the hardware technology, the FPGA framework with its high-speed communication link protocol, and presents our first measurement results.

  5. Hamming Weight Counters and Comparators based on Embedded DSP Blocks for Implementation in FPGA

    Directory of Open Access Journals (Sweden)

    SKLYAROV, V.

    2014-05-01

    Full Text Available This paper is dedicated to the design, implementation and evaluation of fast FPGA-based circuits that compute Hamming weights for binary vectors and compare the results with fixed thresholds and variable bounds. It is shown that digital signal processing (DSP slices that are widely available in contemporary FPGAs may be used efficiently and they frequently provide the fastest and least resource consuming solutions. A thorough analysis and comparison of these with the best known alternatives both in hardware and in software is presented. The results are supported by numerous experiments in recent prototyping boards. A fully synthesizable hardware description language (VHDL specification for one of the proposed core components is given that is ready to be synthesized, implemented, tested and compared in any FPGA that contains embedded DSP48E1 slices (or alternatively DSP48A1 slices from previous generations. Finally, the results of comparisons are provided that include discussions of designs in an ARM processor combined with reconfigurable logic for very long vectors.

  6. FPGA-based real time implementation of MPPT-controller for photovoltaic systems

    Energy Technology Data Exchange (ETDEWEB)

    Mellit, A.; Rezzouk, H.; Medjahed, B. [Faculty of Sciences and Technology, Jijel University, Ouled-aissa, P.O. Box 98, Jijel 18000 (Algeria); Messai, A. [CRNB Ain Oussera, P.O. Box 180, 17200 Djelfa (Algeria)

    2011-05-15

    In this paper an FPGA-based implementation of a real time perturb and observe (P and O) algorithm for tracking the Maximum Power Point (MPP) of a photovoltaic (PV) generator is presented. The P and O algorithm has been designed using the very high-speed description language (VHDL) and implemented on Xilinx Virtex-II-Pro(xc2v1000-4fg456) - Field Programmable Gate Array (FPGA). The algorithm and the hardware have been simulated and tested by conditioning the power produced by the PV-modules installed on the rooftop of the ''Hall of Technology Laboratory'' at Jijel University. The main advantages of the developed MPPT are low cost, good velocity, acceptable reliability, and easy implementation. However, its main disadvantage is related to the fact that for fast changes in irradiance it may fail to track the maximum power point. The efficiency of the implemented P and O controller is about 96%. (author)

  7. FPGA-based calibration and monitoring system for the HADES electromagnetic calorimeter

    Energy Technology Data Exchange (ETDEWEB)

    Lai, Alessandra [University of Turin (Italy); GSI Helmholtzzentrum fuer Schwerionenforschung, Darmstadt (Germany); Collaboration: HADES-Collaboration

    2015-07-01

    The High Acceptance Di-Electron Spectrometer (HADES) at GSI was designed to measure dileptons and strangeness in elementary and heavy-ion collisions. An upgrade of HADES with an Electromagnetic Calorimeter (ECAL) has started and will be ready for beam in 2017. The goal is to measure π{sup 0} and η meson yields together with the dielectron data in pion and proton-induced reactions as well as in heavy ion collisions. Moreover, photon measurement is important for Λ{sup 0} (1405) and Σ{sup 0} (1385) spectroscopy. It is essential to precisely calibrate all the lead-glass crystal modules individually in order to achieve the required ECAL performances. Continuous monitoring with a light pulser system is required. It is foreseen to use blue light from an LED source, driven by short signals from a flexible pulse generator and distributed with optical fibers to each module of the ECAL. Due to their great flexibility, Field Programmable Gate Arrays (FPGA) have been chosen to implement the mentioned monitoring system. In this contribution an FPGA-based calibration system for commissioning as well as long term stability of the ECAL modules are presented.

  8. FPGA-based architecture for motion recovering in real-time

    Science.gov (United States)

    Arias-Estrada, Miguel; Maya-Rueda, Selene E.; Torres-Huitzil, Cesar

    2002-03-01

    A key problem in the computer vision field is the measurement of object motion in a scene. The main goal is to compute an approximation of the 3D motion from the analysis of an image sequence. Once computed, this information can be used as a basis to reach higher level goals in different applications. Motion estimation algorithms pose a significant computational load for the sequential processors limiting its use in practical applications. In this work we propose a hardware architecture for motion estimation in real time based on FPGA technology. The technique used for motion estimation is Optical Flow due to its accuracy, and the density of velocity estimation, however other techniques are being explored. The architecture is composed of parallel modules working in a pipeline scheme to reach high throughput rates near gigaflops. The modules are organized in a regular structure to provide a high degree of flexibility to cover different applications. Some results will be presented and the real-time performance will be discussed and analyzed. The architecture is prototyped in an FPGA board with a Virtex device interfaced to a digital imager.

  9. [Design of extracorporeal apparatus of capsule endoscopy based on ARM+FPGA].

    Science.gov (United States)

    Wang, Shenghua; Zhang, Sijie; Wang, Yue; Wang, Zhenxing

    2011-10-01

    Considering that the patients would bear the annoyance of fixed posture for long time when they are examined with gastrointestinal wireless endoscopy, even though portable devices have been developed, the treatments still depend on PC so much, we proposed an embedded solution based on ARM + FPGA. It used embedded ARM9 S3C2440 as processor core, collected images from digestive tract through capsule endoscopy which can be swallowed down there, and wirelessly transferred these images to the receiving system, then used video decoder chip SAA7114H for analog of NTSC video image decode. And under FPGA's logic controlling, effective digital video signal was transferred to S3C2440 for further treatment. Finally within the embedded Linux environment, we programmed the visual user interfaces using the QT/Embedded, realizing the offline record of the real-time video images of digestive tract portable and preferences. It can make patients move more freely and even without PC when examining. In addition, the method greatly improves the efficiency of the doctor, and is more intelligent and with more humane nature.

  10. Modular and reconfigurable common PCB-platform of FPGA based LLRF control system for TESLA test facility

    Energy Technology Data Exchange (ETDEWEB)

    Pozniak, K.T.; Romaniuk, R.S. [Institute of Electronic Systems, Warsaw (Poland); Kierzkowski, K. [Institute of Experimental Physics, Warsaw (Poland)

    2005-07-01

    The paper includes a description of predicted functionalities to be implemented in a universal motherboard (MB) for the next generation of LLRF control system for TESLA. The motherboard bases on a number of quasi-autonomous embedded executive modules. The modules are implemented in a few FPGA chips featured by the MB. The paper presents a practical design of the MB. The initial (basic) solution of the MB has the Cyclone as the chip where the board management is embedded. The board features communication modules - VME and micro, single chip PC with Ethernet. The board provides power supply for the FPGA chips. The board has fast internal communication between particular modules. (orig.)

  11. Modular and reconfigurable common PCB-platform of FPGA based LLRF control system for TESLA test facility

    International Nuclear Information System (INIS)

    Pozniak, K.T.; Romaniuk, R.S.; Kierzkowski, K.

    2005-01-01

    The paper includes a description of predicted functionalities to be implemented in a universal motherboard (MB) for the next generation of LLRF control system for TESLA. The motherboard bases on a number of quasi-autonomous embedded executive modules. The modules are implemented in a few FPGA chips featured by the MB. The paper presents a practical design of the MB. The initial (basic) solution of the MB has the Cyclone as the chip where the board management is embedded. The board features communication modules - VME and micro, single chip PC with Ethernet. The board provides power supply for the FPGA chips. The board has fast internal communication between particular modules. (orig.)

  12. FPGA-Based Real-Time Motion Detection for Automated Video Surveillance Systems

    Directory of Open Access Journals (Sweden)

    Sanjay Singh

    2016-03-01

    Full Text Available Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation of a motion detection algorithm for such vision based automated surveillance systems. A dedicated VLSI architecture has been proposed and designed for clustering-based motion detection scheme. The working prototype of a complete standalone automated video surveillance system, including input camera interface, designed motion detection VLSI architecture, and output display interface, with real-time relevant motion detection capabilities, has been implemented on Xilinx ML510 (Virtex-5 FX130T FPGA platform. The prototyped system robustly detects the relevant motion in real-time in live PAL (720 × 576 resolution video streams directly coming from the camera.

  13. A Compute Environment of ABC95 Array Computer Based on Multi-FPGA Chip

    Institute of Scientific and Technical Information of China (English)

    2000-01-01

    ABC95 array computer is a multi-function network's computer based on FPGA technology, The multi-function network supports processors conflict-free access data from memory and supports processors access data from processors based on enhanced MESH network.ABC95 instruction's system includes control instructions, scalar instructions, vectors instructions.Mostly net-work instructions are introduced.A programming environment of ABC95 array computer assemble language is designed.A programming environment of ABC95 array computer for VC++ is advanced.It includes load function of ABC95 array computer program and data, store function, run function and so on.Specially, The data type of ABC95 array computer conflict-free access is defined.The results show that these technologies can develop programmer of ABC95 array computer effectively.

  14. FPGA-based trigger system for the LUX dark matter experiment

    Science.gov (United States)

    Akerib, D. S.; Araújo, H. M.; Bai, X.; Bailey, A. J.; Balajthy, J.; Beltrame, P.; Bernard, E. P.; Bernstein, A.; Biesiadzinski, T. P.; Boulton, E. M.; Bradley, A.; Bramante, R.; Cahn, S. B.; Carmona-Benitez, M. C.; Chan, C.; Chapman, J. J.; Chiller, A. A.; Chiller, C.; Currie, A.; Cutter, J. E.; Davison, T. J. R.; de Viveiros, L.; Dobi, A.; Dobson, J. E. Y.; Druszkiewicz, E.; Edwards, B. N.; Faham, C. H.; Fiorucci, S.; Gaitskell, R. J.; Gehman, V. M.; Ghag, C.; Gibson, K. R.; Gilchriese, M. G. D.; Hall, C. R.; Hanhardt, M.; Haselschwardt, S. J.; Hertel, S. A.; Hogan, D. P.; Horn, M.; Huang, D. Q.; Ignarra, C. M.; Ihm, M.; Jacobsen, R. G.; Ji, W.; Kazkaz, K.; Khaitan, D.; Knoche, R.; Larsen, N. A.; Lee, C.; Lenardo, B. G.; Lesko, K. T.; Lindote, A.; Lopes, M. I.; Malling, D. C.; Manalaysay, A. G.; Mannino, R. L.; Marzioni, M. F.; McKinsey, D. N.; Mei, D.-M.; Mock, J.; Moongweluwan, M.; Morad, J. A.; Murphy, A. St. J.; Nehrkorn, C.; Nelson, H. N.; Neves, F.; O`Sullivan, K.; Oliver-Mallory, K. C.; Ott, R. A.; Palladino, K. J.; Pangilinan, M.; Pease, E. K.; Phelps, P.; Reichhart, L.; Rhyne, C.; Shaw, S.; Shutt, T. A.; Silva, C.; Skulski, W.; Solovov, V. N.; Sorensen, P.; Stephenson, S.; Sumner, T. J.; Szydagis, M.; Taylor, D. J.; Taylor, W.; Tennyson, B. P.; Terman, P. A.; Tiedt, D. R.; To, W. H.; Tripathi, M.; Tvrznikova, L.; Uvarov, S.; Verbus, J. R.; Webb, R. C.; White, J. T.; Whitis, T. J.; Witherell, M. S.; Wolfs, F. L. H.; Yin, J.; Young, S. K.; Zhang, C.

    2016-05-01

    LUX is a two-phase (liquid/gas) xenon time projection chamber designed to detect nuclear recoils resulting from interactions with dark matter particles. Signals from the detector are processed with an FPGA-based digital trigger system that analyzes the incoming data in real-time, with just a few microsecond latency. The system enables first pass selection of events of interest based on their pulse shape characteristics and 3D localization of the interactions. It has been shown to be > 99 % efficient in triggering on S2 signals induced by only few extracted liquid electrons. It is continuously and reliably operating since its full underground deployment in early 2013. This document is an overview of the systems capabilities, its inner workings, and its performance.

  15. An FPGA-Based Quench Detection and Protection System for Superconducting Accelerator Magnets

    CERN Document Server

    Carcagno, Ruben H; Lamm, Michael J; Makulski, Andrzej; Nehring, Roger; Orris, Darryl; Pishchalnikov, Yu M; Tartaglia, M

    2005-01-01

    A new quench detection and protection system for superconducting accelerator magnets was developed at the Fermilab's Magnet Test Facility (MTF). This system is based on a Field-Programmable Gate Array (FPGA) module, and it is made of mostly commerically available, integrated hardware and software components. It provides most of the functionality of our existing VME-based quench detection and protection system, but in addition the new system is easily scalable to protect multiple magnets powered independently and has a more powerful user interface and analysis tools. First applications of the new system will be for testing corrector coil packages. In this paper we describe the new system and present results of testing LHC Interaction Region Quadrupole (IRQ) correctors.

  16. An FPGA-based quench detection and protection system for superconducting accelerator magnets

    International Nuclear Information System (INIS)

    Carcagno, R.H.; Feher, S.; Lamm, M.; Makulski, A.; Nehring, R.; Orris, D.F.; Pischalnikov, Y.; Tartaglia, M.; Fermilab

    2005-01-01

    A new quench detection and protection system for superconducting accelerator magnets was developed for the Fermilab's Magnet Test Facility (MTF). This system is based on a Field-Programmable Gate Array (FPGA) module, and it is made of mostly commercially available, integrated hardware and software components. It provides all the functions of our existing VME-based quench detection and protection system, but in addition the new system is easily scalable to protect multiple magnets powered independently and a more powerful user interface and analysis tools. The new system has been used successfully for testing LHC Interaction Region Quadrupoles correctors and High Field Magnet HFDM04. In this paper we describe the system and present results

  17. Design and Implementation of a FPGA and DSP Based MIMO Radar Imaging System

    Directory of Open Access Journals (Sweden)

    Wei Wang

    2015-06-01

    Full Text Available The work presented in this paper is aimed at the implementation of a real-time multiple-input multiple-output (MIMO imaging radar used for area surveillance. In this radar, the equivalent virtual array method and time-division technique are applied to make 16 virtual elements synthesized from the MIMO antenna array. The chirp signal generater is based on a combination of direct digital synthesizer (DDS and phase locked loop (PLL. A signal conditioning circuit is used to deal with the coupling effect within the array. The signal processing platform is based on an efficient field programmable gates array (FPGA and digital signal processor (DSP pipeline where a robust beamforming imaging algorithm is running on. The radar system was evaluated through a real field experiment. Imaging capability and real-time performance shown in the results demonstrate the practical feasibility of the implementation.

  18. An FPGA-based quench detection and protection system for superconducting accelerator magnets

    Energy Technology Data Exchange (ETDEWEB)

    Carcagno, R.H.; Feher, S.; Lamm, M.; Makulski, A.; Nehring, R.; Orris, D.F.; Pischalnikov, Y.; Tartaglia, M.; /Fermilab

    2005-05-01

    A new quench detection and protection system for superconducting accelerator magnets was developed for the Fermilab's Magnet Test Facility (MTF). This system is based on a Field-Programmable Gate Array (FPGA) module, and it is made of mostly commercially available, integrated hardware and software components. It provides all the functions of our existing VME-based quench detection and protection system, but in addition the new system is easily scalable to protect multiple magnets powered independently and a more powerful user interface and analysis tools. The new system has been used successfully for testing LHC Interaction Region Quadrupoles correctors and High Field Magnet HFDM04. In this paper we describe the system and present results.

  19. FPGA Techniques Based New Hybrid Modulation Strategies for Voltage Source Inverters

    Science.gov (United States)

    Sudha, L. U.; Baskaran, J.; Elankurisil, S. A.

    2015-01-01

    This paper corroborates three different hybrid modulation strategies suitable for single-phase voltage source inverter. The proposed method is formulated using fundamental switching and carrier based pulse width modulation methods. The main tale of this proposed method is to optimize a specific performance criterion, such as minimization of the total harmonic distortion (THD), lower order harmonics, switching losses, and heat losses. The proposed method is articulated using fundamental switching and carrier based pulse width modulation methods. Thus, the harmonic pollution in the power system will be reduced and the power quality will be augmented with better harmonic profile for a target fundamental output voltage. The proposed modulation strategies are simulated in MATLAB r2010a and implemented in a Xilinx spartan 3E-500 FG 320 FPGA processor. The feasibility of these modulation strategies is authenticated through simulation and experimental results. PMID:25821852

  20. FPGA-based trigger system for the LUX dark matter experiment

    Energy Technology Data Exchange (ETDEWEB)

    Akerib, D. S.; Araújo, H. M.; Bai, X.; Bailey, A. J.; Balajthy, J.; Beltrame, P.; Bernard, E. P.; Bernstein, A.; Biesiadzinski, T. P.; Boulton, E. M.; Bradley, A.; Bramante, R.; Cahn, S. B.; Carmona-Benitez, M. C.; Chan, C.; Chapman, J. J.; Chiller, A. A.; Chiller, C.; Currie, A.; Cutter, J. E.; Davison, T. J. R.; de Viveiros, L.; Dobi, A.; Dobson, J. E. Y.; Druszkiewicz, E.; Edwards, B. N.; Faham, C. H.; Fiorucci, S.; Gaitskell, R. J.; Gehman, V. M.; Ghag, C.; Gibson, K. R.; Gilchriese, M. G. D.; Hall, C. R.; Hanhardt, M.; Haselschwardt, S. J.; Hertel, S. A.; Hogan, D. P.; Horn, M.; Huang, D. Q.; Ignarra, C. M.; Ihm, M.; Jacobsen, R. G.; Ji, W.; Kazkaz, K.; Khaitan, D.; Knoche, R.; Larsen, N. A.; Lee, C.; Lenardo, B. G.; Lesko, K. T.; Lindote, A.; Lopes, M. I.; Malling, D. C.; Manalaysay, A. G.; Mannino, R. L.; Marzioni, M. F.; McKinsey, D. N.; Mei, D. -M.; Mock, J.; Moongweluwan, M.; Morad, J. A.; Murphy, A. St. J.; Nehrkorn, C.; Nelson, H. N.; Neves, F.; O׳Sullivan, K.; Oliver-Mallory, K. C.; Ott, R. A.; Palladino, K. J.; Pangilinan, M.; Pease, E. K.; Phelps, P.; Reichhart, L.; Rhyne, C.; Shaw, S.; Shutt, T. A.; Silva, C.; Skulski, W.; Solovov, V. N.; Sorensen, P.; Stephenson, S.; Sumner, T. J.; Szydagis, M.; Taylor, D. J.; Taylor, W.; Tennyson, B. P.; Terman, P. A.; Tiedt, D. R.; To, W. H.; Tripathi, M.; Tvrznikova, L.; Uvarov, S.; Verbus, J. R.; Webb, R. C.; White, J. T.; Whitis, T. J.; Witherell, M. S.; Wolfs, F. L. H.; Yin, J.; Young, S. K.; Zhang, C.

    2016-05-01

    LUX is a two-phase (liquid/gas) xenon time projection chamber designed to detect nuclear recoils resulting from interactions with dark matter particles. Signals from the detector are processed with an FPGA-based digital trigger system that analyzes the incoming data in real-time, with just a few microsecond latency. The system enables first pass selection of events of interest based on their pulse shape characteristics and 3D localization of the interactions. It has been shown to be >99% efficient in triggering on S2 signals induced by only few extracted liquid electrons. It is continuously and reliably operating since its full underground deployment in early 2013. This document is an overview of the systems capabilities, its inner workings, and its performance.

  1. A FPGA-Based Broadband EIT System for Complex Bioimpedance Measurements—Design and Performance Estimation

    Directory of Open Access Journals (Sweden)

    Roman Kusche

    2015-07-01

    Full Text Available Electrical impedance tomography (EIT is an imaging method that is able to estimate the electrical conductivity distribution of living tissue. This work presents a field programmable gate array (FPGA-based multi-frequency EIT system for complex, time-resolved bioimpedance measurements. The system has the capability to work with measurement setups with up to 16 current electrodes and 16 voltage electrodes. The excitation current has a range of about 10 µA to 5 mA, whereas the sinusoidal signal used for excitation can have a frequency of up to 500 kHz. Additionally, the usage of a chirp or rectangular signal excitation is possible. Furthermore, the described system has a sample rate of up to 3480 impedance spectra per second (ISPS. The performance of the EIT system is demonstrated with a resistor-based phantom and tank phantoms. Additionally, first measurements taken from the human thorax during a breathing cycle are presented.

  2. 40-Gbps optical backbone network deep packet inspection based on FPGA

    Science.gov (United States)

    Zuo, Yuan; Huang, Zhiping; Su, Shaojing

    2014-11-01

    In the era of information, the big data, which contains huge information, brings about some problems, such as high speed transmission, storage and real-time analysis and process. As the important media for data transmission, the Internet is the significant part for big data processing research. With the large-scale usage of the Internet, the data streaming of network is increasing rapidly. The speed level in the main fiber optic communication of the present has reached 40Gbps, even 100Gbps, therefore data on the optical backbone network shows some features of massive data. Generally, data services are provided via IP packets on the optical backbone network, which is constituted with SDH (Synchronous Digital Hierarchy). Hence this method that IP packets are directly mapped into SDH payload is named POS (Packet over SDH) technology. Aiming at the problems of real time process of high speed massive data, this paper designs a process system platform based on ATCA for 40Gbps POS signal data stream recognition and packet content capture, which employs the FPGA as the CPU. This platform offers pre-processing of clustering algorithms, service traffic identification and data mining for the following big data storage and analysis with high efficiency. Also, the operational procedure is proposed in this paper. Four channels of 10Gbps POS signal decomposed by the analysis module, which chooses FPGA as the kernel, are inputted to the flow classification module and the pattern matching component based on TCAM. Based on the properties of the length of payload and net flows, buffer management is added to the platform to keep the key flow information. According to data stream analysis, DPI (deep packet inspection) and flow balance distribute, the signal is transmitted to the backend machine through the giga Ethernet ports on back board. Practice shows that the proposed platform is superior to the traditional applications based on ASIC and NP.

  3. Embedded Platform for Automatic Testing and Optimizing of FPGA Based Cryptographic True Random Number Generators

    Directory of Open Access Journals (Sweden)

    M. Varchola

    2009-12-01

    Full Text Available This paper deals with an evaluation platform for cryptographic True Random Number Generators (TRNGs based on the hardware implementation of statistical tests for FPGAs. It was developed in order to provide an automatic tool that helps to speed up the TRNG design process and can provide new insights on the TRNG behavior as it will be shown on a particular example in the paper. It enables to test sufficient statistical properties of various TRNG designs under various working conditions on the fly. Moreover, the tests are suitable to be embedded into cryptographic hardware products in order to recognize TRNG output of weak quality and thus increase its robustness and reliability. Tests are fully compatible with the FIPS 140 standard and are implemented by the VHDL language as an IP-Core for vendor independent FPGAs. A recent Flash based Actel Fusion FPGA was chosen for preliminary experiments. The Actel version of the tests possesses an interface to the Actel’s CoreMP7 softcore processor that is fully compatible with the industry standard ARM7TDMI. Moreover, identical tests suite was implemented to the Xilinx Virtex 2 and 5 in order to compare the performance of the proposed solution with the performance of already published one based on the same FPGAs. It was achieved 25% and 65% greater clock frequency respectively while consuming almost equal resources of the Xilinx FPGAs. On the top of it, the proposed FIPS 140 architecture is capable of processing one random bit per one clock cycle which results in 311.5 Mbps throughput for Virtex 5 FPGA.

  4. Design and implementation of FPGA-based LQ control of active magnetic bearings

    Energy Technology Data Exchange (ETDEWEB)

    Jastrzebski, R.

    2007-07-01

    The need for high performance, high precision, and energy saving in rotating machinery demands an alternative solution to traditional bearings. Because of the contactless operation principle, the rotating machines employing active magnetic bearings (AMBs) provide many advantages over the traditional ones. The advantages such as contamination-free operation, low maintenance costs, high rotational speeds, low parasitic losses, programmable stiffness and damping, and vibration insulation come at expense of high cost, and complex technical solution. All these properties make the use of AMBs appropriate primarily for specific and highly demanding applications. High performance and high precision control requires model-based control methods and accurate models of the flexible rotor. In turn, complex models lead to high-order controllers and feature considerable computational burden. Fortunately, in the last few years the advancements in signal processing devices provide new perspective on the real-time control of AMBs. The design and the real-time digital implementation of the high-order LQ controllers, which focus on fast execution times, are the subjects of this work. In particular, the control design and implementation in the field programmable gate array (FPGA) circuits are investigated. The optimal design is guided by the physical constraints of the system for selecting the optimal weighting matrices. The plant model is complemented by augmenting appropriate disturbance models. The compensation of the force-field nonlinearities is proposed for decreasing the uncertainty of the actuator. A disturbance-observer-based unbalance compensation for canceling the magnetic force vibrations or vibrations in the measured positions is presented. The theoretical studies are verified by the practical experiments utilizing a custom-built laboratory test rig. The test rig uses a prototyping control platform developed in the scope of this work. To sum up, the work makes a step in

  5. The new FPGA based discriminator board for the CBELSA/TAPS experiment

    Energy Technology Data Exchange (ETDEWEB)

    Fix, Eugenia [HISKP, Universitaet Bonn (Germany); Collaboration: CBELSA/TAPS-Collaboration

    2016-07-01

    The Crystal Barrel calorimeter at ELSA, which consists of 1320 CsI(Tl) crystals has been upgraded by a new Avalanche Photo Diode (APD) crystal readout.The APD readout electronics will provide a fast trigger signal down to 10 MeV energy deposit per single crystal. The processing of these trigger signals requires the development of a previously not existent timing branch of the readout chain of the Crystal Barrel calorimeter. Core component of the timing branch is a newly developed, FPGA based discriminator board. Its firmware contains modules for time to digital conversion, rise time compensation and parts of a cluster finder. In addition the reference voltages and discriminator thresholds are controlled and monitored. This poster presents the design and the achievable accuracy of the new discriminator.

  6. A real-time MTFC algorithm of space remote-sensing camera based on FPGA

    Science.gov (United States)

    Zhao, Liting; Huang, Gang; Lin, Zhe

    2018-01-01

    A real-time MTFC algorithm of space remote-sensing camera based on FPGA was designed. The algorithm can provide real-time image processing to enhance image clarity when the remote-sensing camera running on-orbit. The image restoration algorithm adopted modular design. The MTF measurement calculation module on-orbit had the function of calculating the edge extension function, line extension function, ESF difference operation, normalization MTF and MTFC parameters. The MTFC image filtering and noise suppression had the function of filtering algorithm and effectively suppressing the noise. The algorithm used System Generator to design the image processing algorithms to simplify the design structure of system and the process redesign. The image gray gradient dot sharpness edge contrast and median-high frequency were enhanced. The image SNR after recovery reduced less than 1 dB compared to the original image. The image restoration system can be widely used in various fields.

  7. Wireless, low-cost, FPGA-based miniature gamma ray spectrometer

    Energy Technology Data Exchange (ETDEWEB)

    Becker, E.M., E-mail: beckere@engr.orst.edu; Farsoni, A.T.

    2014-10-11

    A compact, low-cost, wireless gamma-ray spectrometer is a tool sought by a number of different organizations in the field of radiation detection. Such a device has applications in emergency response, battlefield assessment, and personal dosimetry. A prototype device fitting this description has been constructed in the Advanced Radiation Instrumentation Laboratory at Oregon State University. The prototype uses a CsI(Tl) scintillator coupled to a solid-state photomultiplier and a 40 MHz, 12-bit, FPGA-based digital pulse processor to measure gamma radiation, and is able to be accessed wirelessly by mobile phone. The prototype device consumes roughly 420 mW, weighs about 28 g (not including battery), and measures 2.54×3.81 cm{sup 2}. The prototype device is able to achieve 5.9% FWHM energy resolution at 662 keV.

  8. A clock and data recovery method based on phase detector implemented by delay chain in FPGA

    International Nuclear Information System (INIS)

    Xie Mingpu; Wu Jie; Zhang Jie

    2009-01-01

    A clock and data recovery method based on charge pump PLL was developed to archive medium data rate serial digital communication with simple line transceivers. The phase detector was realized by FPGA. A delay chain was constructed by delay elements with the same fixed delay. Every output of the delay elements was latched by the VCO output clock when the input signal went through the delay chain. The latched result was used to detect the data transition, which reflected the phase difference between the input signal and the VCO output clock. The VCO control voltage was adjust by charge pump to reduce the phase difference and archive phase lock. The loop filter was a passive filter,parameters of which were calculated from parameters of the delay chain and VCO. The experimental result shows that the clock of a 64Mbps transmission was recovered with a jitter less than 200 ps. (authors)

  9. Dual-Phase Lock-In Amplifier Based on FPGA for Low-Frequencies Experiments

    Directory of Open Access Journals (Sweden)

    Gonzalo Macias-Bobadilla

    2016-03-01

    Full Text Available Photothermal techniques allow the detection of characteristics of material without invading it. Researchers have developed hardware for some specific Phase and Amplitude detection (Lock-In Function applications, eliminating space and unnecessary electronic functions, among others. This work shows the development of a Digital Lock-In Amplifier based on a Field Programmable Gate Array (FPGA for low-frequency applications. This system allows selecting and generating the appropriated frequency depending on the kind of experiment or material studied. The results show good frequency stability in the order of 1.0 × 10−9 Hz, which is considered good linearity and repeatability response for the most common Laboratory Amplitude and Phase Shift detection devices, with a low error and standard deviation.

  10. Design of Energy Storage Management System Based on FPGA in Micro-Grid

    Science.gov (United States)

    Liang, Yafeng; Wang, Yanping; Han, Dexiao

    2018-01-01

    Energy storage system is the core to maintain the stable operation of smart micro-grid. Aiming at the existing problems of the energy storage management system in the micro-grid such as Low fault tolerance, easy to cause fluctuations in micro-grid, a new intelligent battery management system based on field programmable gate array is proposed : taking advantage of FPGA to combine the battery management system with the intelligent micro-grid control strategy. Finally, aiming at the problem that during estimation of battery charge State by neural network, initialization of weights and thresholds are not accurate leading to large errors in prediction results, the genetic algorithm is proposed to optimize the neural network method, and the experimental simulation is carried out. The experimental results show that the algorithm has high precision and provides guarantee for the stable operation of micro-grid.

  11. Implementation in an FPGA circuit of Edge detection algorithm based on the Discrete Wavelet Transforms

    Science.gov (United States)

    Bouganssa, Issam; Sbihi, Mohamed; Zaim, Mounia

    2017-07-01

    The 2D Discrete Wavelet Transform (DWT) is a computationally intensive task that is usually implemented on specific architectures in many imaging systems in real time. In this paper, a high throughput edge or contour detection algorithm is proposed based on the discrete wavelet transform. A technique for applying the filters on the three directions (Horizontal, Vertical and Diagonal) of the image is used to present the maximum of the existing contours. The proposed architectures were designed in VHDL and mapped to a Xilinx Sparten6 FPGA. The results of the synthesis show that the proposed architecture has a low area cost and can operate up to 100 MHz, which can perform 2D wavelet analysis for a sequence of images while maintaining the flexibility of the system to support an adaptive algorithm.

  12. FPGA-based real-time phase measuring profilometry algorithm design and implementation

    Science.gov (United States)

    Zhan, Guomin; Tang, Hongwei; Zhong, Kai; Li, Zhongwei; Shi, Yusheng

    2016-11-01

    Phase measuring profilometry (PMP) has been widely used in many fields, like Computer Aided Verification (CAV), Flexible Manufacturing System (FMS) et al. High frame-rate (HFR) real-time vision-based feedback control will be a common demands in near future. However, the instruction time delay in the computer caused by numerous repetitive operations greatly limit the efficiency of data processing. FPGA has the advantages of pipeline architecture and parallel execution, and it fit for handling PMP algorithm. In this paper, we design a fully pipelined hardware architecture for PMP. The functions of hardware architecture includes rectification, phase calculation, phase shifting, and stereo matching. The experiment verified the performance of this method, and the factors that may influence the computation accuracy was analyzed.

  13. FPGA based image processing for optical surface inspection with real time constraints

    Science.gov (United States)

    Hasani, Ylber; Bodenstorfer, Ernst; Brodersen, Jörg; Mayer, Konrad J.

    2015-02-01

    Today, high-quality printing products like banknotes, stamps, or vouchers, are automatically checked by optical surface inspection systems. In a typical optical surface inspection system, several digital cameras acquire the printing products with fine resolution from different viewing angles and at multiple wavelengths of the visible and also near infrared spectrum of light. The cameras deliver data streams with a huge amount of image data that have to be processed by an image processing system in real time. Due to the printing industry's demand for higher throughput together with the necessity to check finer details of the print and its security features, the data rates to be processed tend to explode. In this contribution, a solution is proposed, where the image processing load is distributed between FPGAs and digital signal processors (DSPs) in such a way that the strengths of both technologies can be exploited. The focus lies upon the implementation of image processing algorithms in an FPGA and its advantages. In the presented application, FPGAbased image-preprocessing enables real-time implementation of an optical color surface inspection system with a spatial resolution of 100 μm and for object speeds over 10 m/s. For the implementation of image processing algorithms in the FPGA, pipeline parallelism with clock frequencies up to 150 MHz together with spatial parallelism based on multiple instantiations of modules for parallel processing of multiple data streams are exploited for the processing of image data of two cameras and three color channels. Due to their flexibility and their fast response times, it is shown that FPGAs are ideally suited for realizing a configurable all-digital PLL for the processing of camera line-trigger signals with frequencies about 100 kHz, using pure synchronous digital circuit design.

  14. An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

    Directory of Open Access Journals (Sweden)

    Y. H. Lee

    2016-01-01

    Full Text Available Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

  15. Carry-chain propagation delay impacts on resolution of FPGA-based TDC

    International Nuclear Information System (INIS)

    Dong Lei; Yang Junfeng; Song Kezhu

    2014-01-01

    The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy. (authors)

  16. Development of γ dose rate monitor based on FPGA and single-chip microcomputer

    International Nuclear Information System (INIS)

    He Zhiguo; Ling Qiu; Guo Lanying; Yang Binhua

    2009-01-01

    A novelγdose rate monitor with multiple channels signal collection in which takes the FPGA as the core process chip and single-chip microcomputer as the data processor had been developed. This paper introduced the communication interface design between FPGA and MCU, and gave the data acquisition module and the function simulation chart designed by FPGA. In addition, the software and hardware design diagrams of MCU had been given in this paper. The maximum digitallization was carried on in the designing process. The experiments showed that the scheme for the system matched to the requests completely. (authors)

  17. Development of an FPGA-Based Motion Control IC for Caving Machine

    Directory of Open Access Journals (Sweden)

    Chiu-Keng Lai

    2014-03-01

    Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

  18. Central FPGA-based Destination and Load Control in the LHCb MHz Event Readout

    CERN Document Server

    Jacobsson, Richard

    2012-01-01

    The readout strategy of the LHCb experiment [1] is based on complete event readout at 1 MHz [2]. Over 300 sub-detector readout boards transmit event fragments at 1 MHz over a commercial 70 Gigabyte/s switching network to a distributed event building and trigger processing farm with 1470 individual multi-core computer nodes [3]. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a powerful non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. A high-speed FPGA-based central master module controls the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load balancing and trigger rate regulation as a function of the global farm load. It also ...

  19. On the evaluation of the sensitivity of SRAM-Based FPGA to errors due to natural radiation environment

    International Nuclear Information System (INIS)

    Bocquillon, Alexandre

    2009-01-01

    This work aims at designing a test methodology to analyze the effect of natural radiation on FPGA SRAM-based chip-sets. Study of likely errors due to single or multiple events occurring in the configuration memory will be based on fault-injection experiments performed with laser devices. It relies on both a description of scientific background and a description of complex architecture of FPGA SRAM-Based and usual testing apparatus. Fault injection experiments with laser are conducted on several classes of components in order to perform static tests of the configuration memory and identify the links with the application. It shows the organization and sensitivity of SRAM configuration cells. Criticality criteria for configuration bits have been specified following dynamic tests in protons accelerator, in regard to their impact on the application. From this classification was developed a predicting tool for critical error rate estimation. (author) [fr

  20. Exploration of Heterogeneous FPGA Architectures

    Directory of Open Access Journals (Sweden)

    Umer Farooq

    2011-01-01

    mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

  1. A FPGA-based Network Interface Card with GPUDirect enabling realtime GPU computing in HEP experiments

    CERN Document Server

    Lonardo, Alessandro; Ammendola, Roberto; Biagioni, Andrea; Cotta Ramusino, Angelo; Fiorini, Massimiliano; Frezza, Ottorino; Lamanna, Gianluca; Lo Cicero, Francesca; Martinelli, Michele; Neri, Ilaria; Paolucci, Pier Stanislao; Pastorelli, Elena; Pontisso, Luca; Rossetti, Davide; Simeone, Francesco; Simula, Francesco; Sozzi, Marco; Tosoratto, Laura; Vicini, Piero

    2015-01-01

    The capability of processing high bandwidth data streams in real-time is a computational requirement common to many High Energy Physics experiments. Keeping the latency of the data transport tasks under control is essential in order to meet this requirement. We present NaNet, a FPGA-based PCIe Network Interface Card design featuring Remote Direct Memory Access towards CPU and GPU memories plus a transport protocol offload module characterized by cycle-accurate upper-bound handling. The combination of these two features allows to relieve almost entirely the OS and the application from data tranfer management, minimizing the unavoidable jitter effects associated to OS process scheduling. The design currently supports one GbE (1000Base-T) and three custom 34 Gbps APElink I/O channels, but four-channels 10GbE (10Base-R) and 2.5 Gbps deterministic latency KM3link versions are being implemented. Two use cases of NaNet will be discussed: the GPU-based low level trigger for the RICH detector in the NA62 experiment an...

  2. FPGA implementation of a configurable neuromorphic CPG-based locomotion controller.

    Science.gov (United States)

    Barron-Zambrano, Jose Hugo; Torres-Huitzil, Cesar

    2013-09-01

    Neuromorphic engineering is a discipline devoted to the design and development of computational hardware that mimics the characteristics and capabilities of neuro-biological systems. In recent years, neuromorphic hardware systems have been implemented using a hybrid approach incorporating digital hardware so as to provide flexibility and scalability at the cost of power efficiency and some biological realism. This paper proposes an FPGA-based neuromorphic-like embedded system on a chip to generate locomotion patterns of periodic rhythmic movements inspired by Central Pattern Generators (CPGs). The proposed implementation follows a top-down approach where modularity and hierarchy are two desirable features. The locomotion controller is based on CPG models to produce rhythmic locomotion patterns or gaits for legged robots such as quadrupeds and hexapods. The architecture is configurable and scalable for robots with either different morphologies or different degrees of freedom (DOFs). Experiments performed on a real robot are presented and discussed. The obtained results demonstrate that the CPG-based controller provides the necessary flexibility to generate different rhythmic patterns at run-time suitable for adaptable locomotion. Copyright © 2013 Elsevier Ltd. All rights reserved.

  3. Read-out concepts for FPGA-based sub-systems within the CBM detector

    Energy Technology Data Exchange (ETDEWEB)

    Michel, Jan [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-Collaboration

    2015-07-01

    The Compressed Baryonic Matter experiment (CBM) to be built at FAIR consists of several individual sub-detectors. Some are based on custom ASICs as front-ends. Others employ FPGA based modules where extensive slow control features can be implemented to ease the recording of data and to allow for fast detection of any kind of error condition. Being designed as a free-running data acquisition, the demands also include a synchronized read-out, i.e. distribution of a common clock signal to all modules. To reduce the complexity of wiring, this is to be done sharing the same optical fibers as the data transport. During the past years, TrbNet has been designed and is used in various experiments, initially for the HADES experiment at FAIR. This protocol can now serve as a platform for the CBM read-out. In several steps, synchronous links with deterministic latency, as well as a free-streaming data transport can be included. At the same time, modifications to improve bandwidth and provide compatibility to the CERN GBTx links used for ASIC based sub-systems are to be developed. This contribution shows the planned steps as well as the current status of development.

  4. FPGA-Based Smart Sensor for Online Displacement Measurements Using a Heterodyne Interferometer

    Science.gov (United States)

    Vera-Salas, Luis Alberto; Moreno-Tapia, Sandra Veronica; Garcia-Perez, Arturo; de Jesus Romero-Troncoso, Rene; Osornio-Rios, Roque Alfredo; Serroukh, Ibrahim; Cabal-Yepez, Eduardo

    2011-01-01

    The measurement of small displacements on the nanometric scale demands metrological systems of high accuracy and precision. In this context, interferometer-based displacement measurements have become the main tools used for traceable dimensional metrology. The different industrial applications in which small displacement measurements are employed requires the use of online measurements, high speed processes, open architecture control systems, as well as good adaptability to specific process conditions. The main contribution of this work is the development of a smart sensor for large displacement measurement based on phase measurement which achieves high accuracy and resolution, designed to be used with a commercial heterodyne interferometer. The system is based on a low-cost Field Programmable Gate Array (FPGA) allowing the integration of several functions in a single portable device. This system is optimal for high speed applications where online measurement is needed and the reconfigurability feature allows the addition of different modules for error compensation, as might be required by a specific application. PMID:22164040

  5. Design and development of FPGA based TCP/IP module for real time computers in nuclear power plants

    International Nuclear Information System (INIS)

    Balasri, G. Janani; Santhana Raj, A.; Gour, Aditya; Murali, N.; Manikandan, J.

    2013-01-01

    An VME (Virtual Module Europa) bus based Real Time Computer's (RTC's) are being developed for Prototype Fast Breeder Reactor (PFBR) which is in an advanced stage of construction at Kalpakkam, where the RTC's have to communicate to the central process computer on the data collected from the field instrument and receive data from the central process computer. A Distributed Digital Control System (DDSC) architecture has been designed for this communication which is based on Transfer Communication Protocol/Internet Protocol (TCP/IP) over Ethernet. Currently the RTC's uses 'Wiznet Module', a bought out chip which implements the TCP/IP stack in hardware. This project concentrates on the design and development of Field Programmable Gate Array (FPGA) based TCP/IP module that runs on Microblaze, a 32-bit softcore processor, to take care of the communication as that of Wiznet module. Advantage of switching over to FPGA based system are its reconfigurability, desired number of sockets, and the design is stable even if the FPGA's get obsolete. (author)

  6. FPGA-Based HD Camera System for the Micropositioning of Biomedical Micro-Objects Using a Contactless Micro-Conveyor

    Directory of Open Access Journals (Sweden)

    Elmar Yusifli

    2017-03-01

    Full Text Available With recent advancements, micro-object contactless conveyers are becoming an essential part of the biomedical sector. They help avoid any infection and damage that can occur due to external contact. In this context, a smart micro-conveyor is devised. It is a Field Programmable Gate Array (FPGA-based system that employs a smart surface for conveyance along with an OmniVision complementary metal-oxide-semiconductor (CMOS HD camera for micro-object position detection and tracking. A specific FPGA-based hardware design and VHSIC (Very High Speed Integrated Circuit Hardware Description Language (VHDL implementation are realized. It is done without employing any Nios processor or System on a Programmable Chip (SOPC builder based Central Processing Unit (CPU core. It keeps the system efficient in terms of resource utilization and power consumption. The micro-object positioning status is captured with an embedded FPGA-based camera driver and it is communicated to the Image Processing, Decision Making and Command (IPDC module. The IPDC is programmed in C++ and can run on a Personal Computer (PC or on any appropriate embedded system. The IPDC decisions are sent back to the FPGA, which pilots the smart surface accordingly. In this way, an automated closed-loop system is employed to convey the micro-object towards a desired location. The devised system architecture and implementation principle is described. Its functionality is also verified. Results have confirmed the proper functionality of the developed system, along with its outperformance compared to other solutions.

  7. Implementation of a RANLUX Based Pseudo-Random Number Generator in FPGA Using VHDL and Impulse C

    OpenAIRE

    Agnieszka Dąbrowska-Boruch; Grzegorz Gancarczyk; Kazimierz Wiatr

    2014-01-01

    Monte Carlo simulations are widely used e.g. in the field of physics and molecular modelling. The main role played in these is by the high performance random number generators, such as RANLUX or MERSSENE TWISTER. In this paper the authors introduce the world's first implementation of the RANLUX algorithm on an FPGA platform for high performance computing purposes. A significant speed-up of one generator instance over 60 times, compared with a graphic card based solution, can be noticed. Compa...

  8. 1 GSPS digitizer based on the FPGA Mezzanine Card (FMC) standard with low-count pin connector.

    CERN Document Server

    Vasilyev, Mikhail

    2015-01-01

    Under the scope of a CERN summer student project, the schematic for ADC based on FMC mezzanine card with 1 GSPS sampling rate and 8 bit resolution was developed. The mezzanine is fully compatible with the standard: FPGA Mezzanine Card (FMC) [1]. A low-pin count connector was used to connect the mezzanine with the “carrier”. The carrier was an Open Hardware project: Simple PCIe FMC carrier (SPEC).

  9. FPGA-based implementation for steganalysis: a JPEG-compatibility algorithm

    Science.gov (United States)

    Gutierrez-Fernandez, E.; Portela-García, M.; Lopez-Ongil, C.; Garcia-Valderas, M.

    2013-05-01

    Steganalysis is a process to detect hidden data in cover documents, like digital images, videos, audio files, etc. This is the inverse process of steganography, which is the used method to hide secret messages. The widely use of computers and network technologies make digital files very easy-to-use means for storing secret data or transmitting secret messages through the Internet. Depending on the cover medium used to embed the data, there are different steganalysis methods. In case of images, many of the steganalysis and steganographic methods are focused on JPEG image formats, since JPEG is one of the most common formats. One of the main important handicaps of steganalysis methods is the processing speed, since it is usually necessary to process huge amount of data or it can be necessary to process the on-going internet traffic in real-time. In this paper, a JPEG steganalysis system is implemented in an FPGA in order to speed-up the detection process with respect to software-based implementations and to increase the throughput. In particular, the implemented method is the JPEG-compatibility detection algorithm that is based on the fact that when a JPEG image is modified, the resulting image is incompatible with the JPEG compression process.

  10. FPGA-Based Online PQD Detection and Classification through DWT, Mathematical Morphology and SVD

    Directory of Open Access Journals (Sweden)

    Misael Lopez-Ramirez

    2018-03-01

    Full Text Available Power quality disturbances (PQD in electric distribution systems can be produced by the utilization of non-linear loads or environmental circumstances, causing electrical equipment malfunction and reduction of its useful life. Detecting and classifying different PQDs implies great efforts in planning and structuring the monitoring system. The main disadvantage of most works in the literature is that they treat a limited number of electrical disturbances through personal computer (PC-based computation techniques, which makes it difficult to perform an online PQD classification. In this work, the novel contribution is a methodology for PQD recognition and classification through discrete wavelet transform, mathematical morphology, decomposition of singular values, and statistical analysis. Furthermore, the timely and reliable classification of different disturbances is necessary; hence, a field programmable gate array (FPGA-based integrated circuit is developed to offer a portable hardware processing unit to perform fast, online PQD classification. The obtained numerical and experimental results demonstrate that the proposed method guarantees high effectiveness during online PQD detection and classification of real voltage/current signals.

  11. An FPGA-based DS-CDMA multiuser demodulator employing adaptive multistage parallel interference cancellation

    Science.gov (United States)

    Li, Xinhua; Song, Zhenyu; Zhan, Yongjie; Wu, Qiongzhi

    2009-12-01

    Since the system capacity is severely limited, reducing the multiple access interfere (MAI) is necessary in the multiuser direct-sequence code division multiple access (DS-CDMA) system which is used in the telecommunication terminals data-transferred link system. In this paper, we adopt an adaptive multistage parallel interference cancellation structure in the demodulator based on the least mean square (LMS) algorithm to eliminate the MAI on the basis of overviewing various of multiuser dectection schemes. Neither a training sequence nor a pilot signal is needed in the proposed scheme, and its implementation complexity can be greatly reduced by a LMS approximate algorithm. The algorithm and its FPGA implementation is then derived. Simulation results of the proposed adaptive PIC can outperform some of the existing interference cancellation methods in AWGN channels. The hardware setup of mutiuser demodulator is described, and the experimental results based on it demonstrate that the simulation results shows large performance gains over the conventional single-user demodulator.

  12. An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots

    Directory of Open Access Journals (Sweden)

    Jones Y. Mori

    2012-01-01

    Full Text Available This work presents the development of an integrated hardware/software sensor system for moving object detection and distance calculation, based on background subtraction algorithm. The sensor comprises a catadioptric system composed by a camera and a convex mirror that reflects the environment to the camera from all directions, obtaining a panoramic view. The sensor is used as an omnidirectional vision system, allowing for localization and navigation tasks of mobile robots. Several image processing operations such as filtering, segmentation and morphology have been included in the processing architecture. For achieving distance measurement, an algorithm to determine the center of mass of a detected object was implemented. The overall architecture has been mapped onto a commercial low-cost FPGA device, using a hardware/software co-design approach, which comprises a Nios II embedded microprocessor and specific image processing blocks, which have been implemented in hardware. The background subtraction algorithm was also used to calibrate the system, allowing for accurate results. Synthesis results show that the system can achieve a throughput of 26.6 processed frames per second and the performance analysis pointed out that the overall architecture achieves a speedup factor of 13.78 in comparison with a PC-based solution running on the real-time operating system xPC Target.

  13. An FPGA-based silicon neuronal network with selectable excitability silicon neurons

    Directory of Open Access Journals (Sweden)

    Jing eLi

    2012-12-01

    Full Text Available This paper presents a digital silicon neuronal network which simulates the nerve system in creatures and has the ability to execute intelligent tasks, such as associative memory. Two essential elements, the mathematical-structure-based digital spiking silicon neuron (DSSN and the transmitter release based silicon synapse, allow the network to show rich dynamic behaviors and are computationally efficient for hardware implementation. We adopt mixed pipeline and parallel structure and shift operations to design a sufficient large and complex network without excessive hardware resource cost. The network with $256$ full-connected neurons is built on a Digilent Atlys board equipped with a Xilinx Spartan-6 LX45 FPGA. Besides, a memory control block and USB control block are designed to accomplish the task of data communication between the network and the host PC. This paper also describes the mechanism of associative memory performed in the silicon neuronal network. The network is capable of retrieving stored patterns if the inputs contain enough information of them. The retrieving probability increases with the similarity between the input and the stored pattern increasing. Synchronization of neurons is observed when the successful stored pattern retrieval occurs.

  14. FPGA-Based Flexible Hardware Architecture for Image Interest Point Detection

    Directory of Open Access Journals (Sweden)

    Ana Hernandez-Lopez

    2015-07-01

    Full Text Available An important challenge in computer vision is the implementation of fast and accurate feature detectors, as they are the basis for high-level image processing analysis and understanding. However, image feature detectors cannot be easily applied in embedded scenarios, mainly due to the fact that they are time consuming and require a significant amount of processing power. Although some feature detectors have been implemented in hardware, most implementations target a single detector under very specific constraints. This paper proposes a flexible hardware implementation approach for computing interest point extraction from grey-level images based on two different detectors, Harris and SUSAN, suitable for robotic applications. The design is based on parallel and configurable processing elements for window operators and a buffering strategy to support a coarse-grain pipeline scheme for operator sequencing. When targeted to a Virtex-6 FPGA, a throughput of 49.45 Mpixel/s (processing rate of 161 frames per second of VGA image resolution is achieved at a clock frequency of 50 MHz.

  15. An FPGA-based Bunch-by-Bunch Position and Angle Feedback System at ATF2

    CERN Document Server

    Christian, G B; Bett, D R; Burrows, P N; Constance, B; Davis, M R; Gerbershagen, A; Perry, C; Resta Lopez, J

    2011-01-01

    The FONT5 intra-train feedback system serves as a prototype for an interaction point beam-based feedback system for future electron-positron colliders, such as the International Linear Collider. The system has been tested on the KEK Accelerator Test Facility (ATF) and is deployed to stabilise the beam orbit at the ATF2. The goal of this system is to correct both position and angle jitter in the vertical plane, providing stability of ~1 micron at the entrance to the ATF2 final-focus system. The system comprises three stripline beam position monitors (BPMs) and two stripline kickers, custom low-latency analogue front-end BPM processors, a custom FPGA-based digital processing board with fast ADCs, and custom kicker-drive amplifiers. An overview of the hardware, and the latest results from beam tests at ATF2, will be presented. The total latency of the system with coupled position and angle feedback loops operating simultaneously was measured to be approximately 140 ns. The greatest degree of correction observed ...

  16. FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

    Science.gov (United States)

    Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

    2016-05-01

    This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

  17. High performance image acquisition and processing architecture for fast plant system controllers based on FPGA and GPU

    International Nuclear Information System (INIS)

    Nieto, J.; Sanz, D.; Guillén, P.; Esquembri, S.; Arcas, G. de; Ruiz, M.; Vega, J.; Castro, R.

    2016-01-01

    Highlights: • To test an image acquisition and processing system for Camera Link devices based in a FPGA, compliant with ITER fast controllers. • To move data acquired from the set NI1483-NIPXIe7966R directly to a NVIDIA GPU using NVIDIA GPUDirect RDMA technology. • To obtain a methodology to include GPUs processing in ITER Fast Plant Controllers, using EPICS integration through Nominal Device Support (NDS). - Abstract: The two dominant technologies that are being used in real time image processing are Field Programmable Gate Array (FPGA) and Graphical Processor Unit (GPU) due to their algorithm parallelization capabilities. But not much work has been done to standardize how these technologies can be integrated in data acquisition systems, where control and supervisory requirements are in place, such as ITER (International Thermonuclear Experimental Reactor). This work proposes an architecture, and a development methodology, to develop image acquisition and processing systems based on FPGAs and GPUs compliant with ITER fast controller solutions. A use case based on a Camera Link device connected to an FPGA DAQ device (National Instruments FlexRIO technology), and a NVIDIA Tesla GPU series card has been developed and tested. The architecture proposed has been designed to optimize system performance by minimizing data transfer operations and CPU intervention thanks to the use of NVIDIA GPUDirect RDMA and DMA technologies. This allows moving the data directly between the different hardware elements (FPGA DAQ-GPU-CPU) avoiding CPU intervention and therefore the use of intermediate CPU memory buffers. A special effort has been put to provide a development methodology that, maintaining the highest possible abstraction from the low level implementation details, allows obtaining solutions that conform to CODAC Core System standards by providing EPICS and Nominal Device Support.

  18. High performance image acquisition and processing architecture for fast plant system controllers based on FPGA and GPU

    Energy Technology Data Exchange (ETDEWEB)

    Nieto, J., E-mail: jnieto@sec.upm.es [Grupo de Investigación en Instrumentación y Acústica Aplicada, Universidad Politécnica de Madrid, Crta. Valencia Km-7, Madrid 28031 (Spain); Sanz, D.; Guillén, P.; Esquembri, S.; Arcas, G. de; Ruiz, M. [Grupo de Investigación en Instrumentación y Acústica Aplicada, Universidad Politécnica de Madrid, Crta. Valencia Km-7, Madrid 28031 (Spain); Vega, J.; Castro, R. [Asociación EURATOM/CIEMAT para Fusión, Madrid (Spain)

    2016-11-15

    Highlights: • To test an image acquisition and processing system for Camera Link devices based in a FPGA, compliant with ITER fast controllers. • To move data acquired from the set NI1483-NIPXIe7966R directly to a NVIDIA GPU using NVIDIA GPUDirect RDMA technology. • To obtain a methodology to include GPUs processing in ITER Fast Plant Controllers, using EPICS integration through Nominal Device Support (NDS). - Abstract: The two dominant technologies that are being used in real time image processing are Field Programmable Gate Array (FPGA) and Graphical Processor Unit (GPU) due to their algorithm parallelization capabilities. But not much work has been done to standardize how these technologies can be integrated in data acquisition systems, where control and supervisory requirements are in place, such as ITER (International Thermonuclear Experimental Reactor). This work proposes an architecture, and a development methodology, to develop image acquisition and processing systems based on FPGAs and GPUs compliant with ITER fast controller solutions. A use case based on a Camera Link device connected to an FPGA DAQ device (National Instruments FlexRIO technology), and a NVIDIA Tesla GPU series card has been developed and tested. The architecture proposed has been designed to optimize system performance by minimizing data transfer operations and CPU intervention thanks to the use of NVIDIA GPUDirect RDMA and DMA technologies. This allows moving the data directly between the different hardware elements (FPGA DAQ-GPU-CPU) avoiding CPU intervention and therefore the use of intermediate CPU memory buffers. A special effort has been put to provide a development methodology that, maintaining the highest possible abstraction from the low level implementation details, allows obtaining solutions that conform to CODAC Core System standards by providing EPICS and Nominal Device Support.

  19. Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

    Science.gov (United States)

    Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

    In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

  20. Commissioning of FPGA-based Transverse and Longitudinal Bunch-by-Bunch Feedback System for the TLS

    International Nuclear Information System (INIS)

    Hu, K. H.; Kuo, C. H.; Lau, W. K.; Yeh, M. S.; Hsu, S. Y.; Chou, P. J.; Wang, M. H.; Lee, Demi; Chen, Jenny; Wang, C. J.; Hsu, K. T.; Kobayashi, K.; Nakamura, T.; Dehler, M.

    2006-01-01

    Multi-bunch instabilities deteriorate beam quality, increasing beam emittance, or even causing beam loss in the synchrotron light source. The feedback system is essential to suppress multi-bunch instabilities caused by the impedances of beam ducts, and trapped ions. A new FPGA based transverse and longitudinal bunch-by-bunch feedback system have been commissioned at the Taiwan Light Source recently, A single feedback loop is used to simultaneously suppress the horizontal and the vertical multi-bunch instabilities. Longitudinal instabilities caused by cavity-like structures are suppressed by the longitudinal feedback loop. The same FPGA processor is employed in the transverse feedback and the longitudinal feedback system respectively. Diagnostic memory is included in the system to capture the bunch oscillation signal, which supports various studies

  1. A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor.

    Science.gov (United States)

    Tayara, Hilal; Ham, Woonchul; Chong, Kil To

    2016-12-15

    This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation.

  2. Application of Integrated Verification Approach to FPGA-based Safety-Critical I and C System of Nuclear Power Plant

    Energy Technology Data Exchange (ETDEWEB)

    Ahmed, Ibrahim; Heo, Gyunyoung [Kyunghee Univ., Yongin (Korea, Republic of); Jung, Jaecheon [KEPCO, Ulsan (Korea, Republic of)

    2016-10-15

    Safety-critical instrumentation and control (I and C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. Generally in FPGA design verification, the designers make use of verification techniques by writing the test benches which involved various stages of verification activities of register-transfer level (RTL), gate-level, and place and route. Writing the test benches is considerably time consuming and require a lot of efforts to achieve a satisfied desire results. Furthermore, performing the verification at each stage is a major bottleneck and demanded much activities and time. In addition, verification is conceivably, the most difficult and complicated aspect of any design. Therefore, in view of these, this work applied an integrated verification approach to the verification of FPGA-based I and C system in NPP that simultaneously verified the whole design modules using MATLAB/Simulink HDL Co-simulation models. Verification is conceivably, the most difficult and complicated aspect of any design, and an FPGA design is not an exception. Therefore, in this work, we introduced and discussed how an application of integrated verification technique to the verification and testing of FPGA-based I and C system design in NPP can facilitate the verification processes, and verify the entire design modules of the system simultaneously using MATLAB/Simulink HDL co-simulation models. In conclusion, the results showed that, the integrated verification approach through MATLAB/Simulink models, if applied to any design to be verified, could speed up the design verification and reduce the V and V tasks.

  3. Application of Integrated Verification Approach to FPGA-based Safety-Critical I and C System of Nuclear Power Plant

    International Nuclear Information System (INIS)

    Ahmed, Ibrahim; Heo, Gyunyoung; Jung, Jaecheon

    2016-01-01

    Safety-critical instrumentation and control (I and C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. Generally in FPGA design verification, the designers make use of verification techniques by writing the test benches which involved various stages of verification activities of register-transfer level (RTL), gate-level, and place and route. Writing the test benches is considerably time consuming and require a lot of efforts to achieve a satisfied desire results. Furthermore, performing the verification at each stage is a major bottleneck and demanded much activities and time. In addition, verification is conceivably, the most difficult and complicated aspect of any design. Therefore, in view of these, this work applied an integrated verification approach to the verification of FPGA-based I and C system in NPP that simultaneously verified the whole design modules using MATLAB/Simulink HDL Co-simulation models. Verification is conceivably, the most difficult and complicated aspect of any design, and an FPGA design is not an exception. Therefore, in this work, we introduced and discussed how an application of integrated verification technique to the verification and testing of FPGA-based I and C system design in NPP can facilitate the verification processes, and verify the entire design modules of the system simultaneously using MATLAB/Simulink HDL co-simulation models. In conclusion, the results showed that, the integrated verification approach through MATLAB/Simulink models, if applied to any design to be verified, could speed up the design verification and reduce the V and V tasks

  4. Research on the design of surface acquisition system of active lap based on FPGA and FX2LP

    Science.gov (United States)

    Zhao, Hongshen; Li, Xiaojin; Fan, Bin; Zeng, Zhige

    2014-08-01

    In order to research the dynamic surface shape changes of active lap during the processing, this paper introduces a dynamic surface shape acquisition system of active lap using FPGA and USB communication. This system consists of high-precision micro-displacement sensor array, acquisition board, PC computer composition, and acquisition circuit board includes six sub-boards based on FPGA, a hub-board based on FPGA and USB communication. A sub-board is responsible for a number of independent channel sensors' data acquisition; hub-board is responsible for creating encoder simulation tools to active lap deformation control system with location information, sending synchronization information to latch the sensor data in all of the sub-boards for a time, while addressing the sub-boards to gather the sensor data in each sub-board one by one and transmitting all the sensor data together with location information via the USB chip FX2LP to the host computer. Experimental results show that the system is capable of fixing the location and speed of active lap, meanwhile the control of surface transforming and dynamic surface data acquisition at a certain location in the processing is implemented.

  5. High-speed real-time OFDM transmission based on FPGA

    Science.gov (United States)

    Xiao, Xin; Li, Fan; Yu, Jianjun

    2016-02-01

    In this paper, we review our recent research progresses on real-time orthogonal frequency division multiplexing (OFDM) transmission based on FPGA. We successfully demonstrated four-channel wavelength-division multiplexing (WDM) 256.51Gb/s 16-ary quadrature amplitude modulation (16QAM)-OFDM signal transmission system for short-reach optical amplifier free inter-connection with real-time reception. Four optical carriers are modulated by four different 16QAM-OFDM signals via 10G-class direct modulation lasers (DMLs). We achieved highest capacity real-time reception optical OFDM signal transmission over 2.4-km SMF with the bit-error ratio (BER) under soft-decision forward error correction (SD-FEC) limitation of 2.4×10-2. In order to achieve higher spectrum efficiency (SE), we demonstrate 4-channel high level QAM-OFDM transmission over 20-km SMF-28 with real-time reception. 58.72-Gb/s 256QAM-OFDM and 56.4-Gb/s 128QAM-OFDM signal transmission within 25-GHz grid is achieved with the BER under 2.4×10-2 and real-time reception.

  6. Design and realization of the real-time spectrograph controller for LAMOST based on FPGA

    Science.gov (United States)

    Wang, Jianing; Wu, Liyan; Zeng, Yizhong; Dai, Songxin; Hu, Zhongwen; Zhu, Yongtian; Wang, Lei; Wu, Zhen; Chen, Yi

    2008-08-01

    A large Schmitt reflector telescope, Large Sky Area Multi-Object Fiber Spectroscopic Telescope(LAMOST), is being built in China, which has effective aperture of 4 meters and can observe the spectra of as many as 4000 objects simultaneously. To fit such a large amount of observational objects, the dispersion part is composed of a set of 16 multipurpose fiber-fed double-beam Schmidt spectrographs, of which each has about ten of moveable components realtimely accommodated and manipulated by a controller. An industrial Ethernet network connects those 16 spectrograph controllers. The light from stars is fed to the entrance slits of the spectrographs with optical fibers. In this paper, we mainly introduce the design and realization of our real-time controller for the spectrograph, our design using the technique of System On Programmable Chip (SOPC) based on Field Programmable Gate Array (FPGA) and then realizing the control of the spectrographs through NIOSII Soft Core Embedded Processor. We seal the stepper motor controller as intellectual property (IP) cores and reuse it, greatly simplifying the design process and then shortening the development time. Under the embedded operating system μC/OS-II, a multi-tasks control program has been well written to realize the real-time control of the moveable parts of the spectrographs. At present, a number of such controllers have been applied in the spectrograph of LAMOST.

  7. An FPGA-based Sampling-ADC readout for the crystal barrel calorimeter

    Energy Technology Data Exchange (ETDEWEB)

    Muellers, Johannes [Helmholtz-Institut fuer Strahlen- und Kernphysik, Bonn (Germany); Marciniewski, Pawel [Angstroemlaboratoriet, Uppsala (Sweden); Collaboration: CBELSA/TAPS-Collaboration

    2016-07-01

    The CBELSA/TAPS experiment at the electron accelerator ELSA (Bonn) investigates the photoproduction of mesons off protons and neutrons. The Crystal Barrel Calorimeter has been upgraded replacing its photodiode readout by APDs, which allows the integration of the calorimeter into the first level trigger. Since the possible DAQ rate is currently limited by the digitization stage (LeCroy QDC1885F) to ∼ 2 kHz, the implementation of a new Sampling-ADC (SADC) readout is the second important step in the upgrade of the detector system. Based on the 64-channel PANDA-SADC, the design was modified, adapting it to the needs of the CBELSA/TAPS experiment. The CB-SADC offers 64 channels in one NIM module with up to 14 bit rate at 125 MHz, accompanied by a modular analog input stage and power supply. Data processing and reduction are realized with Kintex7 FPGAs. Readout is possible via gigabit ethernet links. Using an FPGA provides a multitude of possibilities for online feature extraction, such as the determination of the energy deposited in the crystal, TDC capabilities and pile-up detection and recovery. The SADC development is discussed, and first measurements performed in comparison to the presently used LeCroy QDC are presented.

  8. Speech Silicon: An FPGA Architecture for Real-Time Hidden Markov-Model-Based Speech Recognition

    Directory of Open Access Journals (Sweden)

    Schuster Jeffrey

    2006-01-01

    Full Text Available This paper examines the design of an FPGA-based system-on-a-chip capable of performing continuous speech recognition on medium sized vocabularies in real time. Through the creation of three dedicated pipelines, one for each of the major operations in the system, we were able to maximize the throughput of the system while simultaneously minimizing the number of pipeline stalls in the system. Further, by implementing a token-passing scheme between the later stages of the system, the complexity of the control was greatly reduced and the amount of active data present in the system at any time was minimized. Additionally, through in-depth analysis of the SPHINX 3 large vocabulary continuous speech recognition engine, we were able to design models that could be efficiently benchmarked against a known software platform. These results, combined with the ability to reprogram the system for different recognition tasks, serve to create a system capable of performing real-time speech recognition in a vast array of environments.

  9. Speech Silicon: An FPGA Architecture for Real-Time Hidden Markov-Model-Based Speech Recognition

    Directory of Open Access Journals (Sweden)

    Alex K. Jones

    2006-11-01

    Full Text Available This paper examines the design of an FPGA-based system-on-a-chip capable of performing continuous speech recognition on medium sized vocabularies in real time. Through the creation of three dedicated pipelines, one for each of the major operations in the system, we were able to maximize the throughput of the system while simultaneously minimizing the number of pipeline stalls in the system. Further, by implementing a token-passing scheme between the later stages of the system, the complexity of the control was greatly reduced and the amount of active data present in the system at any time was minimized. Additionally, through in-depth analysis of the SPHINX 3 large vocabulary continuous speech recognition engine, we were able to design models that could be efficiently benchmarked against a known software platform. These results, combined with the ability to reprogram the system for different recognition tasks, serve to create a system capable of performing real-time speech recognition in a vast array of environments.

  10. Design of an FPGA-based Radiation Tolerant Agent for Worldfip Fieldbus

    CERN Document Server

    Penacoba, G; Gousiou, E; Page, S; Palluel, J; Serrano, J; van der Bij, E

    2011-01-01

    CERN makes extensive use of the WorldFIP fieldbus interface in the LHC and other accelerators in the preinjectors chain. Following the decision of the provider of the components to stop the developments in this field and foreseeing the potential problems in the subsequent support, CERN decided to purchase the design information of these components and in-source the future developments using this technology. The first in-house design concerns a replacement for the MicroFIP chip whose last version was manufactured in an IC feature size found to be more vulnerable to radiation of high energy particles than the previous versions. NanoFIP is a CERN design based on a Flash FPGA implementing a subset of the functionality allowed by the communication standard, fitting the requirements of the different users and including the robustness against radiation as a design constraint. The development presented involved several groups at CERN working together in the framework of the Open Hardware Repository collaboration, and...

  11. Bio-inspired motion detection in an FPGA-based smart camera module

    International Nuclear Information System (INIS)

    Koehler, T; Roechter, F; Moeller, R; Lindemann, J P

    2009-01-01

    Flying insects, despite their relatively coarse vision and tiny nervous system, are capable of carrying out elegant and fast aerial manoeuvres. Studies of the fly visual system have shown that this is accomplished by the integration of signals from a large number of elementary motion detectors (EMDs) in just a few global flow detector cells. We developed an FPGA-based smart camera module with more than 10 000 single EMDs, which is closely modelled after insect motion-detection circuits with respect to overall architecture, resolution and inter-receptor spacing. Input to the EMD array is provided by a CMOS camera with a high frame rate. Designed as an adaptable solution for different engineering applications and as a testbed for biological models, the EMD detector type and parameters such as the EMD time constants, the motion-detection directions and the angle between correlated receptors are reconfigurable online. This allows a flexible and simultaneous detection of complex motion fields such as translation, rotation and looming, such that various tasks, e.g., obstacle avoidance, height/distance control or speed regulation can be performed by the same compact device

  12. The design of photoelectric signal processing system for a nuclear magnetic resonance gyroscope based on FPGA

    Science.gov (United States)

    Zhang, Xian; Zhou, Binquan; Li, Hong; Zhao, Xinghua; Mu, Weiwei; Wu, Wenfeng

    2017-10-01

    Navigation technology is crucial to the national defense and military, which can realize the measurement of orientation, positioning, attitude and speed for moving object. Inertial navigation is not only autonomous, real-time, continuous, hidden, undisturbed but also no time-limited and environment-limited. The gyroscope is the core component of the inertial navigation system, whose precision and size are the bottleneck of the performance. However, nuclear magnetic resonance gyroscope is characteristic of the advantage of high precision and small size. Nuclear magnetic resonance gyroscope can meet the urgent needs of high-tech weapons and equipment development of new generation. This paper mainly designs a set of photoelectric signal processing system for nuclear magnetic resonance gyroscope based on FPGA, which process and control the information of detecting laser .The photoelectric signal with high frequency carrier is demodulated by in-phase and quadrature demodulation method. Finally, the processing system of photoelectric signal can compensate the residual magnetism of the shielding barrel and provide the information of nuclear magnetic resonance gyroscope angular velocity.

  13. A Service-oriented FPGA-based 3D Model Acquisition System

    Directory of Open Access Journals (Sweden)

    MACHIDON, O. M.

    2015-11-01

    Full Text Available This paper proposes a non-contact, low cost 3D scanning solution using laser striping. The solution is composed of two main parts: the hardware setup - used for acquiring the object's 3D surface information, and the software part - that processes the information and obtains the 3D model representation of the object. We propose two major improvements over the traditional scanning solutions: the 3D information acquisition is based on a reconfigurable hardware platform - a Xilinx Spartan 6 FPGA - which adds flexibility and scalability to the scanning process, while the 3D model reconstruction is remotely available "as a Service", by the means of a web interface that abstracts away the complexity of the underlying processes and improves the performance, while granting easy sharing between users. By separating data capture process from the 3D model reconstruction tasks the system gains in portability - a feature that is absent for most existing solutions. The service-oriented approach brings on a performance gain, since the computational intensive tasks are handled by dedicated servers and ease of use of the system, because the user does not have to bother managing and using the software tools locally.

  14. Time of flight measurements based on FPGA using a breast dedicated PET

    International Nuclear Information System (INIS)

    Aguilar, A; García-Olcina, R; Martos, J; Soret, J; Torres, J; Benlloch, J M; González, A J; Sánchez, F

    2014-01-01

    In this work the implementation of a Time-to-Digital Converter (TDC) using a Nutt delay line FPGA-based and applied on a Positron Emission Tomography (PET) device is going to be presented in order to check the system's suitability for Time of Flight (TOF) measurements. In recent years, FPGAs have shown great advantages for precise time measurements in PET. The architecture employed for these measurements is described in detail. The system developed was tested on a dedicated breast PET prototype, composed of LYSO crystals and Positive Sensitive Photomultipliers (PSPMTs). Two distinct experiments were carried out for this purpose. In the first test, system linearity was evaluated in order to calibrate the time measurements, providing a linearity error of less than 2% and an average time resolution of 1.4 ns FWHM. The second set of measurements tested system resolution, resulting in a FWHM as good as 1.35 ns. The results suggest that the coincidence window for the current PET can be reduced in order to minimize the random events and thus, achieve better image quality

  15. FPGA-based fully digital fast power switch fault detection and compensation for three-phase shunt active filters

    Energy Technology Data Exchange (ETDEWEB)

    Karimi, S.; Saadate, S. [Groupe de Recherche en Electrotechnique et Electronique de Nancy, GREEN-UHP, CNRS UMR 7037 (France); Poure, P. [Laboratoire d' Instrumentation Electronique de Nancy, LIEN, EA 3440, France Nancy Universite - Universite Henri Poincare de Nancy I, BP 239, 54506 Vandoeuvre les Nancy cedex (France)

    2008-11-15

    This paper discusses the design, implementation, experimental validation and performances of a fully digital fast power switch fault detection and compensation for three-phase shunt active power filters. The approach introduced in this paper minimizes the time interval between the fault occurrence and its diagnosis. This paper demonstrates the possibility to detect a faulty switch of the active filter in less than 10 {mu}s by using simultaneously a ''time criterion'' and a ''voltage criterion''. In order to attain this fast detection time a FPGA (Field Programmable Gate Array) is used. The other feature introduced in this approach is that the control scheme used to compensate the current load harmonics and fault tolerant scheme are both programmed in only one FPGA. ''FPGA in the loop'' prototyping results and fully experimental results based on a real active power filter verify satisfactory performances of the proposed method. (author)

  16. The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments.

    Science.gov (United States)

    Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J; Madison, Kirk W

    2018-02-01

    In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

  17. The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments

    Science.gov (United States)

    Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J.; Madison, Kirk W.

    2018-02-01

    In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

  18. Design of the device of auto-measuring radon continuously based on FPGA

    International Nuclear Information System (INIS)

    Wang Yan; Shen Zhengqin; Chen Qiong

    2004-01-01

    This paper introduces the design of the device of auto-measuring radon continuously. The core of the system is the design of controlling system by FPGA, which consists of preset module, electrical calendar module and driving module. The system can automatically measure the consistence of the radon and the separating out rate of it. The information data is displayed by LCD. The high speed micro printer is used to print the measuring result. It adopts FPGA to design the measuring system of the device, which can improve the precision and stability of the system. (authors)

  19. Multi-camera synchronization core implemented on USB3 based FPGA platform

    Science.gov (United States)

    Sousa, Ricardo M.; Wäny, Martin; Santos, Pedro; Dias, Morgado

    2015-03-01

    Centered on Awaiba's NanEye CMOS image sensor family and a FPGA platform with USB3 interface, the aim of this paper is to demonstrate a new technique to synchronize up to 8 individual self-timed cameras with minimal error. Small form factor self-timed camera modules of 1 mm x 1 mm or smaller do not normally allow external synchronization. However, for stereo vision or 3D reconstruction with multiple cameras as well as for applications requiring pulsed illumination it is required to synchronize multiple cameras. In this work, the challenge of synchronizing multiple selftimed cameras with only 4 wire interface has been solved by adaptively regulating the power supply for each of the cameras. To that effect, a control core was created to constantly monitor the operating frequency of each camera by measuring the line period in each frame based on a well-defined sampling signal. The frequency is adjusted by varying the voltage level applied to the sensor based on the error between the measured line period and the desired line period. To ensure phase synchronization between frames, a Master-Slave interface was implemented. A single camera is defined as the Master, with its operating frequency being controlled directly through a PC based interface. The remaining cameras are setup in Slave mode and are interfaced directly with the Master camera control module. This enables the remaining cameras to monitor its line and frame period and adjust their own to achieve phase and frequency synchronization. The result of this work will allow the implementation of smaller than 3mm diameter 3D stereo vision equipment in medical endoscopic context, such as endoscopic surgical robotic or micro invasive surgery.

  20. FPGA-based multisensor real-time machine vision for banknote printing

    Science.gov (United States)

    Li, Rui; Türke, Thomas; Schaede, Johannes; Willeke, Harald; Lohweg, Volker

    2009-02-01

    Automatic sheet inspection in banknote production has been used as a standard quality control tool for more than a decade. As more and more print techniques and new security features are established, total quality in bank note printing must be guaranteed. This aspect has a direct impact on the research and development for bank note inspection systems in general in the sense of technological sustainability. It is accepted, that print defects are generated not only by printing parameter changes, but also by mechanical machine parameter changes, which will change unnoticed in production. Therefore, a new concept for a multi-sensory adaptive learning and classification model based on Fuzzy-Pattern- Classifiers for data inspection and machine conditioning is proposed. A general aim is to improve the known inspection techniques and propose an inspection methodology that can ensure a comprehensive quality control of the printed substrates processed by printing presses, especially printing presses which are designed to process substrates used in the course of the production of banknotes, security documents and others. Therefore, the research and development work in this area necessitates a change in concept for banknote inspection in general. In this paper a new generation of FPGA (Field Programmable Gate Array) based real time inspection technology is presented, which allows not only colour inspection on banknote sheets, but has also the implementation flexibility for various inspection algorithms for security features, such as window threads, embedded threads, OVDs, watermarks, screen printing etc., and multi-sensory data processing. A variety of algorithms is described in the paper, which are designed for and implemented on FPGAs. The focus is based on algorithmic approaches.

  1. A scalable FPGA-based digitizing platform for radiation data acquisition

    International Nuclear Information System (INIS)

    Schiffer, Randolph T.; Flaska, Marek; Pozzi, Sara A.; Carney, Sean; Wentzloff, David D.

    2011-01-01

    Regulating the proliferation of nuclear materials has become an important issue in our society. In order to detect the radiation given off by nuclear materials, systems implementing detectors connected to data processing modules have been developed. We have implemented a scalable, portable detection platform with a data processing module about the size of an external DVD drive. The data processing component of our system utilizes real-time data handling and has the potential for growth and behavior modifications through custom FPGA code editing. The size of our system is dynamic, so additional input channels can be implemented if necessary. This paper presents a scalable, portable detection system capable of transmitting streaming data from its inputs to a PC or laptop. The system also performs tail/total integral pulse shape discrimination (PSD) in real time on the FPGA to filter the data and selectively transmit pulses to a PC. The data arrives at the inputs of the data capturing module, is processed in real time by the onboard FPGA and is then transferred to a PC or laptop via a PCIe cord in discrete packets. The maximum transfer rate from the FPGA to the PC is 2000 MB/s. The Detection for Nuclear Non-Proliferation Group at University of Michigan will use the detection platform to achieve pre-processing of radiation data in real time. Such pre-processing includes PSD, pulse height distributions and particle times of arrival.

  2. FPGA Based Low Power DES Algorithm Design And Implementation using HTML Technology

    DEFF Research Database (Denmark)

    Thind, Vandana; Pandey, Bishwajeet; Kalia, Kartik

    2016-01-01

    In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL...

  3. OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

    Directory of Open Access Journals (Sweden)

    Hasitha Muthumala Waidyasooriya

    2017-01-01

    Full Text Available Finite difference time domain (FDTD method is a very poplar way of numerically solving partial differential equations. FDTD has a low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently, deeply pipelined FPGA accelerators have shown a lot of success by exploiting streaming data flows in FDTD computation. In spite of this success, many FPGA accelerators are not suitable for real-world applications that contain complex boundary conditions. Boundary conditions break the regularity of the data flow, so that the performances are significantly reduced. This paper proposes an FPGA accelerator that computes commonly used absorbing and periodic boundary conditions in many 3D FDTD applications. Accelerator is designed using a “C-like” programming language called OpenCL (open computing language. As a result, the proposed accelerator can be customized easily by changing the software code. According to the experimental results, we achieved over 3.3 times and 1.5 times higher processing speed compared to the CPUs and GPUs, respectively. Moreover, the proposed accelerator is more than 14 times faster compared to the recently proposed FPGA accelerators that are capable of handling complex boundary conditions.

  4. Pseudo Open Drain IO Standards Based Energy Efficient Solar Charge Sensor Design on 20nm FPGA

    DEFF Research Database (Denmark)

    Kalia, K; Pandey, B; Nanda, K

    2015-01-01

    solar charge inverter. We also observed maximum total power reduction in LVCMOS18 (Artix-7 FPGA) as compared to other I/O standards at 10 GHz. Also there is maximum total power reduction in POD12 (Ultra Scale Kintex) as compared to other I/O standards at 2 GHz. There is also a significant change...

  5. FPGA Based Efficient Design of Traffic Light Controller using Frequency Scaling for Family of HSTL

    DEFF Research Database (Denmark)

    Sharma, Shivani; Khan, Sadiq; Das, Bhagwan

    2016-01-01

    utilizes least amount of power and is well tested in hardware using Xilinx Virtex6 Field Programmable gate array. FPGA designs are not only cheaper than ASIC designs but have many positive features like speed and performance. So the factors that contribute to power consumption for family of HSTL...

  6. Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA

    DEFF Research Database (Denmark)

    Saini, Rishita; Bansal, Neha; Bansal, Meenakshi

    2015-01-01

    Thermal aware design is currently gaining importance in VLSI research domain. In this work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA. Ambient Temperature, airflow, and heat sink profile play a significant role in thermal aware hardware design life cycle. Ambient...

  7. LVTTL Based Energy Efficient Watermark Generator Design and Implementation on FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Kaur, Amanpreet; Kumar, Tanesh

    2014-01-01

    -transistor logic (LVTTL) IO standard is used in this design to make it power optimized. This design is implemented on Kintex-7 FPGA, Device XC7K70T and -3 speed grades. When we are scaling the device operating frequency from 100GHz to 5GHz, there is 94.93% saving in total power of the watermark generator...

  8. FPGA-based GEM detector signal acquisition for SXR spectroscopy system

    Science.gov (United States)

    Wojenski, A.; Pozniak, K. T.; Kasprowicz, G.; Kolasinski, P.; Krawczyk, R.; Zabolotny, W.; Chernyshova, M.; Czarski, T.; Malinowski, K.

    2016-11-01

    The presented work is related to the Gas Electron Multiplier (GEM) detector soft X-ray spectroscopy system for tokamak applications. The used GEM detector has one-dimensional, 128 channel readout structure. The channels are connected to the radiation-hard electronics with configurable analog stage and fast ADCs, supporting speeds of 125 MSPS for each channel. The digitalized data is sent directly to the FPGAs using fast serial links. The preprocessing algorithms are implemented in the FPGAs, with the data buffering made in the on-board 2Gb DDR3 memory chips. After the algorithmic stage, the data is sent to the Intel Xeon-based PC for further postprocessing using PCI-Express link Gen 2. For connection of multiple FPGAs, PCI-Express switch 8-to-1 was designed. The whole system can support up to 2048 analog channels. The scope of the work is an FPGA-based implementation of the recorder of the raw signal from GEM detector. Since the system will work in a very challenging environment (neutron radiation, intense electro-magnetic fields), the registered signals from the GEM detector can be corrupted. In the case of the very intense hot plasma radiation (e.g. laser generated plasma), the registered signals can overlap. Therefore, it is valuable to register the raw signals from the GEM detector with high number of events during soft X-ray radiation. The signal analysis will have the direct impact on the implementation of photon energy computation algorithms. As the result, the system will produce energy spectra and topological distribution of soft X-ray radiation. The advanced software was developed in order to perform complex system startup and monitoring of hardware units. Using the array of two one-dimensional GEM detectors it will be possible to perform tomographic reconstruction of plasma impurities radiation in the SXR region.

  9. FPGA based control system for -100 kV, 25 A Crowbarless DC power supply

    International Nuclear Information System (INIS)

    Upadhyay, R.; Tripathi, A.; Badapanda, M.K.; Lad, M.

    2015-01-01

    FPGA based digital control system has been developed for -100 kV, 25 A solid state modular crowbarless DC klystron bias power supply of 1 MW, 352.2 MHz RF test stand. The control system has capability to operate this power supply either in CW or pulse mode. Central controller, PSM controller and graphical user interface are key parts of this control system. Central controller monitors the status of various subsystems of this power supply like 11 kV step start unit, four numbers of main transformers each having 44 numbers of secondary windings and 176 numbers of switch power modules for deciding the number of power modules to be put ON and their duty cycles depending on the set output voltage and current. PSM controller sends appropriate control signal to the switch power modules through fibre optic lines and communicates it to the central controller. Linux based graphical user interface has been developed which enables the user to set the operating parameters along with their trip limits and displays the information of critical parameters of this power supply on a local touch screen panel. Provision for remote control and supervision is also provided through a separate PC connected to the main control system via Ethernet. The control system has capability to trip the power supply within 5 μsec in case any parameter exceeds its set limit. Suitable data logging feature is incorporated for offline fault analysis. The control system architecture along with its software protection interlocks are presented in this paper. The performance of the control system has been verified during operation of -100 kV, 25 A DC power supply with 1 MW, 352.2 MHz klystron amplifier. (author)

  10. Artificial Neural Network-Based Monitoring of the Fuel Assembly Temperature Sensor and FPGA Implementation

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2015-07-01

    Numerous methods have been developed around the world to model the dynamic behavior and detect a faulty operating mode of a temperature sensor. In this context, we present in this study a new method based on the dependence between the fuel assembly temperature profile on control rods positions, and the coolant flow rate in a nuclear reactor. This seems to be possible since the insertion of control rods at different axial positions and variations in flow rate of the reactor coolant results in different produced thermal power in the reactor. This is closely linked to the instant fuel rod temperature profile. In a first step, we selected parameters to be used and confirmed the adequate correlation between the chosen parameters and those to be estimated by the proposed monitoring system. In the next step, we acquired and de-noised the data of corresponding parameters, the qualified data is then used to design and train the artificial neural network. The effective data denoising was done by using the wavelet transform to remove a various kind of artifacts such as inherent noise. With the suitable choice of wavelet level and smoothing method, it was possible for us to remove all the non-required artifacts with a view to verify and analyze the considered signal. In our work, several potential mother wavelet functions (Haar, Daubechies, Bi-orthogonal, Reverse Bi-orthogonal, Discrete Meyer and Symlets) were investigated to find the most similar function with the being processed signals. To implement the proposed monitoring system for the fuel rod temperature sensor (03 wire RTD sensor), we used the Bayesian artificial neural network 'BNN' technique to model the dynamic behavior of the considered sensor, the system correlate the estimated values with the measured for the concretization of the proposed system we propose an FPGA (field programmable gate array) implementation. The monitoring system use the correlation. (authors)

  11. FPGA-based distributed computing microarchitecture for complex physical dynamics investigation.

    Science.gov (United States)

    Borgese, Gianluca; Pace, Calogero; Pantano, Pietro; Bilotta, Eleonora

    2013-09-01

    In this paper, we present a distributed computing system, called DCMARK, aimed at solving partial differential equations at the basis of many investigation fields, such as solid state physics, nuclear physics, and plasma physics. This distributed architecture is based on the cellular neural network paradigm, which allows us to divide the differential equation system solving into many parallel integration operations to be executed by a custom multiprocessor system. We push the number of processors to the limit of one processor for each equation. In order to test the present idea, we choose to implement DCMARK on a single FPGA, designing the single processor in order to minimize its hardware requirements and to obtain a large number of easily interconnected processors. This approach is particularly suited to study the properties of 1-, 2- and 3-D locally interconnected dynamical systems. In order to test the computing platform, we implement a 200 cells, Korteweg-de Vries (KdV) equation solver and perform a comparison between simulations conducted on a high performance PC and on our system. Since our distributed architecture takes a constant computing time to solve the equation system, independently of the number of dynamical elements (cells) of the CNN array, it allows us to reduce the elaboration time more than other similar systems in the literature. To ensure a high level of reconfigurability, we design a compact system on programmable chip managed by a softcore processor, which controls the fast data/control communication between our system and a PC Host. An intuitively graphical user interface allows us to change the calculation parameters and plot the results.

  12. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    CERN Document Server

    Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

    2013-01-01

    The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

  13. Fuzzy logic type 1 and type 2 based on LabVIEW FPGA

    CERN Document Server

    Ponce-Cruz, Pedro; MacCleery, Brian

    2016-01-01

    This book is a comprehensive introduction to LabVIEW FPGA™, a package allowing the programming of intelligent digital controllers in field programmable gate arrays (FPGAs) using graphical code. It shows how both potential difficulties with understanding and programming in VHDL and the consequent difficulty and slowness of implementation can be sidestepped. The text includes a clear theoretical explanation of fuzzy logic (type 1 and type 2) with case studies that implement the theory and systematically demonstrate the implementation process. It goes on to describe basic and advanced levels of programming LabVIEW FPGA and show how implementation of fuzzy-logic control in FPGAs improves system responses. A complete toolkit for implementing fuzzy controllers in LabVIEW FPGA has been developed with the book so that readers can generate new fuzzy controllers and deploy them immediately. Problems and their solutions allow readers to practice the techniques and to absorb the theoretical ideas as they arise. Fuzzy L...

  14. FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

    International Nuclear Information System (INIS)

    Messai, A.; Mellit, A.; Massi Pavan, A.; Guessoum, A.; Mekki, H.

    2011-01-01

    Research highlights: → FL-MPPT controller is implemented on FPGA. → Results obtained with ModelSim show a satisfactory performance. → Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

  15. An FPGA Based Multiprocessing CPU for Beam Synchronous Timing in CERN's SPS and LHC

    CERN Document Server

    Ballester, F J; Gras, J J; Lewis, J; Savioz, J J; Serrano, J

    2003-01-01

    The Beam Synchronous Timing system (BST) will be used around the LHC and its injector, the SPS, to broadcast timing meassages and synchronize actions with the beam in different receivers. To achieve beam synchronization, the BST Master card encodes messages using the bunch clock, with a nominal value of 40.079 MHz for the LHC. These messages are produced by a set of tasks every revolution period, which is every 89 us for the LHC and every 23 us for the SPS, therefore imposing a hard real-time constraint on the system. To achieve determinism, the BST Master uses a dedicated CPU inside its main Field Programmable Gate Array (FPGA) featuring zero-delay hardware task switching and a reduced instruction set. This paper describes the BST Master card, stressing the main FPGA design, as well as the associated software, including the LynxOS driver and the tailor-made assembler.

  16. FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

    Energy Technology Data Exchange (ETDEWEB)

    Messai, A. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mellit, A., E-mail: a.mellit@yahoo.co.u [Department of Electronics, Faculty of Sciences and Technology, Jijel University, Ouled-aissa, P.O. Box 98, Jijel 18000 (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Massi Pavan, A. [Department of Materials and Natural Resources, University of Trieste, Via A. Valerio, 2 - 34127 Trieste (Italy); Guessoum, A. [Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mekki, H. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria)

    2011-07-15

    Research highlights: {yields} FL-MPPT controller is implemented on FPGA. {yields} Results obtained with ModelSim show a satisfactory performance. {yields} Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

  17. Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

    Science.gov (United States)

    Asaad, Sameh W.; Kapur, Mohit

    2016-03-15

    A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

  18. An FPGA-based bolometer for the MAST-U Super-X divertor

    Energy Technology Data Exchange (ETDEWEB)

    Lovell, Jack, E-mail: jack.lovell@durham.ac.uk [Durham University, South Road, Durham DH1 3LE (United Kingdom); Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Naylor, Graham; Field, Anthony [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Drewelow, Peter [MPI für Plasmaphysik, Greifswald (Germany); Sharples, Ray [Durham University, South Road, Durham DH1 3LE (United Kingdom); Collaboration: EUROfusion Consortium, JET, Culham Science Centre, Abingdon OX14 3DB (United Kingdom)

    2016-11-15

    A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of the JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.

  19. FPGA-based algorithms for the new trigger system for the phase 2 upgrade of the CMS drift tubes detector

    International Nuclear Information System (INIS)

    Cela-Ruiz, J.-M.

    2017-01-01

    The new luminosity conditions imposed after the LHC upgrade will require a dedicated upgrade of several subdetectors. To cope with the new requirements, CMS drift tubes subdetector electronics will be redesigned in order to achieve the new foreseen response speed. In particular, it is necessary to enhance the first stage of the trigger system (L1A). In this document we present the development of a software algorithm, based on the mean timer paradigm, capable of reconstructing muon trajectories and rejecting spurious signals. It has been initially written in C++ programming language, but designed with its portability to a FPGA VHDL code in mind.

  20. FPGA-based fused smart-sensor for tool-wear area quantitative estimation in CNC machine inserts.

    Science.gov (United States)

    Trejo-Hernandez, Miguel; Osornio-Rios, Roque Alfredo; de Jesus Romero-Troncoso, Rene; Rodriguez-Donate, Carlos; Dominguez-Gonzalez, Aurelio; Herrera-Ruiz, Gilberto

    2010-01-01

    Manufacturing processes are of great relevance nowadays, when there is a constant claim for better productivity with high quality at low cost. The contribution of this work is the development of a fused smart-sensor, based on FPGA to improve the online quantitative estimation of flank-wear area in CNC machine inserts from the information provided by two primary sensors: the monitoring current output of a servoamplifier, and a 3-axis accelerometer. Results from experimentation show that the fusion of both parameters makes it possible to obtain three times better accuracy when compared with the accuracy obtained from current and vibration signals, individually used.

  1. An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment

    Science.gov (United States)

    Mandal, Swagata; Saini, Jogender; Zabołotny, Wojciech M.; Sau, Suman; Chakrabarti, Amlan; Chattopadhyay, Subhasis

    2017-03-01

    Due to the dramatic increase of data volume in modern high energy physics (HEP) experiments, a robust high-speed data acquisition (DAQ) system is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta, or neutron. Hence, a major challenge in the development of DAQ in the HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here, we have implemented the DAQ using field-programmable gate array (FPGA) due to some of its inherent advantages over the application-specific integrated circuit. A novel orthogonal concatenated code and cyclic redundancy check (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with a 32-b CRC has been used against error in the configuration memory of FPGA. Data from front-end sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate, efficiency, and robustness to radiation.

  2. Design and FPGA Implementation of Variable Cutoff Frequency Filter based on Continuously Variable Fractional Delay Structure and Interpolation Technique

    Directory of Open Access Journals (Sweden)

    Sumedh Dhabu

    2015-09-01

    Full Text Available This paper presents the design and FPGA implementation of interpolated continuously variable fractional delay structure based filter (ICVFD filter with fine control over the cutoff frequency. In the ICVFD filter, each unit delay of the prototype lowpass filter is replaced by a continuously variable fractional delay (CVFD element proposed in this paper. The CVFD element requires the same number of multiplications as that of the second-order fractional delay structure used in the existing fractional delay structure based variable filter (FDS based filter, however it provides fractional delays corresponding to the higher-order fractional delay structures. Hence, the proposed ICVFD filter provides wider cutoff frequency range compared to the FDS based filter. The ICVFD filter is also capable of providing variable bandpass and highpass responses. We use two-stage approach for the FPGA implementation of the ICVFD filter. First, we use pipelining stages to shorten the critical path and improve the operating frequency. Then, we make use of specific hardware resource, i.e. RAM-based Shift Register (SRL to further improve the operating frequency and resource usage.

  3. FPGA BASED ASYNCHRONOUS PIPELINED MB-OFDM UWB TRANSMITTER BACKEND MODULES

    Directory of Open Access Journals (Sweden)

    M. Santhi

    2010-03-01

    Full Text Available In this paper, a novel scheme is proposed which comprises the advantages of asynchronous pipelining techniques and the advantages of FPGAs for implementing a 200Mbps MB-OFDM UWB transmitter digital backend modules. In asynchronous pipelined system, registers are used as in synchronous system. But they are controlled by handshaking signals. Since FPGAs are rich in registers, design and implementation of asynchronous pipelined MBOFDM UWB transmitter on FPGA using four-phase bundled-data protocol is considered in this paper. Novel ideas have also been proposed for designing asynchronous OFDM using Modified Radix-24 SDF and asynchronous interleaver using two RAM banks. Implementation has been performed on ALTERA STRATIX II EP2S60F1020C4 FPGA and it is operating at a speed of 350MHz. It is assured that the proposed MB-OFDM UWB system can be made to work on STRATIX III device with the operating frequency of 528MHz in compliance to the ECMA-368 standard. The proposed scheme is also applicable for FPGA from other vendors and ASIC.

  4. Labview applications based on field programmable gate array (FPGA) on temperature measurement system of heating-02

    International Nuclear Information System (INIS)

    Kussigit Santosa

    2013-01-01

    Temperature measurements system has been created at the heating-02 test using LabVIEW 2011 software. Making this measurement systems on FPGA is the development of previous a measurement system using the measurement with cDAQ9188. The advantage of this system is the independence of the system means that the execution time can run itself without a computer. The scope of the current study was limited on the development, programming and testing of data acquisition focused on programming of the FPGA modules that have been embedded on the cRIO 9074. In the making of temperature measurement systems is required the data acquisition system by National Texas Instruments cRIO 9074 module, power supply, Ni 9023 module, 7011 HIOKI current source, the software Labview 2011 and the computer. The using method is stringing the temperature measurement system, programming of data acquisition the FPGA as well as the acquisition system interface that is easy to do observations. From the experimental results, it can be concluded that the temperature measurement system can run well. So that the measurement system is expected to be used for the actual measurement. (author)

  5. FPGA based phase detection technique for electron density measurement in SST-1 tokamak

    International Nuclear Information System (INIS)

    Pramila; Mandaliya, Hitesh; Rajpal, Rachana; Kaur, Rajwinder

    2016-01-01

    A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper.

  6. Hazard Analysis of Software Requirements Specification for Process Module of FPGA-based Controllers in NPP

    Energy Technology Data Exchange (ETDEWEB)

    Jung; Sejin; Kim, Eui-Sub; Yoo, Junbeom [Konkuk University, Seoul (Korea, Republic of); Keum, Jong Yong; Lee, Jang-Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2016-10-15

    Software in PLC, FPGA which are used to develop I and C system also should be analyzed to hazards and risks before used. NUREG/CR-6430 proposes the method for performing software hazard analysis. It suggests analysis technique for software affected hazards and it reveals that software hazard analysis should be performed with the aspects of software life cycle such as requirements analysis, design, detailed design, implements. It also provides the guide phrases for applying software hazard analysis. HAZOP (Hazard and operability analysis) is one of the analysis technique which is introduced in NUREG/CR-6430 and it is useful technique to use guide phrases. HAZOP is sometimes used to analyze the safety of software. Analysis method of NUREG/CR-6430 had been used in Korea nuclear power plant software for PLC development. Appropriate guide phrases and analysis process are selected to apply efficiently and NUREG/CR-6430 provides applicable methods for software hazard analysis is identified in these researches. We perform software hazard analysis of FPGA software requirements specification with two approaches which are NUREG/CR-6430 and HAZOP with using general GW. We also perform the comparative analysis with them. NUREG/CR-6430 approach has several pros and cons comparing with the HAZOP with general guide words and approach. It is enough applicable to analyze the software requirements specification of FPGA.

  7. FPGA based phase detection technique for electron density measurement in SST-1 tokamak

    Energy Technology Data Exchange (ETDEWEB)

    Pramila, E-mail: pramila@ipr.res.in; Mandaliya, Hitesh; Rajpal, Rachana; Kaur, Rajwinder

    2016-11-15

    A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper.

  8. High speed fault tolerant secure communication for muon chamber using FPGA based GBTx emulator

    Science.gov (United States)

    Sau, Suman; Mandal, Swagata; Saini, Jogender; Chakrabarti, Amlan; Chattopadhyay, Subhasis

    2015-12-01

    The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at the GSI. The CBM experiment will investigate the highly compressed nuclear matter using nucleus-nucleus collisions. This experiment will examine lieavy-ion collisions in fixed target geometry and will be able to measure hadrons, electrons and muons. CBM requires precise time synchronization, compact hardware, radiation tolerance, self-triggered front-end electronics, efficient data aggregation schemes and capability to handle high data rate (up to several TB/s). As a part of the implementation of read out chain of Muon Cliamber(MUCH) [1] in India, we have tried to implement FPGA based emulator of GBTx in India. GBTx is a radiation tolerant ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics (HEP) experiments and is developed by CERN. GBTx will be used in highly irradiated area and more prone to be affected by multi bit error. To mitigate this effect instead of single bit error correcting RS code we have used two bit error correcting (15, 7) BCH code. It will increase the redundancy which in turn increases the reliability of the coded data. So the coded data will be less prone to be affected by noise due to radiation. The data will go from detector to PC through multiple nodes through the communication channel. The computing resources are connected to a network which can be accessed by authorized person to prevent unauthorized data access which might happen by compromising the network security. Thus data encryption is essential. In order to make the data communication secure, advanced encryption standard [2] (AES - a symmetric key cryptography) and RSA [3], [4] (asymmetric key cryptography) are used after the channel coding. We have implemented GBTx emulator on two Xilinx Kintex-7 boards (KC705). One will act as transmitter and other will act as receiver and they are connected

  9. High speed fault tolerant secure communication for muon chamber using FPGA based GBTx emulator

    International Nuclear Information System (INIS)

    Sau, Suman; Chakrabarti, Amlan; Saini, Jogender; Chattopadhyay, Subhasis; Mandal, Swagata

    2015-01-01

    The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at the GSI. The CBM experiment will investigate the highly compressed nuclear matter using nucleus-nucleus collisions. This experiment will examine lieavy-ion collisions in fixed target geometry and will be able to measure hadrons, electrons and muons. CBM requires precise time synchronization, compact hardware, radiation tolerance, self-triggered front-end electronics, efficient data aggregation schemes and capability to handle high data rate (up to several TB/s). As a part of the implementation of read out chain of Muon Cliamber(MUCH) [1] in India, we have tried to implement FPGA based emulator of GBTx in India. GBTx is a radiation tolerant ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics (HEP) experiments and is developed by CERN. GBTx will be used in highly irradiated area and more prone to be affected by multi bit error. To mitigate this effect instead of single bit error correcting RS code we have used two bit error correcting (15, 7) BCH code. It will increase the redundancy which in turn increases the reliability of the coded data. So the coded data will be less prone to be affected by noise due to radiation. The data will go from detector to PC through multiple nodes through the communication channel. The computing resources are connected to a network which can be accessed by authorized person to prevent unauthorized data access which might happen by compromising the network security. Thus data encryption is essential. In order to make the data communication secure, advanced encryption standard [2] (AES - a symmetric key cryptography) and RSA [3], [4] (asymmetric key cryptography) are used after the channel coding. We have implemented GBTx emulator on two Xilinx Kintex-7 boards (KC705). One will act as transmitter and other will act as receiver and they are connected

  10. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    International Nuclear Information System (INIS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Cicero, F. Lo; Lonardo, A; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Simula, F.; Tosoratto, L.; Vicini, P.; Rossetti, D.

    2015-01-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology.The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network.The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols.Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design. (paper)

  11. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    Science.gov (United States)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

    2015-12-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

  12. A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System.

    Science.gov (United States)

    Zhang, Zhen; Ma, Cheng; Zhu, Rong

    2017-08-23

    Artificial Neural Networks (ANNs), including Deep Neural Networks (DNNs), have become the state-of-the-art methods in machine learning and achieved amazing success in speech recognition, visual object recognition, and many other domains. There are several hardware platforms for developing accelerated implementation of ANN models. Since Field Programmable Gate Array (FPGA) architectures are flexible and can provide high performance per watt of power consumption, they have drawn a number of applications from scientists. In this paper, we propose a FPGA-based, granularity-variable neuromorphic processor (FBGVNP). The traits of FBGVNP can be summarized as granularity variability, scalability, integrated computing, and addressing ability: first, the number of neurons is variable rather than constant in one core; second, the multi-core network scale can be extended in various forms; third, the neuron addressing and computing processes are executed simultaneously. These make the processor more flexible and better suited for different applications. Moreover, a neural network-based controller is mapped to FBGVNP and applied in a multi-input, multi-output, (MIMO) real-time, temperature-sensing and control system. Experiments validate the effectiveness of the neuromorphic processor. The FBGVNP provides a new scheme for building ANNs, which is flexible, highly energy-efficient, and can be applied in many areas.

  13. A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System

    Directory of Open Access Journals (Sweden)

    Zhen Zhang

    2017-08-01

    Full Text Available Artificial Neural Networks (ANNs, including Deep Neural Networks (DNNs, have become the state-of-the-art methods in machine learning and achieved amazing success in speech recognition, visual object recognition, and many other domains. There are several hardware platforms for developing accelerated implementation of ANN models. Since Field Programmable Gate Array (FPGA architectures are flexible and can provide high performance per watt of power consumption, they have drawn a number of applications from scientists. In this paper, we propose a FPGA-based, granularity-variable neuromorphic processor (FBGVNP. The traits of FBGVNP can be summarized as granularity variability, scalability, integrated computing, and addressing ability: first, the number of neurons is variable rather than constant in one core; second, the multi-core network scale can be extended in various forms; third, the neuron addressing and computing processes are executed simultaneously. These make the processor more flexible and better suited for different applications. Moreover, a neural network-based controller is mapped to FBGVNP and applied in a multi-input, multi-output, (MIMO real-time, temperature-sensing and control system. Experiments validate the effectiveness of the neuromorphic processor. The FBGVNP provides a new scheme for building ANNs, which is flexible, highly energy-efficient, and can be applied in many areas.

  14. Architectural design for a low cost FPGA-based traffic signal detection system in vehicles

    Science.gov (United States)

    López, Ignacio; Salvador, Rubén; Alarcón, Jaime; Moreno, Félix

    2007-05-01

    In this paper we propose an architecture for an embedded traffic signal detection system. Development of Advanced Driver Assistance Systems (ADAS) is one of the major trends of research in automotion nowadays. Examples of past and ongoing projects in the field are CHAMELEON ("Pre-Crash Application all around the vehicle" IST 1999-10108), PREVENT (Preventive and Active Safety Applications, FP6-507075, http://www.prevent-ip.org/) and AVRT in the US (Advanced Vision-Radar Threat Detection (AVRT): A Pre-Crash Detection and Active Safety System). It can be observed a major interest in systems for real-time analysis of complex driving scenarios, evaluating risk and anticipating collisions. The system will use a low cost CCD camera on the dashboard facing the road. The images will be processed by an Altera Cyclone family FPGA. The board does median and Sobel filtering of the incoming frames at PAL rate, and analyzes them for several categories of signals. The result is conveyed to the driver. The scarce resources provided by the hardware require an architecture developed for optimal use. The system will use a combination of neural networks and an adapted blackboard architecture. Several neural networks will be used in sequence for image analysis, by reconfiguring a single, generic hardware neural network in the FPGA. This generic network is optimized for speed, in order to admit several executions within the frame rate. The sequence will follow the execution cycle of the blackboard architecture. The global, blackboard architecture being developed and the hardware architecture for the generic, reconfigurable FPGA perceptron will be explained in this paper. The project is still at an early stage. However, some hardware implementation results are already available and will be offered in the paper.

  15. FPGA based Fuzzy Logic Controller for plasma position control in ADITYA Tokamak

    International Nuclear Information System (INIS)

    Suratia, Pooja; Patel, Jigneshkumar; Rajpal, Rachana; Kotia, Sorum; Govindarajan, J.

    2012-01-01

    Highlights: ► Evaluation and comparison of the working performance of FLC is done with that of PID Controller. ► FLC is designed using MATLAB Fuzzy Logic Toolbox, and validated on ADITYA RZIP model. ► FLC was implemented on a FPGA. The close-loop testing is done by interfacing FPGA to MATLAB/Simulink. ► Developed FLC controller is able to maintain the plasma column within required range of ±0.05 m and was found to give robust control against various disturbances and faster and smoother response compared to PID Controller. - Abstract: Tokamaks are the most promising devices for obtaining nuclear fusion energy from high-temperature, ionized gas termed as Plasma. The successful operation of tokamak depends on its ability to confine plasma at the geometric center of vacuum vessel with sufficient stability. The quality of plasma discharge in ADITYA Tokamak is strongly related to the radial position of the plasma column in the vacuum vessel. If the plasma column approaches too near to the wall of vacuum vessel, it leads to minor or complete disruption of plasma. Hence the control of plasma position throughout the entire plasma discharge duration is a fundamental requirement. This paper describes Fuzzy Logic Controller (FLC) which is designed for radial plasma position control. This controller is tested and evaluated on the ADITYA RZIP control model. The performance of this FLC was compared with that of Proportional–Integral–Derivative (PID) Controller and the response was found to be faster and smoother. FLC was implemented on a Field Programmable Gate Array (FPGA) chip with the use of a Very High-Speed Integrated-Circuits Hardware Description-Language (VHDL).

  16. FPGA-based quench detection system for super-FRS super-ferric dipole prototype

    International Nuclear Information System (INIS)

    Yang Tongjun; Wu Wei; Yao Qinggao; Yuan Ping; He Yuan; Han Shaofei; Ma Lizhen

    2011-01-01

    The quench detection system for Super-FRS super-ferric dipole prototype magnet of FAIR has been designed and built. The balance bridge was used to detect quench signal. In order to avoid blind zone of quench detection, two independent bridges were used. NI PXI-7830R FPGA was used to implement filter to quench signal and algorithm of quench decision and to produce quench trigger signal. Pre-sample technique was used in quench data acquisition. The data before and after quench could be recorded for analysis later. The test result indicated that the quench of the dipole's superconducting coil could be reliably detected by the quench detection module. (authors)

  17. FPGA-based Bit-Error-Rate Tester for SEU-hardened Optical Links

    CERN Document Server

    Detraz, S; Moreira, P; Papadopoulos, S; Papakonstantinou, I; Seif El Nasr, S; Sigaud, C; Soos, C; Stejskal, P; Troska, J; Versmissen, H

    2009-01-01

    The next generation of optical links for future High-Energy Physics experiments will require components qualified for use in radiation-hard environments. To cope with radiation induced single-event upsets, the physical layer protocol will include Forward Error Correction (FEC). Bit-Error-Rate (BER) testing is a widely used method to characterize digital transmission systems. In order to measure the BER with and without the proposed FEC, simultaneously on several devices, a multi-channel BER tester has been developed. This paper describes the architecture of the tester, its implementation in a Xilinx Virtex-5 FPGA device and discusses the experimental results.

  18. SSTL I/O Standard Based Arithmetic Circuits Design on FPGA

    DEFF Research Database (Denmark)

    Goswami, Kavita; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar

    2016-01-01

    -Tiryagbhyam”. SSTL135_R is minimum I/O power consumer. SSTL135_DCI is maximum power consumer. When we use SSTL135_R in place of SSTL12, SSTL12_DCI, SSTL15, and SSTL135_DCI, there is 42.5%, 82.7%, 28.12%, and 72.9% reduction in I/O power at 21oC, 40oC, 53.5oC and 56.7oC. This design is implemented on Artix-7 FPGA...

  19. Timing Constraints Based High Performance Des Design And Implementation On 28nm FPGA

    DEFF Research Database (Denmark)

    Thind, Vandana; Pandey, Sujeet; Hussain, Dil muhammed Akbar

    2018-01-01

    in this work, we are going to implement DES Algorithm on 28nm Artix-7 FPGA. To achieve high performance design goal, we are using minimum period, maximum frequency, minimum low pulse, minimum high pulse for different cases of worst case slack, maximum delay, setup time, hold time and data skew path....... The cases on which analysis is done are like worst case slack, best case achievable, timing error and timing score, which help in differentiating the amount of timing constraint at two different frequencies. We analyzed that in timing analysis there is maximum of 19.56% of variation in worst case slack, 0...

  20. Design of an Oximeter Based on LED-LED Configuration and FPGA Technology

    OpenAIRE

    Stojanovic, Radovan; Karadaglic, Dejan

    2013-01-01

    A fully digital photoplethysmographic (PPG) sensor and actuator has been developed. The sensing circuit uses one Light Emitting Diode (LED) for emitting light into human tissue and one LED for detecting the reflectance light from human tissue. A Field Programmable Gate Array (FPGA) is used to control the LEDs and determine the PPG and Blood Oxygen Saturation (SpO2). The configurations with two LEDs and four LEDs are developed for measuring PPG signal and Blood Oxygen Saturation (SpO2). N-LEDs...

  1. Potential improvement of CANDU NPP safety margins by shortening the response time of shutdown systems using FPGA based implementation

    Energy Technology Data Exchange (ETDEWEB)

    Jingke She, E-mail: jshe2@uwo.ca [Department of Electrical and Computer Engineering, University of Western Ontario, London, Ontario N6A 5B9 (Canada); Jin Jiang, E-mail: jjiang@eng.uwo.ca [Department of Electrical and Computer Engineering, University of Western Ontario, London, Ontario N6A 5B9 (Canada)

    2012-03-15

    Highlights: Black-Right-Pointing-Pointer Quantitative analysis of the safety margin improvement through thermalhydraulic simulation and analysis. Black-Right-Pointing-Pointer Hardware-in-the-loop simulation of realizing the improvement by an FPGA-based SDS1. Black-Right-Pointing-Pointer Verification of potential operating power upgrade without endangering the plant safety. - Abstract: The relationship between the peak values of critical reactor variables, such as neutronic power, inside a CANDU reactor and the speed of the response of its shutdown system has been analyzed in the event of a large loss of coolant accident (LOCA). The advantage of shortening the response time of the shutdown action has been demonstrated in term of the improved safety margin. A field programmable gate array (FPGA) platform has been chosen to implement such a shutdown system. Hardware-in-the-loop (HIL) simulations have been performed to demonstrate the feasibility of this concept. Furthermore, connections between the speed of response of the shutdown system and the nominal operating power level of the reactor have been drawn to support for potential power upgrade for existing power plants.

  2. Design and implementation of universal mathematical library supporting algorithm development for FPGA based systems in high energy physics experiments

    International Nuclear Information System (INIS)

    Jalmuzna, W.

    2006-02-01

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short Xray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF system in VUV FEL experiment based on modern FPGA chips It is being developed by ELHEP group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryomodule in the experiment. The device can be also used as the simulator of the cavity and testbench for other devices. Flexibility and computation power of this device allow implementation of fast mathematical algorithms. This paper describes the concept, implementation and tests of universal mathematical library for FPGA algorithm implementation. It consists of many useful components such as IQ demodulator, division block, library for complex and floating point operations, etc. It is able to speed up implementation time of many complicated algorithms. Library have already been tested using real accelerator signals and the performance achieved is satisfactory. (Orig.)

  3. FPGA-based 10-Gbit Ethernet Data Acquisition Interface for the Upgraded Electronics of the ATLAS Liquid Argon Calorimeters

    CERN Document Server

    Grohs, J P; The ATLAS collaboration

    2013-01-01

    The readout of the trigger signals of the ATLAS Liquid Argon (LAr) calorimeters is foreseen to be upgraded in order to prepare for operation during the first high-luminosity phase of the Large Hadron Collider (LHC). Signals with improved spatial granularity are planned to be received from the detector by a Digitial Processing System (DPS) in ATCA technology and will be sent in real-time to the ATLAS trigger system using custom optical links. These data are also sampled by the DPS for monitoring and will be read out by the regular Data Acquisition (DAQ) system of ATLAS which is a network-based PC-farm. The bandwidth between DPS module and DAQ system is expected to be in the order of 10 Gbit/s per module and a standard Ethernet protocol is foreseen to be used. DSP data will be prepared and sent by a modern FPGA either through a switch or directly to a Read-Out System (ROS) PC serving as buffer interface of the ATLAS DAQ. In a prototype setup, an ATCA blade equipped with a Xilinx Virtex-5 FPGA is used to send da...

  4. FPGA based, DSP integrated, 8-channel SIMCON, ver. 3.0. Initial results for 8-channel algorithm

    Energy Technology Data Exchange (ETDEWEB)

    Giergusiewicz, W.; Koprek, W.; Jalmuzna, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

    2005-07-01

    The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the VUV-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layer, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACC1 module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0. encouraged us to enter the design of SIMCON 3.1. possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0. is a modular solution, while SIMCON 3.1. will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one, after branching off in this version of the Simcon, will be continued. (orig.)

  5. Design and implementation of universal mathematical library supporting algorithm development for FPGA based systems in high energy physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Jalmuzna, W.

    2006-02-15

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short Xray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF system in VUV FEL experiment based on modern FPGA chips It is being developed by ELHEP group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryomodule in the experiment. The device can be also used as the simulator of the cavity and testbench for other devices. Flexibility and computation power of this device allow implementation of fast mathematical algorithms. This paper describes the concept, implementation and tests of universal mathematical library for FPGA algorithm implementation. It consists of many useful components such as IQ demodulator, division block, library for complex and floating point operations, etc. It is able to speed up implementation time of many complicated algorithms. Library have already been tested using real accelerator signals and the performance achieved is satisfactory. (Orig.)

  6. Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems

    Directory of Open Access Journals (Sweden)

    Sanjay Singh

    2017-05-01

    Full Text Available The design of smart video surveillance systems is an active research field among the computer vision community because of their ability to perform automatic scene analysis by selecting and tracking the objects of interest. In this paper, we present the design and implementation of an FPGA-based standalone working prototype system for real-time tracking of an object of interest in live video streams for such systems. In addition to real-time tracking of the object of interest, the implemented system is also capable of providing purposive automatic camera movement (pan-tilt in the direction determined by movement of the tracked object. The complete system, including camera interface, DDR2 external memory interface controller, designed object tracking VLSI architecture, camera movement controller and display interface, has been implemented on the Xilinx ML510 (Virtex-5 FX130T FPGA Board. Our proposed, designed and implemented system robustly tracks the target object present in the scene in real time for standard PAL (720 × 576 resolution color video and automatically controls camera movement in the direction determined by the movement of the tracked object.

  7. FPGA-based I and C Systems: A Technological Trick or a way to improve NPPs Safety and Security?

    Energy Technology Data Exchange (ETDEWEB)

    Sklyar, Vladimir; Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Vladimir; Bakhmach, Ievgenii [RPC RADIY, Kirovograd (Ukraine)

    2012-03-15

    The objective of this paper is to discuss advantages and values which Field Programmable Gates Array (FPGA) based solutions can add to Instrumentation and Control (I and C) design of Nuclear Power Plants (NPPs). Application of FPGAs as programmable components instead of Programmable Logic Controllers (PLC) is an advanced solution which provides decreasing of software impact on potential common cause failures (CCF). There are the following such advantages: Implementation of safety functions without the use of any operation software and operating system, Flexibility of the I and C platform which can be configured for any type of functions and reactor designs, Reduction in the time necessary for software verification in the design phase, Easy modification of control logic without any need for hardware modification, Possibility of implementing all safety requirements in safety and safety-related I and C systems, Tolerance to internal failures and external environmental impacts, Resilience to obsolescence due to the portability of the Hardware Description Language (HDL) code between various FPGA-chips produced by different manufacturers, Reduction in Corby vulnerability.

  8. An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation

    Directory of Open Access Journals (Sweden)

    David L. Ndzi

    2011-01-01

    Full Text Available This paper describes the development of a fast adaptable FPGA-based wideband channel sounder with signal bandwidths of up to 200 MHz and channel sampling rates up to 5.4 kHz. The application of FPGA allows the user to vary the number of real-time channel response averages, channel sampling interval, and duration of measurement. The waveform, bandwidth, and frequency resolution of the sounder can be adapted for any channel under investigation. The design approach and technology used has led to a reduction in size and weight by more than 60%. This makes the sounder ideal for mobile time-variant wireless communication channels studies. Averaging allows processing gains of up to 30 dB to be achieved for measurement in weak signal conditions. The technique applied also improves reliability, reduces power consumption, and has shifted sounder design complexity from hardware to software. Test results show that the sounder can detect very small-scale variations in channels.

  9. Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

    International Nuclear Information System (INIS)

    Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun

    2016-01-01

    The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD

  10. FPGA implementation for real-time background subtraction based on Horprasert model.

    Science.gov (United States)

    Rodriguez-Gomez, Rafael; Fernandez-Sanchez, Enrique J; Diaz, Javier; Ros, Eduardo

    2012-01-01

    Background subtraction is considered the first processing stage in video surveillance systems, and consists of determining objects in movement in a scene captured by a static camera. It is an intensive task with a high computational cost. This work proposes an embedded novel architecture on FPGA which is able to extract the background on resource-limited environments and offers low degradation (produced because of the hardware-friendly model modification). In addition, the original model is extended in order to detect shadows and improve the quality of the segmentation of the moving objects. We have analyzed the resource consumption and performance in Spartan3 Xilinx FPGAs and compared to others works available on the literature, showing that the current architecture is a good trade-off in terms of accuracy, performance and resources utilization. With less than a 65% of the resources utilization of a XC3SD3400 Spartan-3A low-cost family FPGA, the system achieves a frequency of 66.5 MHz reaching 32.8 fps with resolution 1,024 × 1,024 pixels, and an estimated power consumption of 5.76 W.

  11. A potent approach for the development of FPGA based DAQ system for HEP experiments

    Science.gov (United States)

    Khan, Shuaib Ahmad; Mitra, Jubin; David, Erno; Kiss, Tivadar; Nayak, Tapan Kumar

    2017-10-01

    With ever increasing particle beam energies and interaction rates in modern High Energy Physics (HEP) experiments in the present and future accelerator facilities, there has always been the demand for robust Data Acquisition (DAQ) schemes which perform in the harsh radiation environment and handle high data volume. The scheme is required to be flexible enough to adapt to the demands of future detector and electronics upgrades, and at the same time keeping the cost factor in mind. To address these challenges, in the present work, we discuss an efficient DAQ scheme for error resilient, high speed data communication on commercially available state-of-the-art FPGA with optical links. The scheme utilises GigaBit Transceiver (GBT) protocol to establish radiation tolerant communication link between on-detector front-end electronics situated in harsh radiation environment to the back-end Data Processing Unit (DPU) placed in a low radiation zone. The acquired data are reconstructed in DPU which reduces the data volume significantly, and then transmitted to the computing farms through high speed optical links using 10 Gigabit Ethernet (10GbE). In this study, we focus on implementation and testing of GBT protocol and 10GbE links on an Intel FPGA. Results of the measurements of resource utilisation, critical path delays, signal integrity, eye diagram and Bit Error Rate (BER) are presented, which are the indicators for efficient system performance.

  12. FPGA Implementation for Real-Time Background Subtraction Based on Horprasert Model

    Directory of Open Access Journals (Sweden)

    Eduardo Ros

    2012-01-01

    Full Text Available Background subtraction is considered the first processing stage in video surveillance systems, and consists of determining objects in movement in a scene captured by a static camera. It is an intensive task with a high computational cost. This work proposes an embedded novel architecture on FPGA which is able to extract the background on resource-limited environments and offers low degradation (produced because of the hardware-friendly model modification. In addition, the original model is extended in order to detect shadows and improve the quality of the segmentation of the moving objects. We have analyzed the resource consumption and performance in Spartan3 Xilinx FPGAs and compared to others works available on the literature, showing that the current architecture is a good trade-off in terms of accuracy, performance and resources utilization. With less than a 65% of the resources utilization of a XC3SD3400 Spartan-3A low-cost family FPGA, the system achieves a frequency of 66.5 MHz reaching 32.8 fps with resolution 1,024 x 1,024 pixels, and an estimated power consumption of 5.76 W.

  13. An Improved Minimum Error Interpolator of CNC for General Curves Based on FPGA

    Directory of Open Access Journals (Sweden)

    Jiye HUANG

    2014-05-01

    Full Text Available This paper presents an improved minimum error interpolation algorithm for general curves generation in computer numerical control (CNC. Compared with the conventional interpolation algorithms such as the By-Point Comparison method, the Minimum- Error method and the Digital Differential Analyzer (DDA method, the proposed improved Minimum-Error interpolation algorithm can find a balance between accuracy and efficiency. The new algorithm is applicable for the curves of linear, circular, elliptical and parabolic. The proposed algorithm is realized on a field programmable gate array (FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe. The algorithm has the following advantages: firstly, the maximum interpolation error is only half of the minimum step-size; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

  14. An FPGA based backup version of the TileCal digitizer

    International Nuclear Information System (INIS)

    Eriksson, D; Muschter, S; Bohm, C

    2010-01-01

    The ATLAS Tile Calorimeter front end digitization and readout system comprises about 1800 digitizer boards with two TileDMU ASICs on each board. The TileDMUs are responsible for storing, derandomising and reading out digitized data from twelve ADCs. An ample number of board spares are available. However, a backup solution is desirable in the event of unexpected failure modes. The original version contains both outdated and custom made circuits that are difficult or impossible to find in sufficient numbers. We have developed a new version using inexpensive off the shelf FPGAs (Spartan 6). The FPGAs have all the necessary functionality to emulate the TileDMU and will be readily available for a considerable time. The new board is functionally compatible with the current version and to a large extent uses the same code. The design goal was to leave the digitizer design as intact as possible since it is well tested and performs well. As radiation tolerance is an issue we have implemented triple mode redundancy in the FPGA. To further improve the system we added in system programmability via TTCrx for both the FPGA and the configuration memory using one way JTAG. This provides a way to recover from radiation damage to the configuration PROM or to remotely upgrade system firmware.

  15. An FPGA based backup version of the TileCal digitizer.

    Science.gov (United States)

    Eriksson, D.; Muschter, S.; Bohm, C.

    2010-11-01

    The ATLAS Tile Calorimeter front end digitization and readout system comprises about 1800 digitizer boards with two TileDMU ASICs on each board. The TileDMUs are responsible for storing, derandomising and reading out digitized data from twelve ADCs. An ample number of board spares are available. However, a backup solution is desirable in the event of unexpected failure modes. The original version contains both outdated and custom made circuits that are difficult or impossible to find in sufficient numbers. We have developed a new version using inexpensive off the shelf FPGAs (Spartan 6). The FPGAs have all the necessary functionality to emulate the TileDMU and will be readily available for a considerable time. The new board is functionally compatible with the current version and to a large extent uses the same code. The design goal was to leave the digitizer design as intact as possible since it is well tested and performs well. As radiation tolerance is an issue we have implemented triple mode redundancy in the FPGA. To further improve the system we added in system programmability via TTCrx for both the FPGA and the configuration memory using one way JTAG. This provides a way to recover from radiation damage to the configuration PROM or to remotely upgrade system firmware.

  16. Timing generator of scientific grade CCD camera and its implementation based on FPGA technology

    Science.gov (United States)

    Si, Guoliang; Li, Yunfei; Guo, Yongfei

    2010-10-01

    The Timing Generator's functions of Scientific Grade CCD Camera is briefly presented: it generates various kinds of impulse sequence for the TDI-CCD, video processor and imaging data output, acting as the synchronous coordinator for time in the CCD imaging unit. The IL-E2TDI-CCD sensor produced by DALSA Co.Ltd. use in the Scientific Grade CCD Camera. Driving schedules of IL-E2 TDI-CCD sensor has been examined in detail, the timing generator has been designed for Scientific Grade CCD Camera. FPGA is chosen as the hardware design platform, schedule generator is described with VHDL. The designed generator has been successfully fulfilled function simulation with EDA software and fitted into XC2VP20-FF1152 (a kind of FPGA products made by XILINX). The experiments indicate that the new method improves the integrated level of the system. The Scientific Grade CCD camera system's high reliability, stability and low power supply are achieved. At the same time, the period of design and experiment is sharply shorted.

  17. Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun [KHNP CRI, Daejeon (Korea, Republic of)

    2016-10-15

    The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD.

  18. Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing

    Directory of Open Access Journals (Sweden)

    Ramu Seva

    2017-11-01

    Full Text Available The high performance of FPGA (Field Programmable Gate Array in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively.

  19. A potent approach for the development of FPGA based DAQ system for HEP experiments

    International Nuclear Information System (INIS)

    Khan, Shuaib Ahmad; Mitra, Jubin; Nayak, Tapan Kumar; David, Erno; Kiss, Tivadar

    2017-01-01

    With ever increasing particle beam energies and interaction rates in modern High Energy Physics (HEP) experiments in the present and future accelerator facilities, there has always been the demand for robust Data Acquisition (DAQ) schemes which perform in the harsh radiation environment and handle high data volume. The scheme is required to be flexible enough to adapt to the demands of future detector and electronics upgrades, and at the same time keeping the cost factor in mind. To address these challenges, in the present work, we discuss an efficient DAQ scheme for error resilient, high speed data communication on commercially available state-of-the-art FPGA with optical links. The scheme utilises GigaBit Transceiver (GBT) protocol to establish radiation tolerant communication link between on-detector front-end electronics situated in harsh radiation environment to the back-end Data Processing Unit (DPU) placed in a low radiation zone. The acquired data are reconstructed in DPU which reduces the data volume significantly, and then transmitted to the computing farms through high speed optical links using 10 Gigabit Ethernet (10GbE). In this study, we focus on implementation and testing of GBT protocol and 10GbE links on an Intel FPGA. Results of the measurements of resource utilisation, critical path delays, signal integrity, eye diagram and Bit Error Rate (BER) are presented, which are the indicators for efficient system performance.

  20. A FPGA-based Fast Converging Digital Adaptive Filter for Real-time RFI Mitigation on Ground Based Radio Telescopes

    Science.gov (United States)

    Finger, R.; Curotto, F.; Fuentes, R.; Duan, R.; Bronfman, L.; Li, D.

    2018-02-01

    Radio Frequency Interference (RFI) is a growing concern in the radio astronomy community. Single-dish telescopes are particularly susceptible to RFI. Several methods have been developed to cope with RF-polluted environments, based on flagging, excision, and real-time blanking, among others. All these methods produce some degree of data loss or require assumptions to be made on the astronomical signal. We report the development of a real-time, digital adaptive filter implemented on a Field Programmable Gate Array (FPGA) capable of processing 4096 spectral channels in a 1 GHz of instantaneous bandwidth. The filter is able to cancel a broad range of interference signals and quickly adapt to changes on the RFI source, minimizing the data loss without any assumption on the astronomical or interfering signal properties. The speed of convergence (for a decrease to a 1%) was measured to be 208.1 μs for a broadband noise-like RFI signal and 125.5 μs for a multiple-carrier RFI signal recorded at the FAST radio telescope.

  1. Use of FPGA to face electronic component obsolescence in software based safety I and C in NPPS

    International Nuclear Information System (INIS)

    Hadj, Abdellah; Bach, Julien; Esmenjaud, Claude; Daumas, Frederic; Salauen, Patrick

    2010-01-01

    In order to extend the life time of their Nuclear Power Plants (NPPs), most utilities are looking for ways to implement the renovation of their existing Instrumentation and Control (I and C) systems. When the I and C to modernize is software based, three paths can be considered: - to keep the legacy microprocessor and limit refurbishment to the associated hardware (i.e. the I/O boards, memories and the CPU board itself), - to move to another I and C platform based on another microprocessor, - to move to a non microprocessor based I and C platform. Software based I and C provide strong advantages such as flexibility and ability to implement advanced functions, however the complexity and the decreasing life time of nowadays microprocessors, mainly developed for the needs of the personal computer market, makes difficult their use and licensing for safety digital I and C systems. Solutions based on re-engineering of legacy microprocessors, or use of microprocessors dedicated to critical application need to be considered. In order to share a prospective vision of the future of I and C systems in NPPs, Electricite de France (EDF) Research and Development division and Rolls-Royce have launched a three year cooperation program on the use of the ASIC/FPGA technology in safety I and C systems. The first step of this program addresses the ability of the ASIC/FPGA technology to provide replacement solutions for former microprocessors taking as example the replacement of the Motorola MC6800 microprocessor. This paper presents the development of an IP cloning the Motorola MC6800 microprocessor, suitable for use in the refurbishment of safety I and C equipment based on this microprocessor. (authors)

  2. Realization of manchester encoding and decoding and fast-speed communication for digital power supply based on FPGA

    International Nuclear Information System (INIS)

    Chen Huanguang; Xu Ruinian; Shen Tianjian; Li Deming

    2008-01-01

    A design and simulation to realize the process of Manchester encoding and decoding, to realize the process of SPI communication between FPGA and DSP, using Altera company's Quartus II IDE on FPGA is presented in this paper. And the application on the digital power supply controller with Manchester communication by optical fiber is introduced. (authors)

  3. A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems

    DEFF Research Database (Denmark)

    Pezzarossa, Luca; Schoeberl, Martin; Sparsø, Jens

    2017-01-01

    -source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes......In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading....... The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example...

  4. SSTL I/O Standard Based Environment Friendly Energy Efficient ROM Design on FPGA

    DEFF Research Database (Denmark)

    Bansal, Neha; Bansal, Meenakshi; Saini, Rishita

    2014-01-01

    are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1......Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role...

  5. FPGA-based technology for Pulse Height Analysis in nuclear spectrometry system

    International Nuclear Information System (INIS)

    Andrianiaina, H.; Raoelina Andriambololona; Rajaobelison, J.; Rambolamanana, G.; Roengen, H.

    2009-01-01

    Facing the rapid technology development applied in nuclear instruments, Madagascar-INSTN has taken measures to estabilish and enhance the national capabilities in their maintenance, calibration, design/modification and repair, which is a key factor in the development of sustainable nuclear technology.The maintenance will be more convenient if all technical resources are made available: this is only possible when the acces to designer side of the instruments is permitted. Research and instrumentation development projects have been developed to support and to fit the local needs: Pulse Height Analysis algorithm is designed within FPGA and VHDL programming technics to build a Multi-Input Multi-Channel Analyzer. Description and measurement results with the MIMCA will be described in the present paper

  6. Design of belief propagation based on FPGA for the multistereo CAFADIS camera.

    Science.gov (United States)

    Magdaleno, Eduardo; Lüke, Jonás Philipp; Rodríguez, Manuel; Rodríguez-Ramos, José Manuel

    2010-01-01

    In this paper we describe a fast, specialized hardware implementation of the belief propagation algorithm for the CAFADIS camera, a new plenoptic sensor patented by the University of La Laguna. This camera captures the lightfield of the scene and can be used to find out at which depth each pixel is in focus. The algorithm has been designed for FPGA devices using VHDL. We propose a parallel and pipeline architecture to implement the algorithm without external memory. Although the BRAM resources of the device increase considerably, we can maintain real-time restrictions by using extremely high-performance signal processing capability through parallelism and by accessing several memories simultaneously. The quantifying results with 16 bit precision have shown that performances are really close to the original Matlab programmed algorithm.

  7. An FPGA-based trigger for the phase II of the MEG experiment

    Energy Technology Data Exchange (ETDEWEB)

    Baldini, A. [Istituto Nazionale di Fisica Nucleare, Pisa (Italy); Bemporad, C.; Cei, F. [Istituto Nazionale di Fisica Nucleare, Pisa (Italy); Dipartimento di Fisica, Università di Pisa (Italy); Galli, L.; Grassi, M.; Morsani, F. [Istituto Nazionale di Fisica Nucleare, Pisa (Italy); Nicolò, D., E-mail: donato.nicolo@pi.infn.it [Istituto Nazionale di Fisica Nucleare, Pisa (Italy); Dipartimento di Fisica, Università di Pisa (Italy); Ritt, S. [Paul Scherrer Institut, Villigen AG (Switzerland); Venturini, M. [Istituto Nazionale di Fisica Nucleare, Pisa (Italy); Scuola Normale Superiore, Pisa (Italy)

    2016-07-11

    For the phase II of MEG, we are going to develop a combined trigger and DAQ system. Here we focus on the former side, which operates an on-line reconstruction of detector signals and event selection within 450 μs from event occurrence. Trigger concentrator boards (TCB) are under development to gather data from different crates, each connected to a set of detector channels, to accomplish higher-level algorithms to issue a trigger in the case of a candidate signal event. We describe the major features of the new system, in comparison with phase I, as well as its performances in terms of selection efficiency and background rejection. - Highlights: • A new, two-level trigger scheme for the phase-II of the MEG experiment is presented. • Improvements with respect to phase-I are underlined. • The role of detector upgrades and the use of a new generation of FPGA as well are emphasized.

  8. Design of Belief Propagation Based on FPGA for the Multistereo CAFADIS Camera

    Directory of Open Access Journals (Sweden)

    José Manuel Rodríguez-Ramos

    2010-10-01

    Full Text Available In this paper we describe a fast, specialized hardware implementation of the belief propagation algorithm for the CAFADIS camera, a new plenoptic sensor patented by the University of La Laguna. This camera captures the lightfield of the scene and can be used to find out at which depth each pixel is in focus. The algorithm has been designed for FPGA devices using VHDL. We propose a parallel and pipeline architecture to implement the algorithm without external memory. Although the BRAM resources of the device increase considerably, we can maintain real-time restrictions by using extremely high-performance signal processing capability through parallelism and by accessing several memories simultaneously. The quantifying results with 16 bit precision have shown that performances are really close to the original Matlab programmed algorithm.

  9. A systematic FPGA acceleration design for applications based on convolutional neural networks

    Science.gov (United States)

    Dong, Hao; Jiang, Li; Li, Tianjian; Liang, Xiaoyao

    2018-04-01

    Most FPGA accelerators for convolutional neural network are designed to optimize the inner acceleration and are ignored of the optimization for the data path between the inner accelerator and the outer system. This could lead to poor performance in applications like real time video object detection. We propose a brand new systematic FPFA acceleration design to solve this problem. This design takes the data path optimization between the inner accelerator and the outer system into consideration and optimizes the data path using techniques like hardware format transformation, frame compression. It also takes fixed-point, new pipeline technique to optimize the inner accelerator. All these make the final system's performance very good, reaching about 10 times the performance comparing with the original system.

  10. Design of an Oximeter Based on LED-LED Configuration and FPGA Technology

    Directory of Open Access Journals (Sweden)

    Radovan Stojanovic

    2013-01-01

    Full Text Available A fully digital photoplethysmographic (PPG sensor and actuator has been developed. The sensing circuit uses one Light Emitting Diode (LED for emitting light into human tissue and one LED for detecting the reflectance light from human tissue. A Field Programmable Gate Array (FPGA is used to control the LEDs and determine the PPG and Blood Oxygen Saturation (SpO2. The configurations with two LEDs and four LEDs are developed for measuring PPG signal and Blood Oxygen Saturation (SpO2. N-LEDs configuration is proposed for multichannel SpO2 measurements. The approach resulted in better spectral sensitivity, increased and adjustable resolution, reduced noise, small size, low cost and low power consumption.

  11. Design of an oximeter based on LED-LED configuration and FPGA technology.

    Science.gov (United States)

    Stojanovic, Radovan; Karadaglic, Dejan

    2013-01-04

    A fully digital photoplethysmographic (PPG) sensor and actuator has been developed. The sensing circuit uses one Light Emitting Diode (LED) for emitting light into human tissue and one LED for detecting the reflectance light from human tissue. A Field Programmable Gate Array (FPGA) is used to control the LEDs and determine the PPG and Blood Oxygen Saturation (S(p)O(2)). The configurations with two LEDs and four LEDs are developed for measuring PPG signal and Blood Oxygen Saturation (S(p)O(2)). N-LEDs configuration is proposed for multichannel S(p)O(2) measurements. The approach resulted in better spectral sensitivity, increased and adjustable resolution, reduced noise, small size, low cost and low power consumption.

  12. FPGA based high-performance multi-channel analyzer with local histogram memory

    International Nuclear Information System (INIS)

    Kulkarni, C.P.; Vaidya, P.P.; Paulson, M.

    2004-01-01

    Modern nuclear spectroscopy systems demand for a Multi-Channel Analyzer (MCA) with higher resolution, faster speed and other advanced features. The MCA described here is targeted for such demanding applications. The MCA has an in-built local histogram memory and a memory management unit integrated in an FPGA (Field Programmable Gate Array) chip. In addition to the integrated low power digital circuitry, the system utilizes state of the art advanced analog circuits like low power, high speed and high precision comparators, op-amps, ADC and DAC. The operating resolution is selectable from 256 channels to 16384 channels for pulse height analysis. It supports high count rate applications (typically 100 KHz) without significant dead time penalty. It can have an USB bus interface with simple changes. In general, the MCA gives a high performance, compact and low power alternative for portable and battery operated systems as well as for high end laboratory instruments. (author)

  13. Design of FPGA based high-speed data acquisition and real-time data processing system on J-TEXT tokamak

    International Nuclear Information System (INIS)

    Zheng, W.; Liu, R.; Zhang, M.; Zhuang, G.; Yuan, T.

    2014-01-01

    Highlights: • It is a data acquisition system for polarimeter–interferometer diagnostic on J-TEXT tokamak based on FPGA and PXIe devices. • The system provides a powerful data acquisition and real-time data processing performance. • Users can implement different data processing applications on the FPGA in a short time. • This system supports EPICS and has been integrated into the J-TEXT CODAC system. - Abstract: Tokamak experiment requires high-speed data acquisition and processing systems. In traditional data acquisition system, the sampling rate, channel numbers and processing speed are limited by bus throughput and CPU speed. This paper presents a data acquisition and processing system based on FPGA. The data can be processed in real-time before it is passed to the CPU. It provides processing ability for more channels with higher sampling rates than the traditional data acquisition system while ensuring deterministic real-time performance. A working prototype is developed for the newly built polarimeter–interferometer diagnostic system on the Joint Texas Experimental Tokamak (J-TEXT). It provides 16 channels with 120 MHz maximum sampling rate and 16 bit resolution. The onboard FPGA is able to calculate the plasma electron density and Faraday rotation angel. A RAID 5 storage device is adopted providing 700 MB/s read–write speed to buffer the data to the hard disk continuously for better performance

  14. An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

    Directory of Open Access Journals (Sweden)

    Chao Chen

    2014-01-01

    Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

  15. Efficient Processing of a Rainfall Simulation Watershed on an FPGA-Based Architecture with Fast Access to Neighbourhood Pixels

    Directory of Open Access Journals (Sweden)

    Yeong LeeSeng

    2009-01-01

    Full Text Available This paper describes a hardware architecture to implement the watershed algorithm using rainfall simulation. The speed of the architecture is increased by utilizing a multiple memory bank approach to allow parallel access to the neighbourhood pixel values. In a single read cycle, the architecture is able to obtain all five values of the centre and four neighbours for a 4-connectivity watershed transform. The storage requirement of the multiple bank implementation is the same as a single bank implementation by using a graph-based memory bank addressing scheme. The proposed rainfall watershed architecture consists of two parts. The first part performs the arrowing operation and the second part assigns each pixel to its associated catchment basin. The paper describes the architecture datapath and control logic in detail and concludes with an implementation on a Xilinx Spartan-3 FPGA.

  16. Control electronic platform based on floating-point DSP and FPGA for a NPC multilevel back-to-back converter

    Energy Technology Data Exchange (ETDEWEB)

    Rodriguez, Francisco J.; Cobreces, Santiago; Bueno, Emilio J.; Hernandez, Alvaro; Mateos, Raul; Espinosa, Felipe [Department of Electronics, University of Alcala, Alcala de Henares, Madrid (Spain)

    2008-09-15

    Modern energy concepts as Distributed Power Generation are changing the appearance of electric distribution and transmission and challenging power electronics researchers, which try to develop new solutions of electronic controllers. The aim is to enable the implementation of new and more complex control algorithms to verify the last standards related to the grid energy quality for new power converters, and, also, for equipments which nowadays are operating. This paper presents the design, implementation and test of a novel real-time controller for a Neutral Point Clamped (NPC) (three-level) multilevel converter based on a floating-point Digital Signal Processor (DSP) and on a Field-Programmable Gate Array (FPGA), by operating in a cooperative way. Although the proposed system can be readily applied to any power electronic application, in this work, it is focused on the next system: a 150 kVA back-to-back three-level NPC Voltage Source Converter (VSC) for wind power applications. (author)

  17. Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

    Science.gov (United States)

    Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

    2016-07-01

    to DDC block, which down converts the data to base-band. The DDC block has NCO, mixer and two chains of Bessel filters (fifth order cascaded integration comb filter, two FIR filters, two half band filters and programmable FIR filters) for in-phase (I) and Quadrature phase (Q) channels. The NCO has 32 bits and is set to match the output frequency of ADC. Further, DDC down samples (decimation) the data and reduces the data rate to 16 MSPS. This data is further decimated and the data rate is reduced down to 4/2/1/0.5/0.25/0.125/0.0625 MSPS for baud lengths 0.25/0.5/1/2/4/8/16 μs respectively. The down sampled data is then fed to decoding block, which performs cross correlation to achieve pulse compression of the binary-phase coded data to obtain better range resolution with maximum possible height coverage. This step improves the signal power by a factor equal to the length of the code. Coherent integration block integrates the decoded data coherently for successive pulses, which improves the signal to noise ratio and reduces the data volume. DDC, decoding and coherent integration blocks are implemented in Xilinx vertex5 FPGA. Till this point, function of all six channels is same for DBS mode and multi-receiver modes. Data from vertex5 FPGA is transferred to PC via GbE-1 interface for multi-modes or to two Analog devices make ADSP-TS201 DSP chips (A and B), via link port for DBS mode. ADSP-TS201 chips perform the normalization, DC removal, windowing, FFT computation and spectral averaging on the data, which is transferred to storage/display PC via GbE-2 interface for real-time data display and data storing. Physical layer of GbE interface is implemented in an external chip (Marvel 88E1111) and MAC layer is implemented internal to vertex5 FPGA. The MCDRx has total 4 GB of DDR2 memory for data storage. Spartan6 FPGA is used for generating timing signals, required for basic operation of the radar and testing of the MCDRx.

  18. FPGA Design and Verification Procedure for Nuclear Power Plant MMIS

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Yoo, Kawnwoo; Ryoo, Kwangki [Hanbat National Univ., Daejeon (Korea, Republic of)

    2013-05-15

    In this paper, it is shown that it is possible to ensure reliability by performing the steps of the verification based on the FPGA development methodology, to ensure the safety of application to the NPP MMIS of the FPGA run along the step. Currently, the PLC (Programmable Logic Controller) which is being developed is composed of the FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit). As the importance of the FPGA in the NPP (Nuclear Power Plant) MMIS (Man-Machine Interface System) has been increasing than before, the research on the verification of the FPGA has being more and more concentrated recently.

  19. Feasibility study to use an SRAM-based FPGA in the readout electronics of the upgraded LHCb outer tracker detector

    International Nuclear Information System (INIS)

    Faerber, Christian

    2014-01-01

    This thesis presents a study of the feasibility to use SRAM-based FPGAs as central component of the upgraded LHCb Outer Tracker readout electronics. The FPGA should contain the functionality of a TDC and should provide fast data links using multi-GBit/s transceivers. The TDC core that was developed provides 5 bit time measurements for 32 channels with a bin size of 780 ps. The TDC has the required time resolution of better than 1 ns. This was achieved by manually placing every logic element of the TDC channels and with an iterative procedure feeding timing measurements back to the Place and Route step of the router software. A transceiver and TDC card, and an adapter board for the existing readout electronics was developed. Both boards were used successfully to read out drift times from an Outer Tracker straw-tube module in a cosmic setup. To qualify the proposed electronics for the expected radiation levels an irradiation test with 22 MeV protons and two FPGA boards was performed up to a total ionization dose of 30 Mrad. Both chips sustained the irradiation expected for the full life time of the upgraded LHCb detector of up to 30 krad. After an irradiation dose of 150 krad the first deteriorations of the performance of the chips were observed. The proton cross section for configuration bit flips was determined to be 1.6.10 16 cm 2 per bit. The measured error rate scaled to the upgrade environment would correspond to a manageable firmware error rate.

  20. Real-time co-registered ultrasound and photoacoustic imaging system based on FPGA and DSP architecture

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andres; Zhu, Quing

    2011-03-01

    Co-registering ultrasound (US) and photoacoustic (PA) imaging is a logical extension to conventional ultrasound because both modalities provide complementary information of tumor morphology, tumor vasculature and hypoxia for cancer detection and characterization. In addition, both modalities are capable of providing real-time images for clinical applications. In this paper, a Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) module-based real-time US/PA imaging system is presented. The system provides real-time US/PA data acquisition and image display for up to 5 fps* using the currently implemented DSP board. It can be upgraded to 15 fps, which is the maximum pulse repetition rate of the used laser, by implementing an advanced DSP module. Additionally, the photoacoustic RF data for each frame is saved for further off-line processing. The system frontend consists of eight 16-channel modules made of commercial and customized circuits. Each 16-channel module consists of two commercial 8-channel receiving circuitry boards and one FPGA board from Analog Devices. Each receiving board contains an IC† that combines. 8-channel low-noise amplifiers, variable-gain amplifiers, anti-aliasing filters, and ADC's‡ in a single chip with sampling frequency of 40MHz. The FPGA board captures the LVDSξ Double Data Rate (DDR) digital output of the receiving board and performs data conditioning and subbeamforming. A customized 16-channel transmission circuitry is connected to the two receiving boards for US pulseecho (PE) mode data acquisition. A DSP module uses External Memory Interface (EMIF) to interface with the eight 16-channel modules through a customized adaptor board. The DSP transfers either sub-beamformed data (US pulse-echo mode or PAI imaging mode) or raw data from FPGA boards to its DDR-2 memory through the EMIF link, then it performs additional processing, after that, it transfer the data to the PC** for further image processing. The PC code

  1. Study on FPGA-Based Emulator for the Diagnosis of Gradual Degradation in Reciprocating Pump

    Energy Technology Data Exchange (ETDEWEB)

    Lim, Sang Sun; Kim, Wooshik [Sejong Univ., Seoul (Korea, Republic of); Kim, Tae Yun; Chai, Jang Bom [Ajou Univ., Suwon (Korea, Republic of)

    2017-01-15

    The purpose of this study is to develop a method for diagnosing the degree of gradual degradation of a reciprocating pump caused by continuous use as a water supply pump in a nuclear power plant. Normally, the progress of such degradation is too slow to be noticed. Hence, it is difficult to determine the degree of degradation using the existing diagnostic methods. In this paper, we propose a new method by which the normal state and the degraded state of the pump can be differentiated, so that the degree of degradation can be identified. First, an emulator was developed using FPGA by providing the parameters of the pump under normal state, so that the emulator generates the information of the pump in the healthy state. Then, by comparing this information with the parameters received from various output sensors of the emulator during the current state, it is possible to identify and measure the degree of gradual degradation. This paper presents some of the results obtained during the development process, and results that show how the emulator operates, by comparing the data collected from an actual pump.

  2. Compact FPGA-based beamformer using oversampled 1-bit A/D converters

    DEFF Research Database (Denmark)

    Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

    2005-01-01

    A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadr......% of the available logic resources in a commercially available midrange FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.......A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in......-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal...

  3. FPGA-Based Real Time, Multichannel Emulated-Digital Retina Model Implementation

    Directory of Open Access Journals (Sweden)

    Zsolt Vörösházi

    2009-01-01

    Full Text Available The function of the low-level image processing that takes place in the biological retina is to compress only the relevant visual information to a manageable size. The behavior of the layers and different channels of the neuromorphic retina has been successfully modeled by cellular neural/nonlinear networks (CNNs. In this paper, we present an extended, application-specific emulated-digital CNN-universal machine (UM architecture to compute the complex dynamic of this mammalian retina in video real time. The proposed emulated-digital implementation of multichannel retina model is compared to the previously developed models from three key aspects, which are processing speed, number of physical cells, and accuracy. Our primary aim was to build up a simple, real-time test environment with camera input and display output in order to mimic the behavior of retina model implementation on emulated digital CNN by using low-cost, moderate-sized field-programmable gate array (FPGA architectures.

  4. FPGA-based real-time embedded system for RISS/GPS integrated navigation.

    Science.gov (United States)

    Abdelfatah, Walid Farid; Georgy, Jacques; Iqbal, Umar; Noureldin, Aboelmagd

    2012-01-01

    Navigation algorithms integrating measurements from multi-sensor systems overcome the problems that arise from using GPS navigation systems in standalone mode. Algorithms which integrate the data from 2D low-cost reduced inertial sensor system (RISS), consisting of a gyroscope and an odometer or wheel encoders, along with a GPS receiver via a Kalman filter has proved to be worthy in providing a consistent and more reliable navigation solution compared to standalone GPS receivers. It has been also shown to be beneficial, especially in GPS-denied environments such as urban canyons and tunnels. The main objective of this paper is to narrow the idea-to-implementation gap that follows the algorithm development by realizing a low-cost real-time embedded navigation system capable of computing the data-fused positioning solution. The role of the developed system is to synchronize the measurements from the three sensors, relative to the pulse per second signal generated from the GPS, after which the navigation algorithm is applied to the synchronized measurements to compute the navigation solution in real-time. Employing a customizable soft-core processor on an FPGA in the kernel of the navigation system, provided the flexibility for communicating with the various sensors and the computation capability required by the Kalman filter integration algorithm.

  5. Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA

    International Nuclear Information System (INIS)

    Martins, Roque Hudson da Silva

    2016-01-01

    This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

  6. A cellular automata based FPGA realization of a new metaheuristic bat-inspired algorithm

    Science.gov (United States)

    Progias, Pavlos; Amanatiadis, Angelos A.; Spataro, William; Trunfio, Giuseppe A.; Sirakoulis, Georgios Ch.

    2016-10-01

    Optimization algorithms are often inspired by processes occuring in nature, such as animal behavioral patterns. The main concern with implementing such algorithms in software is the large amounts of processing power they require. In contrast to software code, that can only perform calculations in a serial manner, an implementation in hardware, exploiting the inherent parallelism of single-purpose processors, can prove to be much more efficient both in speed and energy consumption. Furthermore, the use of Cellular Automata (CA) in such an implementation would be efficient both as a model for natural processes, as well as a computational paradigm implemented well on hardware. In this paper, we propose a VHDL implementation of a metaheuristic algorithm inspired by the echolocation behavior of bats. More specifically, the CA model is inspired by the metaheuristic algorithm proposed earlier in the literature, which could be considered at least as efficient than other existing optimization algorithms. The function of the FPGA implementation of our algorithm is explained in full detail and results of our simulations are also demonstrated.

  7. Design of FPGA Based Neural Network Controller for Earth Station Power System

    Directory of Open Access Journals (Sweden)

    Hassen T. Dorrah

    2012-06-01

    Full Text Available Automation of generating hardware description language code from neural networks models can highly decrease time of implementation those networks into a digital devices, thus significant money savings. To implement the neural network into hardware designer, it is required to translate generated model into device structure. VHDL language is used to describe those networks into hardware. VHDL code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic of the earth station and the satellite power systems using ModelSim PE 6.6 simulator tool. Integration between MATLAB and VHDL is used to save execution time of computation. The results shows that a good agreement between MATLAB and VHDL and a fast/flexible feed forward NN which is capable of dealing with floating point arithmetic operations; minimum number of CLB slices; and good speed of performance. FPGA synthesis results are obtained with view RTL schematic and technology schematic from Xilinix tool. Minimum number of utilized resources is obtained by using Xilinix VERTIX5.

  8. DOOCS based control system for FPGA based cavity simulator and controller in VUV FEL

    International Nuclear Information System (INIS)

    Pucyk, P.

    2005-09-01

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short X-ray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF 1 system in VUV FEL experiment It is being developed by ELHEP 2 group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryo module in the experiment. The device can be also used as the simulator of the cavity and test bench for other devices. Ths paper describes the concept, implementation and tests of the DOOCS based control system for SIMCON. The designed system is based the concept of autonomic and extendable modules connected by well defined, unified interfaces. The communication module controls the access to the hardware. It is crucial, that all modules (this presented in thesis and developed in the future) use this interface. Direct access to the control tables let the engineers to perform algorithm development or diagnostic measurements of the LLRF system. Default control tables generator makes the whole SIMCON an autonomic device, which can start immediately the operation without any additional tools. (orig.)

  9. DOOCS based control system for FPGA based cavity simulator and controller in VUV FEL

    International Nuclear Information System (INIS)

    Pucyk, P.D.

    2006-03-01

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short X-ray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF 1 system in VUV FEL experiment It is being developed by ELHEP 2 group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryo module in the experiment. The device can be also used as the simulator of the cavity and test bench for other devices. This paper describes the concept, implementation and tests of the DOOCS based control system for SIMCON. The designed system is based the concept of autonomic and extendable modules connected by well defined, unified interfaces. The communication module controls the access to the hardware. It is crucial, that all modules (this presented in thesis and developed in the future) use this interface. Direct access to the control tables let the engineers to perform algorithm development or diagnostic measurements of the LLRF system. Default control tables generator makes the whole SIMCON an autonomic device, which can start immediately the operation without any additional tools. (Orig.)

  10. Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support

    Directory of Open Access Journals (Sweden)

    Burhan Khurshid

    2015-05-01

    Full Text Available Modern Field Programmable Gate Arrays (FPGA are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC primarily because of the low Non-recurring Engineering (NRE costs associated with FPGA platforms. This has prompted FPGA vendors to improve the capacity and flexibility of the underlying primitive fabric and include specialized macro support and intellectual property (IP cores in their offerings. However, most of the work related to FPGA implementations does not take full advantage of these offerings. This is primarily because designers rely mainly on the technology-independent optimization to enhance the performance of the system and completely neglect the speed-up that is achievable using these embedded primitives and macro support. In this paper, we consider the technology-dependent optimization of fixed-point bit-parallel multipliers by carrying out their implementations using embedded primitives and macro support that are inherent in modern day FPGAs. Our implementation targets three different FPGA families viz. Spartan-6, Virtex-4 and Virtex-5. The implementation results indicate that a considerable speed up in performance is achievable using these embedded FPGA resources.

  11. The effect of structural design parameters on FPGA-based feed-forward space-time trellis coding-orthogonal frequency division multiplexing channel encoders

    Science.gov (United States)

    Passas, Georgios; Freear, Steven; Fawcett, Darren

    2010-08-01

    Orthogonal frequency division multiplexing (OFDM)-based feed-forward space-time trellis code (FFSTTC) encoders can be synthesised as very high speed integrated circuit hardware description language (VHDL) designs. Evaluation of their FPGA implementation can lead to conclusions that help a designer to decide the optimum implementation, given the encoder structural parameters. VLSI architectures based on 1-bit multipliers and look-up tables (LUTs) are compared in terms of FPGA slices and block RAMs (area), as well as in terms of minimum clock period (speed). Area and speed graphs versus encoder memory order are provided for quadrature phase shift keying (QPSK) and 8 phase shift keying (8-PSK) modulation and two transmit antennas, revealing best implementation under these conditions. The effect of number of modulation bits and transmit antennas on the encoder implementation complexity is also investigated.

  12. An FPGA-based track finder for the L1 trigger of the CMS experiment at the HL-LHC

    CERN Document Server

    Cieri, Davide; Harder, Kristian; Manolopoulos, Konstantinos; Shepherd-Themistocleous, Claire; Tomalin, Ian; Aggleton, Robin; Ball, Fionn; Brooke, Jim; Clement, Emyr; Newbold, Dave; Paramesvaran, Sudarshan; Hobson, Peter; Morton, Alexander Davide; Reid, Ivan; Hall, Geoff; Iles, Gregory; James, Thomas Owen; Matsushita, Takashi; Pesaresi, Mark; Rose, Andrew William; Shtipliyski, Antoni; Summers, Sioni; Tapper, Alex; Uchida, Kirika; Vichoudis, Paschalis; Ardila-Perez, Luis; Balzer, Matthias; Caselle, Michele; Sander, Oliver; Schuh, Thomas; Weber, Marc

    2017-01-01

    A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial component of this upgrade will be the ability to reconstruct within a few microseconds all charged particle tracks with transverse momentum above 3 GeV, so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform followed by a track fitting based on the linear regression technique. A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters. It successfully operates on one eighth of the tracker solid angle at a time, processing events taken at 40 MHz, each with up to 200 superimposed proton-proton interactions, whilst satisfying latency constraints. T...

  13. Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

    Energy Technology Data Exchange (ETDEWEB)

    Hu, Wei [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Choi, Yong, E-mail: ychoi.image@gmail.com [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Hong, Key Jo [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Kang, Jihoon [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Jung, Jin Ho [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Huh, Youn Suk [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Lim, Hyun Keong; Kim, Sang Su [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Kim, Byung-Tae [Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Chung, Yonghyun [Department of Radiological Science, Yonsei University College of Health Science, 234 Meaji, Heungup Wonju, Kangwon-Do 220-710 (Korea, Republic of)

    2012-02-01

    Currently, for most photomultiplier tube (PMT)-based PET systems, constant fraction discriminators (CFD) and time to digital converters (TDC) have been employed to detect gamma ray signal arrival time, whereas anger logic circuits and peak detection analog-to-digital converters (ADCs) have been implemented to acquire position and energy information of detected events. As compared to PMT the Geiger-mode avalanche photodiodes (GAPDs) have a variety of advantages, such as compactness, low bias voltage requirement and MRI compatibility. Furthermore, the individual read-out method using a GAPD array coupled 1:1 with an array scintillator can provide better image uniformity than can be achieved using PMT and anger logic circuits. Recently, a brain PET using 72 GAPD arrays (4 Multiplication-Sign 4 array, pixel size: 3 mm Multiplication-Sign 3 mm) coupled 1:1 with LYSO scintillators (4 Multiplication-Sign 4 array, pixel size: 3 mm Multiplication-Sign 3 mm Multiplication-Sign 20 mm) has been developed for simultaneous PET/MRI imaging in our laboratory. Eighteen 64:1 position decoder circuits (PDCs) were used to reduce GAPD channel number and three off-the-shelf free-running ADC and field programmable gate array (FPGA) combined data acquisition (DAQ) cards were used for data acquisition and processing. In this study, a free-running ADC- and FPGA-based signal processing method was developed for the detection of gamma ray signal arrival time, energy and position information all together for each GAPD channel. For the method developed herein, three DAQ cards continuously acquired 18 channels of pre-amplified analog gamma ray signals and 108-bit digital addresses from 18 PDCs. In the FPGA, the digitized gamma ray pulses and digital addresses were processed to generate data packages containing pulse arrival time, baseline value, energy value and GAPD channel ID. Finally, these data packages were saved to a 128 Mbyte on-board synchronous dynamic random access memory (SDRAM) and

  14. An optimization of the FPGA trigger based on the artificial neural network for a detection of neutrino-origin showers

    Energy Technology Data Exchange (ETDEWEB)

    Szadkowski, Zbigniew; Glas, Dariusz [University of Lodz, Department of Physics and Applied Informatics, Faculty of High-Energy Astrophysics, 90-236 Lodz, Pomorska 149, (Poland); Pytel, Krzysztof [University of Lodz, Department of Physics and Applied Informatics, Faculty of Informatics, 90-236 Lodz, (Poland)

    2015-07-01

    Observations of ultra-high energy neutrinos became a priority in experimental astro-particle physics. Up to now, the Pierre Auger Observatory did not find any candidate on a neutrino event. This imposes competitive limits to the diffuse flux of ultra-high energy neutrinos in the EeV range and above. A very low rate of events potentially generated by neutrinos is a significant challenge for a detection technique and requires both sophisticated algorithms and high-resolution hardware. A trigger based on a artificial neural network was implemented into the Cyclone{sup R} V E FPGA 5CEFA9F31I7. The prototype Front-End boards for Auger-Beyond-2015 with Cyclone{sup R} V E can test the neural network algorithm in real pampas conditions in 2015. Showers for muon and tau neutrino initiating particles on various altitudes, angles and energies were simulated in CORSICA and Offline platforms giving pattern of ADC traces in Auger water Cherenkov detectors. The 3-layer 12-10-1 neural network was taught in MATLAB by simulated ADC traces according the Levenberg-Marquardt algorithm. Results show that a probability of a ADC traces generation is very low due to a small neutrino cross-section. Nevertheless, ADC traces, if occur, for 1-10 EeV showers are relatively short and can be analyzed by 16-point input algorithm. For 100 EeV range traces are much longer, but with significantly higher amplitudes, which can be detected by standard threshold algorithms. We optimized the coefficients from MATLAB to get a maximal range of potentially registered events and for fixed-point FPGA processing to minimize calculation errors. Currently used Front-End boards based on no-more produced ACEXR PLDs and obsolete Cyclone{sup R} FPGAs allow an implementation of relatively simple threshold algorithms for triggers. New sophisticated trigger implemented in Cyclone{sup R} V E FPGAs with large amount of DSP blocks, embedded memory running with 120 - 160 MHz sampling may support to discover neutrino events

  15. Genetic algorithm-based neural network for accidents diagnosis of research reactors on FPGA

    International Nuclear Information System (INIS)

    Ghuname, A.A.A.

    2012-01-01

    the efficiency of using genetic algorithm, which can construct the high performance neural network structure for recognizing the Nuclear Research Reactors accidents patterns.The third part is concerned with the hardware implementation of an artificial neural network that had obtained from Genetic Algorithm (GA) using MATLAB's toolbox. The excellent hardware performance has been performed through the use of field programmable gate array (FPGA), on Xilinx chip, to diagnosis the Multi-Purpose Research Reactor of Egypt (MPR) accidents patterns, to avoid the risk of occurrence of a nuclear accident. The artificial neural network hardware model has been designed using Xilinx Software environment. Hardware implementation results presented unfold the promise of the hardware implementation of artificial neural networks for improving the operating performance of the Nuclear Research Reactors.

  16. An FPGA based track finder for the L1 trigger of the CMS experiment at the High Luminosity LHC

    CERN Document Server

    Tomalin, Ian; Ball, Fionn Amhairghen; Balzer, Matthias Norbert; Boudoul, Gaelle; Brooke, James John; Caselle, Michele; Calligaris, Luigi; Cieri, Davide; Clement, Emyr John; Dutta, Suchandra; Hall, Geoffrey; Harder, Kristian; Hobson, Peter; Iles, Gregory Michiel; James, Thomas Owen; Manolopoulos, Konstantinos; Matsushita, Takashi; Morton, Alexander; Newbold, David; Paramesvaran, Sudarshan; Pesaresi, Mark Franco; Pozzobon, Nicola; Reid, Ivan; Rose, A. W; Sander, Oliver; Shepherd-Themistocleous, Claire; Shtipliyski, Antoni; Schuh, Thomas; Skinnari, Louise; Summers, Sioni Paris; Tapper, Alexander; Thea, Alessandro; Uchida, Kirika; Vichoudis, Paschalis; Viret, Sebastien; Weber, M; Aggleton, Robin Cameron

    2017-12-14

    A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial requirement of this upgrade is to provide the ability to reconstruct all charged particle tracks with transverse momentum above 2-3 GeV within 4$\\mu$s so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the Hough Transform, followed by a combinatorial Kalman Filter. A hardware demonstrator using MP7 processing boards has been assembled to prove the entire system functionality, from the output of the tracker readout boards to the reconstruction of tracks with fitted helix parameters. It successfully operates on one eighth of the tracker solid angle acceptance at a time, processing events taken at 40 MHz, each with up to 200 superimposed proton-proton interactions, whilst satisfying the latency requirement. ...

  17. An FPGA Based Implementation for Real-Time Processing of the LHC Beam Loss Monitoring System's Data

    CERN Document Server

    Dehning, B; Emery, J; Ferioli, G; Zamantzas, C

    2006-01-01

    The strategy for machine protection and quench prevention of the Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is mainly based on the Beam Loss Monitoring (BLM) system. At each turn, there will be several thousands of data to record and process in order to decide if the beams should be permitted to continue circulating or their safe extraction is necessary to be triggered. The processing involves a proper analysis of the loss pattern in time and for the decision the energy of the beam needs to be accounted. This complexity needs to be minimized by all means to maximize the reliability of the BLM system and allow a feasible implementation. In this paper, a field programmable gate array (FPGA) based implementation is explored for the real-time processing of the LHC BLM data. It gives emphasis on the highly efficient Successive Running Sums (SRS) technique used that allows many and long integration periods to be maintained for each detector's data with relatively small leng...

  18. Tethered Forth system for FPGA applications

    Science.gov (United States)

    Goździkowski, Paweł; Zabołotny, Wojciech M.

    2013-10-01

    This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

  19. A novel digitization scheme with FPGA-base TDC for beam loss monitors operating at cryogenic temperature

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; Warner, Arden; /Fermilab

    2011-11-01

    Recycling integrators are common current-to-frequency converting circuits for measurements of low current such as that produced by Fermilab's cryogenic ionization chambers. In typical digitization/readout schemes, a counter is utilized to accumulate the number of pulses generated by the recycling integrator to adequately digitize the total charge. In order to calculate current with reasonable resolution (e.g., 7-8 bits), hundreds of pulses must be accumulated which corresponds to a long sampling period, i.e., a very low sampling rate. In our new scheme, an FPGA-based Time-to-Digital Convertor (TDC) is utilized to measure the time intervals between the pulses output from the recycling integrator. Using this method, a sample point of the current can be made with good resolution (>10 bits) for each pulse. This effectively increases the sampling rates by hundreds of times for the same recycling integrator front-end electronics. This scheme provides a fast response to the beams loss and is potentially suitable for accelerator protection applications. Moreover, the method is also self-zero-suppressed, i.e., it produces more data when the beam loss is high while it produces significantly less data when the beam loss is low.

  20. Digital Controller Development Methodology Based on Real-Time Simulations with LabVIEW FPGA Hardware-Software Toolset

    Directory of Open Access Journals (Sweden)

    Tommaso Caldognetto

    2013-12-01

    Full Text Available In this paper, we exemplify the use of NI Lab-VIEW FPGA as a rapid prototyping environment for digital controllers. In our power electronics laboratory, it has been successfully employed in the development, debugging, and test of different power converter controllers for microgrid applications.The paper shows how this high level programming language,together with its target hardware platforms, including CompactRIO and Single Board RIO systems, allows researchers and students to develop even complex applications in reasonable times. The availability of efficient drivers for the considered hardware platforms frees the users from the burden of low level programming. At the same time, the high level programming approach facilitates software re-utilization, allowing the laboratory know-how to steadily grow along time. Furthermore, it allows hardware-in-the-loop real-time simulation, that proved to be effective, and safe, in debugging even complex hardware and software co-designed controllers. To illustrate the effectiveness of these hardware-software toolsets and of the methodology based upon them, two case studies are

  1. FPGA-based upgrade of the read-out electronics for the low energy polarimeter at the cooler synchrotron

    Energy Technology Data Exchange (ETDEWEB)

    Hempelmann, Nils [Institut fuer Kernphysik, Forschungszentrum Juelich (Germany); Collaboration: JEDI-Collaboration

    2015-07-01

    The Cooler Synchrotron (COSY) is a storage ring used for experiments with polarized proton and deuteron beams. The low energy polarimeter is used to determine the vector and tensor polarization of the beam before injection at kinetic energies up to 45 MeV for protons and 75 MeV for deuterons. The polarimeter uses scintillators to measure the energy of both outgoing particles of a scattering reaction and the time between their detection. The present read-out electronics consists of analog NIM modules and is limited in terms of time resolution and the capability for online data analysis. The read-out electronics will be replaced with a a new system based on analog pulse sampling and an FPGA chip for logic operations. The new system will be able to measure the time at which particles arrive to a precision better than 50 ps, facilitating better background reduction using coincidence measurement. In addition to measuring the beam polarization, the system will be used to precisely determine the vector and tensor analyzing powers for deuteron scattering off carbon at a kinetic energy of 75 MeV.

  2. Desgin of On-line Monitoring Device for MOA (Metal Oxide Arrestor Based on FPGA and C8051F

    Directory of Open Access Journals (Sweden)

    Xiaotong YAO

    2014-10-01

    Full Text Available Monitoring of metal oxide surge arresters (MOA due to aging, moisture and other components cause increased resistive current. Through a lot of practices, it has been proved that in the early days, MOA insulation damage and current increase is not obvious. The accurate working conditions of the MOA are also not obvious but it can reflect the aging or moisture of MOA. When the resistive current of the fundamental component increases, there is no increment in the harmonic components that is the general performance of a serious or moisture contamination. In the same way when the resistive current of harmonic components increases, the fundamental component is not increased and it is the general performance of aging. Therefore, this paper designed an experiment-based FPGA and C8051F-line monitoring device. This device uses resistive current as a detection target. The main monitoring parameters are the fundamental and peak value of resistive current, third harmonic content of the leakage current, phase angle difference and power consumption. Through laboratory tests, the device can be used with a network arrester line monitoring, maintenance, reduce the economic losses caused by power outages and improve the distribution network reliability.

  3. Protection and Control with FPGA technology

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-03-15

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

  4. Protection and Control with FPGA technology

    International Nuclear Information System (INIS)

    Sohn, K. Y.; Yi, W. J.; Koo, I. S.

    2012-01-01

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper

  5. An Efficient, FPGA-Based, Cluster Detection Algorithm Implementation for a Strip Detector Readout System in a Time Projection Chamber Polarimeter

    Science.gov (United States)

    Gregory, Kyle J.; Hill, Joanne E. (Editor); Black, J. Kevin; Baumgartner, Wayne H.; Jahoda, Keith

    2016-01-01

    A fundamental challenge in a spaceborne application of a gas-based Time Projection Chamber (TPC) for observation of X-ray polarization is handling the large amount of data collected. The TPC polarimeter described uses the APV-25 Application Specific Integrated Circuit (ASIC) to readout a strip detector. Two dimensional photoelectron track images are created with a time projection technique and used to determine the polarization of the incident X-rays. The detector produces a 128x30 pixel image per photon interaction with each pixel registering 12 bits of collected charge. This creates challenging requirements for data storage and downlink bandwidth with only a modest incidence of photons and can have a significant impact on the overall mission cost. An approach is described for locating and isolating the photoelectron track within the detector image, yielding a much smaller data product, typically between 8x8 pixels and 20x20 pixels. This approach is implemented using a Microsemi RT-ProASIC3-3000 Field-Programmable Gate Array (FPGA), clocked at 20 MHz and utilizing 10.7k logic gates (14% of FPGA), 20 Block RAMs (17% of FPGA), and no external RAM. Results will be presented, demonstrating successful photoelectron track cluster detection with minimal impact to detector dead-time.

  6. FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments

    CERN Document Server

    Pozniak, Krzysztof T

    2004-01-01

    The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY) . A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.

  7. Template characterization and correlation algorithm created from segmentation for the iris biometric authentication based on analysis of textures implemented on a FPGA

    International Nuclear Information System (INIS)

    Giacometto, F J; Vilardy, J M; Torres, C O; Mattos, L

    2011-01-01

    Among the most used biometric signals to set personal security permissions, taker increasingly importance biometric iris recognition based on their textures and images of blood vessels due to the rich in these two unique characteristics that are unique to each individual. This paper presents an implementation of an algorithm characterization and correlation of templates created for biometric authentication based on iris texture analysis programmed on a FPGA (Field Programmable Gate Array), authentication is based on processes like characterization methods based on frequency analysis of the sample, and frequency correlation to obtain the expected results of authentication.

  8. An FPGA based control unit for synchronization of laser Thomson scattering measurements to plasma events on MAST

    International Nuclear Information System (INIS)

    Naylor, G.A.

    2010-01-01

    The power and flexibility of modern Field Programmable Gate Arrays (FPGAs) is now being recognised in many areas of instrumentation and control . The high performance of modern ADCs and the high throughput of FPGAs allow the emulation of many specialised analogue instruments. The functions of heterodyne detection, phase measurements, spectrum analyzers, phase sensitive detectors, counters, etc. can be achieved in relatively simple hardware using an FPGA. The complex filtering functions can be efficiently performed digitally in the FPGA, without recourse to a separate DSP chip. This paper describes the use of a custom off the shelf FPGA board with a collection of custom interface boards to produce a powerful custom trigger system. This has been developed for agile triggering of YAG lasers on MAST. This unit allows various analogue inputs including magnetics data to be processed in real-time and allow Thomson scattering data to be collected at accurate times with respect to randomly occurring MHD phenomena such as neoclassical tearing modes (NTMs). The FPGA allows a 'System On a Chip' architecture in order to perform fast filtering in logic coupled to a dedicated soft processor for real-time fixed latency operations and a second soft processor to handle external communications with the control system for system configuration and reporting of status/archived data. The use of such a generic structure in order to provide a common approach, with reduced software development times, for diverse diagnostic situations will be discussed.

  9. Optimization of an FPGA Trigger Based on an Artificial Neural Network for the Detection of Neutrino-Induced Air Showers

    Science.gov (United States)

    Szadkowski, Zbigniew; Głas, Dariusz; Pytel, Krzysztof; Wiedeński, Michał

    2017-06-01

    Neutrinos play a fundamental role in the understanding of the origin of ultrahigh-energy cosmic rays. They interact through charged and neutral currents in the atmosphere generating extensive air showers. However, the very low rate of events potentially generated by neutrinos is a significant challenge for detection techniques and requires both sophisticated algorithms and high-resolution hardware. Air showers initiated by protons and muon neutrinos at various altitudes, angles, and energies were simulated in CORSIKA and the Auger OffLine event reconstruction platforms, giving analog-to-digital convertor (ADC) patterns in Auger water Cherenkov detectors on the ground. The proton interaction cross section is high, so proton “old” showers start their development early in the atmosphere. In contrast to this, neutrinos can generate “young” showers deeply in the atmosphere relatively close to the detectors. Differences between “old” proton and “young” neutrino showers are visible in attenuation factors of ADC waveforms. For the separation of “old” proton and “young” neutrino ADC traces, many three-layer artificial neural networks (ANNs) were tested. They were trained in MATLAB (in a dedicated way -only “old” proton and “young” neutrino showers as patterns) by simulated ADC traces according to the Levenberg-Marquardt algorithm. Unexpectedly, the recognition efficiency is found to be almost independent of the size of the networks. The ANN trigger based on a selected 8-6-1 network was tested in the Cyclone V E FPGA 5CEFA9F31I7, the heart of prototype front-end boards developed for testing new algorithms in the Pierre Auger surface detectors.

  10. An FPGA-based trigger processor for a measurement of deeply virtual Compton scattering at the COMPASS-II experiment

    Energy Technology Data Exchange (ETDEWEB)

    Schopferer, Sebastian

    2013-12-16

    The COMPASS-II experiment at CERN is focusing on a measurement of the deeply virtual Compton scattering. Several upgrades of the experimental setup have been performed in 2012, namely the construction of a long liquid hydrogen target and a surrounding recoil proton detector called CAMERA. Based on a time-of-flight measurement between two barrels of scintillators, the CAMERA detector allows to detect protons with a kinetic energy down to 35 MeV, which leave the target under large polar angles. At the same time, protons can be distinguished from other particles resulting from background processes by means of an energy loss measurement in the scintillating material. In order to extend the existing COMPASS trigger scheme, a digital trigger system has been developed, which is detailed in the thesis at hand. The trigger system is able to select events with a recoil proton in the final state while suppressing background events, using the particle identification capabilities of the CAMERA detector. Challenging selection criteria based on both the time-of-flight and the energy loss measurement call for a powerful programmable logic board. At the same time, the integration into the existing COMPASS trigger system poses strict constraints on the latency of the trigger decision. For the implementation of the proton trigger system, a new FPGA-based trigger and DAQ hardware called TIGER has been built. The module is operated in two firmware configurations, serving two distinct purposes. Firstly, the trigger processor is responsible for the generation of a trigger signal based on recoil particles, which is included in the global first-level trigger decision. Secondly, a readout concentrator allows to multiplex the data streams of up to 18 readout modules into one link to the DAQ. The CAMERA detector and the corresponding readout and trigger electronics was commissioned during a test run in autumn 2012. This thesis contains details about the trigger concept, the development of the

  11. Susceptibility of Redundant Versus Singular Clock Domains Implemented in SRAM-Based FPGA TMR Designs

    Science.gov (United States)

    Berg, Melanie D.; LaBel, Kenneth A.; Pellish, Jonathan

    2016-01-01

    We present the challenges that arise when using redundant clock domains due to their clock-skew. Radiation data show that a singular clock domain (DTMR) provides an improved TMR methodology for SRAM-based FPGAs over redundant clocks.

  12. Implementation of FPGA-Based Charge Control for a Self-Sufficient Solar Tracking Power Supply System

    Directory of Open Access Journals (Sweden)

    Jui-Ho Chen

    2016-02-01

    Full Text Available This study used a field-programmable gate array (FPGA with a Xilinx Spartan-3 FPGA to implement Reflex charge control in a dual-axis solar tracking system with maximum power point tracking (MPPT. The chaos embedded particle swarm optimization method was used to search for the optimum gain constants of the PI controller and the Reflex charging frequency. This scheme not only increases the output power of solar panels but also has a significant effect on switching loss and oscillation of solar charging. The experiment results showed that the proposed method can also significantly improve temperature rise, and that charging efficiency is also better than it is in a traditional charge mode. The results also showed that charging power was enough for solar tracking and the requirements of the charging system. The most significant contribution of this paper is that the scheme can be applied to any active solar tracking and charging system.

  13. FPGA-based electrocardiography (ECG signal analysis system using least-square linear phase finite impulse response (FIR filter

    Directory of Open Access Journals (Sweden)

    Mohamed G. Egila

    2016-12-01

    Full Text Available This paper presents a proposed design for analyzing electrocardiography (ECG signals. This methodology employs highpass least-square linear phase Finite Impulse Response (FIR filtering technique to filter out the baseline wander noise embedded in the input ECG signal to the system. Discrete Wavelet Transform (DWT was utilized as a feature extraction methodology to extract the reduced feature set from the input ECG signal. The design uses back propagation neural network classifier to classify the input ECG signal. The system is implemented on Xilinx 3AN-XC3S700AN Field Programming Gate Array (FPGA board. A system simulation has been done. The design is compared with some other designs achieving total accuracy of 97.8%, and achieving reduction in utilizing resources on FPGA implementation.

  14. Computer vision camera with embedded FPGA processing

    Science.gov (United States)

    Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

    2000-03-01

    Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

  15. FPGA based computation of average neutron flux and e-folding period for start-up range of reactors

    International Nuclear Information System (INIS)

    Ram, Rajit; Borkar, S.P.; Dixit, M.Y.; Das, Debashis

    2013-01-01

    Pulse processing instrumentation channels used for reactor applications, play a vital role to ensure nuclear safety in startup range of reactor operation and also during fuel loading and first approach to criticality. These channels are intended for continuous run time computation of equivalent reactor core neutron flux and e-folding period. This paper focuses only the computational part of these instrumentation channels which is implemented in single FPGA using 32-bit floating point arithmetic engine. The computations of average count rate, log of average count rate, log rate and reactor period are done in VHDL using digital circuit realization approach. The computation of average count rate is done using fully adaptive window size moving average method, while Taylor series expansion for logarithms is implemented in FPGA to compute log of count rate, log rate and reactor e-folding period. This paper describes the block diagrams of digital logic realization in FPGA and advantage of fully adaptive window size moving average technique over conventional fixed size moving average technique for pulse processing of reactor instrumentations. (author)

  16. Development of An Embedded FPGA-Based Data Acquisition System Dedicated to Zero Power Reactor Noise Experiments

    Directory of Open Access Journals (Sweden)

    Arkani Mohammad

    2014-08-01

    Full Text Available An embedded time interval data acquisition system (DAS is developed for zero power reactor (ZPR noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA. The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.

  17. Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy

    NARCIS (Netherlands)

    Glein, Robert; Rittner, Florian; Becher, Andreas; Ziener, Daniel; Frickel, Jürgen; Teich, Jürgen; Heuberger, Albert

    2015-01-01

    In this paper, we evaluate the suitability of different SRAM-based FPGAs for harsh radiation environments (e.g., space). In particular, we compare the space-grade and radiation-hardened by design Virtex-5QV (XQR5VFX130) with the commercial off-the-shelf Kintex-7 (KC7K325T) from Xilinx. The

  18. Automatic generation of application specific FPGA multicore accelerators

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

    2014-01-01

    High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

  19. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    -the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

  20. 2-Dimension pulse shape discriminator for phoswich detector based on FPGA

    International Nuclear Information System (INIS)

    Ji Jianfeng; Liu Congzhan; Zhang Zhi

    2011-01-01

    It improves the data acquire system for the pulse signal based on digital front-rear pulse shape discrimination system. It adds pulse width information into the pulse's data package. Base on this, we divide the pulse event process into two process, on line coast process and offline accurate process: the online process sets a big threshold, just save the data of the event below this threshold; the offline process uses the acquired data, get the pulse amplitude and pulse width, and then according the spectrum's real shape, set the accurate threshold. this design resolves the problem that the detector's decay time change with the temperature; at the same time, it can correct the system's distortion when the input signal at small amplitude, improves the discrimination system's accuracy. (authors)

  1. Development of an FPGA Based Embedded System for High Speed Object Tracking

    Directory of Open Access Journals (Sweden)

    Chandrashekar MATHAM

    2010-01-01

    Full Text Available This paper deals with the development and implementation of system on chip (SOC for object tracking using histograms. To acquire the distance and velocity information of moving vehicles such as military tanks, to identify the type of target within the range from 100 m to 3 km and to estimate the movements of the vehicle. The VHDL code is written for the above objectives and implemented using Xilinx’s VERTEX-4 based PCI card family.

  2. FPGA-Based Stochastic Echo State Networks for Time-Series Forecasting.

    Science.gov (United States)

    Alomar, Miquel L; Canals, Vincent; Perez-Mora, Nicolas; Martínez-Moll, Víctor; Rosselló, Josep L

    2016-01-01

    Hardware implementation of artificial neural networks (ANNs) allows exploiting the inherent parallelism of these systems. Nevertheless, they require a large amount of resources in terms of area and power dissipation. Recently, Reservoir Computing (RC) has arisen as a strategic technique to design recurrent neural networks (RNNs) with simple learning capabilities. In this work, we show a new approach to implement RC systems with digital gates. The proposed method is based on the use of probabilistic computing concepts to reduce the hardware required to implement different arithmetic operations. The result is the development of a highly functional system with low hardware resources. The presented methodology is applied to chaotic time-series forecasting.

  3. Implementation and Performance of FPGA based track fitting for the Atlas Fast TracKer

    CERN Document Server

    Zou, Rui; The ATLAS collaboration

    2018-01-01

    The Fast TracKer (FTK) within the ATLAS trigger system provides global track reconstruction for all events passing the ATLAS Level 1 trigger by dividing the detector into parallel processing pipelines that implement pattern matching in custom integrated circuits and data routing, reduction, and parameter extraction in FPGAs. In this presentation we will describe the implementation of a critical component of the system which does partial track fitting using a method based on a principal component analysis at a rate of greater than 1 fit per 10 ps, system-wide, to reduce the output of the pattern matching. Firmware design, timing performance and preliminary results will be discussed.

  4. A FPGA-based identity authority method in quantum key distribution system

    International Nuclear Information System (INIS)

    Cui Ke; Luo Chunli; Zhang Hongfei; Lin Shengzhao; Jin Ge; Wang Jian

    2012-01-01

    In this article, an identity authority method realized in hardware is developed which is used in quantum key distribution (QKD) systems. This method is based on LFSR-Teoplitz hashing matrix. Its benefits relay on its easy implementation in hardware and high secure coefficient. It can gain very high security by means of splitting part of the final key generated from QKD systems as the seed where it is required in the identity authority method. We propose an specific flow of the identity authority method according to the problems and features of the hardware. The proposed method can satisfy many kinds of QKD systems. (authors)

  5. An Efficient Digital Pulse Shape Discrimination Technique for Scintillation Detectors Based on FPGA

    International Nuclear Information System (INIS)

    Kamel, M.S.

    2014-01-01

    Different techniques for pulse discrimination (PSD) of the scintillation pulses have been developed. The PSD of scintillation pulese can been used in several applications as Positron Emission Topography (PET) system. Each technique analyzes the resulting pulses from the absorption of radiation in the scintillation pulses were filtered and digitized then it is captured using DAQ, and it sent to the host computer for processing. The spatial resolution of images that generated in PET system can be improved by applying the proposed PSD. In this thesis various digital PSD techniques are proposed to discriminate the scintillation pulses. These techniques are based on discrete sine transform (DST). discrete cosine transform (DCT). Discrete hartley transform (DHT), Discrete Goertzel transform (DGT),and principal component analysis (PCA). Then the output coefficients of the discrete transforms are classified using one of the following classifiers T-test,tuned, or support vector machine (SVM).

  6. FPGA-Based Stochastic Echo State Networks for Time-Series Forecasting

    Directory of Open Access Journals (Sweden)

    Miquel L. Alomar

    2016-01-01

    Full Text Available Hardware implementation of artificial neural networks (ANNs allows exploiting the inherent parallelism of these systems. Nevertheless, they require a large amount of resources in terms of area and power dissipation. Recently, Reservoir Computing (RC has arisen as a strategic technique to design recurrent neural networks (RNNs with simple learning capabilities. In this work, we show a new approach to implement RC systems with digital gates. The proposed method is based on the use of probabilistic computing concepts to reduce the hardware required to implement different arithmetic operations. The result is the development of a highly functional system with low hardware resources. The presented methodology is applied to chaotic time-series forecasting.

  7. A low dead time vernier delay line TDC implemented in an Actel flash-based FPGA

    International Nuclear Information System (INIS)

    Qin Xi; Feng Changqing; Zhang Deliang; Zhao Lei; Liu Shubin; An Qi

    2013-01-01

    In this paper, a high precision vernier delay line (VDL) TDC (Time-to-Digital Converter) in an Actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented, achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size. The TDC has a dead time of about 200 ns while the dynamic range is 655.36 Vs. The double delay lines method is employed to cut the dead time in half to improve its performance. As the bin size of the TDC is dependent on temperature, a compensation algorithm is adopted as temperature drift correction, and the TDC shows satisfying performance in a temperature range from -5℃ to +55℃. (authors)

  8. FPGA-based multimodal embedded sensor system integrating low- and mid-level vision.

    Science.gov (United States)

    Botella, Guillermo; Martín H, José Antonio; Santos, Matilde; Meyer-Baese, Uwe

    2011-01-01

    Motion estimation is a low-level vision task that is especially relevant due to its wide range of applications in the real world. Many of the best motion estimation algorithms include some of the features that are found in mammalians, which would demand huge computational resources and therefore are not usually available in real-time. In this paper we present a novel bioinspired sensor based on the synergy between optical flow and orthogonal variant moments. The bioinspired sensor has been designed for Very Large Scale Integration (VLSI) using properties of the mammalian cortical motion pathway. This sensor combines low-level primitives (optical flow and image moments) in order to produce a mid-level vision abstraction layer. The results are described trough experiments showing the validity of the proposed system and an analysis of the computational resources and performance of the applied algorithms.

  9. SSTL Based Low Power Thermal Efficient WLAN Specific 32bit ALU Design on 28nm FPGA

    DEFF Research Database (Denmark)

    Kalia, Kartik; Pandey, Bishwajeet; Das, Teerath

    2016-01-01

    at minimum and maximum temperature as compared to all other considered I/O standards. This design has application where 32bit ALU design is considered for designing an electronic device such as WLAN. The design can be implemented on different nano chips for better efficiency depending upon the design...... with consideration of airflow toward hit sink and different frequency on which ALU operate in network processor or any WLAN devices. We have done total power analysis of WLAN operating on different frequencies. We have considered a set of frequencies, which are based on IEEE 802.11 standards. First we did...... efficient IO standard. While analyzing we found out that when WLAN device shift from 343.15K to 283.15K, there is maximum thermal power reduction in SSTL135_R as compared to all considered I/O standards. When we compared same I/Os for different frequencies we observed maximum thermal efficiency in SSTL15...

  10. Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

    International Nuclear Information System (INIS)

    Magazzù, G; Borgese, G; Costantino, N; Fanucci, L; Saponara, S; Incandela, J

    2013-01-01

    In many research fields as high energy physics (HEP), astrophysics, nuclear medicine or space engineering with harsh operating conditions, the use of fast and flexible digital communication protocols is becoming more and more important. The possibility to have a smart and tested top-down design flow for the design of a new protocol for control/readout of front-end electronics is very useful. To this aim, and to reduce development time, costs and risks, this paper describes an innovative design/verification flow applied as example case study to a new communication protocol called FF-LYNX. After the description of the main FF-LYNX features, the paper presents: the definition of a parametric SystemC-based Integrated Simulation Environment (ISE) for high-level protocol definition and validation; the set up of figure of merits to drive the design space exploration; the use of ISE for early analysis of the achievable performances when adopting the new communication protocol and its interfaces for a new (or upgraded) physics experiment; the design of VHDL IP cores for the TX and RX protocol interfaces; their implementation on a FPGA-based emulator for functional verification and finally the modification of the FPGA-based emulator for testing the ASIC chipset which implements the rad-tolerant protocol interfaces. For every step, significant results will be shown to underline the usefulness of this design and verification approach that can be applied to any new digital protocol development for smart detectors in physics experiments.

  11. Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

    Science.gov (United States)

    Magazzù, G.; Borgese, G.; Costantino, N.; Fanucci, L.; Incandela, J.; Saponara, S.

    2013-02-01

    In many research fields as high energy physics (HEP), astrophysics, nuclear medicine or space engineering with harsh operating conditions, the use of fast and flexible digital communication protocols is becoming more and more important. The possibility to have a smart and tested top-down design flow for the design of a new protocol for control/readout of front-end electronics is very useful. To this aim, and to reduce development time, costs and risks, this paper describes an innovative design/verification flow applied as example case study to a new communication protocol called FF-LYNX. After the description of the main FF-LYNX features, the paper presents: the definition of a parametric SystemC-based Integrated Simulation Environment (ISE) for high-level protocol definition and validation; the set up of figure of merits to drive the design space exploration; the use of ISE for early analysis of the achievable performances when adopting the new communication protocol and its interfaces for a new (or upgraded) physics experiment; the design of VHDL IP cores for the TX and RX protocol interfaces; their implementation on a FPGA-based emulator for functional verification and finally the modification of the FPGA-based emulator for testing the ASIC chipset which implements the rad-tolerant protocol interfaces. For every step, significant results will be shown to underline the usefulness of this design and verification approach that can be applied to any new digital protocol development for smart detectors in physics experiments.

  12. Reliable and redundant FPGA based read-out design in the ATLAS TileCal Demonstrator

    CERN Document Server

    Åkerstedt, Henrik; The ATLAS collaboration; Drake, Gary; Anderson, Kelby; Bohm, Christian; Oreglia, Mark; Tang, Fukun

    2015-01-01

    The Tile Calorimeter at ATLAS is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector. However, only a subset of the data is actually read out to the counting room. The on-detector electronics will be replaced around 2023. To achieve the required reliability the upgraded system will be highly redundant. Here the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links, will allow a full read-out of all detector data. Due to the higher radiation levels expected when the beam luminosity is increased, opportunities for repairs will be less frequent. The circuitry and firmware must therefore be designed for sufficiently high reliability using redundancy and radiation tolerant components. Within a year, a hybrid demonstrator including the new read-out system will be installed in one slice of ...

  13. FPGA-based Fused Smart Sensor for Real-Time Plant-Transpiration Dynamic Estimation

    Directory of Open Access Journals (Sweden)

    Irineo Torres-Pacheco

    2010-09-01

    Full Text Available Plant transpiration is considered one of the most important physiological functions because it constitutes the plants evolving adaptation to exchange moisture with a dry atmosphere which can dehydrate or eventually kill the plant. Due to the importance of transpiration, accurate measurement methods are required; therefore, a smart sensor that fuses five primary sensors is proposed which can measure air temperature, leaf temperature, air relative humidity, plant out relative humidity and ambient light. A field programmable gate array based unit is used to perform signal processing algorithms as average decimation and infinite impulse response filters to the primary sensor readings in order to reduce the signal noise and improve its quality. Once the primary sensor readings are filtered, transpiration dynamics such as: transpiration, stomatal conductance, leaf-air-temperature-difference and vapor pressure deficit are calculated in real time by the smart sensor. This permits the user to observe different primary and calculated measurements at the same time and the relationship between these which is very useful in precision agriculture in the detection of abnormal conditions. Finally, transpiration related stress conditions can be detected in real time because of the use of online processing and embedded communications capabilities.

  14. FPGA-based Fused Smart Sensor for Real-Time Plant-Transpiration Dynamic Estimation

    Science.gov (United States)

    Millan-Almaraz, Jesus Roberto; de Jesus Romero-Troncoso, Rene; Guevara-Gonzalez, Ramon Gerardo; Contreras-Medina, Luis Miguel; Carrillo-Serrano, Roberto Valentin; Osornio-Rios, Roque Alfredo; Duarte-Galvan, Carlos; Rios-Alcaraz, Miguel Angel; Torres-Pacheco, Irineo

    2010-01-01

    Plant transpiration is considered one of the most important physiological functions because it constitutes the plants evolving adaptation to exchange moisture with a dry atmosphere which can dehydrate or eventually kill the plant. Due to the importance of transpiration, accurate measurement methods are required; therefore, a smart sensor that fuses five primary sensors is proposed which can measure air temperature, leaf temperature, air relative humidity, plant out relative humidity and ambient light. A field programmable gate array based unit is used to perform signal processing algorithms as average decimation and infinite impulse response filters to the primary sensor readings in order to reduce the signal noise and improve its quality. Once the primary sensor readings are filtered, transpiration dynamics such as: transpiration, stomatal conductance, leaf-air-temperature-difference and vapor pressure deficit are calculated in real time by the smart sensor. This permits the user to observe different primary and calculated measurements at the same time and the relationship between these which is very useful in precision agriculture in the detection of abnormal conditions. Finally, transpiration related stress conditions can be detected in real time because of the use of online processing and embedded communications capabilities. PMID:22163656

  15. Burst-Mode Asynchronous Controllers on FPGA

    Directory of Open Access Journals (Sweden)

    Duarte L. Oliveira

    2008-01-01

    Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

  16. A pattern recognition mezzanine based on associative memory and FPGA technology for L1 track triggering at HL-LHC

    International Nuclear Information System (INIS)

    Alunni, L.; Biesuz, N.; Bilei, G.M.; Citraro, S.; Crescioli, F.; Fanò, L.; Fedi, G.; Magalotti, D.; Magazzù, G.; Servoli, L.; Storchi, L.; Palla, F.; Placidi, P.; Papi, A.; Piadyk, Y.; Rossi, E.; Spiezia, A.

    2016-01-01

    The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We present the tests of a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.

  17. A pattern recognition mezzanine based on associative memory and FPGA technology for L1 track triggering at HL-LHC

    Science.gov (United States)

    Alunni, L.; Biesuz, N.; Bilei, G. M.; Citraro, S.; Crescioli, F.; Fanò, L.; Fedi, G.; Magalotti, D.; Magazzù, G.; Servoli, L.; Storchi, L.; Palla, F.; Placidi, P.; Papi, A.; Piadyk, Y.; Rossi, E.; Spiezia, A.

    2016-07-01

    The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We present the tests of a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.

  18. A pattern recognition mezzanine based on associative memory and FPGA technology for L1 track triggering at HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Alunni, L. [INFN Sezione di Perugia (Italy); Biesuz, N. [INFN Sezione di Pisa (Italy); Bilei, G.M. [INFN Sezione di Perugia (Italy); Citraro, S. [Università di Pisa, Pisa (Italy); Crescioli, F. [LPNHE, Paris (France); Fanò, L. [INFN Sezione di Perugia (Italy); Fedi, G., E-mail: giacomo.fedi@pi.infn.it [INFN Sezione di Pisa (Italy); Magalotti, D. [INFN Sezione di Perugia (Italy); UNIMORE, Modena (Italy); Magazzù, G. [INFN Sezione di Pisa (Italy); Servoli, L.; Storchi, L. [INFN Sezione di Perugia (Italy); Palla, F. [INFN Sezione di Pisa (Italy); Placidi, P. [INFN Sezione di Perugia (Italy); DIEI, Perugia (Italy); Papi, A. [INFN Sezione di Perugia (Italy); Piadyk, Y. [LPNHE, Paris (France); Rossi, E. [INFN Sezione di Pisa (Italy); Spiezia, A. [IHEP (China)

    2016-07-11

    The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We present the tests of a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.

  19. Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

    Energy Technology Data Exchange (ETDEWEB)

    Anvar, S. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France); Kestener, P. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)]. E-mail: pierre.kestener@cea.fr; Le Provost, H. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)

    2006-11-15

    The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

  20. An FPGA-based slowcontrol module and a baseline shifting extension card for the sampling-ADC readout of the crystal barrel calorimeter

    Energy Technology Data Exchange (ETDEWEB)

    Urff, Georg; Poller, Timo [Helmholtz-Institut fuer Strahlen- und Kernphysik, Bonn (Germany); Collaboration: CBELSA/TAPS-Collaboration

    2016-07-01

    At the electron accelerator ELSA (Bonn) the CBELSA/TAPS experiment investigates the photoproduction of mesons off protons and neutrons. The CsI(Tl)-crystals of the Crystal Barrel calorimeter are being upgraded from a PIN-diode readout to an APD readout. In the context of this upgrade, an FPGA-based Sampling-ADC (SADC) is presently being developed (HK 304). A Slow-control Module for the SADC with TCP/Telnet access has been developed on the basis of a Spartan6 FPGA. Control and monitoring of the SADC's power supply as well as control of parameters of the analog and digital data processing in the SADC is realized via PMBus/I{sup 2}C. The prototype as well as an overview of its functionality will be presented. In order to fully utilize the dynamic input range of the SADCs, an interfacing extension board was designed. It receives the differential signal generated by previous amplification stages and adds an individual DC offset voltage to each channel supplied by a digital-to-analog converter. The circuit and the used techniques as well as simulations and measurements are presented.

  1. Modular version of SIMCON, FPGA based, DSP integrated, LLRF control system for TESLA FEL part II: measurement of SIMCON 3.0 DSP daughterboard

    Science.gov (United States)

    Giergusiewicz, Wojciech; Koprek, Waldemar; Jalmuzna, Wojciech; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.

    2006-02-01

    The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the W-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layer, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACCl module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0. encouraged us to enter the design of SIMCON 3.1. possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0. is a modular solution, while SIMCON 3.1. will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one - after branching off in this version of the Simcon, will be continued.

  2. Area, speed and power measurements of FPGA-based complex orthogonal space-time block code channel encoders

    Science.gov (United States)

    Passas, Georgios; Freear, Steven; Fawcett, Darren

    2010-01-01

    Space-time coding (STC) is an important milestone in modern wireless communications. In this technique, more copies of the same signal are transmitted through different antennas (space) and different symbol periods (time), to improve the robustness of a wireless system by increasing its diversity gain. STCs are channel coding algorithms that can be readily implemented on a field programmable gate array (FPGA) device. This work provides some figures for the amount of required FPGA hardware resources, the speed that the algorithms can operate and the power consumption requirements of a space-time block code (STBC) encoder. Seven encoder very high-speed integrated circuit hardware description language (VHDL) designs have been coded, synthesised and tested. Each design realises a complex orthogonal space-time block code with a different transmission matrix. All VHDL designs are parameterisable in terms of sample precision. Precisions ranging from 4 bits to 32 bits have been synthesised. Alamouti's STBC encoder design [Alamouti, S.M. (1998), 'A Simple Transmit Diversity Technique for Wireless Communications', IEEE Journal on Selected Areas in Communications, 16:55-108.] proved to be the best trade-off, since it is on average 3.2 times smaller, 1.5 times faster and requires slightly less power than the next best trade-off in the comparison, which is a 3/4-rate full-diversity 3Tx-antenna STBC.

  3. FPGA-based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery

    Directory of Open Access Journals (Sweden)

    Zhaorui Zhang

    2016-08-01

    Full Text Available Collision detection, which refers to the computational problem of finding the relative placement or con-figuration of two or more objects, is an essential component of many applications in computer graphics and robotics. In image-guided robotic surgery, real-time collision detection is critical for preserving healthy anatomical structures during the surgical procedure. However, the computational complexity of the problem usually results in algorithms that operate at low speed. In this paper, we present a fast and accurate algorithm for collision detection between Oriented-Bounding-Boxes (OBBs that is suitable for real-time implementation. Our proposed Sweep and Prune algorithm can perform a preliminary filtering to reduce the number of objects that need to be tested by the classical Separating Axis Test algorithm, while the OBB pairs of interest are preserved. These OBB pairs are re-checked by the Separating Axis Test algorithm to obtain accurate overlapping status between them. To accelerate the execution, our Sweep and Prune algorithm is tailor-made for the proposed method. Meanwhile, a high performance scalable hardware architecture is proposed by analyzing the intrinsic parallelism of our algorithm, and is implemented on FPGA platform. Results show that our hardware design on the FPGA platform can achieve around 8X higher running speed than the software design on a CPU platform. As a result, the proposed algorithm can achieve a collision frame rate of 1 KHz, and fulfill the requirement for the medical surgery scenario of Robot Assisted Laparoscopy.

  4. Random number generators for large-scale parallel Monte Carlo simulations on FPGA

    Science.gov (United States)

    Lin, Y.; Wang, F.; Liu, B.

    2018-05-01

    Through parallelization, field programmable gate array (FPGA) can achieve unprecedented speeds in large-scale parallel Monte Carlo (LPMC) simulations. FPGA presents both new constraints and new opportunities for the implementations of random number generators (RNGs), which are key elements of any Monte Carlo (MC) simulation system. Using empirical and application based tests, this study evaluates all of the four RNGs used in previous FPGA based MC studies and newly proposed FPGA implementations for two well-known high-quality RNGs that are suitable for LPMC studies on FPGA. One of the newly proposed FPGA implementations: a parallel version of additive lagged Fibonacci generator (Parallel ALFG) is found to be the best among the evaluated RNGs in fulfilling the needs of LPMC simulations on FPGA.

  5. FPGA Design Methodologies Applicable to Nuclear Power Plants

    International Nuclear Information System (INIS)

    Kwong, Yongil; Jeong, Choongheui

    2013-01-01

    In order to solve the above problem, NPPs in some countries such as the US, Canada and Japan have already applied FPGA-based equipment which has advantages as follows: It is easier to verify the performance because it needs only HDL code to configure logic circuits without other software, compared to microprocessor-based equipment, It is much cheaper than ASIC in a small quantity, Its logic circuits are re configurable, It has enough resources like logic blocks and memory blocks to implement I and C functions, Multiple functions can be implemented in a FPGA chip, It is stronger with respect to carboy security than microprocessor-based equipment because its configuration cannot be changed by external access, It is simple to replace it with new one when it is obsolete, Its power consumption is lower. However, FPGA-based equipment does not have only the merits. There are some issues on its application to NPPs. First of all, the experiences in applying it to NPPs are much less than to other industries, and international standards or guidelines are also very few. And there is the small number of FPGA platforms for I and C systems. Finally, the specific guidelines on FPGA design are required because the design has both hardware and software characteristics. In order to handle the above issues, KINS(Korea Institute of Nuclear Safety) built a test platform last year and have developed regulatory guidelines for FPGA-application in NPPs. I and C systems of NPPs have been increasingly using FPGA-based equipment as an alternative of microprocessor-based equipment which is not simple to be evaluated for safety due to its complexity. This paper explained the FPGA design flow and design guidelines. Those methodologies can be used as the guidelines on FPGA verification for safety of I and C systems

  6. An FPGA-Based WASN for Remote Real-Time Monitoring of Endangered Species: A Case Study on the Birdsong Recognition of Botaurus stellaris.

    Science.gov (United States)

    Hervás, Marcos; Alsina-Pagès, Rosa Ma; Alías, Francesc; Salvador, Martí

    2017-06-08

    Fast environmental variations due to climate change can cause mass decline or even extinctions of species, having a dramatic impact on the future of biodiversity. During the last decade, different approaches have been proposed to track and monitor endangered species, generally based on costly semi-automatic systems that require human supervision adding limitations in coverage and time. However, the recent emergence of Wireless Acoustic Sensor Networks (WASN) has allowed non-intrusive remote monitoring of endangered species in real time through the automatic identification of the sound they emit. In this work, an FPGA-based WASN centralized architecture is proposed and validated on a simulated operation environment. The feasibility of the architecture is evaluated in a case study designed to detect the threatened Botaurus stellaris among other 19 cohabiting birds species in The Parc Natural dels Aiguamolls de l'Empord.

  7. A new architecture for a single-chip multi-channel beamformer based on a standard FPGA

    DEFF Research Database (Denmark)

    Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

    2001-01-01

    ) modulation analog-to-digital converters (ADC). Second, simple second-order ΔΣ modulation ADC with classic topology is used. This allows for simple analog circuitry and a very compact design. Several tens of these together with the corresponding preamplifiers can be fitted together onto a single analog......A new architecture for a compact medical ultrasound beamformer has been developed. Combination of novel and known principles has been utilized, leading to low processing power requirements and simple analog circuitry. Usage of a field programmable gate array (FPGA) for the digital signal processing...... integrated circuit. Third, parameter driven delay generation is used, using 3 input parameters per line per channel for either linear array imaging or phased array imaging. The delays are generated on the fly. The delay generation logic also determines the digital apodization by using 2 additional parameters...

  8. Field programmable gate array (FPGA implementation of novel complex PN-code-generator- based data scrambler and descrambler

    Directory of Open Access Journals (Sweden)

    Shabir A. Parah

    2010-04-01

    Full Text Available A novel technique for the generation of complex and lengthy code sequences using low- length linear feedback shift registers (LFSRs for data scrambling and descrambling is proposed. The scheme has been implemented using VHSIC hardware description language (VHDL approach which allows the reconfigurability of the proposed system such that the length of the generated sequences can be changed as per the security requirements. In the present design consideration the power consumption and chip area requirements are small and the operating speed is high compared to conventional discrete I.C. design, which is a pre-requisite for any system designer. The design has been synthesised on device EP2S15F484C3 of Straitx II FPGA family, using Quarts Altera version 8.1. The simulation results have been found satisfactory and are in conformity with the theoretical observations.

  9. Implementation of an FPGA based system survey and diagnostic reader with the aim to increase system dependability

    CERN Document Server

    Alsdorf, M; Kwiatkowski, M; Vigano, W; Zamantzas, C

    2012-01-01

    The operation and machine protection of accelerators practically rely on their underlying instrumentation systems and a failure of any of those systems could pose a significant impact on the overall reliability and availability. In order to improve the detection and in some cases the prevention of failures, a survey mechanism could be integrated to the system that collects crucial information about the current system status through a number of acquisition modules. The implementation and integration of such a method is presented with the aim to standardize the implementation, where the acquisition modules share a common build and are connected through a standardized interface to a survey reader. The reader collects regularly data and controls the readout intervals. The information collected from these modules is used locally in the FPGA device to identify critical system failures and results in an immediate failsafe reaction with the data also transmitted and stored in external databases for offline analysis.

  10. High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

    Science.gov (United States)

    Ohara, Tetsuo

    2012-01-01

    A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

  11. FPGA Vision Data Architecture

    Science.gov (United States)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  12. Autonomous Lawnmower using FPGA implementation.

    Science.gov (United States)

    Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

    2016-11-01

    Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

  13. From OO to FPGA :

    Energy Technology Data Exchange (ETDEWEB)

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  14. FPGA programming using FX3

    CERN Document Server

    Calleja, Stefano

    2014-01-01

    An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

  15. Different I/O Standard and Technology Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green Wireless Communication on FPGA

    DEFF Research Database (Denmark)

    Goswami, Kavita; Pandey, Bishwajeet; Kumar, Tanesh

    2017-01-01

    and that eventually decrease power dissipation of wireless communications systems. In order to study the effect of different process technology (40, 65, 90 nm) on our design, a novel design is implemented on 40, 65 and 90 nm based FPGA. In this work, we are integrating thermal aware design approach for energy......This paper deals with low power multiplier design that plays a significant role in green wireless communications systems. Over the period of time, researchers have proposed various multiplier designs in order to get high speed. Vedic multiplier is considered as one of the low power multiplier along...... with high speed as compared with traditional array and booth multipliers. Vedic Multiplier contains a total of sixteen algorithms/sutras for predominantly logical operations. This research focuses on thermal aspects and energy efficiency of wireless communications systems with the thermal aware low power...

  16. Fpga As A Part Of Ms Windows Control Environment

    Directory of Open Access Journals (Sweden)

    Krzysztof Kołek

    2007-01-01

    Full Text Available The attention is focused on the Windows operating system (OS used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS.Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

  17. Prototyping Advanced Control Systems on FPGA

    Directory of Open Access Journals (Sweden)

    Simard Stéphane

    2009-01-01

    Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

  18. Artificial Neural Network as the FPGA Trigger in the Cyclone V based Front-End for a Detection of Neutrino-Origin Showers

    Energy Technology Data Exchange (ETDEWEB)

    Szadkowski, Zbigniew; Glas, Dariusz [University of Lodz, Department of Physics and Applied Informatics, Faculty of High-Energy Astrophysics, 90-236 Lodz, Pomorska 149 (Poland); Pytel, Krzysztof [University of Lodz, Department of Physics and Applied Informatics, Faculty of Informatics, 90-236 Lodz (Poland)

    2015-07-01

    Neutrinos play a fundamental role in the understanding of the origin of ultra-high-energy cosmic rays. They interact through charged and neutral currents in the atmosphere generating extensive air showers. However, their a very low rate of events potentially generated by neutrinos is a significant challenge for a detection technique and requires both sophisticated algorithms and high-resolution hardware. A trigger based on a artificial neural network was implemented into the Cyclone{sup R} V E FPGA 5CEFA9F31I7 - the heart of the prototype Front-End boards developed for tests of new algorithms in the Pierre Auger surface detectors. Showers for muon and tau neutrino initiating particles on various altitudes, angles and energies were simulated in CORSICA and Offline platforms giving pattern of ADC traces in Auger water Cherenkov detectors. The 3-layer 12-8-1 neural network was taught in MATLAB by simulated ADC traces according the Levenberg-Marquardt algorithm. Results show that a probability of a ADC traces generation is very low due to a small neutrino cross-section. Nevertheless, ADC traces, if occur, for 1-10 EeV showers are relatively short and can be analyzed by 16-point input algorithm. We optimized the coefficients from MATLAB to get a maximal range of potentially registered events and for fixed-point FPGA processing to minimize calculation errors. New sophisticated triggers implemented in Cyclone{sup R} V E FPGAs with large amount of DSP blocks, embedded memory running with 120 - 160 MHz sampling may support a discovery of neutrino events in the Pierre Auger Observatory. (authors)

  19. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

  20. Real-time FPGA architectures for computer vision

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar

    2000-03-01

    This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

  1. Enhancement of DRPE performance with a novel scheme based on new RAC: Principle, security analysis and FPGA implementation

    Science.gov (United States)

    Neji, N.; Jridi, M.; Alfalou, A.; Masmoudi, N.

    2016-02-01

    The double random phase encryption (DRPE) method is a well-known all-optical architecture which has many advantages especially in terms of encryption efficiency. However, the method presents some vulnerabilities against attacks and requires a large quantity of information to encode the complex output plane. In this paper, we present an innovative hybrid technique to enhance the performance of DRPE method in terms of compression and encryption. An optimized simultaneous compression and encryption method is applied simultaneously on the real and imaginary components of the DRPE output plane. The compression and encryption technique consists in using an innovative randomized arithmetic coder (RAC) that can well compress the DRPE output planes and at the same time enhance the encryption. The RAC is obtained by an appropriate selection of some conditions in the binary arithmetic coding (BAC) process and by using a pseudo-random number to encrypt the corresponding outputs. The proposed technique has the capabilities to process video content and to be standard compliant with modern video coding standards such as H264 and HEVC. Simulations demonstrate that the proposed crypto-compression system has presented the drawbacks of the DRPE method. The cryptographic properties of DRPE have been enhanced while a compression rate of one-sixth can be achieved. FPGA implementation results show the high performance of the proposed method in terms of maximum operating frequency, hardware occupation, and dynamic power consumption.

  2. LHCb: Dynamically Adaptive Header Generator and Front-End Source Emulator for a 100 Gbps FPGA Based DAQ

    CERN Multimedia

    Srikanth, S

    2014-01-01

    The proposed upgrade for the LHCb experiment envisages a system of 500 Data sources each generating data at 100 Gbps, the acquisition and processing of which is a big challenge even for the current state of the art FPGAs. This requires an FPGA DAQ module that not only handles the data generated by the experiment but also is versatile enough to dynamically adapt to potential inadequacies of other components like the network and PCs. Such a module needs to maintain real time operation while at the same time maintaining system stability and overall data integrity. This also creates a need for a Front-end source Emulator capable of generating the various data patterns, that acts as a testbed to validate the functionality and performance of the Header Generator. The rest of the abstract briefly describes these modules and their implementation. The Header Generator is used to packetize the streaming data from the detectors before it is sent to the PCs for further processing. This is achieved by continuously scannin...

  3. Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule Selection

    Directory of Open Access Journals (Sweden)

    BHUVANESWARI, M. C.

    2013-11-01

    Full Text Available FPGAs are increasingly being used to implement data path intensive algorithms for signal processing and image processing applications. In High Level Synthesis of Data Flow Graphs targeted at FPGAs, the effect of interconnect resources such as multiplexers must be considered since they contribute significantly to the area and switching power. We propose a binding framework for behavioral synthesis of Data Flow Graphs (DFGs onto FPGA targets with power reduction as the main criterion. The technique uses a multi-objective GA, NSGA II for design space exploration to identify schedules that have the potential to yield low-power bindings from a population of non-dominated solutions. A greedy constructive binding technique reported in the literature is adapted for interconnect minimization. The binding is further subjected to a perturbation process by altering the register and multiplexer assignments. Results obtained on standard DFG benchmarks indicate that our technique yields better power aware bindings than the constructive binding approach with little or no area overhead.

  4. FPGA-based upgrade of the read-out electronics for the low energy polarimeter at COSY/Juelich

    Energy Technology Data Exchange (ETDEWEB)

    Hempelmann, Nils [Institut fuer Kernphysik, Forschungszentrum Juelich (Germany); Collaboration: JEDI-Collaboration

    2016-07-01

    The Cooler Synchrotron (COSY) is a facility for cooled polarized beams at the Forschungszentrum in Juelich. The Low Energy Polarimeter (LEP) is the polarimeter in the injection beam line of COSY. The beam polarization is measured using scattering off carbon and polyethylene (CH2) targets. The outgoing particles are detected using twelve plastic scintillators installed in groups of three to the left, to the right, above, and below the beam. The LEP is the routine tool for beam set-up, but its performance was limited by the old read-out electronics consisting of analog NIM modules. A new system using analog pulse sampling and an FPGA chip for signal processing was installed and tested. The ejectile particles were identified by relative time of flight measurement using a signal from the RF amplifier of the cyclotron used for acceleration as a reference. The new system is able to measure the time at which a particle arrives to an accuracy in the order of 50 ps. The presentation includes a review of available systems and a report about measurements in May and December 2015.

  5. An FPGA-based trigger system for the search of μ+→e++γ decay in the MEG experiment

    International Nuclear Information System (INIS)

    Galli, L; Cei, F; Galeotti, S; Magazzù, C; Morsani, F; Nicolò, D; Signorelli, G; Grassi, M

    2013-01-01

    The MEG experiment at PSI aims at investigating the μ + → e + + γ decay with improved sensitivity on the branching ratio (BR) by two orders of magnitude with respect to the previous experimental limit (BR(μ + → e + + γ) ≈ 10 −13 ). The use of the most intense continuous muon beam world wide ( ≈ 10 8 μ/s) to search for such a rare event must be accompanied by an efficient trigger system, able to suppress the huge beam-related background to sustainable rates while preserving the efficiency on signal close to unity. In order to accomplish both objectives, a digital approach was exploited by means of Field Programmable Gate Arrays (FPGA), working as a real-time processors of detector signals to perform an accurate event reconstruction within a 450 ns latency. This approach eventually turned out to be flexible enough to allow us to record calibration events in parallel with the main data acquisition and monitor the detector behavior throughout the data taking. We describe here the hardware implementation of the trigger and its main features as well: signal digitization, online waveform processing, reconstruction algorithms. A detailed description is given of the system architecture, the feature of the boards and their use. The trigger algorithms will be described in details in a dedicated article to be published afterwards.

  6. FPGA-based design and implementation of arterial pulse wave generator using piecewise Gaussian-cosine fitting.

    Science.gov (United States)

    Wang, Lu; Xu, Lisheng; Zhao, Dazhe; Yao, Yang; Song, Dan

    2015-04-01

    Because arterial pulse waves contain vital information related to the condition of the cardiovascular system, considerable attention has been devoted to the study of pulse waves in recent years. Accurate acquisition is essential to investigate arterial pulse waves. However, at the stage of developing equipment for acquiring and analyzing arterial pulse waves, specific pulse signals may be unavailable for debugging and evaluating the system under development. To produce test signals that reflect specific physiological conditions, in this paper, an arterial pulse wave generator has been designed and implemented using a field programmable gate array (FPGA), which can produce the desired pulse waves according to the feature points set by users. To reconstruct a periodic pulse wave from the given feature points, a method known as piecewise Gaussian-cosine fitting is also proposed in this paper. Using a test database that contains four types of typical pulse waves with each type containing 25 pulse wave signals, the maximum residual error of each sampling point of the fitted pulse wave in comparison with the real pulse wave is within 8%. In addition, the function for adding baseline drift and three types of noises is integrated into the developed system because the baseline occasionally wanders, and noise needs to be added for testing the performance of the designed circuits and the analysis algorithms. The proposed arterial pulse wave generator can be considered as a special signal generator with a simple structure, low cost and compact size, which can also provide flexible solutions for many other related research purposes. Copyright © 2015 Elsevier Ltd. All rights reserved.

  7. Adaptive linear predictor FIR filter based on the Cyclone V FPGA with HPS to reduce narrow band RFI in AERA radio detection of cosmic rays

    Energy Technology Data Exchange (ETDEWEB)

    Szadkowski, Zbigniew [University of Lodz, Department of Physics and Applied Informatics, 90-236 Lodz, (Poland)

    2015-07-01

    We present the new approach to a filtering of radio frequency interferences (RFI) in the Auger Engineering Radio Array (AERA) which study the electromagnetic part of the Extensive Air Showers. The radio stations can observe radio signals caused by coherent emissions due to geomagnetic radiation and charge excess processes. AERA observes frequency band from 30 to 80 MHz. This range is highly contaminated by human-made RFI. In order to improve the signal to noise ratio RFI filters are used in AERA to suppress this contamination. The first kind of filter used by AERA was the Median one, based on the Fast Fourier Transform (FFT) technique. The second one, which is currently in use, is the infinite impulse response (IIR) notch filter. The proposed new filter is a finite impulse response (FIR) filter based on a linear prediction (LP). A periodic contamination hidden in a registered signal (digitized in the ADC) can be extracted and next subtracted to make signal cleaner. The FIR filter requires a calculation of n=32, 64 or even 128 coefficients (dependent on a required speed or accuracy) by solving of n linear equations with coefficients built from the covariance Toeplitz matrix. This matrix can be solved by the Levinson recursion, which is much faster than the Gauss procedure. The filter has been already tested in the real AERA radio stations on Argentinean pampas with a very successful results. The linear equations were solved either in the virtual soft-core NIOSR processor (implemented in the FPGA chip as a net of logic elements) or in the external Voipac PXA270M ARM processor. The NIOS processor is relatively slow (50 MHz internal clock), calculations performed in an external processor consume a significant amount of time for data exchange between the FPGA and the processor. Test showed a very good efficiency of the RFI suppression for stationary (long-term) contaminations. However, we observed a short-time contaminations, which could not be suppressed either by the

  8. FPGA remote update for nuclear environments

    Energy Technology Data Exchange (ETDEWEB)

    Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

    2015-07-01

    The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

  9. The FPGA Pixel Array Detector

    International Nuclear Information System (INIS)

    Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

    2013-01-01

    A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

  10. A High-Performance FPGA-Based Image Feature Detector and Matcher Based on the FAST and BRIEF Algorithms

    Directory of Open Access Journals (Sweden)

    Michał Fularz

    2015-10-01

    Full Text Available Image feature detection and matching is a fundamental operation in image processing. As the detected and matched features are used as input data for high-level computer vision algorithms, the matching accuracy directly influences the quality of the results of the whole computer vision system. Moreover, as the algorithms are frequently used as a part of a real-time processing pipeline, the speed at which the input image data are handled is also a concern. The paper proposes an embedded system architecture for feature detection and matching. The architecture implements the FAST feature detector and the BRIEF feature descriptor and is capable of establishing key point correspondences in the input image data stream coming from either an external sensor or memory at a speed of hundreds of frames per second, so that it can cope with most demanding applications. Moreover, the proposed design is highly flexible and configurable, and facilitates the trade-off between the processing speed and programmable logic resource utilization. All the designed hardware blocks are designed to use standard, widely adopted hardware interfaces based on the AMBA AXI4 interface protocol and are connected using an underlying direct memory access (DMA architecture, enabling bottleneck-free inter-component data transfers.

  11. Signal compression in radar using FPGA

    OpenAIRE

    Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

    2010-01-01

    We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

  12. A new FPGA-based time-over-threshold system for the time of flight detectors at the BGO-OD experiment

    Energy Technology Data Exchange (ETDEWEB)

    Freyermuth, Oliver [Physikalisches Institut, Nussallee 12, D-53115 Bonn (Germany); Collaboration: BGO-OD-Collaboration

    2015-07-01

    The BGO-OD experiment at the ELSA accelerator facility at Bonn is built for the systematic investigation of meson photoproduction in the GeV region. It features the unique combination of a central, highly segmented BGO crystal calorimeter covering almost 4π in acceptance and a forward magnetic spectrometer complemented by time of flight walls. The readout of the ToF scintillator bars was upgraded to an FPGA-based VME-board equipped with discriminator mezzanines including per-channel remotely adjustable thresholds. A firmware was developed combining a time-over-threshold (ToT) measurement by implementing a dual-edge TDC, a configurable meantimer trigger logic including a special cosmics trigger, adjustable input delays and gateable scalers, all inside a single electronics module. An experimentally obtained relation between ToT and slope of a PMT signal can be used for a time walk correction to achieve time resolutions comparable to a classical chain of CFD and standard TDC. Additionally, the time-over-threshold information can be exploited for gain matching and allows to monitor online the gain-stability and check for electronics problems such as pulse reflections or baseline jitter. The system is well-suited for a wide range of PMT-based fast detectors with many channels and further applications foreseen.

  13. A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

    Directory of Open Access Journals (Sweden)

    Gabriel J. García

    2014-03-01

    Full Text Available The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc., reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

  14. Characterization of a detector chain using a FPGA-based time-to-digital converter to reconstruct the three-dimensional coordinates of single particles at high flux

    Science.gov (United States)

    Nogrette, F.; Heurteau, D.; Chang, R.; Bouton, Q.; Westbrook, C. I.; Sellem, R.; Clément, D.

    2015-11-01

    We report on the development of a novel FPGA-based time-to-digital converter and its implementation in a detection chain that records the coordinates of single particles along three dimensions. The detector is composed of micro-channel plates mounted on top of a cross delay line and connected to fast electronics. We demonstrate continuous recording of the timing signals from the cross delay line at rates up to 4.1 × 106 s-1 and three-dimensional reconstruction of the coordinates up to 3.2 × 106 particles per second. From the imaging of a calibrated structure we measure the in-plane resolution of the detector to be 140(20) μm at a flux of 3 × 105 particles per second. In addition, we analyze a method to estimate the resolution without placing any structure under vacuum, a significant practical improvement. While we use UV photons here, the results of this work apply to the detection of other kinds of particles.

  15. A survey on FPGA-based sensor systems: towards intelligent and reconfigurable low-power sensors for computer vision, control and signal processing.

    Science.gov (United States)

    García, Gabriel J; Jara, Carlos A; Pomares, Jorge; Alabdo, Aiman; Poggi, Lucas M; Torres, Fernando

    2014-03-31

    The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

  16. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-05-23

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

  17. Energy efficiency analysis and implementation of AES on an FPGA

    Science.gov (United States)

    Kenney, David

    The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

  18. FPGA Implementation of Heart Rate Monitoring System.

    Science.gov (United States)

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  19. Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA; Desenvolvimento de sistema de protecao para reator nuclear de pesquisa baseado em Field Programmable Gate Array - FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Martins, Roque Hudson da Silva

    2016-07-01

    This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

  20. Porting VIRTEX4 data acquisition design to SPARTAN6 FPGA

    International Nuclear Information System (INIS)

    Suetoe, J.; Hegyesi, G.

    2012-01-01

    Complete text of publication follows. The Atomki's Virtex 4 based 4 channel data acquisition card (LIR) card was used in many applications (miniPET-II, miniPET-III, data acquisition system for the multichannel plate installed at the ECR lab). The goal of the work was to improve the LIR using a higher performance FPGA (Spartan6 Trenz module). The Trenz module based system also supports ADC channels up to 16 channels. This work also implied the porting of the Virtex4 based VHDL code to Spartan 6. Further advantage of the proposed system, besides the improvement in the number of ADC channels, that the Spartan6 FPGA is able to run more complex digital signal processing algorithms than the Virtex 4 FPGA. Easy access to the control parameters (via serial interface or Ethernet), flexibility and high performance were considered during the development. SPARTAN6 FPGA based data acquisition provides more facilities than the VIRTEX4 based. SPARTAN6 is a newer generation of XILINX’s FPGAs, which excellent into the high-speed data acquisition. We ported the HDL code, which runs on LIR module (VIRTEX4 based), to the Trenz module (SPARTAN6 based). The main parts of the whole program code are the command line interpreter, GMII interface, DHCP process, ARP process and the data read out. Those parts were implemented by picoblaze embedded system. Figure 1 shows the command line interpreter process in the Hyper Terminal. The command line interpreter communicates with the PC via serial port. In addition, the AdamIOSetting software also use the serial communication, which was created to the VIRTEX FPGA based data collector. In the Wireshark network analyzer software we examined the DHCP and ARP process and using the AdamIOSettings software we tested the data read out from the flash memory of FPGA board. Figure 2 shows the AdamIOSettings program. Acknowledgements. This work was supported by the ENIAC CSI Project (No.120209).

  1. FAS: Using FPGA to Accelerate and Secure SDN Software Switches

    Directory of Open Access Journals (Sweden)

    Wenwen Fu

    2018-01-01

    Full Text Available Software-Defined Networking (SDN promises the vision of more flexible and manageable networks but requires certain level of programmability in the data plane to accommodate different forwarding abstractions. SDN software switches running on commodity multicore platforms are programmable and are with low deployment cost. However, the performance of SDN software switches is not satisfactory due to the complex forwarding operations on packets. Moreover, this may hinder the performance of real-time security on software switch. In this paper, we analyze the forwarding procedure and identify the performance bottleneck of SDN software switches. An FPGA-based mechanism for accelerating and securing SDN switches, named FAS (FPGA-Accelerated SDN software switch, is proposed to take advantage of the reconfigurability and high-performance advantages of FPGA. FAS improves the performance as well as the capacity against malicious traffic attacks of SDN software switches by offloading some functional modules. We validate FAS on an FPGA-based network processing platform. Experiment results demonstrate that the forwarding rate of FAS can be 44% higher than the original SDN software switch. In addition, FAS provides new opportunity to enhance the security of SDN software switches by allowing the deployment of bump-in-the-wire security modules (such as packet detectors and filters in FPGA.

  2. Effective and efficient FPGA synthesis through general functional decomposition

    NARCIS (Netherlands)

    Jozwiak, L.; Slusarczyk, A.S.; Chojnacki, A.

    2003-01-01

    In this paper, a new information-driven circuit synthesis method is discussed that targets LUT-based FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The method is based on the bottom–up general functional decomposition and theory of information relationship measures that we

  3. Implementation of a FPGA-Based Feature Detection and Networking System for Real-time Traffic Monitoring

    OpenAIRE

    Chen, Jieshi; Schafer, Benjamin Carrion; Ho, Ivan Wang-Hei

    2016-01-01

    With the growing demand of real-time traffic monitoring nowadays, software-based image processing can hardly meet the real-time data processing requirement due to the serial data processing nature. In this paper, the implementation of a hardware-based feature detection and networking system prototype for real-time traffic monitoring as well as data transmission is presented. The hardware architecture of the proposed system is mainly composed of three parts: data collection, feature detection,...

  4. A low-power wave union TDC implemented in FPGA

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

    2011-01-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  5. FPGA development board for applications in cosmic rays physics

    International Nuclear Information System (INIS)

    Angelov, Ivo; Damov, Krasimir; Dimitrova, Svetla

    2013-01-01

    The modern experiments in cosmic rays and particle physics are usually performed with large number of detectors and signal processing have to be done by complex electronics. The analog signals from the detectors are converted to digital (by discriminators or fast ADC) and connected to different type of logic implemented in FPGA (Field Programmable Gate Arrays). A FPGA development board based on Xilinx XC3S50AN was designed, assembled and tested. The board will be used for developing a modern registering controller (to replace the existing now) for the muon telescope in the University and can be used for other experiments in cosmic rays physics when fast digital pulses have to be processed. Keywords: FPGA, Spartan3A, muon telescope, cosmic rays variations

  6. Superconducting cavity driving with FPGA controller

    International Nuclear Information System (INIS)

    Czarski, Tomasz; Koprek, Waldemar; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Simrock, Stefan; Brandt, Alexander; Chase, Brian; Carcagno, Ruben; Cancelo, Gustavo; Koeth, Timothy W.

    2006-01-01

    A digital control of superconducting cavities for a linear accelerator is presented. FPGA-based controller, supported by Matlab system, was applied. Electrical model of a resonator was used for design of a control system. Calibration of the signal path is considered. Identification of cavity parameters has been carried out for adaptive control algorithm. Feed-forward and feedback modes were applied in operating the cavities. Required performance has been achieved; i.e. driving on resonance during filling and field stabilization during flattop time, while keeping reasonable level of the power consumption. Representative results of the experiments are presented for different levels of the cavity field gradient

  7. Spacewire Routers Implemented with FPGA Technology

    Science.gov (United States)

    Habinc, Sandi; Isomaki, Marko

    2011-08-01

    Routers are an integral part of SpaceWire networks. Aeroflex Gaisler has developed a highly configurable SpaceWire router VHDL IP core to meet the needs for technology independent router designs. The main design goals have been configurability, technology independence, support of the standard and expandability. The IP core being technologically independent allows it to be used in both ASIC and FPGA technology. The latter is now being used to produce versatile standard products that can reach the market faster than for example an ASIC based product.

  8. Development of A Low-Cost FPGA-Based Measurement System for Real-Time Processing of Acoustic Emission Data: Proof of Concept Using Control of Pulsed Laser Ablation in Liquids.

    Science.gov (United States)

    Wirtz, Sebastian F; Cunha, Adauto P A; Labusch, Marc; Marzun, Galina; Barcikowski, Stephan; Söffker, Dirk

    2018-06-01

    Today, the demand for continuous monitoring of valuable or safety critical equipment is increasing in many industrial applications due to safety and economical requirements. Therefore, reliable in-situ measurement techniques are required for instance in Structural Health Monitoring (SHM) as well as process monitoring and control. Here, current challenges are related to the processing of sensor data with a high data rate and low latency. In particular, measurement and analyses of Acoustic Emission (AE) are widely used for passive, in-situ inspection. Advantages of AE are related to its sensitivity to different micro-mechanical mechanisms on the material level. However, online processing of AE waveforms is computationally demanding. The related equipment is typically bulky, expensive, and not well suited for permanent installation. The contribution of this paper is the development of a Field Programmable Gate Array (FPGA)-based measurement system using ZedBoard devlopment kit with Zynq-7000 system on chip for embedded implementation of suitable online processing algorithms. This platform comprises a dual-core Advanced Reduced Instruction Set Computer Machine (ARM) architecture running a Linux operating system and FPGA fabric. A FPGA-based hardware implementation of the discrete wavelet transform is realized to accelerate processing the AE measurements. Key features of the system are low cost, small form factor, and low energy consumption, which makes it suitable to serve as field-deployed measurement and control device. For verification of the functionality, a novel automatically realized adjustment of the working distance during pulsed laser ablation in liquids is established as an example. A sample rate of 5 MHz is achieved at 16 bit resolution.

  9. FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications

    Directory of Open Access Journals (Sweden)

    S. Tsakiris

    2009-09-01

    Full Text Available This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.

  10. Development of 8K-MCA Add-on based on FPGA technique with a control of VB6 software application under windows environment

    International Nuclear Information System (INIS)

    Dang Lanh; Nguyen Nhi Dien; Nguyen Xuan Hai; Nguyen Bach Viet; Pham Ngoc Son; Huynh Minh; Vuong Huu Tan; Pham Dinh Khang; Phan Nam Anh

    2003-01-01

    The multichannel analyzer is the heart of most experimental measurements. Today, it becomes popular and convenient. It can play a role of getting, processing data and easily interfacing to PC. Some standard-alone multichannel analysis systems can be replaced by Add-on MCA card. Especially, MCA card is necessary for application in nuclear physics research. The main aim of this sub-project is to focus on a design and construction of an 8K-MCA Add-on served for studying nuclear structure, for development of Gamma spectroscopy system, and for a production of low-cost electronics instruments as well. Some experimental results were obtained through the aforementioned card combining with other needed functional analog units. A multichannel data processing (MCD) circuit for nuclear spectroscopy application was developed using a field programmable gate arrays (FPGA) as the central processing element. In addition to the first role, A 13-bit analog-to-digital converter (8k ADC) circuit for nuclear spectroscopy application was also developed using a successive approximation ADC with a control of FPGA technology. The FPGA operates a program that builds the distributed functions of data collected by the ADC and then corrects the ADC differential non-linearity (DNL) via the sliding scale method. The acquisition routine runs in 3.7μ s. the conversion time is approximated 2.2μ s, and the integral non-linearity ≤ 0.14%. (author)

  11. 8-channel, FPGA based, DSP integrated cavity simulator and controller for VUV-FEL. SIMCON 3.0 Ver. 3.0. rev. 1, 06.2005 - Hardware manual

    International Nuclear Information System (INIS)

    Pozniak, K.T.; Czarski, T.; Koprek, W.; Giergusiewicz, W.; Romaniuk, R.S.

    2005-01-01

    The note describes integrated, eight channel system of hardware controller and simulator of the resonant superconducting, narrowband niobium cavity, originally considered for the TTF and TESLA in DESY, Hamburg (now tested for the VUV FEL and developed for X-Ray FEL). The controller bases on a programmable circuit Xilinx VirtexII V4000. The solution uses DSP EMBEDDED BOARD module positioned on a Modular LLRF Control Platform. The algorithm and FPGA circuit configuration was done in the VHDL language. The internal hardware multiplication components, present in Virtex II chips, were used, to improve the floating point calculation efficiency. The implementation was achieved of a device working in the real time, according to the demands of the LLRF control system for the TESLA Test Facility (now associated with the VUV FEL machine). The device under consideration will be referred to as superconducting cavity (SCCav) SIMCON throughout this work. The manual describes hardware features of SIMCON, ver. 3.0 in modular solution. The following components are described here in detail: functional layer, parameter programming, foundations of control of particular blocks and monitoring of the real time processes. This note is accompanied by the one describing the multichannel DOOCS interface for the described hardware system. The interface was prepared in DOOCS for Solaris and in Windows. The hardware and software of 8-channel SIMCON was tested in CHECIA and ACC1 module of VUV FEL linac. The measurements results are presented. While giving all necessary technical details required to understand the work of the integrated hardware controller and simulator and to enable its practical copying, this document is a unity with other TESLA technical notes published by the same team on the subject. Thus, some modeling and other subjects were omitted, as they were addressed in detail in the quoted references. Keywords: Super conducting cavity, cavity simulator, CAVITIES CONTROLLER, SIMCON

  12. FPGA controlled artificial vascular system

    Directory of Open Access Journals (Sweden)

    Laqua D.

    2015-09-01

    Full Text Available Monitoring the oxygen saturation of an unborn child is an invasive procedure, so far. Transabdominal fetal pulse oximetry is a promising method under research, used to estimate the oxygen saturation of a fetus noninvasively. Due to the nature of the method, the fetal information needs to be extracted from a mixed signal. To properly evaluate signal processing algorithms, a phantom modeling fetal and maternal blood circuits and tissue layers is necessary. This paper presents an improved hardware concept for an artificial vascular system, utilizing an FPGA based CompactRIO System from National Instruments. The experimental model to simulate the maternal and fetal blood pressure curve consists of two identical hydraulic circuits. Each of these circuits consists of a pre-pressure system and an artificial vascular system. Pulse curves are generated by proportional valves, separating these two systems. The dilation of the fetal and maternal artificial vessels in tissue substitutes is measured by transmissive and reflective photoplethysmography. The measurement results from the pressure sensors and the transmissive optical sensors are visualized to show the functionality of the pulse generating systems. The trigger frequency for the maternal valve was set to 1 per second, the fetal valve was actuated at 0.7 per second for validation. The reflective curve, capturing pulsations of the fetal and maternal circuit, was obtained with a high power LED (905 nm as light source. The results show that the system generates pulse curves, similar to its physiological equivalent. Further, the acquired reflective optical signal is modulated by the alternating diameter of the tubes of both circuits, allowing for tests of signal processing algorithms.

  13. An FPGA based demonstrator for a topological processor in the future ATLAS L1-Calo trigger “GOLD”

    CERN Document Server

    Ebling, A; Büscher, V; Degele, R; Ji, W; Meyer, C; Moritz, S; Schäfer, U; Simioni, E; Tapprogge, S; Wenzel, V

    2012-01-01

    Abstract: The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based. The LHC machine plans to bring the beam energy to the maximum value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged. To cope with the resulting higher event rate, as part of the ATLAS trigger upgrade, a new electronics module is foreseen to be added in the ATLAS Level-1 Calorimeter Trigger electronics chain: the Topological Processor (TP). Such a processor needs fast optical I/O and large aggregate bandwidth to use the information on trigger object position in space (e.g. jets in the calorimeters or muons measured in the muon detectors) to improve the purity of the L1 triggers streams by applying topological cuts within the L1 latency budget. In this paper, an overview of the adopted technological solutions and the R&D activities on the demonstrator for th...

  14. FPGA-Based Smart Sensor for Drought Stress Detection in Tomato Plants Using Novel Physiological Variables and Discrete Wavelet Transform

    Directory of Open Access Journals (Sweden)

    Carlos Duarte-Galvan

    2014-10-01

    Full Text Available Soil drought represents one of the most dangerous stresses for plants. It impacts the yield and quality of crops, and if it remains undetected for a long time, the entire crop could be lost. However, for some plants a certain amount of drought stress improves specific characteristics. In such cases, a device capable of detecting and quantifying the impact of drought stress in plants is desirable. This article focuses on testing if the monitoring of physiological process through a gas exchange methodology provides enough information to detect drought stress conditions in plants. The experiment consists of using a set of smart sensors based on Field Programmable Gate Arrays (FPGAs to monitor a group of plants under controlled drought conditions. The main objective was to use different digital signal processing techniques such as the Discrete Wavelet Transform (DWT to explore the response of plant physiological processes to drought. Also, an index-based methodology was utilized to compensate the spatial variation inside the greenhouse. As a result, differences between treatments were determined to be independent of climate variations inside the greenhouse. Finally, after using the DWT as digital filter, results demonstrated that the proposed system is capable to reject high frequency noise and to detect drought conditions.

  15. Development of Methods and Means of Configuration Data Transfer For Use in an FPGA Based Trigger Controller Device

    International Nuclear Information System (INIS)

    2010-01-01

    To determine if klystrons will perform to the specifications of the LCLS (Linac Coherent Light Source) project, a new digital trigger controller is needed for the Klystron/Microwave Department Test Laboratory. The controller needed to be programmed and Windows based user interface software needed to be written to interface with the device over a USB (Universal Serial Bus). Programming the device consisted of writing logic in VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language), and the Windows interface software was written in C++. Xilinx ISE (Integrated Software Environment) was used to compile the VHDL code and program the device, and Microsoft Visual Studio 2005 was used to compile the C++ based Windows software. The device was programmed in such a way as to easily allow read/write operations to it using a simple addressing model, and Windows software was developed to interface with the device over a USB connection. A method of setting configuration registers in the trigger device is absolutely necessary to the development of a new triggering system, and the method developed will fulfill this need adequately. More work is needed before the new trigger system is ready for use. The configuration registers in the device need to be fully integrated with the logic that will generate the RF signals, and this system will need to be tested extensively to determine if it meets the requirements for low noise trigger outputs.

  16. Proposed FPGA based tracking for a Level-1 track trigger at CMS for the HL-LHC

    CERN Document Server

    Pozzobon, Nicola

    2014-01-01

    The High Luminosity LHC (HL-LHC) is expected to deliver a luminosity in excess of $5\\times10^{34}$ cm$^{-2}$/s. The high event rate places stringent requirements on the trigger system. A key component of the CMS upgrade for the HL-LHC is a track trigger system which will identify tracks with transverse momenta above 2 GeV already at the first-level trigger within 5 $\\mu$s. This presentation will discuss a proposed track finding and fitting based on the tracklet based approach implemented on FPGAs. Tracklets are formed from pairs of hits in nearby layers in the detector and used in a road search. Summary Fast pattern recognition in Silicon trackers for triggering has often made use of Associative Memories for the pattern recognition step. We propose an alternative approach to solving the pattern recognition and track fitting problem for the upgraded CMS tracker for the HL-LHC operation. We make use of the trigger primitives,stubs, from the tracker. The stubs are formed from pairs of hits in sensors separated r...

  17. A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline

    International Nuclear Information System (INIS)

    Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Wilson, Peter; Phillips, Thomas J.

    2005-01-01

    We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR), FERMILAB-Pub-96/390-E. The TDC described here is intended as a further upgrade beyond that described in the TDR] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2ns, a minimum input pulse width of 4.8ns and a minimum separation of 4.8ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47Mbytes/s. The TDC module also produces prompt trigger data every Tevatron crossing via a deadtimeless fast logic path that can be easily reprogrammed. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and

  18. Single Event Effects in FPGA Devices 2015-2016

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  19. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  20. Superconducting cavity driving with FPGA controller

    Energy Technology Data Exchange (ETDEWEB)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland); Simrock, S.; Brand, A. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Chase, B.; Carcagno, R.; Cancelo, G. [Fermi National Accelerator Lab., Batavia, IL (United States); Koeth, T.W. [Rutgers - the State Univ. of New Jersey, NJ (United States)

    2006-07-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)