CMOS Active-Pixel Image Sensor With Simple Floating Gates

Science.gov (United States)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Soochow University, Suzhou, Jiangsu 215123 (China)

2016-07-11

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

Photon-gated spin transistor

OpenAIRE

Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

2017-01-01

Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

Study of the enhancement-mode AlGaN/GaN high electron mobility transistor with split floating gates

Science.gov (United States)

Wang, Hui; Wang, Ning; Jiang, Ling-Li; Zhao, Hai-Yue; Lin, Xin-Peng; Yu, Hong-Yu

2017-11-01

In this work, the charge storage based split floating gates (FGs) enhancement mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs) are studied. The simulation results reveal that under certain density of two dimensional electron gas, the variation tendency of the threshold voltage (Vth) with the variation of the blocking dielectric thickness depends on the FG charge density. It is found that when the length sum and isolating spacing sum of the FGs both remain unchanged, the Vth shall decrease with the increasing FGs number but maintaining the device as E-mode. It is also reported that for the FGs HEMT, the failure of a FG will lead to the decrease of Vth as well as the increase of drain current, and the failure probability can be improved significantly with the increase of FGs number.

Direct label-free electrical immunodetection of transplant rejection protein biomarker in physiological buffer using floating gate AlGaN/GaN high electron mobility transistors.

Science.gov (United States)

Tulip, Fahmida S; Eteshola, Edward; Desai, Suchita; Mostafa, Salwa; Roopa, Subramanian; Evans, Boyd; Islam, Syed Kamrul

2014-06-01

Monokine induced by interferon gamma (MIG/CXCL9) is used as an immune biomarker for early monitoring of transplant or allograft rejection. This paper demonstrates a direct electrical, label-free detection method of recombinant human MIG with anti-MIG IgG molecules in physiologically relevant buffer environment. The sensor platform used is a biologically modified GaN-based high electron mobility transistor (HEMT) device. Biomolecular recognition capability was provided by using high affinity anti-MIG monoclonal antibody to form molecular affinity interface receptors on short N-hydroxysuccinimide-ester functionalized disulphide (DSP) self-assembled monolayers (SAMs) on the gold sensing gate of the HEMT device. A floating gate configuration has been adopted to eliminate the influences of external gate voltage. Preliminary test results with the proposed chemically treated GaN HEMT biosensor show that MIG can be detected for a wide range of concentration varying from 5 ng/mL to 500 ng/mL.

Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

Energy Technology Data Exchange (ETDEWEB)

Aunet, Snorre

2002-06-01

This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

Enhanced transconductance in a double-gate graphene field-effect transistor

Science.gov (United States)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

Science.gov (United States)

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

Science.gov (United States)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

Science.gov (United States)

Hasaneen, El-Sayed A. M.

nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

Science.gov (United States)

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Water-gel for gating graphene transistors.

Science.gov (United States)

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

Structured-gate organic field-effect transistors

International Nuclear Information System (INIS)

Aljada, Muhsen; Pandey, Ajay K; Velusamy, Marappan; Burn, Paul L; Meredith, Paul; Namdas, Ebinazar B

2012-01-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO 2 ) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends. (paper)

Structured-gate organic field-effect transistors

Science.gov (United States)

Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

2012-06-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

Oscillation of Critical Current by Gate Voltage in Cooper Pair Transistor

International Nuclear Information System (INIS)

Kim, N.; Cheong, Y.; Song, W.

2010-01-01

We measured the critical current of a Cooper pair transistor consisting of two Josephson junctions and a gate electrode. The Cooper pair transistors were fabricated by using electron-beam lithography and double-angle evaporation technique. The Gate voltage dependence of critical current was measured by observing voltage jumps at various gate voltages while sweeping bias current. The observed oscillation was 2e-periodic, which shows the Cooper pair transistor had low level of quasiparticle poisoning.

Floating Gate CMOS Dosimeter With Frequency Output

Science.gov (United States)

Garcia-Moreno, E.; Isern, E.; Roca, M.; Picos, R.; Font, J.; Cesari, J.; Pineda, A.

2012-04-01

This paper presents a gamma radiation dosimeter based on a floating gate sensor. The sensor is coupled with a signal processing circuitry, which furnishes a square wave output signal, the frequency of which depends on the total dose. Like any other floating gate dosimeter, it exhibits zero bias operation and reprogramming capabilities. The dosimeter has been designed in a standard 0.6 m CMOS technology. The whole dosimeter occupies a silicon area of 450 m250 m. The initial sensitivity to a radiation dose is Hz/rad, and to temperature and supply voltage is kHz/°C and 0.067 kHz/mV, respectively. The lowest detectable dose is less than 1 rad.

Non-volatile flash memory with discrete bionanodot floating gate assembled by protein template

International Nuclear Information System (INIS)

Miura, Atsushi; Yamashita, Ichiro; Uraoka, Yukiharu; Fuyuki, Takashi; Tsukamoto, Rikako; Yoshii, Shigeo

2008-01-01

We demonstrated non-volatile flash memory fabrication by utilizing uniformly sized cobalt oxide (Co 3 O 4 ) bionanodot (Co-BND) architecture assembled by a cage-shaped supramolecular protein template. A fabricated high-density Co-BND array was buried in a metal-oxide-semiconductor field-effect-transistor (MOSFET) structure to use as the charge storage node of a floating nanodot gate memory. We observed a clockwise hysteresis in the drain current-gate voltage characteristics of fabricated BND-embedded MOSFETs. Observed hysteresis obviously indicates a memory operation of Co-BND-embedded MOSFETs due to the charge confinement in the embedded BND and successful functioning of embedded BNDs as the charge storage nodes of the non-volatile flash memory. Fabricated Co-BND-embedded MOSFETs showed good memory properties such as wide memory windows, long charge retention and high tolerance to repeated write/erase operations. A new pathway for device fabrication by utilizing the versatile functionality of biomolecules is presented

Investigation of Impact of the Gate Circuitry on IGBT Transistor Dynamic Parameters

Directory of Open Access Journals (Sweden)

Vytautas Bleizgys

2011-03-01

Full Text Available The impact of Insulated Gate Bipolar Transistor driver circuit parameters on the rise and fall time of the collector current and voltage collector-emitter was investigated. The influence of transistor driver circuit parameters on heating of Insulated Gate Bipolar Transistors was investigated as well.Article in Lithuanian

100-nm gate lithography for double-gate transistors

Science.gov (United States)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

Liquid–Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing

KAUST Repository

Zhang, Yu

2017-10-17

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid–liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the “sensing channel” can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

Science.gov (United States)

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Ambipolar organic tri-gate transistor for low-power complementary electronics

NARCIS (Netherlands)

Torricelli, F.; Ghittorelli, M.; Smits, E.C.P.; Roelofs, C.; Janssen, R.A.J.; Gelinck, G.H.; Kovács-Vajna, Z.M.; Cantatore, E.

2016-01-01

Ambipolar transistors typically suffer from large off-current inherently due to ambipolar conduction. Using a tri-gate transistor it is shown that it is possible to electrostatically switch ambipolar polymer transistors from ambipolar to unipolar mode. In unipolar mode, symmetric characteristics

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

Science.gov (United States)

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

Science.gov (United States)

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

High-frequency self-aligned graphene transistors with transferred gate stacks

Science.gov (United States)

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Development and characterization of vertical double-gate MOS field-effect transistors

International Nuclear Information System (INIS)

Trellenkamp, S.

2004-07-01

Planar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 μA/μm and transconductances up to 480 μS/μm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated. (orig.)

Coherent molecular transistor: control through variation of the gate wave function.

Science.gov (United States)

Ernzerhof, Matthias

2014-03-21

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

Coherent molecular transistor: Control through variation of the gate wave function

International Nuclear Information System (INIS)

Ernzerhof, Matthias

2014-01-01

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor

Simulation of 50-nm Gate Graphene Nanoribbon Transistors

Directory of Open Access Journals (Sweden)

Cedric Nanmeni Bondja

2016-01-01

Full Text Available An approach to simulate the steady-state and small-signal behavior of GNR MOSFETs (graphene nanoribbon metal-semiconductor-oxide field-effect transistor is presented. GNR material parameters and a method to account for the density of states of one-dimensional systems like GNRs are implemented in a commercial device simulator. This modified tool is used to calculate the current-voltage characteristics as well the cutoff frequency fT and the maximum frequency of oscillation fmax of GNR MOSFETs. Exemplarily, we consider 50-nm gate GNR MOSFETs with N = 7 armchair GNR channels and examine two transistor configurations. The first configuration is a simplified MOSFET structure with a single GNR channel as usually studied by other groups. Furthermore, and for the first time in the literature, we study in detail a transistor structure with multiple parallel GNR channels and interribbon gates. It is shown that the calculated fT of GNR MOSFETs is significantly lower than that of GFETs (FET with gapless large-area graphene channel with comparable gate length due to the mobility degradation in GNRs. On the other hand, GNR MOSFETs show much higher fmax compared to experimental GFETs due the semiconducting nature of the GNR channels and the resulting better saturation of the drain current. Finally, it is shown that the gate control in FETs with multiple parallel GNR channels is improved while the cutoff frequency is degraded compared to single-channel GNR MOSFETs due to parasitic capacitances of the interribbon gates.

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

Science.gov (United States)

Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

2015-01-14

Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

Science.gov (United States)

Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

2015-12-01

In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

Science.gov (United States)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

International Nuclear Information System (INIS)

Sah, C.-T.; Jie Binbin

2009-01-01

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

Science.gov (United States)

Hunt, Mitchell; Sayyah, Rana; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

Science.gov (United States)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Transport and performance of a gate all around InAs nanowire transistor

International Nuclear Information System (INIS)

Alam, Khairul

2009-01-01

The transport physics and performance metrics of a gate all around an InAs nanowire transistor are studied using a three-dimensional quantum simulation. The transistor action of an InAs nanowire transistor occurs by modulating the transmission coefficient of the device. This action is different from a conventional metal-oxide-semiconductor field effect transistor, where the transistor action occurs by modulating the charge in the channel. The device has 82% tunneling current in the off-state and 81% thermal current in the on-state. The two current components become equal at a gate bias at which an approximate source-channel flat-band condition is achieved. Prior to this gate bias, the tunneling current dominates and the thermal current dominates beyond it. The device has an on/off current ratio of 7.84 × 10 5 and an inverse subthreshold slope of 63 mV dec −1 . The transistor operates in the quantum capacitance limit with a normalized transconductance value of 14.43 mS µm −1 , an intrinsic switching delay of 90.1675 fs, and an intrinsic unity current gain frequency of 6.8697 THz

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

Science.gov (United States)

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

Science.gov (United States)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

Science.gov (United States)

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al2O3 gate oxides

International Nuclear Information System (INIS)

Yeom, Donghyuk; Kang, Jeongmin; Lee, Myoungwon; Jang, Jaewon; Yun, Junggwon; Jeong, Dong-Young; Yoon, Changjoon; Koo, Jamin; Kim, Sangsig

2008-01-01

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al 2 O 3 tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8 V was observed in its drain current versus gate voltage (I DS -V GS ) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper

Light-effect transistor (LET with multiple independent gating controls for optical logic gates and optical amplification

Directory of Open Access Journals (Sweden)

Jason eMarmon

2016-03-01

Full Text Available Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs, remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses. Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors

Directory of Open Access Journals (Sweden)

Guo-Neng Lu

2009-01-01

Full Text Available We present a single-transistor pixel for CMOS image sensors (CIS. It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors.

Science.gov (United States)

Lu, Guo-Neng; Tournier, Arnaud; Roy, François; Deschamps, Benoît

2009-01-01

We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

Science.gov (United States)

Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

2018-02-01

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

Experimental study on x-rays dose enhancement effects for floating gate ROMs

CERN Document Server

Guo Hong Xia; Chen Yu Sheng; Han Fu Bin; He Chao Hui; Zhao Hui

2002-01-01

Experimental results of x-ray dose enhancement effects are given for floating gate read-only memory (ROMs) irradiated in the Beijing Synchrotron Radiation Facility. The wrong byte numbers vs. total irradiation dose have been tested and the equivalent relation of total dose damage is provided compared the response of devices irradiated with sup 6 sup 0 Co gamma-ray source. The x-ray dose enhancement factors for floating gate ROMs are obtained firstly in China. These results can be an effective evaluation data for x-rays radiation hardening technology

Isolated photosystem I reaction centers on a functionalized gated high electron mobility transistor.

Science.gov (United States)

Eliza, Sazia A; Lee, Ida; Tulip, Fahmida S; Mostafa, Salwa; Greenbaum, Elias; Ericson, M Nance; Islam, Syed K

2011-09-01

In oxygenic plants, photons are captured with high quantum efficiency by two specialized reaction centers (RC) called Photosystem I (PS I) and Photosystem II (PS II). The captured photon triggers rapid charge separation and the photon energy is converted into an electrostatic potential across the nanometer-scale (~6 nm) reaction centers. The exogenous photovoltages from a single PS I RC have been previously measured using the technique of Kelvin force probe microscopy (KFM). However, biomolecular photovoltaic applications require two-terminal devices. This paper presents for the first time, a micro-device for detection and characterization of isolated PS I RCs. The device is based on an AlGaN/GaN high electron mobility transistor (HEMT) structure. AlGaN/GaN HEMTs show high current throughputs and greater sensitivity to surface charges compared to other field-effect devices. PS I complexes immobilized on the floating gate of AlGaN/GaN HEMTs resulted in significant changes in the device characteristics under illumination. An analytical model has been developed to estimate the RCs of a major orientation on the functionalized gate surface of the HEMTs. © 2011 IEEE

Isolated Photosystem I Reaction Centers on a Functionalized Gated High Electron Mobility Transistor

Energy Technology Data Exchange (ETDEWEB)

Eliza, Sazia A. [University of Tennessee, Knoxville (UTK); Lee, Ida [ORNL; Tulip, Fahmida S [ORNL; Islam, Syed K [University of Tennessee, Knoxville (UTK); Mostafa, Salwa [University of Tennessee, Knoxville (UTK); Greenbaum, Elias [ORNL; Ericson, Milton Nance [ORNL

2011-01-01

In oxygenic plants, photons are captured with high quantum efficiency by two specialized reaction centers (RC) called Photosystem I (PS I) and Photosystem II (PS II). The captured photon triggers rapid charge separation and the photon energy is converted into an electrostatic potential across the nanometer-scale nm reaction centers. The exogenous photovoltages from a single PS I RC have been previously measured using the technique of Kelvin force probe microscopy (KFM). However, biomolecular photovoltaic applications require two-terminal devices. This paper presents for the first time, a micro-device for detection and characterization of isolated PS I RCs. The device is based on an AlGaN/GaN high electron mobility transistor (HEMT) structure. AlGaN/GaN HEMTs show high current throughputs and greater sensitivity to surface charges compared to other field-effect devices. PS I complexes immobilized on the floating gate of AlGaN/GaN HEMTs resulted in significant changes in the device characteristics under illumination. An analytical model has been developed to estimate the RCs of a major orientation on the functionalized gate surface of the HEMTs.

Detection beyond Debye's length with an electrolyte-gated organic field-effect transistor.

Science.gov (United States)

Palazzo, Gerardo; De Tullio, Donato; Magliulo, Maria; Mallardi, Antonia; Intranuovo, Francesca; Mulla, Mohammad Yusuf; Favia, Pietro; Vikholm-Lundin, Inger; Torsi, Luisa

2015-02-04

Electrolyte-gated organic field-effect transistors are successfully used as biosensors to detect binding events occurring at distances from the transistor electronic channel that are much larger than the Debye length in highly concentrated solutions. The sensing mechanism is mainly capacitive and is due to the formation of Donnan's equilibria within the protein layer, leading to an extra capacitance (CDON) in series to the gating system. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

International Nuclear Information System (INIS)

Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

2014-01-01

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

Optimization of pentacene double floating gate memories based on charge injection regulated by SAM functionalization

Directory of Open Access Journals (Sweden)

S. Li

2018-02-01

Full Text Available Pentacene based double nano-floating gate memories (NFGM by using gold nanoparticles (Au NPs and reduced graphene oxide (rGO sheets as charge trapping layers are prepared and demonstrated. Particularly, the NFGM chemically treated by 2,3,4,5,6-pentafluorobenzenethiol (PFBT self-assembled monolayers (SAM exhibits excellent memory performances, including high mobility of 0.23 cm2V-1s-1, the large memory window of 51 V, and the stable retention property more than 108 s. Comparing the performances of NFGM without treating with PFBT SAM, the improving performances of the memory devices by SAM modification are explained by the increase of charge injection, which could be further investigated by XPS and UPS. In particular, the results highlight the utility of SAM modulations and controlling of charge transport in the development of organic transistor memories.

Optimization of pentacene double floating gate memories based on charge injection regulated by SAM functionalization

Science.gov (United States)

Li, S.; Guérin, D.; Lenfant, S.; Lmimouni, K.

2018-02-01

Pentacene based double nano-floating gate memories (NFGM) by using gold nanoparticles (Au NPs) and reduced graphene oxide (rGO) sheets as charge trapping layers are prepared and demonstrated. Particularly, the NFGM chemically treated by 2,3,4,5,6-pentafluorobenzenethiol (PFBT) self-assembled monolayers (SAM) exhibits excellent memory performances, including high mobility of 0.23 cm2V-1s-1, the large memory window of 51 V, and the stable retention property more than 108 s. Comparing the performances of NFGM without treating with PFBT SAM, the improving performances of the memory devices by SAM modification are explained by the increase of charge injection, which could be further investigated by XPS and UPS. In particular, the results highlight the utility of SAM modulations and controlling of charge transport in the development of organic transistor memories.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

Science.gov (United States)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

International Nuclear Information System (INIS)

Wan, Chang Jin; Wan, Qing; Zhu, Li Qiang; Wan, Xiang; Shi, Yi

2016-01-01

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

Energy Technology Data Exchange (ETDEWEB)

Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Wan, Xiang; Shi, Yi, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

2016-01-25

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

Optimal inverter logic gate using 10-nm double gate-all-around (DGAA transistor with asymmetric channel width

Directory of Open Access Journals (Sweden)

Myunghwan Ryu

2016-01-01

Full Text Available We investigate the electrical characteristics of a double-gate-all-around (DGAA transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.

ZnO nanowire-based nano-floating gate memory with Pt nanocrystals embedded in Al{sub 2}O{sub 3} gate oxides

Energy Technology Data Exchange (ETDEWEB)

Yeom, Donghyuk; Kang, Jeongmin; Lee, Myoungwon; Jang, Jaewon; Yun, Junggwon; Jeong, Dong-Young; Yoon, Changjoon; Koo, Jamin; Kim, Sangsig [Department of Electrical Engineering and Institute for Nano Science, Korea University, Seoul 136-701 (Korea, Republic of)], E-mail: sangsig@korea.ac.kr

2008-10-01

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al{sub 2}O{sub 3} tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8 V was observed in its drain current versus gate voltage (I{sub DS}-V{sub GS}) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Science.gov (United States)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Carbon nanotube transistors with graphene oxide films as gate dielectrics

Institute of Scientific and Technical Information of China (English)

无

2010-01-01

Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

Sensing small neurotransmitter-enzyme interaction with nanoporous gated ion-sensitive field effect transistors.

Science.gov (United States)

Kisner, Alexandre; Stockmann, Regina; Jansen, Michael; Yegin, Ugur; Offenhäusser, Andreas; Kubota, Lauro Tatsuo; Mourzina, Yulia

2012-01-15

Ion-sensitive field effect transistors with gates having a high density of nanopores were fabricated and employed to sense the neurotransmitter dopamine with high selectivity and detectability at micromolar range. The nanoporous structure of the gates was produced by applying a relatively simple anodizing process, which yielded a porous alumina layer with pores exhibiting a mean diameter ranging from 20 to 35 nm. Gate-source voltages of the transistors demonstrated a pH-dependence that was linear over a wide range and could be understood as changes in surface charges during protonation and deprotonation. The large surface area provided by the pores allowed the physical immobilization of tyrosinase, which is an enzyme that oxidizes dopamine, on the gates of the transistors, and thus, changes the acid-base behavior on their surfaces. Concentration-dependent dopamine interacting with immobilized tyrosinase showed a linear dependence into a physiological range of interest for dopamine concentration in the changes of gate-source voltages. In comparison with previous approaches, a response time relatively fast for detecting dopamine was obtained. Additionally, selectivity assays for other neurotransmitters that are abundantly found in the brain were examined. These results demonstrate that the nanoporous structure of ion-sensitive field effect transistors can easily be used to immobilize specific enzyme that can readily and selectively detect small neurotransmitter molecule based on its acid-base interaction with the receptor. Therefore, it could serve as a technology platform for molecular studies of neurotransmitter-enzyme binding and drugs screening. Copyright © 2011 Elsevier B.V. All rights reserved.

Mobility overestimation due to gated contacts in organic field-effect transistors

Science.gov (United States)

Bittle, Emily G.; Basham, James I.; Jackson, Thomas N.; Jurchescu, Oana D.; Gundlach, David J.

2016-01-01

Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current–voltage characteristics and interpreted by using the classical metal oxide–semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm2 V−1 s−1), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current–voltage characterization are overestimated by one order of magnitude or more. PMID:26961271

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

Science.gov (United States)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Sanne, A.; Movva, H. C. P.; Kang, S.; McClellan, C.; Corbet, C. M.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

2014-02-24

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

Asymmetric split-gate ambipolar transistor and its circuit application to complementary inverter

NARCIS (Netherlands)

Yoo, H.; Smits, E.C.P.; van Breemen, A.J.J.M.; van der Steen, J.L.; Torricelli, F.; Ghittorelli, M.; Lee, J.; Gelinck, G.; Kim, J.-J.

2016-01-01

Using a concept of asymmetric side gate and main gate, it is shown that it is possible to realize unipolar transport (both p-type and n-type) in a thin-film transistor with a high-performance ambipolar polymer semiconductor. In a complementary inverter, this results in higher noise margin and DC

Gate-induced carrier delocalization in quantum dot field effect transistors.

Science.gov (United States)

Turk, Michael E; Choi, Ji-Hyuk; Oh, Soong Ju; Fafarman, Aaron T; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R; Kikkawa, James M

2014-10-08

We study gate-controlled, low-temperature resistance and magnetotransport in indium-doped CdSe quantum dot field effect transistors. We show that using the gate to accumulate electrons in the quantum dot channel increases the "localization product" (localization length times dielectric constant) describing transport at the Fermi level, as expected for Fermi level changes near a mobility edge. Our measurements suggest that the localization length increases to significantly greater than the quantum dot diameter.

Ionizing/displacement synergistic effects induced by gamma and neutron irradiation in gate-controlled lateral PNP bipolar transistors

Energy Technology Data Exchange (ETDEWEB)

Wang, Chenhui, E-mail: wangchenhui@nint.ac.cn [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O. Box 69-10, Xi’an 710024 (China); Chen, Wei; Yao, Zhibin; Jin, Xiaoming; Liu, Yan; Yang, Shanchao [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O. Box 69-10, Xi’an 710024 (China); Wang, Zhikuan [State Key Laboratory of Analog Integrated Circuit, Chongqing 400060 (China)

2016-09-21

A kind of gate-controlled lateral PNP bipolar transistor has been specially designed to do experimental validations and studies on the ionizing/displacement synergistic effects in the lateral PNP bipolar transistor. The individual and mixed irradiation experiments of gamma rays and neutrons are accomplished on the transistors. The common emitter current gain, gate sweep characteristics and sub-threshold sweep characteristics are measured after each exposure. The results indicate that under the sequential irradiation of gamma rays and neutrons, the response of the gate-controlled lateral PNP bipolar transistor does exhibit ionizing/displacement synergistic effects and base current degradation is more severe than the simple artificial sum of those under the individual gamma and neutron irradiation. Enough attention should be paid to this phenomenon in radiation damage evaluation. - Highlights: • A kind of gate-controlled lateral PNP bipolar transistor has been specially designed to facilitate the analysis of ionizing/displacement synergistic effects induced by the mixed irradiation of gamma and neutron. • The difference between ionizing/displacement synergistic effects and the simple sum of TID and displacement effects is analyzed. • The physical mechanisms of synergistic effects are explained.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

The effects of transistor source-to-gate bridging faults in complex CMOS gates

Science.gov (United States)

Visweswaran, G. S.; Ali, Akhtar-Uz-Zaman M.; Lala, Parag K.; Hartmann, Carlos R. P.

1991-06-01

A study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 microns there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open fault.

Tin Dioxide Electrolyte-Gated Transistors Working in Depletion and Enhancement Modes.

Science.gov (United States)

Valitova, Irina; Natile, Marta Maria; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2017-10-25

Metal oxide semiconductors are interesting for next-generation flexible and transparent electronics because of their performance and reliability. Tin dioxide (SnO 2 ) is a very promising material that has already found applications in sensing, photovoltaics, optoelectronics, and batteries. In this work, we report on electrolyte-gated, solution-processed polycrystalline SnO 2 transistors on both rigid and flexible substrates. For the transistor channel, we used both unpatterned and patterned SnO 2 films. Since decreasing the SnO 2  area in contact with the electrolyte increases the charge-carrier density, patterned transistors operate in the depletion mode, whereas unpatterned ones operate in the enhancement mode. We also fabricated flexible SnO 2 transistors that operate in the enhancement mode that can withstand moderate mechanical bending.

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

Science.gov (United States)

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

Accurate characterization of organic thin film transistors in the presence of gate leakage current

Directory of Open Access Journals (Sweden)

Vinay K. Singh

2011-12-01

Full Text Available The presence of gate leakage through polymer dielectric in organic thin film transistors (OTFT prevents accurate estimation of transistor characteristics especially in subthreshold regime. To mitigate the impact of gate leakage on transfer characteristics and allow accurate estimation of mobility, subthreshold slope and on/off current ratio, a measurement technique involving simultaneous sweep of both gate and drain voltages is proposed. Two dimensional numerical device simulation is used to illustrate the validity of the proposed technique. Experimental results obtained with Pentacene/PMMA OTFT with significant gate leakage show a low on/off current ratio of ∼ 102 and subthreshold is 10 V/decade obtained using conventional measurement technique. The proposed technique reveals that channel on/off current ratio is more than two orders of magnitude higher at ∼104 and subthreshold slope is 4.5 V/decade.

Anomalous degradation behaviors under illuminated gate bias stress in a-Si:H thin film transistor

International Nuclear Information System (INIS)

Tsai, Ming-Yen; Chang, Ting-Chang; Chu, Ann-Kuo; Hsieh, Tien-Yu; Lin, Kun-Yao; Wu, Yi-Chun; Huang, Shih-Feng; Chiang, Cheng-Lung; Chen, Po-Lin; Lai, Tzu-Chieh; Lo, Chang-Cheng; Lien, Alan

2014-01-01

This study investigates the impact of gate bias stress with and without light illumination in a-Si:H thin film transistors. It has been observed that the I–V curve shifts toward the positive direction after negative and positive gate bias stress due to interface state creation at the gate dielectric. However, this study found that threshold voltages shift negatively and that the transconductance curve maxima are anomalously degraded under illuminated positive gate bias stress. In addition, threshold voltages shift positively under illuminated negative gate bias stress. These degradation behaviors can be ascribed to charge trapping in the passivation layer dominating degradation instability and are verified by a double gate a-Si:H device. - Highlights: • There is abnormal V T shift induced by illuminated gate bias stress in a-Si:H thin film transistors. • Electron–hole pair is generated via trap-assisted photoexcitation. • Abnormal transconductance hump is induced by the leakage current from back channel. • Charge trapping in the passivation layer is likely due to the fact that a constant voltage has been applied to the top gate

Total dose induced latch in short channel NMOS/SOI transistors

International Nuclear Information System (INIS)

Ferlet-Cavrois, V.; Quoizola, S.; Musseau, O.; Flament, O.; Leray, J.L.; Pelloie, J.L.; Raynaud, C.; Faynot, O.

1998-01-01

A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given critical dose. Above this dose, the authors still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic condition is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies

Sidewall gated double well quasi-one-dimensional resonant tunneling transistors

Science.gov (United States)

Kolagunta, V. R.; Janes, D. B.; Melloch, M. R.; Youtsey, C.

1997-12-01

We present gating characteristics of submicron vertical resonant tunneling transistors in double quantum well heterostructures. Current-voltage characteristics at room temperature and 77 K for devices with minimum feature widths of 0.9 and 0.7 μm are presented and discussed. The evolution of the I-V characteristics with increasing negative gate biases is related to the change in the lateral confinement, with a transition from a large area 2D to a quasi-1D. Even gating of multiple wells and lateral confinement effects observable at 77 K make these devices ideally suited for applications in multi-valued logic systems and low-dimensional structures.

Top-gate organic depletion and inversion transistors with doped channel and injection contact

Energy Technology Data Exchange (ETDEWEB)

Liu, Xuhai; Kasemann, Daniel, E-mail: daniel.kasemann@iapp.de; Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Strasse 1, 01069 Dresden (Germany)

2015-03-09

Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

Gate-controlled quantum collimation in nanocolumn resonant tunnelling transistors

International Nuclear Information System (INIS)

Wensorra, J; Lepsa, M I; Trellenkamp, S; Moers, J; Lueth, H; Indlekofer, K M

2009-01-01

Nanoscaled resonant tunneling transistors (RTT) based on MBE-grown GaAs/AlAs double-barrier quantum well (DBQW) structures have been fabricated by a top-down approach using electron-beam lithographic definition of the vertical nanocolumns. In the preparation process, a reproducible mask alignment accuracy of below 10 nm has been achieved and the all-around metal gate at the level of the DBQW structure has been positioned at a distance of about 20 nm relative to the semiconductor nanocolumn. Due to the specific doping profile n ++ /i/n ++ along the transistor nanocolumn, a particular confining potential is established for devices with diameters smaller than 70 nm, which causes a collimation effect of the propagating electrons. Under these conditions, room temperature optimum performance of the nano-RTTs is achieved with peak-to-valley current ratios above 2 and a peak current swing factor of about 6 for gate voltages between -6 and +6 V. These values indicate that our nano-RTTs can be successfully used in low power fast nanoelectronic circuits.

Double-gate junctionless transistor model including short-channel effects

International Nuclear Information System (INIS)

Paz, B C; Pavanello, M A; Ávila-Herrera, F; Cerdeira, A

2015-01-01

This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage (V TH ), subthreshold slope (S) and drain induced barrier lowering. (paper)

Ionizing radiation effects on floating gates

International Nuclear Information System (INIS)

Cellere, G.; Paccagnella, A.; Visconti, A.; Bonanomi, M.

2004-01-01

Floating gate (FG) memories, and in particular Flash, are the dominant among modern nonvolatile memory technologies. Their performance under ionizing radiation was traditionally studied for the use in space, but has become of general interest in recent years. We are showing results on the charge loss from programmed FG arrays after 10 keV x-rays exposure. Exposure to ionizing radiation results in progressive discharge of the FG. More advanced devices, featuring smaller FG, are less sensitive to ionizing radiation that older ones. The reason is identified in the photoemission of electrons from FG, since at high doses it dominates over charge loss deriving from electron/hole pairs generation in the oxides

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

Science.gov (United States)

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Artificial Synapses Based on in-Plane Gate Organic Electrochemical Transistors.

Science.gov (United States)

Qian, Chuan; Sun, Jia; Kong, Ling-An; Gou, Guangyang; Yang, Junliang; He, Jun; Gao, Yongli; Wan, Qing

2016-10-05

Realization of biological synapses using electronic devices is regarded as the basic building blocks for neuromorphic engineering and artificial neural network. With the advantages of biocompatibility, low cost, flexibility, and compatible with printing and roll-to-roll processes, the artificial synapse based on organic transistor is of great interest. In this paper, the artificial synapse simulation by ion-gel gated organic field-effect transistors (FETs) with poly(3-hexylthiophene) (P3HT) active channel is demonstrated. Key features of the synaptic behaviors, such as paired-pulse facilitation (PPF), short-term plasticity (STP), self-tuning, the spike logic operation, spatiotemporal dentritic integration, and modulation are successfully mimicked. Furthermore, the interface doping processes of electrolyte ions between the active P3HT layer and ion gels is comprehensively studied for confirming the operating processes underlying the conductivity and excitatory postsynaptic current (EPSC) variations in the organic synaptic devices. This study represents an important step toward building future artificial neuromorphic systems with newly emerged ion gel gated organic synaptic devices.

Beyond the Nernst-limit with dual-gate ZnO ion-sensitive field-effect transistors

NARCIS (Netherlands)

Spijkman, M.; Smits, E.C.P.; Cillessen, J.F.M.; Biscarini, F.; Blom, P.W.M.; Leeuw, D.M. de

2011-01-01

The sensitivity of conventional ion-sensitive field-effect transistors (ISFETs) is limited to 59 mV/pH, which is the maximum detectable change in electrochemical potential according to the Nernst equation. Here we demonstrate a transducer based on a ZnO dual-gate field-effect transistor that

Tunnel field-effect transistor with two gated intrinsic regions

Directory of Open Access Journals (Sweden)

Y. Zhang

2014-07-01

Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.

Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

Energy Technology Data Exchange (ETDEWEB)

Chao, Jin Yu [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn; Xiao, Hui [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Yuan, Zhi Guo, E-mail: ncityzg@163.com [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China)

2015-12-21

Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

Science.gov (United States)

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Characteristics of dual-gate thin-film transistors for applications in digital radiology

International Nuclear Information System (INIS)

Waechter, D.; Huang, Z.; Zhao, W.; Blevis, I.; Rowlands, J.A.

1996-01-01

A large-area flat-panel detector for digital radiology is being developed. The detector uses an array of dual-gate thin-film transistors (TFTs) to read out X-ray-generated charge produced in an amorphous selenium (a-Se) layer. The TFTs use CdSe as the semiconductor and use the bottom gate for row selection. The top gate can be divided into a 'deliberate' gate, covering most of the channel length, and small 'parasitic' gates that consist of: overlap of source or drain metal over the top-gate oxide; and gap regions in the metal that are covered only by the a-Se. In this paper we present the properties of dual-gate TFTs and examine the effect of both the deliberate and parasitic gates on the detector operation. Various options for controlling the top-gate potential are analyzed and discussed. (author)

Molecular gated-AlGaN/GaN high electron mobility transistor for pH detection.

Science.gov (United States)

Ding, Xiangzhen; Yang, Shuai; Miao, Bin; Gu, Le; Gu, Zhiqi; Zhang, Jian; Wu, Baojun; Wang, Hong; Wu, Dongmin; Li, Jiadong

2018-04-18

A molecular gated-AlGaN/GaN high electron mobility transistor has been developed for pH detection. The sensing surface of the sensor was modified with 3-aminopropyltriethoxysilane to provide amphoteric amine groups, which would play the role of receptors for pH detection. On modification with 3-aminopropyltriethoxysilane, the transistor exhibits good chemical stability in hydrochloric acid solution and is sensitive for pH detection. Thus, our molecular gated-AlGaN/GaN high electron mobility transistor acheived good electrical performances such as chemical stability (remained stable in hydrochloric acid solution), good sensitivity (37.17 μA/pH) and low hysteresis. The results indicate a promising future for high-quality sensors for pH detection.

Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors.

Science.gov (United States)

Nazir, Ghazanfar; Khan, Muhammad Farooq; Aftab, Sikandar; Afzal, Amir Muhammad; Dastgeer, Ghulam; Rehman, Malik Abdul; Seo, Yongho; Eom, Jonghwa

2017-12-28

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R vert ) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R planar ) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R vert increases, but R planar decreases. The increase of R vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Science.gov (United States)

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

Science.gov (United States)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

Science.gov (United States)

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

Science.gov (United States)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses

Energy Technology Data Exchange (ETDEWEB)

Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

2016-06-20

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

Science.gov (United States)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

Science.gov (United States)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

Hysteresis analysis of graphene transistor under repeated test and gate voltage stress

International Nuclear Information System (INIS)

Yang Jie; Jia Kunpeng; Su Yajuan; Zhao Chao; Chen Yang

2014-01-01

The current transport characteristic is studied systematically based on a back-gate graphene field effect transistor, under repeated test and gate voltage stress. The interface trapped charges caused by the gate voltage sweep process screens the gate electric field, and results in the neutral point voltage shift between the forth and back sweep direction. In the repeated test process, the neutral point voltage keeps increasing with test times in both forth and back sweeps, which indicates the existence of interface trapped electrons residual and accumulation. In gate voltage stress experiment, the relative neutral point voltage significantly decreases with the reducing of stress voltage, especially in −40 V, which illustrates the driven-out phenomenon of trapped electrons under negative voltage stress. (semiconductor devices)

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

International Nuclear Information System (INIS)

Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

2016-01-01

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

Science.gov (United States)

Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

2004-06-01

The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

Energy Technology Data Exchange (ETDEWEB)

Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

2016-08-30

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Frequency Response of Graphene Electrolyte-Gated Field-Effect Transistors

Directory of Open Access Journals (Sweden)

Charles Mackin

2018-02-01

Full Text Available This work develops the first frequency-dependent small-signal model for graphene electrolyte-gated field-effect transistors (EGFETs. Graphene EGFETs are microfabricated to measure intrinsic voltage gain, frequency response, and to develop a frequency-dependent small-signal model. The transfer function of the graphene EGFET small-signal model is found to contain a unique pole due to a resistive element, which stems from electrolyte gating. Intrinsic voltage gain, cutoff frequency, and transition frequency for the microfabricated graphene EGFETs are approximately 3.1 V/V, 1.9 kHz, and 6.9 kHz, respectively. This work marks a critical step in the development of high-speed chemical and biological sensors using graphene EGFETs.

Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

Science.gov (United States)

Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2016-04-20

In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Gate Tunable Transport in Graphene/MoS2/(Cr/Au Vertical Field-Effect Transistors

Directory of Open Access Journals (Sweden)

Ghazanfar Nazir

2017-12-01

Full Text Available Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS2/(Cr/Au vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr, the electrical transport in our Gr/MoS2/(Cr/Au vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS2 can be modified by back-gate voltage and the current bias. Vertical resistance (Rvert of a Gr/MoS2/(Cr/Au transistor is compared with planar resistance (Rplanar of a conventional lateral MoS2 field-effect transistor. We have also studied electrical properties for various thicknesses of MoS2 channels in both vertical and lateral transistors. As the thickness of MoS2 increases, Rvert increases, but Rplanar decreases. The increase of Rvert in the thicker MoS2 film is attributed to the interlayer resistance in the vertical direction. However, Rplanar shows a lower value for a thicker MoS2 film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

VHDL-based programming environment for Floating-Gate analog memory cell

Directory of Open Access Journals (Sweden)

Carlos Alberto dos Reis Filho

2005-02-01

Full Text Available An implementation in CMOS technology of a Floating-Gate Analog Memory Cell and Programming Environment is presented. A digital closed-loop control compares a reference value set by user and the memory output and after cycling, the memory output is updated and the new value stored. The circuit can be used as analog trimming for VLSI applications where mechanical trimming associated with postprocessing chip is prohibitive due to high costs.

Measurements of dose with individual FAMOS transistors

Energy Technology Data Exchange (ETDEWEB)

Scheick, L.Z.; McNulty, P.J.; Roth, D.R.; Davis, M.G.; Mason, B.E.

1999-12-01

A new method is described for measuring the doses absorbed by microstructures from an exposure to ionizing radiation. The decrease in the duration of UltraViolet light (UV) exposure required to erase each cell of a commercial UltraViolet erasable Programmable Read Only Memory (UVPROM) correlates with the dose absorbed by the floating gate of that transistor. This technique facilitates analysis of the microdose distribution across the array and the occurrence of Single Event Upset (SEU) like anomalous shifts due to rare large energy-deposition events.

Measurements of dose with individual FAMOS transistors

International Nuclear Information System (INIS)

Scheick, L.Z.; McNulty, P.J.; Roth, D.R.; Davis, M.G.; Mason, B.E.

1999-01-01

A new method is described for measuring the doses absorbed by microstructures from an exposure to ionizing radiation. The decrease in the duration of UltraViolet light (UV) exposure required to erase each cell of a commercial UltraViolet erasable Programmable Read Only Memory (UVPROM) correlates with the dose absorbed by the floating gate of that transistor. This technique facilitates analysis of the microdose distribution across the array and the occurrence of Single Event Upset (SEU) like anomalous shifts due to rare large energy-deposition events

Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

Science.gov (United States)

Takulapalli, Bharath R

2010-02-23

Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.

Modeling nanowire and double-gate junctionless field-effect transistors

CERN Document Server

Jazaeri, Farzan

2018-01-01

The first book on the topic, this is a comprehensive introduction to the modeling and design of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages and limitations of the technology, the authors also provide a thorough overview of published analytical models for double-gate and nanowire configurations, before offering a general introduction to the EPFL charge-based model of junctionless FETs. Important features are introduced gradually, including nanowire versus double-gate equivalence, technological design space, junctionless FET performances, short channel effects, transcapacitances, asymmetric operation, thermal noise, interface traps, and the junction FET. Additional features compatible with biosensor applications are also discussed. This is a valuable resource for students and researchers looking to understand more about this new and fast developing field.

Simulation of Heating of an Oil-Cooled Insulated Gate Bipolar Transistors Converter Model

National Research Council Canada - National Science Library

Ovrebo, Gregory

2004-01-01

I used SolidWorks a three-dimensional modeling software, and FloWorks, a fluid dynamics analysis tool, to simulate oil flow and heat transfer in a heat sink structure attached to three insulated gate bipolar transistors...

Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

Science.gov (United States)

2010-03-31

floating gate devices and metal-insulator-oxide-semiconductor (MIOS) devices. First attempts to use polarizable gate insulators in combination with...bulk of the semiconductor (ii) Due to the polarizable gate dielectric (iii) dipole polarization and (iv)electret effect due to mobile ions in the...characterization was carried out under an argon environment inside the glove box. An Agilent model E5273A with a two source-measurement unit instrument was

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea; Svendsen, Winnie Edith; Dimaki, Maria

2016-01-01

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO{sub 2} gate insulator

Energy Technology Data Exchange (ETDEWEB)

Song, Yang, E-mail: yang_song@brown.edu [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); Zaslavsky, A. [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States); Paine, D.C. [School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States)

2016-09-01

We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO{sub 2} gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al{sub 2}O{sub 3}/HfO{sub 2} gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20 nm thick IZO channel, forming a partially oxidized HfO{sub x} layer, without any additional insulator in-between. After annealing in air at 300 °C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO{sub 2} gate insulator with a low interface trapped charge density N{sub TC} ~ 2.3 × 10{sup 11} cm{sup −2} and acceptably low gate leakage < 3 × 10{sup −7} A/cm{sup 2} at gate voltage V{sub G} = 1 V. The annealed TFTs with gate length L{sub G} = 50 μm have high mobility ~ 95 cm{sup 2}/V ∙ s (determined via the Y-function technique), high on/off ratio ~ 10{sup 7}, near-zero threshold voltage V{sub T} = − 0.02 V, and a subthreshold swing of 0.062 V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing L{sub G}, indicating that high-performance top-gated HfO{sub 2}-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach. - Highlights: • High-performance indium–zinc–oxide (IZO) thin film transistors (TFTs). • Single-step in-situ dielectric formation approach simplifies fabrication process. • During anneal, reaction between HfO{sub x} and IZO channel forms a high quality HfO{sub 2} layer. • Gate insulator HfO{sub 2} shows low interface trapped charge and small gate leakage. • TFTs have high mobility, near-zero threshold voltage, and a low subthreshold swing.

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

Energy Technology Data Exchange (ETDEWEB)

Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 02447 (Korea, Republic of)

2016-07-15

We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

Phosphorus oxide gate dielectric for black phosphorus field effect transistors

Science.gov (United States)

Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

2018-04-01

The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

Science.gov (United States)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

Radiation effects in a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors

International Nuclear Information System (INIS)

Brucker, G.J.; Heagerty, W.

1976-01-01

This paper presents the results obtained from total dose and transient radiation tests on a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors. Samples were irradiated by cobalt-60 gamma rays under worst-case conditions, and by 10-MeV electron pulses of 50-ns and 4.4-μs duration. Devices were fabricated with three different insulators; the two discussed here are standard wet oxide and a pyrogenic oxide. Test transistors on the D/A chips made it possible to diagnose the failure modes of the converter and to evaluate some special designs. These consisted of standard edge p- and n-channel transistors, edgeless units, edgeless tetrode transistors, and an edgeless type transmission gate with a diode clamp from substrate to gate. The total dose results indicate that the pyrogenic oxide increased the failure dose of the operational amplifier portion of the converter from 10 3 rads (Si) to 2 x 10 6 rads (Si); however, the sample and hold failed after exposure to a low level of 10 3 rads (Si). Test devices indicated this to be due to the radiation-induced leakage current of the transmission gate which discharges the sample and hold capacitor. The diode clamp decreased the threshold voltage shifts and the leakage currents. The edgeless devices improved the device performance because of a more abrupt turn-on. Narrow-pulse test data indicated that the edgeless units produced less photocurrent than the edge units by about a factor of three to four. Converter upset levels are less than or equal to 10 9 rads/s due to precision requirements which make a few millivolt transients untenable

Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

Energy Technology Data Exchange (ETDEWEB)

Clément, N., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr; Han, X. L. [Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d' Ascq (France); Larrieu, G., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr [Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, Universite de Toulouse, 7 Avenue Colonel Roche, 31077 Toulouse (France)

2013-12-23

Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

Science.gov (United States)

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

OpenAIRE

Lin, Yu-Hsien; Chou, Jay-Chi

2014-01-01

This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using hafnium oxide (HfO2) gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chem...

Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency

International Nuclear Information System (INIS)

Sehgal, Amit; Mangla, Tina; Gupta, Mridula; Gupta, R.S.

2008-01-01

In this work, a two-dimensional potential distribution formulation is presented for multi-material gate poly-crystalline silicon thin film transistors. The developed formulation incorporates the effects due to traps and grain-boundaries. In short-channel devices, short-channel effects and drain-induced barrier lowering (DIBL) effect exists, and are accounted for in the analysis. The work aims at the reduction of DIBL effect and grain-boundary effects i.e. to reduce the potential barriers generated in the channel by employing gate-engineered structures. A study of work-functions and electrode lengths of multi-material gate electrode is done to suppress the potential barriers, hot electron effect and to improve the carrier transport efficiency. Green's function approach is adopted for the two-dimensional potential solution. The results obtained show a good agreement with simulated results, thus, demonstrating the validity of our model

Bias-induced migration of ionized donors in amorphous oxide semiconductor thin-film transistors with full bottom-gate and partial top-gate structures

Directory of Open Access Journals (Sweden)

Mallory Mativenga

2012-09-01

Full Text Available Bias-induced charge migration in amorphous oxide semiconductor thin-film transistors (TFTs confirmed by overshoots of mobility after bias stressing dual gated TFTs is presented. The overshoots in mobility are reversible and only occur in TFTs with a full bottom-gate (covers the whole channel and partial top-gate (covers only a portion of the channel, indicating a bias-induced uneven distribution of ionized donors: Ionized donors migrate towards the region of the channel that is located underneath the partial top-gate and the decrease in the density of ionized donors in the uncovered portion results in the reversible increase in mobility.

Self-aligned top-gate InGaZnO thin film transistors using SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Chen, Rongsheng; Zhou, Wei; Zhang, Meng; Wong, Man; Kwok, Hoi Sing

2013-12-02

Self-aligned top-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors (TFTs) utilizing SiO{sub 2}/Al{sub 2}O{sub 3} stack thin films as gate dielectric are developed in this paper. Due to high quality of the high-k Al{sub 2}O{sub 3} and good interface between active layer and gate dielectric, the resulting a-IGZO TFT exhibits good electrical performance including field-effect mobility of 9 cm{sup 2}/Vs, threshold voltage of 2.2 V, subthreshold swing of 0.2 V/decade, and on/off current ratio of 1 × 10{sup 7}. With scaling down of the channel length, good characteristics are also obtained with a small shift of the threshold voltage and no degradation of subthreshold swing. - Highlights: • Self-aligned top-gate indium–gallium–zinc oxide thin-film transistor is proposed. • SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric is proposed. • The source/drain areas are hydrogen-doped by CHF{sub 3} plasma. • The devices show good electrical performance and scaling down behavior.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

Science.gov (United States)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

Fabrication and characterization of V-gate AlGaN/GaN high-electron-mobility transistors

International Nuclear Information System (INIS)

Zhang Kai; Cao Meng-Yi; Chen Yong-He; Yang Li-Yuan; Wang Chong; Ma Xiao-Hua; Hao Yue

2013-01-01

V-gate GaN high-electron-mobility transistors (HEMTs) are fabricated and investigated systematically. A V-shaped recess geometry is obtained using an improved Si 3 N 4 recess etching technology. Compared with standard HEMTs, the fabricated V-gate HEMTs exhibit a 17% higher peak extrinsic transconductance due to a narrowed gate foot. Moreover, both the gate leakage and current dispersion are dramatically suppressed simultaneously, although a slight degradation of frequency response is observed. Based on a two-dimensional electric field simulation using Silvaco “ATLAS” for both standard HEMTs and V-gate HEMTs, the relaxation in peak electric field at the gate edge is identified as the predominant factor leading to the superior performance of V-gate HEMTs. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

A Novel Multi-Finger Gate Structure of AlGaN/GaN High Electron Mobility Transistor

International Nuclear Information System (INIS)

Cui Lei; Wang Quan; Wang Xiao-Liang; Xiao Hong-Ling; Wang Cui-Mei; Jiang Li-Juan; Feng Chun; Yin Hai-Bo; Gong Jia-Min; Li Bai-Quan; Wang Zhan-Guo

2015-01-01

A novel multi-finger gate high electron mobility transistor (HEMT) is designed to reduce the peak electric field value at the drain-side gate edge when the device is at off-state. The effective gate length (L_e_f_f) of the multi-finger gate device is smaller than that of the field plate gate device. In this work, field plate gate, five-finger gate and ten-finger gate devices are simulated. The results of the simulation indicate that the multi-finger gate device has a lower peak value than the device with the gate field plate. Moreover, this value would be further reduced when the number of gate fingers is increased. In addition, it has the potential to make the HEMT work in a higher frequency since it has a lower effective length of gate. (paper)

Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

International Nuclear Information System (INIS)

Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo; Kim, Hwajeong; Lee, Joon-Hyung; Park, Soo-Young; Kang, Inn-Kyu

2014-01-01

We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4 ′ -pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm 2 /Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V D ) and gate (V G ) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V D and V G . The best voltage combination was V D = −0.2 V and V G = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

Science.gov (United States)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Transistor-based particle detection systems and methods

Science.gov (United States)

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

KAUST Repository

Salas-Villasenor, A. L.; Mejia, I.; Hovarth, J.; Alshareef, Husam N.; Cha, D. K.; Ramirez-Bon, R.; Gnade, B. E.; Quevedo-Lopez, M. A.

2010-01-01

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

KAUST Repository

Salas-Villasenor, A. L.

2010-06-29

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

Leakage and field emission in side-gate graphene field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.; Cucolo, A. M. [Physics Department “E.R. Caianiello,” University of Salerno, via G. Paolo II, 84084 Fisciano (Italy); CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Giubileo, F. [CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Russo, S.; Unal, S. [Physics Department, University of Exeter, Stocker Road 6, Exeter, Devon EX4 4QL (United Kingdom); Passacantando, M.; Grossi, V. [Department of Physical and Chemical Sciences, University of L' Aquila, Via Vetoio, 67100 Coppito, L' Aquila (Italy)

2016-07-11

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current density as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Science.gov (United States)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Influence of O2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

International Nuclear Information System (INIS)

Ganapathi, Kolla Lakshmi; Bhat, Navakanta; Mohan, Sangeneni

2014-01-01

HfO 2  thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O 2  flow rate, during evaporation is optimized for 35 nm thick HfO 2  films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O 2  flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O 2  flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO 2  films deposited at two O 2  flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO 2  film deposited at 3 SCCM O 2  flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices. (paper)

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

Science.gov (United States)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

MOSFET-BJT hybrid mode of the gated lateral bipolar junction transistor for C-reactive protein detection.

Science.gov (United States)

Yuan, Heng; Kwon, Hyurk-Choon; Yeom, Se-Hyuk; Kwon, Dae-Hyuk; Kang, Shin-Won

2011-10-15

In this study, we propose a novel biosensor based on a gated lateral bipolar junction transistor (BJT) for biomaterial detection. The gated lateral BJT can function as both a BJT and a metal-oxide-semiconductor field-effect transistor (MOSFET) with both the emitter and source, and the collector and drain, coupled. C-reactive protein (CRP), which is an important disease marker in clinical examinations, can be detected using the proposed device. In the MOSFET-BJT hybrid mode, the sensitivity, selectivity, and reproducibility of the gated lateral BJT for biosensors were evaluated in this study. According to the results, in the MOSFET-BJT hybrid mode, the gated lateral BJT shows good selectivity and reproducibility. Changes in the emitter (source) current of the device for CRP antigen detection were approximately 0.65, 0.72, and 0.80 μA/decade at base currents of -50, -30, and -10 μA, respectively. The proposed device has significant application in the detection of certain biomaterials that require a dilution process using a common biosensor, such as a MOSFET-based biosensor. Copyright © 2011 Elsevier B.V. All rights reserved.

A novel Tunneling Graphene Nano Ribbon Field Effect Transistor with dual material gate: Numerical studies

Science.gov (United States)

Ghoreishi, Seyed Saleh; Saghafi, Kamyar; Yousefi, Reza; Moravvej-farshi, Mohammad Kazem

2016-09-01

In this work, we present Dual Material Gate Tunneling Graphene Nano-Ribbon Field Effect Transistors (DMG-T-GNRFET) mainly to suppress the am-bipolar current with assumption that sub-threshold swing which is one of the important characteristics of tunneling transistors must not be degraded. In the proposed structure, dual material gates with different work functions are used. Our investigations are based on numerical simulations which self-consistently solves the 2D Poisson based on an atomistic mode-space approach and Schrodinger equations, within the Non-Equilibrium Green's (NEGF). The proposed device shows lower off-current and on-off ratio becomes 5order of magnitude greater than the conventional device. Also two different short channel effects: Drain Induced Barrier Shortening (DIBS) and hot-electron effect are improved in the proposed device compare to the main structure.

A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

International Nuclear Information System (INIS)

Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

2011-01-01

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (R on,sp ), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its R on,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and R on,sp are investigated, and the optimized results with BV of 83 V and R on,sp of 54 mΩ·mm 2 are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior 'R on,sp /BV' trade-off to the conventional VDMOS (a 38% reduction of R on,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of R on,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively. (interdisciplinary physics and related areas of science and technology)

Tungsten trioxide as high-{kappa} gate dielectric for highly transparent and temperature-stable zinc-oxide-based thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Michael; Wenckstern, Holger von; Grundmann, Marius [Universitaet Leipzig, Fakultaet fuer Physik und Geowissenschaften, Institut fuer Experimentelle Physik II, Linnestr. 5, 04103 Leipzig (Germany)

2012-07-01

We demonstrate metal-insulator-semiconductor field-effect transistors with high-{kappa}, room-temperature deposited, highly transparent tungsten trioxide (WO{sub 3}) as gate dielectric. The channel material consists of a zinc oxide (ZnO) thin-film. The transmittance and resistivity of WO{sub 3} films was tuned in order to obtain a highly transparent and insulating WO{sub 3} dielectric. The devices were processed by standard photolithography using lift-off technique. On top of the WO{sub 3} dielectric a highly transparent and conductive oxide consisting of ZnO: Al 3% wt. was deposited. The gate structure of the devices exhibits an average transmittance in the visible spectral range of 86%. The on/off-current ratio is larger than 10{sup 8} with off- and gate leakage-currents below 3 x 10{sup -8} A/cm{sup 2}. Due to the high relative permittivity of {epsilon}{sub r} {approx} 70, a gate voltage sweep of only 2 V is necessary to turn the transistor on and off with a minimum subthreshold swing of 80 mV/decade. The channel mobility of the transistors equals the Hall-effect mobility with a value of 5 cm{sup 2}/Vs. It is furthermore shown, that the devices are stable up to operating temperatures of at least 150 C.

Extended Gate Field-Effect Transistor Biosensors for Point-Of-Care Testing of Uric Acid.

Science.gov (United States)

Guan, Weihua; Reed, Mark A

2017-01-01

An enzyme-free redox potential sensor using off-chip extended-gate field effect transistor (EGFET) with a ferrocenyl-alkanethiol modified gold electrode has been used to quantify uric acid concentration in human serum and urine. Hexacyanoferrate (II) and (III) ions are used as redox reagent. The potentiometric sensor measures the interface potential on the ferrocene immobilized gold electrode, which is modulated by the redox reaction between uric acid and hexacyanoferrate ions. The device shows a near Nernstian response to uric acid and is highly specific to uric acid in human serum and urine. The interference that comes from glucose, bilirubin, ascorbic acid, and hemoglobin is negligible in the normal concentration range of these interferents. The sensor also exhibits excellent long term reliability and is regenerative. This extended gate field effect transistor based sensor is promising for point-of-care detection of uric acid due to the small size, low cost, and low sample volume consumption.

Extended-gate organic field-effect transistor for the detection of histamine in water

Science.gov (United States)

Minamiki, Tsukuru; Minami, Tsuyoshi; Yokoyama, Daisuke; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

2015-04-01

As part of our ongoing research program to develop health care sensors based on organic field-effect transistor (OFET) devices, we have attempted to detect histamine using an extended-gate OFET. Histamine is found in spoiled or decayed fish, and causes foodborne illness known as scombroid food poisoning. The new OFET device possesses an extended gate functionalized by carboxyalkanethiol that can interact with histamine. As a result, we have succeeded in detecting histamine in water through a shift in OFET threshold voltage. This result indicates the potential utility of the designed OFET devices in food freshness sensing.

Rendering high charge density of states in ionic liquid-gated MoS 2 transistors

NARCIS (Netherlands)

Lee, Y.; Lee, J.; Kim, S.; Park, H.S.

2014-01-01

We investigated high charge density of states (DOS) in the bandgap of MoS2 nanosheets with variable temperature measurements on ionic liquid-gated MoS2 transistors. The thermally activated charge transport indicates that the electrical current in the two-dimensional MoS 2 nanosheets under high

AlGaN/GaN high-electron-mobility transistors with transparent gates by Al-doped ZnO

International Nuclear Information System (INIS)

Wang Chong; He Yun-Long; Zheng Xue-Feng; Ma Xiao-Hua; Zhang Jin-Cheng; Hao Yue

2013-01-01

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Al-doped ZnO (AZO) transparent gate electrodes are fabricated, and Ni/Au/Ni-gated HEMTs are produced in comparison. The AZO-gated HEMTs show good DC characteristics and Schottky rectifying characteristics, and the gate electrodes achieve excellent transparencies. Compared with Ni/Au/Ni-gated HEMTs, AZO-gated HEMTs show a low saturation current, high threshold voltage, high Schottky barrier height, and low gate reverse leakage current. Due to the higher gate resistivity, AZO-gated HEMTs exhibit a current—gain cutoff frequency (f T ) of 10 GHz and a power gain cutoff frequency (f max ) of 5 GHz, and lower maximum oscillation frequency than Ni/Au/Ni-gated HEMTs. Moreover, the C—V characteristics are measured and the gate interface characteristics of the AZO-gated devices are investigated by a C—V dual sweep

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

Science.gov (United States)

Edmonds, L. D.

2016-01-01

Since advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

Silicon on insulator self-aligned transistors

Science.gov (United States)

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Analytical modeling of split-gate junction-less transistor for a biosensor application

Directory of Open Access Journals (Sweden)

Shradhya Singh

2018-04-01

Full Text Available This paper represents the analytical modeling of split-gate Dielectric Modulated Junction Less Transistor (JLT for label free electrical detection of bio molecules. Some part of the channel region is opened for providing the binding sites for the bio molecules unlike conventional MOSFET which is enclosed with the gate electrode. Due to this open area, the surface potential of this region affected by the charged and neutral bio molecules immobilized to the open region of channel. Surface potential of the channel region obtained by solving two-Dimensional Poisson's equation by potential profile having parabolic nature through channel region using technique called conformal mapping. By deriving the surface potential model, derivation of threshold model can also be done. For the detection of bio molecule, variation in to the threshold voltage due to binding of bio molecule in the gate underlap region is the sensing metric.

Implementation of Self-Bias Transistor on Voting Logic

International Nuclear Information System (INIS)

Harzawardi Hasim; Syirrazie Che Soh

2014-01-01

Study in the eld of digital integrated circuit (IC) already become common to the modern industrial. Day by day we have been introduced with new gadget that was developed based on transistor. This paper will study the implementation of self-bias transistor on voting logic. The self-bias transistor will connected both on pull-up network and pull-down network. On previous research, study on comparison of total number of transistors, time propagation delay, and frequency between NAND and NOR gate of voting logic. It's show, with the same number of transistor, NAND gate achieve high frequency and low time propagation delay compare to NOR gate. We extend this analysis by comparing the total number of transistor, time propagation delay, frequency and power dissipation between common NAND gate with self-bias NAND gate. Extensive LTSpice simulations were performed using IBM 90 nm CMOS(Complementary Metal Oxide Semiconductor) process technology. The result show self-bias voting NAND gate consumes 54 % less power dissipation, 43% slow frequency and 43 % high time propagation delay compare to common voting NAND gate. (author)

A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

Institute of Scientific and Technical Information of China (English)

Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

2011-01-01

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (Ron,sp),whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region,is proposed.The theoretical limit of its Ron,sp is deduced,the influence of structure parameters on the breakdown voltage (BV) and Ron,sp are investigated,and the optimized results with BV of 83 V and Ron,sp of 54 mΩ.mm2 are obtained.Simulations show that the inhomogencous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET)has a superior “Ron,sp/BV” trade-off to the conventional VDMOS (a 38％ reduction of Ron,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10％ reduction of Ron,sp with the same BV).The inhomogeneous-floatingislands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET.Its reverse recovery peak current,reverse recovery time and reverse recovery charge are about 50,80 and 40％ of those of the superjunction MOSFET,respectively.

New fabrication technique using side-wall-type plasma-enhanced chemical-vapor deposition for a floating gate memory with a Si nanodot

Energy Technology Data Exchange (ETDEWEB)

Ichikawa, Kazunori; Punchaipetch, Prakaipetch; Yano, Hiroshi; Hatayama, Tomoaki; Uraoka, Yukiharu; Fuyuki, Takashi [Nara Institute of Science and Techonology, Ikoma, Nara (Japan); Tomyo, Atsushi; Takahashi, Eiji; Hayashi, Tsukasa; Ogata, Kiyoshi [Nissin Electric Co., Ltd., Kyoto (Japan)

2006-08-15

We have used side-wall-type plasma-enhanced chemical-vapor deposition (PECVD)to fabricate a floating gate memory using a Si nano-crystal dot on thermal SiO{sub 2} at a low temperature of 430 .deg. C. Atomic and radical hydrogen plays an important role in the low-temperature formation of the dot. Transmission electron microscopy (TEM) and atomic force microscopy (AFM) analyses revealed that the average dot size and density were approximately 5 nm and 8.5 X 10{sup 11} cm{sup -2}, respectively. The electronic properties were investigated with metal-oxide-semiconductor-field-effect transistors (MOSFETs) by embedding the nanocrystal dots into SiO{sub 2} fabricated using CVD. Electron charging and discharging were clearly confirmed at room temperature by the transient behavior of the capacitance and the transfer curve. The number of electrons confined in a single dot was approximately one. Furthermore, we evaluated the electronic behavior by varying the bias condition or the operating temperature. The critical charge density could be confirmed to be independent of the injection condition.

Electrolyte-gated transistors based on phenyl-C61-butyric acid methyl ester (PCBM) films: bridging redox properties, charge carrier transport and device performance.

Science.gov (United States)

Lan, Tian; Soavi, Francesca; Marcaccio, Massimo; Brunner, Pierre-Louis; Sayago, Jonathan; Santato, Clara

2018-05-24

The n-type organic semiconductor phenyl-C61-butyric acid methyl ester (PCBM), a soluble fullerene derivative well investigated for organic solar cells and transistors, can undergo several successive reversible, diffusion-controlled, one-electron reduction processes. We exploited such processes to shed light on the correlation between electron transfer properties, ionic and electronic transport as well as device performance in ionic liquid (IL)-gated transistors. Two ILs were considered, based on bis(trifluoromethylsulfonyl)imide [TFSI] as the anion and 1-ethyl-3-methylimidazolium [EMIM] or 1-butyl-1-methylpyrrolidinium [PYR14] as the cation. The aromatic structure of [EMIM] and its lower steric hindrance with respect to [PYR14] favor a 3D (bulk) electrochemical doping. As opposed to this, for [PYR14] the doping seems to be 2D (surface-confined). If the n-doping of the PCBM is pursued beyond the first electrochemical process, the transistor current vs. gate-source voltage plots in [PYR14][TFSI] feature a maximum that points to the presence of finite windows of high conductivity in IL-gated PCBM transistors.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

Science.gov (United States)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Experimental study on short-circuit characteristics of the new protection circuit of insulated gate bipolar transistor

International Nuclear Information System (INIS)

Ji, In-Hwan; Choi, Young-Hwan; Ha, Min-Woo; Han, Min-Koo; Choi, Yearn-Ik

2006-01-01

A new protection circuit employing the collector to emitter voltage (V CE ) sensing scheme for short-circuit withstanding capability of the insulated gate bipolar transistor (IGBT) is proposed and verified by experimental results. Because the current path between the gate and collector can be successfully eliminated in the proposed protection circuit, the power consumption can be reduced and the gate input impedance can be increased. Previous study is limited to dc characteristics. However, experimental results show that the proposed protection circuit successfully reduces the over-current of main IGBT by 80.4% under the short-circuit condition

Voltage-Controlled Floating Resistor Using DDCC

Directory of Open Access Journals (Sweden)

M. Kumngern

2011-04-01

Full Text Available This paper presents a new simple configuration to realize the voltage-controlled floating resistor, which is suitable for integrated circuit implementation. The proposed resistor is composed of three main components: MOS transistor operating in the non-saturation region, DDCC, and MOS voltage divider. The MOS transistor operating in the non-saturation region is used to configure a floating linear resistor. The DDCC and the MOS transistor voltage divider are used for canceling the nonlinear component term of MOS transistor in the non-saturation region to obtain a linear current/voltage relationship. The DDCC is employed to provide a simple summer of the circuit. This circuit offers an ease for realizing the voltage divider circuit and the temperature effect that includes in term of threshold voltage can be compensated. The proposed configuration employs only 16 MOS transistors. The performances of the proposed circuit are simulated with PSPICE to confirm the presented theory.

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

Science.gov (United States)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

Science.gov (United States)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

Science.gov (United States)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous InGaZnO thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Her, Jim-Long [Division of Natural Science, Center for General Education, Chang Gung University, Taoyuan 333, Taiwan (China); Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Liu, Jiang-Hung; Wang, Hong-Jun; Chen, Ching-Hung [Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan (China); Koyama, Keiichi [Graduate School of Science and Engineering, Kagoshima University, Kagoshima 890-0065 (Japan)

2014-10-31

In this article, we studied the structural properties and electrical characteristics of GdTiO{sub 3} gate dielectric for amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) applications. The a-IGZO TFT device featuring the GdTiO{sub 3} gate dielectric exhibited better electrical characteristics, including a small threshold voltage of 0.14 V, a large field-effect mobility of 32.3 cm{sup 2}/V-s, a high I{sub on}/I{sub off} current ratio of 4.2 × 10{sup 8}, and a low subthreshold swing of 213 mV/decade. Furthermore, the electrical instability of GdTiO{sub 3} a-IGZO TFTs was investigated under both positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS) conditions. The electron charge trapping in the gate dielectric dominates the PGBS degradation, while the oxygen vacancies control the NGBS degradation. - Highlights: • Indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) • Structural and electrical properties of the GdTiO{sub 3} film were studied. • a-IGZO TFT featuring GdTi{sub x}O{sub y} dielectric exhibited better electrical characteristics. • TFT instability investigated under positive and negative gate-bias stress conditions.

New AlGaN/GaN HEMTs employing both a floating gate and a field plate

International Nuclear Information System (INIS)

Lim, Jiyong; Choi, Young-Hwan; Kim, Young-Shil; Han, Min-Koo

2010-01-01

We designed and fabricated AlGaN/GaN high-electron-mobility transistors (HEMTs) employing both a floating gate (FG) and a field plate (FP), which increase the breakdown voltage of AlGaN/GaN HEMTs significantly without sacrificing forward electric characteristics. The electric field strength at the gate-drain region of the proposed AlGaN/GaN HEMT was reduced successfully due to an increase in the number of depletion region edges. The breakdown voltage of the proposed AlGaN/GaN HEMT was 1106 V, while those of the conventional devices with only an FP or FG were 688 and 828 V, respectively. The leakage current of the proposed AlGaN/GaN HEMTs was 1.68 μA under a reverse bias of -100 V while those of the conventional devices with only an FP or FG were 3.21 and 1.91 μA, respectively, under the same condition. The forward electric characteristics of the proposed and conventional AlGaN/GaN HEMTs are similar. The maximum drain current of the proposed AlGaN/GaN HEMTs was 344 mA mm -1 while those of the conventional devices with only an FP or FG were 350 and 357 mA mm -1 , respectively. The maximum transconductance of the proposed device was 102.9 mS mm -1 , while those of the conventional devices were 97.8 and 101.9 mS mm -1 . The breakdown voltage and the leakage current of the proposed device were improved considerably without sacrificing the forward electric characteristics. It should be noted that there were no additional processing steps and mask levels compared to the conventional FP process.

A 1T Dynamic Random Access Memory Cell Based on Gated Thyristor with Surrounding Gate Structure for High Scalability.

Science.gov (United States)

Kim, Hyungjin; Kim, Sihyun; Kim, Hyun-Min; Lee, Kitae; Kim, Sangwan; Pak, Byung-Gook

2018-09-01

In this study, we investigate a one-transistor (1T) dynamic random access memory (DRAM) cell based on a gated-thyristor device utilizing voltage-driven bistability to enable high-speed operations. The structural feature of the surrounding gate using a sidewall provides high scalability with regard to constructing an array architecture of the proposed devices. In addition, the operation mechanism, I-V characteristics, DRAM operations, and bias dependence are analyzed using a commercial device simulator. Unlike conventional 1T DRAM cells utilizing the floating body effect, excess carriers which are required to be stored to make two different states are not generated but injected from the n+ cathode region, giving the device high-speed operation capabilities. The findings here indicate that the proposed DRAM cell offers distinct advantages in terms of scalability and high-speed operations.

Triggering the Electrolyte-Gated Organic Field-Effect Transistor output characteristics through gate functionalization using diazonium chemistry: Application to biodetection of 2,4-dichlorophenoxyacetic acid.

Science.gov (United States)

Nguyen, T T K; Nguyen, T N; Anquetin, G; Reisberg, S; Noël, V; Mattana, G; Touzeau, J; Barbault, F; Pham, M C; Piro, B

2018-04-26

We investigated an Electrolyte-Gated Organic Field-Effect transistor based on poly(N-alkyldiketopyrrolo-pyrrole dithienylthieno[3,2-b]thiophene) as organic semiconductor whose gate electrode was functionalized by electrografting a functional diazonium salt capable to bind an antibody specific to 2,4-dichlorophenoxyacetic acid (2,4-D), an herbicide well-known to be a soil and water pollutant. Molecular docking computations were performed to design the functional diazonium salt to rationalize the antibody capture on the gate surface. Sensing of 2,4-D was performed through a displacement immunoassay. The limit of detection was estimated at around 2.5 fM. Copyright © 2018 Elsevier B.V. All rights reserved.

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

Science.gov (United States)

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

Science.gov (United States)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-08-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics ft/fmax of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with ft/fmax of 48/60 GHz.

Temperature-dependent gate-swing hysteresis of pentacene thin film transistors

Directory of Open Access Journals (Sweden)

Yow-Jon Lin

2014-10-01

Full Text Available The temperature-dependent hysteresis-type transfer characteristics of pentacene-based organic thin film transistors (OTFTs were researched. The temperature-dependent transfer characteristics exhibit hopping conduction behavior. The fitting data for the temperature-dependent off-to-on and on-to-off transfer characteristics of OTFTs demonstrate that the hopping distance (ah and the barrier height for hopping (qϕt control the carrier flow, resulting in the hysteresis-type transfer characteristics of OTFTs. The hopping model gives an explanation of the gate-swing hysteresis and the roles played by qϕt and ah.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.; Smith, Casey; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2011-01-01

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.

2011-10-12

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

2015-10-15

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

N-channel thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride with ultrathin polymer gate buffer layer

International Nuclear Information System (INIS)

Tanida, Shinji; Noda, Kei; Kawabata, Hiroshi; Matsushige, Kazumi

2009-01-01

N-channel operation of thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride (NTCDA) with a 9-nm-thick poly(methyl methacrylate) (PMMA) gate buffer layer was examined. The uniform coverage of the ultrathin PMMA layer on an SiO 2 gate insulator, verified by X-ray reflectivity measurement, caused the increase of electron field-effect mobility because of the suppression of electron traps existing on the SiO 2 surface. In addition, air stability for n-channel operation of the NTCDA transistor was also improved by the PMMA layer which possibly prevented the adsorption of ambient water molecules onto the SiO 2 surface.

Universal core model for multiple-gate field-effect transistors with short channel and quantum mechanical effects

Science.gov (United States)

Shin, Yong Hyeon; Bae, Min Soo; Park, Chuntaek; Park, Joung Won; Park, Hyunwoo; Lee, Yong Ju; Yun, Ilgu

2018-06-01

A universal core model for multiple-gate (MG) field-effect transistors (FETs) with short channel effects (SCEs) and quantum mechanical effects (QMEs) is proposed. By using a Young’s approximation based solution for one-dimensional Poisson’s equations the total inversion charge density (Q inv ) in the channel is modeled for double-gate (DG) and surrounding-gate SG (SG) FETs, following which a universal charge model is derived based on the similarity of the solutions, including for quadruple-gate (QG) FETs. For triple-gate (TG) FETs, the average of DG and QG FETs are used. A SCEs model is also proposed considering the potential difference between the channel’s surface and center. Finally, a QMEs model for MG FETs is developed using the quantum correction compact model. The proposed universal core model is validated on commercially available three-dimensional ATLAS numerical simulations.

Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

Directory of Open Access Journals (Sweden)

Yu-Hsien Lin

2014-01-01

Full Text Available This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using hafnium oxide (HfO2 gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO2 dielectric thin film during high-temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO2 gate dielectric TFT exhibiting high mobility, a high ION/IOFF ratio, low IOFF current, and excellent subthreshold swing (SS.

A self-amplified transistor immunosensor under dual gate operation: highly sensitive detection of hepatitis B surface antigen

Science.gov (United States)

Lee, I.-K.; Jeun, M.; Jang, H.-J.; Cho, W.-J.; Lee, K. H.

2015-10-01

Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor based on a self-amplified transistor under dual gate operation (immuno-DG ISFET) for the detection of hepatitis B surface antigen. To address the challenges in current ISFET-based immunosensors, we have enhanced the sensitivity of an immunosensor by precisely tailoring the nanostructure of the transistor. In the pH sensing test, the immuno-DG ISFET showed superior sensitivity (2085.53 mV per pH) to both standard ISFET under single gate operation (58.88 mV per pH) and DG ISFET with a non-tailored transistor (381.14 mV per pH). Moreover, concerning the detection of hepatitis B surface antigens (HBsAg) using the immuno-DG ISFET, we have successfully detected trace amounts of HBsAg (22.5 fg mL-1) in a non-diluted 1× PBS medium with a high sensitivity of 690 mV. Our results demonstrate that the proposed immuno-DG ISFET can be a biosensor platform for practical use in the diagnosis of various diseases.Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

Science.gov (United States)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

Chemo-Electrical Signal Transduction by Using Stimuli-Responsive Polymer Gate-Modified Field Effect Transistor

Directory of Open Access Journals (Sweden)

Akira Matsumoto

2014-03-01

Full Text Available A glucose-responsive polymer brush was designed on a gold electrode and exploited as an extended gate for a field effect transistor (FET based biosensor. A permittivity change at the gate interface due to the change in hydration upon specific binding with glucose was detectable. The rate of response was markedly enhanced compared to the previously studied cross-linked or gel-coupled electrode, owing to its kinetics involving no process of the polymer network diffusion. This finding may offer a new strategy of the FET-based biosensors effective not only for large molecules but also for electrically neutral molecules such as glucose with improved kinetics.

An Adaptable Neuromorphic Model of Orientation Selectivity Based On Floating Gate Dynamics

Directory of Open Access Journals (Sweden)

Priti eGupta

2014-04-01

Full Text Available The biggest challenge that the neuromorphic community faces today is to build systems that can be considered truly cognitive. Adaptation and self-organization are the two basic principles that underlie any cognitive function that the brain performs. If we can replicate this behavior in hardware, we move a step closer to our goal of having cognitive neuromorphic systems. Adaptive feature selectivity is a mechanism by which nature optimizes resources so as to have greater acuity for more abundant features. Developing neuromorphic feature maps can help design generic machines that can emulate this adaptive behavior. Most neuromorphic models that have attempted to build self-organizing systems, follow the approach of modeling abstract theoretical frameworks in hardware. While this is good from a modeling and analysis perspective, it may not lead to the most efficient hardware. On the other hand, exploiting hardware dynamics to build adaptive systems rather than forcing the hardware to behave like mathematical equations, seems to be a more robust methodology when it comes to developing actual hardware for real world applications. In this paper we use a novel time-staggered Winner Take All circuit, that exploits the adaptation dynamics of floating gate transistors, to model an adaptive cortical cell that demonstrates Orientation Selectivity, a well-known biological phenomenon observed in the visual cortex. The cell performs competitive learning, refining its weights in response to input patterns resembling different oriented bars, becoming selective to a particular oriented pattern. Different analysis performed on the cell such as orientation tuning, application of abnormal inputs, response to spatial frequency and periodic patterns reveal close similarity between our cell and its biological counterpart. Embedded in a RC grid, these cells interact diffusively exhibiting cluster formation, making way for adaptively building orientation selective maps

Proposal for a dual-gate spin field effect transistor: A device with very small switching voltage and a large ON to OFF conductance ratio

Science.gov (United States)

Wan, J.; Cahay, M.; Bandyopadhyay, S.

2008-06-01

We propose a new dual gate spin field effect transistor (SpinFET) consisting of a quasi one-dimensional semiconductor channel sandwiched between two half-metallic contacts. The gate voltage aligns and de-aligns the incident electron energy with Ramsauer resonance levels in the channel, thereby modulating the source-to-drain conductance. The device can be switched from ON to OFF with a few mV change in the gate voltage, resulting in exceedingly low dynamic power dissipation during switching. The conductance ON/OFF ratio stays fairly large ( ∼60) up to a temperature of 10 K. This conductance ratio is comparable to that achievable with carbon nanotube transistors.

MIS field effect transistor with barium titanate thin film as a gate insulator

Energy Technology Data Exchange (ETDEWEB)

Firek, P., E-mail: pfirek@elka.pw.edu.p [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Werbowy, A.; Szmidt, J. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland)

2009-11-25

The properties of barium titanate (BaTiO{sub 3}, BT) like, e.g. high dielectric constant and resistivity, allow it to find numerous applications in field of microelectronics. In this work silicon metal insulator semiconductor field effect transistor (MISFET) structures with BaTiO{sub 3} (containing La{sub 2}O{sub 3} admixture) thin films in a role of gate insulator were investigated. The films were produced by means of radio frequency plasma sputtering (RF PS) of sintered BaTiO{sub 3} + La{sub 2}O{sub 3} (2 wt.%) target. In the paper transfer and output current-voltage (I-V), transconductance and output conductance characteristics of obtained transistors are presented and discussed. Basic parameters of these devices like, e.g. threshold voltage (V{sub TH}), are determined and discussed.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

International Nuclear Information System (INIS)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-01-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics f_t/f_m_a_x of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f_t/f_m_a_x of 48/60 GHz.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

Energy Technology Data Exchange (ETDEWEB)

Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J. [Naval Research Laboratory, Electronics Science and Technology Division, Washington, DC 20375 (United States)

2016-08-08

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics f{sub t}/f{sub max} of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f{sub t}/f{sub max} of 48/60 GHz.

Detailed simulation study of a dual material gate carbon nanotube field-effect transistor

Science.gov (United States)

Orouji, Ali A.; Arefinia, Zahra

2009-02-01

For the first time, a new type of carbon nanotube field-effect transistor (CNTFET), the dual material gate (DMG)-CNTFET, is proposed and simulated using quantum simulation that is based on self-consistent solution between two-dimensional Poisson equation and Schrödinger equation with open boundary conditions, within the nonequilibrium Green's function (NEGF) framework. The proposed structure is similar to that of the conventional coaxial CNTFET with the exception that the gate of the DMG-CNTFET consists of two laterally contacting metals with different work functions. Simulation results show DMG-CNTFET significantly decreases leakage current, drain conductance and subthreshold swing, and increases on-off current ratio and voltage gain as compared to conventional CNTFET. We demonstrate that the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

OpenAIRE

Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

Microscopic gate-modulation imaging of charge and field distribution in polycrystalline organic transistors

Science.gov (United States)

Matsuoka, Satoshi; Tsutsumi, Jun'ya; Kamata, Toshihide; Hasegawa, Tatsuo

2018-04-01

In this work, a high-resolution microscopic gate-modulation imaging (μ-GMI) technique is successfully developed to visualize inhomogeneous charge and electric field distributions in operating organic thin-film transistors (TFTs). We conduct highly sensitive and diffraction-limit gate-modulation sensing for acquiring difference images of semiconducting channels between at gate-on and gate-off states that are biased at an alternate frequency of 15 Hz. As a result, we observe unexpectedly inhomogeneous distribution of positive and negative local gate-modulation (GM) signals at a probe photon energy of 1.85 eV in polycrystalline pentacene TFTs. Spectroscopic analyses based on a series of μ-GMI at various photon energies reveal that two distinct effects appear, simultaneously, within the polycrystalline pentacene channel layers: Negative GM signals at 1.85 eV originate from the second-derivative-like GM spectrum which is caused by the effect of charge accumulation, whereas positive GM signals originate from the first-derivative-like GM spectrum caused by the effect of leaked gate fields. Comparisons with polycrystalline morphologies indicate that grain centers are predominated by areas with high leaked gate fields due to the low charge density, whereas grain edges are predominantly high-charge-density areas with a certain spatial extension as associated with the concentrated carrier traps. Consequently, it is reasonably understood that larger grains lead to higher device mobility, but with greater inhomogeneity in charge distribution. These findings provide a clue to understand and improve device characteristics of polycrystalline TFTs.

The GaN trench gate MOSFET with floating islands: High breakdown voltage and improved BFOM

Science.gov (United States)

Shen, Lingyan; Müller, Stephan; Cheng, Xinhong; Zhang, Dongliang; Zheng, Li; Xu, Dawei; Yu, Yuehui; Meissner, Elke; Erlbacher, Tobias

2018-02-01

A novel GaN trench gate (TG) MOSFET with P-type floating islands (FLI) in drift region, which can suppress the electric field peak at bottom of gate trench during the blocking state and prevent premature breakdown in gate oxide, is proposed and investigated by TCAD simulations. The influence of thickness, position, doping concentration and length of the FLI on breakdown voltage (BV) and specific on-resistance (Ron_sp) is studied, providing useful guidelines for design of this new type of device. Using optimized parameters for the FLI, GaN FLI TG-MOSFET obtains a BV as high as 2464 V with a Ron_sp of 3.0 mΩ cm2. Compared to the conventional GaN TG-MOSFET with the same structure parameters, the Baliga figure of merit (BFOM) is enhanced by 150%, getting closer to theoretical limit for GaN devices.

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

Energy Technology Data Exchange (ETDEWEB)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

Gold nanoparticle-pentacene memory-transistors

OpenAIRE

Novembre , Christophe; Guerin , David; Lmimouni , Kamal; Gamrat , Christian; Vuillaume , Dominique

2008-01-01

We demonstrate an organic memory-transistor device based on a pentacene-gold nanoparticles active layer. Gold (Au) nanoparticles are immobilized on the gate dielectric (silicon dioxide) of a pentacene transistor by an amino-terminated self-assembled monolayer. Under the application of writing and erasing pulses on the gate, large threshold voltage shift (22 V) and on/off drain current ratio of ~3E4 are obtained. The hole field-effect mobility of the transistor is similar in the on and off sta...

The Complete Semiconductor Transistor and Its Incomplete Forms

International Nuclear Information System (INIS)

Jie Binbin; Sah, C.-T.

2009-01-01

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor, BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.

Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module

Science.gov (United States)

2015-02-01

executed with SolidWorks Flow Simulation , a computational fluid-dynamics code. The graph in Fig. 2 shows the timing and amplitudes of power pulses...defined a convective flow of air perpendicular to the bottom surface of the mounting plate, with a velocity of 10 ft/s. The thermal simulations were...Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module by Gregory K Ovrebo ARL-TR-7210

Temperature dependence of the current in Schottky-barrier source-gated transistors

Science.gov (United States)

Sporea, R. A.; Overy, M.; Shannon, J. M.; Silva, S. R. P.

2015-05-01

The temperature dependence of the drain current is an important parameter in thin-film transistors. In this paper, we propose that in source-gated transistors (SGTs), this temperature dependence can be controlled and tuned by varying the length of the source electrode. SGTs comprise a reverse biased potential barrier at the source which controls the current. As a result, a large activation energy for the drain current may be present which, although useful in specific temperature sensing applications, is in general deleterious in many circuit functions. With support from numerical simulations with Silvaco Atlas, we describe how increasing the length of the source electrode can be used to reduce the activation energy of SGT drain current, while maintaining the defining characteristics of SGTs: low saturation voltage, high output impedance in saturation, and tolerance to geometry variations. In this study, we apply the dual current injection modes to obtain drain currents with high and low activation energies and propose mechanisms for their exploitation in future large-area integrated circuit designs.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

International Nuclear Information System (INIS)

Jiang Zhi; Zhuang Yi-Qi; Li Cong; Wang Ping; Liu Yu-Qi

2016-01-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (D it ) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. (paper)

Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO2 nanogranular films

International Nuclear Information System (INIS)

Zhu, Li Qiang; Chao, Jin Yu; Xiao, Hui

2014-01-01

Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO 2 nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics

Al2O3 nanocrystals embedded in amorphous Lu2O3 high-k gate dielectric for floating gate memory application

International Nuclear Information System (INIS)

Yuan, C L; Chan, M Y; Lee, P S; Darmawan, P; Setiawan, Y

2007-01-01

The integration of nanoparticles has high potential in technological applications and opens up possibilities of the development of new devices. Compared to the conventional floating gate memory, a structure containing nanocrystals embedded in dielectrics shows high potential to produce a memory with high endurance, low operating voltage, fast write-erase speeds and better immunity to soft errors [S. Tiwari, F. Rana, H. Hanafi et al. 1996 Appl.Phys. Lett. 68, 1377]. A significant improvement on data retention [J. J. Lee, X. Wang et al. 2003 Proceedings of the VLSI Technol. Symposium, p33] can be observed when discrete nanodots are used instead of continuous floating gate as charge storage nodes because local defect related leakage can be reduced efficiently. Furthermore, using a high-k dielectric in place of the conventional SiO2 based dielectric, nanodots flash memory is able to achieve significantly improved programming efficiency and data retention [A. Thean and J. -P. Leburton, 2002 IEEE Potentials 21, 35; D. W. Kim, T. Kim and S. K. Banerjee, 2003 IEEE Trans. Electron Devices 50, 1823]. We have recently successfully developed a method to produce nanodots embedded in high-k gate dielectrics [C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Electrochemical and Solid-State Letters 9, F53; C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Europhys. Lett. 74, 177]. In this paper, we fabricated the memory structure of Al 2 O 3 nanocrystals embedded in amorphous Lu 2 O 3 high k dielectric using pulsed laser ablation. The mean size and density of the Al 2 O 3 nanocrystals are estimated to be about 5 nm and 7x1011 cm -2 , respectively. Good electrical performances in terms of large memory window and good data retention were observed. Our preparation method is simple, fast and economical

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

Science.gov (United States)

Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

2017-04-01

A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

CERN Document Server

Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

2010-01-01

We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

Directory of Open Access Journals (Sweden)

P. T. Tue

2013-01-01

Full Text Available We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT which uses solution-processed indium-tin-oxide (ITO and lead-zirconium-titanate (PZT film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1 a reduction of the charge injection and (2 an increase of effective coercive voltage dropped on the insulator.

A III-V nanowire channel on silicon for high-performance vertical transistors.

Science.gov (United States)

Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

2012-08-09

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

An Asynchronous IEEE Floating-Point Arithmetic Unit

Directory of Open Access Journals (Sweden)

Joel R. Noche

2007-12-01

Full Text Available An asynchronous floating-point arithmetic unit is designed and tested at the transistor level usingCadence software. It uses CMOS (complementary metal oxide semiconductor and DCVS (differentialcascode voltage switch logic in a 0.35 µm process using a 3.3 V supply voltage, with dual-rail data andsingle-rail control signals using four-phase handshaking.Using 17,085 transistors, the unit handles single-precision (32-bit addition/subtraction, multiplication,division, and remainder using the IEEE 754-1985 Standard for Binary Floating-Point Arithmetic, withrounding and other operations to be handled by separate hardware or software. Division and remainderare done using a restoring subtractive algorithm; multiplication uses an additive algorithm. Exceptionsare noted by flags (and not trap handlers and the output is in single-precision.Previous work on asynchronous floating-point arithmetic units have mostly focused on single operationssuch as division. This is the first work to the authors' knowledge that can perform floating-point addition,multiplication, division, and remainder using a common datapath.

Pulsed laser deposition of oxide gate dielectrics for pentacene organic field-effect transistors

International Nuclear Information System (INIS)

Yaginuma, S.; Yamaguchi, J.; Itaka, K.; Koinuma, H.

2005-01-01

We have fabricated Al 2 O 3 , LaAlO 3 (LAO), CaHfO 3 (CHO) and CaZrO 3 (CZO) thin films for the dielectric layers of field-effect transistors (FETs) by pulsed laser deposition (PLD). The films exhibited very smooth surfaces with root-mean-squares (rms) roughnesses of ∼1.3 A as evaluated by using atomic force microscopy (AFM). The breakdown electric fields of Al 2 O 3 , LAO, CHO and CZO films were 7, 6, 10 and 2 MV/cm, respectively. The magnitude of the leak current in each film was low enough to operate FET. We performed a comparative study of pentacene FET fabricated using these oxide dielectrics as gate insulators. High field-effect mobility of 1.4 cm 2 /V s and on/off current ratio of 10 7 were obtained in the pentacene FET using LAO gate insulating film. Use of the LAO films as gate dielectrics has been found to suppress the hysteresis of pentacene FET operations. The LAO films are relevant to the dielectric layer of organic FETs

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

Science.gov (United States)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

Implementation of floating gate MOSFET in inverter for threshold voltage tunability

Directory of Open Access Journals (Sweden)

Musa F.A.S.

2017-01-01

Full Text Available This paper presents the ability of floating gate MOSFET (FGMOS threshold voltage to be programmed or tuned which is exploited to improve the performance of electronic circuit design. This special characteristic owns by FGMOS is definitely contributes towards low voltage and low power circuit design. The comparison of threshold voltage between FGMOS and conventional NMOS is done in order to prove that FGMOS is able to produce a lower threshold voltage compared to conventional NMOS. In addition, in this paper, an implementation of FGMOS into inverter circuit is also done to show the programmability of FGMOS threshold voltage. The operations of the inverter circuits are verified using Sypnopsys simulation in 0.1μm CMOS technology with supply voltage of 1.8V.

Design method for a digitally trimmable MOS transistor structure

DEFF Research Database (Denmark)

Ning, Feng; Bruun, Erik

1996-01-01

A digitally trimmable MOS transistor is a MOS transistor consisting of a drain, a source, and a main gate as well as several subgates. The transconductance of the transistor is tunabledigitally by means of connecting subgates either to the main gate or to the source terminal. In this paper, a sys...

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

Science.gov (United States)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

International Nuclear Information System (INIS)

Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

2014-01-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

Dual-gate photo thin-film transistor: a “smart” pixel for high- resolution and low-dose X-ray imaging

Science.gov (United States)

Wang, Kai; Ou, Hai; Chen, Jun

2015-06-01

Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The "smart" pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients.

Dual-gate photo thin-film transistor: a “smart” pixel for high- resolution and low-dose X-ray imaging

International Nuclear Information System (INIS)

Wang, Kai; Ou, Hai; Chen, Jun

2015-01-01

Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The 'smart' pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients. (paper)

Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

International Nuclear Information System (INIS)

Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon; Choi, Woon-Seop

2010-01-01

Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility (μ) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of μ and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on μ, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

Flexible suspended gate organic thin-film transistors for ultra-sensitive pressure detection

Science.gov (United States)

Zang, Yaping; Zhang, Fengjiao; Huang, Dazhen; Gao, Xike; di, Chong-An; Zhu, Daoben

2015-03-01

The utilization of organic devices as pressure-sensing elements in artificial intelligence and healthcare applications represents a fascinating opportunity for the next-generation electronic products. To satisfy the critical requirements of these promising applications, the low-cost construction of large-area ultra-sensitive organic pressure devices with outstanding flexibility is highly desired. Here we present flexible suspended gate organic thin-film transistors (SGOTFTs) as a model platform that enables ultra-sensitive pressure detection. More importantly, the unique device geometry of SGOTFTs allows the fine-tuning of their sensitivity by the suspended gate. An unprecedented sensitivity of 192 kPa-1, a low limit-of-detection pressure of <0.5 Pa and a short response time of 10 ms were successfully realized, allowing the real-time detection of acoustic waves. These excellent sensing properties of SGOTFTs, together with their advantages of facile large-area fabrication and versatility in detecting various pressure signals, make SGOTFTs a powerful strategy for spatial pressure mapping in practical applications.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

Science.gov (United States)

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

Science.gov (United States)

Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

2014-12-24

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO{sub 2} nanogranular films

Energy Technology Data Exchange (ETDEWEB)

Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn; Chao, Jin Yu; Xiao, Hui [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China)

2014-12-15

Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO{sub 2} nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

Science.gov (United States)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa; Fahad, Hossain M.; Smith, Casey E.; Rojas, Jhonathan Prieto

2015-01-01

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa

2015-12-29

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

Science.gov (United States)

Zhi, Jiang; Yi-Qi, Zhuang; Cong, Li; Ping, Wang; Yu-Qi, Liu

2016-02-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

A Label-Free Immunosensor for IgG Based on an Extended-Gate Type Organic Field Effect Transistor

Directory of Open Access Journals (Sweden)

Tsukuru Minamiki

2014-09-01

Full Text Available A novel biosensor for immunoglobulin G (IgG detection based on an extended-gate type organic field effect transistor (OFET has been developed that possesses an anti-IgG antibody on its extended-gate electrode and can be operated below 3 V. The titration results from the target IgG in the presence of a bovine serum albumin interferent, clearly exhibiting a negative shift in the OFET transfer curve with increasing IgG concentration. This is presumed to be due an interaction between target IgG and the immobilized anti-IgG antibody on the extended-gate electrode. As a result, a linear range from 0 to 10 µg/mL was achieved with a relatively low detection limit of 0.62 µg/mL (=4 nM. We believe that these results open up opportunities for applying extended-gate-type OFETs to immunosensing.

Raman imaging of carrier distribution in the channel of an ionic liquid-gated transistor fabricated with regioregular poly(3-hexylthiophene)

Science.gov (United States)

Wada, Y.; Enokida, I.; Yamamoto, J.; Furukawa, Y.

2018-05-01

Raman images of carriers (positive polarons) at the channel of an ionic liquid-gated transistor (ILGT) fabricated with regioregular poly(3-hexylthiophene) (P3HT) have been measured with excitation at 785 nm. The observed spectra indicate that carriers generated are positive polarons. The intensities of the 1415 cm-1 band attributed to polarons in the P3HT channel were plotted as Raman images; they showed the carrier density distribution. When the source-drain voltage VD is lower than the source-gate voltage VG (linear region), the carrier density was uniform. When VD is nearly equal to VG (saturation region), a negative carrier density gradient from the source electrode towards the drain electrode was observed. This carrier density distribution is associated with the observed current-voltage characteristics, which is not consistent with the "pinch-off" theory of inorganic semiconductor transistors.

Study of an Insulated Gate Bipolar Transistor (IGBT) and its connection in series. Application at a chopper 1500V-5A-10kHz

International Nuclear Information System (INIS)

Gros, P.

1993-01-01

In the frame of the tokamak ITER (International Thermonuclear Experimental Reactor) we have studied, for neutral particle injection, a converter with at least two static interrupters by Mosfet transistor, bipolar transistor or Insulated Gate Bipolar Transistor (IGBT). After a comparison between these three types of transistors, by the simulating software MICROCAP, a serial of tests has shown the advantages of the IGBT. A command, associated with two IGBT of equivalent characteristics, has given a simple and efficacious solution. The performances are: (1) between two blockages: 50 ns without overvoltage, (2) between two cut-off: 60 ns. 40 figs; 30 refs; 10 annexes

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

Directory of Open Access Journals (Sweden)

Ning Cui

2012-06-01

Full Text Available Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs. In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

Science.gov (United States)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method

International Nuclear Information System (INIS)

Kobayashi, H.; Kim, W. B.; Matsumoto, T.

2011-01-01

We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)

CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

International Nuclear Information System (INIS)

Ginet, Patrick; Akiyama, Sho; Takama, Nobuyuki; Fujita, Hiroyuki; Kim, Beomjoon

2011-01-01

Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL −1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors

Comparison of recessed gate-head structures on normally-off AlGaN/GaN high-electron-mobility transistor performance.

Science.gov (United States)

Khan, Mansoor Ali; Heo, Jun-Woo; Kim, Hyun-Seok; Park, Hyun-Chang

2014-11-01

In this work, different gate-head structures have been compared in the context of AlGaN/GaN-based high-electron-mobility transistors (HEMTs). Field-plate (FP) technology self-aligned to the gate electrode leads to various gate-head structures, most likely gamma (γF)-gate, camel (see symbol)-gate, and mushroom-shaped (T)-gate. In-depth comparison of recessed gate-head structures demonstrated that key performance metrics such as transconductance, output current, and breakdown voltage are better with the T-gate head structure. The recessed T-gate with its one arm toward the source side not only reduces the source-access resistance (R(g) +R(gs)), but also minimizes the source-side dispersion and current leakage, resulting in high transconductance (G(m)) and output current (I(DS)). At the same time, the other arm toward the drain-side reduces the drain-side dispersion and tends to distribute electric field peaks uniformly, resulting in high breakdown voltage (V(BR)). DC and RF analysis showed that the recessed T-gate FP-HEMT is a suitable candidate not only for high-frequency operation, but also for high-power applications.

Using white noise to gate organic transistors for dynamic monitoring of cultured cell layers.

Science.gov (United States)

Rivnay, Jonathan; Leleux, Pierre; Hama, Adel; Ramuz, Marc; Huerta, Miriam; Malliaras, George G; Owens, Roisin M

2015-06-26

Impedance sensing of biological systems allows for monitoring of cell and tissue properties, including cell-substrate attachment, layer confluence, and the "tightness" of an epithelial tissue. These properties are critical for electrical detection of tissue health and viability in applications such as toxicological screening. Organic transistors based on conducting polymers offer a promising route to efficiently transduce ionic currents to attain high quality impedance spectra, but collection of complete impedance spectra can be time consuming (minutes). By applying uniform white noise at the gate of an organic electrochemical transistor (OECT), and measuring the resulting current noise, we are able to dynamically monitor the impedance and thus integrity of cultured epithelial monolayers. We show that noise sourcing can be used to track rapid monolayer disruption due to compounds which interfere with dynamic polymerization events crucial for maintaining cytoskeletal integrity, and to resolve sub-second alterations to the monolayer integrity.

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

Directory of Open Access Journals (Sweden)

Yu-Hsien Lin

2015-01-01

Full Text Available We investigated amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using different high-k gate dielectric materials such as silicon nitride (Si3N4 and aluminum oxide (Al2O3 at low temperature process (<300°C and compared them with low temperature silicon dioxide (SiO2. The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

International Nuclear Information System (INIS)

Lin, Y. H.; Chou, J. C.

2015-01-01

We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT_s) using different high-Κ gate dielectric materials such as silicon nitride (Si_3N_4) and aluminum oxide (Al_2O_3) at low temperature process (<300 degree) and compared them with low temperature silicon dioxide (SiO_2). The IGZO device with high-Κ gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, post annealing treatment is an essential process for completing the process. The chemical reaction of the high-κ/IGZO interface due to heat formation in high-Κ/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-Κ gate dielectric materials and explained the interface effect by charge band diagram.

High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

Directory of Open Access Journals (Sweden)

Murali Gedda

2013-11-01

Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

Energy Technology Data Exchange (ETDEWEB)

Hong, Sung Ju; Park, Min; Kang, Hojin; Park, Yung Woo, E-mail: ywpark@snu.ac.kr [Department of Physics and Astronomy, Seoul National University, Seoul 151-747 (Korea, Republic of); Lee, Minwoo; Jeong, Dae Hong [Department of Chemistry Education, Seoul National University, Seoul 151-742 (Korea, Republic of)

2016-08-15

We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibility in transition metal dichalcogenide (TMD)-based electronics.

Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application

Science.gov (United States)

Navlakha, Nupur; Kranti, Abhinav

2017-07-01

Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1 = SM × RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2 = SM × CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM.

Self-Heating Effects In Polysilicon Source Gated Transistors

Science.gov (United States)

Sporea, R. A.; Burridge, T.; Silva, S. R. P.

2015-01-01

Source-gated transistors (SGTs) are thin-film devices which rely on a potential barrier at the source to achieve high gain, tolerance to fabrication variability, and low series voltage drop, relevant to a multitude of energy-efficient, large-area, cost effective applications. The current through the reverse-biased source barrier has a potentially high positive temperature coefficient, which may lead to undesirable thermal runaway effects and even device failure through self-heating. Using numerical simulations we show that, even in highly thermally-confined scenarios and at high current levels, self-heating is insufficient to compromise device integrity. Performance is minimally affected through a modest increase in output conductance, which may limit the maximum attainable gain. Measurements on polysilicon devices confirm the simulated results, with even smaller penalties in performance, largely due to improved heat dissipation through metal contacts. We conclude that SGTs can be reliably used for high gain, power efficient analog and digital circuits without significant performance impact due to self-heating. This further demonstrates the robustness of SGTs. PMID:26351099

Comprehensive study of gate-terminated and source-terminated field-plate 0.13 µm NMOS transistors

International Nuclear Information System (INIS)

Chiu, Hsien-Chin; Lin, Shao-Wei; Cheng, Chia-Shih; Wei, Chien-Cheng

2008-01-01

This study systematically investigated microwave noise, power and linearity characteristics of field-plate (FP) 0.13 µm CMOS transistors in which the field-plate metal is connected to the gate terminal and the source terminal. The gate-terminated FP NMOS (FP-G NMOS) provided the best noise figure (NF) at 6 GHz compared with standard devices and the source-terminated FP device (FP-S NMOS) as the lowest gate resistance (R g ) was obtained by this structure. By adopting the field-plate metal in NMOS, both FP-S and FP-G devices achieved higher current density at high gate bias voltages. Moreover, these two devices also had higher efficiency under high drain-to-source voltages at the high input power swing. The third-order inter-modulation product (IM3) is −39.4 dBm for FP-S NMOS at P in of −20 dBm; the corresponding values for FP-G and standard devices are −34.9 dBm and −37.3 dBm, respectively. Experimental results indicate that the FP-G architecture is suitable for low noise applications and FP-S is suitable for high power and high linearity operation

A spiking neuron circuit based on a carbon nanotube transistor

International Nuclear Information System (INIS)

Chen, C-L; Kim, K; Truong, Q; Shen, A; Li, Z; Chen, Y

2012-01-01

A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a ‘soma’ circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions. (paper)

High performance tunnel field-effect transistor by gate and source engineering.

Science.gov (United States)

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-12-19

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

Science.gov (United States)

Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

2016-01-26

Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

Proton migration mechanism for the instability of organic field-effect transistors

NARCIS (Netherlands)

Sharma, A.; Mathijssen, S.G.J.; Kemerink, M.; Leeuw, de D.M.; Bobbert, P.A.

2009-01-01

During prolonged application of a gate bias, organic field-effect transistors show an instability involving a gradual shift of the threshold voltage toward the applied gate bias voltage. We propose a model for this instability in p-type transistors with a silicon-dioxide gate dielectric, based on

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

Science.gov (United States)

Zhang, Xian-Jun; Yang, Yin-Tang; Duan, Bao-Xing; Chai, Chang-Chun; Song, Kun; Chen, Bin

2012-09-01

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET).

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

International Nuclear Information System (INIS)

Zhang Xian-Jun; Yang Yin-Tang; Duan Bao-Xing; Chai Chang-Chun; Song Kun; Chen Bin

2012-01-01

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET)

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

Science.gov (United States)

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Solution-gated graphene transistors for chemical and biological sensors.

Science.gov (United States)

Yan, Feng; Zhang, Meng; Li, Jinhua

2014-03-01

Graphene has attracted much attention in biomedical applications for its fascinating properties. Because of the well-known 2D structure, every atom of graphene is exposed to the environment, so the electronic properties of graphene are very sensitive to charged analytes (ions, DNA, cells, etc.) or an electric field around it, which renders graphene an ideal material for high-performance sensors. Solution-gated graphene transistors (SGGTs) can operate in electrolytes and are thus excellent candidates for chemical and biological sensors, which have been extensively studied in the recent 5 years. Here, the device physics, the sensing mechanisms, and the performance of the recently developed SGGT-based chemical and biological sensors, including pH, ion, cell, bacterial, DNA, protein, glucose sensors, etc., are introduced. Their advantages and shortcomings, in comparison with some conventional techniques, are discussed. Conclusions and challenges for the future development of the field are addressed in the end. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey; Qaisi, Ramy M.; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-01-01

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

Science.gov (United States)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Nanosecond Time-Resolved Microscopic Gate-Modulation Imaging of Polycrystalline Organic Thin-Film Transistors

Science.gov (United States)

Matsuoka, Satoshi; Tsutsumi, Jun'ya; Matsui, Hiroyuki; Kamata, Toshihide; Hasegawa, Tatsuo

2018-02-01

We develop a time-resolved microscopic gate-modulation (μ GM ) imaging technique to investigate the temporal evolution of the channel current and accumulated charges in polycrystalline pentacene thin-film transistors (TFTs). A time resolution of as high as 50 ns is achieved by using a fast image-intensifier system that could amplify a series of instantaneous optical microscopic images acquired at various time intervals after the stepped gate bias is switched on. The differential images obtained by subtracting the gate-off image allows us to acquire a series of temporal μ GM images that clearly show the gradual propagation of both channel charges and leaked gate fields within the polycrystalline channel layers. The frontal positions for the propagations of both channel charges and leaked gate fields coincide at all the time intervals, demonstrating that the layered gate dielectric capacitors are successively transversely charged up along the direction of current propagation. The initial μ GM images also indicate that the electric field effect is originally concentrated around a limited area with a width of a few micrometers bordering the channel-electrode interface, and that the field intensity reaches a maximum after 200 ns and then decays. The time required for charge propagation over the whole channel region with a length of 100 μ m is estimated at about 900 ns, which is consistent with the measured field-effect mobility and the temporal-response model for organic TFTs. The effect of grain boundaries can be also visualized by comparison of the μ GM images for the transient and the steady states, which confirms that the potential barriers at the grain boundaries cause the transient shift in the accumulated charges or the transient accumulation of additional charges around the grain boundaries.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

Science.gov (United States)

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Edge-on gating effect in molecular wires.

Science.gov (United States)

Lo, Wai-Yip; Bi, Wuguo; Li, Lianwei; Jung, In Hwan; Yu, Luping

2015-02-11

This work demonstrates edge-on chemical gating effect in molecular wires utilizing the pyridinoparacyclophane (PC) moiety as the gate. Different substituents with varied electronic demands are attached to the gate to simulate the effect of varying gating voltages similar to that in field-effect transistor (FET). It was observed that the orbital energy level and charge carrier's tunneling barriers can be tuned by changing the gating group from strong electron acceptors to strong electron donors. The single molecule conductance and current-voltage characteristics of this molecular system are truly similar to those expected for an actual single molecular transistor.

The floating-gate non-volatile semiconductor memory--from invention to the digital age.

Science.gov (United States)

Sze, S M

2012-10-01

In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

Influence of the gate position on source-to-drain resistance in AlGaN/AlN/GaN heterostructure field-effect transistors

Directory of Open Access Journals (Sweden)

Yan Liu

2017-08-01

Full Text Available Using a suitable dual-gate structure, the source-to-drain resistance (RSD of AlGaN/AlN/GaN heterostructure field-effect transistor (HFET with varying gate position has been studied at room temperature. The theoretical and experimental results have revealed a dependence of RSD on the gate position. The variation of RSD with the gate position is found to stem from the polarization Coulomb field (PCF scattering. This finding is of great benefit to the optimization of the performance of AlGaN/AlN/GaN HFET. Especially, when the AlGaN/AlN/GaN HFET works as a microwave device, it is beneficial to achieve the impedance matching by designing the appropriate gate position based on PCF scattering.

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

Science.gov (United States)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

Science.gov (United States)

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

Science.gov (United States)

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

Directory of Open Access Journals (Sweden)

Minkyu Chun

2015-05-01

Full Text Available We investigated the effects of top gate voltage (VTG and temperature (in the range of 25 to 70 oC on dual-gate (DG back-channel-etched (BCE amorphous-indium-gallium-zinc-oxide (a-IGZO thin film transistors (TFTs characteristics. The increment of VTG from -20V to +20V, decreases the threshold voltage (VTH from 19.6V to 3.8V and increases the electron density to 8.8 x 1018cm−3. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on VTG. At VTG of 20V, the mobility decreases from 19.1 to 15.4 cm2/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at VTG of - 20V, the mobility increases from 6.4 to 7.5cm2/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

Logarithmic current-measuring transistor circuits

DEFF Research Database (Denmark)

Højberg, Kristian Søe

1967-01-01

Describes two transistorized circuits for the logarithmic measurement of small currents suitable for nuclear reactor instrumentation. The logarithmic element is applied in the feedback path of an amplifier, and only one dual transistor is used as logarithmic diode and temperature compensating...... transistor. A simple one-amplifier circuit is compared with a two-amplifier system. The circuits presented have been developed in connexion with an amplifier using a dual m.o.s. transistor input stage with diode-protected gates....

Enhancement of the saturation mobility in a ferroelectric-gated field-effect transistor by the surface planarization of ferroelectric film

Energy Technology Data Exchange (ETDEWEB)

Kim, Woo Young, E-mail: semigumi@kaist.ac.kr [Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of); Jeon, Gwang-Jae; Kang, In-Ku; Shim, Hyun Bin; Lee, Hee Chul [Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)

2015-09-30

Ferroelectricity refers to the property of a dielectric material to undergo spontaneous polarization which originates from the crystalline phase. Hence, ferroelectric materials have a certain degree of surface roughness when they are formed as a thin film. A high degree of surface roughness may cause unintended phenomena when the ferroelectric material is used in electronic devices. Specifically, the quality of subsequently deposited film could be affected by the rough surface. The present study reports that the surface roughness of ferroelectric polymer film can be reduced by a double-spin-coating method of a solution, with control of the solubility of the solution. At an identical thickness of 350 nm, double-spin-coated ferroelectric film has a root-mean-square roughness of only 3 nm, while for single-spin-coated ferroelectric film this value is approximately 16 nm. A ferroelectric-gated field-effect transistor was fabricated using the proposed double-spin-coating method, showing a maximum saturation mobility as much as seven-fold than that of a transistor fabricated with single-spin-coated ferroelectric film. The enhanced saturation mobility could be explained by the Poole–Frenkel conduction mechanism. The proposed method to reduce the surface roughness of ferroelectric film would be useful for high performance organic electronic devices, including crystalline-phase dielectric film. - Highlights: • Single and double-layer solution-processed polymer ferroelectric films were obtained. • Adjusting the solvent solubility allows making double-layer ferroelectric (DF) films. • The DF film has a smoother surface than single-layer ferroelectric (SF) film. • DF-gated transistor has faster saturation mobility than SF-based transistor. • Solvent solubility adjustment led to higher performance organic devices.

Performance of organic field effect transistors with high-k gate oxide after application of consecutive bias stress

Energy Technology Data Exchange (ETDEWEB)

Lee, Sunwoo; Choi, Changhwan; Lee, Kilbock [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of); Cho, Joong Hwee [Department of Embedded Systems Engineering,University of Incheon, Incheon 406-722 (Korea, Republic of); Ko, Ki-Young [Korea Institute of Patent Information, Seoul, 146-8 (Korea, Republic of); Ahn, Jinho, E-mail: jhahn@hanyang.ac.kr [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of)

2012-10-30

We report the effect of consecutive electrical stress on the performance of organic field effect transistors (OFETs). Sputtered aluminum oxide (Al{sub 2}O{sub 3}) and hafnium oxide (HfO{sub 2}) were used as gate oxide layers. After the electrical stress, the threshold voltage, which strongly depends on bulk defects, was remarkably shifted to the negative direction, while the other performance characteristics of OFETs such as on-current, transconductance and mobility, which are sensitive to interface defects, were slightly decreased. This result implies that the defects in the bulk layer are significantly affected compared to the defects in the interface layer. Thus, it is important to control the defects in the pentacene bulk layer in order to maintain the good reliabilities of pentacene devices. Those defects in HfO{sub 2} gate oxide devices were larger compared to those in Al{sub 2}O{sub 3} gate oxide devices.

Decrease in effective electron mobility in the channel of a metal-oxide-semiconductor transistor as the gate length is decreased

International Nuclear Information System (INIS)

Frantsuzov, A. A.; Boyarkina, N. I.; Popov, V. P.

2008-01-01

Effective electron mobility μ eff in channels of metal-oxide-semiconductor transistors with a gate length L in the range of 3.8 to 0.34 μm was measured; the transistors were formed on wafers of the silicon-oninsulator type. It was found that μ eff decreases as L is decreased. It is shown that this decrease can be accounted for by the effect of series resistances of the source and drain only if it is assumed that there is a rapid increase in these resistances as the gate voltage is decreased. This assumption is difficult to substantiate. A more realistic model is suggested; this model accounts for the observed decrease in μ eff as L is decreased. The model implies that zones with a mobility lower than that in the middle part of the channel originate at the edges of the gate. An analysis shows that, in this case, the plot of the dependence of 1/μ eff on 1/L should be linear, which is exactly what is observed experimentally. The use of this plot makes it possible to determine both the electron mobility μ 0 in the middle part of the channel and the quantity A that characterizes the zones with lowered mobility at the gate’s edges.

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

International Nuclear Information System (INIS)

Liu Ying; He Jin; Chan Mansun; Ye Yun; Zhao Wei; Wu Wen; Deng Wan-Ling; Wang Wen-Ping; Du Cai-Xia

2014-01-01

An analytical model of gate-all-around (GAA) silicon nanowire tunneling field effect transistors (NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling (BTBT) efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane's expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

High performance tunnel field-effect transistor by gate and source engineering

International Nuclear Information System (INIS)

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-01-01

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I ON /I OFF ratio (∼10 7 ) at V DS  = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high I ON /I OFF ratio of ∼10 8 and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec −1 was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching. (paper)

Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

International Nuclear Information System (INIS)

Ai-Fang, Yu; Qiong, Qi; Peng, Jiang; Chao, Jiang

2009-01-01

Carrier mobility enhancement from 0.09 to 0.59 cm 2 /Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO 2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO 2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO 2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski–Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility. (cross-disciplinary physics and related areas of science and technology)

High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper

Science.gov (United States)

Kim, Minkyu; Jeong, Jong Han; Lee, Hun Jung; Ahn, Tae Kyung; Shin, Hyun Soo; Park, Jin-Seong; Jeong, Jae Kyeong; Mo, Yeon-Gon; Kim, Hye Dong

2007-05-01

The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiOx layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W /L=10μm/50μm) fabricated on glass exhibited a high field-effect mobility of 35.8cm2/Vs, a subthreshold gate swing value of 0.59V/decade, a thrseshold voltage of 5.9V, and an Ion/off ratio of 4.9×106, which is acceptable for use as the switching transistor of an active-matrix TFT backplane.

Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

Energy Technology Data Exchange (ETDEWEB)

Liao, Po-Yung [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan (China); Chou, Cheng-Hsu; Chang, Jung-Fang [Product Technology Center, Chimei Innolux Corp., Tainan 741, Taiwan (China)

2016-03-31

The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V{sub T}) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V{sub T} shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V{sub T} shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V{sub T} shift increases with decreasing frequency of the top gate pulses.

Investigating degradation behavior of hole-trapping effect under static and dynamic gate-bias stress in a dual gate a-InGaZnO thin film transistor with etch stop layer

International Nuclear Information System (INIS)

Liao, Po-Yung; Chang, Ting-Chang; Hsieh, Tien-Yu; Tsai, Ming-Yen; Chen, Bo-Wei; Chu, Ann-Kuo; Chou, Cheng-Hsu; Chang, Jung-Fang

2016-01-01

The degree of degradation between the amorphous-indium–gallium–zinc oxide (a-IGZO) thin film transistor (TFT) using the top-gate only or bottom-gate only is compared. Under negative gate bias illumination stress (NBIS), the threshold voltage (V T ) after bottom-gate NBIS monotonically shifts in the negative direction, whereas top-gate NBIS operation exhibits on-state current increases without V T shift. Such anomalous degradation behavior of NBIS under top-gate operation is due to hole-trapping in the etch stop layer above the central portion of the channel. These phenomena can be ascribed to the screening of the electric field by redundant source/drain electrodes. In addition, the device degradation of dual gate a-IGZO TFT stressed with different top gate pulse waveforms is investigated. It is observed that the degradation is dependent on the frequency of the top gate pulses. The V T shift increases with decreasing frequency, indicating the hole mobility of IGZO is low. - Highlights: • Static and dynamic gate bias stresses are imposed on dual gate InGaZnO TFTs. • Top-gate NBIS operation exhibits on-state current increases without VT shift. • The degradation behavior of top-gate NBIS is due to hole-trapping in the ESL. • The degradation is dependent on the frequency of the top gate pulses. • The V T shift increases with decreasing frequency of the top gate pulses.

High performance organic field-effect transistors with ultra-thin HfO2 gate insulator deposited directly onto the organic semiconductor

International Nuclear Information System (INIS)

Ono, S.; Häusermann, R.; Chiba, D.; Shimamura, K.; Ono, T.; Batlogg, B.

2014-01-01

We have produced stable organic field-effect transistors (OFETs) with an ultra-thin HfO 2 gate insulator deposited directly on top of rubrene single crystals by atomic layer deposition (ALD). We find that ALD is a gentle deposition process to grow thin films without damaging rubrene single crystals, as results these devices have a negligibly small threshold voltage and are very stable against gate-bias-stress, and the mobility exceeds 1 cm 2 /V s. Moreover, the devices show very little degradation even when kept in air for more than 2 months. These results demonstrate thin HfO 2 layers deposited by ALD to be well suited as high capacitance gate dielectrics in OFETs operating at small gate voltage. In addition, the dielectric layer acts as an effective passivation layer to protect the organic semiconductor

Effect of a gate buffer layer on the performance of a 4H-SiC Schottky barrier field-effect transistor

International Nuclear Information System (INIS)

Zhang Xianjun; Yang Yintang; Chai Changchun; Duan Baoxing; Song Kun; Chen Bin

2012-01-01

A lower doped layer is inserted between the gate and channel layer and its effect on the performance of a 4H-SiC Schottky barrier field-effect transistor (MESFET) is investigated. The dependences of the drain current and small signal parameters on this inserted gate-buffer layer are obtained by solving one-dimensional (1-D) and two-dimensional (2-D) Poisson's equations. The drain current and small signal parameters of the 4H-SiC MESFET with a gate-buffer layer thickness of 0.15 μm are calculated and the breakdown characteristics are simulated. The results show that the current is increased by increasing the thickness of the gate-buffer layer; the breakdown voltage is 160 V, compared with 125 V for the conventional 4H-SiC MESFET; the cutoff frequency is 27 GHz, which is higher than 20 GHz of the conventional structure due to the lower doped gate-buffer layer. (semiconductor devices)

Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

International Nuclear Information System (INIS)

Yoon, Sung-Min; Yang, Shin-Hyuk; Ko Park, Sang-Hee; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon

2009-01-01

Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A.

Radio Frequency Transistors Using Aligned Semiconducting Carbon Nanotubes with Current-Gain Cutoff Frequency and Maximum Oscillation Frequency Simultaneously Greater than 70 GHz.

Science.gov (United States)

Cao, Yu; Brady, Gerald J; Gui, Hui; Rutherglen, Chris; Arnold, Michael S; Zhou, Chongwu

2016-07-26

In this paper, we report record radio frequency (RF) performance of carbon nanotube transistors based on combined use of a self-aligned T-shape gate structure, and well-aligned, high-semiconducting-purity, high-density polyfluorene-sorted semiconducting carbon nanotubes, which were deposited using dose-controlled, floating evaporative self-assembly method. These transistors show outstanding direct current (DC) performance with on-current density of 350 μA/μm, transconductance as high as 310 μS/μm, and superior current saturation with normalized output resistance greater than 100 kΩ·μm. These transistors create a record as carbon nanotube RF transistors that demonstrate both the current-gain cutoff frequency (ft) and the maximum oscillation frequency (fmax) greater than 70 GHz. Furthermore, these transistors exhibit good linearity performance with 1 dB gain compression point (P1dB) of 14 dBm and input third-order intercept point (IIP3) of 22 dBm. Our study advances state-of-the-art of carbon nanotube RF electronics, which have the potential to be made flexible and may find broad applications for signal amplification, wireless communication, and wearable/flexible electronics.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

Science.gov (United States)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Multiple Independent Gate FETs: How Many Gates Do We Need?

OpenAIRE

Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni

2015-01-01

Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...

Improvements in the reliability of a-InGaZnO thin-film transistors with triple stacked gate insulator in flexible electronics applications

Energy Technology Data Exchange (ETDEWEB)

Chen, Hua-Mao [Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Tai, Ya-Hsiang [Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Chen, Kuan-Fu [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Chiang, Hsiao-Cheng [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Liu, Kuan-Hsien [Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan (China); Lee, Chao-Kuei [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Lin, Wei-Ting; Cheng, Chun-Cheng; Tu, Chun-Hao; Liu, Chu-Yu [Advanced Technology Research Center, AU Optronics Corp, Hsinchu, Taiwan (China)

2015-11-30

This study examined the impact of the low-temperature stacking gate insulator on the gate bias instability of a-InGaZnO thin film transistors in flexible electronics applications. Although the quality of SiN{sub x} at low process/deposition temperature is better than that of SiO{sub x} at similarly low process/deposition temperature, there is still a very large positive threshold voltage (V{sub th}) shift of 9.4 V for devices with a single low-temperature SiN{sub x} gate insulator under positive gate bias stress. However, a suitable oxide–nitride–oxide-stacked gate insulator exhibits a V{sub th} shift of only 0.23 V. This improvement results from the larger band offset and suitable gate insulator thickness that can effectively suppress carrier trapping behavior. - Highlights: • The cause of the bias instability for a low-temperature gate insulator is verified. • A triple-stacked gate insulator was fabricated. • A suitable triple stacked gate insulator shows only 0.23 V threshold voltage shift.

Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

Science.gov (United States)

Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

2016-01-01

The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

Problems of noise modeling in the presence of total current branching in high electron mobility transistor and field-effect transistor channels

International Nuclear Information System (INIS)

Shiktorov, P; Starikov, E; Gružinskis, V; Varani, L; Sabatini, G; Marinchio, H; Reggiani, L

2009-01-01

In the framework of analytical and hydrodynamic models for the description of carrier transport and noise in high electron mobility transistor/field-effect transistor channels the main features of the intrinsic noise of transistors are investigated under continuous branching of the current between channel and gate. It is shown that the current-noise and voltage-noise spectra at the transistor terminals contain an excess noise related to thermal excitation of plasma wave modes in the dielectric layer between the channel and gate. It is found that the set of modes of excited plasma waves can be governed by the external embedding circuits, thus violating a universal description of noise in terms of Norton and Thevenin noise generators

Method for double-sided processing of thin film transistors

Science.gov (United States)

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Effect of liquid gate bias rising time in pH sensors based on Si nanowire ion sensitive field effect transistors

Science.gov (United States)

Jang, Jungkyu; Choi, Sungju; Kim, Jungmok; Park, Tae Jung; Park, Byung-Gook; Kim, Dong Myong; Choi, Sung-Jin; Lee, Seung Min; Kim, Dae Hwan; Mo, Hyun-Sun

2018-02-01

In this study, we investigate the effect of rising time (TR) of liquid gate bias (VLG) on transient responses in pH sensors based on Si nanowire ion-sensitive field-effect transistors (ISFETs). As TR becomes shorter and pH values decrease, the ISFET current takes a longer time to saturate to the pH-dependent steady-state value. By correlating VLG with the internal gate-to-source voltage of the ISFET, we found that this effect occurs when the drift/diffusion of mobile ions in analytes in response to VLG is delayed. This gives us useful insight on the design of ISFET-based point-of-care circuits and systems, particularly with respect to determining an appropriate rising time for the liquid gate bias.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

Science.gov (United States)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

MOSFET Electric-Charge Sensor

Science.gov (United States)

Robinson, Paul A., Jr.

1988-01-01

Charged-particle probe compact and consumes little power. Proposed modification enables metal oxide/semiconductor field-effect transistor (MOSFET) to act as detector of static electric charges or energetic charged particles. Thickened gate insulation acts as control structure. During measurements metal gate allowed to "float" to potential of charge accumulated in insulation. Stack of modified MOSFET'S constitutes detector of energetic charged particles. Each gate "floats" to potential induced by charged-particle beam penetrating its layer.

Application of calendering for improving the electrical characteristics of a printed top-gate, bottom-contact organic thin film transistors

Science.gov (United States)

Lee, Sang Hoon; Lee, Dong Geun; Jung, Hoeryong; Lee, Sangyoon

2018-05-01

Interface between the channel and the gate dielectric of organic thin film transistors (OTFTs) needs to be smoothed in order to improve the electrical characteristics. In this study, an optimized calendering process was proposed to improve the surface roughness of the channel. Top-gate, bottom-contact structural p-type OTFT samples were fabricated using roll-to-roll gravure printing (source/drain, channel), spin coating (gate dielectric), and inkjet printing (gate electrode). The calendering process was optimized using the grey-based Taguchi method. The channel surface roughness and electrical characteristics of calendered and non-calendered samples were measured and compared. As a result, the average improvement in the surface roughness of the calendered samples was 26.61%. The average on–off ratio and field-effect mobility of the calendered samples were 3.574 × 104 and 0.1113 cm2 V‑1 s‑1, respectively, which correspond to the improvements of 16.72 and 10.20%, respectively.

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

Energy Technology Data Exchange (ETDEWEB)

Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 130-701 (Korea, Republic of)

2015-05-15

We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

Top-gate hybrid complementary inverters using pentacene and amorphous InGaZnO thin-film transistors with high operational stability

Directory of Open Access Journals (Sweden)

J. B. Kim

2012-03-01

Full Text Available We report on the operational stability of low-voltage hybrid organic-inorganic complementary inverters with a top-gate bottom source-drain geometry. The inverters are comprised of p-channel pentacene and n-channel amorphous InGaZnO thin-film transistors (TFTs with bi-layer gate dielectrics formed from an amorphous layer of a fluoropolymer (CYTOP and a high-k layer of Al2O3. The p- and n- channel TFTs show saturation mobility values of 0.1 ± 0.01 and 5.0 ± 0.5 cm2/Vs, respectively. The individual transistors show high electrical stability with less than 6% drain-to-source current variations after 1 h direct current (DC bias stress. Complementary inverters yield hysteresis-free voltage transfer characteristics for forward and reverse input biases with static DC gain values larger than 45 V/V at 8 V before and after being subjected to different conditions of electrical stress. Small and reversible variations of the switching threshold voltage of the inverters during these stress tests are compatible with the observed stability of the individual TFTs.

Contact effects analyzed by a parameter extraction method based on a single bottom-gate/top-contact organic thin-film transistor

Science.gov (United States)

Takagaki, Shunsuke; Yamada, Hirofumi; Noda, Kei

2018-03-01

Contact effects in organic thin-film transistors (OTFTs) were examined by using our previously proposed parameter extraction method from the electrical characteristics of a single staggered-type device. Gate-voltage-dependent contact resistance and channel mobility in the linear regime were evaluated for bottom-gate/top-contact (BGTC) pentacene TFTs with active layers of different thicknesses, and for pentacene TFTs with contact-doped layers prepared by coevaporation of pentacene and tetrafluorotetracyanoquinodimethane (F4TCNQ). The extracted parameters suggested that the influence of the contact resistance becomes more prominent with the larger active-layer thickness, and that contact-doping experiments give rise to a drastic decrease in the contact resistance and a concurrent considerable improvement in the channel mobility. Additionally, the estimated energy distributions of trap density in the transistor channel probably reflect the trap filling with charge carriers injected into the channel regions. The analysis results in this study confirm the effectiveness of our proposed method, with which we can investigate contact effects and circumvent the influences of characteristic variations in OTFT fabrication.

A single nano cantilever as a reprogrammable universal logic gate

International Nuclear Information System (INIS)

Chappanda, K N; Ilyas, S; Kazmi, S N R; Younis, M I; Holguin-Lerma, J; Batra, N M; Costa, P M F J

2017-01-01

The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing. (paper)

A single nano cantilever as a reprogrammable universal logic gate

KAUST Repository

Chappanda, K. N.

2017-02-24

The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.

Radiation effect of gate controlled lateral PNP BJTs

International Nuclear Information System (INIS)

Xi Shanbin; Zhou Dong; Lu Wu; Ren Diyuan; Wen Lin; Sun Jing; Wang Zhikuan

2012-01-01

Design and fabricate a new test structure of bipolar device: the gate controlled later PNP bipolar transistor (GCLPNP BJT), then sealed it together with the normal lateral PNP bipolar transistor which is made under the same manufacture process. Then 60 Co-γ radiation effects and annealing behaviors of these two structures are investigated. The results show that the response about base current, collector current, access base current and normalized current gain of GCLPNP bipolar transistor are almost identical to the normal one. Radiation induced defects in the GCLPNP bipolar transistor is separated quantitatively. Studying on the quantitative change of radiation induced defects in the domestic gate controlled bipolar transistor should be a useful way to research the change of radiation induced charges of normal PNP bipolar transistor. (authors)

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

Science.gov (United States)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

Multiple-channel detection of cellular activities by ion-sensitive transistors

Science.gov (United States)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper

International Nuclear Information System (INIS)

Kim, Minkyu; Jeong, Jong Han; Lee, Hun Jung; Ahn, Tae Kyung; Shin, Hyun Soo; Park, Jin-Seong; Jeong, Jae Kyeong; Mo, Yeon-Gon; Kim, Hye Dong

2007-01-01

The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiO x layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W/L=10 μm/50 μm) fabricated on glass exhibited a high field-effect mobility of 35.8 cm 2 /V s, a subthreshold gate swing value of 0.59 V/decade, a thrseshold voltage of 5.9 V, and an I on/off ratio of 4.9x10 6 , which is acceptable for use as the switching transistor of an active-matrix TFT backplane

Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal–oxide–silicon field effect transistors

International Nuclear Information System (INIS)

Jin, Xiaoshi; Liu, Xi; Lee, Jung-Hee; Lee, Jong-Ho

2014-01-01

A subthreshold model of short-channel junctionless field effect transistors with cylindrical surrounding-gate nanowire structure has been proposed. It was based on an approximated solution of two-dimensional Poisson's equation. The derivation of this model was introduced and the accuracy of the proposed models have been verified by comparison with both previous models and the SILVACO Atlas TCAD simulation results, which show good agreement. (paper)

Leakage current suppression with a combination of planarized gate and overlap/off-set structure in metal-induced laterally crystallized polycrystalline-silicon thin-film transistors

Science.gov (United States)

Chae, Hee Jae; Seok, Ki Hwan; Lee, Sol Kyu; Joo, Seung Ki

2018-04-01

A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.

Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

Science.gov (United States)

Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

2018-06-01

Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Science.gov (United States)

Sengupta, Sarmista; Pandit, Soumya

2015-06-01

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.

Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

International Nuclear Information System (INIS)

Liu, Siyang; Zhang, Chunwei; Sun, Weifeng; Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu

2014-01-01

Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic

Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

Energy Technology Data Exchange (ETDEWEB)

Liu, Siyang; Zhang, Chunwei; Sun, Weifeng, E-mail: swffrog@seu.edu.cn [National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 (China); Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu [CSMC Technologies Corporation, Wuxi 214061 (China)

2014-04-14

Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic.

Principles of an atomtronic transistor

International Nuclear Information System (INIS)

Caliga, Seth C; Anderson, Dana Z; Straatsma, Cameron J E; Zozulya, Alex A

2016-01-01

A semiclassical formalism is used to investigate the transistor-like behavior of ultracold atoms in a triple-well potential. Atom current flows from the source well, held at fixed chemical potential and temperature, into an empty drain well. In steady-state, the gate well located between the source and drain is shown to acquire a well-defined chemical potential and temperature, which are controlled by the relative height of the barriers separating the three wells. It is shown that the gate chemical potential can exceed that of the source and have a lower temperature. In electronics terminology, the source–gate junction can be reverse-biased. As a result, the device exhibits regimes of negative resistance and transresistance, indicating the presence of gain. Given an external current input to the gate, transistor-like behavior is characterized both in terms of the current gain, which can be greater than unity, and the power output of the device. (paper)

Modelling of nanoscale multi-gate transistors affected by atomistic interface roughness

Science.gov (United States)

Nagy, Daniel; Aldegunde, Manuel; Elmessary, Muhammad A.; García-Loureiro, Antonio J.; Seoane, Natalia; Kalna, Karol

2018-04-01

Interface roughness scattering (IRS) is one of the major scattering mechanisms limiting the performance of non-planar multi-gate transistors, like Fin field-effect transistors (FETs). Here, two physical models (Ando’s and multi-sub-band) of electron scattering with the interface roughness induced potential are investigated using an in-house built 3D finite element ensemble Monte Carlo simulation toolbox including parameter-free 2D Schrödinger equation quantum correction that handles all relevant scattering mechanisms within highly non-equilibrium carrier transport. Moreover, we predict the effect of IRS on performance of FinFETs with realistic channel cross-section shapes with respect to the IRS correlation length (Λ) and RMS height (Δ_RMS ). The simulations of the n-type SOI FinFETs with the multi-sub-band IRS model shows its very strong effect on electron transport in the device channel compared to the Ando’s model. We have also found that the FinFETs are strongly affected by the IRS in the ON-region. The limiting effect of the IRS significantly increases as the Fin width is reduced. The FinFETs with channel orientation are affected more by the IRS than those with the crystal orientation. Finally, Λ and Δ_RMS are shown to affect the device performance similarly. A change in values by 30% (Λ) or 20% (Δ_RMS ) results in an increase (decrease) of up to 13% in the drive current.

Ultra-Low Power Consuming Direct Radiation Sensors Based on Floating Gate Structures

Directory of Open Access Journals (Sweden)

Evgeny Pikhay

2017-07-01

Full Text Available In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail. Original array sensors were suggested and fabricated that allowed high statistical significance of the radiation measurements and radiation imaging functions. Single sensors and array sensors were analyzed in combination with the specially developed test structures. This allowed insight into the physics of sensor operations and exclusion of the phenomena related to material degradation under irradiation in the interpretation of the measurement results. Response of the developed sensors to various sources of ionizing radiation (Gamma, X-ray, UV, energetic ions was investigated. The optimal design of sensor for implementation in dosimetry systems was suggested. The roadmap for future improvement of sensor performance is suggested.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

Science.gov (United States)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

Science.gov (United States)

Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode.

Science.gov (United States)

Yun, Ho-Jin; Ham, Yong-Hyun; Shin, Hong-Sik; Jeong, Kwang-Seok; Park, Jeong-Gyu; Choi, Deuk-Sung; Lee, Ga-Won

2011-07-01

We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.

Influence of gate dielectric on the ambipolar characteristics of solution-processed organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Ribierre, J C; Ghosh, S; Takaishi, K; Muto, T; Aoyama, T, E-mail: jcribierre@ewha.ac.kr, E-mail: taoyama@riken.jp [Advanced Science Institute, RIKEN, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

2011-05-25

Solution-processed ambipolar organic field-effect transistors based on dicyanomethylene-substituted quinoidal quaterthiophene derivative [QQT(CN)4] are fabricated using various gate dielectric materials including cross-linked polyimide and poly-4-vinylphenol. Devices with spin-coated polymeric gate dielectric layers show a reduced hysteresis in their transfer characteristics. Among the insulating polymers examined in this study, a new fluorinated polymer with a low dielectric constant of 2.8 significantly improves both hole and electron field-effect mobilities of QQT(CN)4 thin films to values as high as 0.04 and 0.002 cm{sup 2} V{sup -1} s{sup -1}. These values are close to the best mobilities obtained in QQT(CN)4 devices fabricated on SiO{sub 2} treated with octadecyltrichlorosilane. The influence of the metal used for source/drain metal electrodes on the device performance is also investigated. Whereas best device performances are achieved with gold electrodes, more balanced electron and hole field-effect mobilities could be obtained using chromium.

Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

Science.gov (United States)

Ramezani, Zeinab; Orouji, Ali A.

2018-01-01

A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

Fully printed metabolite sensor using organic electrochemical transistor

Science.gov (United States)

Scheiblin, Gaëtan; Aliane, Abdelkader; Coppard, Romain; Owens, Róisín. M.; Mailley, Pascal; Malliaras, George G.

2015-08-01

As conducting polymer based devices, organic electrochemical transistors (OECTs) are suited for printing process. The convenience of the screen-printing techniques allowed us to design and fabricate OECTs with a selected design and using different gate material. Depending on the material used, we were able to tune the transistor for different biological application. Ag/AgCl gate provided transistor with good transconductance, and electrochemical sensitivity to pH was provided by polyaniline ink. Finally, we validate the enzymatic sensing of glucose and lactate with a Poly(3,4-ethylene dioxythiophene) doped with poly(styrene sulfonate) (PEDOT:PSS) gate often used due to its biocompatible properties. The screen-printing process allowed us to fabricate a large amount of devices in a short period of time, using only commercially available grades of ink, showing by this way the possible transfer to industrial purpose.

Vertically aligned carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi

2012-10-01

Vertically aligned carbon nanotube field-effect transistors (CNTFETs) have been developed using pure semiconducting carbon nanotubes. The source and drain were vertically stacked, separated by a dielectric, and the carbon nanotubes were placed on the sidewall of the stack to bridge the source and drain. Both the effective gate dielectric and gate electrode were normal to the substrate surface. The channel length is determined by the dielectric thickness between source and drain electrodes, making it easier to fabricate sub-micrometer transistors without using time-consuming electron beam lithography. The transistor area is much smaller than the planar CNTFET due to the vertical arrangement of source and drain and the reduced channel area. © 2012 Elsevier Ltd. All rights reserved.

A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature

Science.gov (United States)

Yadav, Dharmendra Singh; Raad, Bhagwan Ram; Sharma, Dheeraj

2016-12-01

In this paper, we focus on the improvement of figures of merit for charge plasma based tunnel field-effect transistor (TFET) in terms of ON-state current, threshold voltage, sub-threshold swing, ambipolar nature, and gate to drain capacitance which provides better channel controlling of the device with improved high frequency response at ultra-low supply voltages. Regarding this, we simultaneously employ work function engineering on the drain and gate electrode of the charge plasma TFET. The use of gate work function engineering modulates the barrier on the source/channel interface leads to improvement in the ON-state current, threshold voltage, and sub-threshold swing. Apart from this, for the first time use of work function engineering on the drain electrode increases the tunneling barrier for the flow of holes on the drain/channel interface, it results into suppression of ambipolar behavior. The lowering of gate to drain capacitance therefore enhanced high frequency parameters. Whereas, the presence of dual work functionality at the gate electrode and over the drain region improves the overall performance of the charge plasma based TFET.

Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

Science.gov (United States)

Shin, SeungJun; Yu, YunSeop; Choi, JungBum

2008-10-01

New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

An Al₂O₃ Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials.

Science.gov (United States)

Yang, Hang; Qin, Shiqiao; Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Peng, Gang; Zhang, Xueao

2017-09-22

We fabricated 70 nm Al₂O₃ gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al₂O₃/Si substrate is superior to that on a traditional 300 nm SiO₂/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al₂O₃/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS₂, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices.

Thermal transistor utilizing gas-liquid transition

KAUST Repository

Komatsu, Teruhisa S.

2011-01-25

We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter. © 2011 American Physical Society.

Graphene-graphite oxide field-effect transistors.

Science.gov (United States)

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Photodetection in p–n junctions formed by electrolyte-gated transistors of two-dimensional crystals

KAUST Repository

Kozawa, Daichi

2016-11-16

Transition metal dichalcogenide monolayers have attracted much attention due to their strong light absorption and excellent electronic properties. These advantages make this type of two-dimensional crystal a promising one for optoelectronic device applications. In the case of photoelectric conversion devices such as photodetectors and photovoltaic cells, p–n junctions are one of the most important devices. Here, we demonstrate photodetection with WSe2 monolayer films. We prepare the electrolyte-gated ambipolar transistors and electrostatic p–n junctions are formed by the electrolyte-gating technique at 270 K. These p-n junctions are cooled down to fix the ion motion (and p-n junctions) and we observed the reasonable photocurrent spectra without the external bias, indicating the formation of p-n junctions. Very interestingly, two-terminal devices exhibit higher photoresponsivity than that of three-terminal ones, suggesting the formation of highly balanced anion and cation layers. The maximum photoresponsivity reaches 5 mA/W in resonance with the first excitonic peak. Our technique provides important evidence for optoelectronics in atomically thin crystals.

Screening-induced surface polar optical phonon scattering in dual-gated graphene field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Hu, Bo, E-mail: hubo2011@semi.ac.cn

2015-03-15

The effect of surface polar optical phonons (SOs) from the dielectric layers on electron mobility in dual-gated graphene field effect transistors (GFETs) is studied theoretically. By taking into account SO scattering of electron as a main scattering mechanism, the electron mobility is calculated by the iterative solution of Boltzmann transport equation. In treating scattering with the SO modes, the dynamic dielectric screening is included and compared to the static dielectric screening and the dielectric screening in the static limit. It is found that the dynamic dielectric screening effect plays an important role in the range of low net carrier density. More importantly, in-plane acoustic phonon scattering and charged impurity scattering are also included in the total mobility for SiO{sub 2}-supported GFETs with various high-κ top-gate dielectric layers considered. The calculated total mobility results suggest both Al{sub 2}O{sub 3} and AlN are the promising candidate dielectric layers for the enhancement in room temperature mobility of graphene in the future.

Photodetection in p–n junctions formed by electrolyte-gated transistors of two-dimensional crystals

KAUST Repository

Kozawa, Daichi; Pu, Jiang; Shimizu, Ryo; Kimura, Shota; Chiu, Ming-Hui; Matsuki, Keiichiro; Wada, Yoshifumi; Sakanoue, Tomo; Iwasa, Yoshihiro; Li, Lain-Jong; Takenobu, Taishi

2016-01-01

Transition metal dichalcogenide monolayers have attracted much attention due to their strong light absorption and excellent electronic properties. These advantages make this type of two-dimensional crystal a promising one for optoelectronic device applications. In the case of photoelectric conversion devices such as photodetectors and photovoltaic cells, p–n junctions are one of the most important devices. Here, we demonstrate photodetection with WSe2 monolayer films. We prepare the electrolyte-gated ambipolar transistors and electrostatic p–n junctions are formed by the electrolyte-gating technique at 270 K. These p-n junctions are cooled down to fix the ion motion (and p-n junctions) and we observed the reasonable photocurrent spectra without the external bias, indicating the formation of p-n junctions. Very interestingly, two-terminal devices exhibit higher photoresponsivity than that of three-terminal ones, suggesting the formation of highly balanced anion and cation layers. The maximum photoresponsivity reaches 5 mA/W in resonance with the first excitonic peak. Our technique provides important evidence for optoelectronics in atomically thin crystals.

Monolithic acoustic graphene transistors based on lithium niobate thin film

Science.gov (United States)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

Science.gov (United States)

Fan, Ching-Lin; Shang, Ming-Chi; Hsia, Mao-Yuan; Wang, Shea-Jue; Huang, Bohr-Ran; Lee, Win-Der

2016-03-01

A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4-vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

Detection of prostate-specific antigen with biomolecule-gated AlGaN/GaN high electron mobility transistors

Science.gov (United States)

Li, Jia-dong; Cheng, Jun-jie; Miao, Bin; Wei, Xiao-wei; Xie, Jie; Zhang, Jin-cheng; Zhang, Zhi-qiang; Wu, Dong-min

2014-07-01

In order to improve the sensitivity of AlGaN/GaN high electron mobility transistor (HEMT) biosensors, a simple biomolecule-gated AlGaN/GaN HEMT structure was designed and successfully fabricated for prostate specific antigen (PSA) detection. UV/ozone was used to oxidize the GaN surface and then a 3-aminopropyl trimethoxysilane (APTES) self-assembled monolayer was bound to the sensing region. This monolayer serves as a binding layer for attachment of the prostate specific antibody (anti-PSA). The biomolecule-gated AlGaN/GaN HEMT sensor shows a rapid and sensitive response when the target prostate-specific antigen in buffer solution was added to the antibody-immobilized sensing area. The current change showed a logarithm relationship against the PSA concentration from 0.1 pg/ml to 0.993 ng/ml. The sensitivity of 0.215% is determined for 0.1 pg/ml PSA solution. The above experimental result of the biomolecule-gated AlGaN/GaN HEMT biosensor suggested that this biosensor might be a useful tool for prostate cancer screening.

Detection of prostate-specific antigen with biomolecule-gated AlGaN/GaN high electron mobility transistors

International Nuclear Information System (INIS)

Li, Jia-dong; Miao, Bin; Wei, Xiao-wei; Xie, Jie; Wu, Dong-min; Cheng, Jun-jie; Zhang, Jin-cheng; Zhang, Zhi-qiang

2014-01-01

In order to improve the sensitivity of AlGaN/GaN high electron mobility transistor (HEMT) biosensors, a simple biomolecule-gated AlGaN/GaN HEMT structure was designed and successfully fabricated for prostate specific antigen (PSA) detection. UV/ozone was used to oxidize the GaN surface and then a 3-aminopropyl trimethoxysilane (APTES) self-assembled monolayer was bound to the sensing region. This monolayer serves as a binding layer for attachment of the prostate specific antibody (anti-PSA). The biomolecule-gated AlGaN/GaN HEMT sensor shows a rapid and sensitive response when the target prostate-specific antigen in buffer solution was added to the antibody-immobilized sensing area. The current change showed a logarithm relationship against the PSA concentration from 0.1 pg/ml to 0.993 ng/ml. The sensitivity of 0.215% is determined for 0.1 pg/ml PSA solution. The above experimental result of the biomolecule-gated AlGaN/GaN HEMT biosensor suggested that this biosensor might be a useful tool for prostate cancer screening. (paper)

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

Science.gov (United States)

Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

2018-04-01

Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

Science.gov (United States)

Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

2015-12-18

The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

Science.gov (United States)

Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

2017-10-01

In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

International Nuclear Information System (INIS)

Xia, D X; Xu, J B

2010-01-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm 2 V -1 s -1 and 2.1 cm 2 V -1 s -1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics. (fast track communication)

Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

International Nuclear Information System (INIS)

Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

2009-01-01

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique

Directory of Open Access Journals (Sweden)

Juan Jesus Ocampo-Hidalgo

2017-05-01

Full Text Available This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.

Electrical characteristics of vapor deposited amorphous MoS2 two-terminal structures and back gate thin film transistors with Al, Au, Cu and Ni-Au contacts

International Nuclear Information System (INIS)

Kouvatsos, Dimitrios N.; Papadimitropoulos, Georgios; Spiliotis, Thanassis; Vasilopoulou, Maria; Davazoglou, Dimitrios; Barreca, Davide; Gasparotto, Alberto

2015-01-01

Amorphous molybdenum sulphide (a-MoS 2 ) thin films were deposited at near room temperature on oxidized silicon substrates and were electrically characterized with the use of two-terminal structures and of back-gated thin film transistors utilizing the substrate silicon as gate. Current-voltage characteristics were extracted for various metals used as pads, showing significant current variations attributable to different metal-sulphide interface properties and contact resistances, while the effect of a forming gas anneal was determined. With the use of heavily doped silicon substrates and aluminum backside deposition, thin film transistor (TFT) structures with the a-MoS 2 film as active layer were fabricated and characterized. Transfer characteristics showing a gate field effect, despite a leakage often present, were extracted for these devices, indicating that high mobility devices can be fabricated. SEM and EDXA measurements were also performed in an attempt to clarify issues related to material properties and fabrication procedures, so as to achieve a reliable and optimized a-MoS 2 TFT fabrication process. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene–graphene composite layers for flexible thin film transistors with a polymer gate dielectric

International Nuclear Information System (INIS)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-01-01

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene–graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene–graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm 2  V −1  s −1 and a threshold voltage of −0.7 V at V gs = −40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm 2  V −1  s −1 and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies. (paper)

Static Characteristics of the Ferroelectric Transistor Inverter

Science.gov (United States)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors.

Science.gov (United States)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2013-11-07

In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

International Nuclear Information System (INIS)

Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

2006-01-01

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 μm 2 for the two-input NAND gate and 0.049 μm 2 for the full adder circuits

Performance and Design Considerations of a Novel Dual-Material Gate Carbon Nanotube Field-Effect Transistors: Nonequilibrium Green's Function Approach

Science.gov (United States)

Arefinia, Zahra; Orouji, Ali A.

2009-02-01

The concept of dual-material gate (DMG) is applied to the carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions, and the features exhibited by the resulting new structure, i.e., the DMG-CNTFET structure, have been examined for the first time by developing a two-dimensional (2D) full quantum simulation. The simulations have been done by the self-consistent solution of 2D Poisson-Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The results show DMG-CNTFET decreases significantly leakage current and drain conductance and increases on-off current ratio and voltage gain as compared to the single material gate counterparts CNTFET. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate metals. Therefore, this work provides an incentive for further experimental exploration.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

Science.gov (United States)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Effects of the gate dielectric on the subthreshold transport of carbon nanotube network transistors grown by using plasma-enhanced chemical vapor deposition

International Nuclear Information System (INIS)

Jeong, Seung Geun; Park, Wan Jun

2010-01-01

In this study, we investigated the subthreshold slope of random network carbon nanotube transistors with different geometries and passivations. Single-wall carbon nanotubes with lengths of 1-2 m were grown by using plasma-enhanced chemical vapor deposition to form the transistor channels. A critical channel length, where the subthreshold slope was saturated, of 7 μm was obtained. This was due to the percolational behavior of the nanotube random networks. With the dielectric passivation, the subthreshold slope was dramatically reduced from 9 V/decade to 0.9 V/decade by reducing interfacial trap sites, which then reduced the interface capacitance between the nanotube network and the gate dielectric.

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

Science.gov (United States)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

Poly(4-vinylphenol gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2016-03-01

Full Text Available A Microwave-Induction Heating (MIH scheme is proposed for the poly(4-vinylphenol (PVP gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

Single-Walled Carbon-Nanotubes-Based Organic Memory Structures

Directory of Open Access Journals (Sweden)

Sundes Fakher

2016-09-01

Full Text Available The electrical behaviour of organic memory structures, based on single-walled carbon-nanotubes (SWCNTs, metal–insulator–semiconductor (MIS and thin film transistor (TFT structures, using poly(methyl methacrylate (PMMA as the gate dielectric, are reported. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of SWCNTs, embedded within the insulating layer, were used as the floating gate. SWCNTs-based memory devices exhibited clear hysteresis in their electrical characteristics (capacitance–voltage (C–V for MIS structures, as well as output and transfer characteristics for transistors. Both structures were shown to produce reliable and large memory windows by virtue of high capacity and reduced charge leakage. The hysteresis in the output and transfer characteristics, the shifts in the threshold voltage of the transfer characteristics, and the flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the SWCNTs floating gate. Under an appropriate gate bias (1 s pulses, the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses as low as 1 V resulted in clear write and erase states.

High mobility polymer gated organic field effect transistor using zinc ...

Indian Academy of Sciences (India)

Organic thin film transistors were fabricated using evaporated zinc phthalocyanine as the active layer. Parylene film ... At room temperature, these transistors exhibit p-type conductivity with field-effect ... Keywords. Organic semiconductor; field effect transistor; phthalocyanine; high mobility. ... The evaporation rate was kept at ...

High-current and low acceleration voltage arsenic ion implanted polysilicon-gate and source-drain electrode Si mos transistor

International Nuclear Information System (INIS)

Saito, Yasuyuki; Sugimura, Yoshiro; Sugihara, Michiyuki

1993-01-01

The fabrication process of high current arsenic (As) ion implanted polysilicon (Si) gate and source drain (SD) electrode Si n-channel metal oxide-semiconductor field effect transistor (MOSFET) was examined. Poly Si film n-type doping was performed by using high current (typical current: 2mA) and relatively low acceleration voltage (40keV) As ion implantation technique (Lintott series 3). It was observed that high dose As implanted poly Si films as is show refractoriness against radical fluorine excited by microwave. Using GCA MANN4800 (m/c ID No.2, resist: OFPR) mask pattern printing technique, the high current As ion implantation technique and radical fluorine gas phase etching (Chemical dry etching: CDE) technique, the n-channel Poly Si gate (ρs = ≅100Ω/□) enhancement MQSFETs(ρs source drain = ≅50Ω/□, SiO 2 gate=380 angstrom) with off-leak-less were obtained on 3 inch Czochralski grown 2Ωcm boron doped p type wafers (Osaka titanium). By the same process, a 8 bit single chip μ-processor with 26MHz full operation was performed

Characterization of Screen-Printed Organic Electrochemical Transistors to Detect Cations of Different Sizes

Directory of Open Access Journals (Sweden)

Laura Contat-Rodrigo

2016-09-01

Full Text Available A novel screen-printing fabrication method was used to prepare organic electrochemical transistors (OECTs based on poly(3,4-ethylenedioxythiophene doped with polysterene sulfonate (PEDOT:PSS. Initially, three types of these screen-printed OECTs with a different channel and gate areas ratio were compared in terms of output characteristics, transfer characteristics, and current modulation in a phosphate buffered saline (PBS solution. Results confirm that transistors with a gate electrode larger than the channel exhibit higher modulation. OECTs with this geometry were therefore chosen to investigate their ion-sensitive properties in aqueous solutions of cations of different sizes (sodium and rhodamine B. The effect of the gate electrode was additionally studied by comparing these all-PEDOT:PSS transistors with OECTs with the same geometry but with a non-polarizable metal gate (Ag. The operation of the all-PEDOT:PSS OECTs yields a response that is not dependent on a Na+ or rhodamine concentration. The weak modulation of these transistors can be explained assuming that PEDOT:PSS behaves like a supercapacitor. In contrast, the operation of Ag-Gate OECTs yields a response that is dependent on ion concentration due to the redox reaction taking place at the gate electrode with Cl− counter-ions. This indicates that, for cation detection, the response is maximized in OECTs with non-polarizable gate electrodes.

Current Enhancement with Contact-Area-Limited Doping for Bottom-Gate, Bottom-Contact Organic Thin-Film Transistors

Science.gov (United States)

Noda, Kei; Wakatsuki, Yusuke; Yamagishi, Yuji; Wada, Yasuo; Toyabe, Toru; Matsushige, Kazumi

2013-02-01

The current enhancement mechanism in contact-area-limited doping for bottom-gate, bottom-contact (BGBC) p-channel organic thin-film transistors (OTFTs) was investigated both by simulation and experiment. Simulation results suggest that carrier shortage and large potential drop occur in the source-electrode/channel interface region in a conventional BGBC OTFT during operation, which results in a decrease in the effective field-effect mobility. These phenomena are attributed to the low carrier concentration of active semiconductor layers in OTFTs and can be alleviated by contact-area-limited doping, where highly doped layers are prepared over source-drain electrodes. According to two-dimensional current distribution obtained from the device simulation, a current flow from the source electrode to the channel region via highly doped layers is generated in addition to the direct carrier injection from the source electrode to the channel, leading to the enhancement of the drain current and effective field-effect mobility. The expected current enhancement mechanism in contact-area-limited doping was experimentally confirmed in typical α-sexithiophene (α-6T) BGBC thin-film transistors.

3D modeling of dual-gate FinFET.

Science.gov (United States)

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-13

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

Effect of gate length on breakdown voltage in AlGaN/GaN high-electron-mobility transistor

International Nuclear Information System (INIS)

Luo Jun; Zhao Sheng-Lei; Mi Min-Han; Zhang Jin-Cheng; Ma Xiao-Hua; Hao Yue; Chen Wei-Wei; Hou Bin

2016-01-01

The effects of gate length L G on breakdown voltage V BR are investigated in AlGaN/GaN high-electron-mobility transistors (HEMTs) with L G = 1 μm∼ 20 μm. With the increase of L G , V BR is first increased, and then saturated at L G = 3 μm. For the HEMT with L G = 1 μm, breakdown voltage V BR is 117 V, and it can be enhanced to 148 V for the HEMT with L G = 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage. A similar suppression of the impact ionization exists in the HEMTs with L G > 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with L G = 3 μm∼20 μm, and their breakdown voltages are in a range of 140 V–156 V. (paper)

A gate drive circuit for gate-turn-off (GTO) devices in series stack

International Nuclear Information System (INIS)

Despe, O.

1999-01-01

A gate-turn-off (GTO) switch is under development at the Advanced Photon Source as a replacement for a thyratron switch in high power pulsed application. The high voltage in the application requires multiple GTOs connected in series. One component that is critical to the success of GTO operation is the gate drive circuit. The gate drive circuit has to provide fast high-current pulses to the GTO gate for fast turn-on and turn-off. It also has to be able to operate while floating at high voltage. This paper describes a gate drive circuit that meets these requirements

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

Science.gov (United States)

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

International Nuclear Information System (INIS)

Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

2005-01-01

AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

pH sensor using AlGaN/GaN high electron mobility transistors with Sc2O3 in the gate region

International Nuclear Information System (INIS)

Kang, B. S.; Wang, H. T.; Ren, F.; Gila, B. P.; Abernathy, C. R.; Pearton, S. J.; Johnson, J. W.; Rajagopal, P.; Roberts, J. C.; Piner, E. L.; Linthicum, K. J.

2007-01-01

Ungated AlGaN/GaN high electron mobility transistors (HEMTs) exhibit large changes in current upon exposing the gate region to polar liquids. The polar nature of the electrolyte introduced leds to a change of surface charges, producing a change in surface potential at the semiconductor/liquid interface. The use of Sc 2 O 3 gate dielectric produced superior results to either a native oxide or UV ozone-induced oxide in the gate region. The ungated HEMTs with Sc 2 O 3 in the gate region exhibited a linear change in current between pH 3 and 10 of 37 μA/pH. The HEMT pH sensors show stable operation with a resolution of <0.1 pH over the entire pH range. The results indicate that the HEMTs may have application in monitoring pH solution changes between 7 and 8, the range of interest for testing human blood

Nano-CMOS gate dielectric engineering

CERN Document Server

Wong, Hei

2011-01-01

According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

Experimental study on gamma irradiation effects of floating gate ROMs The ROM is stated for Read-only Memory

CERN Document Server

He Chao Hui; Chen Xiao Hua; Wang Yan Ping; Peng Hong Lun

2002-01-01

Experimental results of gamma irradiation effects are given for Floating gate ROMs. There is an accumulated dose threshold. Errors occur when accumulated dose is above the threshold, no error occurs when below the threshold. The errors go up with the increase of the accumulated dose. Errors occur in devices that are measured during irradiation and irradiated in power on, moreover, new data cannot be written in these devices with programmer. However, under more accumulated dose, there is no error in devices in power off mode and new data can be written in these devices with programmer

Silicon nanowire transistors

CERN Document Server

Bindal, Ahmet

2016-01-01

This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

Paraffin wax passivation layer improvements in electrical characteristics of bottom gate amorphous indium–gallium–zinc oxide thin-film transistors

International Nuclear Information System (INIS)

Chang, Geng-Wei; Chang, Ting-Chang; Syu, Yong-En; Tsai, Tsung-Ming; Chang, Kuan-Chang; Tu, Chun-Hao; Jian, Fu-Yen; Hung, Ya-Chi; Tai, Ya-Hsiang

2011-01-01

In this research, paraffin wax is employed as the passivation layer of the bottom gate amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs), and it is formed by sol–gel process in the atmosphere. The high yield and low cost passivation layer of sol–gel process technology has attracted much attention for current flat-panel-display manufacturing. Comparing with passivation-free a-IGZO TFTs, passivated devices exhibit a superior stability against positive gate bias stress in different ambient gas, demonstrating that paraffin wax shows gas-resisting characteristics for a-IGZO TFTs application. Furthermore, light-induced stretch-out phenomenon for paraffin wax passivated device is suppressed. This superior stability of the passivated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities.

Four-gate transistor analog multiplier circuit

Science.gov (United States)

Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)

2011-01-01

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

Group IV nanotube transistors for next generation ubiquitous computing

KAUST Repository

Fahad, Hossain M.; Hussain, Aftab M.; Sevilla, Galo T.; Banerjee, Sanjay K.; Hussain, Muhammad Mustafa

2014-01-01

Evolution in transistor technology from increasingly large power consuming single gate planar devices to energy efficient multiple gate non-planar ultra-narrow (< 20 nm) fins has enhanced the scaling trend to facilitate doubling performance. However

Pseudo-diode based on protonic/electronic hybrid oxide transistor

Science.gov (United States)

Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

2018-01-01

Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

Science.gov (United States)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor

Kink effect and noise performance in isolated-gate InAs/AlSb high electron mobility transistors

International Nuclear Information System (INIS)

Vasallo, B G; González, T; Mateos, J; Rodilla, H; Moschetti, G; Grahn, J

2012-01-01

The kink effect can spoil the otherwise excellent low noise performance of InAs/AlSb high electron mobility transistors. It has its origin in the pile-up of holes (generated by impact ionization) taking place mainly at the drain side of the buffer, which leads to a reduction of the gate-induced channel depletion and results in a drain current enhancement. Our results indicate that the generation of holes by impact ionization and their further recombination lead to fluctuations in the charge of the hole pile-up, which provoke an important increase in the drain current noise, even when the kink effect is hardly perceptible in the output characteristics. (paper)

Resonant Tunneling in Gated Vertical One- dimensional Structures

Science.gov (United States)

Kolagunta, V. R.; Janes, D. B.; Melloch, M. R.; Webb, K. J.

1997-03-01

Vertical sub-micron transistors incorporating resonant tunneling multiple quantum well heterostructures are interesting in applications for both multi-valued logic devices and the study of quantization effects in vertical quasi- one-, zero- dimensional structures. Earlier we have demonstrated room temperature pinch-off of the resonant peak in sub-micron vertical resonant tunneling transistors structures using a self-aligned sidewall gating technique ( V.R. Kolagunta et. al., Applied Physics Lett., 69), 374(1996). In this paper we present the study of gating effects in vertical multiple quantum well resonant tunneling transistors. Multiple well quasi-1-D sidewall gated transistors with mesa dimensions of L_x=0.5-0.9μm and L_y=10-40μm were fabricated. The quantum heterostructure in these devices consists of two non-symmetric (180 ÅÅi-GaAs wells separated from each other and from the top and bottom n^+ GaAs/contacts region using Al_0.3Ga_0.7As tunneling barriers. Room temperature pinch-off of the multiple resonant peaks similar to that reported in the case of single well devices is observed in these devices^1. Current-voltage characteristics at liquid nitrogen temperatures show splitting of the resonant peaks into sub-bands with increasing negative gate bias indicative of quasi- 1-D confinement. Room-temperature and low-temperature current-voltage measurements shall be presented and discussed.

Pentacene based thin film transistors with high-k dielectric Nd2O3 as a gate insulator

International Nuclear Information System (INIS)

Sarma, R.; Saikia, D.

2010-01-01

We have investigated the pentacene based Organic Thin Film Transistors (OTFTs) with high-k dielectric Nd 2 O 3 . Use of high dielectric constant (high-k) gate insulator Nd 2 O 3 reduces the threshold voltage and sub threshold swing of the OTFTs. The calculated threshold voltage -2.2V and sub-threshold swing 1V/decade, current ON-OFF ratio is 1.7 X 10 4 and mobility is 0.13cm 2 /V.s. Pentacene film is deposited on Nd 2 O 3 surface using two step deposition method. Deposited pentacene film is found poly crystalline in nature. (author)

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

Science.gov (United States)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Investigations on field-effect transistors based on two-dimensional materials

Energy Technology Data Exchange (ETDEWEB)

Finge, T.; Riederer, F.; Grap, T.; Knoch, J. [Institute of Semiconductor Electronics, RWTH Aachen University (Germany); Mueller, M.R. [Institute of Semiconductor Electronics, RWTH Aachen University (Germany); Infineon Technologies, Villach (Austria); Kallis, K. [Intelligent Microsystems Chair, TU Dortmund University (Germany)

2017-11-15

In the present article, experimental and theoretical investigations regarding field-effect transistors based on two-dimensional (2D) materials are presented. First, the properties of contacts between a metal and 2D material are discussed. To this end, metal-to-graphene contacts as well to transition metal dichalcogenides (TMD) are studied. Whereas metal-graphene contacts can be tuned with an appropriate back-gate, metal-TMD contacts exhibit strong Fermi level pinning showing substantially limited maximum possible drive current. Next, tungsten diselenide (WSe{sub 2}) field-effect transistors are presented. Employing buried-triple-gate substrates allows tuning source, channel and drain by applying appropriate gate voltages so that the device can be reconfigured to work as n-type, p-type and as so-called band-to-band tunnel field-effect transistor on the same WSe{sub 2} flake. (copyright 2017 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

On theory of single-molecule transistor

International Nuclear Information System (INIS)

Tran Tien Phuc

2009-01-01

The results of the study on single-molecule transistor are mainly investigated in this paper. The structure of constructed single-molecule transistor is similar to a conventional MOSFET. The conductive channel of the transistors is a single-molecule of halogenated benzene derivatives. The chemical simulation software CAChe was used to design and implement for the essential parameter of the molecules utilized as the conductive channel. The GUI of Matlab has been built to design its graphical interface, calculate and plot the output I-V characteristic curves for the transistor. The influence of temperature, length and width of the conductive channel, and gate voltage is considered. As a result, the simulated curves are similar to the traditional MOSFET's. The operating temperature range of the transistors is wider compared with silicon semiconductors. The supply voltage for transistors is only about 1 V. The size of transistors in this research is several nanometers.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

Science.gov (United States)

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-12-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

Energy Technology Data Exchange (ETDEWEB)

Jo, Kwang-Won; Cho, Won-Ju, E-mail: chowj@kw.ac.kr [Department of Electronic Materials Engineering, Kwangwoon University, 447-1, Wolgye-dong, Nowon-gu, Seoul 139-701 (Korea, Republic of)

2014-11-24

In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S. [Department of Electrical and Computer Engineering, University of Waterloo, 200 University Avenue West, Waterloo, Ontario N2L 3G1 (Canada)

2015-07-13

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

International Nuclear Information System (INIS)

Jo, Kwang-Won; Cho, Won-Ju

2014-01-01

In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV ON ) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress

Electrical properties of ZnO-based bottom-gate thin film transistors fabricated by using radio frequency magnetron sputtering

Energy Technology Data Exchange (ETDEWEB)

Navamathavan, R. [Nano Thin Film Materials Laboratory, Department of Physics, Cheju National University, Jeju 690-756 (Korea, Republic of)], E-mail: n_mathavan@yahoo.com; Choi, Chi Kyu [Nano Thin Film Materials Laboratory, Department of Physics, Cheju National University, Jeju 690-756 (Korea, Republic of); Park, Seong-Ju [Nanophotonic Semiconductors Laboratory, Department of Materials Science and Engineering, Gwangju Institute of Science and Technology, Gwangju 500-712 (Korea, Republic of)

2009-05-05

We report on enhancement-mode thin film transistors (TFTs) using ZnO as an active channel layer deposited by radio frequency (rf) magnetron sputtering at 300 deg. C. The TFT structure consisted of ZnO as a channel, SiN{sub x} as a gate insulator and indium tin oxide (ITO) as a gate which were deposited onto a Corning glass substrate. X-ray diffraction pattern revealed that dense columnar structure of closely packed ZnO nano grains along the c-axis. The transfer characteristics of a typical ZnO TFT exhibited a field effect mobility of 31 cm{sup 2}/V s, a drain current on/off ratio of 10{sup 4}, the low off-current value in the order of 10{sup -10} A, and a threshold voltage of 1.7 V. The transparent ZnO TFT exhibited n-channel enhancement mode behavior.

Gate Control Coefficient Effect on CNFET Characteristic

International Nuclear Information System (INIS)

Sanudin, Rahmat; Ma'Radzi, Ahmad Alabqari; Nayan, Nafarizal

2009-01-01

The development of carbon nanotube field-effect transistor (CNFET) as alternative to existing transistor technology has long been published and discussed. The emergence of this device offers new material and structure in building a transistor. This paper intends to do an analysis of gate control coefficient effect on CNFET performance. The analysis is based on simulation study of current-voltage (I-V) characteristic of ballistic CNFET. The simulation study used the MOSFET-like CNFET mathematical model to establish the device output characteristic. Based on the analysis of simulation result, it is found that the gate control coefficient contributes to a significant effect on the performance of CNFET. The result also shown the parameter could help to improve the device performance in terms of its output and response as well. Nevertheless, the characteristic of the carbon nanotube that acts as the channel is totally important in determining the performance of the transistor as a whole.

Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

Directory of Open Access Journals (Sweden)

Qi Liu

2014-08-01

Full Text Available A novel high-κ organometallic lanthanide complex, Eu(tta3L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine, is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs. The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μFET of 0.17 cm2 V−1 s−1, threshold voltage (Vth of −0.9 V, on/off current ratio of 5 × 103, and subthreshold slope (SS of 1.0 V dec−1, which is much better than that of devices obtained on conventional 300 nm SiO2 substrate (0.13 cm2 V−1 s−1, −7.3 V and 3.1 V dec−1 for μFET, Vth and SS value when operated at −30 V. These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

Directory of Open Access Journals (Sweden)

Xiaojun Cheng

2014-05-01

Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

Scaling the Serialization of MOSFETs by Magnetically Coupling Their Gate Electrodes

DEFF Research Database (Denmark)

Dimopoulos, Emmanouil; Munk-Nielsen, Stig

2013-01-01

More than twenty years of thorough research on the serialization of power semiconductor switches, like the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or the Insulated Gate Bipolar Transistor (IGBT), have resulted into several different stacking concepts; all aiming towards...... the establishment of a high-efficient, high-voltage, fast-switching device. Among the prevailing stacking approaches lies the gate balancing core technique, which, in its initial form, demonstrated very good performance in strings of high-power IGBT modules, by magnetically coupling their gate electrodes. Recently...

High performance top-gated ferroelectric field effect transistors based on two-dimensional ZnO nanosheets

Science.gov (United States)

Tian, Hongzheng; Wang, Xudong; Zhu, Yuankun; Liao, Lei; Wang, Xianying; Wang, Jianlu; Hu, Weida

2017-01-01

High quality ultrathin two-dimensional zinc oxide (ZnO) nanosheets (NSs) are synthesized, and the ZnO NS ferroelectric field effect transistors (FeFETs) are demonstrated based on the P(VDF-TrFE) polymer film used as the top gate insulating layer. The ZnO NSs exhibit a maximum field effect mobility of 588.9 cm2/Vs and a large transconductance of 2.5 μS due to their high crystalline quality and ultrathin two-dimensional structure. The polarization property of the P(VDF-TrFE) film is studied, and a remnant polarization of >100 μC/cm2 is achieved with a P(VDF-TrFE) thickness of 300 nm. Because of the ultrahigh remnant polarization field generated in the P(VDF-TrFE) film, the FeFETs show a large memory window of 16.9 V and a high source-drain on/off current ratio of more than 107 at zero gate voltage and a source-drain bias of 0.1 V. Furthermore, a retention time of >3000 s of the polarization state is obtained, inspiring a promising candidate for applications in data storage with non-volatile features.

Self-Aligned van der Waals Heterojunction Diodes and Transistors.

Science.gov (United States)

Sangwan, Vinod K; Beck, Megan E; Henning, Alex; Luo, Jiajia; Bergeron, Hadallia; Kang, Junmo; Balla, Itamar; Inbar, Hadass; Lauhon, Lincoln J; Hersam, Mark C

2018-02-14

A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS 2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of antiambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated antiambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries. For example, the versatility of this scheme is demonstrated via contact-doped MoS 2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150-800 nm using photolithography on large-area MoS 2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step toward the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems.

Highly stable thin film transistors using multilayer channel structure

KAUST Repository

Nayak, Pradipta K.; Wang, Zhenwei; Anjum, Dalaver H.; Hedhili, Mohamed N.; Alshareef, Husam N.

2015-01-01

We report highly stable gate-bias stress performance of thin film transistors (TFTs) using zinc oxide (ZnO)/hafnium oxide (HfO2) multilayer structure as the channel layer. Positive and negative gate-bias stress stability of the TFTs was measured

Junctionless Cooper pair transistor

Energy Technology Data Exchange (ETDEWEB)

Arutyunov, K. Yu., E-mail: konstantin.yu.arutyunov@jyu.fi [National Research University Higher School of Economics , Moscow Institute of Electronics and Mathematics, 101000 Moscow (Russian Federation); P.L. Kapitza Institute for Physical Problems RAS , Moscow 119334 (Russian Federation); Lehtinen, J.S. [VTT Technical Research Centre of Finland Ltd., Centre for Metrology MIKES, P.O. Box 1000, FI-02044 VTT (Finland)

2017-02-15

Highlights: • Junctionless Cooper pair box. • Quantum phase slips. • Coulomb blockade and gate modulation of the Coulomb gap. - Abstract: Quantum phase slip (QPS) is the topological singularity of the complex order parameter of a quasi-one-dimensional superconductor: momentary zeroing of the modulus and simultaneous 'slip' of the phase by ±2π. The QPS event(s) are the dynamic equivalent of tunneling through a conventional Josephson junction containing static in space and time weak link(s). Here we demonstrate the operation of a superconducting single electron transistor (Cooper pair transistor) without any tunnel junctions. Instead a pair of thin superconducting titanium wires in QPS regime was used. The current–voltage characteristics demonstrate the clear Coulomb blockade with magnitude of the Coulomb gap modulated by the gate potential. The Coulomb blockade disappears above the critical temperature, and at low temperatures can be suppressed by strong magnetic field.

Molecular doping for control of gate bias stress in organic thin film transistors

Energy Technology Data Exchange (ETDEWEB)

Hein, Moritz P., E-mail: hein@iapp.de; Lüssem, Björn; Jankowski, Jens; Tietze, Max L.; Riede, Moritz K. [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany); Zakhidov, Alexander A. [Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany); Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Straße 1, 01069 Dresden (Germany); Fraunhofer COMEDD, Maria-Reiche-Str. 2, 01109 Dresden (Germany)

2014-01-06

The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface.

Molecular doping for control of gate bias stress in organic thin film transistors

International Nuclear Information System (INIS)

Hein, Moritz P.; Lüssem, Björn; Jankowski, Jens; Tietze, Max L.; Riede, Moritz K.; Zakhidov, Alexander A.; Leo, Karl

2014-01-01

The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface

Organic tunnel field effect transistors

KAUST Repository

Tietze, Max Lutz; Lussem, Bjorn; Liu, Shiyi

2017-01-01

Various examples are provided for organic tunnel field effect transistors (OTFET), and methods thereof. In one example, an OTFET includes a first intrinsic layer (i-layer) of organic semiconductor material disposed over a gate insulating layer

Controlling the dimensionality of charge transport in organic thin-film transistors

Science.gov (United States)

Laiho, Ari; Herlogsson, Lars; Forchheimer, Robert; Crispin, Xavier; Berggren, Magnus

2011-01-01

Electrolyte-gated organic thin-film transistors (OTFTs) can offer a feasible platform for future flexible, large-area and low-cost electronic applications. These transistors can be divided into two groups on the basis of their operation mechanism: (i) field-effect transistors that switch fast but carry much less current than (ii) the electrochemical transistors which, on the contrary, switch slowly. An attractive approach would be to combine the benefits of the field-effect and the electrochemical transistors into one transistor that would both switch fast and carry high current densities. Here we report the development of a polyelectrolyte-gated OTFT based on conjugated polyelectrolytes, and we demonstrate that the OTFTs can be controllably operated either in the field-effect or the electrochemical regime. Moreover, we show that the extent of electrochemical doping can be restricted to a few monolayers of the conjugated polyelectrolyte film, which allows both high current densities and fast switching speeds at the same time. We propose an operation mechanism based on self-doping of the conjugated polyelectrolyte backbone by its ionic side groups. PMID:21876143

Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

International Nuclear Information System (INIS)

Katsuno, Takashi; Ishikawa, Tsuyoshi; Ueda, Hiroyuki; Uesugi, Tsutomu; Manaka, Takaaki; Iwamoto, Mitsumasa

2014-01-01

Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800 μs) the completion of drain-stress voltage (200 V) in the off-state, the second-harmonic (SH) signals appeared within 2 μm from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

International Nuclear Information System (INIS)

Takano, H.; Hosogi, K.; Kato, T.

1995-01-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs

Outlook and emerging semiconducting materials for ambipolar transistors.

Science.gov (United States)

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electro-Thermo-Mechanical Analysis of High-Power Press-Pack Insulated Gate Bipolar Transistors under Various Mechanical Clamping Conditions

DEFF Research Database (Denmark)

Hasmasan, Adrian Augustin; Busca, Cristian; Teodorescu, Remus

2014-01-01

With the continuously increasing demand for energy and the limited supply of fossil fuels, renewable power sources are becoming ever more important. Knowing that future energy demand will grow, manufacturers are increasing the size of new wind turbines (WTs) in order to reduce the cost of energy...... production. The reliability of the components has a large impact on the overall cost of a WT, and press-pack (PP) insulated gate bipolar transistors (IGBTs) could be a good solution for future multi-megawatt WTs because of advantages like high power density and reliability. When used in power converters, PP...

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

Institute of Scientific and Technical Information of China (English)

潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

2011-01-01

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95％ active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

Electrochemical Single-Molecule Transistors with Optimized Gate Coupling

DEFF Research Database (Denmark)

Osorio, Henrry M.; Catarelli, Samantha; Cea, Pilar

2015-01-01

Electrochemical gating at the single molecule level of viologen molecular bridges in ionic liquids is examined. Contrary to previous data recorded in aqueous electrolytes, a clear and sharp peak in the single molecule conductance versus electrochemical potential data is obtained in ionic liquids....... These data are rationalized in terms of a two-step electrochemical model for charge transport across the redox bridge. In this model the gate coupling in the ionic liquid is found to be fully effective with a modeled gate coupling parameter, ξ, of unity. This compares to a much lower gate coupling parameter...

Schottky barrier diode embedded AlGaN/GaN switching transistor

International Nuclear Information System (INIS)

Park, Bong-Ryeol; Lee, Jung-Yeon; Lee, Jae-Gil; Lee, Dong-Myung; Cha, Ho-Young; Kim, Moon-Kyung

2013-01-01

We developed a Schottky barrier diode (SBD) embedded AlGaN/GaN switching transistor to allow negative current flow during off-state condition. An SBD was embedded in a recessed normally-off AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistor (MOSHFET). The fabricated device exhibited normally-off characteristics with a gate threshold voltage of 2.8 V, a diode turn-on voltage of 1.2 V, and a breakdown voltage of 849 V for the anode-to-drain distance of 8 µm. An on-resistance of 2.66 mΩcm 2 was achieved at a gate voltage of 16 V in the forward transistor mode. Eliminating the need for an external diode, the SBD embedded switching transistor has advantages of significant reduction in parasitic inductance and chip area. (paper)

An All-Solid-State pH Sensor Employing Fluorine-Terminated Polycrystalline Boron-Doped Diamond as a pH-Insensitive Solution-Gate Field-Effect Transistor.

Science.gov (United States)

Shintani, Yukihiro; Kobayashi, Mikinori; Kawarada, Hiroshi

2017-05-05

A fluorine-terminated polycrystalline boron-doped diamond surface is successfully employed as a pH-insensitive SGFET (solution-gate field-effect transistor) for an all-solid-state pH sensor. The fluorinated polycrystalline boron-doped diamond (BDD) channel possesses a pH-insensitivity of less than 3mV/pH compared with a pH-sensitive oxygenated channel. With differential FET (field-effect transistor) sensing, a sensitivity of 27 mv/pH was obtained in the pH range of 2-10; therefore, it demonstrated excellent performance for an all-solid-state pH sensor with a pH-sensitive oxygen-terminated polycrystalline BDD SGFET and a platinum quasi-reference electrode, respectively.

Improved transfer of graphene for gated Schottky-junction, vertical, organic, field-effect transistors.

Science.gov (United States)

Lemaitre, Maxime G; Donoghue, Evan P; McCarthy, Mitchell A; Liu, Bo; Tongay, Sefaattin; Gila, Brent; Kumar, Purushottam; Singh, Rajiv K; Appleton, Bill R; Rinzler, Andrew G

2012-10-23

An improved process for graphene transfer was used to demonstrate high performance graphene enabled vertical organic field effect transistors (G-VFETs). The process reduces disorder and eliminates the polymeric residue that typically plagues transferred films. The method also allows for purposely creating pores in the graphene of a controlled areal density. Transconductance observed in G-VFETs fabricated with a continuous (pore-free) graphene source electrode is attributed to modulation of the contact barrier height between the graphene and organic semiconductor due to a gate field induced Fermi level shift in the low density of electronic-states graphene electrode. Pores introduced in the graphene source electrode are shown to boost the G-VFET performance, which scales with the areal pore density taking advantage of both barrier height lowering and tunnel barrier thinning. Devices with areal pore densities of 20% exhibit on/off ratios and output current densities exceeding 10(6) and 200 mA/cm(2), respectively, at drain voltages below 5 V.

Low-Temperature Solution-Processed Gate Dielectrics for High-Performance Organic Thin Film Transistors

Directory of Open Access Journals (Sweden)

Jaekyun Kim

2015-10-01

Full Text Available A low-temperature solution-processed high-k gate dielectric layer for use in a high-performance solution-processed semiconducting polymer organic thin-film transistor (OTFT was demonstrated. Photochemical activation of sol-gel-derived AlOx films under 150 °C permitted the formation of a dense film with low leakage and relatively high dielectric-permittivity characteristics, which are almost comparable to the results yielded by the conventionally used vacuum deposition and high temperature annealing method. Octadecylphosphonic acid (ODPA self-assembled monolayer (SAM treatment of the AlOx was employed in order to realize high-performance (>0.4 cm2/Vs saturation mobility and low-operation-voltage (<5 V diketopyrrolopyrrole (DPP-based OTFTs on an ultra-thin polyimide film (3-μm thick. Thus, low-temperature photochemically-annealed solution-processed AlOx film with SAM layer is an attractive candidate as a dielectric-layer for use in high-performance organic TFTs operated at low voltages.

Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress

International Nuclear Information System (INIS)

Hsieh, Tien-Yu; Chang, Ting-Chang; Chen, Te-Chih; Tsai, Ming-Yen; Chen, Yu-Te

2013-01-01

This paper investigates the degradation mechanism of amorphous InGaZnO thin-film transistors under DC and AC gate bias stress. Comparing the degradation behavior at equal accumulated effective stress time, more pronounced threshold voltage shift under AC positive gate bias stress in comparison with DC stress indicates extra electron-trapping phenomenon that occurs in the duration of rising/falling time in pulse. Contrarily, illuminated AC negative gate bias stress exhibits much less threshold voltage shift than DC stress, suggesting that the photo-generated hole does not have sufficient time to drift to the interface of IGZO/gate insulator and causes hole-trapping under AC operation. Since the evolution of threshold voltage fits the stretched-exponential equation well, the different degradation tendencies under DC/AC stress can be attributed to the different electron- and hole-trapping efficiencies, and this is further verified by varying pulse waveform. - Highlights: ► Static and dynamic gate bias stresses are imposed on InGaZnO TFTs. ► Dynamic positive gate bias induces more pronounced threshold voltage shift. ► Static negative-bias illumination stress induces more severe threshold voltage shift. ► Evolution of threshold voltage fits the stretched-exponential equation well

Bimodal gate-dielectric deposition for improved performance of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

International Nuclear Information System (INIS)

Pang Liang; Kim, Kyekyoon

2012-01-01

A bimodal deposition scheme combining radiofrequency magnetron sputtering and plasma enhanced chemical vapour deposition (PECVD) is proposed as a means for improving the performance of GaN-based metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs). High-density sputtered-SiO 2 is utilized to reduce the gate leakage current and enhance the breakdown voltage while low-density PECVD-SiO 2 is employed to buffer the sputtering damage and further increase the drain current by engineering the stress-induced-polarization. Thus-fabricated MOSHEMT exhibited a low leakage current of 4.21 × 10 -9 A mm -1 and high breakdown voltage of 634 V for a gate-drain distance of 6 µm, demonstrating the promise of bimodal-SiO 2 deposition scheme for the development of GaN-based MOSHEMTs for high-power application. (paper)

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors.

Science.gov (United States)

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-12-11

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption.

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors

Science.gov (United States)

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-01-01

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption. PMID:26656113

Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

Energy Technology Data Exchange (ETDEWEB)

Liu, Qi; Li, Yi; Zhang, Yang; Song, You, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Wang, Xizhang, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Hu, Zheng [Key Laboratory of Mesoscopic Chemistry of MOE, Jiangsu Provincial Lab for Nanotechnology, School of Chemistry and Chemical Engineering, Nanjing University, Nanjing 210093, China. High-Tech Research Institute of Nanjing University (Suzhou), Suzhou 215123 (China); Sun, Huabin; Li, Yun, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Shi, Yi [School of Electronic Science and Engineering and Jiangsu Provincial Key Laboratory of Photonic and Electronic Materials, Nanjing University, Nanjing 210093 (China)

2014-08-15

A novel high-κ organometallic lanthanide complex, Eu(tta){sub 3}L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine), is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs). The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μ{sub FET}) of 0.17 cm{sup 2} V{sup −1} s{sup −1}, threshold voltage (V{sub th}) of −0.9 V, on/off current ratio of 5 × 10{sup 3}, and subthreshold slope (SS) of 1.0 V dec{sup −1}, which is much better than that of devices obtained on conventional 300 nm SiO{sub 2} substrate (0.13 cm{sup 2} V{sup −1} s{sup −1}, −7.3 V and 3.1 V dec{sup −1} for μ{sub FET}, V{sub th} and SS value when operated at −30 V). These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

pH sensing characteristics and biosensing application of solution-gated reduced graphene oxide field-effect transistors.

Science.gov (United States)

Sohn, Il-Yung; Kim, Duck-Jin; Jung, Jin-Heak; Yoon, Ok Ja; Thanh, Tien Nguyen; Quang, Trung Tran; Lee, Nae-Eung

2013-07-15

Solution-gated reduced graphene oxide field-effect transistors (R-GO FETs) were investigated for pH sensing and biochemical sensing applications. A channel of a networked R-GO film formed by self-assembly was incorporated as a sensing layer into a solution-gated FET structure for pH sensing and the detection of acetylcholine (Ach), which is a neurotransmitter in the nerve system, through enzymatic reactions. The fabricated R-GO FET was sensitive to protons (H(+)) with a pH sensitivity of 29 mV/pH in terms of the shift of the charge neutrality point (CNP), which is attributed to changes in the surface potential caused by the interaction of protons with OH surface functional groups present on the R-GO surface. The R-GO FET immobilized with acetylcholinesterase (AchE) was used to detect Ach in the concentration range of 0.1-10mM by sensing protons generated during the enzymatic reactions. The results indicate that R-GO FETs provide the capability to detect protons, demonstrating their applicability as a biosensing device for enzymatic reactions. Copyright © 2013 Elsevier B.V. All rights reserved.

Proton conducting sodium alginate electrolyte laterally coupled low-voltage oxide-based transistors

Energy Technology Data Exchange (ETDEWEB)

Liu, Yang Hui; Wan, Qing, E-mail: wanqing@nju.edu.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China); Qiang Zhu, Li, E-mail: lqzhu@nimte.ac.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Shi, Yi [School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China)

2014-03-31

Solution-processed sodium alginate electrolyte film shows a high proton conductivity of ∼5.5 × 10{sup −3} S/cm and a high lateral electric-double-layer (EDL) capacitance of ∼2.0 μF/cm{sup 2} at room temperature with a relative humidity of 57%. Low-voltage in-plane-gate indium-zinc-oxide-based EDL transistors laterally gated by sodium alginate electrolytes are fabricated on glass substrates. The field-effect mobility, current ON/OFF ratio, and subthreshold swing of such EDL transistors are estimated to be 4.2 cm{sup 2} V{sup −1} s{sup −1}, 2.8 × 10{sup 6}, and 130 mV/decade, respectively. At last, a low-voltage driven resistor-load inverter is also demonstrated. Such in-plane-gate EDL transistors have potential applications in portable electronics and low-cost biosensors.

Analysing organic transistors based on interface approximation

International Nuclear Information System (INIS)

Akiyama, Yuto; Mori, Takehiko

2014-01-01

Temperature-dependent characteristics of organic transistors are analysed thoroughly using interface approximation. In contrast to amorphous silicon transistors, it is characteristic of organic transistors that the accumulation layer is concentrated on the first monolayer, and it is appropriate to consider interface charge rather than band bending. On the basis of this model, observed characteristics of hexamethylenetetrathiafulvalene (HMTTF) and dibenzotetrathiafulvalene (DBTTF) transistors with various surface treatments are analysed, and the trap distribution is extracted. In turn, starting from a simple exponential distribution, we can reproduce the temperature-dependent transistor characteristics as well as the gate voltage dependence of the activation energy, so we can investigate various aspects of organic transistors self-consistently under the interface approximation. Small deviation from such an ideal transistor operation is discussed assuming the presence of an energetically discrete trap level, which leads to a hump in the transfer characteristics. The contact resistance is estimated by measuring the transfer characteristics up to the linear region

Near-thermal limit gating in heavily doped III-V semiconductor nanowires using polymer electrolytes

Science.gov (United States)

Ullah, A. R.; Carrad, D. J.; Krogstrup, P.; Nygârd, J.; Micolich, A. P.

2018-02-01

Doping is a common route to reducing nanowire transistor on-resistance but it has limits. A high doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even when the Be doping in our GaAs nanowires is so high that traditional metal-oxide gates fail. In this regime we obtain a combination of subthreshold swing and contact resistance that surpasses the best existing p -type nanowire metal-oxide semiconductor field-effect transistors (MOSFETs). Our subthreshold swing of 75 mV/dec is within 25 % of the room-temperature thermal limit and comparable with n -InP and n -GaAs nanowire MOSFETs. Our results open a new path to extending the performance and application of nanowire transistors, and motivate further work on improved solid electrolytes for nanoscale device applications.

Optical Co-Incidence Gate | Srinivasulu | African Journal of Science ...

African Journals Online (AJOL)

The paper explains Optical co-incidence gate, realized using Unijunction transistors (UJT), Light emitting diodes (LED) and Photo-resistors (LDR), which works on 1.8Vdc instead of 3Vdc. The power dissipation of the designed gate is only 3 mW. This optical gate finds application in the field of Mechatronics, Instrumentation ...

Research on total-dose hardening for H-gate PD NMOSFET/SIMOX by ion implanting into buried oxide

International Nuclear Information System (INIS)

Qian Cong; Zhang Zhengxuan; Zhang Feng; Lin Chenglu

2008-01-01

In this work, we investigate the back-gate I-V characteristics for two kinds of NMOSFET/SIMOX transistors with H gate structure fabricated on two different SOI wafers. A transistors are made on the wafer implanted with Si + and then annealed in N 2 , and B transistors are made on the wafer without implantation and annealing. It is demonstrated experimentally that A transistors have much less back-gate threshold voltage shift ΔV th than B transistors under X-ray total close irradiation. Subthreshold charge separation technique is employed to estimate the build-up of oxide charge and interface traps during irradiation, showing that the reduced ΔV th for A transistors is mainly due to its less build-up of oxide charge than B transistors. Photo-luminescence (PL) research indicates that Si implantation results in the formation of silicon nanocrystalline (nanocluster) whose size increases with the implant dose. This structure can trap electrons to compensate the positive charge build-up in the buried oxide during irradiation, and thus reduce the threshold voltage negative shift. (authors)

Extended-gate field-effect transistor (EG-FET) with molecularly imprinted polymer (MIP) film for selective inosine determination.

Science.gov (United States)

Iskierko, Zofia; Sosnowska, Marta; Sharma, Piyush Sindhu; Benincori, Tiziana; D'Souza, Francis; Kaminska, Izabela; Fronc, Krzysztof; Noworyta, Krzysztof

2015-12-15

A novel recognition unit of chemical sensor for selective determination of the inosine, renal disfunction biomarker, was devised and prepared. For that purpose, inosine-templated molecularly imprinted polymer (MIP) film was deposited on an extended-gate field-effect transistor (EG-FET) signal transducing unit. The MIP film was prepared by electrochemical polymerization of bis(bithiophene) derivatives bearing cytosine and boronic acid substituents, in the presence of the inosine template and a thiophene cross-linker. After MIP film deposition, the template was removed, and was confirmed by UV-visible spectroscopy. Subsequently, the film composition was characterized by spectroscopic techniques, and its morphology and thickness were determined by AFM. The finally MIP film-coated extended-gate field-effect transistor (EG-FET) was used for signal transduction. This combination is not widely studied in the literature, despite the fact that it allows for facile integration of electrodeposited MIP film with FET transducer. The linear dynamic concentration range of the chemosensor was 0.5-50 μM with inosine detectability of 0.62 μM. The obtained detectability compares well to the levels of the inosine in body fluids which are in the range 0-2.9 µM for patients with diagnosed diabetic nephropathy, gout or hyperuricemia, and can reach 25 µM in certain cases. The imprinting factor for inosine, determined from piezomicrogravimetric experiments with use of the MIP film-coated quartz crystal resonator, was found to be 5.5. Higher selectivity for inosine with respect to common interferents was also achieved with the present molecularly engineered sensing element. The obtained analytical parameters of the devised chemosensor allow for its use for practical sample measurements. Copyright © 2015 Elsevier B.V. All rights reserved.

Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

Science.gov (United States)

Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

2005-04-01

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Chemical-free n-type and p-type multilayer-graphene transistors

Energy Technology Data Exchange (ETDEWEB)

Dissanayake, D. M. N. M., E-mail: nandithad@voxtel-inc.com [Voxtel Inc, Lockey Laboratories, University of Oregon, Eugene Oregon 97402 (United States); Eisaman, M. D. [Sustainable Energy Technologies Department, Brookhaven National Laboratory, Upton, New York 11973 (United States); Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, New York 11794 (United States); Department of Physics and Astronomy, Stony Brook University, Stony Brook, New York 11794 (United States)

2016-08-01

A single-step doping method to fabricate n- and p-type multilayer graphene (MG) top-gate field effect transistors (GFETs) is demonstrated. The transistors are fabricated on soda-lime glass substrates, with the n-type doping of MG caused by the sodium in the substrate without the addition of external chemicals. Placing a hydrogen silsesquioxane (HSQ) barrier layer between the MG and the substrate blocks the n-doping, resulting in p-type doping of the MG above regions patterned with HSQ. The HSQ is deposited in a single fabrication step using electron beam lithography, allowing the patterning of arbitrary sub-micron spatial patterns of n- and p-type doping. When a MG channel is deposited partially on the barrier and partially on the glass substrate, a p-type and n-type doping profile is created, which is used for fabricating complementary transistors pairs. Unlike chemically doped GFETs in which the external dopants are typically introduced from the top, these substrate doped GFETs allow for a top gate which gives a stronger electrostatic coupling to the channel, reducing the operating gate bias. Overall, this method enables scalable fabrication of n- and p-type complementary top-gated GFETs with high spatial resolution for graphene microelectronic applications.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

Directory of Open Access Journals (Sweden)

Nandu B Chaure, Andrew N Cammidge, Isabelle Chambrier, Michael J Cook, Markys G Cain, Craig E Murphy, Chandana Pal and Asim K Ray

2011-01-01

Full Text Available Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl copper phthalocyanine (CuPc6 were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO2 as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS resulted in values of 4×10−2 cm2 V−1 s−1 and 106 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

Energy Technology Data Exchange (ETDEWEB)

Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio [Consiglio Nazionale delle Ricerche-Istituto per la Microelettronica e Microsistemi (CNR-IMM), Strada VIII 5, Zona Industriale 95121 Catania (Italy)

2016-07-04

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{sup 11} cm{sup −2}).

Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

International Nuclear Information System (INIS)

Miyoshi, Makoto; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi; Mizuno, Masaya; Soga, Tetsuo

2015-01-01

Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO 2 /Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO 2 /Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO 2 /Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm 2 /V s for electrons and 880 cm 2 /V s for holes, respectively

Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Miyoshi, Makoto, E-mail: miyoshi.makoto@nitech.ac.jp; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Mizuno, Masaya [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Soga, Tetsuo [Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan)

2015-08-17

Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO{sub 2}/Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO{sub 2}/Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO{sub 2}/Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm{sup 2}/V s for electrons and 880 cm{sup 2}/V s for holes, respectively.

Analyzing Single-Event Gate Ruptures In Power MOSFET's

Science.gov (United States)

Zoutendyk, John A.

1993-01-01

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

Drain current enhancement induced by hole injection from gate of 600-V-class normally off gate injection transistor under high temperature conditions up to 200 °C

Science.gov (United States)

Ishii, Hajime; Ueno, Hiroaki; Ueda, Tetsuzo; Endoh, Tetsuo

2018-06-01

In this paper, the current–voltage (I–V) characteristics of a 600-V-class normally off GaN gate injection transistor (GIT) from 25 to 200 °C are analyzed, and it is revealed that the drain current of the GIT increases during high-temperature operation. It is found that the maximum drain current (I dmax) of the GIT is 86% higher than that of a conventional 600-V-class normally off GaN metal insulator semiconductor hetero-FET (MIS-HFET) at 150 °C, whereas the GIT obtains 56% I dmax even at 200 °C. Moreover, the mechanism of the drain current increase of the GIT is clarified by examining the relationship between the temperature dependence of the I–V characteristics of the GIT and the gate hole injection effect determined from the shift of the second transconductance (g m) peak of the g m–V g characteristic. From the above, the GIT is a promising device with enough drivability for future power switching applications even under high-temperature conditions.

Pentacene thin-film transistors and inverters with plasma-enhanced atomic-layer-deposited Al2O3 gate dielectric

International Nuclear Information System (INIS)

Koo, Jae Bon; Lim, Jung Wook; Kim, Seong Hyun; Yun, Sun Jin; Ku, Chan Hoe; Lim, Sang Chul; Lee, Jung Hun

2007-01-01

The performances of pentacene thin-film transistor with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al 2 O 3 dielectric are reported. Saturation mobility of 0.38 cm 2 /V s, threshold voltage of 1 V, subthreshold swing of 0.6 V/decade, and on/off current ratio of about 10 8 have been obtained. Both depletion and enhancement mode inverter have been realized with the change of treatment method of hexamethyldisilazane on PEALD Al 2 O 3 gate dielectric. Full swing depletion mode inverter has been demonstrated at input voltages ranging from 5 V to - 5 V at supply voltage of - 5 V

Uniformity of fully gravure printed organic field-effect transistors

International Nuclear Information System (INIS)

Hambsch, M.; Reuter, K.; Stanel, M.; Schmidt, G.; Kempa, H.; Fuegmann, U.; Hahn, U.; Huebler, A.C.

2010-01-01

Fully mass-printed organic field-effect transistors were made completely by means of gravure printing. Therefore a special printing layout was developed in order to avoid register problems in print direction. Upon using this layout, contact pads for source-drain electrodes of the transistors are printed together with the gate electrodes in one and the same printing run. More than 50,000 transistors have been produced and by random tests a yield of approximately 75% has been determined. The principle suitability of the gravure printed transistors for integrated circuits has been shown by the realization of ring oscillators.

Current-Induced Transistor Sensorics with Electrogenic Cells

Directory of Open Access Journals (Sweden)

Peter Fromherz

2016-04-01

Full Text Available The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned.

Subthreshold currents in CMOS transistors made on oxygen-implanted silicon

International Nuclear Information System (INIS)

Foster, D.J.

1983-01-01

Kinks have been observed in subthreshold current plots of mesa-shaped n-channel transistors made on oxygen-implanted silicon substrates. The kinks represent additional current flow and are due to overlapping fields from the gate electrode causing early corner inversion and to a Qsub(ss) side-wall effect. Subthreshold currents in n-channel transistors are dominated by the two effects which, as a consequence, reduce threshold voltages especially in narrow n-channel transistors. The subthreshold characteristics of p-channel transistors were not affected in the same way. (author)

Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

International Nuclear Information System (INIS)

Lin, Ray-Ming; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

2013-01-01

In this study, the rare earth erbium oxide (Er 2 O 3 ) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t ) of the MOS–HEMT were 125 mV/decade and 4.3 × 10 12 cm −2 , respectively. The dielectric constant of the Er 2 O 3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er 2 O 3 MOS–HEMT. - Highlights: ► GaN/AlGaN/Er 2 O 3 metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er 2 O 3 with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I ON /I OFF ratio

Copper atomic-scale transistors.

Science.gov (United States)

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

SWNT array resonant gate MOS transistor.

Science.gov (United States)

Arun, A; Campidelli, S; Filoramo, A; Derycke, V; Salet, P; Ionescu, A M; Goffman, M F

2011-02-04

We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

SWNT array resonant gate MOS transistor

International Nuclear Information System (INIS)

Arun, A; Salet, P; Ionescu, A M; Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F

2011-01-01

We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

High Sensitivity pH Sensor Based on Porous Silicon (PSi) Extended Gate Field-Effect Transistor.

Science.gov (United States)

Al-Hardan, Naif H; Abdul Hamid, Muhammad Azmi; Ahmed, Naser M; Jalar, Azman; Shamsudin, Roslinda; Othman, Norinsan Kamil; Kar Keng, Lim; Chiu, Weesiong; Al-Rawi, Hamzah N

2016-06-07

In this study, porous silicon (PSi) was prepared and tested as an extended gate field-effect transistor (EGFET) for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

Electrically controlled wire-channel GaN/AlGaN transistor for terahertz plasma applications

Science.gov (United States)

Cywiński, G.; Yahniuk, I.; Kruszewski, P.; Grabowski, M.; Nowakowski-Szkudlarek, K.; Prystawko, P.; Sai, P.; Knap, W.; Simin, G. S.; Rumyantsev, S. L.

2018-03-01

We report on a design of fin-shaped channel GaN/AlGaN field-effect transistors developed for studying resonant terahertz plasma oscillations. Unlike common two dimensional FinFET transistor design, the gates were deposited only to the sides of the two dimensional electron gas channel, i.e., metal layers were not deposited on the top of the AlGaN. This side gate configuration allowed us to electrically control the conductivity of the channel by changing its width while keeping the carrier density and mobility virtually unchanged. Computer simulations and analytical model describe well the general shape of the characteristics. The side gate control of the channel width of these transistors allowed us to eliminate the so-called oblique plasma wave modes and paves the way towards future terahertz detectors and emitters using high quality factor plasma wave resonances.

Bias stress effect and recovery in organic field effect transistors : proton migration mechanism

NARCIS (Netherlands)

Sharma, A.; Mathijssen, S.G.J.; Kemerink, M.; Leeuw, de D.M.; Bobbert, P.A.; Bao, Z.; McCulloch, I.

2010-01-01

Organic field-effect transistors exhibit operational instabilities when a gate bias is applied. For a constant gate bias the threshold voltage shifts towards the applied gate bias voltage, an effect known as the bias-stress effect. We have performed a detailed experimental and theoretical study of

Colour tuneable light-emitting transistor

Energy Technology Data Exchange (ETDEWEB)

Feldmeier, Eva J.; Melzer, Christian; Seggern, Heinz von [Electronic Materials Department, Institute of Materials Science, Technische Universitaet Darmstadt (Germany)

2010-07-01

In recent years the interest in ambipolar organic light-emitting field-effect transistors has increased steadily as the devices combine switching behaviour of transistors with light emission. Usually, small molecules and polymers with a band gap in the visible spectral range serve as semiconducting materials. Mandatory remain balanced injection and transport properties for both charge carrier types to provide full control of the spatial position of the recombination zone of electrons and holes in the transistor channel via the applied voltages. As will be presented here, the spatial control of the recombination zone opens new possibilities towards light-emitting devices with colour tuneable emission. In our contribution an organic light-emitting field-effect transistors is presented whose emission colour can be changed by the applied voltages. The organic top-contact field-effect transistor is based on a parallel layer stack of acenes serving as organic transport and emission layers. The transistor displays ambipolar characteristics with a narrow recombination zone within the transistor channel. During operation the recombination zone can be moved by a proper change in the drain and gate bias from one organic semiconductor layer to another one inducing a change in the emission colour. In the presented example the emission maxima can be switched from 530 nm to 580 nm.

Graphene field effect transistor without an energy gap.

Science.gov (United States)

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

Few-layer SnSe{sub 2} transistors with high on/off ratios

Energy Technology Data Exchange (ETDEWEB)

Pei, Tengfei; Bao, Lihong, E-mail: lhbao@iphy.ac.cn; Wang, Guocai; Ma, Ruisong; Yang, Haifang; Li, Junjie; Gu, Changzhi; Du, Shixuan; Gao, Hong-jun [Institute of Physics, Chinese Academy of Sciences, P. O. Box 603, Beijing 100190 (China); Pantelides, Sokrates [Department of Physics and Astronomy, Vanderbilt University, Nashville, Tennessee 37235 (United States); Material Science and Technology Division, Oak Ridge National Laboratory, Oak Ridge, Tennessee 37381 (United States)

2016-02-01

We report few-layer SnSe{sub 2} field effect transistors (FETs) with high current on/off ratios. By trying different gate configurations, 300 nm SiO{sub 2} and 70 nm HfO{sub 2} as back gate only and 70 nm HfO{sub 2} as back gate combined with a top capping layer of polymer electrolyte, few-layer SnSe{sub 2} FET with a current on/off ratio of 10{sup 4} can be obtained. This provides a reliable solution for electrically modulating quasi-two-dimensional materials with high electron density (over 10{sup 13} cm{sup −2}) for field-effect transistor applications.

A high performance gate drive for large gate turn off thyristors