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Sample records for floating gate transistors

  1. Floating gate transistors as biosensors (Conference Presentation)

    Science.gov (United States)

    Frisbie, C. Daniel

    2016-11-01

    Electrolyte gated transistors (EGTs) are a sub-class of thin film transistors that are extremely promising for biological sensing applications. These devices employ a solid electrolyte as the gate insulator; the very large capacitance of the electrolyte results in low voltage operation and high transconductance or gain. This talk will describe the fabrication of floating gate EGTs and their use as ricin sensors. The critical performance metrics for EGTs compared with other types of TFTs will also be reviewed.

  2. Organic nano-floating-gate transistor memory with metal nanoparticles

    Science.gov (United States)

    Van Tho, Luu; Baeg, Kang-Jun; Noh, Yong-Young

    2016-04-01

    Organic non-volatile memory is advanced topics for various soft electronics applications as lightweight, low-cost, flexible, and printable solid-state data storage media. As a key building block, organic field-effect transistors (OFETs) with a nano-floating gate are widely used and promising structures to store digital information stably in a memory cell. Different types of nano-floating-gates and their various synthesis methods have been developed and applied to fabricate nanoparticle-based non-volatile memory devices. In this review, recent advances in the classes of nano-floating-gate OFET memory devices using metal nanoparticles as charge-trapping sites are briefly reviewed. Details of device fabrication, characterization, and operation mechanisms are reported based on recent research activities reported in the literature.

  3. Graphene-graphene oxide floating gate transistor memory.

    Science.gov (United States)

    Jang, Sukjae; Hwang, Euyheon; Lee, Jung Heon; Park, Ho Seok; Cho, Jeong Ho

    2015-01-21

    A novel transparent, flexible, graphene channel floating-gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH3+), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al2 O3 blocking dielectric layers. Important design rules are proposed for a high-performance graphene memory device: (i) precise doping of the graphene channel, and (ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor-type memory device. Additionally, the positively charged GO (GO-NH3+) interacts electrostatically with hydroxyl groups of both UV-treated Al2 O3 and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene-graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10(5) s), and good mechanical stability (1000 cycles).

  4. Low Noise Bias Current/Voltage References Based on Floating-Gate MOS Transistors

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    The exploitation of floating-gate MOS transistors as reference current and voltage sources is investigated. Test structures of common source and common drain floating-gate devices have been implemented in a commercially available 0.8 micron double-poly CMOS process. The measurements performed...... promise a good maintenance of the operating point of the floating-gate devices. Examples of utilizing of such bias sources in low-noise sensor preamplifiers are discussed....

  5. Low Noise Bias Current/Voltage References Based on Floating-Gate MOS Transistors

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    The exploitation of floating-gate MOS transistors as reference current and voltage sources is investigated. Test structures of common source and common drain floating-gate devices have been implemented in a commercially available 0.8 micron double-poly CMOS process. The measurements performed...... promise a good maintenance of the operating point of the floating-gate devices. Examples of utilizing of such bias sources in low-noise sensor preamplifiers are discussed....

  6. Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

    Science.gov (United States)

    Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

    2016-11-01

    Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

  7. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

    2014-10-20

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  8. Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

    Energy Technology Data Exchange (ETDEWEB)

    Han, Jinhua; Wang, Wei, E-mail: wwei99@jlu.edu.cn; Ying, Jun; Xie, Wenfa [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

    2014-01-06

    An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

  9. Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors

    DEFF Research Database (Denmark)

    Mucha, Igor

    1999-01-01

    A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultralow supply voltage operation also in CMOS processes with high threshold voltages....... This paper presents the theoretical basis for the design of "floating-gate'' switched current memory cells by giving a detailed description and analysis of the most important impacts degrading the performance of the cells. To support the theoretical assumptions circuits based on "floating-gate'' switched...... current memory cells were designed using a CMOS process with threshold voltages V-T0n = \\V-T0p\\ = 0.9 V for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than +/-18 mu...

  10. A semi-floating gate transistor for low-voltage ultrafast memory and sensing operation.

    Science.gov (United States)

    Wang, Peng-Fei; Lin, Xi; Liu, Lei; Sun, Qing-Qing; Zhou, Peng; Liu, Xiao-Yong; Liu, Wei; Gong, Yi; Zhang, David Wei

    2013-08-09

    As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra-high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.

  11. Nonvolatile Transistor Memory with Self-Assembled Semiconducting Polymer Nanodomain Floating Gates.

    Science.gov (United States)

    Wang, Wei; Kim, Kang Lib; Cho, Suk Man; Lee, Ju Han; Park, Cheolmin

    2016-12-14

    Organic field effect transistor based nonvolatile memory (OFET-NVM) with semiconducting nanofloating gates offers additional benefits over OFET-NVMs with conventional metallic floating gates due to the facile controllability of charge storage based on the energetic structure of the floating gate. In particular, an all-in-one tunneling and floating-gate layer in which the semiconducting polymer nanodomains are self-assembled in the dielectric tunneling layer is promising. In this study, we utilize crystals of a p-type semiconducting polymer in which the crystalline lamellae of the polymer are spontaneously developed and embedded in the tunneling matrix as the nanofloating gate. The widths and lengths of the polymer nanodomains are approximately 20 nm and a few hundred nanometers, respectively. An OFET-NVM containing the crystalline nanofloating gates exhibits memory performance with a large memory window of 10 V, programming/erasing switching endurance for over 500 cycles, and a long retention time of 5000 s. Moreover, the device performance is improved by comixing with an n-type semiconductor; thus, the solution-processed p- and n-type double floating gates capable of storing both holes and electrons allow for the multilevel operation of our OFET-NVM. Four highly reliable levels (two bits per cell) of charge trapping and detrapping are achieved using this OFET-NVM by accurately choosing the programming/erasing voltages.

  12. Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

    Science.gov (United States)

    Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

    2010-01-01

    Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

  13. Using a floating-gate MOS transistor as a transducer in a MEMS gas sensing system.

    Science.gov (United States)

    Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M; Avila-García, Alejandro; Vazquez-Acosta, E N; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

    2010-01-01

    Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe(2)O(3) layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.

  14. Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

    Directory of Open Access Journals (Sweden)

    Gaspar Casados-Cruz

    2010-11-01

    Full Text Available Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.

  15. An Investigation of Impact of Transistor Gate’s Thickness of Floating Gate Transistor in Improvement of Sensitivity of Low-Power Gamma-Ray Dosimeters

    Directory of Open Access Journals (Sweden)

    Armin Afshari Moghaddam

    2016-03-01

    Full Text Available Gamma-ray dosimeter is an instrument which measures dose amount attracted by gamma ray. This integrated sensor is utilized for high irradiation and low sensitivity applications such as blood sterilization. In this article, a gamma-ray MOSFET dosimeter including a floating-gate MOSFET transistor as a sensor and a gate connection reference transistor with identical geometry are simulated using the TSMC 0.13-micron process technology. Floating-gate transistor is used in low-power circuits. The dosimeter applied herein makes use of general dose measurement methodology. Source of gamma ray is cobalt-60. Here, the impact of transistor gate’s thickness of floating transistor served as a sensor on sensitivity of dosimeter is examined. To do so, dosimeter was simulated using the software HSPICE, and impact of different thicknesses of floating transistors on sensitivity was examined. Finally, it was concluded that an increase in transistor gate’s thickness of floating transistor would bring about an improvement of at least 25 percent in sensitivity.

  16. Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

    Directory of Open Access Journals (Sweden)

    R. Srivastava

    2014-12-01

    Full Text Available This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator.

  17. Input Stage for Low-Voltage, Low-Noise Preamplifiers Based on a Floating-Gate MOS Transistor

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe degradat......A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe...

  18. Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

    Directory of Open Access Journals (Sweden)

    F. Khateb

    2012-06-01

    Full Text Available The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit.

  19. Memristive operation mode of a site-controlled quantum dot floating gate transistor

    Energy Technology Data Exchange (ETDEWEB)

    Maier, P., E-mail: patrick.maier@physik.uni-wuerzburg.de; Hartmann, F.; Mauder, T.; Emmerling, M.; Schneider, C.; Kamp, M.; Worschech, L. [Technische Physik, Physikalisches Institut, Wilhelm Conrad Röntgen Research Center for Complex Material Systems, Universität Würzburg, Am Hubland, D-97074 Würzburg (Germany); Höfling, S. [Technische Physik, Physikalisches Institut, Wilhelm Conrad Röntgen Research Center for Complex Material Systems, Universität Würzburg, Am Hubland, D-97074 Würzburg (Germany); SUPA, School of Physics and Astronomy, University of St Andrews, St Andrews KY16 9SS (United Kingdom)

    2015-05-18

    We have realized a floating gate transistor based on a GaAs/AlGaAs heterostructure with site-controlled InAs quantum dots. By short-circuiting the source contact with the lateral gates and performing closed voltage sweep cycles, we observe a memristive operation mode with pinched hysteresis loops and two clearly distinguishable conductive states. The conductance depends on the quantum dot charge which can be altered in a controllable manner by the voltage value and time interval spent in the charging region. The quantum dot memristor has the potential to realize artificial synapses in a state-of-the-art opto-electronic semiconductor platform by charge localization and Coulomb coupling.

  20. Nano-Floating Gate Memory Devices Composed of ZnO Thin-Film Transistors on Flexible Plastics

    Directory of Open Access Journals (Sweden)

    Park Byoungjun

    2011-01-01

    Full Text Available Abstract Nano-floating gate memory devices were fabricated on a flexible plastic substrate by a low-temperature fabrication process. The memory characteristics of ZnO-based thin-film transistors with Al nanoparticles embedded in the gate oxides were investigated in this study. Their electron mobility was found to be 0.18 cm2/V·s and their on/off ratio was in the range of 104–105. The threshold voltages of the programmed and erased states were negligibly changed up to 103 cycles. The flexibility, memory properties, and low-temperature fabrication of the nano-floating gate memory devices described herein suggest that they have potential applications for future flexible integrated electronics.

  1. Differential multiple-time-programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

    Science.gov (United States)

    Hsu, Chia-Ling; Liao, Chu-Feng; Chien, Wei Yu; Chih, Yue-Der; Lin, Chrong Jung; King, Ya-Chin

    2017-04-01

    In this paper, we present a new differential multiple-time-programmable (MTP) memory cell with a novel slot contact coupling structure in the fin field-effect transistor (FinFET) CMOS process. This MTP cell contains a pair of floating metal gates to store differential data on a single cell. Through differential read operations, the cells are less susceptible to read error caused by cell-to-cell variations. In a nano-scaled FinFET process, the gate dielectric layer becomes too thin to retain charge in the floating gates for long periods of time. Differential cell design further extends the data lifetime, even with the serious charge-loss problem, and reduces the overall intellectual property (IP) area.

  2. Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Chi, Li-Feng, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn [Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

    2015-03-23

    Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

  3. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    Science.gov (United States)

    Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-09-01

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm2/V s. The unidirectional shift of turn-on voltage (Von) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (VP/VE) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm2/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the VP/VE of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional Von shift. As a result, an enlarged memory window of 28.6 V at the VP/VE of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  4. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Wei, E-mail: wwei99@jlu.edu.cn; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

    2014-09-22

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  5. Cycle of charge carrier states with formation and extinction of a floating gate in an ambipolar tetracyanoquaterthienoquinoid-based field-effect transistor

    Science.gov (United States)

    Itoh, Takuro; Toyota, Taro; Higuchi, Hiroyuki; Matsushita, Michio M.; Suzuki, Kentaro; Sugawara, Tadashi

    2017-03-01

    A tetracyanoquaterthienoquinoid (TCT4Q)-based field effect transistor is characterized by the ambipolar transfer characteristics and the facile shift of the threshold voltage induced by the bias stress. The trapping and detrapping kinetics of charge carriers was investigated in detail by the temperature dependence of the decay of source-drain current (ISD). We found a repeatable formation of a molecular floating gate is derived from a 'charge carrier-and-gate' cycle comprising four stages, trapping of mobile carriers, formation of a floating gate, induction of oppositely charged mobile carriers, and recombination between mobile and trapped carriers to restore the initial state.

  6. Design of a High Precision, Wide Ranged Analog Clock Generator with Field Programmability Using Floating-Gate Transistors

    Directory of Open Access Journals (Sweden)

    Prem Pyara

    2010-09-01

    Full Text Available This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chipprogrammability feature using Floating-gate transistors. The programmable oscillator can attain acontinuous range of time-periods lying in the programming precision range of Floating Gates. Thecircuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current ofcurrent generator circuit is programmable and mirrored to the wave generator to generate the desiredsquare wave. The topology is well suited to applications like clocking high performance ADCs and DACsas well as used as the internal clock in structured analog CMOS designs. A simulation model of thecircuit was built in T-Spice, 0.35μm CMOS process. The circuit results in finely tuned clock withprogrammability precision of about 13bit [1]. Simulation results show high amount of temperatureinsensitivity (0.507ns/°C for a large range of thermal conditions. The proposed circuit can compensateany change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.

  7. Design of a High Precision, Wide Ranged Analog Clock Generator with Field Programmability Using Floating-Gate Transistors

    Directory of Open Access Journals (Sweden)

    Garima Kapur

    2010-09-01

    Full Text Available This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain acontinuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACsas well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35μm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13 bit [1]. Simulation results show high amount of temperature insensitivity (0.507 ns/°C for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.

  8. Charging dynamics of a floating gate transistor with site-controlled quantum dots

    Energy Technology Data Exchange (ETDEWEB)

    Maier, P., E-mail: patrick.maier@physik.uni-wuerzburg.de; Hartmann, F.; Emmerling, M.; Schneider, C.; Höfling, S.; Kamp, M.; Worschech, L. [Technische Physik, Physikalisches Institut, Wilhelm Conrad Röntgen Research Center for Complex Material Systems, Universität Würzburg, Am Hubland, D-97074 Würzburg (Germany)

    2014-08-04

    A quantum dot memory based on a GaAs/AlGaAs quantum wire with site-controlled InAs quantum dots was realized by means of molecular beam epitaxy and etching techniques. By sampling of different gate voltage sweeps for the determination of charging and discharging thresholds, it was found that discharging takes place at short time scales of μs, whereas several seconds of waiting times within a distinct negative gate voltage range were needed to charge the quantum dots. Such quantum dot structures have thus the potential to implement logic functions comprising charge and time dependent ingredients such as counting of signals or learning rules.

  9. Impact of strain on gate-induced floating body effect for partially depleted silicon-on-insulator p-type metal–oxide–semiconductor-field-effect-transistors

    Energy Technology Data Exchange (ETDEWEB)

    Lo, Wen-Hung [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Dai, Chih-Hao [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Chung, Wan-Lin [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Chen, Ching-En; Ho, Szu-Han [Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC (China); Tsai, Jyun-Yu [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Chen, Hua-Mao [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC (China); Liu, Guan-Ru [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Cheng, Osbert; Huang, Cheng-Tung [Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan, ROC (China)

    2013-01-01

    This work investigates impact of mechanical strain on gate-induced-floating-body-effect (GIFBE) for partially depleted silicon-on-insulator p-type metal–oxide–semiconductor field effect transistors (PD SOI p-MOSFETs). First part, the original mechanism of GIFBE on PD SOI p-MOSFETs is studied. The experimental results indicate that GIFBE causes a reduction in oxide electric field (E{sub ox}), resulting in an underestimate of negative-bias temperature instability (NBTI) degradation. This can be attributed to the electrons tunneling from the process-induced partial n{sup +} poly gate and anode electron injection (AEI) model, rather than the electron valence band tunneling (EVB) widely accepted as the mechanism for n-MOSFETs. And then, the second part shows that the strained FB device has less NBTI degradation than the unstrained devices. This behavior can be attributed to the fact that more electron accumulation was induced by strain-induced band gap narrowing, reducing NBTI significantly. - Highlights: ► This work investigates the impact of mechanical strain on GIFBE for PD SOI p-MOSFETs. ► FB device shows an insignificant NBTI due to GIFBE. ► GIFBE results from the partial n{sup +} poly gate and anode electron injection model. ► The strained FB device has less NBTI degradation than unstrained devices. ► We verify the band gap narrowing causes less NBTI on strained FB device.

  10. Direct label-free electrical immunodetection of transplant rejection protein biomarker in physiological buffer using floating gate AlGaN/GaN high electron mobility transistors.

    Science.gov (United States)

    Tulip, Fahmida S; Eteshola, Edward; Desai, Suchita; Mostafa, Salwa; Roopa, Subramanian; Evans, Boyd; Islam, Syed Kamrul

    2014-06-01

    Monokine induced by interferon gamma (MIG/CXCL9) is used as an immune biomarker for early monitoring of transplant or allograft rejection. This paper demonstrates a direct electrical, label-free detection method of recombinant human MIG with anti-MIG IgG molecules in physiologically relevant buffer environment. The sensor platform used is a biologically modified GaN-based high electron mobility transistor (HEMT) device. Biomolecular recognition capability was provided by using high affinity anti-MIG monoclonal antibody to form molecular affinity interface receptors on short N-hydroxysuccinimide-ester functionalized disulphide (DSP) self-assembled monolayers (SAMs) on the gold sensing gate of the HEMT device. A floating gate configuration has been adopted to eliminate the influences of external gate voltage. Preliminary test results with the proposed chemically treated GaN HEMT biosensor show that MIG can be detected for a wide range of concentration varying from 5 ng/mL to 500 ng/mL.

  11. The four-gate transistor

    Science.gov (United States)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  12. Gate-enclosed NMOS transistors

    Institute of Scientific and Technical Information of China (English)

    Fan Xue; Li Ping; Li Wei; Zhang Bin; Xie Xiaodong; Wang Gang; Hu Bin; Zhai Yahong

    2011-01-01

    In order to quantitatively compare the design cost and performance of various gate styles,NMOS transistors with two-edged,annular and ring gate layouts were designed and fabricated by a commercial 0.35 μm CMOS process.By comparing the minimum W/L ratios and transistor areas,it was found that either the annular layout or its ring counterpart incurs a higher area penalty that depends on the W/L ratio of the transistor to be designed.Furthermore,by comparing the output and transfer characteristics of the transistors and analyzing the popular existing methods for extracting the effective W/L ratio,it was shown that the mid-line approximation for annular NMOS could incur an error of more than 10%.It was also demonstrated that the foundry-provided extraction tool needs significant adaptation when being applied to the enclosed-gate transistors,since it is targeted only toward the two-edged transistor.A simple approach for rough extraction of the W/L ratio for the ring-gate NMOS was presented and its effectiveness was confirmed by the experimental results with an error up to 8%.

  13. Logic Gates with Ion Transistors

    CERN Document Server

    Grebel, Haim

    2016-01-01

    Electronic logic gates are the basic building blocks of every computing and micro controlling system. Logic gates are made of switches, such as diodes and transistors. Ion-selective, ionic switches may emulate electronic switches [1-8]. If we ever want to create artificial bio-chemical circuitry, then we need to move a step further towards ion-logic circuitry. Here we demonstrate ion XOR and OR gates with electrochemical cells, and specifically, with two wet-cell batteries. In parallel to vacuum tubes, the batteries were modified to include a third, permeable and conductive mid electrode (the gate), which was placed between the anode and cathode in order to affect the ion flow through it. The key is to control the cell output with a much smaller biasing power, as demonstrated here. A successful demonstration points to self-powered ion logic gates.

  14. Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

    Science.gov (United States)

    Bae, Jong-Ho; Lee, Jong-Ho

    2016-05-01

    A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

  15. Ionic thermoelectric gating organic transistors

    Science.gov (United States)

    Zhao, Dan; Fabiano, Simone; Berggren, Magnus; Crispin, Xavier

    2017-01-01

    Temperature is one of the most important environmental stimuli to record and amplify. While traditional thermoelectric materials are attractive for temperature/heat flow sensing applications, their sensitivity is limited by their low Seebeck coefficient (∼100 μV K−1). Here we take advantage of the large ionic thermoelectric Seebeck coefficient found in polymer electrolytes (∼10,000 μV K−1) to introduce the concept of ionic thermoelectric gating a low-voltage organic transistor. The temperature sensing amplification of such ionic thermoelectric-gated devices is thousands of times superior to that of a single thermoelectric leg in traditional thermopiles. This suggests that ionic thermoelectric sensors offer a way to go beyond the limitations of traditional thermopiles and pyroelectric detectors. These findings pave the way for new infrared-gated electronic circuits with potential applications in photonics, thermography and electronic-skins. PMID:28139738

  16. Ionic thermoelectric gating organic transistors

    Science.gov (United States)

    Zhao, Dan; Fabiano, Simone; Berggren, Magnus; Crispin, Xavier

    2017-01-01

    Temperature is one of the most important environmental stimuli to record and amplify. While traditional thermoelectric materials are attractive for temperature/heat flow sensing applications, their sensitivity is limited by their low Seebeck coefficient (~100 μV K-1). Here we take advantage of the large ionic thermoelectric Seebeck coefficient found in polymer electrolytes (~10,000 μV K-1) to introduce the concept of ionic thermoelectric gating a low-voltage organic transistor. The temperature sensing amplification of such ionic thermoelectric-gated devices is thousands of times superior to that of a single thermoelectric leg in traditional thermopiles. This suggests that ionic thermoelectric sensors offer a way to go beyond the limitations of traditional thermopiles and pyroelectric detectors. These findings pave the way for new infrared-gated electronic circuits with potential applications in photonics, thermography and electronic-skins.

  17. Advanced insulated gate bipolar transistor gate drive

    Science.gov (United States)

    Short, James Evans; West, Shawn Michael; Fabean, Robert J.

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  18. Logic gates based on ion transistors.

    Science.gov (United States)

    Tybrandt, Klas; Forchheimer, Robert; Berggren, Magnus

    2012-05-29

    Precise control over processing, transport and delivery of ionic and molecular signals is of great importance in numerous fields of life sciences. Integrated circuits based on ion transistors would be one approach to route and dispense complex chemical signal patterns to achieve such control. To date several types of ion transistors have been reported; however, only individual devices have so far been presented and most of them are not functional at physiological salt concentrations. Here we report integrated chemical logic gates based on ion bipolar junction transistors. Inverters and NAND gates of both npn type and complementary type are demonstrated. We find that complementary ion gates have higher gain and lower power consumption, as compared with the single transistor-type gates, which imitates the advantages of complementary logics found in conventional electronics. Ion inverters and NAND gates lay the groundwork for further development of solid-state chemical delivery circuits.

  19. Water-gel for gating graphene transistors.

    Science.gov (United States)

    Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

    2014-05-14

    Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

  20. TRANSISTOR IMPLEMENTATION OF REVERSIBLE PRT GATES

    Directory of Open Access Journals (Sweden)

    RASHMI S.B,

    2011-03-01

    Full Text Available Reversible logic has emerged as one of the most important approaches for power optimization with its application in low power VLSI design. Reversible or information lossless circuits have applications in nanotechnology, digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requirement in the emerging field of quantum computing. In this paper, two newoptimized universal gates are proposed. One of them has an ability to operate as a reversible half adder and half subtractor imultaneously. Another one acts only as half adder with minimum transistor count. The reversible gates are evaluated in terms of number of transistor count, critical path, garbage outputs and one to one mapping. Here transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on the results of the analysis, some of the trade-offs are made in the design to improve the efficiency.

  1. Molecular floating-gate organic nonvolatile memory with a fully solution processed core architecture

    Science.gov (United States)

    Wu, Chao; Wang, Wei; Song, Junfeng

    2016-11-01

    In this paper, we demonstrated a floating-gate organic thin film transistor based nonvolatile memory, in which the core architecture was processed by a sequential three-step solution spin-coating method. The molecular semiconductor 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-Pen) distributing in the matrix of polymer poly(styrene) (PS), acting as the floating-gate and tunneling layer, respectively, was processed by one-step spin-coating from their blending solution. The effect of the proportion of TIPS-Pen in the matrix of PS on the memory performances of devices was researched. As a result, a good nonvolatile memory was achieved, with a memory window larger than 25 V, stable memory endurance property over 500 cycles and retention time longer than 5000 s with a high memory ratio larger than 102, at an optimal proportion of TIPS-Pen in the matrix of PS.

  2. Precursor Parameter Identification for Insulated Gate Bipolar Transistor (IGBT) Prognostics

    Data.gov (United States)

    National Aeronautics and Space Administration — Precursor parameters have been identified to enable development of a prognostic approach for insulated gate bipolar transistors (IGBT). The IGBT were subjected to...

  3. Capacitance Variation of Electrolyte-Gated Bilayer Graphene Based Transistors

    OpenAIRE

    Hediyeh Karimi; Rubiyah Yusof; Mohammad Taghi Ahmadi; Mehdi Saeidmanesh; Meisam Rahmani; Elnaz Akbari; Wong King Kiat

    2013-01-01

    Quantum capacitance of electrolyte-gated bilayer graphene field-effect transistors is investigated in this paper. Bilayer graphene has received huge attention due to the fact that an energy gap could be opened by chemical doping or by applying external perpendicular electric field. So, this extraordinary property can be exploited to use bilayer graphene as a channel in electrolyte-gated field-effect transistors. The quantum capacitance of bi-layer graphene with an equivalent circuit is presen...

  4. A New Design Technique of Reversible BCD Adder Based on NMOS With Pass Transistor Gates

    CERN Document Server

    Hossain, Md Sazzad; Rahman, Md Motiur; Hossain, A S M Delowar; Hasan, Md Minul

    2012-01-01

    In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.

  5. Controlled Phase Gate Based on an Electron Floating on Helium

    Institute of Scientific and Technical Information of China (English)

    SHI Yan-Li; MEI Feng; YU Ya-Fei; ZHANG Zhi-Ming

    2011-01-01

    We propose a scheme to generate the controlled phase gate by using an electron floating on liquid helium. The electron is also driven by a classical laser beam and by an oscillating magnetic field. In the process, the vibration of the electron is used as the qubus to couple the energy level qubit (1D Stark-shifted hydrogen) and spin qubit Ultimately. the controlled phase gate can be generated.%@@ We propose a scheme to generate the controlled phase gate by using an electron floating on liquid helium.The electron is also driven by a classical laser beam and by an oscillating magnetic field.In the process,the vibration of the electron is used as the qubus to couple the energy level qubit(1D Stark-shifted hydrogen) and spin qubit.Ultimately,the controlled phase gate can be generated.

  6. Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

    Science.gov (United States)

    Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

    2015-05-26

    Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

  7. Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

    Science.gov (United States)

    Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

    2016-01-01

    The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

  8. A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

    Science.gov (United States)

    Wang, Han; Gou, Chao; Luo, Kai

    2017-04-01

    This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and {I}{{Q}} of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.

  9. Voltage controlled resistor using quasi-floating-gate MOSFETs

    Directory of Open Access Journals (Sweden)

    Susheel Sharma

    2013-01-01

    Full Text Available A voltage controlled resistor (VCR using quasi-floating-gate MOSFETs (QFGMOS suitable for low voltage applications is presented. The performance of the VCR implemented with QFGMOS is compared with its floating-gate MOSFET (FGMOS version. It was found that QFGMOS offers better performance than FGMOS in terms of frequency response, offsets and chip area. The VCR using QFGMOS offers high bandwidth and low power dissipation and yields high value of resistance as compared to its FGMOS counterpart. The workability of the presented circuits was tested by PSpice simulations using level 3 parameters of 0.5μm CMOS technology with supply voltage of ± 0.75V. The simulations results were found to be in accordance with the theoretical predictions.

  10. SEMICONDUCTOR DEVICES: Trench gate IGBT structure with floating P region

    Science.gov (United States)

    Mengliang, Qian; Zehong, Li; Bo, Zhang; Zhaoji, Li

    2010-02-01

    A new trench gate IGBT structure with a floating P region is proposed, which introduces a floating P region into the trench accumulation layer controlled IGBT (TAC-IGBT). The new structure maintains a low on-state voltage drop and large forward biased safe operating area (FBSOA) of the TAC-IGBT structure while reduces the leakage current and improves the breakdown voltage. In addition, it enlarges the short circuit safe operating area (SCSOA) of the TAC-IGBT, and is simple in fabrication and design. Simulation results indicate that, for IGBT structures with a breakdown voltage of 1200 V, the leakage current of the new trench gate IGBT structure is one order of magnitude lower than the TAC-IGBT structure and the breakdown voltage is 150 V higher than the TAC-IGBT.

  11. Interdigitated Extended Gate Field Effect Transistor Without Reference Electrode

    Science.gov (United States)

    Ali, Ghusoon M.

    2017-02-01

    An interdigitated extended gate field effect transistor (IEGFET) has been proposed as a modified pH sensor structure of an extended gate field effect transistor (EGFET). The reference electrode and the extended gate in the conventional device have been replaced by a single interdigitated extended gate. A metal-semiconductor-metal interdigitated extended gate containing two multi-finger Ni electrodes based on zinc oxide (ZnO) thin film as a pH-sensitive membrane. ZnO thin film was grown on a p-type Si (100) substrate by the sol-gel technique. The fabricated extended gate is connected to a commercial metal-oxide-semiconductor field-effect transistor device in CD4007UB. The experimental data show that this structure has real time and linear pH voltage and current sensitivities in a concentration range between pH 4 and 11. The voltage and current sensitivities are found to be about 22.4 mV/pH and 45 μA/pH, respectively. Reference electrode elimination makes the IEGFET device simple to fabricate, easy to carry out the measurements, needing a small volume of solution to test and suitable for disposable biosensor applications. Furthermore, this uncomplicated structure could be extended to fabricate multiple ions microsensors and lab-on-chip devices.

  12. Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Aunet, Snorre

    2002-06-01

    This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

  13. Frequency response of electrolyte-gated graphene electrodes and transistors

    Science.gov (United States)

    Drieschner, Simon; Guimerà, Anton; Cortadella, Ramon G.; Viana, Damià; Makrygiannis, Evangelos; Blaschke, Benno M.; Vieten, Josua; Garrido, Jose A.

    2017-03-01

    The interface between graphene and aqueous electrolytes is of high importance for applications of graphene in the field of biosensors and bioelectronics. The graphene/electrolyte interface is governed by the low density of states of graphene that limits the capacitance near the Dirac point in graphene and the sheet resistance. While several reports have focused on studying the capacitance of graphene as a function of the gate voltage, the frequency response of graphene electrodes and electrolyte-gated transistors has not been discussed so far. Here, we report on the impedance characterization of single layer graphene electrodes and transistors, showing that due to the relatively high sheet resistance of graphene, the frequency response is governed by the distribution of resistive and capacitive circuit elements along the graphene/electrolyte interface. Based on an analytical solution for the impedance of the distributed circuit elements, we model the graphene/electrolyte interface both for the electrode and the transistor configurations. Using this model, we can extract the relevant material and device parameters such as the voltage-dependent intrinsic sheet and series resistances as well as the interfacial capacitance. The model also provides information about the frequency threshold of electrolyte-gated graphene transistors, above which the device exhibits a non-resistive response, offering an important insight into the suitable frequency range of operation of electrolyte-gated graphene devices.

  14. Stable charge storing in two-dimensional MoS2 nanoflake floating gates for multilevel organic flash memory

    Science.gov (United States)

    Kang, Minji; Kim, Yeong-A.; Yun, Jin-Mun; Khim, Dongyoon; Kim, Jihong; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

    2014-10-01

    In this study, we investigated chemically exfoliated two-dimensional (2-D) nanoflakes of molybdenum disulfide (MoS2) as charge-storing elements for use in organic multilevel memory devices (of the printed/flexible non-volatile type) based on organic field-effect transistors (OFETs) containing poly(3-hexylthiophene) (P3HT). The metallic MoS2 nanoflakes were exfoliated in 2-methoxyethanol by the lithium intercalation method and were deposited as nano-floating gates between polystyrene and poly(methyl methacrylate), used as bilayered gate dielectrics, by a simple spin-coating and low temperature (102 times, and most importantly, quasi-permanent charge-storing characteristics, i.e., a very long retention time (longer than the technological requirement of commercial memory devices (>10 years)). In addition, we successfully developed multilevel memory cells (2 bits per cell) by controlling the gate bias magnitude.In this study, we investigated chemically exfoliated two-dimensional (2-D) nanoflakes of molybdenum disulfide (MoS2) as charge-storing elements for use in organic multilevel memory devices (of the printed/flexible non-volatile type) based on organic field-effect transistors (OFETs) containing poly(3-hexylthiophene) (P3HT). The metallic MoS2 nanoflakes were exfoliated in 2-methoxyethanol by the lithium intercalation method and were deposited as nano-floating gates between polystyrene and poly(methyl methacrylate), used as bilayered gate dielectrics, by a simple spin-coating and low temperature (102 times, and most importantly, quasi-permanent charge-storing characteristics, i.e., a very long retention time (longer than the technological requirement of commercial memory devices (>10 years)). In addition, we successfully developed multilevel memory cells (2 bits per cell) by controlling the gate bias magnitude. Electronic supplementary information (ESI) available: The memory characteristics with thickness of MoS2 nanoflakes as nano-floating-gate. See DOI: 10.1039/c

  15. Electrolyte-gated transistors for organic and printed electronics.

    Science.gov (United States)

    Kim, Se Hyun; Hong, Kihyon; Xie, Wei; Lee, Keun Hyung; Zhang, Sipei; Lodge, Timothy P; Frisbie, C Daniel

    2013-04-04

    Here we summarize recent progress in the development of electrolyte-gated transistors (EGTs) for organic and printed electronics. EGTs employ a high capacitance electrolyte as the gate insulator; the high capacitance increases drive current, lowers operating voltages, and enables new transistor architectures. Although the use of electrolytes in electronics is an old concept going back to the early days of the silicon transistor, new printable, fast-response polymer electrolytes are expanding the potential applications of EGTs in flexible, printed digital circuits, rollable displays, and conformal bioelectronic sensors. This report introduces the structure and operation mechanisms of EGTs and reviews key developments in electrolyte materials for use in printed electronics. The bulk of the article is devoted to electrical characterization of EGTs and emerging applications. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  16. Modeling and simulation of floating gate nanocrystal FET devices and circuits

    Science.gov (United States)

    Hasaneen, El-Sayed A. M.

    nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

  17. Plasmonic response of partially gated field effect transistors

    Science.gov (United States)

    Rudin, S.; Rupper, G.; Reed, M. L.; Shur, M.

    2016-09-01

    Electron density oscillations in the transistor channels - plasma waves in the two-dimensional electron gas - determine the high frequency device response. Plasmonic field effect transistors have emerged as very sensitive, tunable, and extremely fast detectors of THz radiation. They have been implemented using silicon (CMOS), AlGaAs/InGaAs HEMTs, and AlGaAs/InGaAs HEMTs, with the HEMTs shown to operate more efficiently at higher THz frequencies. These HEMTs have both gated and ungated sections of the device channel between the source and drain, and the photovoltaic regime of operation requires an asymmetric gate placement in the device channel. The interactions of the plasma waves in the gated and ungated channel regions strongly affect the overall response and have been investigated in numerous publications. This work addresses a new aspect of such interaction - the effect of the relative position of the gated and ungated section. We show this previously unexplored effect plays a dominant role in determining the response. The results of the numerical simulation based on the solution of the complete system of the hydrodynamic equations describing the electron fluid in the device channel show that the inverse response frequency could be approximated by the sum of the gated plasmon transit time in the gated section of the device, the ungated plasmon transit time in the ungated section of the device between the gate and the drain, and the RC gate-to-source constant. Here R and C are the resistance and capacitance of the gate to source section. Hence, the highest speed is achieved when the gate is as close to the source as possible. This suggests a novel plasmonic detector design, where the gate and source electrode overlap, which is shown to have a superior frequency response for the same distance between the source and the drain.

  18. Modeling and discussion of threshold voltage for a multi-floating gate FET pH sensor

    Institute of Scientific and Technical Information of China (English)

    Shi Zhaoxia; Zhu Dazhong

    2009-01-01

    Research into new pH sensors fabricated by the standard CMOS process is currently a hot topic. The new pH sensing multi-floating gate field effect transistor is found to have a very large threshold voltage, which is different from the normal ion-sensitive field effect transistor. After analyzing all the interface layers of the structure, a new sensitive model based on the Gauss theorem and the charge neutrality principle is created in this paper. According to the model, the charge trapped on the multi-floating gate during the process and the thickness of the sensitive layer are the main causes of the large threshold voltage. From this model, it is also found that removing the charge on the multi-floating gate is an effective way to decrease the threshold voltage. The test results for three different standard pH buffer solutions show the correctness of the model and point the way to solve the large threshold problem.

  19. A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates

    Directory of Open Access Journals (Sweden)

    Md. Sazzad Hossain

    2011-12-01

    Full Text Available In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.

  20. Four-gate transistor analog multiplier circuit

    Science.gov (United States)

    Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)

    2011-01-01

    A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

  1. Light emission and floating gate memory characteristics of germanium nanocrystals

    Energy Technology Data Exchange (ETDEWEB)

    Das, Samaresh; Manna, Santanu; Singha, Rajkumar; Dhar, Achintya; Ray, Samit Kumar [Department of Physics and Meteorology, Indian Institute of Technology Kharagpur, Kharagpur-721302 (India); Anopchenko, Aleksei; Daldosso, Nicola; Pavesi, Lorenzo [Laboratorio di Nanoscienze, Dipartimento di Fisica, Universita di Trento, Via Sommarive 14, 38100 Povo (Trento) (Italy)

    2011-03-15

    We report Ge nanocrystals (NCs) based dual functional light emitting and metal insulator semiconductor (MIS) flash memory devices, fabricated by rf sputtering. Transmission electron micrographs revealed the formation of spherically shaped Ge NCs. We have observed broad electroluminescence (EL) around 760 nm, which is attributed to electron-hole recombination in quantum confined Ge NCs. The dependence of integrated EL intensity on drive currents has also been studied. An anti-clockwise hysteresis behaviour is observed in capacitance-voltage measurements of MIS devices for different sweep voltages, indicating net electron trapping in NC based floating gates. (Copyright copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  2. Orientation selectivity in a multi-gated organic electrochemical transistor

    Science.gov (United States)

    Gkoupidenis, Paschalis; Koutsouras, Dimitrios A.; Lonjaret, Thomas; Fairfield, Jessamyn A.; Malliaras, George G.

    2016-06-01

    Neuromorphic devices offer promising computational paradigms that transcend the limitations of conventional technologies. A prominent example, inspired by the workings of the brain, is spatiotemporal information processing. Here we demonstrate orientation selectivity, a spatiotemporal processing function of the visual cortex, using a poly(3,4ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) organic electrochemical transistor with multiple gates. Spatially distributed inputs on a gate electrode array are found to correlate with the output of the transistor, leading to the ability to discriminate between different stimuli orientations. The demonstration of spatiotemporal processing in an organic electronic device paves the way for neuromorphic devices with new form factors and a facile interface with biology.

  3. Capacitance Variation of Electrolyte-Gated Bilayer Graphene Based Transistors

    Directory of Open Access Journals (Sweden)

    Hediyeh Karimi

    2013-01-01

    Full Text Available Quantum capacitance of electrolyte-gated bilayer graphene field-effect transistors is investigated in this paper. Bilayer graphene has received huge attention due to the fact that an energy gap could be opened by chemical doping or by applying external perpendicular electric field. So, this extraordinary property can be exploited to use bilayer graphene as a channel in electrolyte-gated field-effect transistors. The quantum capacitance of bi-layer graphene with an equivalent circuit is presented, and also based on the analytical model a numerical solution is reported. We begin by modeling the DOS, followed by carrier concentration as a function V in degenerate and nondegenerate regimes. To further confirm this viewpoint, the presented analytical model is compared with experimental data, and acceptable agreement is reported.

  4. Carbon nanotube transistors with graphene oxide films as gate dielectrics

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

  5. High-transconductance graphene solution-gated field effect transistors

    Science.gov (United States)

    Hess, L. H.; Hauf, M. V.; Seifert, M.; Speck, F.; Seyller, T.; Stutzmann, M.; Sharp, I. D.; Garrido, J. A.

    2011-07-01

    In this work, we report on the electronic properties of solution-gated field effect transistors (SGFETs) fabricated using large-area graphene. Devices prepared both with epitaxially grown graphene on SiC as well as with chemical vapor deposition grown graphene on Cu exhibit high transconductances, which are a consequence of the high mobility of charge carriers in graphene and the large capacitance at the graphene/water interface. The performance of graphene SGFETs, in terms of gate sensitivity, is compared to other SGFET technologies and found to be clearly superior, confirming the potential of graphene SGFETs for sensing applications in electrolytic environments.

  6. SWNT array resonant gate MOS transistor.

    Science.gov (United States)

    Arun, A; Campidelli, S; Filoramo, A; Derycke, V; Salet, P; Ionescu, A M; Goffman, M F

    2011-02-04

    We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

  7. SWNT array resonant gate MOS transistor

    Energy Technology Data Exchange (ETDEWEB)

    Arun, A; Salet, P; Ionescu, A M [NanoLab, Ecole Polytechnique Federale de Lausanne, CH-1015, Lausanne (Switzerland); Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F, E-mail: marcelo.goffman@cea.fr [Laboratoire d' Electronique Moleculaire, SPEC (CNRS URA 2454), IRAMIS, CEA, Gif-sur-Yvette (France)

    2011-02-04

    We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

  8. Scaling issues for analogue circuits using Double Gate SOI transistors

    Science.gov (United States)

    Lim, Tao Chuan; Armstrong, G. Alastair

    2007-02-01

    This work presents a systematic analysis on the impact of source-drain engineering using gate "non-overlapped" on the RF performance of nano-scaled fully depleted Double Gate SOI transistors, when used in the design of a typical two stage Operational Transconductance Amplifier (OTA). It is evident that for a gate length less than 40 nm, the incorporation of optimal source-drain engineering requiring a spacer length, which may exceed the length of the gate, is particularly beneficial in analogue applications. Lengthening the spacer reduces gate capacitance in the weak/moderate inversion region more than transconductance, improving cut-off frequency fT. This improvement is particularly significant in a circuit application where an optimal spacer of 1.5 times the gate length is proposed. This gate under-lapped concept with extended spacer can also significantly enhance DC gain of the OTA, by increasing the Early Voltage, while maximising the transconductance to current ratio in the weak to moderate inversion, close to threshold voltage. With optimally designed devices, the sensitivity of OTA circuit performance to doping profile is shown to be relatively low.

  9. Simulation of 50-nm Gate Graphene Nanoribbon Transistors

    Directory of Open Access Journals (Sweden)

    Cedric Nanmeni Bondja

    2016-01-01

    Full Text Available An approach to simulate the steady-state and small-signal behavior of GNR MOSFETs (graphene nanoribbon metal-semiconductor-oxide field-effect transistor is presented. GNR material parameters and a method to account for the density of states of one-dimensional systems like GNRs are implemented in a commercial device simulator. This modified tool is used to calculate the current-voltage characteristics as well the cutoff frequency fT and the maximum frequency of oscillation fmax of GNR MOSFETs. Exemplarily, we consider 50-nm gate GNR MOSFETs with N = 7 armchair GNR channels and examine two transistor configurations. The first configuration is a simplified MOSFET structure with a single GNR channel as usually studied by other groups. Furthermore, and for the first time in the literature, we study in detail a transistor structure with multiple parallel GNR channels and interribbon gates. It is shown that the calculated fT of GNR MOSFETs is significantly lower than that of GFETs (FET with gapless large-area graphene channel with comparable gate length due to the mobility degradation in GNRs. On the other hand, GNR MOSFETs show much higher fmax compared to experimental GFETs due the semiconducting nature of the GNR channels and the resulting better saturation of the drain current. Finally, it is shown that the gate control in FETs with multiple parallel GNR channels is improved while the cutoff frequency is degraded compared to single-channel GNR MOSFETs due to parasitic capacitances of the interribbon gates.

  10. Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

    Science.gov (United States)

    Wei, Jiaxing; Liu, Siyang; Liu, Xiaoqiang; Sun, Weifeng; Liu, Yuwei; Liu, Xiaohong; Hou, Bo

    2017-08-01

    The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

  11. Fullerene thin-film transistors fabricated on polymeric gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Puigdollers, J. [Micro and Nano Technology Group (MNT), Dept. Enginyeria Electronica, Universitat Politecnica Catalunya, C/ Jordi Girona 1-3, Modul C4, 08034-Barcelona (Spain)], E-mail: jpuigd@eel.upc.edu; Voz, C. [Micro and Nano Technology Group (MNT), Dept. Enginyeria Electronica, Universitat Politecnica Catalunya, C/ Jordi Girona 1-3, Modul C4, 08034-Barcelona (Spain); Cheylan, S. [ICFO - Mediterranean Technology Park, Avda del Canal Olimpic s/n, 08860-Castelldefels (Spain); Orpella, A.; Vetter, M.; Alcubilla, R. [Micro and Nano Technology Group (MNT), Dept. Enginyeria Electronica, Universitat Politecnica Catalunya, C/ Jordi Girona 1-3, Modul C4, 08034-Barcelona (Spain)

    2007-07-16

    Thin-film transistors with fullerene as n-type organic semiconductor have been fabricated. A polymeric gate dielectric, polymethyl methacrylate, has been used as an alternative to usual inorganic dielectrics. No significant differences in the microstructure of fullerene thin-films grown on polymethyl methacrylate were observed. Devices with either gold or aluminium top electrodes have been fabricated. Although the lower work-function of aluminium compared to gold should favour electron injection, similar field-effect mobilities in the range of 10{sup -2} cm{sup 2} V{sup -1} s{sup -1} were achieved in both cases. Actually, the output characteristics indicate that organic thin-film transistors behave more linearly with gold than with aluminium electrodes. These results confirm that not only energy barriers determine carrier injection at metal/organic interfaces, but also chemical interactions.

  12. Compact core model for Symmetric Double-Gate Junctionless Transistors

    Science.gov (United States)

    Cerdeira, A.; Ávila, F.; Íñiguez, B.; de Souza, M.; Pavanello, M. A.; Estrada, M.

    2014-04-01

    A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including the series resistance effects. Most model parameters are related to physical magnitudes and the extraction procedure for each of them is well established. The model provides an accurate continuous description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of being symmetrical with respect to drain voltage equal to zero. It is validated with simulations for doping concentrations of 5 × 1018 and 1 × 1019 cm-3, as well as for layer thickness of 10 and 15 nm, allowing normally-off operation.

  13. An Analytical Universal Model for Symmetric Double Gate Junctionless Transistors

    Directory of Open Access Journals (Sweden)

    N. Bora

    2016-06-01

    Full Text Available An analytical surface potential based universal model for the drain current voltage characteristics of Symmetric Double gate (DG junctionless field effect transistors is presented. This novel universal model is valid for all operating regions from depletion to inversion regions of operations. The primary conduction mechanism is governed by the bulk current where the channel becomes fully depleted in turning it off. This model has been validated by using TCAD device simulating software. The comparison shows high accuracy of the proposed model.

  14. Electrolyte-gated organic synapse transistor interfaced with neurons

    CERN Document Server

    Desbief, Simon; Casalini, Stefano; Guerin, David; Tortorella, Silvia; Barbalinardo, Marianna; Kyndiah, Adrica; Murgia, Mauro; Cramer, Tobias; Biscarini, Fabio; Vuillaume, Dominique

    2016-01-01

    We demonstrate an electrolyte-gated hybrid nanoparticle/organic synapstor (synapse-transistor, termed EGOS) that exhibits short-term plasticity as biological synapses. The response of EGOS makes it suitable to be interfaced with neurons: short-term plasticity is observed at spike voltage as low as 50 mV (in a par with the amplitude of action potential in neurons) and with a typical response time in the range of tens milliseconds. Human neuroblastoma stem cells are adhered and differentiated into neurons on top of EGOS. We observe that the presence of the cells does not alter short-term plasticity of the device.

  15. The design and fabrication on gate type resonant tunneling transistor

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    In light of fabricating resonant tunneling diode(RTD),in this paper a GaAs-based resonant tunneling transistor with gate structure(GRTT)has been designed and fabricated successfully.A systematic depiction centers on the designs of material structure,device structure,photo lithography mask,fabrication of device and the measurement and analysis of parameters.The fabricated GRTT has a maximum PVCR of 46 and a maximum transconductance of 8 mS.The work lays the foundation for further improvement on the performance and parameters of RTT.

  16. Electrical Characteristics of Copper Phthalocyanine Thin-Film Transistors with Polyamide-6/Polytetrafluoroethylene Gate Insulator

    Institute of Scientific and Technical Information of China (English)

    YU Shun-Yang; XU Shi-Ai; MA Dong-Ge

    2007-01-01

    Polyamide-6(PA 6)/polytetrafluoroethylene is studied as a potential gate dielectric for flexible organic thin film transistors.The salne method used for the formation of organic semiconductor and gate dielectric films greatly simplifies the fabrication process of devices.The fabricated transistors show good electrical characteristics.Ambipolar behaviour is observed even when the device is operated in air.

  17. Scaling carbon nanotube complementary transistors to 5-nm gate lengths

    Science.gov (United States)

    Qiu, Chenguang; Zhang, Zhiyong; Xiao, Mengmeng; Yang, Yingjun; Zhong, Donglai; Peng, Lian-Mao

    2017-01-01

    High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

  18. Simulation-based study of negative capacitance double-gate junctionless transistors with ferroelectric gate dielectric

    Science.gov (United States)

    Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

    2016-12-01

    In this work, a kind of negative capacitance double-gate junctionless transistor (NC-DG-JLT) with ferroelectric (FE) gate dielectric and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure is proposed. It is demonstrated that NC-DG-JLTs can lower off-state current, improve on-state drain current, and lower subthreshold swing at the same time compared with its conventional DG JLT counterpart using numerical simulation. The steep subthreshold swing (SS detail. The low off-state current and high on/off current ratio could be obtained even for ultra-small transistors by optimizing the device parameters. NC-DG-JLTs have a great potential for low power dissipation applications.

  19. Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module

    Science.gov (United States)

    2015-02-01

    Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module by Gregory K Ovrebo ARL-TR-7210...ARL-TR-7210 February 2015 Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module Gregory K... Bipolar Transistor (IGBT) Power Module 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) Gregory K Ovrebo 5d

  20. Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate

    CERN Document Server

    Kumar, Manoj; Pandey, Sujata

    2012-01-01

    In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272$\\mu$W in 0.35$\\mu$m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542$\\mu$W. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35$\\mu$m CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit's shows better performance in terms of power consumption and transistor count.

  1. Infrared light gated MoS₂ field effect transistor.

    Science.gov (United States)

    Fang, Huajing; Lin, Ziyuan; Wang, Xinsheng; Tang, Chun-Yin; Chen, Yan; Zhang, Fan; Chai, Yang; Li, Qiang; Yan, Qingfeng; Chan, H L W; Dai, Ji-Yan

    2015-12-14

    Molybdenum disulfide (MoS₂) as a promising 2D material has attracted extensive attentions due to its unique physical, optical and electrical properties. In this work, we demonstrate an infrared (IR) light gated MoS₂ transistor through a device composed of MoS₂ monolayer and a ferroelectric single crystal Pb(Mg(1/3)Nb(2/3))O₃-PbTiO₃ (PMN-PT). With a monolayer MoS₂ onto the top surface of (111) PMN-PT crystal, the drain current of MoS₂ channel can be modulated with infrared illumination and this modulation process is reversible. Thus, the transistor can work as a new kind of IR photodetector with a high IR responsivity of 114%/Wcm⁻². The IR response of MoS₂ transistor is attributed to the polarization change of PMN-PT single crystal induced by the pyroelectric effect which results in a field effect. Our result promises the application of MoS₂ 2D material in infrared optoelectronic devices. Combining with the intrinsic photocurrent feature of MoS₂ in the visible range, the MoS₂ on ferroelectric single crystal may be sensitive to a broadband wavelength of light.

  2. Organic transistors making use of room temperature ionic liquids as gating medium

    Science.gov (United States)

    Hoyos, Jonathan Javier Sayago

    The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric

  3. Dual-gate thin-film transistors, integrated circuits and sensors

    NARCIS (Netherlands)

    Spijkman, M.-J.; Myny, K.; Smits, E.C.P.; Heremans, P.; Blom, P.W.M.; Leeuw, D.M. de

    2011-01-01

    The first dual-gate thin-film transistor (DGTFT) was reported in 1981 with CdSe as the semiconductor. Other TFT technologies such as a-Si:H and organic semiconductors have led to additional ways of making DGTFTs. DGTFTs contain a second gate dielectric with a second gate positioned opposite of the f

  4. Dual-Gate Thin-Film Transistors, Integrated Circuits and Sensors

    NARCIS (Netherlands)

    Spijkman, Mark-Jan; Myny, Kris; Smits, Edsger C. P.; Heremans, Paul; Blom, Paul W. M.; de Leeuw, Dago M.

    2011-01-01

    The first dual-gate thin-film transistor (DGTFT) was reported in 1981 with CdSe as the semiconductor. Other TFT technologies such as a-Si:H and organic semiconductors have led to additional ways of making DGTFTs. DGTFTs contain a second gate dielectric with a second gate positioned opposite of the f

  5. Unipolar organic transistor circuits made robust by dual-gate technology

    NARCIS (Netherlands)

    Myny, K.; Beenhakkers, M.J.; Aerle, N.A.J.M. van; Gelinck, G.H.; Genoe, J.; Dehaene, W.; Heremans, P.

    2011-01-01

    Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in the technology functions as a VT-control gate. Both zero-VGS-load and diode-load logic are investigated. The noise margin o

  6. Coulomb blockade in a Si channel gated by an Al single-electron transistor

    OpenAIRE

    Sun, L.; K. R. Brown; Kane, B. E.

    2007-01-01

    We incorporate an Al-AlO_x-Al single-electron transistor as the gate of a narrow (~100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET). Near the MOSFET channel conductance threshold, we observe oscillations in the conductance associated with Coulomb blockade in the channel, revealing the formation of a Si single-electron transistor. Abrupt steps present in sweeps of the Al transistor conductance versus gate voltage are correlated with single-electron charging events in the Si t...

  7. Solution-gated graphene transistors for chemical and biological sensors.

    Science.gov (United States)

    Yan, Feng; Zhang, Meng; Li, Jinhua

    2014-03-01

    Graphene has attracted much attention in biomedical applications for its fascinating properties. Because of the well-known 2D structure, every atom of graphene is exposed to the environment, so the electronic properties of graphene are very sensitive to charged analytes (ions, DNA, cells, etc.) or an electric field around it, which renders graphene an ideal material for high-performance sensors. Solution-gated graphene transistors (SGGTs) can operate in electrolytes and are thus excellent candidates for chemical and biological sensors, which have been extensively studied in the recent 5 years. Here, the device physics, the sensing mechanisms, and the performance of the recently developed SGGT-based chemical and biological sensors, including pH, ion, cell, bacterial, DNA, protein, glucose sensors, etc., are introduced. Their advantages and shortcomings, in comparison with some conventional techniques, are discussed. Conclusions and challenges for the future development of the field are addressed in the end.

  8. Total ionizing dose effects in multiple-gate field-effect transistor

    Science.gov (United States)

    Gaillardin, Marc; Marcandella, Claude; Martinez, Martial; Raine, Mélanie; Paillet, Philippe; Duhamel, Olivier; Richard, Nicolas

    2017-08-01

    This paper focuses on total ionizing dose (TID) effects induced in multiple-gate field-effect transistors. The impact of device architecture, geometry and scaling on the TID response of multiple-gate transistors is reviewed in both bulk and silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technologies. These innovating devices exhibit specific ionizing dose responses which strongly depend on their three-dimensional nature. Their TID responses may look like the one usually observed in planar two-dimensional bulk or SOI transistors, but multiple-gate devices can also behave like any other CMOS device.

  9. Isolated photosystem I reaction centers on a functionalized gated high electron mobility transistor.

    Science.gov (United States)

    Eliza, Sazia A; Lee, Ida; Tulip, Fahmida S; Mostafa, Salwa; Greenbaum, Elias; Ericson, M Nance; Islam, Syed K

    2011-09-01

    In oxygenic plants, photons are captured with high quantum efficiency by two specialized reaction centers (RC) called Photosystem I (PS I) and Photosystem II (PS II). The captured photon triggers rapid charge separation and the photon energy is converted into an electrostatic potential across the nanometer-scale (~6 nm) reaction centers. The exogenous photovoltages from a single PS I RC have been previously measured using the technique of Kelvin force probe microscopy (KFM). However, biomolecular photovoltaic applications require two-terminal devices. This paper presents for the first time, a micro-device for detection and characterization of isolated PS I RCs. The device is based on an AlGaN/GaN high electron mobility transistor (HEMT) structure. AlGaN/GaN HEMTs show high current throughputs and greater sensitivity to surface charges compared to other field-effect devices. PS I complexes immobilized on the floating gate of AlGaN/GaN HEMTs resulted in significant changes in the device characteristics under illumination. An analytical model has been developed to estimate the RCs of a major orientation on the functionalized gate surface of the HEMTs.

  10. Development of paper-gate transistor toward direct detection from microbiological fluids

    Science.gov (United States)

    Kajisa, Taira; Sakata, Toshiya

    2017-04-01

    In this study, a paper-gate transistor was developed to detect glucose using an extended-gate field-effect transistor (FET). A filter paper was used as an extended gate electrode, in which Au nanoparticles (AuNPs) modified with phenylboronic acids (PBAs) were included. PBA-AuNPs play an important role as a support to not only be entrapped in cellulose fibrils but also bind to the targeted glucose in a paper. The surface properties of PBA-AuNPs were investigated to elucidate the electrical properties of the paper-gate electrode using an absorption spectrum and a zeta potential analysis. Moreover, the paper-gate electrode enabled us to detect glucose at the micromolar level on the basis of the principle of FET devices. A platform based on the paper-gate transistor is suitable for a highly sensitive system to detect glucose in trace samples such as tears, sweat, and saliva in the future.

  11. A novel 10-nm physical gate length double-gate junction field effect transistor

    Institute of Scientific and Technical Information of China (English)

    Hou Xiao-Yu; Huang Ru; Chen Gang; Liu Sheng; Zhang Xing; Yu Bin; Wang Yang-Yuan

    2008-01-01

    A novel double-gate (DG) junction field effect transistor (JFET) with depletion operation mode is proposed in this paper.Compared with the conventional DG MOSFET,the novel DG JFET can achieve excellent performance with square body design,which relaxes the requirement on silicon film thickness of DG devices.Moreover,due to the structural symmetry,both p-type and n-type devices can be realized on exactly the same structure,which greatly simplifies integration.It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.

  12. Electrostatic control of polarity of α-MoTe2 transistors with dual top gates

    Science.gov (United States)

    Nakaharai, Shu; Yamamoto, Mahito; Ueno, Keiji; Lin, Yen-Fu; Li, Song-Lin; Tsukagoshi, Kazuhito

    2015-03-01

    Transition metal dichalcogenides have been expected for future applications in nanoelectronics due to their unique features of the atomically-thin structure. Using semiconducting α-molybdenum ditelluride (α-MoTe2) , we realized field effect transistors (FETs) in which the polarity (n- or p-type) can be electrostatically controlled without impurity doping. The fabricated device had a pair of top gates (aluminum electrode on silicon dioxide) attached in series with a gap length of 100 nm in between. We experimentally performed transistor operations in both n-FET and p-FET modes in a single device by changing the voltage applied to one of the two top gates, which determined the transistor polarity, and sweeping the bias of the other gate. The demonstrated reversibility of the transistor polarity will contribute to the renovated architecture of logic circuits with lower numbers of transistors and hence the lower power consumption than the conventional technology.

  13. Ambipolar Organic Tri-Gate Transistor for Low-Power Complementary Electronics.

    Science.gov (United States)

    Torricelli, Fabrizio; Ghittorelli, Matteo; Smits, Edsger C P; Roelofs, Christian W S; Janssen, René A J; Gelinck, Gerwin H; Kovács-Vajna, Zsolt M; Cantatore, Eugenio

    2016-01-13

    Ambipolar transistors typically suffer from large off-current inherently due to ambipolar conduction. Using a tri-gate transistor it is shown that it is possible to electrostatically switch ambipolar polymer transistors from ambipolar to unipolar mode. In unipolar mode, symmetric characteristics with an on/off current ratio of larger than 10(5) are obtained. This enables easy integration into low-power complementary logic and volatile electronic memories.

  14. Highly stable carbon nanotube top-gate transistors with tunable threshold voltage

    NARCIS (Netherlands)

    Wang, H.; Cobb, B.; Breemen, A. van; Gelinck, G.H.; Bao, Z.

    2014-01-01

    Carbon-nanotube top-gate transistors with fluorinated dielectrics are presented. With PTrFE as the dielectric, the devices have absent or small hysteresis at different sweep rates and excellent bias-stress stability under ambient conditions. Ambipolar single-walled carbon nanotube (SWNT) transistors

  15. Electrolyte-gated organic field-effect transistor for selective reversible ion detection.

    Science.gov (United States)

    Schmoltner, Kerstin; Kofler, Johannes; Klug, Andreas; List-Kratochvil, Emil J W

    2013-12-17

    An ion-sensitive electrolyte-gated organic field-effect transistor for selective and reversible detection of sodium (Na(+) ) down to 10(-6) M is presented. The inherent low voltage - high current operation of these transistors in combination with a state-of-the-art ion-selective membrane proves to be a novel, versatile modular sensor platform.

  16. Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

    Science.gov (United States)

    Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

    2016-06-15

    Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

  17. Radiation Resistance of Fluorine-Implanted PNP Using Gated-Controlled Lateral PNP Transistor Structure

    Institute of Scientific and Technical Information of China (English)

    Xin Wang; Wu Lu; Wu-Ying Ma; Qi Guo; Zhi-Kuan Wang; Cheng-Fa He; Mo-Han Liu

    2016-01-01

    The radiation damage responses of fluorinated and non-fluorinated lateral PNP transistors are studied with specially designed gated-controlled lateral PNP transistors that allow for the extraction of the oxide trapped charge (Not) and interface trap (Nit) densities.All the samples are exposed in the Co-60γ ray with the dose rate of 0.5 Gy(Si)/s.After the irradiation,the buildup of Not and Nit of the samples with total dose is investigated by the gate sweep test technique.The results show that the radiation resistance of fluorinated lateral PNP transistors is significantly enhanced compared with the non-fluorinated ones.

  18. Modeling and simulation study of novel Double Gate Ferroelectric Junctionless (DGFJL) transistor

    Science.gov (United States)

    Mehta, Hema; Kaur, Harsupreet

    2016-09-01

    In this work we have proposed an analytical model for Double Gate Ferroelectric Junctionless Transistor (DGFJL), a novel device, which incorporates the advantages of both Junctionless (JL) transistor and Negative Capacitance phenomenon. A complete drain current model has been developed by using Landau-Khalatnikov equation and parabolic potential approximation to analyze device behavior in different operating regions. It has been demonstrated that DGFJL transistor acts as a step-up voltage transformer and exhibits subthreshold slope values less than 60 mV/dec. In order to assess the advantages offered by the proposed device, extensive comparative study has been done with equivalent Double Gate Junctionless Transistor (DGJL) transistor with gate insulator thickness same as ferroelectric gate stack thickness of DGFJL transistor. It is shown that incorporation of ferroelectric layer can overcome the variability issues observed in JL transistors. The device has been studied over a wide range of parameters and bias conditions to comprehensively investigate the device design guidelines to obtain a better insight into the application of DGFJL as a potential candidate for future technology nodes. The analytical results so derived from the model have been verified with simulated results obtained using ATLAS TCAD simulator and a good agreement has been found.

  19. Study of total ionizing dose radiation effects on enclosed gate transistors in a commercial CMOS technology

    Institute of Scientific and Technical Information of China (English)

    Li Dong-Mei; Wang Zhi-Hua; Huangfu Li-Ying; Gou Qiu-Jing

    2007-01-01

    This paper studies the total ionizing dose radiation effects on MOS (metal-oxide-semiconductor) transistors with normal and enclosed gate layout in a standard commercial CMOS (compensate MOS) bulk process. The leakage current, threshold voltage shift, and transconductance of the devices were monitored before and after γ-ray irradiation.The parameters of the devices with different layout under different bias condition during irradiation at different total dose are investigate. The results show that the enclosedosed layout not only effectively eliminates the leakage but also improves the performance of threshold voltage and transconductance for NMOS (n-type channel MOS) transistors. The experimental results also indicate that analogue bias during irradiation is the worst case for enclosed gate NMOS. There is no evident different behaviour observed between normal PMOS (p-type channel MOS) transistors and enclosed gate PMOS transistors.

  20. Experimental study on x-rays dose enhancement effects for floating gate ROMs

    CERN Document Server

    Guo Hong Xia; Chen Yu Sheng; Han Fu Bin; He Chao Hui; Zhao Hui

    2002-01-01

    Experimental results of x-ray dose enhancement effects are given for floating gate read-only memory (ROMs) irradiated in the Beijing Synchrotron Radiation Facility. The wrong byte numbers vs. total irradiation dose have been tested and the equivalent relation of total dose damage is provided compared the response of devices irradiated with sup 6 sup 0 Co gamma-ray source. The x-ray dose enhancement factors for floating gate ROMs are obtained firstly in China. These results can be an effective evaluation data for x-rays radiation hardening technology

  1. Electrolyte gate dependent high-frequency measurement of graphene field-effect transistor for sensing applications

    OpenAIRE

    Fu, W.; El Abbassi, M.; Hasler, T.; M. Jung; M. Steinacher; Calame, M.; Schönenberger,C.; Puebla-Hellmann, G.; Hellmüller, S.; T. Ihn; Wallraff, A.

    2014-01-01

    We performed radiofrequency (RF) reflectometry measurements at 2.4 GHz on electrolyte-gated graphene field-effect transistors (GFETs) utilizing a tunable stub-matching circuit for impedance matching. We demonstrate that the gate voltage dependent RF resistivity of graphene can be deduced even in the presence of the electrolyte which is in direct contact with the graphene layer. The RF resistivity is found to be consistent with its DC counterpart in the full gate voltage range. Furthermore, in...

  2. High-Performance Flexible Organic Nano-Floating Gate Memory Devices Functionalized with Cobalt Ferrite Nanoparticles.

    Science.gov (United States)

    Jung, Ji Hyung; Kim, Sunghwan; Kim, Hyeonjung; Park, Jongnam; Oh, Joon Hak

    2015-10-07

    Nano-floating gate memory (NFGM) devices are transistor-type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe2O4) nanoparticles (NPs) as charge trap sites and pentacene as a p-type semiconductor. Monodisperse CoFe2O4 NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle-particle interactions. CoFe2O4 NP-based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I(on)/I(off)) of ≈2.98 × 10(3), and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe2O4 NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifies the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and flexible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly flexible, high-performance organic memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  3. Effects of Ambient Air and Temperature on Ionic Gel Gated Single-Walled Carbon Nanotube Thin-Film Transistor and Circuits.

    Science.gov (United States)

    Li, Huaping; Zhou, Lili

    2015-10-21

    Single-walled carbon nanotube thin-film transistor (SWCNT TFT) and circuits were fabricated by fully inkjet printing gold nanoparticles as source/drain electrodes, semiconducting SWCNT thin films as channel materials, PS-PMMA-PS/EMIM TFSI composite gel as gate dielectrics, and PEDOT/PSS as gate electrodes. The ionic gel gated SWCNT TFT shows reversible conversion from p-type transistor behavior in air to ambipolar features under vacuum due to reversible oxygen doping in semiconducting SWCNT thin films. The threshold voltages of ionic gel gated SWCNT TFT and inverters are largely shifted to the low value (0.5 V for p-region and 1.0 V for n-region) by vacuum annealing at 140 °C to exhausively remove water that is incorporated in the ionic gel as floating gates. The vacuum annealed ionic gel gated SWCNT TFT shows linear temperature dependent transconductances and threshold voltages for both p- and n-regions. The strong temperature dependent transconductances (0.08 μS/K for p-region, 0.4 μS/K for n-region) indicate their potential application in thermal sensors. In the other hand, the weak temperature dependent threshold voltages (-1.5 mV/K for p-region, -1.1 mV/K for n-region) reflect their excellent thermal stability.

  4. Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

    Science.gov (United States)

    Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

    2009-01-01

    Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

  5. The Substrate is a pH-Controlled Second Gate of Electrolyte-Gated Organic Field-Effect Transistor.

    Science.gov (United States)

    Di Lauro, Michele; Casalini, Stefano; Berto, Marcello; Campana, Alessandra; Cramer, Tobias; Murgia, Mauro; Geoghegan, Mark; Bortolotti, Carlo A; Biscarini, Fabio

    2016-11-23

    Electrolyte-gated organic field-effect transistors (EGOFETs), based on ultrathin pentacene films on quartz, were operated with electrolyte solutions whose pH was systematically changed. Transistor parameters exhibit nonmonotonic variation versus pH, which cannot be accounted for by capacitive coupling through the Debye-Helmholtz layer. The data were fitted with an analytical model of the accumulated charge in the EGOFET, where Langmuir adsorption was introduced to describe the pH-dependent charge buildup at the quartz surface. The model provides an excellent fit to the threshold voltage and transfer characteristics as a function of the pH, which demonstrates that quartz acts as a second gate controlled by pH and is mostly effective from neutral to alkaline pH. The effective capacitance of the device is always greater than the capacitance of the electrolyte, thus highlighting the role of the substrate as an important active element for amplification of the transistor response.

  6. A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

    Science.gov (United States)

    Edmonds, L. D.

    2016-01-01

    Since advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

  7. A Novel Quadratic Buck-Boost DC-DC Converter without Floating Gate-Driver

    DEFF Research Database (Denmark)

    Mostaan, Ali; A. Gorji, Saman; N. Soltani, Mohsen

    2016-01-01

    for floating gate driver. In addition, the voltage stress of one of the switches is lower than the existing quadratic buck-boost converters. Performance of the analytical results is validated using both simulation in MATLAB/SIMULINK and experimental tests where the proposed converter is evaluated in both buck...

  8. A Novel Quadratic Buck-Boost DC-DC Converter without Floating Gate-Driver

    DEFF Research Database (Denmark)

    Mostaan, Ali; A. Gorji, Saman; N. Soltani, Mohsen

    2016-01-01

    for floating gate driver. In addition, the voltage stress of one of the switches is lower than the existing quadratic buck-boost converters. Performance of the analytical results is validated using both simulation in MATLAB/SIMULINK and experimental tests where the proposed converter is evaluated in both buck...

  9. A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

    2015-01-01

    A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

  10. Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

    OpenAIRE

    S. M. Rezaul Hasan; Yufridin Wahab

    2002-01-01

    This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without a...

  11. Molecular doping effect in bottom-gate, bottom-contact pentacene thin-film transistors

    OpenAIRE

    Wakatsuki, Yusuke; Noda, Kei; Wada, Yasuo; Toyabe, Toru; Matsushige, Kazumi

    2011-01-01

    A bottom-gate, bottom-contact (BGBC) organic thin-film transistor (OTFT) with carrier-doped regions over source-drain electrodes was investigated. Device simulation with our originally developed device simulator demonstrates that heavily doped layers (p+ layers) on top of the source-drain contact region can compensate the deficiency of charge carriers at the source-channel interface during transistor operation, leading to the increase of the drain current and the apparent field-effect mobilit...

  12. A Printed Biosensor Based on an Organic Electrochemical Transistor with Mediated Gate Electrode

    OpenAIRE

    Hedborg, Julia

    2012-01-01

    Biosensor technology is an expanding field of research and there is a great market demand for low-cost disposable sensors. The aim of this project was to come up with a printed, disposable biosensor for glucose based on an organic electrochemical transistor (OECT). The organic semiconductor PEDOT:PSS was used as the material for the transistor channel and the gate electrode was made of carbon bulk modified with the different redox mediators potassium ferricyanide and ferrocene and the catalys...

  13. High mobility polymer gated organic field effect transistor using zinc phthalocyanine

    Indian Academy of Sciences (India)

    K R Rajesh; V Kannan; M R Kim; Y S Chae; J K Rhee

    2014-02-01

    Organic thin film transistors were fabricated using evaporated zinc phthalocyanine as the active layer. Parylene film prepared by chemical vapour deposition was used as the organic gate insulator. The annealing of the samples was performed at 120°C for 3 h. At room temperature, these transistors exhibit -type conductivity with field-effect mobilities ranging from 0.025–0.037 cm2/Vs and a (on/off) ratio of ∼ 103. The effect of annealing on transistor characteristics is discussed.

  14. Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

    Energy Technology Data Exchange (ETDEWEB)

    Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Wan, Xiang; Shi, Yi, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2016-01-25

    The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

  15. Vertical Ge and GeSn heterojunction gate-all-around tunneling field effect transistors

    Science.gov (United States)

    Schulze, Jörg; Blech, Andreas; Datta, Arnab; Fischer, Inga A.; Hähnel, Daniel; Naasz, Sandra; Rolseth, Erlend; Tropper, Eva-Maria

    2015-08-01

    We present experimental results on the fabrication and characterization of vertical Ge and GeSn heterojunction Tunneling Field Effect Transistors (TFETs). A gate-all-around process with mesa diameters down to 70 nm is used to reduce leakage currents and improve electrostatic control of the gate over the transistor channel. An ION = 88.4 μA/μm at VDS = VG = -2 V is obtained for a TFET with a 10 nm Ge0.92Sn0.08 layer at the source/channel junction. We discuss further possibilities for device improvements.

  16. Scanning Kelvin probe microscopy on organic field-effect transistors during gate bias stress

    Science.gov (United States)

    Mathijssen, S. G. J.; Cölle, M.; Mank, A. J. G.; Kemerink, M.; Bobbert, P. A.; de Leeuw, D. M.

    2007-05-01

    The reliability of organic field-effect transistors is studied using both transport and scanning Kelvin probe microscopy measurements. A direct correlation between the current and potential of a p-type transistor is demonstrated. During gate bias stress, a decrease in current is observed, that is correlated with the increased curvature of the potential profile. After gate bias stress, the potential changes consistently in all operating regimes: the potential profile gets more convex, in accordance with the simultaneously observed shift in threshold voltage. The changes of the potential are attributed to positive immobile charges, which contribute to the potential, but not to the current.

  17. Simulation and Finite Element Analysis of Electrical Characteristics of Gate-all-Around Junctionless Nanowire Transistors

    Directory of Open Access Journals (Sweden)

    Neel Chatterjee

    2016-03-01

    Full Text Available Gate all around nanowire transistors is one of the widely researched semiconductor devices, which has shown possibility of further miniaturization of semiconductor devices. This structure promises better current controllability and also lowers power consumption. In this paper, Silicon and Indium Antimonide based nanowire transistors have been designed and simulated using Multiphysics simulation software to investigate on its electrical properties. Simulations have been carried out to study band bending, drain current and current density inside the device for changing gate voltages. Further analytical model of the device is developed to explain the physical mechanism behind the operation of the device to support the simulation result.

  18. Sensing small neurotransmitter-enzyme interaction with nanoporous gated ion-sensitive field effect transistors.

    Science.gov (United States)

    Kisner, Alexandre; Stockmann, Regina; Jansen, Michael; Yegin, Ugur; Offenhäusser, Andreas; Kubota, Lauro Tatsuo; Mourzina, Yulia

    2012-01-15

    Ion-sensitive field effect transistors with gates having a high density of nanopores were fabricated and employed to sense the neurotransmitter dopamine with high selectivity and detectability at micromolar range. The nanoporous structure of the gates was produced by applying a relatively simple anodizing process, which yielded a porous alumina layer with pores exhibiting a mean diameter ranging from 20 to 35 nm. Gate-source voltages of the transistors demonstrated a pH-dependence that was linear over a wide range and could be understood as changes in surface charges during protonation and deprotonation. The large surface area provided by the pores allowed the physical immobilization of tyrosinase, which is an enzyme that oxidizes dopamine, on the gates of the transistors, and thus, changes the acid-base behavior on their surfaces. Concentration-dependent dopamine interacting with immobilized tyrosinase showed a linear dependence into a physiological range of interest for dopamine concentration in the changes of gate-source voltages. In comparison with previous approaches, a response time relatively fast for detecting dopamine was obtained. Additionally, selectivity assays for other neurotransmitters that are abundantly found in the brain were examined. These results demonstrate that the nanoporous structure of ion-sensitive field effect transistors can easily be used to immobilize specific enzyme that can readily and selectively detect small neurotransmitter molecule based on its acid-base interaction with the receptor. Therefore, it could serve as a technology platform for molecular studies of neurotransmitter-enzyme binding and drugs screening.

  19. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    Science.gov (United States)

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors.

  20. Controlling charge injection by self-assembled monolayers in bottom-gate and top-gate organic field-effect transistors

    NARCIS (Netherlands)

    Gholamrezaie, F.; Asadi, K.; Kicken, R.A.H.J.; Langeveld-Voss, B.M.W.; Leeuw, D.M. de; Blom, P.W.M.

    2011-01-01

    We investigate the modulation of the charge injection in organic field-effect transistors with self-assembled monolayers (SAMs) using both a bottom-gate and a top-gate geometry. The current modulation by using SAMs is more pronounced in the top-gate geometry due to the better defined upper surface o

  1. Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

    OpenAIRE

    2016-01-01

    Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires’ suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-sca...

  2. Novel three-state quantum dot gate field effect transistor fabrication, modeling and applications

    CERN Document Server

    Karmakar, Supriya

    2014-01-01

    The book presents the fabrication and circuit modeling of quantum dot gate field effect transistor (QDGFET) and quantum dot gate NMOS inverter (QDNMOS inverter). It also introduces the development of a circuit model of QDGFET based on Berkley Short Channel IGFET model (BSIM). Different ternary logic circuits based on QDGFET are also investigated in this book. Advanced circuit such as three-bit and six bit analog-to-digital converter (ADC) and digital-to-analog converter (DAC) were also simulated.

  3. Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors.

    Science.gov (United States)

    Lepadatu, A M; Palade, C; Slav, A; Maraloiu, A V; Lazanu, S; Stoica, T; Logofatu, C; Teodorescu, V S; Ciurea, M L

    2017-04-28

    High performance trilayer memory capacitors with a floating gate of a single layer of Ge quantum dots (QDs) in HfO2 were fabricated using magnetron sputtering followed by rapid thermal annealing (RTA). The layer sequence of the capacitors is gate HfO 2/floating gate of single layer of Ge QDs in HfO 2/tunnel HfO 2/p-Si wafers. Both Ge and HfO2 are nanostructured by RTA at moderate temperatures of 600-700 °C. By nanostructuring at 600 °C, the formation of a single layer of well separated Ge QDs with diameters of 2-3 nm at a density of 4-5 × 10(15) m(-2) is achieved in the floating gate (intermediate layer). The Ge QDs inside the intermediate layer are arranged in a single layer and are separated from each other by HfO2 nanocrystals (NCs) about 8 nm in diameter with a tetragonal/orthorhombic structure. The Ge QDs in the single layer are located at the crossing of the HfO2 NCs boundaries. In the intermediate layer, besides Ge QDs, a part of the Ge atoms is segregated by RTA at the HfO2 NCs boundaries, while another part of the Ge atoms is present inside the HfO2 lattice stabilizing the tetragonal/orthorhombic structure. The fabricated capacitors show a memory window of 3.8 ± 0.5 V and a capacitance-time characteristic with 14% capacitance decay in the first 3000-4000 s followed by a very slow capacitance decrease extrapolated to 50% after 10 years. This high performance is mainly due to the floating gate of a single layer of well separated Ge QDs in HfO2, distanced from the Si substrate by the tunnel oxide layer with a precise thickness.

  4. Analyses of Short Channel Effects of Single-Gate and Double-Gate Graphene Nanoribbon Field Effect Transistors

    Directory of Open Access Journals (Sweden)

    Hojjatollah Sarvari

    2016-01-01

    Full Text Available Short channel effects of single-gate and double-gate graphene nanoribbon field effect transistors (GNRFETs are studied based on the atomistic pz orbital model for the Hamiltonian of graphene nanoribbon using the nonequilibrium Green’s function formalism. A tight-binding Hamiltonian with an atomistic pz orbital basis set is used to describe the atomistic details in the channel of the GNRFETs. We have investigated the vital short channel effect parameters such as Ion and Ioff, the threshold voltage, the subthreshold swing, and the drain induced barrier lowering versus the channel length and oxide thickness of the GNRFETs in detail. The gate capacitance and the transconductance of both devices are also computed in order to calculate the intrinsic cut-off frequency and switching delay of GNRFETs. Furthermore, the effects of doping of the channel on the threshold voltage and the frequency response of the double-gate GNRFET are discussed. We have shown that the single-gate GNRFET suffers more from short channel effects if compared with those of the double-gate structure; however, both devices have nearly the same cut-off frequency in the range of terahertz. This work provides a collection of data comparing different features of short channel effects of the single gate with those of the double gate GNRFETs. The results give a very good insight into the devices and are very useful for their digital applications.

  5. Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

    CERN Document Server

    Marmon, Jason K; Wang, Kai; Zhou, Weilie; Zhang, Yong

    2016-01-01

    Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore's law to the quantum region without requiring a FET's fabrication complexity, e.g. a physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x10^6 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/de...

  6. A Dynamic Simulation on Single Gate Junctionless Field Effect Transistor Based on Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    Roya Norani

    Full Text Available We study the I-V characteristics of single gate junctionless field effect transistor by device simulation. The sample FET is simulated at different channel lengths and the I-V curve changes due to variations of and channel length have been systematically ...

  7. Rendering high charge density of states in ionic liquid-gated MoS 2 transistors

    NARCIS (Netherlands)

    Lee, Y.; Lee, J.; Kim, S.; Park, H.S.

    2014-01-01

    We investigated high charge density of states (DOS) in the bandgap of MoS2 nanosheets with variable temperature measurements on ionic liquid-gated MoS2 transistors. The thermally activated charge transport indicates that the electrical current in the two-dimensional MoS 2 nanosheets under high charg

  8. Field Plate Optimization in Low-Power High-Gain Source-Gated Transistors

    NARCIS (Netherlands)

    Sporea,R.A.; Trainor, M.J.; Young, N.D.; Shannon, J.M.; Silva, S.R.P.

    2012-01-01

    Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high performance analog circuits fabricated in thin-film technologies. The quality of the saturation is greatly influenced by the design of the field-

  9. Polymer thin-film transistor based on a high dielectric constant gate insulator

    Institute of Scientific and Technical Information of China (English)

    Lü Wen; Peng Jun-Biao; Yang Kai-Xia; Lan Lin-Feng; Niu Qiao-Li; Cao Yong

    2007-01-01

    In this paper full polymer thin-film transistors (PTFTs) based on Poly (acrylonitrile) (PAN) as the gate dielectric and poly (2-methoxy-5-(2'-ethyl-hexyloxy)-1,4-phenylene-vinylene) (MEH-PPV) as the semiconductor layer were investigated by using different channel width/length ratios. Relatively high dielectric constant of the polymer dielectric layer (6.27) can remarkably reduce the threshold voltage of the transistors to below-3 V. Hole field-effect mobility of MEH-PPV of the PTFTs was about 4.8 × 10-4 cm2/Vs, and on/off current ratio was larger than 102, which was comparable with that of transistors with widely used Poly (4-vinyl phenol) (PVP) or SiO2 as gate dielectrics.

  10. Controlling the threshold voltage of SnO2 nanowire transistors with dual in-plane-gate structures gated by chitosan proton conductors

    Science.gov (United States)

    Liu, Huixuan; Tan, Rongri

    2017-05-01

    We fabricated novel dual in-plane-gate electric-double-layer (EDL) SnO2 nanowire transistors gated by chitosan using only one transmission electron microscopy (TEM) nickel grid mask at room temperature, and we successfully controlled its threshold voltage. By changing the second in-plane gate bias from 1.0 to -1.0 V, we tuned the threshold voltage of these transistors from -0.35 to 0.21 V. Their operation voltage was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance (4.24 µF/cm2). These dual in-plane-gate nanowire transistors could pave the way to useful low-voltage nanoelectronic devices.

  11. Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates

    Science.gov (United States)

    Kim, Hoon-Sik; Won, Sang Min; Ha, Young-Geun; Ahn, Jong-Hyun; Facchetti, Antonio; Marks, Tobin J.; Rogers, John A.

    2009-11-01

    This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ˜680 cm2/V s, on/off ratios >107, gate leakage current densities <2.8×10-7 A/cm2, and subthreshold slopes ˜120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.

  12. Organic nanodielectrics for low voltage carbon nanotube thin film transistors and complementary logic gates.

    Science.gov (United States)

    Hur, Seung-Hyun; Yoon, Myung-Han; Gaur, Anshu; Shim, Moonsub; Facchetti, Antonio; Marks, Tobin J; Rogers, John A

    2005-10-12

    We report the implementation of three dimensionally cross-linked, organic nanodielectric multilayers as ultrathin gate dielectrics for a type of thin film transistor device that uses networks of single-walled carbon nanotubes as effective semiconductor thin films. Unipolar n- and p-channel devices are demonstrated by use of polymer coatings to control the behavior of the networks. Monolithically integrating these devices yields complementary logic gates. The organic multilayers provide exceptionally good gate dielectrics for these systems and allow for low voltage, low hysteresis operation. The excellent performance characteristics suggest that organic dielectrics of this general type could provide a promising path to SWNT-based thin film electronics.

  13. VHDL-based programming environment for Floating-Gate analog memory cell

    Directory of Open Access Journals (Sweden)

    Carlos Alberto dos Reis Filho

    2005-02-01

    Full Text Available An implementation in CMOS technology of a Floating-Gate Analog Memory Cell and Programming Environment is presented. A digital closed-loop control compares a reference value set by user and the memory output and after cycling, the memory output is updated and the new value stored. The circuit can be used as analog trimming for VLSI applications where mechanical trimming associated with postprocessing chip is prohibitive due to high costs.

  14. Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

    Science.gov (United States)

    Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

    2015-05-27

    The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

  15. Delay Optimization of Low Power Reversible Gate using MOS Transistor Level design

    Directory of Open Access Journals (Sweden)

    Mukesh Kumar Kushwaha

    2015-10-01

    Full Text Available In Semiconductor industry has witnessed and explosive growth of integration of sophisticated multimedia base application onto mobile electronic gadget since the last decade. The critical concern in this aspect is to reduce the power consumption beyond a certain range of operating frequency. An important factor in the design of VLSI circuits is the choices of reversible logic. Basically conventionally digital circuits have been implemented using the logic gates, which were irreversible in nature only NOT gate are reversible. These irreversible gates produce energy loss due to the information bits lost during the operation information loss occurs because the total number of output signals generated is less than total number of input signals applied. In reversible if the input vector can be uniquely recovered from the output vector and if there is a one to one correspondence between its input and output logic. This paper present a new representation of existing reversible gate in MOS transistor. The MOS transistor designing using a gate diffusion input. Those new representation of MOS transistor has a hoping future in design of low power consumption circuits and high speed application

  16. Coupling between electrolyte and organic semiconductor in electrolyte-gated organic field effect transistors (Conference Presentation)

    Science.gov (United States)

    Biscarini, Fabio; Di Lauro, Michele; Berto, Marcello; Bortolotti, Carlo A.; Geerts, Yves H.; Vuillaume, Dominique

    2016-11-01

    Organic field effect transistors (OFET) operated in aqueous environments are emerging as ultra-sensitive biosensors and transducers of electrical and electrochemical signals from a biological environment. Their applications range from detection of biomarkers in bodily fluids to implants for bidirectional communication with the central nervous system. They can be used in diagnostics, advanced treatments and theranostics. Several OFET layouts have been demonstrated to be effective in aqueous operations, which are distinguished either by their architecture or by the respective mechanism of doping by the ions in the electrolyte solution. In this work we discuss the unification of the seemingly different architectures, such as electrolyte-gated OFET (EGOFET), organic electrochemical transistor (OECT) and dual-gate ion-sensing FET. We first demonstrate that these architectures give rise to the frequency-dependent response of a synapstor (synapse-like transistor), with enhanced or depressed modulation of the output current depending on the frequency of the time-dependent gate voltage. This behavior that was reported for OFETs with embedded metal nanoparticles shows the existence of a capacitive coupling through an equivalent network of RC elements. Upon the systematic change of ions in the electrolyte and the morphology of the charge transport layer, we show how the time scale of the synapstor is changed. We finally show how the substrate plays effectively the role of a second bottom gate, whose potential is actually fixed by the pH/composition of the electrolyte and the gate voltage applied.

  17. Fabrication of Pentacene Thin-Film Transistors with Patterned Polyimide Photoresist as Gate Dielectrics and Research of Their Degradation

    Institute of Scientific and Technical Information of China (English)

    LIANG Yan; DONG Gui-Fang; HU Yuan-Chuan; HU Yan; WANG Li-Duo; QIU Yong

    2004-01-01

    @@ Pentacene organic thin-film transistors using commercial photoresist as gate dielectrics were fabricated. The photoresist was spin-coated and directly patterned by photolithography. As a result, the fabrication processes were greatly reduced. With the characteristics of the transistors measured, the degradation of the transistors was investigated. In the search for the factors causing degradation, a transistor using poly(methyl methacrylate)as the gate dielectric was also fabricated. It is regarded that the degradation is caused by the changes at the interface between photoresist and pentacene film.

  18. Nanoscaled biological gated field effect transistors for cytogenetic analysis

    DEFF Research Database (Denmark)

    Kwasny, Dorota; Dimaki, Maria; Andersen, Karsten Brandt;

    2014-01-01

    Cytogenetic analysis is the study of chromosome structure and function, and is often used in cancer diagnosis, as many chromosome abnormalities are linked to the onset of cancer. A novel label free detection method for chromosomal translocation analysis using nanoscaled field effect transistors...

  19. Plasma-Wave Enhanced THz-Performance of a Nanometer Side-Gated Transistor

    Directory of Open Access Journals (Sweden)

    K. Y. Xu

    2014-07-01

    Full Text Available By using a two-dimensional-three-dimensional (2D-3D combined ensemble Monte Carlo (EMC model, the performance of a nanometer side-gated transistor is studied at terahertz (THz region. The transistor is based on a GaN/AlGaN heterosturcture at whose hetero-interface a two-dimensional electron gas (2DEG is formed. And the side-gate of the transistor is intentionally designed as an insulating trench with a 2DEG area in the center. Simulation results reveal that at low working frequency the performances of the transistor are almost frequency independent. However when the working frequency reaches THz region, obvious enhancements of the performances have been observed. The enhancements are accompanied by two peaks respectively at the frequency of about 4 THz and 6 THz. As such, the frequency-dependent performances become frequency nonmonotonic. Further analysis shows that the performance enhancements can be attributed to the excitations of 2D plasma waves in the side-gate which including a 2DEG area in its center.

  20. An LMS Programming Scheme and Floating-Gate Technology Enabled Trimmer-Less and Low Voltage Flame Detection Sensor

    Science.gov (United States)

    Iglesias-Rojas, Juan Carlos; Gomez-Castañeda, Felipe; Moreno-Cadenas, Jose Antonio

    2017-01-01

    In this paper, a Least Mean Square (LMS) programming scheme is used to set the offset voltage of two operational amplifiers that were built using floating-gate transistors, enabling a 0.95 VRMS trimmer-less flame detection sensor. The programming scheme is capable of setting the offset voltage over a wide range of values by means of electron injection. The flame detection sensor consists of two programmable offset operational amplifiers; the first amplifier serves as a 26 μV offset voltage follower, whereas the second amplifier acts as a programmable trimmer-less voltage comparator. Both amplifiers form the proposed sensor, whose principle of functionality is based on the detection of the electrical changes produced by the flame ionization. The experimental results show that it is possible to measure the presence of a flame accurately after programming the amplifiers with a maximum of 35 LMS-algorithm iterations. Current commercial flame detectors are mainly used in absorption refrigerators and large industrial gas heaters, where a high voltage AC source and several mechanical trimmings are used in order to accurately measure the presence of the flame. PMID:28613250

  1. An LMS Programming Scheme and Floating-Gate Technology Enabled Trimmer-Less and Low Voltage Flame Detection Sensor.

    Science.gov (United States)

    Iglesias-Rojas, Juan Carlos; Gomez-Castañeda, Felipe; Moreno-Cadenas, Jose Antonio

    2017-06-14

    In this paper, a Least Mean Square (LMS) programming scheme is used to set the offset voltage of two operational amplifiers that were built using floating-gate transistors, enabling a 0.95 VRMS trimmer-less flame detection sensor. The programming scheme is capable of setting the offset voltage over a wide range of values by means of electron injection. The flame detection sensor consists of two programmable offset operational amplifiers; the first amplifier serves as a 26 μV offset voltage follower, whereas the second amplifier acts as a programmable trimmer-less voltage comparator. Both amplifiers form the proposed sensor, whose principle of functionality is based on the detection of the electrical changes produced by the flame ionization. The experimental results show that it is possible to measure the presence of a flame accurately after programming the amplifiers with a maximum of 35 LMS-algorithm iterations. Current commercial flame detectors are mainly used in absorption refrigerators and large industrial gas heaters, where a high voltage AC source and several mechanical trimmings are used in order to accurately measure the presence of the flame.

  2. Terahertz signal detection in a short gate length field-effect transistor with a two-dimensional electron gas

    Energy Technology Data Exchange (ETDEWEB)

    Vostokov, N. V., E-mail: vostokov@ipm.sci-nnov.ru; Shashkin, V. I. [Institute for Physics of Microstructures of the Russian Academy of Sciences, 603950 Nizhny Novgorod, Russia and N. I. Lobachevsky State University of Nizhny Novgorod, 603950 Nizhny Novgorod (Russian Federation)

    2015-11-28

    We consider the problem of non-resonant detection of terahertz signals in a short gate length field-effect transistor having a two-dimensional electron channel with zero external bias between the source and the drain. The channel resistance, gate-channel capacitance, and quadratic nonlinearity parameter of the transistor during detection as a function of the gate bias voltage are studied. Characteristics of detection of the transistor connected in an antenna with real impedance are analyzed. The consideration is based on both a simple one-dimensional model of the transistor and allowance for the two-dimensional distribution of the electric field in the transistor structure. The results given by the different models are discussed.

  3. Post annealing effect on the electrical properties of top-gate SWNT network transistors.

    Science.gov (United States)

    Kim, Un Jeong; Suh, D Y; Min, S C; Park, Wanjun

    2011-07-01

    High performance top-gate single walled carbon nanotube network transistors are fabricated with aluminum oxide (Al2O3) layer as a gate dielectric by atomic layer deposition. It exhibits large on/off ratio (>10(4)) due to selective growth of semiconducting tubes by the plasma enhanced chemical vapor deposition. I-V characteristics show p-type or n-type depending on the deposition temperature. We investigate the type dependent characteristics for the carrier polarities with the post annealing effect on the top-gate SWNT network transistors. The dramatic change in the polarity of the top-gate SWNT network transistors, from n-type to p-type due to conversion of I-V characteristics is observed by post-annealing at 350 degrees C for 30 minutes under vacuum. Our observation suggests that competition between electron transfer from the Al2O3 layers to the SWNT surface and electron capture by oxygen molecules adsorbed on the tube walls seems to be the key point for the V(th) change as a function of Al2O3 deposition temperature.

  4. Back-gate effects and mobility characterization in junctionless transistor

    Science.gov (United States)

    Parihar, Mukta Singh; Liu, Fanyu; Navarro, Carlos; Barraud, Sylvain; Bawedin, Maryline; Ionica, Irina; Kranti, Abhinav; Cristoloveanu, Sorin

    2016-11-01

    This work addresses the effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced Fully Depleted Silicon-on-Insulator (FDSOI) technology. A systematic methodology to extract and distinguish the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the transport properties of back channel in ultra-thin heavily doped JL devices. It is demonstrated that both volume and accumulation-layer mobility values increase when the front interface is in accumulation.

  5. Beyond the Nernst-limit with dual-gate ZnO ion-sensitive field-effect transistors

    NARCIS (Netherlands)

    Spijkman, M.; Smits, E.C.P.; Cillessen, J.F.M.; Biscarini, F.; Blom, P.W.M.; Leeuw, D.M. de

    2011-01-01

    The sensitivity of conventional ion-sensitive field-effect transistors (ISFETs) is limited to 59 mV/pH, which is the maximum detectable change in electrochemical potential according to the Nernst equation. Here we demonstrate a transducer based on a ZnO dual-gate field-effect transistor that breache

  6. Liquid crystal-gated-organic field-effect transistors with in-plane drain-source-gate electrode structure.

    Science.gov (United States)

    Seo, Jooyeok; Nam, Sungho; Jeong, Jaehoon; Lee, Chulyeon; Kim, Hwajeong; Kim, Youngkyoo

    2015-01-14

    We report planar liquid crystal-gated-organic field-effect transistors (LC-g-OFETs) with a simple in-plane drain-source-gate electrode structure, which can be cost-effectively prepared by typical photolithography/etching processes. The LC-g-OFET devices were fabricated by forming the LC layer (4-cyano-4'-pentylbiphenyl, 5CB) on top of the channel layer (poly(3-hexylthiophene), P3HT) that was spin-coated on the patterned indium-tin oxide (ITO)-coated glass substrates. The LC-g-OFET devices showed p-type transistor characteristics, while a current saturation behavior in the output curves was achieved for the 50-150 nm-thick P3HT (channel) layers. A prospective on/off ratio (>1 × 10(3)) was obtained regardless of the P3HT thickness, whereas the resulting hole mobility (0.5-1.1 cm(2)/(V s)) at a linear regime was dependent on the P3HT thickness. The tilted ordering of 5CB at the LC-P3HT interfaces, which is induced by the gate electric field, has been proposed as a core point of working mechanism for the present LC-g-OFETs.

  7. 100-nm-size ferroelectric-gate field-effect transistor with 108-cycle endurance

    Science.gov (United States)

    Van Hai, Le; Takahashi, Mitsue; Zhang, Wei; Sakai, Shigeki

    2015-08-01

    The fabrication process of 100-nm-size ferroelectric-gate field-effect transistors (FeFETs) with high endurance was reported. The FeFETs had Pt/Sr0.8Ca0.2Bi2Ta2O9 (SCBT)/HfO2/Si stacks where the Pt gate length was 100 nm. The FeFETs were successfully fabricated by integrating many technologies such as fine patterning of etching masks by electron-beam lithography, precise anisotropic etching of the gate stacks, well-controlled ion implantation for gate-self-aligned sources and drains, and the sidewall-cover process that we had developed. Good performances of the FeFETs were characterized by the endurance of 108 program-and-erase cycles with negligible threshold-voltage shift and good drain-current retention for 3.98 × 105 s.

  8. Electrochemical Single-Molecule Transistors with Optimized Gate Coupling

    DEFF Research Database (Denmark)

    Osorio, Henrry M.; Catarelli, Samantha; Cea, Pilar

    2015-01-01

    Electrochemical gating at the single molecule level of viologen molecular bridges in ionic liquids is examined. Contrary to previous data recorded in aqueous electrolytes, a clear and sharp peak in the single molecule conductance versus electrochemical potential data is obtained in ionic liquids....

  9. Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

    Directory of Open Access Journals (Sweden)

    S. M. Rezaul Hasan

    2002-01-01

    Full Text Available This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

  10. Compact model for short-channel symmetric double-gate junctionless transistors

    Science.gov (United States)

    Ávila-Herrera, F.; Cerdeira, A.; Paz, B. C.; Estrada, M.; Íñiguez, B.; Pavanello, M. A.

    2015-09-01

    In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25 nm to 500 nm and for doping concentrations of 5 × 1018 and 1 × 1019 cm-3, as well as for Si layer thickness of 10 and 15 nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.

  11. High performance In2O3 nanowire transistors using organic gate nanodielectrics

    Science.gov (United States)

    Ju, Sanghyun; Ishikawa, Fumiaki; Chen, Pochiang; Chang, Hsiao-Kang; Zhou, Chongwu; Ha, Young-geun; Liu, Jun; Facchetti, Antonio; Marks, Tobin J.; Janes, David B.

    2008-06-01

    We report the fabrication of high performance nanowire transistors (NWTs) using In2O3 nanowires as the active channel and a self-assembled nanodielectric (SAND) as the gate insulator. The SAND-based single In2O3 NWTs are controlled by individually addressed gate electrodes. These devices exhibit n-type transistor characteristics with an on-current of ˜25μA for a single In2O3 nanowire at 2.0Vds, 2.1Vgs, a subthreshold slope of 0.2V/decade, an on-off current ratio of 106, and a field-effect mobility of ˜1450cm2/Vs. These results demonstrate that SAND-based In2O3 NWTs are promising candidates for high performance nanoscale logic technologies.

  12. Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor

    Institute of Scientific and Technical Information of China (English)

    HE Jin; BIAN Wei; TAO Ya-Dong; LIU Feng; SONG Yan; ZHANG Xing

    2006-01-01

    A novel lateral double-gate tunnelling field effect transistor (DG-TFET) is studied and its performance is presented by a two-dimensional device simulation with code ISE. The result demonstrates that this new tunnelling transistor allows for the steeper sub-threshold swing below 60mV/dec, the super low supply voltage (operable at VDD < 0.3 V) and the rail-to-rail logic (significant on-state current at the drain-source voltage VDS = 50 mV)for the aggressive technology assumptions of the availability of high-k/metal stack with equivalent gate oxide thickness EOT =0.24 nm and the work function difference 4.5eV of materials.

  13. Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Kawanago, Takamasa, E-mail: kawanago.t.ab@m.titech.ac.jp; Oda, Shunri [Quantum Nanoelectronics Research Center (QNERC), Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo, 152-8550 (Japan)

    2016-01-25

    In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS{sub 2}) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS{sub 2} flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS{sub 2}/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS{sub 2}/SAM structure. The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS{sub 2} field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.

  14. Extended-gate organic field-effect transistor for the detection of histamine in water

    Science.gov (United States)

    Minamiki, Tsukuru; Minami, Tsuyoshi; Yokoyama, Daisuke; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

    2015-04-01

    As part of our ongoing research program to develop health care sensors based on organic field-effect transistor (OFET) devices, we have attempted to detect histamine using an extended-gate OFET. Histamine is found in spoiled or decayed fish, and causes foodborne illness known as scombroid food poisoning. The new OFET device possesses an extended gate functionalized by carboxyalkanethiol that can interact with histamine. As a result, we have succeeded in detecting histamine in water through a shift in OFET threshold voltage. This result indicates the potential utility of the designed OFET devices in food freshness sensing.

  15. Dual-Material Surrounding-Gate Metal-Oxide-Semiconductor Field Effect Transistors with Asymmetric Halo

    Institute of Scientific and Technical Information of China (English)

    LI Zun-Chao

    2009-01-01

    Asymmetrical halo and dual-material gate structure are used in the sub-100 nm surrounding-gate metal-oxide-semiconductor field effect transistor (MOSFET) to improve the performance. Using three-region parabolic po-tential distribution and universal boundary condition, analytical surface potential and threshold voltage models of the novel MOSFET are developed based on the solution of Poisson's equation. The performance of the MOS-FET is examined by the analytical models and the 3D numerical device simulator Davinci. It is shown that the novel MOSFET can suppress short channel effect and improve carrier transport efficiency. The derived analytical models agree well with Davinci.

  16. Development of 8-inch Key Processes for Insulated-Gate Bipolar Transistor

    Directory of Open Access Journals (Sweden)

    Guoyou Liu

    2015-09-01

    Full Text Available Based on the construction of the 8-inch fabrication line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor (DMOS+ insulated-gate bipolar transistor (IGBT technology and the fifth-generation trench gate IGBT technology, have been developed, realizing a great-leap forward technological development for the manufacturing of high-voltage IGBT from 6-inch to 8-inch. The 1600 A/1.7 kV and 1500 A/3.3 kV IGBT modules have been successfully fabricated, qualified, and applied in rail transportation traction system.

  17. Fabrication of pentacene organic field-effect transistors with polyimide gate dielectric layer

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    The organic field effect transistors had been fabricated using the pentacene by vacuum evaporation as the active layer, the polyimide by spin coating as insulator layer, and aluminum by vacuum evaporation as gate, source and drain electrodes respectively. The field-effect mobility of 0.079 cm2/V.s was tested at Vds=70 V, and on/off radio up to 1.7×104.

  18. Transparent, low-power pressure sensor matrix based on coplanar-gate graphene transistors.

    Science.gov (United States)

    Sun, Qijun; Kim, Do Hwan; Park, Sang Sik; Lee, Nae Yoon; Zhang, Yu; Lee, Jung Heon; Cho, Kilwon; Cho, Jeong Ho

    2014-07-16

    A novel device architecture for preparing a transparent and low-voltage graphene pressure-sensor matrix on plastic and rubber substrates is demonstrated. The coplanar gate configuration of the graphene transistor enables a simplified procedure. The resulting devices exhibit excellent device performance, including a high transparency of ca. 80% in the visible range, a low operating voltage less than 2 V, a high pressure sensitivity of 0.12 kPa(-1) , and excellent mechanical durability over 2500 cycles.

  19. Modeling and simulation of Double Gate Junctionless Transistor considering fringing field effects

    Science.gov (United States)

    Kumari, Vandana; Modi, Neel; Saxena, Manoj; Gupta, Mridula

    2015-05-01

    In the present work, the performance of DG-JL transistor has been analysed using analytical modeling scheme as well as 3D device simulation technique. Thus an advance two dimensional analytical sub-threshold drain current model for Double Gate Junctionless (DG-JL) Transistor is presented in this work by considering the impact of fringing field from the gate to source/drain region using conformal mapping technique. The results obtained from proposed model have been verified with the ATLAS 3D device simulation software results. The relevant Short Channel Effect parameters like threshold voltage roll off, Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (S) are also evaluated using modeling scheme. In addition to this, the suitability of DG-JL Transistor for low voltage digital and analog applications has been investigated through exhaustive device simulation using ATLAS 3D device simulation software only. In essence, this work provides the dependencies of the device performance on the physical device parameters of DG-JL transistor for its assessment for better digital and analog operation.

  20. High capacitance organic field-effect transistors with modified gate insulator surface

    Science.gov (United States)

    Majewski, L. A.; Schroeder, R.; Grell, M.; Glarvey, P. A.; Turner, M. L.

    2004-11-01

    In this paper, we report on flexible, high capacitance, pentacene, and regioregular poly(3-hexylthiophene) (rr-P3HT) organic field-effect transistors fabricated on metallized Mylar films. The gate insulator, Al2O3, was prepared by means of anodization. We show that covering the anodized gate insulator with an octadecyltrichlorosilane self-assembled monolayer or apoly(α-methylstyrene) capping layer has the same effect on carrier mobility as for thermally grown silicon oxide. In addition, temperature-dependent measurements of mobility were performed on transistors fabricated with and without modification of the gate dielectric. In the case of both the pentacene and the rr-P3HT transistors, the μ(T ) behavior shows that the cause of the mobility enhancement through surface modification is not a reduction in the level of energetic disorder (σ in Bässler's model), as in the case of the fully amorphous organic semiconductor poly(triarylamine) [Veres et al., Adv. Funct. Mater. 13, 199 (2003)]. It appears that the surface modification improves mobility by changing the morphology of the semiconducting films.

  1. Characterization and Modeling of a Floating Gate Dosimeter with Gamma and Protons at Various Energies

    CERN Document Server

    Danzeca, S; Brugger, M; Dusseau, L; Masi, A; Pineda, A; Spiezia, G

    2014-01-01

    In this work a prototype of a floating gate sensor FGDOS has been characterized with a Co-60 source and with protons. The dependency of the sensor sensitivity on the dose rate and accumulated Total Ionizing Dose (TID) are investigated. The proton test permits to measure the sensitivity of the sensor at different incoming particles energies. An analytical model of the sensor is presented in the paper and the theoretical sensitivity for the prototype of FGDOS is evaluated. Finally, the model allows to accurately measuring the charge yield for different particle types and different energies.

  2. Evaluation of nanocomposite gate insulators for flexible organic thin-film transistors.

    Science.gov (United States)

    Kim, Jin Soo; Cho, Sung Won; Kim, Ii; Hwang, Byeong Ung; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

    2014-11-01

    To develop physically flexible electronics, high performance and mechanical stability of component materials and devices are required. For a flexible display, a backplane with flexible thin-film transistors (TFTs) must be developed. Gate insulating materials with excellent electrical and mechanical properties are highly important to the development of flexible TFTs. We investigated nanocomposite gate dielectrics composed of polyimide (PI) because of their superior thermal stability, as well as different inorganic HfO2, TiO2, and Al2O3 nanoparticles with high dielectric constants. Nanocomposite gate dielectrics of HfO2 nanoparticles and PI lowered leakage current density and increased the relative dielectric constant compared to PI solely because of a high degree of dispersion. Pentacene TFTs with HfO2 nanocomposite gate insulators also showed higher field-effect mobility (μ), smaller subthreshold swing, and an enhanced on/off current ratio (I(on/off)) compared to those of the PI gate dielectric. In addition, mechanical cyclic bending tests involving bending cycles of 2 x 10(5) time sat a bending radius of 5 mm showed improvement in electrical stability of nanocomposite gate insulators with a change in leakage current density of nanocomposite gate insulators below 30%.

  3. Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing.

    Science.gov (United States)

    Park, Dong-Wook; Kim, Hyungsoo; Bong, Jihye; Mikael, Solomon; Kim, Tong June; Williams, Justin C; Ma, Zhenqiang

    2016-10-10

    Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm(2)/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics.

  4. Stability Diagrams of Single-Common-Gate Double-Dot Single-Electron Transistors with Arbitrary Junction and Gate Capacitances

    Science.gov (United States)

    Imai, Shigeru; Kato, Hiroki; Hiraoka, Yasuhiro

    2012-12-01

    Stability diagrams of single-common-gate double-dot single-electron transistors are drawn in the Vg-V plane using the exact formulas that represent Coulomb blockade conditions, where the gate, source, and drain voltages are Vg, -V/2, and V/2, respectively. The stability regions are arranged along the Vg axis with no overlap. If gate capacitances Cg1 and Cg2 satisfy Cg1/m1 = Cg2/m2 = C0, the stability diagram is periodic with the period of e/C0 along the Vg axis, where m1 and m2 are natural numbers prime to each other. The stability diagram is point-symmetrical with respect to the point (me/2C0, 0) for all integers m. If Vg increases at V = 0, electrons are transferred into the islands under a rule, which can be explained in terms of periodicity and symmetry. The detailed features are described for the cases of uniform gate capacitances and uniform junction capacitances.

  5. Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

    Science.gov (United States)

    Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

    2017-06-01

    Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air-SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand.

  6. Fast Robust Gate-Drivers with Easy Adjustable Voltage Ranges for Driving Normally-On Wide-Bandgap Power Transistors

    OpenAIRE

    Jacqmaer, Pieter; Everts, Jordi; Gelagaev, Ratmir; Tant, Peter; Driesen, Johan

    2010-01-01

    Wide-bandgap (WBG) semiconductors, such as gallium nitride (GaN), are more and more being used in switching power devices. An AlGaN/GaN/AlGaN Double Heterojunction Field Effect transistor (DHFET) was developed in previous work and needed to be tested. The used test circuit was a buck converter. This type of converter, in addition with the normally-on switching behaviour of the GaN-based transistors, requires dedicated gate drive circuitry, resulting in the development of three types of gate-d...

  7. ZnO piezoelectric fine wire gated graphene oxide field effect transistor.

    Science.gov (United States)

    Mohan, Rajneesh; Krishnamoorthy, Karthikeyan; Kim, Gui-Sik; Kim, Sang-Jae

    2013-05-01

    Here we report the fabrication and characteristics of graphene oxide (GO) field effect transistor gated with piezopotential of ZnO fine wires on a flexible substrate. The FET device consists of GO thin film on the bottom and ZnO piezoelectric fine wire (PFW) on the top. In the FET device the GO serves as a carrier transport channel and ZnO PFW acts as a gate. When the substrate is bent, a piezopotential is generated in the ZnO PFW. The piezopotential created by the strain in the ZnO PFW was used to control the carrier transport in the GO channel. This device demonstrates the application of piezoelectric ZnO PFW for creating the gating effect on the semiconducting performance of GO film.

  8. Performance of pentacene-based organic field effect transistors using different polymer gate dielectrics

    Institute of Scientific and Technical Information of China (English)

    WU Ren-lei; CHENG Xiao-man; ZHENG Hong; YIN Shou-gen

    2009-01-01

    Pentacene-based organic field effect transistors (OFETs) are fabricated using poly(methyl methacrylate) (PMMA) and polyimide (PI) as gate dielectrics, respectively. The fabricated OFETs exhibit reasonable device characteristics. The field-effect mobility, threshold voltage, and on/off current radio are determined to be 3.214 × 10-2 cm2 / Vs, -28 V, and 1 × 103 respectively for OFETs with PMMA as gate dielectrics, and 7.306×10-3cm2 / Vs, -21 V, and 2 ×102 for OFETs with PI. Furthermore, the dielectric properties of gate insulator layer are tested and the dipole effect at the semiconductor/dielectrics interface is also analyzed by a model of energy level diagram.

  9. Design Architecture of field-effect transistor with back gate electrode for biosensor application

    Science.gov (United States)

    Fathil, M. F. M.; Arshad, M. K. Md.; Hashim, U.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Adzhri, R.; Zaki, M.; Azman, A. H.

    2016-07-01

    This paper presents the preparation method of photolithography chrome mask design used in fabrication process of field-effect transistor with back gate biasing based biosensor. Initially, the chrome masks are designed by studying the process flow of the biosensor fabrication, followed by drawing of the actual chrome mask using the AutoCAD software. The overall width and length of the device is optimized at 16 mm and 16 mm, respectively. Fabrication processes of the biosensor required five chrome masks, which included source and drain formation mask, the back gate area formation mask, electrode formation mask, front gate area formation mask, and passivation area formation mask. The complete chrome masks design will be sent for chrome mask fabrication and for future use in biosensor fabrication.

  10. Three-Dimensional Nanodot-Type Floating Gate Memory Fabricated by Bio-Layer-by-Layer Method

    Science.gov (United States)

    Ohara, Kosuke; Zheng, Bin; Uenuma, Mutsunori; Ishikawa, Yasuaki; Shiba, Kiyotaka; Yamashita, Ichiro; Uraoka, Yukiharu

    2011-08-01

    The properties of a nanodot-type floating gate memory with a multilayered nanodot array were investigated. High-density and uniform cobalt bio-nanodot (Co-BND) arrays were stacked on a SiO2 tunnel oxide layer by a bio-layer-by-layer method (Bio-LBL). Memory properties, such as hysteresis width, charge retention, charging speed, and reliability, were improved by increasing the number of Co-BND arrays in a floating gate memory. This research confirmed that the proposed memory is promising for application in next-generation memory devices.

  11. High-Performance Wrap-Gated InGaAs Nanowire Field-Effect Transistors with Sputtered Dielectrics

    OpenAIRE

    Li-Fan Shen; SenPo Yip; Zai-xing Yang; Ming Fang; TakFu Hung; Pun, Edwin Y. B.; Ho, Johnny C.

    2015-01-01

    Although wrap-gated nanowire field-effect-transistors (NWFETs) have been explored as an ideal electronic device geometry for low-power and high-frequency applications, further performance enhancement and practical implementation are still suffering from electron scattering on nanowire surface/interface traps between the nanowire channel and gate dielectric as well as the complicated device fabrication scheme. Here, we report the development of high-performance wrap-gated InGaAs NWFETs using c...

  12. H-terminated diamond field effect transistor with ferroelectric gate insulator

    Energy Technology Data Exchange (ETDEWEB)

    Karaya, Ryota; Furuichi, Hiroki [Graduate School of Natural Science and Technology, Kanazawa University, Kanazawa, Ishikawa 920-1155 (Japan); Nakajima, Takashi [Department of Applied Physics, Tokyo University of Science, Katsushika-ku, Tokyo 125-8585 (Japan); Tokuda, Norio; Kawae, Takeshi, E-mail: kawae@ec.t.kanazawa-u.ac.jp [College of Science and Engineering, Kanazawa University, Kanazawa, Ishikawa 920-1155 (Japan)

    2016-06-13

    An H-terminated diamond field-effect-transistor (FET) with a ferroelectric vinylidene fluoride (VDF)-trifluoroethylene (TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film was deposited on the H-terminated diamond by the spin-coating method and low-temperature annealing was performed to suppress processing damage to the H-terminated diamond surface channel layer. The fabricated FET structure showed the typical properties of depletion-type p-channel FET and showed clear saturation of the drain current with a maximum value of 50 mA/mm. The drain current versus gate voltage curves of the proposed FET showed clockwise hysteresis loops due to the ferroelectricity of the VDF-TrFE gate insulator, and the memory window width was 19 V, when the gate voltage was swept from 20 to −20 V. The maximum on/off current ratio and the linear mobility were 10{sup 8} and 398 cm{sup 2}/V s, respectively. In addition, we modulated the drain current of the fabricated FET structure via the remnant polarization of the VDF-TrFE gate and obtained an on/off current ratio of 10{sup 3} without applying a DC gate voltage.

  13. Polysilsesquioxanes for Gate-Insulating Materials of Organic Thin-Film Transistors

    Directory of Open Access Journals (Sweden)

    Kimihiro Matsukawa

    2012-01-01

    Full Text Available Printable organic thin-film transistor (O-TFT is one of the most recognized technical issues nowadays. Our recent progress on the formation of organic-inorganic hybrid thin films consists of polymethylsilsesquioxane (PMSQ, and its applications for the gate-insulating layer of O-TFTs are introduced in this paper. PMSQ synthesized in toluene solution with formic acid catalyst exhibited the electric resistivity of higher than 1014 Ω cm after thermal treatment at 150°C, and the very low concentration of residual silanol groups in PMSQ was confirmed. The PMSQ film contains no mobile ionic impurities, and this is also important property for the practical use for the gate-insulating materials. In the case of top-contact type TFT using poly(3-hexylthiophene (P3HT with PMSQ gate-insulating layer, the device properties were comparable with the TFTs having thermally grown SiO2 gate-insulating layer. The feasibility of PMSQ as a gate-insulating material for O-TFTs, which was fabricated on a flexible plastic substrate, has been demonstrated. Moreover, by the modification of PMSQ, further functionalities, such as surface hydrophobicity, high permittivity that allows low driving voltage, and photocurability that allows photolithography, could be appended to the PMSQ gate-insulating layers.

  14. Strain Gated Bilayer Molybdenum Disulfide Field Effect Transistor with Edge Contacts.

    Science.gov (United States)

    Chai, Yu; Su, Shanshan; Yan, Dong; Ozkan, Mihrimah; Lake, Roger; Ozkan, Cengiz S

    2017-02-10

    Silicon nitride stress capping layer is an industry proven technique for increasing electron mobility and drive currents in n-channel silicon MOSFETs. Herein, the strain induced by silicon nitride is firstly characterized through the changes in photoluminescence and Raman spectra of a bare bilayer MoS2 (Molybdenum disulfide). To make an analogy of the strain-gated silicon MOSFET, strain is exerted to a bilayer MoS2 field effect transistor (FET) through deposition of a silicon nitride stress liner that warps both the gate and the source-drain area. Helium plasma etched MoS2 layers for edge contacts. Current on/off ratio and other performance metrics are measured and compared as the FETs evolve from back-gated, to top-gated and finally, to strain-gated configurations. While the indirect band gap of bilayer MoS2 at 0% strain is 1.25 eV, the band gap decreases as the tensile strain increases on an average of ~100 meV per 1% tensile strain, and the decrease in band gap is mainly due to lowering the conduction band at K point. Comparing top- and strain-gated structures, we find a 58% increase in electron mobility and 46% increase in on-current magnitude, signalling a benign effect of tensile strain on the carrier transport properties of MoS2.

  15. Transcap: A new integrated hybrid supercapacitor and electrolyte-gated transistor device (Presentation Recording)

    Science.gov (United States)

    Santato, Clara

    2015-10-01

    The boom in multifunctional, flexible, and portable electronics and the increasing need of low-energy cost and autonomy for applications ranging from wireless sensor networks for smart environments to biomedical applications are triggering research efforts towards the development of self-powered sustainable electronic devices. Within this context, the coupling of electronic devices (e.g. sensors, transistors) with small size energy storage systems (e.g. micro-batteries or micro-supercapacitors) is actively pursued. Micro-electrochemical supercapacitors are attracting much attention in electronics for their capability of delivering short power pulses with high stability over repeated charge/discharge cycling. For their high specific pseudocapacitance, electronically conducting polymers are well known as positive materials for hybrid supercapacitors featuring high surface carbon negative electrodes. The processability of both polymer and carbon is of great relevance for the development of flexible miniaturised devices. Electronically conducting polymers are even well known to feature an electronic conductivity that depends on their oxidation (p-doped state) and that it is modulated by the polymer potential. This property and the related pseudocapacitive response make polymer very attracting channel materials for electrolyte-gated (EG) transistors. Here, we propose a novel concept of "Trans-capacitor", an integrated device that exhibits the storage properties of a polymer/carbon hybrid supercapacitor and the low-voltage operation of an electrolyte-gated transistor.

  16. Bias-induced migration of ionized donors in amorphous oxide semiconductor thin-film transistors with full bottom-gate and partial top-gate structures

    Directory of Open Access Journals (Sweden)

    Mallory Mativenga

    2012-09-01

    Full Text Available Bias-induced charge migration in amorphous oxide semiconductor thin-film transistors (TFTs confirmed by overshoots of mobility after bias stressing dual gated TFTs is presented. The overshoots in mobility are reversible and only occur in TFTs with a full bottom-gate (covers the whole channel and partial top-gate (covers only a portion of the channel, indicating a bias-induced uneven distribution of ionized donors: Ionized donors migrate towards the region of the channel that is located underneath the partial top-gate and the decrease in the density of ionized donors in the uncovered portion results in the reversible increase in mobility.

  17. Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

    Science.gov (United States)

    Guerfi, Youssouf; Larrieu, Guilhem

    2016-04-01

    Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

  18. Organic Thin-Film Transistors Based on Vapor-Deposition Polymerized Gate Insulators

    Science.gov (United States)

    Pyo, S. W.; Lee, D. H.; Koo, J. R.; Kim, J. H.; Shim, J. H.; Kim, Y. K.

    2005-01-01

    In this study, we demonstrated that organic thin-film transistors (OTFTs) can be fabricated by using organic gate insulators using a vapor deposition polymerization (VDP) process. We found that electrical output characteristics in our organic thin-film transistors using a staggered-inverted top-contact structure show a saturated slope in the saturation region and a subthreshold nonlinearity in the triode region. The field-effect mobility, threshold voltage, and on-off current ratio of OTFTs using 4,4'-oxydiphthalic anhydride[ODPA]-4,4'-oxydianiline[ODA] and 2,2-bis(3,4-dicarboxyphenyl) hexafluoropropane dianhydride[6FDA]-[ODA] as gate insulators with a thickness of 0.45 μm were about 0.13-0.5 cm2/Vs, -7 V, and 104, respectively. To form polyimide as a gate insulator, the VDP process was also introduced instead of a spin-coating process, in which a polyimide film was codeposited by the high-vacuum thermal evaporation of ODPA and ODA, 6FDA and ODA, and cured at 150°C for 1 h followed by 200°C for 1 h after codeposition. To explain the differences in the electrical characteristics caused by the insulators, the morphology of pentacene on the polyimide from ODPA-ODA was compared with that from 6FDA-ODA, respectively.

  19. Impact of Scaling Gate Insulator Thickness on the Performance of Carbon Nanotube Field Effect Transistors (CNTFETs

    Directory of Open Access Journals (Sweden)

    Devi Dass

    2013-05-01

    Full Text Available As scaling down Si MOSFET devices degrade device performance in terms of short channel effects. Carbon nanotube field effect transistor (CNTFET is one of the novel nanoelectronics devices that overcome those MOSFET limitations. The carbon nanotube field effect transistors (CNTFETs have been explored and proposed to be the promising candidate for the next generation of integrated circuit (IC devices. To explore the role of CNTFETs in future integrated circuits, it is important to evaluate their performance. However, to do that we need a model that can accurately describe the behavior of the CNTFETs so that the design and evaluation of circuits using these devices can be made. In this paper, we have investigated the effect of scaling gate insulator thickness on the device performance of cylindrical shaped ballistic CNTFET in terms of transfer characteristics, output characteristics, average velocity, gm/Id ratio, mobile charge, quantum capacitance/insulator capacitance, drive current (Ion, Ion / Ioff ratio, transconductance, and output conductance. We concluded that the device metrics such as Ion, Ion / Ioff ratio, transconductance, and output conductance increases with the decrease in gate insulator thickness. Also, we concluded that the gate insulator thickness reduction causes subthreshold slope close to the theoretical limit of 60 mV/decade and DIBL close to zero at room temperature.

  20. Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

    Science.gov (United States)

    Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Hwajeong; Lee, Joon-Hyung; Park, Soo-Young; Kang, Inn-Kyu; Kim, Youngkyoo

    2014-09-01

    We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4'-pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm2/Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (VD) and gate (VG) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of VD and VG. The best voltage combination was VD = -0.2 V and VG = -1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors.

  1. Steep switching characteristics of single-gated feedback field-effect transistors

    Science.gov (United States)

    Kim, Minsuk; Kim, Yoonjoong; Lim, Doohyeok; Woo, Sola; Cho, Kyoungah; Kim, Sangsig

    2017-02-01

    In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I-V characteristics, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. Our proposed feedback field-effect transistors exhibit subthreshold swings of less than 0.1 mV dec-1, an on/off current ratio of approximately 1011, and an on-current of approximately 10-4 A at room temperature, demonstrating that the switching characteristics are superior to those of other silicon-based devices. In addition, the device parameters that affect the device performance, hysteresis characteristics, and temperature-dependent device characteristics are discussed in detail.

  2. The Bipolar Field-Effect Transistor: ⅩⅢ. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

    Institute of Scientific and Technical Information of China (English)

    薩支唐; 揭斌斌

    2009-01-01

    This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These ex-amples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impure-thin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concen-tration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

  3. Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors

    Science.gov (United States)

    Carrion, Enrique A.; Serov, Andrey Y.; Islam, Sharnali; Behnam, Ashkan; Malik, Akshay; Xiong, Feng; Bianchi, Massimiliano; Sordan, Roman; Pop, Eric

    2014-05-01

    We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple DC characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/um. In addition, using modeling and capacitance-voltage measurements we extract charge trap densities up to 10^12 1/cm^2 in the top gate dielectric (here Al2O3). Our study illustrates important time- and field-dependent imperfections of top-gated GFETs with high-k dielectrics, which must be carefully considered for future developments of this technology

  4. A CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) oscillator

    Science.gov (United States)

    Chin, Chi-Hang; Li, Ming-Huang; Chen, Chao-Yu; Wang, Yu-Lin; Li, Sheng-Shian

    2015-11-01

    A high-frequency CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) fabricated by a standard 0.35 μm 2-poly-4-metal CMOS-MEMS platform is implemented to enable a Pierce-type oscillator. The proposed arrayed RGFET exhibits low motional impedance of only 5 kΩ under a purely capacitive transduction and decent power handling capability. With such features, the implemented oscillator shows impressive phase noise of  -117 dBc Hz-1 at the far-from-carrier offset (1 MHz). In this work, we design a clamped-clamped beam (CCB) arrayed resonator utilizing a high-velocity mechanical coupling scheme to serve as the resonant-gate array. To achieve a functional arrayed RGFET, a corresponding FET array is directly placed underneath the resonant gate array to convert the motional current on the resonant-gate array into a voltage output with a tunable transconductance gain. To understand the behavior of the proposed device, an equivalent circuit model consisting of the resonant unit and FET is also provided. To verify the effects of the post-CMOS process on device performance, a conventional MOS I D current measurement is carried out. Finally, a CMOS-MEMS arrayed RGFET oscillator is realized by utilizing a Pierce oscillator architecture, showing decent phase noise performance that benefits from the array design to alleviate the nonlinear effect of the resonant gate.

  5. Field-effect and capacitive properties of water-gated transistors based on polythiophene derivatives

    Directory of Open Access Journals (Sweden)

    R. Porrazzo

    2015-01-01

    Full Text Available Recently, water-gated organic field-effect transistors (WGOFET have been intensively studied for their application in the biological field. Surprisingly, a very limited number of conjugated polymers have been reported so far. Here, we systematically explore a series of polythiophene derivatives, presenting different alkyl side chains lengths and orientation, and characterized by various morphologies: comparative evaluation of their performances allows highlighting the critical role played by alkyl side chains, which significantly affects the polymer/water interface capacitance. Reported results provide useful guidelines towards further development of WGOFETs and represent a step forward in the understanding of the polymer/water interface phenomena.

  6. Electrolyte-gated graphene field-effect transistors for detecting pH and protein adsorption.

    Science.gov (United States)

    Ohno, Yasuhide; Maehashi, Kenzo; Yamashiro, Yusuke; Matsumoto, Kazuhiko

    2009-09-01

    We investigated electrolyte-gated graphene field-effect transistors (GFETs) for electrical detecting pH and protein adsorptions. Nonfunctionalized single-layer graphene was used as a channel. GFETs immersed in an electrolyte showed transconductances 30 times higher than those in a vacuum and their conductances exhibited a direct linear increase with electrolyte pH, indicating their potential for use in pH sensor applications. We also attempted to direct surface-protein adsorption and showed that the conductance of GFETs increased with exposure to a protein at several hundred picomolar. The GFETs thus acted as highly sensitive electrical sensors for detecting pH and biomolecule concentrations.

  7. Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

    DEFF Research Database (Denmark)

    Pfreundt, Andrea

    with nanowire sensors functionalized using different modification schemes. To facilitate functionalization and measurement and as a first step towards integration into a point-of-care device, several microfluidic tools were developed for sample delivery to the sensor surface and as a modular platform......This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

  8. Electric Double Layer Gate Field-Effect Transistors Based on Si

    Science.gov (United States)

    Yanase, Takashi; Shimada, Toshihiro; Hasegawa, Tetsuya

    2010-04-01

    Electric double layer field-effect transistors (EDL-FETs) were fabricated using single crystal Si wafer as the active semiconductor and various characteristics were studied including dynamic response against step-function gate bias. The static FET mobility was more than 100 cm2 V-1 s-1. The response time of the drain current was 20 µs for ionic liquid and 3 ms for poly(ethylene glycol) (PEG) solution of LiBF4. Unexpected fast response was observed at a certain “speed up bias” condition. This effect will be useful to switching circuits using EDL-FETs.

  9. Organic thin film transistors with polymer brush gate dielectrics synthesized by atom transfer radical polymerization

    DEFF Research Database (Denmark)

    Pinto, J.C.; Whiting, G.L.; Khodabakhsh, S.

    2008-01-01

    , synthesized by atom transfer radical polymerization (ATRP), were used to fabricate low voltage OFETs with both evaporated pentacene and solution deposited poly(3-hexylthiophene). The semiconductor-dielectric interfaces in these systems were studied with a variety of methods including scanning force microscopy......Low operating voltage is an important requirement that must be met for industrial adoption of organic field-effect transistors (OFETs). We report here solution fabricated polymer brush gate insulators with good uniformity, low surface roughness and high capacitance. These ultra thin polymer films...

  10. Probing top-gated field effect transistor of reduced graphene oxide monolayer made by dielectrophoresis

    OpenAIRE

    Vasu, K. S.; Chakraborty, Biswanath; Sampath, S.; Sood, A. K.

    2010-01-01

    We demonstrate top-gated field effect transistor made of reduced graphene oxide (RGO) monolayer (graphene) by dielectrophoresis. Raman spectrum of RGO flakes of typical size of 5{\\mu}m x 5{\\mu}m show a single 2D band at 2687 cm-1, characteristic of a single layer graphene. The two probe current - voltage measurements of RGO flakes, deposited in between the patterned electrodes with a gap of 2.5 {\\mu}m using a.c. dielectrophoresis show ohmic behavior with a resistance of ~ 37k{\\Omega}. The tem...

  11. Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

    Science.gov (United States)

    Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

    2017-10-01

    Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

  12. Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

    CERN Document Server

    Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

    2010-01-01

    We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

  13. Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability

    Energy Technology Data Exchange (ETDEWEB)

    Chiou, Uio-Pu; Pan, Fu-Ming, E-mail: fmpan@faculty.nctu.edu.tw [Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu 30050, Taiwan (China); Shieh, Jia-Min, E-mail: jmshieh@narlabs.org.tw, E-mail: jmshieh@faculty.nctu.edu.tw [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (China); Yang, Chih-Chao [National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Huang, Wen-Hsien [Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu 30050, Taiwan (China); National Nano Device Laboratories, No. 26, Prosperity Road 1, Hsinchu 30078, Taiwan (China); Kao, Yo-Tsung [Departments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung University, Hsinchu 30010, Taiwan (China)

    2013-11-11

    We fabricated nano-crystalline Si (nc-Si:H) thin-film transistors (TFTs) with a double-metal-gate structure, which showed a high electron-mobility (μ{sub FE}) and adjustable threshold voltages (V{sub th}). The nc-Si:H channel and source/drain (S/D) of the multilayered TFT were deposited at 375 °C by inductively coupled plasma chemical vapor deposition. The low grain-boundary defect density of the channel layer is responsible for the high μ{sub FE} of 370 cm{sup 2}/V-s, a steep subthreshold slope of 90 mV/decade, and a low V{sub th} of −0.64 V. When biased with the double-gate driving mode, the device shows a tunable V{sub th} value extending from −1 V up to 2.7 V.

  14. Solvent Effects on the Transient Characteristics of Liquid-Gate Field Effect Transistors with Silicon Substrate

    Science.gov (United States)

    Yanase, Takashi; Hasegawa, Tetsuya; Nagahama, Taro; Shimada, Toshihiro

    2012-11-01

    The transient characteristics of electric double layer (EDL) gated field-effect transistors with Si as an active semiconductor were studied using various electrolyte solutions of LiBF4 by applying a step-function voltage to determine the optimum electrolyte for semiconductor circuits using EDLs. The tR, determined by EDL dynamics in the present experiment, was minimum as a function of the kind of solvent used owing to the competing effects of the EDL thickness and viscosity. The responses of the electrolyte solutions with various solvents at the same concentration were classified into three categories on the basis of tR: slow response of a complex-forming solvent, intermediate response of protic solvents, and fast response of nonprotic solvents. The best response time was 55 µs when a 1.0 M acetonitrile solution was used as the liquid-gate insulator.

  15. Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

    Science.gov (United States)

    Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

    2010-01-01

    Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

  16. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

    Science.gov (United States)

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-12-17

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

  17. Ionizing/displacement synergistic effects induced by gamma and neutron irradiation in gate-controlled lateral PNP bipolar transistors

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Chenhui, E-mail: wangchenhui@nint.ac.cn [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O. Box 69-10, Xi’an 710024 (China); Chen, Wei; Yao, Zhibin; Jin, Xiaoming; Liu, Yan; Yang, Shanchao [State Key Laboratory of Intense Pulsed Irradiation Simulation and Effect, Northwest Institute of Nuclear Technology, P.O. Box 69-10, Xi’an 710024 (China); Wang, Zhikuan [State Key Laboratory of Analog Integrated Circuit, Chongqing 400060 (China)

    2016-09-21

    A kind of gate-controlled lateral PNP bipolar transistor has been specially designed to do experimental validations and studies on the ionizing/displacement synergistic effects in the lateral PNP bipolar transistor. The individual and mixed irradiation experiments of gamma rays and neutrons are accomplished on the transistors. The common emitter current gain, gate sweep characteristics and sub-threshold sweep characteristics are measured after each exposure. The results indicate that under the sequential irradiation of gamma rays and neutrons, the response of the gate-controlled lateral PNP bipolar transistor does exhibit ionizing/displacement synergistic effects and base current degradation is more severe than the simple artificial sum of those under the individual gamma and neutron irradiation. Enough attention should be paid to this phenomenon in radiation damage evaluation. - Highlights: • A kind of gate-controlled lateral PNP bipolar transistor has been specially designed to facilitate the analysis of ionizing/displacement synergistic effects induced by the mixed irradiation of gamma and neutron. • The difference between ionizing/displacement synergistic effects and the simple sum of TID and displacement effects is analyzed. • The physical mechanisms of synergistic effects are explained.

  18. Fabrication and characterization of V-gate AlGaN/GaN high-electron-mobility transistors

    Institute of Scientific and Technical Information of China (English)

    Zhang Kai; Cao Meng-Yi; Chen Yong-He; Yang Li-Yuan; Wang Chong; Ma Xiao-Hua; Hao Yue

    2013-01-01

    V-gate GaN high-electron-mobility transistors (HEMTs) are fabricated and investigated systematically.A V-shaped recess geometry is obtained using an improved Si3N4 recess etching technology.Compared with standard HEMTs,the fabricated V-gate HEMTs exhibit a 17% higher peak extrinsic transconductance due to a narrowed gate foot.Moreover,both the gate leakage and current dispersion are dramatically suppressed simultaneously,although a slight degradation of frequency response is observed.Based on a two-dimensional electric field simulation using Silvaco "ATLAS" for both standard HEMTs and V-gate HEMTs,the relaxation in peak electric field at the gate edge is identified as the predominant factor leading to the superior performance of V-gate HEMTs.

  19. B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride–trifluoroethylene gate insulator

    Science.gov (United States)

    Karaya, Ryota; Baba, Ikki; Mori, Yosuke; Matsumoto, Tsubasa; Nakajima, Takashi; Tokuda, Norio; Kawae, Takeshi

    2017-10-01

    A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride–trifluoroethylene (VDF–TrFE) copolymer gate insulator was fabricated. The VDF–TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF–TrFE/B-doped diamond layered structure showed ideal behavior as a metal–ferroelectric–semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to ‑20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF–TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.

  20. Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

    Science.gov (United States)

    Kumar, Manoj; Arya, Sandeep K.; Pandey, Sujata

    2012-03-01

    Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

  1. Gate-Sensing Coherent Charge Oscillations in a Silicon Field-Effect Transistor.

    Science.gov (United States)

    Gonzalez-Zalba, M Fernando; Shevchenko, Sergey N; Barraud, Sylvain; Johansson, J Robert; Ferguson, Andrew J; Nori, Franco; Betz, Andreas C

    2016-03-09

    Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as tunneling and coherence, can be harnessed to use existing CMOS technology for quantum information processing. Here, we report the observation of coherent charge oscillations in a double quantum dot formed in a silicon nanowire transistor detected via its dispersive interaction with a radio frequency resonant circuit coupled via the gate. Differential capacitance changes at the interdot charge transitions allow us to monitor the state of the system in the strong-driving regime where we observe the emergence of Landau-Zener-Stückelberg-Majorana interference on the phase response of the resonator. A theoretical analysis of the dispersive signal demonstrates that quantum and tunneling capacitance changes must be included to describe the qubit-resonator interaction. Furthermore, a Fourier analysis of the interference pattern reveals a charge coherence time, T2 ≈ 100 ps. Our results demonstrate charge coherent control and readout in a simple silicon transistor and open up the possibility to implement charge and spin qubits in existing CMOS technology.

  2. Facile fabrication of electrolyte-gated single-crystalline cuprous oxide nanowire field-effect transistors

    Science.gov (United States)

    Stoesser, Anna; von Seggern, Falk; Purohit, Suneeti; Nasr, Babak; Kruk, Robert; Dehm, Simone; Wang, Di; Hahn, Horst; Dasgupta, Subho

    2016-10-01

    Oxide semiconductors are considered to be one of the forefront candidates for the new generation, high-performance electronics. However, one of the major limitations for oxide electronics is the scarcity of an equally good hole-conducting semiconductor, which can provide identical performance for the p-type metal oxide semiconductor field-effect transistors as compared to their electron conducting counterparts. In this quest, here we present a bulk synthesis method for single crystalline cuprous oxide (Cu2O) nanowires, their chemical and morphological characterization and suitability as active channel material in electrolyte-gated, low-power, field-effect transistors (FETs) for portable and flexible logic circuits. The bulk synthesis method used in the present study includes two steps: namely hydrothermal synthesis of the nanowires and the removal of the surface organic contaminants. The surface treated nanowires are then dispersed on a receiver substrate where the passive electrodes are structured, followed by printing of a composite solid polymer electrolyte (CSPE), chosen as the gate insulator. The characteristic electrical properties of individual nanowire FETs are found to be quite interesting including accumulation-mode operation and field-effect mobility of 0.15 cm2 V-1 s-1.

  3. Probing top-gated field effect transistor of reduced graphene oxide monolayer made by dielectrophoresis

    Science.gov (United States)

    Vasu, K. S.; Chakraborty, Biswanath; Sampath, S.; Sood, A. K.

    2010-08-01

    We demonstrate a top-gated field effect transistor made of a reduced graphene oxide (RGO) monolayer (graphene) by dielectrophoresis. The Raman spectrum of RGO flakes of typical size of 5 μm×5 μm shows a single 2D band at 2687 cm -1, characteristic of single-layer graphene. The two-probe current-voltage measurements of RGO flakes, deposited in between the patterned electrodes with a gap of 2.5 μm using ac dielectrophoresis, show ohmic behavior with a resistance of ˜37 kΩ. The temperature dependence of the resistance (R) of RGO measured between 305 K and 393 K yields a temperature coefficient of resistance [dR/dT]/R˜-9.5×10-4/K, the same as that of mechanically exfoliated single-layer graphene. The field-effect transistor action was obtained by electrochemical top-gating using a solid polymer electrolyte (PEO+LiClO 4) and Pt wire. The ambipolar nature of graphene flakes is observed up to a doping level of ˜6×1012/cm and carrier mobility of ˜50 cm 2/V s. The source-drain current characteristics show a tendency of current saturation at high source-drain voltage which is analyzed quantitatively by a diffusive transport model.

  4. A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

    Institute of Scientific and Technical Information of China (English)

    Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

    2011-01-01

    A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (Ron,sp),whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region,is proposed.The theoretical limit of its Ron,sp is deduced,the influence of structure parameters on the breakdown voltage (BV) and Ron,sp are investigated,and the optimized results with BV of 83 V and Ron,sp of 54 mΩ.mm2 are obtained.Simulations show that the inhomogencous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET)has a superior “Ron,sp/BV” trade-off to the conventional VDMOS (a 38% reduction of Ron,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of Ron,sp with the same BV).The inhomogeneous-floatingislands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET.Its reverse recovery peak current,reverse recovery time and reverse recovery charge are about 50,80 and 40% of those of the superjunction MOSFET,respectively.

  5. Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo, E-mail: ykimm@knu.ac.kr [Organic Nanoelectronics Laboratory, Department of Chemical Engineering and Graduate School of Applied Chemical Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Kim, Hwajeong [Organic Nanoelectronics Laboratory, Department of Chemical Engineering and Graduate School of Applied Chemical Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Priority Research Center, Research Institute of Advanced Energy Technology, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Lee, Joon-Hyung [School of Materials Science and Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of); Park, Soo-Young; Kang, Inn-Kyu [Department of Polymer Science and Engineering and Graduate School of Applied Chemical Engineering, Kyungpook National University, Daegu, 702-701 (Korea, Republic of)

    2014-09-15

    We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4{sup ′}-pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm{sup 2}/Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V{sub D}) and gate (V{sub G}) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V{sub D} and V{sub G}. The best voltage combination was V{sub D} = −0.2 V and V{sub G} = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors.

  6. Effects of bias stress on ZnO nanowire field-effect transistors fabricated with organic gate nanodielectrics

    Science.gov (United States)

    Ju, Sanghyun; Janes, David B.; Lu, Gang; Facchetti, Antonio; Marks, Tobin J.

    2006-11-01

    The effects of bias stress (gate stress or drain stress) on nanowire field-effect transistor (NW-FET) stability were investigated as a function of stress bias and stress time. The n-channel NW-FETs used a nanoscopic self-assembled organic gate insulator, and each device contained a single ZnO nanowire. Before stress, the off current is limited by a leakage current in the 1nA range, which increases as the gate to source bias becomes increasingly negative. The devices also exhibited significant changes in threshold voltage (Vth) and off current over 500 repeated measurement sweeps. The leakage current was significantly reduced after gate stress, but not after drain stress. Vth variations observed upon successive bias sweeps for devices following gate stress or drain stress were smaller than the Vth variation of unstressed devices. These observations suggest that gate stress and drain stress modify the ZnO nanowire-gate insulator interface, which can reduce electron trapping at the surface and therefore reduce the off current levels and variations in Vth. These results confirm that gate and drain stresses are effective means to stabilize device operation and provide high performance transistors with impressive reliabilities.

  7. Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

    Science.gov (United States)

    Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

    2016-11-01

    Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

  8. Formation of a Stable p-n Junction in a Liquid-Gated MoS2 Ambipolar Transistor

    NARCIS (Netherlands)

    Zhang, Y. J.; Ye, J. T.; Yornogida, Y.; Takenobu, T.; Iwasa, Y.

    2013-01-01

    Molybdenum disulfide (MoS2) has gained attention because of its high mobility and circular dichroism. As a crucial step to merge these advantages into a single device, we present a method that electronically controls and locates p-n junctions in liquid-gated ambipolar MoS2 transistors. A bias-indepe

  9. Solution processed self-assembled monolayer gate dielectrics for low-voltage organic transistors. : Section Title: Electric Phenomena

    NARCIS (Netherlands)

    Ball, James; Wobkenberg, Paul H.; Colleaux, Florian; Kooistra, Floris B.; Hummelen, Jan C.; Bradley, Donal D. C.; Anthopoulos, Thomas D.

    2008-01-01

    Low-voltage org. transistors are sought for implementation in high vol. low-power portable electronics of the future. Here we assess the suitability of three phosphonic acid based self-assembling mols. for use as ultra-thin gate dielecs. in low-voltage soln. processable org. field-effect

  10. Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

    KAUST Repository

    Salas-Villasenor, A. L.

    2010-06-29

    Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

  11. Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

    Science.gov (United States)

    Kumar, Neeraj; Kito, Ai; Inoue, Isao

    2015-03-01

    We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

  12. Proton radiation hardness of single-nanowire transistors using robust organic gate nanodielectrics

    Science.gov (United States)

    Ju, Sanghyun; Lee, Kangho; Janes, David B.; Dwivedi, Ramesh C.; Baffour-Awuah, Habibah; Wilkins, R.; Yoon, Myung-Han; Facchetti, Antonio; Mark, Tobin J.

    2006-08-01

    In this contribution, the radiation tolerance of single ZnO nanowire field-effect transistors (NW-FETs) fabricated with a self-assembled superlattice (SAS) gate insulator is investigated and compared with that of ZnO NW-FETs fabricated with a 60nm SiO2 gate insulator. A total-radiation dose study was performed using 10MeV protons at doses of 5.71 and 285krad(Si ). The threshold voltage (Vth) of the SAS-based ZnO NW-FETs is not shifted significantly following irradiation at these doses. In contrast, Vth parameters of the SiO2-based ZnO NW-FETs display average shifts of ˜-4.0 and ˜-10.9V for 5.71 and 285krad(Si ) H+ irradiation, respectively. In addition, little change is observed in the subthreshold characteristics (off current, subthreshold slope) of the SAS-based ZnO NW-FETs following H+ irradiation. These results strongly argue that the bulk oxide trap density and interface trap density formed within the SAS and/or at the SAS-ZnO NW interface during H+ irradiation are significantly lower than those for the corresponding SiO2 gate dielectrics. The radiation-robust SAS-based ZnO NW-FETs are thus promising candidates for future space-based applications in electronics and flexible displays.

  13. Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

    Science.gov (United States)

    Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

    2016-04-01

    Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

  14. Stability analysis of a back-gate graphene transistor in air environment

    Institute of Scientific and Technical Information of China (English)

    Jia Kunpeng; Yang Jie; Su Yajuan; Nie Pengfei; Zhong Jian; Liang Qingqing; Zhu Huilong

    2013-01-01

    The stability of a graphene field effect transistor (GFET) is important to its performance optimization,and study of hysteresis behavior can propose useful suggestions for GFET fabrication and optimization.In this work,a back-gate GFET has been fabricated and characterized,which is compatible with the CMOS process.The stability ofa GFET in air has been studied and it is found that a GFET's electrical performance dramatically changes when exposed to air.The hysteresis characteristic of a GFET depending on time has been observed and analyzed systematically.Hysteresis behavior is reversed at room temperature with the Dirac point positive shifted when the GFET is exposed to air after annealing.

  15. Analytic modeling of a depletion-mode cylindrical surrounding-gate nanowire field-effect transistor.

    Science.gov (United States)

    Yu, Yun Seop; Park, Hyung-Kun

    2012-07-01

    A compact model for depletion-mode p-type cylindrical surrounding-gate nanowire field-effect transistors (SGNWFETs) is proposed. The SGNWFET model consists of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic SGNWFET. Based on the electrostatic method, the intrinsic SGNWFET model was derived from current conduction mechanisms attributed to bulk charges through the center neutral region, in addition to accumulation charges through the surface accumulation region. The authors' previously developed Schottky diode model was used for the M-S contacts. The new model was applied to an advanced design system (ADS), whereby the intrinsic part of the SGNWFET and the Schottky diode were developed using the Verilog-A language. The results of the simulation of the newly developed SGNWFET model reproduced the experiment results considerably well.

  16. Characterization of insulated-gate bipolar transistor temperature on insulating, heat-spreading polycrystalline diamond substrate

    Science.gov (United States)

    Umezawa, Hitoshi; Shikata, Shin-ichi; Kato, Yukako; Mokuno, Yoshiaki; Seki, Akinori; Suzuki, Hiroshi; Bessho, Takeshi

    2017-01-01

    Polycrystalline diamond films have been utilized as direct bonding aluminum (DBA) substrates to improve cooling efficiency. A diamond film with a high quality factor was characterized by Raman spectroscopy and showed a high thermal conductivity of more than 1800 W m-1 K-1 and a low leakage current, even at an applied bias of 3 kV, because of the suppression of electrical conduction through the grain boundaries. The operating temperatures of Insulated-gate bipolar transistors (IGBTs) on diamond DBAs were 20-28% lower than those on AlN DBAs. The thermal resistivity of the diamond DBA module was 0.32 °C/W. The uniformity of the temperature distribution on a diamond DBA was excellent.

  17. Gate frequency sweep: An effective method to evaluate the dynamic performance of AlGaN/GaN power heterojunction field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Santi, C. de; Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it; Meneghesso, G.; Zanoni, E. [Department of Information Engineering, University of Padua, via Gradenigo 6/B, Padova 35131 (Italy); Ishida, H.; Ueda, T. [Panasonic Corporation, Semiconductor Device Research Center, SDRC, 1 Kotari-yakemachi, Nagaokakyio City, Kyoto 317-8520 (Japan)

    2014-08-18

    With this paper we propose a test method for evaluating the dynamic performance of GaN-based transistors, namely, gate-frequency sweep measurements: the effectiveness of the method is verified by characterizing the dynamic performance of Gate Injection Transistors. We demonstrate that this method can provide an effective description of the impact of traps on the transient performance of Heterojunction Field Effect Transistors, and information on the properties (activation energy and cross section) of the related defects. Moreover, we discuss the relation between the results obtained by gate-frequency sweep measurements and those collected by conventional drain current transients and double pulse characterization.

  18. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    Science.gov (United States)

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T.

    2014-06-01

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al2O3/ZrO2 as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  19. Mobility enhancement of SnO2 nanowire transistors gated with a nanogranular SiO2 solid electrolyte.

    Science.gov (United States)

    Sun, Jia; Huang, Wenlong; Qian, Chuan; Yang, Junliang; Gao, Yongli

    2014-01-21

    Field-effect transistors (FETs) based on semiconducting nanowires are the most fundamental electronic elements for exploring charge transport as well as possible applications in functional nanoelectronics. Here, we report the effect of different gate dielectrics on the electrical performance of SnO2 nanowire FETs. By using solid-electrolytes with large electric-double-layer (EDL) capacitance as gate dielectrics, both low-voltage operation and high gating efficiency can be obtained. Electrical transport measurements indicate that the nanowire FETs gated by solid-electrolytes show improved electrical performances in terms of on-current, sub-threshold swing, and mobility, in comparison to those gated by traditional thermally grown dielectrics. The observed performance improvement is possibly due to the reduction of the contact-resistance and the Schottky barrier at the semiconductor/metal junctions.

  20. Boron δ-doped (111) diamond solution gate field effect transistors.

    Science.gov (United States)

    Edgington, Robert; Ruslinda, A Rahim; Sato, Syunsuke; Ishiyama, Yuichiro; Tsuge, Kyosuke; Ono, Tasuku; Kawarada, Hiroshi; Jackman, Richard B

    2012-03-15

    A solution gate field effect transistor (SGFET) using an oxidised boron δ-doped channel on (111) diamond is presented for the first time. Employing an optimised plasma chemical vapour deposition (PECVD) recipe to deposit δ-layers, SGFETs show improved current-voltage (I-V) characteristics in comparison to previous similar devices fabricated on (100) and polycrystalline diamond, where the device is shown to operate in the enhancement mode of operation, achieving channel pinch-off and drain-source current saturation within the electrochemical window of diamond. A maximum gain and transconductance of 3 and 200μS/mm are extracted, showing comparable figures of merit to hydrogen-based SGFET. The oxidised device shows a site-binding model pH sensitivity of 36 mV/pH, displaying fast temporal responses. Considering the biocompatibility of diamond towards cells, the device's highly mutable transistor characteristics, pH sensitivity and stability against anodic oxidation common to hydrogen terminated diamond SGFET, oxidised boron δ-doped diamond SGFETs show promise for the recording of action potentials from electrogenic cells. Copyright © 2011 Elsevier B.V. All rights reserved.

  1. Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

    Institute of Scientific and Technical Information of China (English)

    Manoj Kumar; Sandeep K. Arya; Sujata Pandey

    2012-01-01

    Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits.Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed.Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS & PMOS transistor switching networks are presented.A threetransistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 μW.The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

  2. Current saturation in submicrometer graphene transistors with thin gate dielectric: experiment, simulation, and theory.

    Science.gov (United States)

    Han, Shu-Jen; Reddy, Dharmendar; Carpenter, Gary D; Franklin, Aaron D; Jenkins, Keith A

    2012-06-26

    Recently, graphene field-effect transistors (FET) with cutoff frequencies (f(T)) between 100 and 300 GHz have been reported; however, the devices showed very weak drain current saturation, leading to an undesirably high output conductance (g(ds)= dI(ds)/dV(ds)). A crucial figure-of-merit for analog/RF transistors is the intrinsic voltage gain (g(m)/g(ds)) which requires both high g(m) (primary component of f(T)) and low g(ds). Obtaining current saturation has become one of the key challenges in graphene device design. In this work, we study theoretically the influence of the dielectric thickness on the output characteristics of graphene FETs by using a surface-potential-based device model. We also experimentally demonstrate that by employing a very thin gate dielectric (equivalent oxide thickness less than 2 nm), full drain current saturation can be obtained for large-scale chemical vapor deposition graphene FETs with short channels. In addition to showing intrinsic voltage gain (as high as 34) that is comparable to commercial semiconductor FETs with bandgaps, we also demonstrate high frequency AC voltage gain and S21 power gain from s-parameter measurements.

  3. High Fill-Factor Imagers for Neuromorphic Processing Enabled by Floating-Gate Circuits

    Directory of Open Access Journals (Sweden)

    Hasler Paul

    2003-01-01

    Full Text Available In neuromorphic modeling of the retina, it would be very nice to have processing capabilities at the focal plane while retaining the density of typical active pixel sensor (APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our transform imager technology and basic architecture that uses analog floating-gate devices to make it possible to have computational imagers with high pixel densities. This imager approach allows programmable focal-plane processing that can perform retinal and higher-level bioinspired computation. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting dataflow architecture can directly perform computation of spatial transforms, motion computations, and stereo computations. The core imager performs computations at the pixel plane, but still holds a fill factor greater than 40 percent—comparable to the high fill factors of APS imagers. Each pixel is composed of a photodiode sensor element and a multiplier. We present experimental results from several imager arrays built in 0.5 m process (up to in an area of 4 millimeter squared.

  4. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    Energy Technology Data Exchange (ETDEWEB)

    Chao, Jin Yu [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn; Xiao, Hui [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Yuan, Zhi Guo, E-mail: ncityzg@163.com [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China)

    2015-12-21

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  5. Transistors

    CERN Document Server

    Kendall, E J M

    2013-01-01

    Transistors covers the main thread of transistor development. This book is organized into 2 parts encompassing 19, and starts with an overview of the semi-conductor physics pertinent to the understanding of transistors, as well as features and applications of the point contact devices and junction devices. The subsequent part deals with the modulation of conductance of thin films of conductors by surface charges, the metal-semi conductor, and the semi-conductor triode. These topics are followed by discussions on the nature of the forward current, physical principles in transistor, the hole inj

  6. Unique device operations by combining optical-memory effect and electrical-gate modulation in a photochromism-based dual-gate transistor.

    Science.gov (United States)

    Ishiguro, Yasushi; Hayakawa, Ryoma; Yasuda, Takeshi; Chikyow, Toyohiro; Wakayama, Yutaka

    2013-10-09

    We demonstrate a new device that combines a light-field effect and an electrical-gate effect to control the drain current in a dual-gate transistor. We used two organic layers, photochromic spiropyran (SP)-doped poly(triarylamine) (PTAA) and pristine PTAA, as top and bottom channels, respectively, connected to common source and drain electrodes. The application of voltage to the top and bottom gates modulated the drain current through each layer independently. UV irradiation suppressed the drain current through the top channel. The suppressed current was then maintained even after the UV light was turned off because of an optical memory effect induced by photoisomerization of SP. In contrast, UV irradiation did not change the drain current in the bottom channel. Our dual-gate transistor thus has two organic channels with distinct photosensitivities: an optically active SP-PTAA film and an optically inactive PTAA film. This device configuration allows multi-level switching via top- and bottom-gate electrical fields with an optical-memory effect.

  7. The origin of excellent gate-bias stress stability in organic field-effect transistors employing fluorinated-polymer gate dielectrics.

    Science.gov (United States)

    Kim, Jiye; Jang, Jaeyoung; Kim, Kyunghun; Kim, Haekyoung; Kim, Se Hyun; Park, Chan Eon

    2014-11-12

    Tuning of the energetic barriers to charge transfer at the semiconductor/dielectric interface in organic field-effect transistors (OFETs) is achieved by varying the dielectric functionality. Based on this, the correlation between the magnitude of the energy barrier and the gate-bias stress stability of the OFETs is demonstrated, and the origin of the excellent device stability of OFETs employing fluorinated dielectrics is revealed.

  8. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    Energy Technology Data Exchange (ETDEWEB)

    Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

    2016-08-30

    Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  9. Flexible suspended gate organic thin-film transistors for ultra-sensitive pressure detection

    Science.gov (United States)

    Zang, Yaping; Zhang, Fengjiao; Huang, Dazhen; Gao, Xike; di, Chong-An; Zhu, Daoben

    2015-03-01

    The utilization of organic devices as pressure-sensing elements in artificial intelligence and healthcare applications represents a fascinating opportunity for the next-generation electronic products. To satisfy the critical requirements of these promising applications, the low-cost construction of large-area ultra-sensitive organic pressure devices with outstanding flexibility is highly desired. Here we present flexible suspended gate organic thin-film transistors (SGOTFTs) as a model platform that enables ultra-sensitive pressure detection. More importantly, the unique device geometry of SGOTFTs allows the fine-tuning of their sensitivity by the suspended gate. An unprecedented sensitivity of 192 kPa-1, a low limit-of-detection pressure of <0.5 Pa and a short response time of 10 ms were successfully realized, allowing the real-time detection of acoustic waves. These excellent sensing properties of SGOTFTs, together with their advantages of facile large-area fabrication and versatility in detecting various pressure signals, make SGOTFTs a powerful strategy for spatial pressure mapping in practical applications.

  10. Fluorinated polyimide gate dielectrics for the advancing the electrical stability of organic field-effect transistors.

    Science.gov (United States)

    Baek, Yonghwa; Lim, Sooman; Yoo, Eun Joo; Kim, Lae Ho; Kim, Haekyoung; Lee, Seung Woo; Kim, Se Hyun; Park, Chan Eon

    2014-09-10

    Organic field-effect transistors (OFETs) that operated with good electrical stability were prepared by synthesizing fluorinated polyimide (PI) gate dielectrics based on 6FDA-PDA-PDA PI and 6FDA-CF3Bz-PDA PI. 6FDA-PDA-PDA PI and 6FDA-CF3Bz-PDA PI contain 6 and 18 fluorine atoms per repeat unit, respectively. These fluorinated polymers provided smooth surface topographies and surface energies that decreased as the number of fluorine atoms in the polymer backbone increased. These properties led to a better crystalline morphology in the semiconductor film grown over their surfaces. The number of fluorine atoms in the PI backbone increased, the field-effect mobility improved, and the threshold voltage shifted toward positive values (from -0.38 to +2.21 V) in the OFETs with pentacene and triethylsilylethynyl anthradithiophene. In addition, the highly fluorinated polyimide dielectric showed negligible hysteresis and a notable gate bias stability under both a N2 environment and ambient air.

  11. Screening-induced surface polar optical phonon scattering in dual-gated graphene field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Hu, Bo, E-mail: hubo2011@semi.ac.cn

    2015-03-15

    The effect of surface polar optical phonons (SOs) from the dielectric layers on electron mobility in dual-gated graphene field effect transistors (GFETs) is studied theoretically. By taking into account SO scattering of electron as a main scattering mechanism, the electron mobility is calculated by the iterative solution of Boltzmann transport equation. In treating scattering with the SO modes, the dynamic dielectric screening is included and compared to the static dielectric screening and the dielectric screening in the static limit. It is found that the dynamic dielectric screening effect plays an important role in the range of low net carrier density. More importantly, in-plane acoustic phonon scattering and charged impurity scattering are also included in the total mobility for SiO{sub 2}-supported GFETs with various high-κ top-gate dielectric layers considered. The calculated total mobility results suggest both Al{sub 2}O{sub 3} and AlN are the promising candidate dielectric layers for the enhancement in room temperature mobility of graphene in the future.

  12. Improved double-gate armchair silicene nanoribbon field-effect-transistor at large transport bandgap

    Science.gov (United States)

    Mohsen, Mahmoudi; Zahra, Ahangari; Morteza, Fathipour

    2016-01-01

    The electrical characteristics of a double-gate armchair silicene nanoribbon field-effect-transistor (DG ASiNR FET) are thoroughly investigated by using a ballistic quantum transport model based on non-equilibrium Green’s function (NEGF) approach self-consistently coupled with a three-dimensional (3D) Poisson equation. We evaluate the influence of variation in uniaxial tensile strain, ribbon temperature and oxide thickness on the on-off current ratio, subthreshold swing, transconductance and the delay time of a 12-nm-length ultranarrow ASiNR FET. A novel two-parameter strain magnitude and temperature-dependent model is presented for designing an optimized device possessing balanced amelioration of all the electrical parameters. We demonstrate that employing HfO2 as the gate insulator can be a favorable choice and simultaneous use of it with proper combination of temperature and strain magnitude can achieve better device performance. Furthermore, a general model power (GMP) is derived which explicitly provides the electron effective mass as a function of the bandgap of a hydrogen passivated ASiNR under strain.

  13. Nanocrystalline cellulose applied simultaneously as the gate dielectric and the substrate in flexible field effect transistors.

    Science.gov (United States)

    Gaspar, D; Fernandes, S N; de Oliveira, A G; Fernandes, J G; Grey, P; Pontes, R V; Pereira, L; Martins, R; Godinho, M H; Fortunato, E

    2014-03-07

    Cotton-based nanocrystalline cellulose (NCC), also known as nanopaper, one of the major sources of renewable materials, is a promising substrate and component for producing low cost fully recyclable flexible paper electronic devices and systems due to its properties (lightweight, stiffness, non-toxicity, transparency, low thermal expansion, gas impermeability and improved mechanical properties).Here, we have demonstrated for the first time a thin transparent nanopaper-based field effect transistor (FET) where NCC is simultaneously used as the substrate and as the gate dielectric layer in an 'interstrate' structure, since the device is built on both sides of the NCC films; while the active channel layer is based on oxide amorphous semiconductors, the gate electrode is based on a transparent conductive oxide.Such hybrid FETs present excellent operating characteristics such as high channel saturation mobility (>7 cm(2) V (-1) s(-1)), drain-source current on/off modulation ratio higher than 10(5), enhancement n-type operation and subthreshold gate voltage swing of 2.11 V/decade. The NCC film FET characteristics have been measured in air ambient conditions and present good stability, after two weeks of being processed, without any type of encapsulation or passivation layer. The results obtained are comparable to ones produced for conventional cellulose paper, marking this out as a promising approach for attaining high-performance disposable electronics such as paper displays, smart labels, smart packaging, RFID (radio-frequency identification) and point-of-care systems for self-analysis in bioscience applications, among others.

  14. Nanocrystalline cellulose applied simultaneously as the gate dielectric and the substrate in flexible field effect transistors

    Science.gov (United States)

    Gaspar, D.; Fernandes, S. N.; de Oliveira, A. G.; Fernandes, J. G.; Grey, P.; Pontes, R. V.; Pereira, L.; Martins, R.; Godinho, M. H.; Fortunato, E.

    2014-03-01

    Cotton-based nanocrystalline cellulose (NCC), also known as nanopaper, one of the major sources of renewable materials, is a promising substrate and component for producing low cost fully recyclable flexible paper electronic devices and systems due to its properties (lightweight, stiffness, non-toxicity, transparency, low thermal expansion, gas impermeability and improved mechanical properties). Here, we have demonstrated for the first time a thin transparent nanopaper-based field effect transistor (FET) where NCC is simultaneously used as the substrate and as the gate dielectric layer in an ‘interstrate’ structure, since the device is built on both sides of the NCC films; while the active channel layer is based on oxide amorphous semiconductors, the gate electrode is based on a transparent conductive oxide. Such hybrid FETs present excellent operating characteristics such as high channel saturation mobility (>7 cm2 V -1 s-1), drain-source current on/off modulation ratio higher than 105, enhancement n-type operation and subthreshold gate voltage swing of 2.11 V/decade. The NCC film FET characteristics have been measured in air ambient conditions and present good stability, after two weeks of being processed, without any type of encapsulation or passivation layer. The results obtained are comparable to ones produced for conventional cellulose paper, marking this out as a promising approach for attaining high-performance disposable electronics such as paper displays, smart labels, smart packaging, RFID (radio-frequency identification) and point-of-care systems for self-analysis in bioscience applications, among others.

  15. A Numerical Technique for Removing Residual Gate-Source Capacitances When Extracting Parasitic Inductance for GaN High Electron Mobility Transistors (HEMTs)

    Science.gov (United States)

    2011-03-01

    Residual Gate-source Capacitances When Extracting Parasitic Inductance for GaN High Electron Mobility Transistors ( HEMTs ) Benjamin Huebschman and Pankaj...Extracting Parasitic Inductance for GaN High Electron Mobility Transistors ( HEMTs ) 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6...nitride ( GaN ) high electron mobility transistors ( HEMTs ) begin to realize their performance potential, and to transition from experimental devices to

  16. A PNPN tunnel field-effect transistor with high-k gate and low-k fringe dielectrics

    Institute of Scientific and Technical Information of China (English)

    Cui Ning; Liang Renrong; Wang Jing; Zhou Wei; Xu Jun

    2012-01-01

    A PNPN tunnel field effect transistor (TFET) with a high-k gate dielectric and a low-k fringe dielectric is introduced.The effects of the gate and fringe electric fields on the TFET's performance were investigated through two-dimensional simulations.The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel,while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability.The TFET device with the proposed structure has good switching characteristics,enhanced on-state current,and high process tolerance.It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.

  17. A Label-Free Immunosensor for IgG Based on an Extended-Gate Type Organic Field Effect Transistor

    Directory of Open Access Journals (Sweden)

    Tsukuru Minamiki

    2014-09-01

    Full Text Available A novel biosensor for immunoglobulin G (IgG detection based on an extended-gate type organic field effect transistor (OFET has been developed that possesses an anti-IgG antibody on its extended-gate electrode and can be operated below 3 V. The titration results from the target IgG in the presence of a bovine serum albumin interferent, clearly exhibiting a negative shift in the OFET transfer curve with increasing IgG concentration. This is presumed to be due an interaction between target IgG and the immobilized anti-IgG antibody on the extended-gate electrode. As a result, a linear range from 0 to 10 µg/mL was achieved with a relatively low detection limit of 0.62 µg/mL (=4 nM. We believe that these results open up opportunities for applying extended-gate-type OFETs to immunosensing.

  18. GaN High-Electron-Mobility Transistor with WN x /Cu Gate for High-Power Applications

    Science.gov (United States)

    Hsieh, Ting-En; Lin, Yueh-Chin; Li, Fang-Ming; Shi, Wang-Cheng; Huang, Yu-Xiang; Lan, Wei-Cheng; Chin, Ping-Chieh; Chang, Edward Yi

    2015-12-01

    A GaN high-electron-mobility transistor (HEMT) with WN x /Cu gate for high-power applications has been investigated. The direct-current (DC) characteristics of the device are comparable to those of conventional Ni/Au-gated GaN HEMTs. The results of high-voltage stress testing indicate that the device is stable after application of 200 V stress for 42 h. The WN x /Cu-gated GaN HEMT exhibited no obvious changes in the DC characteristics or Schottky barrier height before and after annealing at 250°C for 1 h. These results demonstrate that the WN x /Cu gate structure can be used in a GaN HEMT for high-power applications with good thermal stability.

  19. Fabrication and Characterization of Ferroelectric Gate Field-Effect Transistor Memory Based on Ferroelectric-Insulator Interface Conduction

    Science.gov (United States)

    Lee, Bong Yeon; Minami, Takaki; Kanashima, Takeshi; Okuyama, Masanori

    2006-11-01

    A new type of ferroelectric gate field-effect transistor (FET) using ferroelectric-insulator interface conduction has been proposed. Drain current flows along the interface between the ferroelectric and insulator layers and requires no semiconductor. The channel region of the FET is composed of a Pt/insulator HfO2/ferroelectric Pb(Zr0.52Ti0.48)O3 (PZT)/Pt/TiO2/SiO2/Si multilayer, and the source and drain areas are formed at the interface of the PZT and HfO2 films. Drain current versus gate voltage characteristics show a clockwise hysteresis loop similar to that for a conventional p-channel transistor. The FET shows that the on/off ratio of the conduction current is within 105 to 106 and that the off-state current is about 10-10 A.

  20. 64 kbit Ferroelectric-Gate-Transistor-Integrated NAND Flash Memory with 7.5 V Program and Long Data Retention

    Science.gov (United States)

    Zhang, Xizhen; Takahashi, Mitsue; Takeuchi, Ken; Sakai, Shigeki

    2012-04-01

    A 64 kbit (kb) one-transistor-type ferroelectric memory array was fabricated and characterized. Pt/SrBi2Ta2O9/Hf-Al-O/Si ferroelectric-gate field-effect transistors (FeFETs) were used as the memory cells. The gate length and width were 5 and 5 µm, respectively. The array design was based on NAND flash memory organized as 8 word lines × 32 blocks × 256 bit lines. Erase, program, and nondestructive-read operations were demonstrated in every block. Threshold-voltage (Vth) reading of all the 64 kb memory cells showed a clear separation between their all-erased and all-programmed states. A checkerboard pattern was also programmed in a block and the two distinguishable Vth distributions were read out. The Vth retention of a block of 2 kb memory cells showed no significant degradation after two days.

  1. Enhancing controllability and stability of bottom-gated graphene thin-film transistors by passivation with methylamine

    Energy Technology Data Exchange (ETDEWEB)

    Drapeko, Maksim, E-mail: maksim.drapeko.10@ucl.ac.uk, E-mail: md584@cam.ac.uk [London Centre for Nanotechnology, University College London, 17-19 Gordon Street, WC1H 0AH London, United Kingdom and Centre for Advanced Photonics and Electronics, Department of Engineering, Cambridge University, 9 J J Thomson Avenue, CB3 0HE Cambridge (United Kingdom)

    2014-06-02

    This paper is intended to aid to bridge the gap between chemistry and electronic engineering. In this work, the fabrication of chemical vapour deposited graphene field-effect transistors employing silicon-nitride (Si{sub 3}N{sub 4}) gate dielectric is presented, showing originally p-type channel conduction due to ambient impurities yielding uncontrollable behaviour. Vacuum annealing has been performed to balance off hole and electron conduction in the channel, leading to the observation of the Dirac point and therefore improving controllability. Non-covalent functionalisation by methylamine has been performed for passivation and stability reasons yielding electron mobility of 4800 cm{sup 2}/V s and hole mobility of 3800 cm{sup 2}/V s as well as stabilised controllable behaviour of a bottom-gated transistor. The introduction of interface charge following the non-covalent functionalisation as well as the charge balance have been discussed and analysed.

  2. Excitatory Post-Synaptic Potential Mimicked in Indium-Zinc-Oxide Synaptic Transistors Gated by Methyl Cellulose Solid Electrolyte

    Science.gov (United States)

    Guo, Liqiang; Wen, Juan; Ding, Jianning; Wan, Changjin; Cheng, Guanggui

    2016-12-01

    The excitatory postsynaptic potential (EPSP) of biological synapses is mimicked in indium-zinc-oxide synaptic transistors gated by methyl cellulose solid electrolyte. These synaptic transistors show excellent electrical performance at an operating voltage of 0.8 V, Ion/off ratio of 2.5 × 106, and mobility of 38.4 cm2/Vs. After this device is connected to a resistance of 4 MΩ in series, it exhibits excellent characteristics as an inverter. A threshold potential of 0.3 V is achieved by changing the gate pulse amplitude, width, or number, which is analogous to biological EPSP.

  3. The Helium Field Effect Transistor (II): Gated Transport of Surface-State Electrons Through Micro-constrictions

    Science.gov (United States)

    Shaban, F.; Ashari, M.; Lorenz, T.; Rau, R.; Scheer, E.; Kono, K.; Rees, D. G.; Leiderer, P.

    2016-11-01

    We present transport measurements of surface-state electrons on liquid helium films in confined geometry. The measurements are taken using split-gate devices similar to a field effect transistor. The number of electrons passing between the source and drain areas of the device can be precisely controlled by changing the length of the voltage pulse applied to the gate electrode. We find evidence that the effective driving potential depends on electron-electron interactions, as well as the electric field applied to the substrate. Our measurements indicate that the mobility of electrons on helium films can be high and that microfabricated transistor devices allow electron manipulation on length scales close to the interelectron separation. Our experiment is an important step toward investigations of surface-state electron properties at much higher densities, for which the quantum melting of the system to a degenerate Fermi gas should be observed.

  4. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    Science.gov (United States)

    Besleaga, C.; Stan, G. E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

    2016-08-01

    The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium-gallium-zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium-gallium-zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  5. SEMICONDUCTOR DEVICES Low voltage copper phthalocyanine organic thin film transistors with a polymer layer as the gate insulator

    Science.gov (United States)

    Xueqiang, Liu; Weihong, Bi; Tong, Zhang

    2010-12-01

    Low voltage organic thin film transistors (OTFTs) were created using polymethyl-methacrylate-co g-lyciclyl-methacrylate (PMMA-GMA) as the gate dielectric. The OTFTs performed acceptably at supply voltages of about 10 V. From a densely packed copolymer brush, a leakage current as low as 2 × 10-8 A/cm2 was obtained. From the measured capacitance—insulator frequency characteristics, a dielectric constant in the range 3.9-5.0 was obtained. By controlling the thickness of the gate dielectric, the threshold voltage was reduced from -3.5 to -2.0 V. The copper phthalocyanine (CuPc) based organic thin film transistor could be operated at low voltage and 1.2 × 10-3 cm2/(V·s) mobility.

  6. A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Wei-Chen; Lin, Horng-Chih; Lin, Zer-Ming; Huang, Tiao-Yuan [Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, 300, Taiwan (China); Hsu, Chin-Tsai, E-mail: hclin@faculty.nctu.edu.tw [National Nano Device Laboratories, Hsinchu, 300, Taiwan (China)

    2010-10-29

    Employing mix-and-match lithography of I-line stepper and e-beam direct writing, independent double-gated poly-Si nanowire thin film transistors with channel lengths ranging from 70 nm to 5 {mu}m were fabricated and characterized. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length dependent abrupt switching behavior for one of the single-gated modes. Through simulation and experimental verification, the root cause for this phenomenon was identified to be the non-uniformly distributed dopants introduced by ion implantation.

  7. Solution-deposited sodium beta-alumina gate dielectrics for low-voltage and transparent field-effect transistors.

    Science.gov (United States)

    Pal, Bhola N; Dhar, Bal Mukund; See, Kevin C; Katz, Howard E

    2009-11-01

    Sodium beta-alumina (SBA) has high two-dimensional conductivity, owing to mobile sodium ions in lattice planes, between which are insulating AlO(x) layers. SBA can provide high capacitance perpendicular to the planes, while causing negligible leakage current owing to the lack of electron carriers and limited mobility of sodium ions through the aluminium oxide layers. Here, we describe sol-gel-beta-alumina films as transistor gate dielectrics with solution-deposited zinc-oxide-based semiconductors and indium tin oxide (ITO) gate electrodes. The transistors operate in air with a few volts input. The highest electron mobility, 28.0 cm2 V(-1) s(-1), was from zinc tin oxide (ZTO), with an on/off ratio of 2 x 10(4). ZTO over a lower-temperature, amorphous dielectric, had a mobility of 10 cm2 V(-1) s(-1). We also used silicon wafer and flexible polyimide-aluminium foil substrates for solution-processed n-type oxide and organic transistors. Using poly(3,4-ethylenedioxythiophene) poly(styrenesulphonate) conducting polymer electrodes, we prepared an all-solution-processed, low-voltage transparent oxide transistor on an ITO glass substrate.

  8. All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal.

    Science.gov (United States)

    Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

    2016-08-05

    In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature 'prototype' PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits.

  9. High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO{sub 2} gate insulator

    Energy Technology Data Exchange (ETDEWEB)

    Song, Yang, E-mail: yang_song@brown.edu [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); Zaslavsky, A. [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States); Paine, D.C. [School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States)

    2016-09-01

    We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO{sub 2} gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al{sub 2}O{sub 3}/HfO{sub 2} gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20 nm thick IZO channel, forming a partially oxidized HfO{sub x} layer, without any additional insulator in-between. After annealing in air at 300 °C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO{sub 2} gate insulator with a low interface trapped charge density N{sub TC} ~ 2.3 × 10{sup 11} cm{sup −2} and acceptably low gate leakage < 3 × 10{sup −7} A/cm{sup 2} at gate voltage V{sub G} = 1 V. The annealed TFTs with gate length L{sub G} = 50 μm have high mobility ~ 95 cm{sup 2}/V ∙ s (determined via the Y-function technique), high on/off ratio ~ 10{sup 7}, near-zero threshold voltage V{sub T} = − 0.02 V, and a subthreshold swing of 0.062 V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing L{sub G}, indicating that high-performance top-gated HfO{sub 2}-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach. - Highlights: • High-performance indium–zinc–oxide (IZO) thin film transistors (TFTs). • Single-step in-situ dielectric formation approach simplifies fabrication process. • During anneal, reaction between HfO{sub x} and IZO channel forms a high quality HfO{sub 2} layer. • Gate insulator HfO{sub 2} shows low interface trapped charge and small gate leakage. • TFTs have high mobility, near-zero threshold voltage, and a low subthreshold swing.

  10. Theoretical study of the source-drain current and gate leakage current to understand the graphene field-effect transistors.

    Science.gov (United States)

    Yu, Cui; Liu, Hongmei; Ni, Wenbin; Gao, Nengyue; Zhao, Jianwei; Zhang, Haoli

    2011-02-28

    We designed acene molecules attached to two semi-infinite metallic electrodes to explore the source-drain current of graphene and the gate leakage current of the gate dielectric material in the field-effect transistors (FETs) device using the first-principles density functional theory combined with the non-equilibrium Green's function formalism. In the acene-based molecular junctions, we modify the connection position of the thiol group at one side, forming different electron transport routes. The electron transport routes besides the shortest one are defined as the cross channels. The simulation results indicate that electron transport through the cross channels is as efficient as that through the shortest one, since the conductance is weakly dependent on the distance. Thus, it is possible to connect the graphene with multiple leads, leading the graphene as a channel utilized in the graphene-based FETs in the mesoscopic system. When the conjugation of the cross channel is blocked, the junction conductance decreases dramatically. The differential conductance of the BA-1 is nearly 7 (54.57 μS) times as large as that of the BA-4 (7.35 μS) at zero bias. Therefore, the blocked graphene can be employed as the gate dielectric material in the top-gated graphene FET device, since the leakage current is small. The graphene-based field-effect transistors fabricated with a single layer of graphene as the channel and the blocked graphene as the gate dielectric material represent one way to overcome the problem of miniaturization which faces the new generation of transistors.

  11. Experimental study on gamma irradiation effects of floating gate ROMs The ROM is stated for Read-only Memory

    CERN Document Server

    He Chao Hui; Chen Xiao Hua; Wang Yan Ping; Peng Hong Lun

    2002-01-01

    Experimental results of gamma irradiation effects are given for Floating gate ROMs. There is an accumulated dose threshold. Errors occur when accumulated dose is above the threshold, no error occurs when below the threshold. The errors go up with the increase of the accumulated dose. Errors occur in devices that are measured during irradiation and irradiated in power on, moreover, new data cannot be written in these devices with programmer. However, under more accumulated dose, there is no error in devices in power off mode and new data can be written in these devices with programmer

  12. Role of deposition and annealing of the top gate dielectric in a-IGZO TFT-based dual-gate ion-sensitive field-effect transistors

    Science.gov (United States)

    Kumar, Narendra; Sutradhar, Moitri; Kumar, Jitendra; Panda, Siddhartha

    2017-03-01

    The deposition of the top gate dielectric in thin film transistor (TFT)-based dual-gate ion-sensitive field-effect transistors (DG ISFETs) is critical, and expected not to affect the bottom gate TFT characteristics, while providing a higher pH sensitive surface and efficient capacitive coupling between the gates. Amorphous Ta2O5, in addition to having good sensing properties, possesses a high dielectric constant of ∼25 making it well suited as the top gate dielectric in a DG ISFET by providing higher capacitive coupling (ratio of C top/C bottom) leading to higher amplification. To avoid damage of the a-IGZO channel reported to be caused by plasma exposure, deposition of Ta2O5 by e-beam evaporation followed by annealing was investigated in this work to obtain sensitivity over the Nernst limit. The deteriorated bottom gate TFT characteristics, indicated by an increase in the channel conductance, confirmed that plasma exposure is not the sole contributor to the changes. Oxygen vacancies at the Ta2O5/a-IGZO interface, which emerged during processing, increased the channel conductivity, became filled by optimum annealing in oxygen at 400 °C for 1 h, which was confirmed by an x-ray photoelectron spectroscopy depth profiling analysis. The obtained pH sensitivity of the TFT-based DG ISFET was 402 mV pH‑1, which is about 6.8 times the Nernst limit (59 mV pH‑1). The concept of capacitive coupling was also demonstrated by simulating an a-IGZO-based DG TFT structure. Here, the exposure of the top gate dielectric to the electrolyte without applying any top gate bias led to changes in the measured threshold voltage of the bottom gate TFT, and this obviated the requirement of a reference electrode needed in conventional ISFETs and other reported DG ISFETs. These devices, with high sensitivities and requiring low volumes (∼2 μl) of analyte solution, could be potential candidates for utilization as chemical sensors and biosensors.

  13. High Mobility and Low Density of Trap States in Dual-Solid-Gated PbS Nanocrystal Field-Effect Transistors

    NARCIS (Netherlands)

    Nugraha, Mohamad Insan; Haeusermann, Roger; Bisri, Satria Zulkarnaen; Matsui, Hiroyuki; Sytnyk, Mykhailo; Heiss, Wolfgang; Takeya, Jun; Loi, Maria Antonietta

    2015-01-01

    Dual-gated PbS nanocrystal field-effect transistors employing SiO2 and Cytop as gate dielectrics are fabricated. The obtained electron mobility (0.2 cm(2) V-1 s(-1)) and the high on/off ratio (10(5)-10(6)), show that the controlled nanocrystal assembly (obtained with self-assembled monolayers), as w

  14. Persistent photocurrent (PPC) in solution-processed organic thin film transistors: Mechanisms of gate voltage control

    Science.gov (United States)

    Singh, Subhash; Mohapatra, Y. N.

    2016-07-01

    There is a growing need to understand mechanisms of photoresponse in devices based on organic semiconductor thin films and interfaces. The phenomenon of persistent photocurrent (PPC) has been systematically investigated in solution processed TIPS-Pentacene based organic thin film transistors (OTFTs) as an important example of an organic semiconductor material system. With increasing light intensity from dark to 385 mW/cm2, there is a significant shift in threshold voltage (VTh) while the filed-effect mobility remains unchanged. The OTFT shows large photoresponse under white light illumination due to exponential tail states with characteristic energy parameter of 86 meV. The photo-induced current is observed to persist even for several hours after turning the light off. To investigate the origin of PPC, its quenching mechanism is investigated by a variety of methods involving a combination of gate bias, illumination and temperature. We show that a coherent model of trap-charge induced carrier concentration is able to account for the quenching behavior. Analysis of isothermal transients using time-analyzed transient spectroscopy shows that the emission rates are activated and are also field enhanced due to Poole-Frankel effect. The results shed light on the nature, origin, and energetic distribution of the traps controlling PPC in solution processed organic semiconductors and their interfaces.

  15. Novel method for measurement of transistor gate length using energy-filtered transmission electron microscopy

    Science.gov (United States)

    Lee, Sungho; Kim, Tae-Hoon; Kang, Jonghyuk; Yang, Cheol-Woong

    2016-12-01

    As the feature size of devices continues to decrease, transmission electron microscopy (TEM) is becoming indispensable for measuring the critical dimension (CD) of structures. Semiconductors consist primarily of silicon-based materials such as silicon, silicon dioxide, and silicon nitride, and the electrons transmitted through a plan-view TEM sample provide diverse information about various overlapped silicon-based materials. This information is exceedingly complex, which makes it difficult to clarify the boundary to be measured. Therefore, we propose a simple measurement method using energy-filtered TEM (EF-TEM). A precise and effective measurement condition was obtained by determining the maximum value of the integrated area ratio of the electron energy loss spectrum at the boundary to be measured. This method employs an adjustable slit allowing only electrons with a certain energy range to pass. EF-TEM imaging showed a sharp transition at the boundary when the energy-filter’s passband centre was set at 90 eV, with a slit width of 40 eV. This was the optimum condition for the CD measurement of silicon-based materials involving silicon nitride. Electron energy loss spectroscopy (EELS) and EF-TEM images were used to verify this method, which makes it possible to measure the transistor gate length in a dynamic random access memory manufactured using 35 nm process technology. This method can be adapted to measure the CD of other non-silicon-based materials using the EELS area ratio of the boundary materials.

  16. Low-Temperature Solution-Processed Gate Dielectrics for High-Performance Organic Thin Film Transistors

    Directory of Open Access Journals (Sweden)

    Jaekyun Kim

    2015-10-01

    Full Text Available A low-temperature solution-processed high-k gate dielectric layer for use in a high-performance solution-processed semiconducting polymer organic thin-film transistor (OTFT was demonstrated. Photochemical activation of sol-gel-derived AlOx films under 150 °C permitted the formation of a dense film with low leakage and relatively high dielectric-permittivity characteristics, which are almost comparable to the results yielded by the conventionally used vacuum deposition and high temperature annealing method. Octadecylphosphonic acid (ODPA self-assembled monolayer (SAM treatment of the AlOx was employed in order to realize high-performance (>0.4 cm2/Vs saturation mobility and low-operation-voltage (<5 V diketopyrrolopyrrole (DPP-based OTFTs on an ultra-thin polyimide film (3-μm thick. Thus, low-temperature photochemically-annealed solution-processed AlOx film with SAM layer is an attractive candidate as a dielectric-layer for use in high-performance organic TFTs operated at low voltages.

  17. Ferroelectric Single-Crystal Gated Graphene/Hexagonal-BN/Ferroelectric Field-Effect Transistor.

    Science.gov (United States)

    Park, Nahee; Kang, Haeyong; Park, Jeongmin; Lee, Yourack; Yun, Yoojoo; Lee, Jeong-Ho; Lee, Sang-Goo; Lee, Young Hee; Suh, Dongseok

    2015-11-24

    The effect of a ferroelectric polarization field on the charge transport in a two-dimensional (2D) material was examined using a graphene monolayer on a hexagonal boron nitride (hBN) field-effect transistor (FET) fabricated using a ferroelectric single-crystal substrate, (1-x)[Pb(Mg1/3Nb2/3)O3]-x[PbTiO3] (PMN-PT). In this configuration, the intrinsic properties of graphene were preserved with the use of an hBN flake, and the influence of the polarization field from PMN-PT could be distinguished. During a wide-range gate-voltage (VG) sweep, a sharp inversion of the spontaneous polarization affected the graphene channel conductance asymmetrically as well as an antihysteretic behavior. Additionally, a transition from antihysteresis to normal ferroelectric hysteresis occurred, depending on the V(G) sweep range relative to the ferroelectric coercive field. We developed a model to interpret the complex coupling among antihysteresis, current saturation, and sudden conductance variation in relation with the ferroelectric switching and the polarization-assisted charge trapping, which can be generalized to explain the combination of 2D structured materials with ferroelectrics.

  18. Double gate graphene nanoribbon field effect transistor with single halo pocket in channel region

    Science.gov (United States)

    Naderi, Ali

    2016-01-01

    A new structure for graphene nanoribbon field-effect transistors (GNRFETs) is proposed and investigated using quantum simulation with a nonequilibrium Green's function (NEGF) method. Tunneling leakage current and ambipolar conduction are known effects for MOSFET-like GNRFETs. To minimize these issues a novel structure with a simple change of the GNRFETs by using single halo pocket in the intrinsic channel region, "Single Halo GNRFET (SH-GNRFET)", is proposed. An appropriate halo pocket at source side of channel is used to modify potential distribution of the gate region and weaken band to band tunneling (BTBT). In devices with materials like Si in channel region, doping type of halo and source/drain regions are different. But, here, due to the smaller bandgap of graphene, the mentioned doping types should be the same to reduce BTBT. Simulations have shown that in comparison with conventional GNRFET (C-GNRFET), an SH-GNRFET with appropriately halo doping results in a larger ON current (Ion), smaller OFF current (Ioff), a larger ON-OFF current ratio (Ion/Ioff), superior ambipolar characteristics, a reduced power-delay product and lower delay time.

  19. Physically responsive field-effect transistors with giant electromechanical coupling induced by nanocomposite gate dielectrics.

    Science.gov (United States)

    Tien, Nguyen Thanh; Trung, Tran Quang; Seoul, Young Gug; Kim, Do Il; Lee, Nae-Eung

    2011-09-27

    Physically responsive field-effect transistors (physi-FETs) that are sensitive to physical stimuli have been studied for decades. The important issue for separating the responses of sensing materials from interference by other subcomponents in a FET transducer under global physical stimuli has not been completely resolved. In addition, challenges remain with regard to the design and employment of smart materials for flexible physi-FETs with a large electro-physical coupling effect. In this article, we propose the direct integration of nanocomposite (NC) gate dielectrics of barium titanate (BT) nanoparticles (NPs) and highly crystalline poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) into flexible organic FETs to achieve a large electro-physical coupling effect. Additionally, a new alternating current biasing method is proposed for precise extraction and quantification of tiny variations in the remnant polarization of NCs caused by mechanical stimuli. An investigation of physi-FETs under static mechanical stimuli revealed the first ever reported giant, positive piezoelectric coefficients of d(33) up to 960 pC/N in the NCs. The large coefficients are presumably due to the significant contributions of the intrinsic positive piezoelectricity of the BT NPs and P(VDF-TrFE) crystallites. © 2011 American Chemical Society

  20. Gate-Bias Stability Behavior Tailored by Dielectric Polymer Stereostructure in Organic Transistors.

    Science.gov (United States)

    Lee, Junghwi; Min, Honggi; Park, Namwoo; Jeong, Heejeong; Han, Singu; Kim, Se Hyun; Lee, Hwa Sung

    2015-11-18

    Understanding charge trapping in a polymer dielectric is critical to the design of high-performance organic field-effect transistors (OFETs). We investigated the OFET stability as a function of the dielectric polymer stereostructure under a gate bias stress and during long-term operation. To this end, iso-, syn-, and atactic poly(methyl methacrylate) (PMMA) polymers with identical molecular weights and polydispersity indices were selected. The PMMA stereostructure was found to significantly influence the charge trapping behavior and trap formation in the polymer dielectrics. This influence was especially strong in the bulk region rather than in the surface region. The regular configurational arrangements (isotactic > syntactic > atactic) of the pendant groups on the PMMA backbone chain facilitated closer packing between the polymer interchains and led to a higher crystallinity of the polymer dielectric, which caused a reduction in the free volumes that act as sites for charge trapping and air molecule absorption. The PMMA dielectrics with regular stereostructures (iso- and syn-stereoisomers) exhibited more stable OFET operation under bias stress compared to devices prepared using irregular a-PMMA in both vacuum and air.

  1. Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

    Directory of Open Access Journals (Sweden)

    Farhad Larki

    2012-12-01

    Full Text Available A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015 silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current.

  2. The impact of gate dielectric materials on the light-induced bias instability in Hf-In-Zn-O thin film transistor

    Science.gov (United States)

    Kwon, Jang-Yeon; Jung, Ji Sim; Son, Kyoung Seok; Lee, Kwang-Hee; Park, Joon Seok; Kim, Tae Sang; Park, Jin-Seong; Choi, Rino; Jeong, Jae Kyeong; Koo, Bonwon; Lee, Sang Yoon

    2010-11-01

    This study examined the effect of gate dielectric materials on the light-induced bias instability of Hf-In-Zn-O (HIZO) transistor. The HfOx and SiNx gated devices suffered from a huge negative threshold voltage (Vth) shift (>11 V) during the application of negative-bias-thermal illumination stress for 3 h. In contrast, the HIZO transistor exhibited much better stability (<2.0 V) in terms of Vth movement under identical stress conditions. Based on the experimental results, we propose a plausible degradation model for the trapping of the photocreated hole carrier either at the channel/gate dielectric or dielectric bulk layer.

  3. Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

    Science.gov (United States)

    Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

    2016-03-01

    Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect.

  4. Electron Spin Resonance Study of Organic Interfaces in Ion Gel-Gated Rubrene Single-Crystal Transistors

    Science.gov (United States)

    Takahashi, Yuki; Tsuji, Masaki; Yomogida, Yohei; Takenobu, Taishi; Iwasa, Yoshihiro; Marumoto, Kazuhiro

    2013-04-01

    Organic interfaces of rubrene single crystals (RSCs) in ion gel-gated electric double-layer transistors (EDLTs) were investigated by electron spin resonance (ESR). The EDLTs were fabricated by laminating ion-gel films onto RSCs. Clear ESR signals due to field-injected holes in RSCs were successfully observed at low gate voltages, showing a high spin concentration due to the high capacitance of EDLTs. The analyses of anisotropic ESR signals and its gate-voltage dependence show that the bulk molecular orientation at RSCs' interfaces is preserved without forming deep trapping levels, which demonstrate that organic interfaces in RSC-EDLTs are clean and undamaged under a strong electric field in EDLTs.

  5. Low-voltage large-current ion gel gated polymer transistors fabricated by a "cut and bond" process.

    Science.gov (United States)

    Shao, Xianyi; Bao, Bei; Zhao, Jiaqing; Tang, Wei; Wang, Shun; Guo, Xiaojun

    2015-03-04

    A "cut and bond" process using a commercial die bonder was developed for fabricating ion gel gated organic thin-film transistors (OTFTs). It addresses the issues of damaging or contaminating the channel layer when depositing the ion gel layer on top in conventional fabrication processes. The formed isolated dielectric regions can help to eliminate possible lateral electric field coupling through the dielectric layer when several devices are integrated to construct functional circuits. The fabricated OTFTs provide mA-level ON current, and an ON/OFF current ratio higher than 10(5) with the gate swing voltage of less than 3 V. With the developed process, the ion gel OTFTs are integrated with inorganic light emitting diodes (LEDs) of different colors on plastic substrate using the same die bonder, and the light emission of the LEDs can be modulated in a wide range from dark to high brightness with change of the gate voltage less than 3 V.

  6. Fabrication and independent control of patterned polymer gate for a few-layer WSe2 field-effect transistor

    Directory of Open Access Journals (Sweden)

    Sung Ju Hong

    2016-08-01

    Full Text Available We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D semiconductor, few-layer tungsten diselenide (WSe2 field-effect transistor (FET. We expose an electron-beam in a desirable region to form the patterned structure. The WSe2 FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS2 FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibility in transition metal dichalcogenide (TMD-based electronics.

  7. Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

    Science.gov (United States)

    Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

    2017-01-01

    Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low-k). To supplement low-k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high-k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high-k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3.

  8. Current saturation and kink effect in zero-bandgap double-gate silicene field-effect transistors

    Science.gov (United States)

    Patel, Nishant; Choudhary, Sudhanshu

    2017-10-01

    Double gate silicene field effect transistor is investigated using Density Functional Theory (DFT) and Non-Equilibrium Green's Function (NEGF) formalism. The results suggest that with an increase in gate bias, bandgap is introduced in silicene which results in reduction in device current. The increase in silicene bandgap is also related to the reduction in channel length. It is observed that drain to source current (IDS) saturates on increasing drain to source voltage (VDS). On increasing VDS beyond saturation region, at some value of VDS kink effect is seen which is due to switching in the type of carriers at the drain end due to ambipolar channel. Transconductance (gm) is seen to reduce with reduction in channel length, however, gm improves with reduced oxide thickness due to better gate controllability. The output characteristics do not change much with oxide thickness.

  9. Top gate ZnO-Al2O3 thin film transistors fabricated using a chemical bath deposition technique

    Science.gov (United States)

    Gogoi, Paragjyoti; Saikia, Rajib; Changmai, Sanjib

    2015-04-01

    ZnO thin films were prepared by a simple chemical bath deposition technique using an inorganic solution mixture of ZnCl2 and NH3 on glass substrates and then were used as the active material in thin film transistors (TFTs). The TFTs were fabricated in a top gate coplanar electrode structure with high-k Al2O3 as the gate insulator and Al as the source, drain and gate electrodes. The TFTs were annealed in air at 500 °C for 1 h. The TFTs with a 50 μm channel length exhibited a high field-effect mobility of 0.45 cm2/(V·s) and a low threshold voltage of 1.8 V. The sub-threshold swing and drain current ON-OFF ratio were found to be 0.6 V/dec and 106, respectively.

  10. Novel process for widening memory window of sub-200 nm ferroelectric-gate field-effect transistor by ferroelectric coating the gate-stack sidewall

    Science.gov (United States)

    Van Hai, Le; Takahashi, Mitsue; Zhang, Wei; Sakai, Shigeki

    2015-01-01

    Ferroelectric-gate field-effect transistors (FeFETs) with metallurgical-gate lengths of 140 nm, 160 nm and 190 nm were successfully fabricated using a novel fabrication process. The gate stacks of the FeFETs were Pt/Sr0.8Ca0.2Bi2Ta2O9(SCBT)/HfO2/Si. Key to the process was covering the as-etched gate-stack sidewalls with SCBT precursor films and annealing altogether. The FeFETs which underwent the novel process showed larger memory windows than those without the process by about 0.5 V at scanned gate-voltages of 1 ± 5 V. Endurances of the FeFETs made by the novel process were measured up to 109 cycles with good separations of the on- and off-states. The endurance pulses were 1 ± 5 V with 2 μs period. Good data-retentions of them were also demonstrated which were measured for at least 6.5 days.

  11. AlGaN/GaN high electron mobility transistors with selective area grown p-GaN gates

    Science.gov (United States)

    Yuliang, Huang; Lian, Zhang; Zhe, Cheng; Yun, Zhang; Yujie, Ai; Yongbing, Zhao; Hongxi, Lu; Junxi, Wang; Jinmin, Li

    2016-11-01

    We report a selective area growth (SAG) method to define the p-GaN gate of AlGaN/GaN high electron mobility transistors (HEMTs) by metal-organic chemical vapor deposition. Compared with Schottky gate HEMTs, the SAG p-GaN gate HEMTs show more positive threshold voltage (V th) and better gate control ability. The influence of Cp2Mg flux of SAG p-GaN gate on the AlGaN/GaN HEMTs has also been studied. With the increasing Cp2Mg from 0.16 μmol/min to 0.20 μmol/min, the V th raises from -0.67 V to -0.37 V. The maximum transconductance of the SAG HEMT at a drain voltage of 10 V is 113.9 mS/mm while that value of the Schottky HEMT is 51.6 mS/mm. The SAG method paves a promising way for achieving p-GaN gate normally-off AlGaN/GaN HEMTs without dry etching damage. Project supported by the National Natural Sciences Foundation of China (Nos. 61376090, 61306008) and the National High Technology Program of China (No. 2014AA032606).

  12. Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

    Institute of Scientific and Technical Information of China (English)

    Zheng Zhi; Li Wei; Li Ping

    2013-01-01

    A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper.Based on this principle,the floating layer can pin the potential for modulating bulk field.In particular,the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX).At variation of back-gate bias,the shielding charges of NFL can alsoeliminate back-gate effects.The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS,yielding a 77% improvement.Furthermore,due to the field shielding effect of the NFL,the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.

  13. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio

    Science.gov (United States)

    Vu, Quoc An; Shin, Yong Seon; Kim, Young Rae; Nguyen, Van Luan; Kang, Won Tae; Kim, Hyun; Luong, Dinh Hoa; Lee, Il Min; Lee, Kiyoung; Ko, Dong-Su; Heo, Jinseong; Park, Seongjun; Lee, Young Hee; Yu, Woo Jong

    2016-09-01

    Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10-14 A, leading to ultrahigh on/off ratio over 109, about ~103 times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics.

  14. Insulated gate and surface passivation structures for GaN-based power transistors

    Science.gov (United States)

    Yatabe, Zenji; Asubar, Joel T.; Hashizume, Tamotsu

    2016-10-01

    Recent years have witnessed GaN-based devices delivering their promise of unprecedented power and frequency levels and demonstrating their capability as an able replacement for Si-based devices. High-electron-mobility transistors (HEMTs), a key representative architecture of GaN-based devices, are well-suited for high-power and high frequency device applications, owing to highly desirable III-nitride physical properties. However, these devices are still hounded by issues not previously encountered in their more established Si- and GaAs-based devices counterparts. Metal-insulator-semiconductor (MIS) structures are usually employed with varying degrees of success in sidestepping the major problematic issues such as excessive leakage current and current instability. While different insulator materials have been applied to GaN-based transistors, the properties of insulator/III-N interfaces are still not fully understood. This is mainly due to the difficulty of characterizing insulator/AlGaN interfaces in a MIS HEMT because of the two resulting interfaces: insulator/AlGaN and AlGaN/GaN, making the potential modulation rather complicated. Although there have been many reports of low interface-trap densities in HEMT MIS capacitors, several papers have incorrectly evaluated their capacitance-voltage (C-V) characteristics. A HEMT MIS structure typically shows a 2-step C-V behavior. However, several groups reported C-V curves without the characteristic step at the forward bias regime, which is likely to the high-density states at the insulator/AlGaN interface impeding the potential control of the AlGaN surface by the gate bias. In this review paper, first we describe critical issues and problems including leakage current, current collapse and threshold voltage instability in AlGaN/GaN HEMTs. Then we present interface properties, focusing on interface states, of GaN MIS systems using oxides, nitrides and high-κ dielectrics. Next, the properties of a variety of AlGaN/GaN MIS

  15. Gate bias stress stability under light irradiation for indium zinc oxide thin-film transistors based on anodic aluminium oxide gate dielectrics

    Science.gov (United States)

    Li, Min; Lan, Linfeng; Xu, Miao; Wang, Lei; Xu, Hua; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Yao, Rihui; Peng, Junbiao

    2011-11-01

    Thin-film transistors (TFTs) using indium zinc oxide as the active layer and anodic aluminium oxide (Al2O3) as the gate dielectric layer were fabricated. The device showed an electron mobility of as high as 10.1 cm2 V-1 s-1, an on/off current ratio of as high as ~108, and a turn-on voltage (Von) of only -0.5 V. Furthermore, this kind of TFTs was very stable under positive bias illumination stress. However, when the device experienced negative bias illumination stress, the threshold voltage shifted to the positive direction. It was found that the instability under negative bias illumination stress (NBIS) was due to the electrons from the Al gate trapping into the Al2O3 dielectric when exposed to the illuminated light. Using a stacked structure of Al2O3/SiO2 dielectrics, the device became more stable under NBIS.

  16. The Theoretical Investigation and Analysis of High-Performance ZnO Double-Gate Double-Layer Insulator Thin-Film Transistors

    Institute of Scientific and Technical Information of China (English)

    GAO Hai-Xia; HU Rong; YANG Yin-Tang

    2012-01-01

    A novel structure of a ZnO thin-film transistor with a double-gate and double-layer insulator is proposed to improve device performance.Compared with the conventional ZnO thin-film transistor structure,the novel thinfilm transistor has a higher on-state current,steeper sub-threshold characteristics and a lower threshold voltage,owing to the double-gate and high-k dielectric.Based on two-dimensional simulation,the potential channel distribution and the reasons for the improvement in performance are investigated.%A novei structure of a ZnO thin-film transistor with a double-gate and double-layer insulator is proposed to improve device performance. Compared with the conventional ZnO thin-Rim transistor structure, the novel thin-Sim transistor has a higher on-state current, steeper sub-threshold characteristics and a lower threshold voltage, owing to the double-gate and high-k dielectric. Based on two-dimensional simulation, the potential channel distribution and the reasons for the improvement in performance are investigated.

  17. Back-gated Nb-doped MoS2 junctionless field-effect-transistors

    Directory of Open Access Journals (Sweden)

    Gioele Mirabelli

    2016-02-01

    Full Text Available Electrical measurements were carried out to measure the performance and evaluate the characteristics of MoS2 flakes doped with Niobium (Nb. The flakes were obtained by mechanical exfoliation and transferred onto 85 nm thick SiO2 oxide and a highly doped Si handle wafer. Ti/Au (5/45 nm deposited on top of the flake allowed the realization of a back-gate structure, which was analyzed structurally through Scanning Electron Microscopy (SEM and Transmission Electron Microscopy (TEM. To best of our knowledge this is the first cross-sectional TEM study of exfoliated Nb-doped MoS2 flakes. In fact to date TEM of transition-metal-dichalcogenide flakes is extremely rare in the literature, considering the recent body of work. The devices were then electrically characterized by temperature dependent Ids versus Vds and Ids versus Vbg curves. The temperature dependency of the device shows a semiconductor behavior and, the doping effect by Nb atoms introduces acceptors in the structure, with a p-type concentration 4.3 × 1019 cm−3 measured by Hall effect. The p-type doping is confirmed by all the electrical measurements, making the structure a junctionless transistor. In addition, other parameters regarding the contact resistance between the top metal and MoS2 are extracted thanks to a simple Transfer Length Method (TLM structure, showing a promising contact resistivity of 1.05 × 10−7 Ω/cm2 and a sheet resistance of 2.36 × 102 Ω/sq.

  18. A study on III-nitride recessed-gate field-effect transistors using a remote-oxygen-plasma treatment

    Science.gov (United States)

    Lee, Y.-C.; Kao, T.-T.; Shen, S.-C.

    2015-04-01

    We report a comparative study of the device performance of III-nitride (III-N) heterojunction field-effect transistors (HFETs) and metal-insulator-semiconductor field-effect transistors (MISFETs). The influence of a remote-oxygen-plasma treatment was investigated. The plasma-treated recessed-gate HFETs and MISFETs show normally-off characteristics with higher peak transconductance, lower sub-threshold slope, smaller hysteresis. An on-off ratio greater than 2.2E11 with a significant suppression of gate leakage can be achieved in plasma-treated III-N MISFETs. A drain current transient measurement was performed to analyze the traps in these devices and possible origins of these traps are studied. Six traps with characteristic time constants (τ) ranging from 180 s to 3 ms are identified in both HFETs and MISFETs, in addition to a trap which is associated with the ALD-grown gate dielectrics for the MISFETs. The results suggest that improved device performance in these plasma-treated III-N FETs is attributed to the reduced trap states with τ 2 s) cannot be reduced by the plasma treatment and are related to the oxygen and carbon impurities and the buffer traps in the bulk semiconductors.

  19. A self-amplified transistor immunosensor under dual gate operation: highly sensitive detection of hepatitis B surface antigen

    Science.gov (United States)

    Lee, I.-K.; Jeun, M.; Jang, H.-J.; Cho, W.-J.; Lee, K. H.

    2015-10-01

    Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor based on a self-amplified transistor under dual gate operation (immuno-DG ISFET) for the detection of hepatitis B surface antigen. To address the challenges in current ISFET-based immunosensors, we have enhanced the sensitivity of an immunosensor by precisely tailoring the nanostructure of the transistor. In the pH sensing test, the immuno-DG ISFET showed superior sensitivity (2085.53 mV per pH) to both standard ISFET under single gate operation (58.88 mV per pH) and DG ISFET with a non-tailored transistor (381.14 mV per pH). Moreover, concerning the detection of hepatitis B surface antigens (HBsAg) using the immuno-DG ISFET, we have successfully detected trace amounts of HBsAg (22.5 fg mL-1) in a non-diluted 1× PBS medium with a high sensitivity of 690 mV. Our results demonstrate that the proposed immuno-DG ISFET can be a biosensor platform for practical use in the diagnosis of various diseases.Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor

  20. Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

    Institute of Scientific and Technical Information of China (English)

    YU Ai-Fang; QI Qiong; JIANG Peng; JIANG Chao

    2009-01-01

    Carrier mobifity enhancement from 0.09 to 0.59cm2/Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO2 surface is believed to be the origin of the excellent carrier mobifity of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski-Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility.

  1. Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

    Directory of Open Access Journals (Sweden)

    Yu-Hsien Lin

    2014-01-01

    Full Text Available This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using hafnium oxide (HfO2 gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO2 dielectric thin film during high-temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO2 gate dielectric TFT exhibiting high mobility, a high ION/IOFF ratio, low IOFF current, and excellent subthreshold swing (SS.

  2. Bio-fabrication of nanomesh channels of single-walled carbon nanotubes for locally gated field-effect transistors

    Science.gov (United States)

    Byeon, Hye-Hyeon; Lee, Woo Chul; Kim, Wonbin; Kim, Seong Keun; Kim, Woong; Yi, Hyunjung

    2017-01-01

    Single-walled carbon nanotubes (SWNTs) are one of the promising electronic components for nanoscale electronic devices such as field-effect transistors (FETs) owing to their excellent device characteristics such as high conductivity, high carrier mobility and mechanical flexibility. Localized gating gemometry of FETs enables individual addressing of active channels and allows for better electrostatics via thinner dielectric layer of high k-value. For localized gating of SWNTs, it becomes critical to define SWNTs of controlled nanostructures and functionality onto desired locations in high precision. Here, we demonstrate that a biologically templated approach in combination of microfabrication processes can successfully produce a nanostructured channels of SWNTs for localized active devices such as local bottom-gated FETs. A large-scale nanostructured network, nanomesh, of SWNTs were assembled in solution using an M13 phage with strong binding affinity toward SWNTs and micrometer-scale nanomesh channels were defined using negative photolithography and plasma-etching processes. The bio-fabrication approach produced local bottom-gated FETs with remarkably controllable nanostructures and successfully enabled semiconducting behavior out of unsorted SWNTs. In addition, the localized gating scheme enhanced the device performances such as operation voltage and I on/I off ratio. We believe that our approach provides a useful and integrative method for fabricating electronic devices out of nanoscale electronic materials for applications in which tunable electrical properties, mechanical flexibility, ambient stability, and chemical stability are of crucial importance.

  3. A self-amplified transistor immunosensor under dual gate operation: highly sensitive detection of hepatitis B surface antigen.

    Science.gov (United States)

    Lee, I-K; Jeun, M; Jang, H-J; Cho, W-J; Lee, K H

    2015-10-28

    Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor based on a self-amplified transistor under dual gate operation (immuno-DG ISFET) for the detection of hepatitis B surface antigen. To address the challenges in current ISFET-based immunosensors, we have enhanced the sensitivity of an immunosensor by precisely tailoring the nanostructure of the transistor. In the pH sensing test, the immuno-DG ISFET showed superior sensitivity (2085.53 mV per pH) to both standard ISFET under single gate operation (58.88 mV per pH) and DG ISFET with a non-tailored transistor (381.14 mV per pH). Moreover, concerning the detection of hepatitis B surface antigens (HBsAg) using the immuno-DG ISFET, we have successfully detected trace amounts of HBsAg (22.5 fg mL(-1)) in a non-diluted 1× PBS medium with a high sensitivity of 690 mV. Our results demonstrate that the proposed immuno-DG ISFET can be a biosensor platform for practical use in the diagnosis of various diseases.

  4. A New Structure of Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor to Suppress the Floating Body Effect

    Institute of Scientific and Technical Information of China (English)

    朱鸣; 林青; 张正选; 林成鲁

    2003-01-01

    Considering that the silicon-on-insulator (SOI) devices have an inherent floating body effect, which may cause substantial influences in the performance of SOI device and circuit, we propose a novel device structure to suppress the floating body effect. In the new structure there is a buried p+ region under the n+ source and that region is extended to outside of the source, and this additional p+ region provides a path for accumulated holes to flow out of the body. Numerical simulations were carried out with Medici, and the output characteristics and gate characteristics were compared with those of conventional SOI counterparts. The simulated results show the suppression of floating body effect in the novel SOI device as expected.

  5. Influence of Gate Dielectric and Its Surface Treatment on Electrical Characteristics of Solution-Processed ZnO Transistors.

    Science.gov (United States)

    Song, Dong-Seok; Kim, Jae-Hyun; Jung, Ji-Hoon; Bae, Jin-Hyuk; Zhang, Xue; Park, Ji-Ho; Park, Jaehoon

    2016-02-01

    We report how interface treatments affect electrical performance, including subthreshold characteristics, in solution-processed transparent metal oxide thin-film transistors (TFTs) with SiO2 and SiNx gate dielectrics. Ultra-violet (UV) ozone treatment and O2 plasma treatment are carried out as a surface treatment of the interface between a spin-coated zinc oxide (ZnO) layer and a gate dielectric. With the SiO2 dielectric, UV ozone treatment dominantly affects subthreshold characteristics, while O2 plasma treatment produces enhanced mobility and lower threshold voltage shift. With the SiNx dielectric, every electrical parameter including mobility, threshold voltage shift, and subthreshold characteristics is enhanced by 02 plasma treatment. Our experimental results demonstrate that interface engineering treatments variously influence the electrical performance in solution-processed ZnO TFTs.

  6. Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

    Science.gov (United States)

    Jo, Kwang-Won; Cho, Won-Ju

    2014-11-01

    In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔVON) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.

  7. High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

    Directory of Open Access Journals (Sweden)

    Murali Gedda

    2013-11-01

    Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

  8. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    Science.gov (United States)

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-12-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

  9. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    Science.gov (United States)

    Tari, Alireza; Lee, Czang-Ho; Wong, William S.

    2015-07-01

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO2, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiNx, and (3) a PECVD SiOx/SiNx dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the Vo concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiNx (high Vo) and SiO2 (low Vo) had the highest and lowest conductivity, respectively. A PECVD SiOx/SiNx dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  10. Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

    Science.gov (United States)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2013-10-01

    In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

  11. Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Siyang; Zhang, Chunwei; Sun, Weifeng, E-mail: swffrog@seu.edu.cn [National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 (China); Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu [CSMC Technologies Corporation, Wuxi 214061 (China)

    2014-04-14

    Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic.

  12. Experimental study on radiation effects in floating gate read-only-memories and static random access memories

    Institute of Scientific and Technical Information of China (English)

    He Chao-Hui; Li Yong-Hong

    2007-01-01

    Radiation effects of the floating gate read-only-memory (FG ROM) and the static random access memory (SRAM)have been evaluated using the 14 MeV neutron and 31.9MeV proton beams and Co-60 γ-rays. The neutron fluence,when the first error occurs in the FG ROMs, is at least 5 orders of magnitude higher than that in the SRAMs, and the proton fluence, 4 orders of magnitude higher. The total dose threshold for Co-60 γ-ray irradiation is about 104 rad (Si)for both memories. The difference and similarity are attributed to the structure of the memory cells and the mechanism of radiation effects. It is concluded that the FG ROMs are more reliable as semiconductor memories for storing data than the SRAMs, when they are used in the satellites or space crafts exposed to high energy particle radiation.

  13. Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

    Science.gov (United States)

    Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

    2016-12-01

    This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

  14. Ultra-Low-Voltage Low-Power Bulk-Driven Quasi-Floating-Gate Operational Transconductance Amplifier

    Directory of Open Access Journals (Sweden)

    Ziad Alsibai

    2014-01-01

    Full Text Available A new ultra-low-voltage (LV low-power (LP bulk-driven quasi-floating-gate (BD-QFG operational transconductance amplifier (OTA is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW.

  15. Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

    Science.gov (United States)

    Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

    2013-01-01

    Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

  16. Improved Carrier Mobility in Few-Layer MoS2 Field-Effect Transistors with Ionic-Liquid Gating

    Science.gov (United States)

    Perera, Meeghage; Lin, Ming-Wei; Chuang, Hsun-Jen; Chamlagain, Bhim; Wang, Chongyu; Tan, Xuebin; Cheng, Mark; Tománek, David; Zhou, Zhixian

    2014-03-01

    We report the fabrication of ionic liquid (IL) gated field-effect transistors (FETs) consisting of bilayer and few-layer MoS2. Our transport measurements indicate that the electron mobility μ ~ 60 cm2V-1s-1 at 250 K in ionic liquid gated devices exceeds significantly that of comparable back-gated devices. IL-FETs display a mobility increase from ~100 cm2V-1s-1 at 180 K to ~220 cm2V-1s-1 at 77 K in good agreement with the true channel mobility determined from four-terminal measurements, ambipolar behavior with a high ON/OFF ratio >107 (104) for electrons (holes), and a near ideal sub-threshold swing of ~50 mV/dec at 250 K. We attribute the observed performance enhancement, specifically the increased carrier mobility that is limited by phonons, to the reduction of the Schottky barrier at the source and drain electrode by band bending caused by the ultrathin ionic-liquid dielectric layer. In addition, graphene contacted MoS2 FETs with IL-gating will also be discussed. This work was supported by NSF (No. ECCS-1128297).

  17. Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

    Directory of Open Access Journals (Sweden)

    Yu-Hsien Lin

    2015-01-01

    Full Text Available We investigated amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using different high-k gate dielectric materials such as silicon nitride (Si3N4 and aluminum oxide (Al2O3 at low temperature process (<300°C and compared them with low temperature silicon dioxide (SiO2. The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

  18. Dirac point and transconductance of top-gated graphene field-effect transistors operating at elevated temperature

    Energy Technology Data Exchange (ETDEWEB)

    Hopf, T.; Vassilevski, K. V., E-mail: k.vasilevskiy@ncl.ac.uk; Escobedo-Cousin, E.; King, P. J.; Wright, N. G.; O' Neill, A. G.; Horsfall, A. B.; Goss, J. P. [School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne NE1 7RU (United Kingdom); Wells, G. H.; Hunt, M. R. C. [Department of Physics, Durham University, Durham DH1 3LE (United Kingdom)

    2014-10-21

    Top-gated graphene field-effect transistors (GFETs) have been fabricated using bilayer epitaxial graphene grown on the Si-face of 4H-SiC substrates by thermal decomposition of silicon carbide in high vacuum. Graphene films were characterized by Raman spectroscopy, Atomic Force Microscopy, Scanning Tunnelling Microscopy, and Hall measurements to estimate graphene thickness, morphology, and charge transport properties. A 27 nm thick Al₂O₃ gate dielectric was grown by atomic layer deposition with an e-beam evaporated Al seed layer. Electrical characterization of the GFETs has been performed at operating temperatures up to 100 °C limited by deterioration of the gate dielectric performance at higher temperatures. Devices displayed stable operation with the gate oxide dielectric strength exceeding 4.5 MV/cm at 100 °C. Significant shifting of the charge neutrality point and an increase of the peak transconductance were observed in the GFETs as the operating temperature was elevated from room temperature to 100 °C.

  19. Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

    Science.gov (United States)

    Choi, Youn Sung; Numata, Toshinori; Nishida, Toshikazu; Harris, Rusty; Thompson, Scott E.

    2008-03-01

    Uniaxial four-point wafer bending stress-altered gate tunneling currents are measured for germanium (Ge)/silicon (Si) channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with HfO2/SiO2 gate dielectrics and TiN/P+ poly Si electrodes. Carrier separation is used to measure electron and hole currents. The strain-altered hole tunneling current from the p-type inversion layer of Ge is measured to be ˜4 times larger than that for the Si channel MOSFET, since the larger strain-induced valence band-edge splitting in Ge results in more hole repopulation into a subband with a smaller out-of-plane effective mass and a lower tunneling barrier height. The strain-altered electron tunneling current from the metal gate is measured and shown to change due to strain altering the metal work function as quantified by flatband voltage shift measurements of Si MOS capacitors with TaN electrodes.

  20. New adders using hybrid circuit consisting of three-gate single-electron transistors (TG-SETs) and MOSFETs.

    Science.gov (United States)

    Yu, YunSeop; Choi, JungBum

    2007-11-01

    A half-adder (HA) and a full-adder (FA) using hybrid circuits combining three-gate single-electron transistors (TG-SETs) with metal-oxide-semiconductor field-effect-transistors (MOSFETs) are proposed. The proposed HA consists of three TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs, and the proposed FA consists of eight TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs. The complexities in the HA and the FA are 7 and 12, respectively, and the worst-case delays in the HA and the FA are 1.48 ns and 2.25 ns, respectively. Compared with the conventional CMOS FA with 0.35 microm technology, the proposed FA can be constructed with 0.43 of devices, and can operate with 3.5 of worst-case delay, 1/534 of average power consumption, and 1/152 of power-delay-product (PDP). The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are fitly determined. The basic operations of the proposed HA and the proposed FA have been successfully confirmed through SPICE circuit simulation based on the physical device model of TG-SETs.

  1. Positive charge trapping phenomenon in n-channel thin-film transistors with amorphous alumina gate insulators

    Science.gov (United States)

    Daus, Alwin; Vogt, Christian; Münzenrieder, Niko; Petti, Luisa; Knobelspies, Stefan; Cantarella, Giuseppe; Luisier, Mathieu; Salvatore, Giovanni A.; Tröster, Gerhard

    2016-12-01

    In this work, we investigate the charge trapping behavior in InGaZnO4 (IGZO) thin-film transistors with amorphous Al2O3 (alumina) gate insulators. For thicknesses ≤10 nm, we observe a positive charge generation at intrinsic defects inside the Al2O3, which is initiated by quantum-mechanical tunneling of electrons from the semiconductor through the Al2O3 layer. Consequently, the drain current shows a counter-clockwise hysteresis. Furthermore, the de-trapping through resonant tunneling causes a drastic subthreshold swing reduction. We report a minimum value of 19 mV/dec at room temperature, which is far below the fundamental limit of standard field-effect transistors. Additionally, we study the thickness dependence for Al2O3 layers with thicknesses of 5, 10, and 20 nm. The comparison of two different gate metals shows an enhanced tunneling current and an enhanced positive charge generation for Cu compared to Cr.

  2. Processing and performance of organic insulators as a gate layer in organic thin film transistors fabricated on polyethylene terephthalate substrate

    Indian Academy of Sciences (India)

    Saumen Mandal; Monica Katiyar

    2013-08-01

    Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering processing of dielectric layer on polyethylene terephthalate (PET), characterization of dielectric property, pentacene film morphology and OTFT characterization. Here, we present the processing and performance of three organic dielectrics, poly(4-vinylphenol) (PVPh), polyvinyl alcohol (PVA) and poly(methylmethacrylate) (PMMA), as a gate layer in pentacene-based organic thin film transistor on PET substrate. We have used thermogravimetric analysis of organic dielectric solution to determine annealing temperature for spin-coated films of these dielectrics. Comparison of the leakage currents for the three dielectrics shows PVA exhibiting lowest leakage (in the voltage range of −30 to +30 V). This is partly because solvent is completely eliminated in the case of PVA as observed by differential thermogravimetric analysis (DTGA). We propose that DTGA can be a useful tool to optimize processing of dielectric layers. From organic thin film transistor point of view, crystal structure, morphology and surface roughness of pentacene film on all the dielectric layers were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM).We observe pyramidal pentacene on PVPh whereas commonly observed dendritic pentacene on PMMA and PVA surface. Pentacene morphology development is discussed in terms of surface roughness, surface energy and molecular nature of the dielectric layer.

  3. High mobility and low density of trap states in dual-solid-gated PbS nanocrystal field-effect transistors.

    Science.gov (United States)

    Nugraha, Mohamad Insan; Häusermann, Roger; Bisri, Satria Zulkarnaen; Matsui, Hiroyuki; Sytnyk, Mykhailo; Heiss, Wolfgang; Takeya, Jun; Loi, Maria Antonietta

    2015-03-25

    Dual-gated PbS nanocrystal field-effect transistors employing SiO2 and Cytop as gate dielectrics are fabricated. The obtained electron mobility (0.2 cm(2) V(-1) s(-1) ) and the high on/off ratio (10(5) -10(6) ), show that the controlled nanocrystal assembly (obtained with self-assembled monolayers), as well as the trap density reduction (using Cytop as dielectric), are crucial steps for the future application of nanocrystals.

  4. AlGaN/GaN high-electron-mobility transistors with transparent gates by Al-doped ZnO

    Institute of Scientific and Technical Information of China (English)

    Wang Chong; He Yun-Long; Zheng Xue-Feng; Ma Xiao-Hua; Zhang Jin-Cheng; Hao Yue

    2013-01-01

    AlGaN/GaN high-electron-mobility transistors (HEMTs) with Al-doped ZnO (AZO) transparent gate electrodes are fabricated,and Ni/Au/Ni-gated HEMTs are produced in comparison.The AZO-gated HEMTs show good DC characteristics and Schottky rectifying characteristics,and the gate electrodes achieve excellent transparencies.Compared with Ni/Au/Ni-gated HEMTs,AZO-gated HEMTs show a low saturation current,high threshold voltage,high Schottky barrier height,and low gate reverse leakage current.Due to the higher gate resistivity,AZO-gated HEMTs exhibit a current-gain cutoff frequency (fT) of 10 GHz and a power gain cutoff frequency (fmax) of 5 GHz,and lower maximum oscillation frequency than Ni/Au/Ni-gated HEMTs.Moreover,the C-V characteristics are measured and the gate interface characteristics of the AZO-gated devices are investigated by a C-V dual sweep.

  5. Enhancement mode AlGaN/GaN MOS high-electron-mobility transistors with ZrO2 gate dielectric deposited by atomic layer deposition

    Science.gov (United States)

    Anderson, Travis J.; Wheeler, Virginia D.; Shahin, David I.; Tadjer, Marko J.; Koehler, Andrew D.; Hobart, Karl D.; Christou, Aris; Kub, Francis J.; Eddy, Charles R., Jr.

    2016-07-01

    Advanced applications of AlGaN/GaN high-electron-mobility transistors (HEMTs) in high-power RF and power switching are driving the need for insulated gate technology. We present a metal-oxide-semiconductor (MOS) gate structure using atomic-layer-deposited ZrO2 as a high-k, high-breakdown gate dielectric for reduced gate leakage and a recessed barrier structure for enhancement mode operation. Compared to a Schottky metal-gate HEMT, the recessed MOS-HEMT structure demonstrated a reduction in the gate leakage current by 4 orders of magnitude and a threshold voltage shift of +6 V to a record +3.99 V, enabled by a combination of a recessed barrier structure and negative oxide charge.

  6. Single electron charge sensitivity of liquid-gated carbon nanotube transistors.

    Science.gov (United States)

    Sharf, Tal; Wang, Neng-Ping; Kevek, Joshua W; Brown, Morgan A; Wilson, Heather; Heinze, Stefan; Minot, Ethan D

    2014-09-10

    Random telegraph signals corresponding to activated charge traps were observed with liquid-gated CNT FETs. The high signal-to-noise ratio that we observe demonstrates that single electron charge sensing is possible with CNT FETs in liquids at room temperature. We have characterized the gate-voltage dependence of the random telegraph signals and compared to theoretical predictions. The gate-voltage dependence clearly identifies the sign of the activated trapped charge.

  7. Piezo-phototronic Boolean logic and computation using photon and strain dual-gated nanowire transistors.

    Science.gov (United States)

    Yu, Ruomeng; Wu, Wenzhuo; Pan, Caofeng; Wang, Zhaona; Ding, Yong; Wang, Zhong Lin

    2015-02-04

    Using polarization charges created at the metal-cadmium sulfide interface under strain to gate/modulate electrical transport and optoelectronic processes of charge carriers, the piezo-phototronic effect is applied to process mechanical and optical stimuli into electronic controlling signals. The cascade nanowire networks are demonstrated for achieving logic gates, binary computations, and gated D latches to store information carried by these stimuli.

  8. PMMA–SiO{sub 2} hybrid films as gate dielectric for ZnO based thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Morales-Acosta, M.D. [Centro de Investigación y de Estudios Avanzados del IPN, Unidad Querétaro, Apdo. Postal 1-798, Querétaro, Qro. 76001 (Mexico); Quevedo-López, M.A. [Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX 75083 (United States); Ramírez-Bon, R., E-mail: rrbon@qro.cinvestav.mx [Centro de Investigación y de Estudios Avanzados del IPN, Unidad Querétaro, Apdo. Postal 1-798, Querétaro, Qro. 76001 (Mexico)

    2014-08-01

    In this paper we report a low temperature sol–gel deposition process of PMMA–SiO{sub 2} hybrid films, with variable dielectric properties depending on the composition of the precursor solution, for applications to gate dielectric layers in field-effect thin film transistors (FE-TFT). The hybrid layers were processed by a modified sol–gel route using as precursors Tetraethyl orthosilicate (TEOS) and Methyl methacrylate (MMA), and 3-(Trimethoxysilyl)propyl methacrylate (TMSPM) as the coupling agent. Three types of hybrid films were processed with molar ratios of the precursors in the initial solution 1.0: 0.25, 0.50, 0.75: 1.0 for TEOS: TMSPM: MMA, respectively. The hybrid films were deposited by spin coating of the hybrid precursor solutions onto p-type Si (100) substrates and heat-treated at 90 °C for 24 h. The chemical bonding in the hybrid films was analyzed by Fourier Transform Infrared Spectroscopy to confirm their hybrid nature. The refractive index of the hybrid films as a function of the TMSPM coupling agent concentration, were determined from a simultaneous analysis of optical reflectance and spectroscopic ellipsometry experimental data. The PMMA–SiO{sub 2} hybrid films were studied as dielectric films using metal-insulator-metal structures. Capacitance–Voltage (C–V) and current–voltage (I–V) electrical methods were used to extract the dielectric properties of the different hybrid layers. The three types of hybrid films were tested as gate dielectric layers in thin film transistors with structure ZnO/PMMA–SiO{sub 2}/p-Si with a common bottom gate and patterned Al source/drain contacts, with different channel lengths. We analyzed the output electrical responses of the ZnO-based TFTs to determine their performance parameters as a function of channel length and hybrid gate dielectric layer. - Highlights: • PMMA–SiO{sub 2} hybrid films as dielectric material synthesized by sol–gel process at low temperature. • PMMA–SiO{sub 2

  9. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

    NARCIS (Netherlands)

    Niang, K.M.; Barquinha, P.M.C.; Martins, R.F.P.; Cobb, B.; Powell, M.J.; Flewitt, A.J.

    2016-01-01

    Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analyse

  10. Electro-Thermo-Mechanical Analysis of High-Power Press-Pack Insulated Gate Bipolar Transistors under Various Mechanical Clamping Conditions

    DEFF Research Database (Denmark)

    Hasmasan, Adrian Augustin; Busca, Cristian; Teodorescu, Remus;

    2014-01-01

    production. The reliability of the components has a large impact on the overall cost of a WT, and press-pack (PP) insulated gate bipolar transistors (IGBTs) could be a good solution for future multi-megawatt WTs because of advantages like high power density and reliability. When used in power converters, PP...

  11. Water-Gated n-Type Organic Field-Effect Transistors for Complementary Integrated Circuits Operating in an Aqueous Environment

    Science.gov (United States)

    2017-01-01

    The first demonstration of an n-type water-gated organic field-effect transistor (WGOFET) is here reported, along with simple water-gated complementary integrated circuits, in the form of inverting logic gates. For the n-type WGOFET active layer, high-electron-affinity organic semiconductors, including naphthalene diimide co-polymers and a soluble fullerene derivative, have been compared, with the latter enabling a high electric double layer capacitance in the range of 1 μF cm–2 in full accumulation and a mobility–capacitance product of 7 × 10–3 μF/V s. Short-term stability measurements indicate promising cycling robustness, despite operating the device in an environment typically considered harsh, especially for electron-transporting organic molecules. This work paves the way toward advanced circuitry design for signal conditioning and actuation in an aqueous environment and opens new perspectives in the implementation of active bio-organic interfaces for biosensing and neuromodulation.

  12. Effect of gate length on breakdown voltage in AlGaN/GaN high-electron-mobility transistor

    Science.gov (United States)

    Jun, Luo; Sheng-Lei, Zhao; Min-Han, Mi; Wei-Wei, Chen; Bin, Hou; Jin-Cheng, Zhang; Xiao-Hua, Ma; Yue, Hao

    2016-02-01

    The effects of gate length LG on breakdown voltage VBR are investigated in AlGaN/GaN high-electron-mobility transistors (HEMTs) with LG = 1 μm˜ 20 μm. With the increase of LG, VBR is first increased, and then saturated at LG = 3 μm. For the HEMT with LG = 1 μm, breakdown voltage VBR is 117 V, and it can be enhanced to 148 V for the HEMT with LG = 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage. A similar suppression of the impact ionization exists in the HEMTs with LG > 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with LG = 3 μm˜20 μm, and their breakdown voltages are in a range of 140 V-156 V. Project supported by the National Natural Science Foundation of China (Grant Nos. 61334002, 61106106, and 61204085).

  13. Selective nitrate detection by an enzymatic sensor based on an extended-gate type organic field-effect transistor.

    Science.gov (United States)

    Minami, Tsuyoshi; Sasaki, Yui; Minamiki, Tsukuru; Wakida, Shin-Ichi; Kurita, Ryoji; Niwa, Osamu; Tokito, Shizuo

    2016-07-15

    First selective nitrate biosensor device based on an extended-gate type organic field-effect transistor (OFET) is reported. The fabricated sensor device consists of the extended-gate electrode functionalized by a nitrate reductase with a mediator (=a bipyridinium derivative) and an OFET-based transducer. The mechanism of the nitrate detection can be explained by an electron-relay on the extended-gate electrode, resulting in changes of the electric properties of the OFET. The detection limit of nitrate in water is estimated to be 45 ppb, which suggests that the sensitivity of our fabricated sensor is comparable to those of some conventional detection methods. As a practical application of the OFET sensor, the nitrate detection in diluted human saliva has been successfully demonstrated; the results agreed well with those by conventional colorimetric measurement. The advantages of OFETs are printability, mechanical flexibility, stretchability and disposability, meaning that the fabricated OFET could open up a new approach for low-cost electronic devices toward on-site detection of nitrate in aqueous media.

  14. Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor

    Science.gov (United States)

    Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

    2017-03-01

    In this paper, analog/RF performance of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor (HJTFET) has been explored. A highly doped n+ layer is placed at the Source-Channel junction in order to improve the horizontal electric field component and thus, improve the realiability of the device. The analog performance of the device is analysed by extracting current-voltage characteristics, transcondutance (gm), gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). Further, RF performance of the device is evaluated by obtaining cut-off frequency (fT) and Gain Bandwidth (GBW) product. ION /IOFF ratio equal to ≈ 109, subthreshold slope of 27 mV/dec, maximum fT of 2.1 THz and maximum GBW of 484 GHz were achieved. Also, the impact of temperature variation on the linearity performance of the device has been investigated. Furthermore, the circuit level performance of the device is performed by implementing a Common Source (CS) amplifier; maximum gain of 31.11 dB and 3-dB cut-off frequency equal to 91.2 GHz were achieved for load resistance (RL) = 17.5 KΩ.

  15. Ferroelectric-gate field effect transistor memories device physics and applications

    CERN Document Server

    Ishiwara, Hiroshi; Okuyama, Masanori; Sakai, Shigeki; Yoon, Sung-Min

    2016-01-01

    This book provides comprehensive coverage of the materials characteristics, process technologies, and device operations for memory field-effect transistors employing inorganic or organic ferroelectric thin films. This transistor-type ferroelectric memory has interesting fundamental device physics and potentially large industrial impact. Among the various applications of ferroelectric thin films, the development of nonvolatile ferroelectric random access memory (FeRAM) has progressed most actively since the late 1980s and has achieved modest mass production levels for specific applications since 1995. There are two types of memory cells in ferroelectric nonvolatile memories. One is the capacitor-type FeRAM and the other is the field-effect transistor (FET)-type FeRAM. Although the FET-type FeRAM claims ultimate scalability and nondestructive readout characteristics, the capacitor-type FeRAMs have been the main interest for the major semiconductor memory companies, because the ferroelectric FET has fatal handic...

  16. Preparation and operation characteristics of organic semiconductor transistor using thin film Al gate and copper phthalocyanine

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    The organic static induction transistors (OSITs) are fabricated by the method of evaporating and plating in a vacuum with copper phthalocyanine (CuPc) dye, and has a five layered structure of Au/CuPc/AL/CuPc/Au. The experiment reveals that OSITs have obtained a low driving voltage, high current density and high switch speed such as IDs = 1.2 × 10-6A/mm2 , and the degree of 1 000 Hz. The OSITs have excellent operation characteristics of typical static induction transistors.

  17. Instrumentation for Gate Current Noise Measurements on sub-100 nm MOS Transistors

    CERN Document Server

    Gaioni, L; Ratti, L; Re, V; Speziali, V; Traversi, G

    2008-01-01

    This work describes a measuring system that was developed to characterize the gate current noise performances of CMOS devices with minimum feature size in the 100 nm span. These devices play an essential role in the design of present daymixedsignal integrated circuits, because of the advantages associated with the scaling process. The reduction in the gate oxide thickness brought about by CMOS technology downscaling leads to a non-negligible gate current due to direct tunneling phenomena; this current represents a noise source which requires an accurate characterization for optimum analog design. In this paper, two instruments able to perform measurements in two different ranges of gate current values will be discussed. Some of the results of gate current noise characterization will also be presented.

  18. Effects of annealing on electrical performance of multilayer MoS2 transistors with atomic layer deposited HfO2 gate dielectric

    Science.gov (United States)

    Wen, Ming; Xu, Jingping; Liu, Lu; Lai, Pui-To; Tang, Wing-Man

    2016-09-01

    Atomic layer deposited HfO2 annealed in different ambients (N2, O2, and NH3) is used to replace SiO2 as a gate dielectric for fabricating back-gated multilayer MoS2 transistors. Excellent electrical properties such as a mobility of 15.1 cm2/(V·s), an on/off ratio exceeding 107, and a hysteresis of 0.133 V are achieved for samples annealed in NH3 at 400 °C for 10 min. This is caused by the NH3 annealing passivation effects that reduce defective states in the HfO2 dielectric and the interface. The capacitance equivalent thickness is only 7.85 nm, which is quite small for a back-gated MoS2 transistor and is conducive to the scaling down of the device.

  19. Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

    KAUST Repository

    Fahad, Hossain M.

    2011-10-12

    We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

  20. Comparison of recessed gate-head structures on normally-off AlGaN/GaN high-electron-mobility transistor performance.

    Science.gov (United States)

    Khan, Mansoor Ali; Heo, Jun-Woo; Kim, Hyun-Seok; Park, Hyun-Chang

    2014-11-01

    In this work, different gate-head structures have been compared in the context of AlGaN/GaN-based high-electron-mobility transistors (HEMTs). Field-plate (FP) technology self-aligned to the gate electrode leads to various gate-head structures, most likely gamma (γF)-gate, camel (see symbol)-gate, and mushroom-shaped (T)-gate. In-depth comparison of recessed gate-head structures demonstrated that key performance metrics such as transconductance, output current, and breakdown voltage are better with the T-gate head structure. The recessed T-gate with its one arm toward the source side not only reduces the source-access resistance (R(g) +R(gs)), but also minimizes the source-side dispersion and current leakage, resulting in high transconductance (G(m)) and output current (I(DS)). At the same time, the other arm toward the drain-side reduces the drain-side dispersion and tends to distribute electric field peaks uniformly, resulting in high breakdown voltage (V(BR)). DC and RF analysis showed that the recessed T-gate FP-HEMT is a suitable candidate not only for high-frequency operation, but also for high-power applications.

  1. High Sensitivity pH Sensor Based on Porous Silicon (PSi) Extended Gate Field-Effect Transistor

    Science.gov (United States)

    Al-Hardan, Naif H.; Abdul Hamid, Muhammad Azmi; Ahmed, Naser M.; Jalar, Azman; Shamsudin, Roslinda; Othman, Norinsan Kamil; Kar Keng, Lim; Chiu, Weesiong; Al-Rawi, Hamzah N.

    2016-01-01

    In this study, porous silicon (PSi) was prepared and tested as an extended gate field-effect transistor (EGFET) for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions. PMID:27338381

  2. Compact model of ferroelectric-gate field-effect transistor for circuit simulation based on multidomain Landau–Kalathnikov theory

    Science.gov (United States)

    Asai, Hidehiro; Fukuda, Koichi; Hattori, Junichi; Koike, Hanpei; Miyata, Noriyuki; Takahashi, Mitsue; Sakai, Shigeki

    2017-04-01

    We report a new compact model for a ferroelectric-gate field-effect transistor (FeFET) considering multiple ferroelectric domain structures that can be thermally activated. The dynamics of the electric polarization and the thermal activation rate are calculated on the basis of the Landau–Khalatnikov (LK) theory. We implement this compact model in a circuit simulator, SmartSPICE, using Verilog-A language for analog circuit simulations. The device characteristics of FeFETs reported in experiments are well fitted by our compact model. We also perform the circuit simulation for the inverter utilizing FeFETs by using this compact model. Unlike normal inverters composed of MOSFETs, the switching speed of the inverter changes with the voltage pulse before the operation.

  3. Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors

    Science.gov (United States)

    Choi, Woo Young

    2017-04-01

    The effects of drain bias on the statistical variation of double-gate (DG) tunnel field-effect transistors (TFETs) are discussed in comparison with DG metal–oxide–semiconductor FETs (MOSFETs). Statistical variation corresponds to the variation of threshold voltage (V th), subthreshold swing (SS), and drain-induced barrier thinning (DIBT). The unique statistical variation characteristics of DG TFETs and DG MOSFETs with the variation of drain bias are analyzed by using full three-dimensional technology computer-aided design (TCAD) simulation in terms of the three dominant variation sources: line-edge roughness (LER), random dopant fluctuation (RDF) and workfunction variation (WFV). It is observed than DG TFETs suffer from less severe statistical variation as drain voltage increases unlike DG MOSFETs.

  4. High Sensitivity pH Sensor Based on Porous Silicon (PSi Extended Gate Field-Effect Transistor

    Directory of Open Access Journals (Sweden)

    Naif H. Al-Hardan

    2016-06-01

    Full Text Available In this study, porous silicon (PSi was prepared and tested as an extended gate field-effect transistor (EGFET for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

  5. High temperature performance of Si:HfO2 based long channel Double Gate Ferroelectric Junctionless Transistors

    Science.gov (United States)

    Mehta, Hema; Kaur, Harsupreet

    2017-03-01

    In this work, we present a study that explores the suitability of Double Gate Ferroelectric Junctionless Transistor (DGFJL) incorporating Si:HfO2 for high temperature applications. At present, very few studies are focussed on Si:HfO2 to investigate its integrability in the present CMOS design space. Therefore, in the present study, using analytical modeling and TCAD simulations, it is demonstrated that Si:HfO2 based DGFJL exhibits superior performance in terms of substantial gain, reduced leakage currents, improved current drivability and high Ion/Ioff ratio at elevated temperatures as compared to the DGJL counterpart. The study, thus, highlights the fact that DGFJL is a potential candidate for device applications at high temperatures.

  6. A top-gate GaN nanowire metal-semiconductor field effect transistor with improved channel electrostatic control

    Science.gov (United States)

    Gačević, Ž.; López-Romero, D.; Juan Mangas, T.; Calleja, E.

    2016-01-01

    A uniformly n-type doped GaN:Si nanowire (NW), with a diameter of d = 90 nm and a length of 1.2 μm, is processed into a metal-semiconductor field effect transistor (MESFET) with a semi-cylindrical top Ti/Au Schottky gate. The FET is in a normally-ON mode, with the threshold at -0.7 V and transconductance of gm ˜ 2 μS (the transconductance normalized with NW diameter gm/d > 22 mS/mm). It enters the saturation mode at VDS ˜ 4.5 V, with the maximum measured drain current IDS = 5.0 μA and the current density exceeding JDS > 78 kA/cm2.

  7. Studies on the reliability of ni-gate aluminum gallium nitride / gallium nitride high electron mobility transistors using chemical deprocessing

    Science.gov (United States)

    Whiting, Patrick Guzek

    Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors are becoming the technology of choice for applications where hundreds of volts need to be applied in a circuit at frequencies in the hundreds of gigahertz, such as microwave communications. However, because these devices are very new, their reliability in the field is not well understood, partly because of the stochastic nature of the defects which form as a result of their operation. Many analytical techniques are not well suited to the analysis of these defects because they sample regions of the device which are either too small or too large for accurate observation. The use of chemical deprocessing in addition to surface-sensitive analysis techniques such as Scanning Electron Microscopy and Scanning Probe Microscopy can be utilized in the analysis of defect formation in devices formed with nickel gates. Hydrofluoric acid is used to etch the passivation nitride which covers the semiconducting layer of the transistor. A metal etch utilizing FeCN/KI is used to etch the ohmic and gate contacts of the device and a long exposure in various solvent solutions is used to remove organic contaminants, exposing the surface of the semiconducting layer for analysis. Deprocessing was used in conjunction with a variety of metrology techniques to analyze three different defects. One of these defects is a nanoscale crack which emanates from metal inclusions formed during alloying of the ohmic contacts of the device prior to use in the field, could impact the yield of production-level manufacturing of these devices. This defect also appears to grow, in some cases, during electrostatic stressing. Another defect, a native oxide at the surface of the semiconducting layer which appears to react in the presence of an electric field, has not been observed before during post-mortem analysis of degraded devices. It could play a major part in the degredation of the gate contact during high-field, off

  8. Flexible SiInZnO thin film transistor with organic/inorganic hybrid gate dielectric processed at 150 °C

    Science.gov (United States)

    Choi, J. Y.; Kim, S.; Hwang, B.-U.; Lee, N.-E.; Lee, S. Y.

    2016-12-01

    Silicon indium zinc oxide (SIZO) thin film transistors (TFTs) have been fabricated on a flexible polyimide (PI) substrate by using organic/inorganic hybrid gate dielectrics of poly-4vinyl phenol (PVP) and Al2O3. To improve the mechanical stability, Al2O3 has been used as a buffer layer on the flexible substrate. The Al2O3 layer of hybrid gate dielectrics protected the organic gate dielectric and improved mechanical flexibility. The different surface roughness of the gate dielectrics is investigated. The performance of the device with smooth surface roughness was significantly improved. Finally, the electrical characteristics of the TFTs with hybrid gate dielectrics were measured as well as the promising electrical endurance characteristics at the bending radius of 5 mm.

  9. Controllability of self-aligned four-terminal planar embedded metal double-gate low-temperature polycrystalline-silicon thin-film transistors on a glass substrate

    Science.gov (United States)

    Ohsawa, Hiroki; Sasaki, Shun; Hara, Akito

    2016-03-01

    Self-aligned four-terminal n-channel (n-ch) and p-channel (p-ch) planar embedded metal double-gate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature of 550 °C. This device includes a metal top gate (TG) and a metal bottom gate (BG), which are used as the drive and control gates or vice versa. The BG was embedded in a glass substrate, and a poly-Si channel with large lateral grains was fabricated by continuous-wave laser lateral crystallization. The threshold voltage modulation factors under various control gate voltages (γ = ΔVth/ΔVCG) were nearly equal to the theoretical predictions in both the n- and p-ch TFTs. By exploiting this high controllability, an enhancement depletion (ED) inverter was fabricated, and successful operation at 2.0 V was confirmed.

  10. Extended-gate field-effect transistor (EG-FET) with molecularly imprinted polymer (MIP) film for selective inosine determination.

    Science.gov (United States)

    Iskierko, Zofia; Sosnowska, Marta; Sharma, Piyush Sindhu; Benincori, Tiziana; D'Souza, Francis; Kaminska, Izabela; Fronc, Krzysztof; Noworyta, Krzysztof

    2015-12-15

    A novel recognition unit of chemical sensor for selective determination of the inosine, renal disfunction biomarker, was devised and prepared. For that purpose, inosine-templated molecularly imprinted polymer (MIP) film was deposited on an extended-gate field-effect transistor (EG-FET) signal transducing unit. The MIP film was prepared by electrochemical polymerization of bis(bithiophene) derivatives bearing cytosine and boronic acid substituents, in the presence of the inosine template and a thiophene cross-linker. After MIP film deposition, the template was removed, and was confirmed by UV-visible spectroscopy. Subsequently, the film composition was characterized by spectroscopic techniques, and its morphology and thickness were determined by AFM. The finally MIP film-coated extended-gate field-effect transistor (EG-FET) was used for signal transduction. This combination is not widely studied in the literature, despite the fact that it allows for facile integration of electrodeposited MIP film with FET transducer. The linear dynamic concentration range of the chemosensor was 0.5-50 μM with inosine detectability of 0.62 μM. The obtained detectability compares well to the levels of the inosine in body fluids which are in the range 0-2.9 µM for patients with diagnosed diabetic nephropathy, gout or hyperuricemia, and can reach 25 µM in certain cases. The imprinting factor for inosine, determined from piezomicrogravimetric experiments with use of the MIP film-coated quartz crystal resonator, was found to be 5.5. Higher selectivity for inosine with respect to common interferents was also achieved with the present molecularly engineered sensing element. The obtained analytical parameters of the devised chemosensor allow for its use for practical sample measurements.

  11. Self-aligned top-gate amorphous indium zinc oxide thin-film transistors exceeding low-temperature poly-Si transistor performance.

    Science.gov (United States)

    Park, Jae Chul; Lee, Ho-Nyeon; Im, Seongil

    2013-08-14

    Thin-film transistor (TFT) is a key component of active-matrix flat-panel displays (AMFPDs). These days, the low-temperature poly silicon (LTPS) TFTs are to match with advanced AMFPDs such as the active matrix organic light-emitting diode (AMOLED) display, because of their high mobility for fast pixel switching. However, the manufacturing process of LTPS TFT is quite complicated, costly, and scale-limited. Amorphous oxide semiconductor (AOS) TFT technology is another candidate, which is as simple as that of conventioanl amorphous (a)-Si TFTs in fabrication but provides much superior device performances to those of a-Si TFTs. Hence, various AOSs have been compared with LTPS for active channel layer of the advanced TFTs, but have always been found to be relatively inferior to LTPS. In the present work, we clear the persistent inferiority, innovating the device performaces of a-IZO TFT by adopting a self-aligned coplanar top-gate structure and modifying the surface of a-IZO material. Herein, we demonstrate a high-performance simple-processed a-IZO TFT with mobility of ∼157 cm(2) V(-1) s(-1), SS of ∼190 mV dec(-1), and good bias/photostabilities, which overall surpass the performances of high-cost LTPS TFTs.

  12. Improved gate oxide integrity of strained Si n-channel metal oxide silicon field effect transistors using thin virtual substrates

    Science.gov (United States)

    Yan, L.; Olsen, S. H.; Escobedo-Cousin, E.; O'Neill, A. G.

    2008-05-01

    This work presents a detailed study of ultrathin gate oxide integrity in strained Si metal oxide silicon field effect transistors (MOSFETs) fabricated on thin virtual substrates aimed at reducing device self-heating. The gate oxide quality and reliability of the devices are compared to those of simultaneously processed Si control devices and conventional thick virtual substrate devices that have the same Ge content (20%), strained Si channel thickness, and channel strain. The thin virtual substrates offer the same mobility enhancement as the thick virtual substrates (˜100% compared to universal mobility data) and are effective at reducing device self-heating. Up to 90% improvement in gate leakage current is demonstrated for the strained Si n-channel MOSFETs compared to that for the bulk Si controls. The lower leakage arises from the increased electron affinity in tensile strained Si and is significant due to the sizeable strain generated by using wafer-level stressors. The strain-induced leakage reductions also lead to major improvements in stress-induced leakage current (SILC) and oxide reliability. The lower leakage current of the thin and thick virtual substrate devices compares well to theoretical estimates based on the Wentzel-Kramers-Brillouin approximation. Breakdown characteristics also differ considerably between the devices, with the strained Si devices exhibiting a one order of magnitude increase in time to hard breakdown (THBD) compared to the Si control devices following high-field stressing at 17 MV cm-1. The strained Si devices are exempted from soft breakdown. Experimental based analytical leakage modeling has been carried out across the field range for the first time in thin oxides and demonstrates that Poole-Frenkel (PF) emissions followed by Fowler-Nordheim tunneling dominate gate leakage current at low fields in all of the devices. This contrasts to the frequently reported assumption that direct tunneling dominates gate leakage in ultrathin

  13. Compact analytical model for single gate AlInSb/InSb high electron mobility transistors

    Institute of Scientific and Technical Information of China (English)

    S.Theodore Chandra; N.B.Balamurugan; G.Subalakshmi; T.Shalini; G.Lakshmi Priya

    2014-01-01

    We have developed a 2D analytical model for the single gate AlInSb/InSb HEMT device by solving the Poisson equation using the parabolic approximation method.The developed model analyses the device performance by calculating the parameters such as surface potential,electric field distribution and drain current.The high mobility of the AlInSb/InSb quantum makes this HEMT ideal for high frequency,high power applications.The working of the single gate AlInSb/InSb HEMT device is studied by considering the variation of gate source voltage,drain source voltage,and channel length under the gate region and temperature.The carrier transport efficiency is improved by uniform electric field along the channel and the peak values near the source and drain regions.The results from the analytical model are compared with that of numerical simulations (TCAD) and a good agreement between them is achieved.

  14. Aerosol jet printed p- and n-type electrolyte-gated transistors with a variety of electrode materials: exploring practical routes to printed electronics.

    Science.gov (United States)

    Hong, Kihyon; Kim, Se Hyun; Mahajan, Ankit; Frisbie, C Daniel

    2014-11-12

    Printing electrically functional liquid inks is a promising approach for achieving low-cost, large-area, additive manufacturing of flexible electronic circuits. To print thin-film transistors, a basic building block of thin-film electronics, it is important to have several options for printable electrode materials that exhibit high conductivity, high stability, and low-cost. Here we report completely aerosol jet printed (AJP) p- and n-type electrolyte-gated transistors (EGTs) using a variety of different electrode materials including highly conductive metal nanoparticles (Ag), conducting polymers (polystyrenesulfonate doped poly(3,4-ethylendedioxythiophene, PEDOT:PSS), transparent conducting oxides (indium tin oxide), and carbon-based materials (reduced graphene oxide). Using these source-drain electrode materials and a PEDOT:PSS/ion gel gate stack, we demonstrated all-printed p- and n-type EGTs in combination with poly(3-hexythiophene) and ZnO semiconductors. All transistor components (including electrodes, semiconductors, and gate insulators) were printed by AJP. Both kinds of devices showed typical p- and n-type transistor characteristics, and exhibited both low-threshold voltages (<2 V) and high hole and electron mobilities. Our assessment suggests Ag electrodes may be the best option in terms of overall performance for both types of EGTs.

  15. Graphene quantum dots as a highly efficient solution-processed charge trapping medium for organic nano-floating gate memory.

    Science.gov (United States)

    Ji, Yongsung; Kim, Juhan; Cha, An-Na; Lee, Sang-A; Lee, Myung Woo; Suh, Jung Sang; Bae, Sukang; Moon, Byung Joon; Lee, Sang Hyun; Lee, Dong Su; Wang, Gunuk; Kim, Tae-Wook

    2016-04-08

    A highly efficient solution-processible charge trapping medium is a prerequisite to developing high-performance organic nano-floating gate memory (NFGM) devices. Although several candidates for the charge trapping layer have been proposed for organic memory, a method for significantly increasing the density of stored charges in nanoscale layers remains a considerable challenge. Here, solution-processible graphene quantum dots (GQDs) were prepared by a modified thermal plasma jet method; the GQDs were mostly composed of carbon without any serious oxidation, which was confirmed by x-ray photoelectron spectroscopy. These GQDs have multiple energy levels because of their size distribution, and they can be effectively utilized as charge trapping media for organic NFGM applications. The NFGM device exhibited excellent reversible switching characteristics, with an on/off current ratio greater than 10(6), a stable retention time of 10(4) s and reliable cycling endurance over 100 cycles. In particular, we estimated that the GQDs layer trapped ∼7.2 × 10(12) cm(-2) charges per unit area, which is a much higher density than those of other solution-processible nanomaterials, suggesting that the GQDs layer holds promise as a highly efficient nanoscale charge trapping material.

  16. Iridium oxides based gate interface of AlGaN/GaN high electron mobility transistors formed by high temperature oxidation

    Energy Technology Data Exchange (ETDEWEB)

    Lalinský, T. [Institute of Electrical Engineering of the Slovak Academy of Sciences, Dúbravská cesta 9, 841 04 Bratislava (Slovakia); Vallo, M., E-mail: martin.vallo@savba.sk [Institute of Electrical Engineering of the Slovak Academy of Sciences, Dúbravská cesta 9, 841 04 Bratislava (Slovakia); Vanko, G.; Dobročka, E. [Institute of Electrical Engineering of the Slovak Academy of Sciences, Dúbravská cesta 9, 841 04 Bratislava (Slovakia); Vincze, A. [International Laser Centre, Ilkovičova 3, 841 04 Bratislava (Slovakia); Osvald, J.; Rýger, I.; Dzuba, J. [Institute of Electrical Engineering of the Slovak Academy of Sciences, Dúbravská cesta 9, 841 04 Bratislava (Slovakia)

    2013-10-15

    We report on a high temperature forming of iridium oxides (IrO{sub 2}) gates of circular AlGaN/GaN high electron mobility transistors (C-HEMTs) to be predetermined for high temperature applications. IrO{sub 2} gate interfacial layer is formed by high temperature oxidation (T = 500–800 °C, for 1 min) of 15 nm thick Ir gate contact layer. A comprehensive microstructural and electrical characterization of the IrO{sub 2} gates is carried out to explain the improved transport properties and thermal stability of the gate interfaces. It is found that the transformation of Ir gate layer into its crystalline IrO{sub 2} phase at oxidation temperatures of 700 °C and 800 °C provides the high barrier gate interface with prevailing thermionic emission transport mechanism. Accelerated reliability tests are used to confirm C-HEMT thermally stable performance deduced from both the gate interface and 2DEG channel stability. The introduced AlGaN/GaN C-HEMTs with high temperature grown IrO{sub 2} gates seem to be very attractive for both the high temperature operated electronic and sensor devices.

  17. Study the Characteristic of P-Type Junction-Less Side Gate Silicon Nanowire Transistor Fabricated by Atomic Force Microscopy Lithography

    Directory of Open Access Journals (Sweden)

    Arash Dehzangi

    2011-01-01

    Full Text Available Problem statement: Nanotransistor now is one of the most promising fields in nanoelectronics in order to decrease the energy consuming and application to create developed programmable information processors. Most of Computing and communications companies invest hundreds of millions of dollars in research funds every year to develop smaller transistors. Approach: The Junction-less side gate silicon Nano-wire transistor has been fabricated by Atomic Force Microscopy (AFM and wet etching on p-type Silicon On Insulator (SOI wafer. Then, we checked the characteristic and conductance trend in this device regarding to semi-classical approach by Semiconductor Probe Analyser (SPA. Results: We observed in characteristic of the device directly proportionality of the negative gate voltage and Source-Drain current. In semi classical approach, negative Gate voltage decreased the energy States of the Nano-wire between the source and the drain. The graph for positive gate voltage plotted as well to check. In other hand, the conductance will be following characteristic due to varying the gate voltage under the different drain-source voltage. Conclusion: The channel energy states are supposed to locate between two electrochemical potentials of the contacts in order to transform the charge. For the p-type channel the transform of the carriers is located in valence band and changing the positive or negative gate voltage, making the valence band energy states out of or in the area between the electrochemical potentials of the contacts causing the current reduced or increased.

  18. Direct Electrical Detection of DNA Hybridization Based on Electrolyte-Gated Graphene Field-Effect Transistor

    Science.gov (United States)

    Ohno, Yasuhide; Okamoto, Shogo; Maehashi, Kenzo; Matsumoto, Kazuhiko

    2013-11-01

    DNA hybridization was electrically detected by graphene field-effect transistors. Probe DNA was modified on the graphene channel by a pyrene-based linker material. The transfer characteristic was shifted by the negative charges on the probe DNA, and the drain current was changed by the full-complementary DNA while no current change was observed after adding noncomplementary DNA, indicating that the graphene field-effect transistor detected the DNA hybridization. In addition, the number of DNAs was estimated by the simple plate capacitor model. As a result, one probe DNA was attached on the graphene channel per 10×10 nm2, indicating their high density functionalization. We estimated that 30% of probe DNA on the graphene channel was hybridized with 200 nM full-complementary DNA while only 5% of probe DNA was bound to the noncomplementary DNA. These results will help to pave the way for future biosensing applications based on graphene FETs.

  19. Photodetection in p–n junctions formed by electrolyte-gated transistors of two-dimensional crystals

    KAUST Repository

    Kozawa, Daichi

    2016-11-16

    Transition metal dichalcogenide monolayers have attracted much attention due to their strong light absorption and excellent electronic properties. These advantages make this type of two-dimensional crystal a promising one for optoelectronic device applications. In the case of photoelectric conversion devices such as photodetectors and photovoltaic cells, p–n junctions are one of the most important devices. Here, we demonstrate photodetection with WSe2 monolayer films. We prepare the electrolyte-gated ambipolar transistors and electrostatic p–n junctions are formed by the electrolyte-gating technique at 270 K. These p-n junctions are cooled down to fix the ion motion (and p-n junctions) and we observed the reasonable photocurrent spectra without the external bias, indicating the formation of p-n junctions. Very interestingly, two-terminal devices exhibit higher photoresponsivity than that of three-terminal ones, suggesting the formation of highly balanced anion and cation layers. The maximum photoresponsivity reaches 5 mA/W in resonance with the first excitonic peak. Our technique provides important evidence for optoelectronics in atomically thin crystals.

  20. Microscopic signature of insulator-to-metal transition in highly doped semicrystalline conducting polymers in ionic-liquid-gated transistors

    Energy Technology Data Exchange (ETDEWEB)

    Tanaka, Hisaaki, E-mail: htanaka@nuap.nagoya-u.ac.jp; Nishio, Satoshi; Ito, Hiroshi; Kuroda, Shin-ichi [Department of Applied Physics, Nagoya University, Chikusa, Nagoya 464-8603 (Japan)

    2015-12-14

    Electronic state of charge carriers, in particular, in highly doped regions, in thin-film transistors of a semicrystalline conducting polymer poly(2,5-bis(3-alkylthiophene-2-yl)thieno[3,2-b]thiophene), has been studied by using field-induced electron spin resonance (ESR) spectroscopy. By adopting an ionic-liquid gate insulator, a gate-controlled reversible electrochemical hole-doping of the polymer backbone is achieved, as confirmed from the change of the optical absorption spectra. The edge-on molecular orientation in the pristine film is maintained even after the electrochemical doping, which is clarified from the angular dependence of the g value. As the doping level increases, spin 1/2 polarons transform into spinless bipolarons, which is demonstrated from the spin-charge relation showing a spin concentration peak around 1%, contrasting to the monotonic increase in the charge concentration. At high doping levels, a drastic change in the linewidth anisotropy due to the generation of conduction electrons is observed, indicating the onset of metallic state, which is also supported by the temperature dependence of the spin susceptibility and the ESR linewidth. Our results suggest that semicrystalline conducting polymers become metallic with retaining their molecular orientational order, when appropriate doping methods are chosen.

  1. pH sensing characteristics and biosensing application of solution-gated reduced graphene oxide field-effect transistors.

    Science.gov (United States)

    Sohn, Il-Yung; Kim, Duck-Jin; Jung, Jin-Heak; Yoon, Ok Ja; Thanh, Tien Nguyen; Quang, Trung Tran; Lee, Nae-Eung

    2013-07-15

    Solution-gated reduced graphene oxide field-effect transistors (R-GO FETs) were investigated for pH sensing and biochemical sensing applications. A channel of a networked R-GO film formed by self-assembly was incorporated as a sensing layer into a solution-gated FET structure for pH sensing and the detection of acetylcholine (Ach), which is a neurotransmitter in the nerve system, through enzymatic reactions. The fabricated R-GO FET was sensitive to protons (H(+)) with a pH sensitivity of 29 mV/pH in terms of the shift of the charge neutrality point (CNP), which is attributed to changes in the surface potential caused by the interaction of protons with OH surface functional groups present on the R-GO surface. The R-GO FET immobilized with acetylcholinesterase (AchE) was used to detect Ach in the concentration range of 0.1-10mM by sensing protons generated during the enzymatic reactions. The results indicate that R-GO FETs provide the capability to detect protons, demonstrating their applicability as a biosensing device for enzymatic reactions.

  2. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S. [Department of Electrical and Computer Engineering, University of Waterloo, 200 University Avenue West, Waterloo, Ontario N2L 3G1 (Canada)

    2015-07-13

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  3. Frequency kesponse of top-gated carbon nanotube field-effect transistors

    OpenAIRE

    Singh, Dinkar V.; Jenkins, Keith A.; Appenzeller, Joerg; Neumayer, D.; Grill, Alfred; Wong, H. S. Philip

    2004-01-01

    The ac performance of carbon nanotube field-effect transistors (CNFETs) has been characterized using two approaches involving: 1) time- and 2) frequency-domain measurements. A high input impedance measurement system was used to demonstrate time-domain switching of CNFETs at frequencies up to 100 kHz. The low level of signal crosstalk in CNFETs fabricated on quartz substrates enabled frequency-domain measurements of the ac response of CNFETs in the megahertz range, over five orders of magnitud...

  4. Sensing with Advanced Computing Technology: Fin Field-Effect Transistors with High-k Gate Stack on Bulk Silicon.

    Science.gov (United States)

    Rigante, Sara; Scarbolo, Paolo; Wipf, Mathias; Stoop, Ralph L; Bedner, Kristine; Buitrago, Elizabeth; Bazigos, Antonios; Bouvet, Didier; Calame, Michel; Schönenberger, Christian; Ionescu, Adrian M

    2015-05-26

    Field-effect transistors (FETs) form an established technology for sensing applications. However, recent advancements and use of high-performance multigate metal-oxide semiconductor FETs (double-gate, FinFET, trigate, gate-all-around) in computing technology, instead of bulk MOSFETs, raise new opportunities and questions about the most suitable device architectures for sensing integrated circuits. In this work, we propose pH and ion sensors exploiting FinFETs fabricated on bulk silicon by a fully CMOS compatible approach, as an alternative to the widely investigated silicon nanowires on silicon-on-insulator substrates. We also provide an analytical insight of the concept of sensitivity for the electronic integration of sensors. N-channel fully depleted FinFETs with critical dimensions on the order of 20 nm and HfO2 as a high-k gate insulator have been developed and characterized, showing excellent electrical properties, subthreshold swing, SS ∼ 70 mV/dec, and on-to-off current ratio, Ion/Ioff ∼ 10(6), at room temperature. The same FinFET architecture is validated as a highly sensitive, stable, and reproducible pH sensor. An intrinsic sensitivity close to the Nernst limit, S = 57 mV/pH, is achieved. The pH response in terms of output current reaches Sout = 60%. Long-term measurements have been performed over 4.5 days with a resulting drift in time δVth/δt = 0.10 mV/h. Finally, we show the capability to reproduce experimental data with an extended three-dimensional commercial finite element analysis simulator, in both dry and wet environments, which is useful for future advanced sensor design and optimization.

  5. A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS

    Directory of Open Access Journals (Sweden)

    Nabihah Ahmad

    2013-01-01

    Full Text Available A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.

  6. Organic Thin Film Field Effect Transistors with PMMA-GMA Gate Dielectric

    Institute of Scientific and Technical Information of China (English)

    JIANG Wen-Hai; DU Guo-Tong; YU Shu-Kun; WANG Wei; CHANG Yu-Chun; WANG Xu

    2006-01-01

    @@ We fabricate organic thin films using the copolymer of methyl methacrylate and glycidyl methacrylate (PMMA-GMA) as a gate dielectric with a simple top-contact structure. Copper phthalocyanine (CuPc) TFTs are fabricated and the influences of annealing on the performance are studied. The mobilities increase from 2.5 ×103 cm2/Vs to 4.2 × 103 cm2/Vs and threshold voltages decrease from -18 V to -10 V after annealing. The good performances of the devices approach those obtained with inorganic gate dielectric materials such as silicon dioxide under the same technical conditions. It is fully proven that PMMA-GMA is a competitive candidate as an excellent gate insulation layer.

  7. Transparent multi-level-cell nonvolatile memory with dual-gate amorphous indium-gallium-zinc oxide thin-film transistors

    Science.gov (United States)

    Ahn, Min-Ju; Cho, Won-Ju

    2016-12-01

    A fully transparent, nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a dual gate (DG) structure for a multi-level-cell (MLC) application. A large memory window was obtained at a low program voltage in the DG read-operation mode owing to the capacitive-coupling effect between the front gate and the back gate. The MLC was implemented by using the DG read-operation mode with four highly stable levels, as follows: A large threshold-voltage difference >3.5 V per level was obtained under a low program voltage <14 V with a fast program speed of 1 ms. In contrast, the conventional single gate operation mode was incompatible with the MLC application.

  8. Investigation of gate-diode degradation in normally-off p-GaN/AlGaN/GaN high-electron-mobility transistors

    Science.gov (United States)

    Tapajna, M.; Hilt, O.; Bahat-Treidel, E.; Würfl, J.; Kuzmík, J.

    2015-11-01

    Gate diode conduction mechanisms were analyzed in normally-off p-GaN/AlGaN/GaN high-electron mobility transistors grown on Si wafers before and after forward bias stresses. Electrical characterization of the gate diodes indicates forward current to be limited by channel electrons injected through the AlGaN/p-GaN triangular barrier promoted by traps. On the other hand, reverse current was found to be consistent with carrier generation-recombination processes in the AlGaN layer. Soft breakdown observed after ˜105 s during forward bias stress at gate voltage of 7 V was attributed to formation of conductive channel in p-GaN/AlGaN gate stack via trap generation and percolation mechanism, likely due to coexistence of high electric field and high forward current density. Possible enhancement of localized conductive channels originating from spatial inhomogeneities is proposed to be responsible for the degradation.

  9. Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

    Science.gov (United States)

    Liuan, Li; Jiaqi, Zhang; Yang, Liu; Jin-Ping, Ao

    2016-03-01

    In this paper, TiN/AlOx gated AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 °C with the contact resistance approximately 1.6 Ω·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlOx gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AlGaN/GaN MOS-HFETs. Project supported by the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260).

  10. Normally-off AlGaN/GaN high-electron-mobility transistor on Si(111) by recessed gate and fluorine plasma treatment

    Science.gov (United States)

    Lin, Jyun-Hao; Huang, Shyh-Jer; Lai, Chao-Hsing; Su, Yan-Kuin

    2016-01-01

    We have studied the efficiency of using both recessed gate and fluorine plasma treatment to achieve normally-off high-electron-mobility transistor (HEMT). It is found that, by a simple recess process, one cannot achieve normally off device with high drain current because of gate leakage problem after inductively coupled plasma (ICP) etching for recessed structure. The proper method is adding fluorine treatment based on recess gate. The normally off GaN HEMTs with recess gate and fluorine treatment show very good performance. It is found that the threshold voltages can be shifted to +1.1 V, and the drain current at VGS - Vth = 2 V and VDS = 20 V was 218 mA/mm.

  11. Detangling extrinsic and intrinsic hysteresis for detecting dynamic switch of electric dipoles using graphene field-effect transistors on ferroelectric gates.

    Science.gov (United States)

    Ma, Chunrui; Gong, Youpin; Lu, Rongtao; Brown, Emery; Ma, Beihai; Li, Jun; Wu, Judy

    2015-11-28

    A transition in source-drain current vs. back gate voltage (ID-VBG) characteristics from extrinsic polar molecule dominant hysteresis to anti-hysteresis induced by an oxygen deficient surface layer that is intrinsic to the ferroelectric thin films has been observed on graphene field-effect transistors on Pb0.92La0.08Zr0.52Ti0.48O3 gates (GFET/PLZT-Gate) during a vacuum annealing process developed to systematically remove the polar molecules adsorbed on the GFET channel surface. This allows the extrinsic and intrinsic hysteresis on GFET/PLZT-gate devices to detangle and the detection of the dynamic switch of electric dipoles using GFETs, taking advantage of their high gating efficiency on ferroelectric gate. A model of the charge trapping and pinning mechanism is proposed to successfully explain the transition. In response to pulsed VBG trains of positive, negative, as well as alternating polarities, respectively, the source-drain current ID variation is instantaneous with the response amplitude following the ID-VBG loops measured by DC VBG with consideration of the remnant polarization after a given VBG pulse when the gate electric field exceeds the coercive field of the PLZT. A detection sensitivity of around 212 dipole per μm(2) has been demonstrated at room temperature, suggesting the GFET/ferroelectric-gate devices provide a promising high-sensitivity scheme for uncooled detection of electrical dipole dynamic switch.

  12. Silicon-on-insulator-based high-voltage, high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Tolbert, Leon M [ORNL; Huque, Mohammad A [ORNL; Blalock, Benjamin J [ORNL; Islam, Syed K [ORNL

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  13. Intermodulation Linearity in High-k/Metal Gate 28 nm RF CMOS Transistors

    Directory of Open Access Journals (Sweden)

    Zhen Li

    2015-09-01

    Full Text Available This paper presents experimental characterization, simulation, and Volterra series based analysis of intermodulation linearity on a high-k/metal gate 28 nm RF CMOS technology. A figure-of-merit is proposed to account for both VGS and VDS nonlinearity, and extracted from frequency dependence of measured IIP3. Implications to biasing current and voltage optimization for linearity are discussed.

  14. The Bipolar Field-Effect Transistor:Ⅶ. The Unipolar Current Mode for Analog-RF Operation(Two-MOS-Gates on Pure-Base

    Institute of Scientific and Technical Information of China (English)

    Jie Binbin; Sah Chih-Tang

    2009-01-01

    This paper reports the DC steady-state current-voltage and conductance-voltage characteristics of a Bipolar Field-Effect Transistor (BiFET) under the unipolar (electron) current mode of operation, with bipolar (elec-tron and hole) charge distributions considered. The model BiFET example presented has two MOS-gates on the two surfaces of a thin pure silicon base layer with electron and hole contacts on both edges of the thin base. The hole contacts on both edges of the thin pure base layer are grounded to give zero hole current. This 1-transistor analog-RF Basic Building Block nMOS amplifier circuit, operated in the unipolar current mode, complements the 1-transistor digital Basic Build Block CMOS voltage inverter circuit, operated in the bipolar-current mode just presented by us.

  15. High Electron Mobility Ge n-Channel Metal-Insulator-Semiconductor Field-Effect Transistors Fabricated by the Gate-Last Process with the Solid Source Diffusion Technique

    Science.gov (United States)

    Maeda, Tatsuro; Morita, Yukinori; Takagi, Shinichi

    2010-06-01

    We fabricate high-k/Ge n-channel metal-insulator-semiconductor field-effect transistors (MISFETs) by the gate-last process with the thermal solid source diffusion to achieve both of high quality source/drain (S/D) and gate stack. The n+/p junction formed by solid source diffusion technique of Sb dopant shows the excellent diode characteristics of ˜1.5×105 on/off ratio between +1 and -1 V and the quite low reverse current density of ˜4.1×10-4 A/cm2 at +1 V after the fabrication of high-k/Ge n-channel MISFETs that enable us to observe well-behaved transistor performances. The extracted electron mobility with the peak of 891 cm2/(V.s) is high enough to be superior to the Si universal electron mobility especially in low Eeff.

  16. Amorphous Strontium Titanate Film as Gate Dielectric for Higher Performance and Low Voltage Operation of Transparent and Flexible Organic Field Effect Transistor.

    Science.gov (United States)

    Yadav, Sarita; Ghosh, Subhasis

    2016-04-27

    We report that the pervoskite material, strontium titanate (STO) can be used as a gate dielectric layer of flexible and low voltage organic field effect transistor (OFET). The crystallinity, dielectric constant, and surface morphology of STO films can be controlled by the engineering of the growth condition. Under optimized growth condition, amorphous films of STO show a much better gate dielectric compared to other gate dielectrics used to date, with very small leakage current density for flexible and low voltage (transistors with amorphous STO gate dielectric show high mobility of 2 cm(2)/(V s), on/off ratio of 10(6), subthreshold swing of 0.3 V/dec and low interface trap density. Similarly excellent performance has been obtained in copper phthalocyanine (CuPc) based OFETs with on/off ratio ∼10(5) and carrier mobility ∼5.9 × 10(-2) cm(2)/(V s). Moreover, the operating voltage (∼5 V) has been reduced by more than one order of magnitude. It has been demonstrated that the low processing temperature of amorphous STO makes it the most suitable gate dielectric for flexible and transparent organic devices to operate under low voltage.

  17. Metal-Semiconductor Field-Effect Transistors Fabricated Using DVT Grown n-MoSe2 Crystals With Cu-Schottky Gates

    Directory of Open Access Journals (Sweden)

    C.K. Sumesh

    2011-01-01

    Full Text Available Metal-semiconductor field-effect transistors (MESFETs based on DVT grown MoSe2 crystals and Cu Schottky gate have been fabricated and studied. When Schottky gate voltage (Vgs changes from 0 to 10 V, the source-drain current (Ids increases exponentially with Vgs and the conductance shows a drastic increase with positive Vgs. The fabricated n-MoSe2 MESFET have a saturated current level of about 100 mA and maximum transconductance of about 53 mA/V. Their results suggest a way of fabricating MESFETs from layered metal dichalcogenide semiconducting materials.

  18. Low-operating-voltage polymer thin-film transistors based on poly(3-hexylthiophene) with hafnium oxide as the gate dielectric

    OpenAIRE

    Liu, YR; Deng, LF; Yao, RH; Lai, PT

    2010-01-01

    The effects of hafnium oxide $(hbox{HfO}-{2})$ gate dielectric annealing treatment in oxygen $(hbox{O}-{2})$ and ammonia $(hbox{NH}-{3})$ ambient on the electrical performance of polymer thin-film transistors (PTFTs) based on poly(3-hexylthiophene) are investigated. The PTFTs with $hbox{HfO}-{2}$ gate dielectric and also octadecyltrichlorosilane surface modification, prepared by spin-coating process, exhibit good performance, such as a small threshold voltage of $-$0.5 V and an operating volt...

  19. Poly(4-vinylphenol gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

    Directory of Open Access Journals (Sweden)

    Ching-Lin Fan

    2016-03-01

    Full Text Available A Microwave-Induction Heating (MIH scheme is proposed for the poly(4-vinylphenol (PVP gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

  20. Laser printed organic semiconductor PQT-12 for bottom-gate organic thin-film transistors: Fabrication and characterization

    Science.gov (United States)

    Makrygianni, M.; Ainsebaa, A.; Nagel, M.; Sanaur, S.; Raptis, Y. S.; Zergioti, I.; Tsamakis, D.

    2016-12-01

    In this work, we report on the effect of laser printed Poly (3,3‴-didodecyl quarter thiophene) on its optical, structural and electrical properties for bottom-gate/bottom-contact organic thin-film transistors applications. This semiconducting π-conjugated polymer was solution-deposited (spin-coated) on a donor substrate and transferred by means of solid phase laser-induced forward transfer (LIFT) technique on SiO2/Si receiver substrates to form the active material. This article presents a detailed study of the electrical properties of the fabricated transistors by measuring the parasitic resistances for gold (Au) and platinum (Pt) as source-drain electrodes, for optimizing OTFTs in terms of contacts. In addition, X-ray diffraction patterns revealed that it is possible to control the polymer microstructure through the choice of solvent. Also, no significant change in polymer chain orientation was observed between two printed patterns at 90 and 130 mJ/cm2 as confirmed by Raman spectra. The results demonstrate hole mobility values of (2.6 ± 1.3) × 10-2 cm2/Vs, and lower parasitic resistance for dielectric surface roughness around 1.2 nm and Pt electrodes. Higher performances are correlated to i) the well-ordering of PQT-12 surface when a high-boiling-point solvent is used and ii) the less limitating Pt source/drain electrodes. This analytical study proves that solid phase LIFT printing is a reliable technology for the fabrication of thin, organic large area electronics in a well-defined manner.

  1. Ultra-thin films of polysilsesquioxanes possessing 3-methacryloxypropyl groups as gate insulator for organic field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Nakahara, Yoshio; Kawa, Haruna [Department of Applied Chemistry, Faculty of Systems Engineering, Wakayama University, 930 Sakae-dani, Wakayama 640-8510 (Japan); Yoshiki, Jun [Division of Information and Electronic Engineering, Faculty of Engineering, Muroran Institute of Technology, 27-1 Mizumoto-cho, Muroran 050-8585 (Japan); Kumei, Maki; Yamamoto, Hiroyuki; Oi, Fumio [Konishi Chemical IND. Co., LTD., 3-4-77 Kozaika, Wakayama 641-0007 (Japan); Yamakado, Hideo [Department of Applied Chemistry, Faculty of Systems Engineering, Wakayama University, 930 Sakae-dani, Wakayama 640-8510 (Japan); Fukuda, Hisashi [Division of Engineering for Composite Functions, Faculty of Engineering, Muroran Institute of Technology, 27-1 Mizumoto-cho, Muroran 050-8585 (Japan); Kimura, Keiichi, E-mail: kkimura@center.wakayama-u.ac.jp [Department of Applied Chemistry, Faculty of Systems Engineering, Wakayama University, 930 Sakae-dani, Wakayama 640-8510 (Japan)

    2012-10-01

    Polysilsesquioxanes (PSQs) possessing 3-methacryloxypropyl groups as an organic moiety of the side chain were synthesized by sol-gel condensation copolymerization of the corresponding trialkoxysilanes. The ultra-thin PSQ film with a radical initiator and a cross-linking agent was prepared by a spin-coating method, and the film was cured integrally at low temperatures of less than 120 Degree-Sign C through two different kinds of polymeric reactions, which were radical polymerization of vinyl groups and sol-gel condensation polymerization of terminated silanol and alkoxy groups. The obtained PSQ film showed the almost perfect solubilization resistance to acetone, which is a good solvent of PSQ before polymerization. It became clear by atomic force microscopy observation that the surface of the PSQ film was very smooth at a nano-meter level. Furthermore, pentacene-based organic field-effect transistor (OFET) with the PSQ film as a gate insulator showed typical p-channel enhancement mode operation characteristics and therefore the ultra-thin PSQ film has the potential to be applicable for solution-processed OFET systems. - Highlights: Black-Right-Pointing-Pointer Polysilsesquioxanes (PSQs) possessing 3-methacryloxypropyl groups were synthesized. Black-Right-Pointing-Pointer The ultra-thin PSQ film could be cured at low temperatures of less than 120 Degree-Sign C. Black-Right-Pointing-Pointer The PSQ film showed the almost perfect solubilization resistance to organic solvent. Black-Right-Pointing-Pointer The surface of the PSQ film was very smooth at a nano-meter level. Black-Right-Pointing-Pointer Pentacene-based organic field-effect transistor with the PSQ film was fabricated.

  2. Metal-oxide assisted surface treatment of polyimide gate insulators for high-performance organic thin-film transistors.

    Science.gov (United States)

    Kim, Sohee; Ha, Taewook; Yoo, Sungmi; Ka, Jae-Won; Kim, Jinsoo; Won, Jong Chan; Choi, Dong Hoon; Jang, Kwang-Suk; Kim, Yun Ho

    2017-06-14

    We developed a facile method for treating polyimide-based organic gate insulator (OGI) surfaces with self-assembled monolayers (SAMs) by introducing metal-oxide interlayers, called the metal-oxide assisted SAM treatment (MAST). To create sites for surface modification with SAM materials on polyimide-based OGI (KPI) surfaces, the metal-oxide interlayer, here amorphous alumina (α-Al2O3), was deposited on the KPI gate insulator using spin-coating via a rapid sol-gel reaction, providing an excellent template for the formation of a high-quality SAM with phosphonic acid anchor groups. The SAM of octadecylphosphonic acid (ODPA) was successfully treated by spin-coating onto the α-Al2O3-deposited KPI film. After the surface treatment by ODPA/α-Al2O3, the surface energy of the KPI thin film was remarkably decreased and the molecular compatibility of the film with an organic semiconductor (OSC), 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C10), was increased. Ph-BTBT-C10 molecules were uniformly deposited on the treated gate insulator surface and grown with high crystallinity, as confirmed by atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The mobility of Ph-BTBT-C10 thin-film transistors (TFTs) was approximately doubled, from 0.56 ± 0.05 cm(2) V(-1) s(-1) to 1.26 ± 0.06 cm(2) V(-1) s(-1), after the surface treatment. The surface treatment of α-Al2O3 and ODPA significantly decreased the threshold voltage from -21.2 V to -8.3 V by reducing the trap sites in the OGI and improving the interfacial properties with the OSC. We suggest that the MAST method for OGIs can be applied to various OGI materials lacking reactive sites using SAMs. It may provide a new platform for the surface treatment of OGIs, similar to that of conventional SiO2 gate insulators.

  3. Low-voltage antimony-doped SnO2 nanowire transparent transistors gated by microporous SiO2-based proton conductors

    Institute of Scientific and Technical Information of China (English)

    Xuan Rui-Jie; Liu Hui-Xuan

    2012-01-01

    A battery drivable low-voltage transparent lightly antimony(Sb)-doped SnO2 nanowire electric-double-layer (EDL)field-effect transistor (FET) is fabricated on an ITO glass substrate at room temperature.An ultralow operation voltage of 1 V is obtained on account of an untralarge specific gate capacitance (~ 2.14 μF/cm2) directly bound up with mobile ions-induced EDL (sandwiched between the top and bottom electrodes) effect.The transparent FET shows excellent electric characteristics with a field-effect mobility of 54.43 cm2/V.s,current on/off ration of 2 × 104,and subthreshold gate voltage swing (S =dVgs/d(logIds)) of 140 mV/decade.The threshold voltage Vth (0.1 V) is estimated which indicates that the SnO2 namowire transistor operates in an n-type enhanced mode.Such a low-voltage transparent nanowire transistor gated by a microporous SiO2-based solid electrolyte is very promising for battery-powered portable nanoscale sensors.

  4. Sub-15 nm gate-all-around field effect transistors on vertical silicon nanowires

    Science.gov (United States)

    Larrieu, G.; Guerfi, Y.; Han, X. L.; Clément, N.

    2017-04-01

    A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling.

  5. Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang [Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Zhao, Juan [School of Optoelectronic Information, University of Electronic Science and Technology of China, Chengdu 610054 (China); Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S., E-mail: michael.arnold@wisc.edu [Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States)

    2015-08-03

    Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10{sup 4} and a field-effect mobility of 5 cm{sup 2} V{sup −1} s{sup −1} under elongation and demonstrate invariant performance over 1000 stretching cycles.

  6. ZnO-based thin film transistors employing aluminum titanate gate dielectrics deposited by spray pyrolysis at ambient air.

    Science.gov (United States)

    Afouxenidis, Dimitrios; Mazzocco, Riccardo; Vourlias, Georgios; Livesley, Peter J; Krier, Anthony; Milne, William I; Kolosov, Oleg; Adamopoulos, George

    2015-04-08

    The replacement of SiO2 gate dielectrics with metal oxides of higher dielectric constant has led to the investigation of a wide range of materials with superior properties compared with SiO2. Despite their attractive properties, these high-k dielectrics are usually manufactured using costly vacuum-based techniques. To overcome this bottleneck, research has focused on the development of alternative deposition methods based on solution-processable metal oxides. Here we report the application of spray pyrolysis for the deposition and investigation of Al2x-1·TixOy dielectrics as a function of the [Ti(4+)]/[Ti(4+)+2·Al(3+)] ratio and their implementation in thin film transistors (TFTs) employing spray-coated ZnO as the active semiconducting channels. The films are studied by UV-visible absorption spectroscopy, spectroscopic ellipsometry, impedance spectroscopy, atomic force microscopy, X-ray diffraction and field-effect measurements. Analyses reveal amorphous Al2x-1·TixOy dielectrics that exhibit a wide band gap (∼4.5 eV), low roughness (∼0.9 nm), high dielectric constant (k ∼ 13), Schottky pinning factor S of ∼0.44 and very low leakage currents (<5 nA/cm(2)). TFTs employing stoichiometric Al2O3·TiO2 gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with low operating voltages (∼10 V), negligible hysteresis, high on/off current modulation ratio of ∼10(6), subthreshold swing (SS) of ∼550 mV/dec and electron mobility of ∼10 cm(2) V(-1) s(-1).

  7. Characteristics enhancement of a GaAs based heterostructure field-effect transistor with an electrophoretic deposition (EPD) surface treated gate structure

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Chun-Chia [Institute of Microelectronics, Department of Electrical Engineering, National Cheng-Kung University, No. 1, University Road, Tainan 70101, Taiwan, ROC (China); Chen, Huey-Ing; Liu, I-Ping [Department of Chemical Engineering, National Cheng-Kung University, No. 1, University Road, Tainan 70101, Taiwan, ROC (China); Chou, Po-Cheng; Liou, Jian-Kai; Tsai, Yu-Ting [Institute of Microelectronics, Department of Electrical Engineering, National Cheng-Kung University, No. 1, University Road, Tainan 70101, Taiwan, ROC (China); Liu, Wen-Chau, E-mail: wcliu@mail.ncku.edu.tw [Institute of Microelectronics, Department of Electrical Engineering, National Cheng-Kung University, No. 1, University Road, Tainan 70101, Taiwan, ROC (China)

    2015-06-30

    Highlights: • Platinum (Pt) was formed on the gate region of a heterostructure field-effect transistor (HFET) by an electrophoretic deposition (EPD) approach. • EPD-based Pt morphologies were examined by SEM, AFM, XRD, and EDS analyses. • EPD approach shows advantages of low cost, simple apparatus, and adjustable alloy grain size. • EPD-based Pt-gate structure contributes to device's superior temperature-dependent I–V characteristics. - Abstract: A Pt/AlGaAs/InGaAs/GaAs heterostructure field-effect transistor (HFET), prepared by an electrophoretic deposition (EPD) approach on gate Schottky contact region, is fabricated and studied. The EPD-based Pt-gates with three different molar ratios (ω{sub 0}) are examined by scanning electron microscopy (SEM) image. Good Pt-gate coverage with effective reduction of thermal-induced defects at Pt/AlGaAs interface is achieved through a low temperature EPD approach. Experimentally, for a gate dimension of 1 μm × 100 μm, a lower gate current of 1.9 × 10{sup −2} mA/mm, a higher turn-on voltage of 0.85 V, a higher maximum drain saturation current of 319.3 mA/mm, and a higher maximum extrinsic transconductance of 146.8 mS/mm are obtained for an EPD-based HFET at 300 K. Moreover, comparable microwave characteristics of an EPD-based HFET are demonstrated at different temperature ambiences. Therefore, based on the improved DC performance and inherent benefits of low cost, simple apparatus, flexible deposition on varied substrates, and adjustable alloy grain size, the proposed EPD approach shows the promise to fabricate high-performance electronic devices.

  8. Piezoelectric potential gated field-effect transistor based on a free-standing ZnO wire.

    Science.gov (United States)

    Fei, Peng; Yeh, Ping-Hung; Zhou, Jun; Xu, Sheng; Gao, Yifan; Song, Jinhui; Gu, Yudong; Huang, Yanyi; Wang, Zhong Lin

    2009-10-01

    We report an external force triggered field-effect transistor based on a free-standing piezoelectric fine wire (PFW). The device consists of an Ag source electrode and an Au drain electrode at two ends of a ZnO PFW, which were separated by an insulating polydimethylsiloxane (PDMS) thin layer. The working principle of the sensor is proposed based on the piezoelectric potential gating effect. Once subjected to a mechanical impact, the bent ZnO PFW cantilever creates a piezoelectric potential distribution across it width at its root and simultaneously produces a local reverse depletion layer with much higher donor concentration than normal, which can dramatically change the current flowing from the source electrode to drain electrode when the device is under a fixed voltage bias. Due to the free-standing structure of the sensor device, it has a prompt response time less than 20 ms and quite high and stable sensitivity of 2%/microN. The effect from contact resistance has been ruled out.

  9. Zinc Oxide Nanorods Grown on Printed Circuit Board for Extended-Gate Field-Effect Transistor pH Sensor

    Science.gov (United States)

    Van Thanh, Pham; Nhu, Le Thi Quynh; Mai, Hong Hanh; Tuyen, Nguyen Viet; Doanh, Sai Cong; Viet, Nguyen Canh; Kien, Do Trung

    2017-02-01

    Zinc oxide (ZnO) nanorods (NRs) were grown directly on printed circuit boards with a 35-μm-thick copper layer using a seedless galvanic-cell hydrothermal process. The hexagonal structure of the synthesized ZnO NRs was observed by scanning electron microscopy. The microstructural characteristics of the as-grown ZnO NRs were investigated by x-ray diffraction analysis, revealing preferred (002) growth direction. Raman and photoluminescence spectra confirmed the high crystalline quality of the ZnO NRs. As-grown ZnO NRs were then grown for 7 h using the galvanic effect for use as the pH membrane of an extended-gate field-effect transistor pH sensor (pH-EGFET). The current-voltage characteristics showed sensitivity of 15.4 mV/pH and 0.26 (μA)1/2/pH in the linear and saturated region, respectively. Due to their cost effectiveness, low-temperature processing, and ease of fabrication, such devices are potential candidates for use as flexible, low-cost, disposable biosensors.

  10. Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field effect transistor

    Science.gov (United States)

    Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

    2016-06-01

    In this paper, for the first time, the impact of drain doping profile on device electrostatics and circuit performance of novel InAs/Si Hetero-junction Double Gate Tunnel Field Effect Transistor (H-DGTFET) has been investigated. A highly doped layer placed near the source and channel junction decreases the width of the depletion region, thus, improving the ON-current and circuit performance. For this purpose, the effects of drain doping profile on the analog/RF performance of H-DGTFET is studied in terms of transconductance (gm), parasitic capacitances, cut-off frequency (fT) and gain bandwidth (GBW) product. The value of fT is increased by 13.84% and the GBW is improved by 144.7% for GD profile in Drain with CL = 0.05 when compared to UD profile. Further, the impact of drain doping profile on the circuit performance has been investigated by implementing digital and analog/RF circuits most widely used for nanoelectronic applications. For this, Verilog-A model has been developed for InAs/Si H-DGTFET. The circuit level performance assessment is carried out by implementing inverter, common source amplifier, inverter amplifier and pseudo differential amplifier by using Complementary TFET (CTFET) technology in a Verilog-A environment.

  11. High performance ZnO nanowire field effect transistors with organic gate nanodielectrics: effects of metal contacts and ozone treatment

    Energy Technology Data Exchange (ETDEWEB)

    Ju, Sanghyun [School of Electrical and Computer Engineering, and Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907 (United States); Lee, Kangho [School of Electrical and Computer Engineering, and Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907 (United States); Yoon, Myung-Han [Department of Chemistry and Materials Research Center, and Institute for Nanoelectronics and Computing, Northwestern University, Evanston, IL 60208-3113 (United States); Facchetti, Antonio [Department of Chemistry and Materials Research Center, and Institute for Nanoelectronics and Computing, Northwestern University, Evanston, IL 60208-3113 (United States); Marks, Tobin J [Department of Chemistry and Materials Research Center, and Institute for Nanoelectronics and Computing, Northwestern University, Evanston, IL 60208-3113 (United States); Janes, David B [School of Electrical and Computer Engineering, and Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907 (United States)

    2007-04-18

    High performance ZnO nanowire field effect transistors (NW-FETs) were fabricated using a nanoscopic self-assembled organic gate insulator and characterized in terms of conventional device performance metrics. To optimize device performance and understand the effects of interface properties, devices were fabricated with both Al and Au/Ti source/drain contacts, and device electrical properties were characterized following annealing and ozone treatment. Ozone-treated single ZnO NW-FETs with Al contacts exhibited an on-current (I{sub on}) of {approx}4 {mu}A at 0.9 V{sub gs} and 1.0 V{sub ds}, a threshold voltage (V{sub th}) of 0.2 V, a subthreshold slope (S) of {approx}130 mV/decade, an on-off current ratio (I{sub on}:I{sub off}) of {approx}10{sup 7}, and a field effect mobility ({mu}{sub eff}) of {approx}1175 cm{sup 2} V{sup -1} s{sup -1}. In addition, ozone-treated ZnO NW-FETs consistently retained the enhanced device performance metrics after SiO{sub 2} passivation. A 2D device simulation was performed to explain the enhanced device performance in terms of changes in interfacial trap and fixed charge densities.

  12. High performance ZnO nanowire field effect transistors with organic gate nanodielectrics: effects of metal contacts and ozone treatment

    Science.gov (United States)

    Ju, Sanghyun; Lee, Kangho; Yoon, Myung-Han; Facchetti, Antonio; Marks, Tobin J.; Janes, David B.

    2007-04-01

    High performance ZnO nanowire field effect transistors (NW-FETs) were fabricated using a nanoscopic self-assembled organic gate insulator and characterized in terms of conventional device performance metrics. To optimize device performance and understand the effects of interface properties, devices were fabricated with both Al and Au/Ti source/drain contacts, and device electrical properties were characterized following annealing and ozone treatment. Ozone-treated single ZnO NW-FETs with Al contacts exhibited an on-current (Ion) of ~4 µA at 0.9 Vgs and 1.0 Vds, a threshold voltage (Vth) of 0.2 V, a subthreshold slope (S) of ~130 mV/decade, an on-off current ratio (Ion:Ioff) of ~107, and a field effect mobility (μeff) of ~1175 cm2 V-1 s-1. In addition, ozone-treated ZnO NW-FETs consistently retained the enhanced device performance metrics after SiO2 passivation. A 2D device simulation was performed to explain the enhanced device performance in terms of changes in interfacial trap and fixed charge densities.

  13. A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects

    Science.gov (United States)

    Raksharam; Dutta, Aloke K.

    2017-04-01

    In this paper, a unified analytical model for the drain current of a symmetric Double-Gate Junctionless Field-Effect Transistor (DG-JLFET) is presented. The operation of the device has been classified into four modes: subthreshold, semi-depleted, accumulation, and hybrid; with the main focus of this work being on the accumulation mode, which has not been dealt with in detail so far in the literature. A physics-based model, using a simplified one-dimensional approach, has been developed for this mode, and it has been successfully integrated with the model for the hybrid mode. It also includes the effect of carrier mobility degradation due to the transverse electric field, which was hitherto missing in the earlier models reported in the literature. The piece-wise models have been unified using suitable interpolation functions. In addition, the model includes two most important short-channel effects pertaining to DG-JLFETs, namely the Drain Induced Barrier Lowering (DIBL) and the Subthreshold Swing (SS) degradation. The model is completely analytical, and is thus computationally highly efficient. The results of our model have shown an excellent match with those obtained from TCAD simulations for both long- and short-channel devices, as well as with the experimental data reported in the literature.

  14. Low-temperature processable inherently photosensitive polyimide as a gate insulator for organic thin-film transistors

    Science.gov (United States)

    Pyo, Seungmoon; Son, Hyunsam; Choi, Kil-Yeong; Yi, Mi Hye; Hong, Sung Kwon

    2005-03-01

    We have fabricated organic thin-film transistors (OTFTs) on polyethersulfone substrate using low-temperature processable, inherently photosensitive polyimide as the gate insulator and pentacene as the active material. The polyimide was prepared through two-step reaction. The polyimide precursor, poly(amic acid), was prepared from a dianhydride and aromatic diamine through a polycondensation reaction, and subsequently converted to its corresponding polyimide by a chemical imidization. Photolithographic properties of the polyimide are investigated. The pattern resolution of the cured polyimide was about 50μm. The pentacene OTFTs with the patterned polyimide were obtained with a carrier mobility of 0.1cm2/Vs and ION/IOFF of 5×105. The OTFT characteristics are discussed in more detail with respect to the electrical properties of the photosensitive polyimide thin film. This low-temperature photopatternable polyimide paves the way for the easy and low-cost fabrication of OTFT arrays without expensive and complicated photolithography and dry etching processes.

  15. High performing solution-coated electrolyte-gated organic field-effect transistors for aqueous media operation

    Science.gov (United States)

    Zhang, Qiaoming; Leonardi, Francesca; Casalini, Stefano; Temiño, Inés; Mas-Torrent, Marta

    2016-12-01

    Since the first demonstration, the electrolyte-gated organic field-effect transistors (EGOFETs) have immediately gained much attention for the development of cutting-edge technology and they are expected to have a strong impact in the field of (bio-)sensors. However EGOFETs directly expose their active material towards the aqueous media, hence a limited library of organic semiconductors is actually suitable. By using two mostly unexplored strategies in EGOFETs such as blended materials together with a printing technique, we have successfully widened this library. Our benchmarks were 6,13-bis(triisopropylsilylethynyl)pentacene and 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene (diF-TES-ADT), which have been firstly blended with polystyrene and secondly deposited by means of the bar-assisted meniscus shearing (BAMS) technique. Our approach yielded thin films (i.e. no thicker than 30 nm) suitable for organic electronics and stable in liquid environment. Up to date, these EGOFETs show unprecedented performances. Furthermore, an extremely harsh environment, like NaCl 1M, has been used in order to test the limit of operability of these electronic devices. Albeit an electrical worsening is observed, our devices can operate under different electrical stresses within the time frame of hours up to a week. In conclusion, our approach turns out to be a powerful tool for the EGOFET manufacturing.

  16. Improvement of switching speed of a 600-V nonpunch through insulated gate bipolar transistor using fast neutron irradiation

    Energy Technology Data Exchange (ETDEWEB)

    Baek, Ha Ni; Sun, Gwang Min; Kim, Ji Suck; Hoang, Sy Minh Tuan; Jin, Mi Eun; Ahn, Sung Ho [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2017-02-15

    Fast neutron irradiation was used to improve the switching speed of a 600-V nonpunch-through insulated gate bipolar transistor. Fast neutron irradiation was carried out at 30-MeV energy in doses of 1 × 10{sup 8} n/cm{sup 2}, 1 × 10{sup 9} n/cm{sup 2}, 1 × 10{sup 10} n/cm{sup 2}, and 1 × 10{sup 11} n/cm{sup 2}. Electrical characteristics such as current–voltage, forward on-state voltage drop, and switching speed of the device were analyzed and compared with those prior to irradiation. The on-state voltage drop of the initial devices prior to irradiation was 2.08 V, which increased to 2.10 V, 2.20 V, 2.3 V, and 2.4 V, respectively, depending on the irradiation dose. This effect arises because of the lattice defects generated by the fast neutrons. In particular, the turnoff delay time was reduced to 92 nanoseconds, 45% of that prior to irradiation, which means there is a substantial improvement in the switching speed of the device.

  17. Zinc Oxide Nanorods Grown on Printed Circuit Board for Extended-Gate Field-Effect Transistor pH Sensor

    Science.gov (United States)

    Van Thanh, Pham; Nhu, Le Thi Quynh; Mai, Hong Hanh; Tuyen, Nguyen Viet; Doanh, Sai Cong; Viet, Nguyen Canh; Kien, Do Trung

    2017-06-01

    Zinc oxide (ZnO) nanorods (NRs) were grown directly on printed circuit boards with a 35- μm-thick copper layer using a seedless galvanic-cell hydrothermal process. The hexagonal structure of the synthesized ZnO NRs was observed by scanning electron microscopy. The microstructural characteristics of the as-grown ZnO NRs were investigated by x-ray diffraction analysis, revealing preferred (002) growth direction. Raman and photoluminescence spectra confirmed the high crystalline quality of the ZnO NRs. As-grown ZnO NRs were then grown for 7 h using the galvanic effect for use as the pH membrane of an extended-gate field-effect transistor pH sensor (pH-EGFET). The current-voltage characteristics showed sensitivity of 15.4 mV/pH and 0.26 ( μA)1/2/pH in the linear and saturated region, respectively. Due to their cost effectiveness, low-temperature processing, and ease of fabrication, such devices are potential candidates for use as flexible, low-cost, disposable biosensors.

  18. Theoretical Study of Triboelectric-Potential Gated/Driven Metal-Oxide-Semiconductor Field-Effect Transistor.

    Science.gov (United States)

    Peng, Wenbo; Yu, Ruomeng; He, Yongning; Wang, Zhong Lin

    2016-04-26

    Triboelectric nanogenerator has drawn considerable attentions as a potential candidate for harvesting mechanical energies in our daily life. By utilizing the triboelectric potential generated through the coupling of contact electrification and electrostatic induction, the "tribotronics" has been introduced to tune/control the charge carrier transport behavior of silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). Here, we perform a theoretical study of the performances of tribotronic MOSFET gated by triboelectric potential in two working modes through finite element analysis. The drain-source current dependence on contact-electrification generated triboelectric charges, gap separation distance, and externally applied bias are investigated. The in-depth physical mechanism of the tribotronic MOSFET operations is thoroughly illustrated by calculating and analyzing the charge transfer process, voltage relationship to gap separation distance, and electric potential distribution. Moreover, a tribotronic MOSFET working concept is proposed, simulated and studied for performing self-powered FET and logic operations. This work provides a deep understanding of working mechanisms and design guidance of tribotronic MOSFET for potential applications in micro/nanoelectromechanical systems (MEMS/NEMS), human-machine interface, flexible electronics, and self-powered active sensors.

  19. Effects of Ta incorporation in Y2O3 gate dielectric of InGaZnO thin-film transistor

    Science.gov (United States)

    Song, J. Q.; Qian, L. X.; Lai, P. T.

    2016-10-01

    The effects of Ta incorporation in Y2O3 gate dielectric on the electrical characteristics of InGaZnO thin-film transistor are investigated. With an appropriate Ta content in the Y2O3 gate dielectric, the saturation mobility of the thin-film transistor can be significantly increased, about three times that of the control sample with Y2O3 gate dielectric. Accordingly, the sample with a Ta/Ta+Y ratio of 68.6% presents a high saturation mobility of 33.5 cm2 V-1 s-1, low threshold voltage of 2.0 V, large on/off current ratio of 2.8 × 107, and suppressed hysteresis. This can be attributed to the fact that the Ta incorporation can suppress the hygroscopicity of Y2O3 and thus reduces the Y2O3/InGaZnO interface roughness and also the traps at/near the interface, as supported by atomic force microscopy and low-frequency noise measurement, respectively. However, excessive Ta incorporation in the Y2O3 gate dielectric leads to degradation in device performance because Ta-related defects are generated.

  20. High performance TiN gate contact on AlGaN/GaN transistor using a mechanically strain induced P-doping

    Energy Technology Data Exchange (ETDEWEB)

    Soltani, A., E-mail: ali.soltani@iemn.univ-lille1.fr; Rousseau, M.; Gerbedoen, J.-C.; Bourzgui, N. [Institut d' Electronique de Microélectronique et de Nanotechnologie, UMR-CNRS 8520, USTL, Avenue Poincaré, 59652 Villeneuve d' Ascq (France); Mattalah, M. [Laboratoire de Microélectronique, Université Djilali Liabès, 22000 Sidi Bel Abbès (Algeria); Bonanno, P. L.; Ougazzaden, A. [School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30324-0250 (United States); UMI 2958 Georgia Tech-CNRS, Georgia Tech Lorraine, 2-3 Rue Marconi, 57070 Metz-Technopôle (France); Telia, A. [LMI, Electronic Department, Faculty of Engineering, Mentouri University of Constantine, Constantine (Algeria); Patriarche, G. [Laboratoire de Photonique et Nanostructures, CNRS UPR 20, Route de Nozay, 91460 Marcoussis (France); BenMoussa, A. [Solar Terrestrial Center of Excellence, Royal Observatory of Belgium, Circular 3, B-1180 Brussels (Belgium)

    2014-06-09

    High performance titanium nitride sub-100 nm rectifying contact, deposited by sputtering on AlGaN/GaN high electron mobility transistors, shows a reverse leakage current as low as 38 pA/mm at V{sub GS} = −40 V and a Schottky barrier height of 0.95 eV. Based on structural characterization and 3D simulations, it is found that the polarization gradient induced by the gate metallization forms a P-type pseudo-doping region under the gate between the tensile surface and the compressively strained bulk AlGaN barrier layer. The strain induced by the gate metallization can compensate for the piezoelectric component. As a result, the gate contact can operate at temperatures as high as 700 °C and can withstand a large reverse bias of up to −100 V, which is interesting for high-performance transistors dedicated to power applications.

  1. Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

    Science.gov (United States)

    Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

    2016-08-01

    A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics ft/fmax of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with ft/fmax of 48/60 GHz.

  2. An improved fault tolerant for a five-phase induction machine under open gate transistor faults

    Directory of Open Access Journals (Sweden)

    Elhussien A. Mahmoud

    2016-09-01

    Full Text Available Of the different outstanding merits of multiphase machines is their ability to run steadily with some phases open. Commonly, optimal current control (OCC to remaining healthy phases is usually engaged to ensure a certain optimization criterion. Most of the available literature investigates the fault case where one of the motor phases is completely disconnected due to a failure in one of the inverter legs. To maintain pre-fault operating conditions, the machine experiences a 53% increase in the total copper loss; otherwise, the machine should be deloaded. Under open gate fault condition of one of the upper or lower switching devices, the corresponding switch will be open, while the other switch in the same leg can be still used to enhance the machine performance under this case. This paper proposes an improved control strategy to optimize a five-phase induction motor drive under a gate failure of one of the inverter switching devices using a half cycle optimal current control (HCOCC technique. When compared with a conventional OCC, the proposed controller can effectively reduce the excessive copper loss by 50%, improve efficiency, and decrease the corresponding derating factor. The proposed controller is verified using a five-phase induction machine based on a simulation case study using MATLAB/SIMULINK.

  3. Quantum Interference Phenomena and Novel Switching in Split Gate High Electron Mobility Transistors.

    Science.gov (United States)

    Wu, Jong-Ching

    Nanometer scales electronic channels with and without a discontinuity were made in modulation-doped AlGaAs/GaAs heterojunctions using a split-gate technique. Quantum interference phenomena in an electron cavity, and fast switching behavior due to hot electron effects in a lateral double potential barrier structure were explored. First, one-dimensional channels with a double bend discontinuity were examined in the mK temperature range. Low-field ac-conductance measurements have evidenced quantum wave guide effects: resonant features were observed in the one-dimensional conductance plateaus in which the number of peaks was directly related to the geometry of the double bend. Temperature and magnetic field studies, along with a standing wave model have provided a better understanding of quantum interference phenomena in electron wave guide and cavity structures. Secondly, a structure containing two cascaded double bend discontinuities was studied. The structure behaves as a constricted cavity coupling two point-contacts, in which the depletion by the split gate was used to form and control the lateral double potential barriers. The low temperature source-drain characteristics exhibited a pronounced S-shaped negative differential conductance that can be attributed to a nonlinear electron temperature effect along the conducting path. The data presented show two types of conducting state: electron tunneling in the off state and hot electron conduction (thermionic emission) in the on state. The estimated switching speed of the device could be as fast as 5 ps due to short transit time.

  4. Explicit Compact Surface-Potential and Drain-Current Models for Generic Asymmetric Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    Science.gov (United States)

    Zhu, Zhaomin; Zhou, Xing; Chandrasekaran, Karthik; Rustagi, Subhash C.; See, Guan Huei

    2007-04-01

    In this paper, explicit surface potentials for undoped asymmetric-double-gate (a-DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) suitable for compact model development are presented for the first time. The model is physically derived from Poisson’s equation in each region of operation and adopted in a unified regional approach. The proposed model is physically scalable with oxide/channel thicknesses and has been verified with generic implicit solutions for independent gate biases as well as for different gate/oxide materials. The model is extendable to silicon-on-insulator (SOI) and symmetric-DG (s-DG) MOSFETs. Finally, a continuous, explicit drain-current equation has been derived on the basis of the developed explicit surface-potential solutions.

  5. High sensitivity AlGaN/GaN field effect transistor protein sensors operated in the subthreshold regime by a control gate electrode

    Science.gov (United States)

    Wen, Xuejin; Gupta, Samit; Wang, Yuji; Nicholson, Theodore R.; Lee, Stephen C.; Lu, Wu

    2011-07-01

    We demonstrate high sensitivity AlGaN/GaN field effect transistor biosensors with a control gate electrode for streptavidin detection. The device active area is functionalized with 3-Aminopropyltriethoxysilane and N-hydroxysulfosuccinimide-biotin for streptavidin binding. Without any electrochemical side effects, a gate voltage is applied through a Pt control electrode to the solution so that the device operates sensitively in the subthreshold regime. Due to the logarithmic relationship between the channel current and gate voltage in the subthreshold regime, at a concentration of 4.73 pM streptavidin, the device exhibits 9.97% current change in the subthreshold regime compared with the current in phosphate buffered saline solution. In the linear regime, the current change is 0.49% at the same streptavidin concentration.

  6. Current collapse imaging of Schottky gate AlGaN/GaN high electron mobility transistors by electric field-induced optical second-harmonic generation measurement

    Energy Technology Data Exchange (ETDEWEB)

    Katsuno, Takashi, E-mail: e1417@mosk.tytlabs.co.jp; Ishikawa, Tsuyoshi; Ueda, Hiroyuki; Uesugi, Tsutomu [Toyota Central R and D Laboratories Inc., Nagakute, Aichi 480-1192 (Japan); Manaka, Takaaki; Iwamoto, Mitsumasa [Department of Physical Electronics, Tokyo Institute of Technology, Meguro, Tokyo 152-8552 (Japan)

    2014-06-23

    Two-dimensional current collapse imaging of a Schottky gate AlGaN/GaN high electron mobility transistor device was achieved by optical electric field-induced second-harmonic generation (EFISHG) measurements. EFISHG measurements can detect the electric field produced by carriers trapped in the on-state of the device, which leads to current collapse. Immediately after (e.g., 1, 100, or 800 μs) the completion of drain-stress voltage (200 V) in the off-state, the second-harmonic (SH) signals appeared within 2 μm from the gate edge on the drain electrode. The SH signal intensity became weak with time, which suggests that the trapped carriers are emitted from the trap sites. The SH signal location supports the well-known virtual gate model for current collapse.

  7. Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain

    Science.gov (United States)

    Kwon, Dae Woong; Kim, Jang Hyun; Park, Euyhwan; Lee, Junil; Park, Taehyung; Lee, Ryoongbin; Kim, Sihyun; Park, Byung-Gook

    2016-06-01

    A novel fabrication method is proposed to reduce large gate-to-drain capacitance (C GD) and to improve AC switching characteristics in tunnel field-effect transistor (TFETs) with elevated drain (TFETED). In the proposed method, gate oxide at drain region (GDOX) is selectively formed through oxide deposition and spacer-etch process. Furthermore, the thicknesses of the GDOX are simply controlled by the amount of the oxide deposition and etch. Mixed-mode device and circuit technology computer aided design (TCAD) simulations are performed to verify the effects of the GDOX thickness on DC and AC switching characteristics of a TFETED inverter. As a result, it is found that AC switching characteristics such as output voltage pre-shoot and falling/rising delay are improved with nearly unchanged DC characteristics by thicker GDOX. This improvement is explained successfully by reduced C GD and positive shifted gate voltage (V G) versus C GD curves with the thicker GDOX.

  8. A Pt/AlGaN/GaN heterostructure field-effect transistor (HFET) prepared by an electrophoretic deposition (EPD)-gate approach

    Science.gov (United States)

    Hung, Ching-Wen; Chang, Ching-Hong; Chen, Wei-Cheng; Chen, Chun-Chia; Chen, Huey-Ing; Tsai, Yu-Ting; Tsai, Jung-Hui; Liu, Wen-Chau

    2016-10-01

    Based on an electrophoretic deposition (EPD)-gate approach, a Pt/AlGaN/GaN heterostructure field-effect transistor (HFET) is fabricated and investigated at higher temperatures. The Pt/AlGaN interface with nearly oxide-free is verified by an Auger Electron Spectroscopy (AES) depth profile for the studied EPD-HFET. This result substantially enhances device performance at room temperature (300 K). Experimentally, the studied EPD-HFET exhibits a high turn-on voltage, a well suppression on gate leakage, a superior maximum drain saturation current, and an excellent extrinsic transconductance. Moreover, the microwave performance of an EPD-HFET is demonstrated at room temperature. Consequentially, this EPD-gate approach gives a promise for high-performance electronic applications.

  9. Highly scaled ( Lg ˜ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μA/μm

    Science.gov (United States)

    Loh, Wei-Yip; Jeon, Kanghoon; Kang, Chang Yong; Oh, Jungwoo; King Liu, Tsu-Jae; Tseng, Hsing-Huang; Xiong, Wade; Majhi, Prashant; Jammy, Raj; Hu, Chenming

    2011-11-01

    Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60 nm gate length (effective gate length [Lg] ∼ 40 nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (ION)) > 100 μA/μm with ION/IOFF > 105 at a drain bias of -1 V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.

  10. In operando characterization of ion gel gating in electrochemical polythiophene transistors

    Science.gov (United States)

    Brady, Michael; Chabinyc, Michael; Hexemer, Alexander; Wang, Cheng

    To progress structural understanding of soft matter in electrochemical devices, it is critical to observe such structural detail in operando such that correlations among material choice, processing, structure, and performance are well formed. We explore these correlations in a novel TFT device, one in which the dielectric layer is a mobile ion gel comprised of a matrix polymer and ionic liquid. This design enables the low-voltage (1 - 2 V) operation of a high mobility P3HT transistor and has applications in low power electronics. Specifically, this work details the development of an in-situ sample environment for the characterization of TFTs under bias, using synchrotron X-ray scattering instruments such as GIWAXS, GISAXS, and RSoXS. Of particular interest are GIWAXS for characterization of the ion-crystallite interaction in P3HT and GISAXS for measuring the change in domain structure as ion channels form during biasing. Additionally, RSoXS is a critical tool for analyzing the composition profile of mobile ions within each layer with reflectivity, as well as for the characterization of domain swelling caused by ion infiltration. Generally, we have found that the mobile anion is a critical species in the electrochemical doping of P3HT, whereby this ion swells the P3HT layer and causes crystallite disordering. The dynamics of ion motion and the resulting effects on polymer structure will be of particular focus in in-situ GIWAXS and RSoXS measurements.

  11. A comparative study of spin coated and floating film transfer method coated poly (3-hexylthiophene)/poly (3-hexylthiophene)-nanofibers based field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Tiwari, Shashi; Balasubramanian, S. K. [Department of Electronics Engineering, Indian Institute of Technology (Banaras Hindu University), Varanasi 221005 (India); Takashima, Wataru [Research Center for Advanced Eco-fitting Technology, Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology, 2-4 Hibikino, Wakamatsu, Kitakyushu 808-0196 (Japan); Nagamatsu, S. [Department of Computer Science and Systems Engineerings, Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka 820-8502 (Japan); Prakash, Rajiv, E-mail: rajivprakash12@yahoo.com [School of Materials Science and Technology, Indian Institute of Technology (Banaras Hindu University), Varanasi 221005 (India)

    2014-09-07

    A comparative study on electrical performance, optical properties, and surface morphology of poly(3-hexylthiophene) (P3HT) and P3HT-nanofibers based “normally on” type p-channel field effect transistors (FETs), fabricated by two different coating techniques has been reported here. Nanofibers are prepared in the laboratory with the approach of self-assembly of P3HT molecules into nanofibers in an appropriate solvent. P3HT (0.3 wt. %) and P3HT-nanofibers (∼0.25 wt. %) are used as semiconductor transport materials for deposition over FETs channel through spin coating as well as through our recently developed floating film transfer method (FTM). FETs fabricated using FTM show superior performance compared to spin coated devices; however, the mobility of FTM films based FETs is comparable to the mobility of spin coated one. The devices based on P3HT-nanofibers (using both the techniques) show much better performance in comparison to P3HT FETs. The best performance among all the fabricated organic field effect transistors are observed for FTM coated P3HT-nanofibers FETs. This improved performance of nanofiber-FETs is due to ordering of fibers and also due to the fact that fibers offer excellent charge transport facility because of point to point transmission. The optical properties and structural morphologies (P3HT and P3HT-nanofibers) are studied using UV-visible absorption spectrophotometer and atomic force microscopy , respectively. Coating techniques and effect of fiber formation for organic conductors give information for fabrication of organic devices with improved performance.

  12. Investigation of the novel 4Hsbnd SiC trench MOSFET with non-uniform doping floating islands

    Science.gov (United States)

    Song, Qingwen; Tang, Xiaoyan; Tian, Ruiyan; Zhang, Yimeng; Guo, Tao; Tang, Guannan; Yang, Shuai; Yuan, Hao; He, Yanjing

    2016-11-01

    In this paper, a novel 4Hsbnd SiC trench metal-oxide-semiconductor field-effect transistor (MOSFET) with non-uniform doping floating islands is proposed, using a Gaussian doping profile in the floating islands. The feature of the non-uniform doping floating island is that the doping concentration of upper part is higher than the lower part. The electric field between the floating island and drift region can be reduced by the decrease in the doping concentration of the lower part. At the same time, the high doping concentration for the upper part of the floating island is utilized, so that gate oxide layer at the sharp corner of the trench gate bottom cannot be broken down in advance. The simulation results indicate that the breakdown voltage of the novel structure can increase by 48%, compared with the structure with the uniform doping (6 × 1017 cm-3) floating island. Furthermore, the switching and gate charge characteristics of the UMOSFETs with uniform and Gaussian doping floating islands have been simulated using two simple switching circuits. The results indicate that changing the doping concentration of the floating islands has no negative effect on the switching characteristics.

  13. Investigation of passivation effects in AlGaN/GaN metal-insulator-semiconductor high electron-mobility transistor by gate-drain conductance dispersion study

    Institute of Scientific and Technical Information of China (English)

    Bi Zhi-Wei; Chang Yong-Ming; Li Zhi-Ming; Mei Nan; Hu Zhen-Hua; Mao Wei; Hao Yue; Feng Qian; Cao Yan-Rong; Gao Zhi-Yuan; Zhang Jin-Cheng; Ma Xiao-Hua

    2011-01-01

    This paper studies the drain current collapse of AlGaN/GaN metal-insulator-semiconductor high electron-mobility transistors(MIS-HEMTs)with NbAlO dielectric by applying dual-pulsed stress to the gate and drain of the device.For NbAlO MIS-HEMT,smaller current collapse is found,especially when the gate static voltage is-8 V.Through a thorough study of the gate-drain conductance dispersion,it is found that the growth of NbAlO can reduce the trap density of the AlGaN surface.Therefore,fewer traps can be filled by gate electrons,and hence the depletion effect in the channel is suppressed effectively.It is proved that the NbAlO gate dielectric can not only decrease gate leakage current but also passivate the AlGaN surface effectively,and weaken the current collapse effect accordingly.

  14. NOT and NAND logic circuits composed of top-gate ZnO nanowire field-effect transistors with high-k Al(2)O(3) gate layers.

    Science.gov (United States)

    Yeom, Donghyuk; Keem, Kihyun; Kang, Jeongmin; Jeong, Dong-Young; Yoon, Changjoon; Kim, Dongseung; Kim, Sangsig

    2008-07-02

    Electrical characteristics of NOT and NAND logic circuits fabricated using top-gate ZnO nanowire field-effect transistors (FETs) with high-k Al(2)O(3) gate layers were investigated in this study. To form a NOT logic circuit, two identical FETs whose I(on)/I(off) ratios were as high as ∼10(8) were connected in series in a single ZnO nanowire channel, sharing a common source electrode. Its voltage transfer characteristics exhibited an inverting operation and its logic swing was 98%. In addition, the characteristics of a NAND logic circuit composed of three top-gate FETs connected in series in a single nanowire channel are discussed in this paper.

  15. Characterization of high-dose and high-energy implanted gate and source diode and analysis of lateral spreading of p gate profile in high voltage SiC static induction transistors

    Science.gov (United States)

    Onose, Hidekatsu; Kobayashi, Yutaka; Onuki, Jin

    2017-03-01

    The effect of the p gate dose on the characteristics of the gate-source diode in SiC static induction transistors (SIT) was investigated. It was found that a dose of 1.5 × 1014 cm-2 yields a pn junction breakdown voltage higher than 60 V and good forward characteristics. A normally on SiC SIT was fabricated and demonstrated. A blocking voltage higher than 2.0 kV at a gate-source voltage of -50 V and on-resistance of 70 mΩ cm2 were obtained. Device simulations were performed to investigate the effect of the lateral spreading. By comparing the measured I-V curves with simulation results, the lateral spreading factor was estimated to be about 0.5. The lateral spreading detrimentally affected the electrical properties of the SIT made using implantations at energies higher than 1 MeV.

  16. Tinv Scaling and Gate Leakage Reduction for n-Type Metal Oxide Semiconductor Field Effect Transistor with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone-Water-Last Treatment

    Science.gov (United States)

    Oshiyama, Itaru; Tai, Kaori; Hirano, Tomoyuki; Yamaguchi, Shinpei; Tanaka, Kazuaki; Hagimoto, Yoshiya; Uemura, Takayuki; Ando, Takashi; Watanabe, Koji; Yamamoto, Ryo; Kanda, Saori; Wang, Junli; Tateshita, Yasushi; Wakabayashi, Hitoshi; Tagawa, Yukio; Tsukamoto, Masanori; Iwamoto, Hayato; Saito, Masaki; Oshima, Masaharu; Toyoda, Satoshi; Nagashima, Naoki; Kadomura, Shingo

    2008-04-01

    In this paper, we demonstrate a wet treatment for the HfSix/HfO2 gate stack of n-type metal oxide semiconductor field effect transistor (nMOSFET) fabricated by a gate-last process in order to scale down the electrical thickness at inversion state Tinv value and reduce the gate leakage Jg. As a result, we succeeded in scaling down Tinv to 1.41 nm without mobility or Jg degradation by ozone-water-last treatment. We found that a high-density interfacial layer (IFL) is formed owing to the ozone-water-last treatment, and Hf diffusion to the IFL is suppressed, which was analyzed by high-resolution angle-resolved spectroscopy.

  17. Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

    KAUST Repository

    Alshammari, Fwzah H.

    2016-08-24

    We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

  18. Graphene-based liquid-gated field effect transistor for biosensing: Theory and experiments.

    Science.gov (United States)

    Reiner-Rozman, Ciril; Larisika, Melanie; Nowak, Christoph; Knoll, Wolfgang

    2015-08-15

    We present an experimental and theoretical characterization for reduced Graphene-Oxide (rGO) based FETs used for biosensing applications. The presented approach shows a complete result analysis and theoretically predictable electrical properties. The formulation was tested for the analysis of the device performance in the liquid gate mode of operation with variation of the ionic strength and pH-values of the electrolytes in contact with the FET. The dependence on the Debye length was confirmed experimentally and theoretically, utilizing the Debye length as a working parameter and thus defining the limits of applicability for the presented rGO-FETs. Furthermore, the FETs were tested for the sensing of biomolecules (bovine serum albumin (BSA) as reference) binding to gate-immobilized anti-BSA antibodies and analyzed using the Langmuir binding theory for the description of the equilibrium surface coverage as a function of the bulk (analyte) concentration. The obtained binding coefficients for BSA are found to be same as in results from literature, hence confirming the applicability of the devices. The FETs used in the experiments were fabricated using wet-chemically synthesized graphene, displaying high electron and hole mobility (µ) and provide the strong sensitivity also for low potential changes (by change of pH, ion concentration, or molecule adsorption). The binding coefficient for BSA-anti-BSA interaction shows a behavior corresponding to the Langmuir adsorption theory with a Limit of Detection (LOD) in the picomolar concentration range. The presented approach shows high reproducibility and sensitivity and a good agreement of the experimental results with the calculated data.

  19. Detangling extrinsic and intrinsic hysteresis for detecting dynamic switch of electric dipoles using graphene field-effect transistors on ferroelectric gates

    Science.gov (United States)

    Ma, Chunrui; Gong, Youpin; Lu, Rongtao; Brown, Emery; Ma, Beihai; Li, Jun; Wu, Judy

    2015-11-01

    A transition in source-drain current vs. back gate voltage (ID-VBG) characteristics from extrinsic polar molecule dominant hysteresis to anti-hysteresis induced by an oxygen deficient surface layer that is intrinsic to the ferroelectric thin films has been observed on graphene field-effect transistors on Pb0.92La0.08Zr0.52Ti0.48O3 gates (GFET/PLZT-Gate) during a vacuum annealing process developed to systematically remove the polar molecules adsorbed on the GFET channel surface. This allows the extrinsic and intrinsic hysteresis on GFET/PLZT-gate devices to detangle and the detection of the dynamic switch of electric dipoles using GFETs, taking advantage of their high gating efficiency on ferroelectric gate. A model of the charge trapping and pinning mechanism is proposed to successfully explain the transition. In response to pulsed VBG trains of positive, negative, as well as alternating polarities, respectively, the source-drain current ID variation is instantaneous with the response amplitude following the ID-VBG loops measured by DC VBG with consideration of the remnant polarization after a given VBG pulse when the gate electric field exceeds the coercive field of the PLZT. A detection sensitivity of around 212 dipole per μm2 has been demonstrated at room temperature, suggesting the GFET/ferroelectric-gate devices provide a promising high-sensitivity scheme for uncooled detection of electrical dipole dynamic switch.A transition in source-drain current vs. back gate voltage (ID-VBG) characteristics from extrinsic polar molecule dominant hysteresis to anti-hysteresis induced by an oxygen deficient surface layer that is intrinsic to the ferroelectric thin films has been observed on graphene field-effect transistors on Pb0.92La0.08Zr0.52Ti0.48O3 gates (GFET/PLZT-Gate) during a vacuum annealing process developed to systematically remove the polar molecules adsorbed on the GFET channel surface. This allows the extrinsic and intrinsic hysteresis on GFET/PLZT-gate

  20. Research Progress of Floating Gate Type Organic Nonvolatile Memories%浮栅型有机非易失性存储器的研究

    Institute of Scientific and Technical Information of China (English)

    陆旭兵; 邵亚云; 刘俊明

    2013-01-01

    有机柔性电子器件具有低制造成本、大面积、可柔性折叠等优点,是近年来国内外学术界和工业界的研究热点。有机非易失存储器是一种重要的有机柔性电子器件。介绍了浮栅型有机非易失性存储器件的工作原理;综述了国内外学术界对浮栅型有机非易失性存储器的研究进展、存在的问题及解决对策。%The organic electron devices have been widely investigated in both academia and industry due to their advantages of low cost , large area , and flexibility etc .The organic nonvolatile memory is one of the important or-ganic devices .In this paper , we will first explain the working principles of the floating gate type organic nonvolatile memory.Then we will introduce some recent progresses of the floating gate organic nonvolatile memories .Finally the existing challenges and possible solutions for their low voltage , high reliability operations were discussed .

  1. An anti-ferroelectric gated Landau transistor to achieve sub-60 mV/dec switching at low voltage and high speed

    Science.gov (United States)

    Karda, Kamal; Jain, Ankit; Mouli, Chandra; Alam, Muhammad Ashraful

    2015-04-01

    Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the classical gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate that a FET integrated with 10 nm HfO2-based anti-ferroelectric and FE hetero stack would achieve ultralow S with ON-current ( Io n) at par with classical transistors at significantly lower voltage and would simplify integration. Our results address the well-known challenges/criticisms of classical Landau transistors, thereby, making them technology relevant for modern ICs.

  2. Extended-gate field-effect transistor packed in micro channel for glucose, urea and protein biomarker detection.

    Science.gov (United States)

    Lin, Yen-Heng; Chu, Chih-Pin; Lin, Chen-Fu; Liao, Hsin-Hao; Tsai, Hann-Huei; Juang, Ying-Zong

    2015-12-01

    This study developed a packaging method to integrate the extended-gate field-effect transistor (EGFET) into a microfluidic chip as a biological sensor. In addition, we present two immobilization approaches for the bio-recognition that are appropriate to this chip, allowing it to measure the concentrations of hydrogen ions, glucose, urea, and specific proteins in a solution. Alginate-calcium microcubes were used to embed the enzymes and magnetic powder (enzyme carrier). When the sensing chip needs the enzyme for the catalytic reaction, the alginate microcubes containing the corresponding enzymes enter through the flow channel and are immobilized on the EGFET surface with an external magnet. High sensing performance of the chip is achieved, with 37.45 mV/mM for measuring hydrogen ions at pH 6-8 with a linearity of 0.9939, 7.00 mV/mM for measuring glucose with a linearity of 0.9962, and 8.01 mV/mM for measuring urea with a linearity of 0.9809. In addition, based on the principle of the immunoassay, the magnetic beads with the specific antibody were used to capture the target protein in the sample. Then, negatively charged DNA fragments bound to a secondary antibody were used to amplify the signal for EGFET measurement. The magnetic beads with completed immune response bonding were then fixed on the surface of the sensor by an external magnetic field. Therefore, the measured object can directly contact the sensor surface, and quantitative detection of the protein concentration can be achieved. Apolipoprotein A1 (APOA1) was detected as a target protein, with a minimum detection limit of approximately 12.5 ng/mL.

  3. Recent Progress of Ferroelectric-Gate Field-Effect Transistors and Applications to Nonvolatile Logic and FeNAND Flash Memory

    Directory of Open Access Journals (Sweden)

    Mitsue Takahashi

    2010-11-01

    Full Text Available We have investigated ferroelectric-gate field-effect transistors (FeFETs with Pt/SrBi2Ta2O9/(HfO2x(Al2O31−x (Hf-Al-O and Pt/SrBi2Ta2O9/HfO2 gate stacks. The fabricated FeFETs have excellent data retention characteristics: The drain current ratio between the on- and off-states of a FeFET was more than 2 × 106 after 12 days, and the decreasing rate of this ratio was so small that the extrapolated drain current ratio after 10 years is larger than 1 × 105. A fabricated self-aligned gate Pt/SrBi2Ta2O9/Hf-Al-O/Si FET revealed a sufficiently large drain current ratio of 2.4 × 105 after 33.5 day, which is 6.5 × 104 after 10 years by extrapolation. The developed FeFETs also revealed stable retention characteristics at an elevated temperature up to 120 °C and had small transistor threshold voltage (Vth distribution. The Vth can be adjusted by controlling channel impurity densities for both n-channel and p-channel FeFETs. These performances are now suitable to integrated circuit application with nonvolatile functions. Fundamental properties for the applications to ferroelectric-CMOS nonvolatile logic-circuits and to ferroelectric-NAND flash memories are demonstrated.

  4. Origin of mobility enhancement by chemical treatment of gate-dielectric surface in organic thin-film transistors: Quantitative analyses of various limiting factors in pentacene thin films

    Science.gov (United States)

    Matsubara, R.; Sakai, Y.; Nomura, T.; Sakai, M.; Kudo, K.; Majima, Y.; Knipp, D.; Nakamura, M.

    2015-11-01

    For the better performance of organic thin-film transistors (TFTs), gate-insulator surface treatments are often applied. However, the origin of mobility increase has not been well understood because mobility-limiting factors have not been compared quantitatively. In this work, we clarify the influence of gate-insulator surface treatments in pentacene thin-film transistors on the limiting factors of mobility, i.e., size of crystal-growth domain, crystallite size, HOMO-band-edge fluctuation, and carrier transport barrier at domain boundary. We quantitatively investigated these factors for pentacene TFTs with bare, hexamethyldisilazane-treated, and polyimide-coated SiO2 layers as gate dielectrics. By applying these surface treatments, size of crystal-growth domain increases but both crystallite size and HOMO-band-edge fluctuation remain unchanged. Analyzing the experimental results, we also show that the barrier height at the boundary between crystal-growth domains is not sensitive to the treatments. The results imply that the essential increase in mobility by these surface treatments is only due to the increase in size of crystal-growth domain or the decrease in the number of energy barriers at domain boundaries in the TFT channel.

  5. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Naquin, Clint; Lee, Mark [Department of Physics, University of Texas at Dallas, Richardson, Texas 75080 (United States); Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken [Texas Instruments Inc., Richardson, Texas 75243 (United States)

    2015-09-28

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (V{sub G}) spacing between NDTCs. The V{sub G} spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  6. Design of a reversible single precision floating point subtractor.

    Science.gov (United States)

    Anantha Lakshmi, Av; Sudha, Gf

    2014-01-04

    In recent years, Reversible logic has emerged as a major area of research due to its ability to reduce the power dissipation which is the main requirement in the low power digital circuit design. It has wide applications like low power CMOS design, Nano-technology, Digital signal processing, Communication, DNA computing and Optical computing. Floating-point operations are needed very frequently in nearly all computing disciplines, and studies have shown floating-point addition/subtraction to be the most used floating-point operation. However, few designs exist on efficient reversible BCD subtractors but no work on reversible floating point subtractor. In this paper, it is proposed to present an efficient reversible single precision floating-point subtractor. The proposed design requires reversible designs of an 8-bit and a 24-bit comparator unit, an 8-bit and a 24-bit subtractor, and a normalization unit. For normalization, a 24-bit Reversible Leading Zero Detector and a 24-bit reversible shift register is implemented to shift the mantissas. To realize a reversible 1-bit comparator, in this paper, two new 3x3 reversible gates are proposed The proposed reversible 1-bit comparator is better and optimized in terms of the number of reversible gates used, the number of transistor count and the number of garbage outputs. The proposed work is analysed in terms of number of reversible gates, garbage outputs, constant inputs and quantum costs. Using these modules, an efficient design of a reversible single precision floating point subtractor is proposed. Proposed circuits have been simulated using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3. The total on-chip power consumed by the proposed 32-bit reversible floating point subtractor is 0.410 W.

  7. Improvement in performance of solution-processed indium-zinc-tin oxide thin-film transistors by UV/O3 treatment on zirconium oxide gate insulator

    Science.gov (United States)

    Naik, Bukke Ravindra; Avis, Christophe; Delwar Hossain Chowdhury, Md; Kim, Taehun; Lin, Tengda; Jang, Jin

    2016-03-01

    We studied solution-processed amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs) with spin-coated zirconium oxide (ZrOx) as the gate insulator. The ZrOx gate insulator was used without and with UV/O3 treatment. The TFTs with an untreated ZrOx gate dielectric showed a saturation mobility (μsat) of 0.91 ± 0.29 cm2 V-1 s-1, a threshold voltage (Vth) of 0.28 ± 0.36 V, a subthreshold swing (SS) of 199 ± 37.17 mV/dec, and a current ratio (ION/IOFF) of ˜107. The TFTs with a UV/O3-treated ZrOx gate insulator exhibited μsat of 2.65 ± 0.43 cm2 V-1 s-1, Vth of 0.44 ± 0.35 V, SS of 133 ± 24.81 mV/dec, and ION/IOFF of ˜108. Hysteresis was 0.32 V in the untreated TFTs and was eliminated by UV/O3 treatment. Also, the leakage current decreased significantly when the IZTO TFT was coated onto a UV/O3-treated ZrOx gate insulator.

  8. Electrical characteristics of top contact pentacene organic thin film transistors with SiO2 and poly(methyl methacrylate) as gate dielectrics

    Indian Academy of Sciences (India)

    Jaya Lohani; Praveen Saho; Upender Kumar; V R Balakrishnan; P K Basu

    2008-09-01

    Organic thin film transistors (OTFTs) were fabricated using pentacene as the active layer with two different gate dielectrics, namely SiO2 and poly(methyl methacrylate) (PMMA), in top contact geometry for comparative studies. OTFTs with SiO2 as dielectric and gold deposited on the rough side of highly doped silicon (n+ -Si) as gate electrode exhibited reasonable field effect mobilities. To deal with poor stability and large leakage currents between source/drain and gate electrodes in these devices, isolated OTFTs with reduced source/drain contact area were fabricated by selective deposition of pentacene on SiO2/PMMA through shadow mask. This led to almost negligible leakage currents and no degradation in electrical performance even after 14 days of storage under ambient conditions. But, the field effect mobilities obtained were lower than 10-3 cm2 V-1 s-1, whereas by using PMMA as gate dielectric with chromium deposited on the polished side of n+ -Si as gate electrode, improved field effect mobilities (> 0.02 cm2 V-1 s-1) were obtained. PMMA-based OTFTs also exhibited lower leakage currents and reproducible output characteristics even after 30 days of storage under ambient conditions.

  9. Characterization of Al2O3/GaN/AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with different gate recess depths

    Institute of Scientific and Technical Information of China (English)

    Ma Xiao-Hua; Pan Cai-Yuan; Yang Li-Yuan; Yu Hui-You; Yang Ling; Quan Si; Wang Hao; Zhang Jin-Cheng; Hao Yue

    2011-01-01

    In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal-insulator-semiconductor (MIS) high electron mobility transistors (HEMTs), we demonstrate better performances of recessed-gate Al2O3 MIS-HEMTs which are fabricated by Fluorine-based Si3N4 etching and chlorinebased AlGaN etching with three etching times (15 s, 17 s and 19 s). The gate leakage current of MIS-HEMT is about three orders of magnitude lower than that of AlGaN/GaN HEMT. Through the recessed-gate etching, the transconductance increases effectively. When the recessed-gate depth is 1.02 nm, the best interface performance with γit=(0.20-1.59) μs and Dit=(0.55-1.08)×1012 cm-2·eV-1 can be obtained. After chlorine-based etching, the interface trap density reduces considerably without generating any new type of trap. The accumulated chlorine ions and the N vacancies in the AlGaN surface caused by the plasma etching can degrade the breakdown and the high frequency performances of devices. By comparing the characteristics of recessed-gate MIS-HEMTs with different etching times, it is found that a low power chlorine-based plasma etching for a short time (15 s in this paper) can enhance the performances of MIS-HEMTs effectively.

  10. Enhancement of the saturation mobility in a ferroelectric-gated field-effect transistor by the surface planarization of ferroelectric film

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Woo Young, E-mail: semigumi@kaist.ac.kr [Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of); Jeon, Gwang-Jae; Kang, In-Ku; Shim, Hyun Bin; Lee, Hee Chul [Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)

    2015-09-30

    Ferroelectricity refers to the property of a dielectric material to undergo spontaneous polarization which originates from the crystalline phase. Hence, ferroelectric materials have a certain degree of surface roughness when they are formed as a thin film. A high degree of surface roughness may cause unintended phenomena when the ferroelectric material is used in electronic devices. Specifically, the quality of subsequently deposited film could be affected by the rough surface. The present study reports that the surface roughness of ferroelectric polymer film can be reduced by a double-spin-coating method of a solution, with control of the solubility of the solution. At an identical thickness of 350 nm, double-spin-coated ferroelectric film has a root-mean-square roughness of only 3 nm, while for single-spin-coated ferroelectric film this value is approximately 16 nm. A ferroelectric-gated field-effect transistor was fabricated using the proposed double-spin-coating method, showing a maximum saturation mobility as much as seven-fold than that of a transistor fabricated with single-spin-coated ferroelectric film. The enhanced saturation mobility could be explained by the Poole–Frenkel conduction mechanism. The proposed method to reduce the surface roughness of ferroelectric film would be useful for high performance organic electronic devices, including crystalline-phase dielectric film. - Highlights: • Single and double-layer solution-processed polymer ferroelectric films were obtained. • Adjusting the solvent solubility allows making double-layer ferroelectric (DF) films. • The DF film has a smoother surface than single-layer ferroelectric (SF) film. • DF-gated transistor has faster saturation mobility than SF-based transistor. • Solvent solubility adjustment led to higher performance organic devices.

  11. Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

    Science.gov (United States)

    Veloso, Anabela; Aik Chew, Soon; Higuchi, Yuichi; Ragnarsson, Lars-Åke; Simoen, Eddy; Schram, Tom; Witters, Thomas; Van Ammel, Annemie; Dekkers, Harold; Tielens, Hilde; Devriendt, Katia; Heylen, Nancy; Sebaai, Farid; Brus, Stephan; Favia, Paola; Geypen, Jef; Bender, Hugo; Phatak, Anup; Chen, Michael S.; Lu, Xinliang; Ganguli, Seshadri; Lei, Yu; Tang, Wei; Fu, Xinyu; Gandikota, Srinivas; Noori, Atif; Brand, Adam; Yoshida, Naomi; Thean, Aaron; Horiguchi, Naoto

    2013-04-01

    This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

  12. Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

    Science.gov (United States)

    Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

    2013-01-01

    Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

  13. Gate voltage and drain current stress instabilities in amorphous In–Ga–Zn–O thin-film transistors with an asymmetric graphene electrode

    Directory of Open Access Journals (Sweden)

    Joonwoo Kim

    2015-09-01

    Full Text Available The gate voltage and drain current stress instabilities in amorphous In–Ga–Zn–O thin-film transistors (a-IGZO TFTs having an asymmetric graphene electrode structure are studied. A large positive shift in the threshold voltage, which is well fitted to a stretched-exponential equation, and an increase in the subthreshold slope are observed when drain current stress is applied. This is due to an increase in temperature caused by power dissipation in the graphene/a-IGZO contact region, in addition to the channel region, which is different from the behavior in a-IGZO TFTs with a conventional transparent electrode.

  14. High power terahertz emission from a single gate AlGaN/GaN field effect transistor with periodic Ohmic contacts for plasmon coupling

    Science.gov (United States)

    Onishi, Toshikazu; Tanigawa, Tatsuya; Takigawa, Shinichi

    2010-08-01

    We report on room temperature terahertz (THz) emission by a single, short gate AlGaN/GaN field effect transistor with grating Ohmic contacts. The fingers of metal contacts are fabricated at the nanoscale in length and spacing in order to work as a radiation coupler of electron plasmons in the THz range. Spectrum analysis revealed a broadband emission centered at 1.5 THz with a controlled polarization by the grating contacts. The measured output power is linearly increased with the drain input power and reached up to 1.8 μW.

  15. Dual Metal/High-k Gate-Last Complementary Metal-Oxide-Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

    Science.gov (United States)

    Kikuchi, Yoshiaki; Wakabayashi, Hitoshi; Tsukamoto, Masanori; Nagashima, Naoki

    2011-08-01

    For the first time, dual metal/high-k gate-last complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal-oxide-semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal-oxide-semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

  16. Low-frequency noise in amorphous indium-gallium-zinc oxide thin-film transistors with an inverse staggered structure and an SiO2 gate insulator

    Science.gov (United States)

    Park, Jae Chul; Lee, Ho-Nyeon

    2014-05-01

    We report the low-frequency noise (LFN) behavior of amorphous indium-gallium-zinc oxide thin-film transistors with an inverse staggered structure and an SiO2 gate insulator. The normalized noise power spectral density depended on channel length, L, with the form 1/L2, and on the gate bias voltage, VG, and threshold voltage, VTH, with the form 1/(VG - VTH)β where 1.5 < β < 2.1. In addition, the scattering constant α was less than 105 Ω. These results suggest that the contact resistance has a significant role in the LFN behavior and the charge-carrier density fluctuation is the dominant origin of LFN.

  17. Paraffin wax passivation layer improvements in electrical characteristics of bottom gate amorphous indium-gallium-zinc oxide thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Chang, Geng-Wei [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsin-Chu, 300, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Physics and Center for Nanoscience and Nanotechnology, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung, Taiwan (China); Syu, Yong-En [Department of Physics and Center for Nanoscience and Nanotechnology, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung, Taiwan (China); Tsai, Tsung-Ming; Chang, Kuan-Chang [Institute of Materials Science and Engineering, National Sun Yat-Sen University, Kaohsiung, 70 Lien-hai Road, Kaohsiung, 804, Taiwan (China); Tu, Chun-Hao [Institute of Electronics, National Chiao Tung University, Hsin-Chu, 300, Taiwan (China); Jian, Fu-Yen [Department of Physics and Center for Nanoscience and Nanotechnology, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung, Taiwan (China); Hung, Ya-Chi [Institute of Materials Science and Engineering, National Sun Yat-Sen University, Kaohsiung, 70 Lien-hai Road, Kaohsiung, 804, Taiwan (China); Tai, Ya-Hsiang [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsin-Chu, 300, Taiwan (China)

    2011-12-30

    In this research, paraffin wax is employed as the passivation layer of the bottom gate amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs), and it is formed by sol-gel process in the atmosphere. The high yield and low cost passivation layer of sol-gel process technology has attracted much attention for current flat-panel-display manufacturing. Comparing with passivation-free a-IGZO TFTs, passivated devices exhibit a superior stability against positive gate bias stress in different ambient gas, demonstrating that paraffin wax shows gas-resisting characteristics for a-IGZO TFTs application. Furthermore, light-induced stretch-out phenomenon for paraffin wax passivated device is suppressed. This superior stability of the passivated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities.

  18. Effect of gate-length shortening on the terahertz small-signal and self-oscillations characteristics of field-effect transistors

    Science.gov (United States)

    Starikov, E.; Shiktorov, P.; Gružinskis, V.; Marinchio, H.; Palermo, C.; Varani, L.

    2015-12-01

    We investigate the shortening of the gate-length in submicrometric and nanometric field-effect transistors as a powerful tool to improve their self-oscillations performances in the terahertz frequency region due to the appearance of the Dyakonov-Shur instability. The theoretical model is based on the numerical solution of hydrodynamic equations for the electron transport in FETs/HEMTs channels. We show that a decrease of the gate length allows, on the one hand, to increase the intrinsic resonant frequencies near 1 THz and, on the other hand, to improve the conditions for the onset of the Dyakonov-Shur instability and related phenomena. The small-signal characteristics calculated under constant drain-voltage operation are compared with the drain-voltage self-oscillations calculated under constant drain-current operation.

  19. Bottom-gate poly-Si thin-film transistors by nickel silicide seed-induced lateral crystallization with self-aligned lightly doped layer

    Science.gov (United States)

    Lee, Sol Kyu; Seok, Ki Hwan; Chae, Hee Jae; Lee, Yong Hee; Han, Ji Su; Jo, Hyeon Ah; Joo, Seung Ki

    2017-03-01

    We report a novel method to reduce source and drain (S/D) resistances, and to form a lightly doped layer (LDL) of bottom-gate polycrystalline silicon (poly-Si) thin-film transistors (TFTs). For application in driving TFTs, which operate under high drain voltage condition, poly-Si TFTs are needed in order to attain reliability against hot-carriers as well as high field-effect mobility (μFE). With an additional doping on the p+ Si layer, sheet resistance on S/D was reduced by 37.5% and an LDL was introduced between the channel and drain. These results contributed to not only a lower leakage current and gate-induced drain leakage, but also high immunity of kink-effect and hot-carrier stress. Furthermore, the measured electrical characteristics exhibited a steep subthreshold slope of 190 mV/dec and high μFE of 263 cm2/Vs.

  20. Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

    Science.gov (United States)

    Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

    2016-01-26

    Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

  1. Radiation-hardened transistor and integrated circuit

    Science.gov (United States)

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  2. Improvement in reliability of amorphous indium-gallium-zinc oxide thin-film transistors with Teflon/SiO2 bilayer passivation under gate bias stress

    Science.gov (United States)

    Fan, Ching-Lin; Tseng, Fan-Ping; Li, Bo-Jyun; Lin, Yu-Zuo; Wang, Shea-Jue; Lee, Win-Der; Huang, Bohr-Ran

    2016-02-01

    The reliability of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with Teflon/SiO2 bilayer passivation prepared under positive and negative gate bias stresses (PGBS and NGBS, respectively) was investigated. Heavier electrical degradation was observed under PGBS than under NGBS, indicating that the environmental effects under PGBS are more evident than those under NGBS. The device with bilayer passivation under PGBS shows two-step degradation. The positive threshold voltage shifts during the initial stressing period (before 500 s), owing to the charges trapped in the gate insulator or at the gate insulator/a-IGZO active layer interface. The negative threshold voltage shift accompanies the increase in subthreshold swing (SS) for the continuous stressing period (after 500 s) owing to H2O molecules from ambience diffused within the a-IGZO TFTs. It is believed that Teflon/SiO2 bilayer passivation can effectively improve the reliability of the a-IGZO TFTs without passivation even though the devices are stressed under gate bias.

  3. Self-aligned metal double-gate junctionless p-channel low-temperature polycrystalline-germanium thin-film transistor with thin germanium film on glass substrate

    Science.gov (United States)

    Hara, Akito; Nishimura, Yuya; Ohsawa, Hiroki

    2017-03-01

    Low-temperature (LT) polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) are viable contenders for use in the backplanes of flat-panel displays and in systems-on-glass because of their superior electrical properties compared with silicon and oxide semiconductors. However, LT poly-Ge shows strong p-type characteristics. Therefore, it is not easy to reduce the leakage current using a single-gate structure such as a top-gate or bottom-gate structure. In this study, self-aligned planar metal double-gate p-channel junctionless LT poly-Ge TFTs are fabricated on a glass substrate using a 15-nm-thick solid-phase crystallized poly-Ge film and aluminum-induced lateral metallization source-drain regions (Al-LM-SD). A nominal field-effect mobility of 19 cm2 V-1 s-1 and an on/off ratio of 2 × 103 were obtained by optimizing the Al-LM-SD on a glass substrate through a simple, inexpensive LT process.

  4. Using in-process measurements of open-gate structures to evaluate threshold voltage of normally-off GaN-based high electron mobility transistors

    Energy Technology Data Exchange (ETDEWEB)

    Hou, Bin; Ma, Xiao-Hua, E-mail: xhma@xidian.edu.cn, E-mail: yhao@xidian.edu.cn; Chen, Wei-Wei; Zhu, Jie-Jie; Xie, Yong [School of Advanced Materials and Nanotechnology, Xidian University, Xi' an 710071 (China); Key Lab of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China); Zhao, Sheng-Lei; Chen, Yong-He; Zhang, Jin-Cheng; Hao, Yue, E-mail: xhma@xidian.edu.cn, E-mail: yhao@xidian.edu.cn [Key Lab of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China)

    2015-10-19

    The parameters of open-gate structures treated with different etching time were monitored during the gate recess process, and their impacts on the threshold voltage (V{sub th}) of final fabricated AlGaN/GaN high electron mobility transistors (HEMTs) based on open-gate structures were discussed in this paper. It is found that V{sub th} can exceed 0 V when channel resistance in the recessed region (R{sub on-open}) increases over ∼275 Ω mm, maximum current (I{sub Dmax}) decreases below ∼29 mA/mm, or recessed barrier thickness (t{sub RB}) is below ∼7.5 nm. In addition, t{sub RB} obtained by atomic force microscopy measurements and C-V measurements are also compared. Finally, theoretical common criteria based on the experimental results of this work for t{sub RB} and R{sub on-open} were established to evaluate the V{sub th} of a regular normally-off AlGaN/GaN HEMTs. The results indicate that these parameters of open-gate structure can be utilized to achieve normally-off HEMTs with controllable V{sub th}.

  5. Investigation of gate-diode degradation in normally-off p-GaN/AlGaN/GaN high-electron-mobility transistors

    Energy Technology Data Exchange (ETDEWEB)

    Ťapajna, M., E-mail: milan.tapajna@savba.sk; Kuzmík, J. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, 841 04 Bratislava (Slovakia); Hilt, O.; Bahat-Treidel, E.; Würfl, J. [Ferdinand-Braun-Institut, Leibniz Institut für Höchstfrequenztechnik, Gustav-Kirchhoff-Strasse 4, 12489 Berlin (Germany)

    2015-11-09

    Gate diode conduction mechanisms were analyzed in normally-off p-GaN/AlGaN/GaN high-electron mobility transistors grown on Si wafers before and after forward bias stresses. Electrical characterization of the gate diodes indicates forward current to be limited by channel electrons injected through the AlGaN/p-GaN triangular barrier promoted by traps. On the other hand, reverse current was found to be consistent with carrier generation-recombination processes in the AlGaN layer. Soft breakdown observed after ∼10{sup 5 }s during forward bias stress at gate voltage of 7 V was attributed to formation of conductive channel in p-GaN/AlGaN gate stack via trap generation and percolation mechanism, likely due to coexistence of high electric field and high forward current density. Possible enhancement of localized conductive channels originating from spatial inhomogeneities is proposed to be responsible for the degradation.

  6. Investigation of light doping and hetero gate dielectric carbon nanotube tunneling field-effect transistor for improved device and circuit-level performance

    Science.gov (United States)

    Wang, Wei; Sun, Yuan; Wang, Huan; Xu, Hongsong; Xu, Min; Jiang, Sitao; Yue, Gongshu

    2016-03-01

    We perform a comparative study (both for device and circuit simulations) of three carbon nanotube tunneling field-effect transistor (CNT-TFET) designs: high-K gate dielectric TFETs (HK-TFETs), hetero gate dielectric TFETs (HTFETs) and a novel CNT-TFET-based combination of light doping and hetero gate dielectric TFETs (LD-HTFETs). At device level, the effects of channel and gate dielectric engineering on the switching and high-frequency characteristics for CNT-TFET have been theoretically investigated using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green’s functions solved self-consistently with Poisson’s equations. It is revealed that the proposed LD-HTFET structure can significantly reduce leakage current, enhance control ability of the gate on the channel, improve the switching speed, and is more suitable for use in low-power, high-frequency circuits. At circuit level, using HSPICE with look-up table-based Verilog-A models, the performance and reliability of CNT-TFET logic gate circuits is evaluated on the basis of power consumption, average delay, stability, energy consumption and power-delay product (PDP). Simulation results indicate that, compared to a traditional CNT-TFET-based circuit, the one based on LD-HTFET has a significantly better performance (static noise margin, energy, delay, PDP). It is also observed that our proposed design exhibits better robustness under different operational conditions by considering power supply voltage and temperature variations. Our results may be useful for designing and optimizing CNTFET devices and circuits.

  7. Preliminary results on low power sigmoid neuron transistor response in 28 nm high-k metal gate Fully Depleted SOI technology

    Science.gov (United States)

    Galy, Ph.; Dehan, P.; Jimenez, J.; Heitz, B.

    2013-11-01

    The purpose of this paper is to describe a preliminary approach to achieve a sigmoid neuron transistor response using the 28 nm high-k metal gate Fully Depleted SOI (FDSOI) technology. It is well known that a neural network is an ambitious way to handle signal and/or data flow. Of interest also is the 'learning phase' of the proposed structure. However, the major difficulty of such structures, where the elementary device is a "Neuron Design (ND)" is in their integration. The elementary ND is based upon a circuit with at least ten interconnected CMOS transistors in order to obtain a sigmoid response activation function (in this example) with multiple inputs typically as per the McCulloch and Pitts model. Given that a large number of NDs are required to build an Artificial Neural Network (ANN), the power consumption of such a structure is a key topic that is also addressed. Another open question concerns the dispersion response due to process variability. This study reports on a new single undoped Formal Neuron Transistor (NT) solution.

  8. Low voltage and high ON/OFF ratio field-effect transistors based on CVD MoS2 and ultra high-k gate dielectric PZT.

    Science.gov (United States)

    Zhou, Changjian; Wang, Xinsheng; Raju, Salahuddin; Lin, Ziyuan; Villaroman, Daniel; Huang, Baoling; Chan, Helen Lai-Wa; Chan, Mansun; Chai, Yang

    2015-05-21

    MoS2 and other atomic-level thick layered materials have been shown to have a high potential for outperforming Si transistors at the scaling limit. In this work, we demonstrate a MoS2 transistor with a low voltage and high ON/OFF ratio. A record small equivalent oxide thickness of ∼1.1 nm has been obtained by using ultra high-k gate dielectric Pb(Zr0.52Ti0.48)O3. The low threshold voltage (swing of 85.9 mV dec(-1), the high ON/OFF ratio of ∼10(8) and the negligible hysteresis ensure a high performance of the MoS2 transistor operating at 1 V. The extracted field-effect mobility of 1-10 cm(2) V(-1) s(-1) suggests a high crystalline quality of the CVD-grown MoS2 flakes. The combination of the two-dimensional layered semiconductor and the ultra high-k dielectric may enable the development of low-power electronic applications.

  9. 底栅和顶栅结构全透明氧化锌薄膜晶体管的制备%Fabrication of Bottom-Gate and Top-Gate Transparent ZnO Thin Film Transistors

    Institute of Scientific and Technical Information of China (English)

    张新安; 张景文; 张伟风; 王东; 毕臻; 边旭明; 侯洵

    2008-01-01

    Transparent zinc oxide thin film transistors (ZnO-TFTs) with bottom-gate and top-gate structures were con-structed on 50mm silica glass substrates. The ZnO films were deposited by RF magnetron sputtering and SiO2 films servedas the gate insulator layer. We found that the ZnO-TFTs with bottom-gate structure have better electrical performancethan those with top-gate structure. The bottom-gate ZnO-TFTs operate as an n-channel enhancement mode,which haveclear pinch off and saturation characteristics. The field effect mobility, threshold voltage, and the current on/off rationel depletion mode operation and no saturation characteristics were detected. The electrical difference of the devices maybe due to the different character of the interface between the channel and insulator layers. The two transistors types havehigh transparency in the visible light region.%报道了制备在50mm石英玻璃衬底上的透明氧化锌薄膜晶体管(ZnO-TFT),采用了底栅和顶栅两种结构进行比较.ZnO沟道层由射频磁控溅射方法制备,SiO2薄膜作为栅绝缘层.结果发现底栅结构的ZnO-TFT具有较好的电学性质,该器件工作在n沟道增强模式,具有较好的夹断效应和饱和特性,其场效应迁移率、阈值电压和电流开关比分别为18.4cm2/(V·s),-0.5V和104.顶栅结构的ZnO-TFT则工作在n沟道耗尽模式,没有明显的饱和特征.不同结构ZnO-TFT电学性质的差别可能是由于不同的ZnO/SiO2界面特性所致.两种结构的ZnO-TFT在可见光波段都有很高的光学透过率.

  10. Top-gated chemical vapor deposited MoS{sub 2} field-effect transistors on Si{sub 3}N{sub 4} substrates

    Energy Technology Data Exchange (ETDEWEB)

    Sanne, A.; Ghosh, R.; Rai, A.; Movva, H. C. P.; Sharma, A.; Rao, R.; Mathew, L.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

    2015-02-09

    We report the electrical characteristics of chemical vapor deposited (CVD) monolayer molybdenum disulfide (MoS{sub 2}) top-gated field-effect transistors (FETs) on silicon nitride (Si{sub 3}N{sub 4}) substrates. We show that Si{sub 3}N{sub 4} substrates offer comparable electrical performance to thermally grown SiO{sub 2} substrates for MoS{sub 2} FETs, offering an attractive passivating substrate for transition-metal dichalcogenides (TMD) with a smooth surface morphology. Single-crystal MoS{sub 2} grains are grown via vapor transport process using solid precursors directly on low pressure CVD Si{sub 3}N{sub 4}, eliminating the need for transfer processes which degrade electrical performance. Monolayer top-gated MoS{sub 2} FETs with Al{sub 2}O{sub 3} gate dielectric on Si{sub 3}N{sub 4} achieve a room temperature mobility of 24 cm{sup 2}/V s with I{sub on}/I{sub off} current ratios exceeding 10{sup 7}. Using HfO{sub 2} as a gate dielectric, monolayer top-gated CVD MoS{sub 2} FETs on Si{sub 3}N{sub 4} achieve current densities of 55 μA/μm and a transconductance of 6.12 μS/μm at V{sub tg} of −5 V and V{sub ds} of 2 V. We observe an increase in mobility at lower temperatures, indicating phonon scattering may dominate over charged impurity scattering in our devices. Our results show that Si{sub 3}N{sub 4} is an attractive alternative to thermally grown SiO{sub 2} substrate for TMD FETs.

  11. Anisotropic high-k deposition for gate-last processing of metal-oxide-semiconductor field-effect transistor utilizing electron-cyclotron-resonance plasma sputtering

    Energy Technology Data Exchange (ETDEWEB)

    Kikuchi, Yoshiaki, E-mail: kikuchi.y.ao@m.titech.ac.jp; Gao, Jun; Sano, Takahiro; Ohmi, Shun-ichiro, E-mail: ohmi@ep.titech.ac.jp

    2012-01-31

    A high-k/metal gate structure has been investigated for application to state-of-the-art metal-oxide-semiconductor field-effect transistors. In the high-k/metal gate structure, the 32-nm technology node was realized by using the high-k-last, metal-last integration process. We investigated anisotropic deposition for 3-dimensional gate structures on Si substrates utilizing electron-cyclotron-resonance plasma sputtering to reduce parasitic capacitance. Anisotropic HfN film deposition was realized and the deposition thickness on the side wall was reduced with decreasing sputtering gas pressure, from 0.15 to 0.06 Pa, corresponding to Ar/N{sub 2} flow ratios of 20/1 and 5/1 sccm. The HfSiON gate insulator formed from the anisotropically deposited HfN film showed an equivalent-oxide-thickness of 2.1 nm and a gate leakage of 3.1 Multiplication-Sign 10{sup -6}A/cm{sup 2} at V{sub FB}-1.0. - Highlights: Black-Right-Pointing-Pointer High-k film deposition was controlled by the deposition pressure. Black-Right-Pointing-Pointer The pressure decreases with a reduction of gas flow rate during the high-k film deposition. Black-Right-Pointing-Pointer A flat band voltage shows negative shifts with reduction of gas flow rates. Black-Right-Pointing-Pointer A reason of the flat band voltage shift is an increase in Si-N bonding.

  12. Mechanism Study of Gate Leakage Current for AlGaN/GaN High Electron Mobility Transistor Structure Under High Reverse Bias by Thin Surface Barrier Model and Technology Computer Aided Design Simulation

    Science.gov (United States)

    Hayashi, Kazuo; Yamaguchi, Yutaro; Oishi, Toshiyuki; Otsuka, Hiroshi; Yamanaka, Koji; Nakayama, Masatoshi; Miyamoto, Yasuyuki

    2013-04-01

    Gate leakage current mechanism in GaN high electron mobility transistors (HEMTs) has been studied using a two-dimensional thin surface barrier (TSB) model to represent two unintentional donor thin layers that exit under and outside the gate electrode due to the existence of surface defects. The donor thin layer outside the gate affects the reverse gate current at the high gate voltage above the pinch-off voltage. Higher donor concentration of thin layer outside the gate results in larger ratio of lateral to vertical components of the electric field at the gate edge. On the other hand, the electric field at the center of the gate has only the vertical electric field component. As a result, the two-dimensional effects are only important for the reverse gate current above the pinch-off voltage. We have confirmed in this paper that the simulation results provided by our model correlate very well with the experimental reverse gate current characteristics of the device for a very wide range of reverse gate voltage from 0.1 to 90 V.

  13. Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor

    Directory of Open Access Journals (Sweden)

    Fatima Zohra Rahou

    2016-11-01

    Full Text Available The implementation of high-k gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components. From the simulation result; it was shown that HfO2 is the best dielectric material with metal gate TiN, which giving better subthreshold swing (SS, drain-induced barrier lowing (DIBL, leakage current Ioff and Ion/Ioff ratio.

  14. Lowered operation voltage in Pt/SBi2Ta2O9/HfO2/Si ferroelectric-gate field-effect transistors by oxynitriding Si

    Science.gov (United States)

    Horiuchi, Takeshi; Takahashi, Mitsue; Li, Qiu-Hong; Wang, Shouyu; Sakai, Shigeki

    2010-05-01

    Oxynitrided Si (SiON) surfaces show smaller subthreshold swings than do directly nitrided Si (SiN) surfaces when used in ferroelectric-gate field-effect transistors (FeFETs) having the following stacked-gate structure: Pt/SrBi2Ta2O9(SBT)/HfO2/Si. SiON/Si substrates for FeFETs were prepared by rapid thermal oxidation (RTO) in O2 at 1000 °C and subsequent rapid thermal nitridation (RTN) in NH3 at various temperatures in the range 950-1150 °C. The electrical properties of the Pt/SBT/HfO2/SiON/Si FeFET were compared with those of reference FETs, i.e. Pt/SBT/HfO2 gate stacks formed on Si substrates subjected to various treatments: SiNx/Si formed by RTN, SiO2/Si formed by RTO and untreated Si. The Pt/SBT/HfO2/SiON/Si FeFET had a larger memory window than all the other reference FeFETs, particularly at low operation voltages when the RTN temperature was 1050 °C.

  15. High performance thin film transistor (flex-TFT) with textured nanostructure ZnO film channel fabricated by exploiting electric double layer gate insulator

    Science.gov (United States)

    Ghimire, Rishi Ram; Raychaudhuri, A. K.

    2017-01-01

    We report a flexible thin film transistor (flex-TFT) fabricated on a commonly available polyimide (Kapton®) tape with a channel of highly textured nanocrystalline ZnO film grown by pulsed laser deposition. The flex-TFT with an electric double layer (EDL) gate insulator shows a low threshold for operation (Vth ≤ 1 V), an ON/OFF ratio reaching ≈107 and a subthreshold swing ≈75 mV/dec. The superior performance is enabled by a high saturation mobility (μs ≈ 70 cm2/V s) of the highly textured nanocrystalline channel. The low Vth arises from large charge density (≈1014/cm2) induced into the channel by EDL gate insulator. The large charge density induced by the EDL gate dielectric also enhances the Hall mobility in the film and brings down the sheet resistance by nearly 2 orders, which leads to large ON/OFF ratio. The flex-TFT operation can be sustained with reproducibility when the TFT is bent down to a radius of curvature ≈2 cm.

  16. Thermally oxidized 2D TaS2 as a high-κ gate dielectric for MoS2 field-effect transistors

    Science.gov (United States)

    Chamlagain, Bhim; Cui, Qingsong; Paudel, Sagar; Ming-Cheng Cheng, Mark; Chen, Pai-Yen; Zhou, Zhixian

    2017-09-01

    We report a new approach to integrating high-κ dielectrics in both bottom- and top-gated MoS2 field-effect transistors (FETs) through thermal oxidation and mechanical assembly of layered two-dimensional (2D) TaS2. Combined x-ray photoelectron spectroscopy (XPS), optical microscopy, atomic force microscopy (AFM), and capacitance-voltage (C-V) measurements confirm that multilayer TaS2 flakes can be uniformly transformed to Ta2O5 with a high dielectric constant of ~15.5 via thermal oxidation, while preserving the geometry and ultra-smooth surfaces of 2D TMDs. Top-gated MoS2 FETs fabricated using the thermally oxidized Ta2O5 as gate dielectric demonstrate a high current on/off ratio approaching 106, a subthreshold swing (SS) down to 61 mV/dec, and a field-effect mobility exceeding 60 cm2 V-1 s-1 at room temperature, indicating high dielectric quality and low interface trap density.

  17. Effect of annealing temperature on structural and electrical properties of high-κ YbTixOy gate dielectrics for InGaZnO thin film transistors

    Science.gov (United States)

    Pan, Tung-Ming; Chen, Fa-Hsyang; Hung, Meng-Ning

    2015-01-01

    This paper describes the effect of annealing temperature on the structural properties and electrical characteristics of high-κ YbTixOy gate dielectrics for indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). X-ray diffraction, x-ray photoelectron spectroscopy and atomic force microscopy were used to study the structural, chemical and morphological features, respectively, of these dielectric films annealed at 200, 300 and 400 °C. The YbTixOy IGZO TFT that had been annealed at 400 °C exhibited better electrical characteristics, such as a small threshold voltage of 0.53 V, a large field-effect mobility of 19.1 cm2 V-1 s-1, a high Ion/Ioff ratio of 2.8 × 107, and a low subthreshold swing of 176 mV dec.-1, relative to those of the systems that had been subjected to other annealing conditions. This result suggests that YbTixOy dielectric possesses a higher dielectric constant as well as lower oxygen vacancies (or defects) in the film. In addition, the instability of YbTixOy IGZO TFT was studied under positive gate-bias stress and negative gate-bias stress conditions.

  18. In situ Raman spectroscopy of the graphene/water interface of a solution-gated field-effect transistor: electron-phonon coupling and spectroelectrochemistry.

    Science.gov (United States)

    Binder, J; Urban, J M; Stepniewski, R; Strupinski, W; Wysmolek, A

    2016-01-29

    We present a novel measurement approach which combines the electrical characterization of solution-gated field-effect transistors based on epitaxial bilayer graphene on 4H-SiC (0001) with simultaneous Raman spectroscopy. By changing the gate voltage, we observed Raman signatures related to the resonant electron-phonon coupling. An analysis of these Raman bands enabled the extraction of the geometrical capacitance of the system and an accurate calculation of the Fermi levels for bilayer graphene. An intentional application of higher gate voltages allowed us to trigger electrochemical reactions, which we followed in situ by Raman spectroscopy. The reactions showed a partially reversible character, as indicated by an emergence/disappearance of peaks assigned to C-H and Si-H vibration modes as well as an increase/decrease of the defect-related Raman D band intensity. Our setup provides a highly interesting platform for future spectroelectrochemical research on electrically-induced sorption processes of graphene on the micrometer scale.

  19. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    Science.gov (United States)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  20. Characteristics of cylindrical surrounding-gate GaAs x Sb1-x /In y Ga1-y As heterojunction tunneling field-effect transistors

    Science.gov (United States)

    Guan, Yun-He; Li, Zun-Chao; Luo, Dong-Xu; Meng, Qing-Zhi; Zhang, Ye-Fei

    2016-10-01

    A III-V heterojunction tunneling field-effect transistor (TFET) can enhance the on-state current effectively, and GaAs x Sb1-x /In y Ga1-y As heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition. In this paper, the performance of the cylindrical surrounding-gate GaAs x Sb1-x /In y Ga1-y As heterojunction TFET with gate-drain underlap is investigated by numerical simulation. We validate that reducing drain doping concentration and increasing gate-drain underlap could be effective ways to reduce the off-state current and subthreshold swing (SS), while increasing source doping concentration and adjusting the composition of GaAs x Sb1-x /In y Ga1-y As can improve the on-state current. In addition, the resonant TFET based on GaAs x Sb1-x /In y Ga1-y As is also studied, and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current, respectively, and is much superior to the conventional TFET. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176038 and 61474093), the Science and Technology Planning Project of Guangdong Province, China (Grant No. 2015A010103002), and the Technology Development Program of Shaanxi Province, China (Grant No. 2016GY-075).

  1. Oxide thickness-dependent effects of source doping profile on the performance of single- and double-gate tunnel field-effect transistors

    Science.gov (United States)

    Chien, Nguyen Dang; Shih, Chun-Hsing

    2017-02-01

    Operated by the band-to-band tunneling at the source-channel junction, the source engineering has been considered as an efficient approach to enhance the performance of tunnel field-effect transistors (TFETs). In this paper, we report a new feature that the effects of source doping profile on the performance of single- and double-gate germanium TFETs depend on equivalent oxide thickness (EOT). Based on the numerical simulations, it is shown that the effect of source concentration on the on-current is stronger with decreasing the EOT, particularly in the double-gate configuration due to the higher gate control capability. Importantly, when the EOT is decreased below a certain value, abrupt source-channel junctions are not only unnecessary, but gradual source doping profiles even improve the performance of TFETs because of the increase in vertical tunneling generation. With the continuous trend of scaling EOT, the oxide thickness-dependent effects of source doping profile should be properly considered in designing TFET devices.

  2. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

    Science.gov (United States)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-04-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  3. Maximum frequency of oscillation of 1.3 THz obtained by using an extended drain-side recess structure in 75-nm-gate InAlAs/InGaAs high-electron-mobility transistors

    Science.gov (United States)

    Takahashi, Tsuyoshi; Kawano, Yoichi; Makiyama, Kozo; Shiba, Shoichi; Sato, Masaru; Nakasha, Yasuhiro; Hara, Naoki

    2017-02-01

    A maximum frequency of oscillation (f max) of 1.3 THz was achieved using an extended drain-side recess structure of InAlAs/InGaAs high-electron-mobility transistors (HEMTs), although the gate length was relatively long at 75 nm. The high f max was improved by reducing the drain output conductance (g d). The use of an asymmetric gate recess structure and double-side doping above and below a channel region were effective in reducing g d. Further improvements in transconductance (g m) and g d were achieved by reducing the distance between the source and gate electrodes.

  4. Graphene transistors for bioelectronics

    OpenAIRE

    Hess, Lucas H.; Seifert, Max; Garrido, Jose A.

    2013-01-01

    This paper provides an overview on graphene solution-gated field effect transistors (SGFETs) and their applications in bioelectronics. The fabrication and characterization of arrays of graphene SGFETs is presented and discussed with respect to competing technologies. To obtain a better understanding of the working principle of solution-gated transistors, the graphene-electrolyte interface is discussed in detail. The in-vitro biocompatibility of graphene is assessed by primary neuron cultures....

  5. Low Threshold Voltage and High Mobility N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor Using Hf-Si/HfO2 Gate Stack Fabricated by Gate-Last Process

    Science.gov (United States)

    Ando, Takashi; Hirano, Tomoyuki; Tai, Kaori; Yamaguchi, Shinpei; Yoshida, Shinichi; Iwamoto, Hayato; Kadomura, Shingo; Watanabe, Heiji

    2010-01-01

    Systematic characterization of Hf-Si/HfO2 gate stacks revealed two mobility degradation modes. One is carrier scattering by fixed charges and/or trapped charges induced by the crystallization in the thick HfO2 case (inversion oxide thickness, Tinv> 1.6 nm). The other is the Hf penetration into the interfacial layer with the Si substrate in the thin HfO2 case (Tinv< 1.6 nm) for the Hf-rich electrode. It was demonstrated that careful optimization of the HfO2 thickness and the Hf-Si composition can suppress both modes. As a result, a high electron mobility equivalent to that of n+polycrystalline silicon (poly-Si)/SiO2 (248 cm2 V-1 s-1 at Eeff=1 MV/cm) was obtained at Tinv of 1.47 nm. Moreover, the effective work function of the optimized Hf-Si/HfO2 gate stack is located within 50 mV from the Si band edge (Ec). An extremely high Ion of 1165 µA/µm (at Ioff = 81 nA/µm) at Vdd=1.0 V was demonstrated for a 45 nm gate n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) without strain enhanced technology.

  6. Low-Frequency Noise Characterization of Ultra-shallow Gate N-channel Junction Field Effect Transistors

    NARCIS (Netherlands)

    Piccolo, G.; Sarubbi, F.; Vandamme, L.J.K.; Macucci, M.; Scholtes, T.L.M.; Nanver, L.K.

    2007-01-01

    A recently developed technique for ultra shallow pn junction formation has been applied for the fabrication of ring-gate n-channel junction field effect devices (JFET) devices. Several different geometries, gate formation parameters and channel doping profiles have been realized and characterized wi

  7. Field-Induced Defect Morphology in Ni-gate AlGaN/GaN High Electron Mobility Transistors

    Science.gov (United States)

    2013-07-10

    mobility transistors. VC 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4813535] AlGaN/ GaN high electron mobility transistors ( HEMTs ) remain...interactions could enhance the reliability of AlGaN/ GaN HEMTs by circumventing the defect formation conditions and preventing device degradation...AlGaN/ GaN HEMTs used for this work were all grown on the same semi-insulating 6H-SiC substrate and received the same processing. An AlN nucleation layer

  8. A Novel pH-dependent Drift Improvement Method for Zirconium Dioxide Gated pH-Ion Sensitive Field Effect Transistors

    Directory of Open Access Journals (Sweden)

    Kow-Ming Chang

    2010-05-01

    Full Text Available A novel compensation method for Zirconium dioxide gated Ion Sensitive Field Effect Transistors (ISFETs to improve pH-dependent drift was demonstrated. Through the sequential measurements for both the n-channel and p-channel ISFETs, 75–100% pH-dependent drift could be successfully suppressed for the first seven hours. As a result, a nearly constant drift rate versus pH value was obtained, which increases the accuracy of pH measurements. Meanwhile, the drawback of the hyperbolic-like change with time of the common drift behavior for ISFETs was improved. A state-of-the-art integrated scheme adopting this method was also illustrated.

  9. Thirty-Day-Long Data Retention in Ferroelectric-Gate Field-Effect Transistors with HfO2 Buffer Layers

    Science.gov (United States)

    Takahashi, Kazuhiro; Aizawa, Koji; Park, Byung-Eun; Ishiwara, Hiroshi

    2005-08-01

    Metal-ferroelectric-insulator-semiconductor (MFIS) diodes and p-channel MFIS field-effect transistors (FETs) were fabricated and their electrical properties were characterized. These MFIS structures were formed using HfO2 as an insulating buffer layer, and SrBi2Ta2O9 (SBT) and (Bi,La)4Ti3O12 (BLT) as ferroelectric films. HfO2 buffer layers of about 8 nm physical thickness were deposited by ultrahigh-vacuum (UHV) electron-beam evaporation, then ferroelectric films of about 400 nm thickness were deposited by sol-gel spin coating. The fabricated p-channel MFIS-FETs with the SBT/HfO2 gate structure exhibited a drain current on/off ratio larger than 103 even after 30 days had elapsed. It was also found that the degradation of ferroelectricity was not pronounced even after applying 2.2× 1011 bipolar pulses.

  10. Ultrahigh sensitive sub-terahertz detection by InP-based asymmetric dual-grating-gate high-electron-mobility transistors and their broadband characteristics

    Energy Technology Data Exchange (ETDEWEB)

    Kurita, Y.; Satou, A., E-mail: a-satou@riec.tohoku.ac.jp; Kobayashi, K.; Boubanga Tombet, S.; Suemitsu, T.; Otsuji, T. [Research Institute of Electrical Communication, Tohoku University, 2-1-1 Katahira, Aoba-ku, Sendai 980-8577 (Japan); Ducournau, G. [Institut d' Electronique, de Microélectronique et de Nanotechnologie, 59562 Villeneuve d' Ascq Cedex (France); Coquillat, D.; Knap, W. [Laboratoire Charles Coulomb, UMR 5221, Université Montpellier 2 - CNRS, F-34095 Montpellier (France); Meziani, Y. M. [Departamento de Fisica Aplicada, Universidad de Salamanca, Salamanca 37008 (Spain); Popov, V. V. [Kotelnikov Institute of Radio Engineering and Electronics, 410019 Saratov (Russian Federation)

    2014-06-23

    We report on room-temperature plasmonic detection of sub-terahertz radiation by InAlAs/InGaAs/InP high electron mobility transistors with an asymmetric dual-grating-gate structure. Maximum responsivities of 22.7 kV/W at 200 GHz and 21.5 kV/W at 292 GHz were achieved under unbiased drain-to-source condition. The minimum noise equivalent power was estimated to be 0.48 pW/Hz{sup 0.5} at 200 GHz at room temperature, which is the record-breaking value ever reported for plasmonic THz detectors. Frequency dependence of the responsivity in the frequency range of 0.2–2 THz is in good agreement with the theory.

  11. Influence of source and drain contacts on the properties of the indium-zinc oxide thin-film transistors based on anodic aluminum oxide gate dielectrics

    Science.gov (United States)

    Lan, Linfeng; Xu, Miao; Peng, Junbiao; Xu, Hua; Li, Min; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Wang, Lei; Yao, Rihui

    2011-11-01

    Thin-film transistors (TFTs) based on indium-zinc oxide (IZO) active layer and anodic aluminum oxide (Al2O3) gate dielectric layer were fabricated. The influence of source and drain (S/D) contacts on TFT performance was investigated by comparing IZO-TFTs with different S/D electrodes. The TFT with Mo S/D electrodes had higher output current and lower threshold voltage, but had poorer subthreshold swing and lower effective electron mobility compared to that with ITO S/D electrodes. By using x-ray photoelectron spectroscopy (XPS) depth profile analyzing method, it was observed that Mo was diffusing seriously into IZO, resulting in the variation of the effective channel length, thereby causing serious short-channel effect, poor subshreshold swing, and bad uniformity of the TFTs with Mo S/D electrodes.

  12. AlGaN/GaN high-electron-mobility transistor with distributed gate grown on stripe-patterned Si(111) substrate

    Science.gov (United States)

    Lin, Jyun-Hao; Huang, Shyh-Jer; Lai, Chao-Hsing; Su, Yan-Kuin

    2016-01-01

    We have successfully fabricated an AlGaN/GaN high-electron-mobility transistor with a distributed gate (DG-HEMT) on a stripe-patterned Si substrate. With the help of the stripe pattern, GaN film with low defect density could be deposited by two-step growth. The striped AlGaN/GaN structure could be obtained naturally by stopping the epitaxy process before coalescence. The DG-HEMT fabricated on the striped pattern layout shows good performance. The output characteristics were enhanced from 297 to 337 mA/mm, because the high quality of GaN grown on the patterned substrate can reduce the number of defects. In addition, the drain current was not decreased because the heat problem was reduced in the DG structure.

  13. Controlling of the surface energy of the gate dielectric in organic field-effect transistors by polymer blend

    NARCIS (Netherlands)

    Gao, Jia; Asadi, Kamal; Xu, Jian Bin; An, Jin

    2009-01-01

    In this letter, we demonstrate that by blending insulating polymers, one can fabricate an insulating layer with controllable surface energy for organic field-effect transistors. As a model system, we used copper phthalocyanine evaporated on layers of polymethyl metacrylate blended with polystyrene w

  14. A common gate thin film transistor on poly(ethylene naphthalate) foil using step-and-flash imprint lithography

    NARCIS (Netherlands)

    Moonen, P.F.; Vratzov, B.; Smaal, W.T.T.; Gelinck, G.H.; Peter, M.; Meinders, E.R.; Huskens, J.

    2011-01-01

    In this paper the fabrication of flexible thin film transistors (TFTs) on poly(ethylene naphthalate) foil is reported, with the source-drain layer patterned by step-and-flash imprint lithography (SFIL) as a first step towards fully UV-imprinted TFTs. The semiconductor was deposited by inkjet

  15. Controlling of the surface energy of the gate dielectric in organic field-effect transistors by polymer blend

    NARCIS (Netherlands)

    Gao, Jia; Asadi, Kamal; Xu, Jian Bin; An, Jin

    2009-01-01

    In this letter, we demonstrate that by blending insulating polymers, one can fabricate an insulating layer with controllable surface energy for organic field-effect transistors. As a model system, we used copper phthalocyanine evaporated on layers of polymethyl metacrylate blended with polystyrene w

  16. A common gate thin film transistor on poly(ethylene naphthalate) foil using step-and-flash imprint lithography

    NARCIS (Netherlands)

    Moonen, P.F.; Vratzov, B.; Smaal, W.T.T.; Gelinck, G.H.; Peter, M.; Meinders, E.R.; Huskens, J.

    2011-01-01

    In this paper the fabrication of flexible thin film transistors (TFTs) on poly(ethylene naphthalate) foil is reported, with the source-drain layer patterned by step-and-flash imprint lithography (SFIL) as a first step towards fully UV-imprinted TFTs. The semiconductor was deposited by inkjet printin

  17. Channel length scaling and the impact of metal gate work function on the performance of double gate-metal oxide semiconductor field-effect transistors

    Indian Academy of Sciences (India)

    D Rechem; S Latreche; C Gontrand

    2009-03-01

    In this paper, we study the effects of short channel on double gate MOSFETs. We evaluate the variation of the threshold voltage, the subthreshold slope, the leakage current and the drain-induced barrier lowering when channel length CH decreases. Further- more, quantum effects on the performance of DG-MOSFETs are addressed and discussed. We also study the influence of metal gate work function on the performance of nanoscale MOSFETs. We use a self-consistent Poisson–Schrödinger solver in two dimensions over the entire device. A good agreement with numerical simulation results is obtained.

  18. High-performance enhancement-mode Al2O3/InAlGaN/GaN MOS high-electron mobility transistors with a self-aligned gate recessing technology

    Science.gov (United States)

    Zhang, Kai; Kong, Cen; Zhou, Jianjun; Kong, Yuechan; Chen, Tangsheng

    2017-02-01

    The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

  19. Slowing DNA Translocation in a Nanofluidic Field-Effect Transistor.

    Science.gov (United States)

    Liu, Yifan; Yobas, Levent

    2016-04-26

    Here, we present an experimental demonstration of slowing DNA translocation across a nanochannel by modulating the channel surface charge through an externally applied gate bias. The experiments were performed on a nanofluidic field-effect transistor, which is a monolithic integrated platform featuring a 50 nm-diameter in-plane alumina nanocapillary whose entire length is surrounded by a gate electrode. The field-effect transistor behavior was validated on the gating of ionic conductance and protein transport. The gating of DNA translocation was subsequently studied by measuring discrete current dips associated with single λ-DNA translocation events under a source-to-drain bias of 1 V. The translocation speeds under various gate bias conditions were extracted by fitting event histograms of the measured translocation time to the first passage time distributions obtained from a simple 1D biased diffusion model. A positive gate bias was observed to slow the translocation of single λ-DNA chains markedly; the translocation speed was reduced by an order of magnitude from 18.4 mm/s obtained under a floating gate down to 1.33 mm/s under a positive gate bias of 9 V. Therefore, a dynamic and flexible regulation of the DNA translocation speed, which is vital for single-molecule sequencing, can be achieved on this device by simply tuning the gate bias. The device is realized in a conventional semiconductor microfabrication process without the requirement of advanced lithography, and can be potentially further developed into a compact electronic single-molecule sequencer.

  20. 1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Guo-Neng Lu

    2009-01-01

    Full Text Available We present a single-transistor pixel for CMOS image sensors (CIS. It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

  1. Hysteresis of Electronic Transport in Graphene Transistors

    OpenAIRE

    Wang, Haomin; Wu, Yihong; Cong, Chunxiao; Shang, Jingzhi; Yu, Ting

    2010-01-01

    Graphene field effect transistors commonly comprise graphene flakes lying on SiO2 surfaces. The gate-voltage dependent conductance shows hysteresis depending on the gate sweeping rate/range. It is shown here that the transistors exhibit two different kinds of hysteresis in their electrical characteristics. Charge transfer causes a positive shift in the gate voltage of the minimum conductance, while capacitive gating can cause the negative shift of conductance with respect to gate voltage. The...

  2. Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

    Science.gov (United States)

    Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

    2013-07-23

    Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

  3. Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

    KAUST Repository

    Smith, Casey

    2013-07-23

    Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

  4. Properties of c-axis-aligned crystalline indium-gallium-zinc oxide field-effect transistors fabricated through a tapered-trench gate process

    Science.gov (United States)

    Asami, Yoshinobu; Kurata, Motomu; Okazaki, Yutaka; Higa, Eiji; Matsubayashi, Daisuke; Okamoto, Satoru; Sasagawa, Shinya; Moriwaka, Tomoaki; Kakehata, Tetsuya; Yakubo, Yuto; Kato, Kiyoshi; Hamada, Takashi; Sakakura, Masayuki; Hayakawa, Masahiko; Yamazaki, Shunpei

    2016-04-01

    To achieve both low power consumption and high-speed operation, we fabricated c-axis-aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) field-effect transistors (FETs) with In-rich IGZO and common IGZO (\\text{In}:\\text{Ga}:\\text{Zn} = 1:1:1 in atomic ratio) active layers through a simple process using trench gates, and evaluated their characteristics. The results confirm that 60-nm-node IGZO FETs fabricated through a 450 °C process show an extremely low off-state current below the detection limit (at most 2 × 10-16 A) even at a measurement temperature of 150 °C. The results also reveal that the FETs with the In-rich IGZO active layer show a higher on-state current than those with the common IGZO active layer and have excellent frequency characteristics with a cutoff frequency and a maximum oscillation frequency of up to 20 and 6 GHz, respectively. Thus, we demonstrated that CAAC-IGZO FETs with trench gates are promising for achieving both low power consumption and high-speed operation.

  5. Trap density probing on top-gate MoS₂ nanosheet field-effect transistors by photo-excited charge collection spectroscopy.

    Science.gov (United States)

    Choi, Kyunghee; Raza, Syed Raza Ali; Lee, Hee Sung; Jeon, Pyo Jin; Pezeshki, Atiye; Min, Sung-Wook; Kim, Jin Sung; Yoon, Woojin; Ju, Sang-Yong; Lee, Kimoon; Im, Seongil

    2015-03-19

    Two-dimensional (2D) molybdenum disulfide (MoS₂) field-effect transistors (FETs) have been extensively studied, but most of the FETs with gate insulators have displayed negative threshold voltage values, which indicates the presence of interfacial traps both shallow and deep in energy level. Despite such interface trap issues, reports on trap densities in MoS₂ are quite limited. Here, we probed top-gate MoS₂ FETs with two- (2L), three- (3L), and four-layer (4L) MoS₂/dielectric interfaces to quantify deep-level interface trap densities by photo-excited charge collection spectroscopy (PECCS), and reported the result that deep-level trap densities over 10(12) cm(-2) may exist in the interface and bulk MoS₂ near the interface. Transfer curve hysteresis and PECCS measurements show that shallow traps and deep traps are not that different in density order from each other. We conclude that our PECCS analysis distinguishably provides valuable information on deep level interface/bulk trap densities in 2D-based FETs.

  6. Effect of gate-dielectrics on the electrical characteristics of solution-processed single-wall-carbon-nanotube thin-film transistors

    Science.gov (United States)

    Ha, Tae-Jun

    2017-02-01

    High performance of solution-processed, single-wall-carbon-nanotube (SWCNT) thin-film transistors (TFTs) is investigated through the use in the different gate-dielectrics of silicon dioxide (SiO2), silicon nitride (SiNx), the bilayers of SiO2 and SiNx, and hexagonal boron-nitride (h-BN) thin films. The different interfacial characteristics affect the electrical characteristics of the SWCNT-TFTs including key device metrics. Significantly, the hysteresis window that is normally observed in drop-casted SWCNT-TFTs was majorly suppressed by the employment of a thin lower dielectric-constant material on a higher dielectricconstant material. Sub-2V operating SWCNT-TFTs with solution-processed h-BN gate dielectrics with good above- and sub-threshold characteristics are also investigated on the basis of interfacial characteristics underlying the device physics. Such performance can be realized by the suppressed interfacial impurity scattering through the chemically clean interface combined with optimized solution-process below 100 °C. [Figure not available: see fulltext.

  7. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    Science.gov (United States)

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  8. Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1-xGaxAs channel capping layer

    Science.gov (United States)

    Huang, Cheng-Hao; Li, Yiming

    2015-06-01

    In this work, we study characteristics of 14-nm-gate InGaAs-based trigate MOSFET (metal-oxide-semiconductor field effect transistor) devices with a channel capping layer. The impacts of thickness and gallium (Ga) concentration of the channel capping layer on the device characteristic are firstly simulated and optimized by using three-dimensional quantum-mechanically corrected device simulation. Devices with In1-xGaxAs/In0.53Ga0.47As channels have the large driving current owing to small energy band gap and low alloy scattering at the channel surface. By simultaneously considering various physical and switching properties, a 4-nm-thick In0.68Ga0.32As channel capping layer can be adopted for advanced applications. Under the optimized channel parameters, we further examine the effects of channel fin angle and the work-function fluctuation (WKF) resulting from nano-sized metal grains of NiSi gate on the characteristic degradation and variability. To maintain the device characteristics and achieve the minimal variation induced by WKF, the physical findings of this study indicate a critical channel fin angle of 85o is needed for the device with an averaged grain size of NiSi below 4x4 nm2.

  9. Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

    Directory of Open Access Journals (Sweden)

    Cheng-Hao Huang

    2015-06-01

    Full Text Available In this work, we study characteristics of 14-nm-gate InGaAs-based trigate MOSFET (metal-oxide-semiconductor field effect transistor devices with a channel capping layer. The impacts of thickness and gallium (Ga concentration of the channel capping layer on the device characteristic are firstly simulated and optimized by using three-dimensional quantum-mechanically corrected device simulation. Devices with In1−xGaxAs/In0.53Ga0.47As channels have the large driving current owing to small energy band gap and low alloy scattering at the channel surface. By simultaneously considering various physical and switching properties, a 4-nm-thick In0.68Ga0.32As channel capping layer can be adopted for advanced applications. Under the optimized channel parameters, we further examine the effects of channel fin angle and the work-function fluctuation (WKF resulting from nano-sized metal grains of NiSi gate on the characteristic degradation and variability. To maintain the device characteristics and achieve the minimal variation induced by WKF, the physical findings of this study indicate a critical channel fin angle of 85o is needed for the device with an averaged grain size of NiSi below 4x4 nm2.

  10. 25 GHz embedded-gate graphene transistors with high-k dielectrics on extremely flexible plastic sheets.

    Science.gov (United States)

    Lee, Jongho; Ha, Tae-Jun; Li, Huifeng; Parrish, Kristen N; Holt, Milo; Dodabalapur, Ananth; Ruoff, Rodney S; Akinwande, Deji

    2013-09-24

    Despite the widespread interest in graphene electronics over the past decade, high-performance graphene field-effect transistors (GFETs) on flexible substrates have been rarely achieved, even though this atomic sheet is widely understood to have greater prospects for flexible electronic systems. In this article, we report detailed studies on the electrical and mechanical properties of vapor synthesized high-quality monolayer graphene integrated onto flexible polyimide substrates. Flexible graphene transistors with high-k dielectric afforded intrinsic gain, maximum carrier mobilities of 3900 cm(2)/V·s, and importantly, 25 GHz cutoff frequency, which is more than a factor of 2.5 times higher than prior results. Mechanical studies reveal robust transistor performance under repeated bending, down to 0.7 mm bending radius, whose tensile strain is a factor of 2-5 times higher than in prior studies. In addition, integration of functional coatings such as highly hydrophobic fluoropolymers combined with the self-passivation properties of the polyimide substrate provides water-resistant protection without compromising flexibility, which is an important advancement for the realization of future robust flexible systems based on graphene.

  11. Simulation Study on SOI LDMOS Devices with Floating Gates%浮栅结构SOI LDMOS 器件的模拟研究

    Institute of Scientific and Technical Information of China (English)

    葛梅; 王颖

    2011-01-01

    研究了一种具有浮栅结构的SOI LDMOS (FGSOI LDMOS)器件模型,并分析了该结构的耐压机理,通过Silvaco TCAD软件对该结构进行仿真优化.通过仿真验证可知,该结构通过类场板的结终端技术可以调节器件的横向电场,从而得到比普通SOI LDMOS器件更高的耐压并且降低了器件的比导通电阻.仿真结果表明,该结构与普通SOI LDMOS 器件结构在相同的尺寸条件下耐压提高了41%,比导通电阻降低了21.9%.%An SOI LDMOS device structure with floating gates (FG) was investigated and its breakdown mechanism was analyzed. This structure was proved by Silvaco TCAD software. The simulation results show that the lateral electric field of the device is modulated by the technology of the field plate, the breakdown voltage is increased and the specific on-resistance of the device is decreased.Compared with the normal SOI LDMOS device, the breakdown voltage is increased by 41%, the specific on-resistance of the FG SOl LDMOS is decreased by 21.9% .

  12. Polarization of Bi{sub 2}Te{sub 3} thin film in a floating-gate capacitor structure

    Energy Technology Data Exchange (ETDEWEB)

    Yuan, Hui, E-mail: hyuan@gmu.edu, E-mail: qli6@gmu.edu; Li, Haitao; Zhu, Hao [Department of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia 22030 (United States); Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology, Gaithersburg, Maryland 20899-8120 (United States); Zhang, Kai; Baumgart, Helmut [Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, Virginia 23529 (United States); Bonevich, John E. [Materials Science and Engineering Division, National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States); Richter, Curt A. [Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology, Gaithersburg, Maryland 20899-8120 (United States); Li, Qiliang, E-mail: hyuan@gmu.edu, E-mail: qli6@gmu.edu [Department of Electrical and Computer Engineering, George Mason University, Fairfax, Virginia 22030 (United States)

    2014-12-08

    Metal-Oxide-Semiconductor (MOS) capacitors with Bi{sub 2}Te{sub 3} thin film sandwiched and embedded inside the oxide layer have been fabricated and studied. The capacitors exhibit ferroelectric-like hysteresis which is a result of the robust, reversible polarization of the Bi{sub 2}Te{sub 3} thin film while the gate voltage sweeps. The temperature-dependent capacitance measurement indicates that the activation energy is about 0.33 eV for separating the electron and hole pairs in the bulk of Bi{sub 2}Te{sub 3}, and driving them to either the top or bottom surface of the thin film. Because of the fast polarization speed, potentially excellent endurance, and the complementary metal–oxide–semiconductor compatibility, the Bi{sub 2}Te{sub 3} embedded MOS structures are very interesting for memory application.

  13. Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

    Science.gov (United States)

    Kapoor, V. J.; Shokrani, M.

    1991-01-01

    A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

  14. Silicon on insulator self-aligned transistors

    Science.gov (United States)

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  15. Effect of Reverse Substrate Bias on Degradation of Ultra-Thin Gate-Oxide n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors under Different Stress Modes

    Institute of Scientific and Technical Information of China (English)

    ZHAO Yao; XU Ming-Zhen; TAN Chang-Hua

    2005-01-01

    @@ Degradation of ultra-thin gate-oxide n-channel metal-oxide-semiconductor field-effect transistors with the halo structure has been studied under different stress modes with a reverse substrate bias. The device degradation under the same stress mode with different reverse substrate voltages has been characterized by monitoring the substrate current in a stressing process, which follows a simple power law. When the gate voltage is less than the critical value, the device degradation will first decrease and then increase with the increasing reverse sub strate voltage, otherwise, the device degradation will increase continuously. The critical value can be obtained by measuring the substrate current variation with the increases of reverse substrate voltage and gate voltage. The experimental results indicate that the stress mode with enhanced injection efficiency and smaller device degradation can be obtained when the gate voltage is less than the critical value with a proper reverse substratevoltage chosen.

  16. Improvement on the dynamical performance of a power bipolar static induction transistor with a buried gate structure

    Institute of Scientific and Technical Information of China (English)

    Wang Yongshun; Feng Jingjing; Liu Chunjuan; Wang Zaixing; Zhang Caizhen; Chang Peng

    2011-01-01

    The failure of a bipolar static induction transistor (BSIT) often occurs in the transient process between the conducting-state and the blocking-state,so a profound understanding of the physical mechanism of the switching process is of significance for designing and fabricating perfect devices.The dynamical characteristics of the transient process between conducting-state and blocking-state BSITs are represented in detail in this paper.The influences of material,structural and technological parameters on the dynamical performances of BSITs are discussed.The mechanism underlying the transient conversion process is analyzed in depth.The technological approaches are developed to improve the dynamical characteristics of BSITs.

  17. Thermally deposited Ag-doped CdS thin film transistors with high-k rare-earth oxide Nd{sub 2}O{sub 3} as gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Gogoi, P., E-mail: paragjyoti_g@rediffmail.com [Sibsagar College, Material Science Laboratory, Department of Physics (India)

    2013-03-15

    The performance of thermally deposited CdS thin film transistors doped with Ag has been reported. Ag-doped CdS thin films have been prepared using chemical method. High dielectric constant rare earth oxide Nd{sub 2}O{sub 3} has been used as gate insulator. The thin film trasistors are fabricated in coplanar electrode structure on ultrasonically cleaned glass substrates with a channel length of 50 {mu}m. The thin film transistors exhibit a high mobility of 4.3 cm{sup 2} V{sup -1} s{sup -1} and low threshold voltage of 1 V. The ON-OFF ratio of the thin film transistors is found as 10{sup 5}. The TFTs also exhibit good transconductance and gain band-width product of 1.15 Multiplication-Sign 10{sup -3} mho and 71 kHz respectively.

  18. Functionalization and Characterization of Nanomaterial Gated Field-Effect Transistor-Based Biosensors and the Design of a Multi-Analyte Implantable Biosensing Platform

    Science.gov (United States)

    Croce, Robert A., Jr.

    Advances in semiconductor research and complementary-metal-oxide semiconductor fabrication allow for the design and implementation of miniaturized metabolic monitoring systems, as well as advanced biosensor design. The first part of this dissertation will focus on the design and fabrication of nanomaterial (single-walled carbon nanotube and quantum dot) gated field-effect transistors configured as protein sensors. These novel device structures have been functionalized with single-stranded DNA aptamers, and have shown sensor operation towards the protein Thrombin. Such advanced transistor-based sensing schemes present considerable advantages over traditional sensing methodologies in view of its miniaturization, low cost, and facile fabrication, paving the way for the ultimate realization of a multi-analyte lab-on-chip. The second part of this dissertation focuses on the design and fabrication of a needle-implantable glucose sensing platform which is based solely on photovoltaic powering and optical communication. By employing these powering and communication schemes, this design negates the need for bulky on-chip RF-based transmitters and batteries in an effort to attain extreme miniaturization required for needle-implantable/extractable applications. A complete single-sensor system coupled with a miniaturized amperometric glucose sensor has been demonstrated to exhibit reality of this technology. Furthermore, an optical selection scheme of multiple potentiostats for four different analytes (glucose, lactate, O 2 and CO2) as well as the optical transmission of sensor data has been designed for multi-analyte applications. The last part of this dissertation will focus on the development of a computational model for the amperometric glucose sensors employed in the aforementioned implantable platform. This model has been applied to single-layer single-enzyme systems, as well as multi-layer (single enzyme) systems utilizing glucose flux limiting layer-by-layer assembled

  19. Sodium beta-alumina thin films as gate dielectrics for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

    Institute of Scientific and Technical Information of China (English)

    Tian Ben-Lang; Chen Chao; Li Yan-Rong; Zhang Wan-Li; Liu Xing-Zhao

    2012-01-01

    Sodium beta-alumina (SBA) is deposited on AlGaN/GaN by using a co-deposition process with sodium and Al2O3 as the precursors.The X-ray diffraction (XRD) spectrum reveals that the deposited thin film is amorphous.The binding energy and composition of the deposited thin film,obtained from the X-ray photoelectron spectroscopy (XPS)measurement,are consistent with those of SBA.The dielectric constant of the SBA thin film is about 50.Each of the capacitance-voltage characteristics obtained at five different frequencies shows a high-quality interface between SBA and A1GaN.The interface trap density of metal-insulator-semiconductor high-electron-mobility transistor (MISHEMT)is measured to be (3.5~9.5)× 1010 cm-2.eV-1 by the conductance method.The fixed charge density of SBA dielectric is on the order of 2.7x1012 cm-2.Compared with the AlGaN/GaN metal semiconductor hetcrostructure high-electron-mobility transistor (MESHEMT),the AlGaN/GaN MISHEMT usually has a threshold voltage that shifts negatively.However,the threshold voltage of the AlGaN/GaN MISHEMT using SBA as the gate dielectric shifts positively from -5.5 V to-3.5 V.From XPS results,the surface valence-band maximum (VBM-EF) of AlGaN is found to decrease from 2.56 eV to 2.25 eV after the SBA thin film deposition.The possible reasons why the threshold voltage of AlGaN/GaN MISHEMT with the SBA gate dielectric shifts positively are the influence of SBA on surface valence-band maximum (VBM-EF),the reduction of interface traps and the effects of sodium ions,and/or the fixed charges in SBA on the two-dimensional electron gas (2DEG).

  20. Effect of Surface-optical Phonons on the Charge Transport in Wrap-gated Semiconducting Nanowire Field-effect Transistors

    Science.gov (United States)

    Konar, Aniruddha; Fang, Tian; Jena, Debdeep

    2010-03-01

    Surface phonons (SO-phonons) arise at the boundary of two different dielectric mediums. Though the effect of electron-surface phonon scattering on low-filed charge transport has been studied extensively for thin Si-MOSFET [1] and graphene [2], its effect on the 1D nanowire devices has not studied so far. Vibrating diploes in polar gate-dielectric induces a time-varying potential inside the nanowires. The frequencies of these time-varying fields have been calculated by implementing electrostatic boundary conditions at different interfaces of nanowire-dielectric-metal system. Our calculation shows that the electron-SO phonon interaction strength decays exponentially from the gate-nanowire interface towards the nanowire axis. Electron-SO phonon scattering rate has been calculated using Boltzmann transport equation under relaxation time approximation. We find that for thin nanowires (radius 1-20 nm), electron-SO phonon scattering rate is comparable to other dominant scattering mechanisms (such as impurity and bulk optical phonon scatterings) and reduces carrier mobility significantly. Calculating surface-phonon limited mobility of Si nanowires on various available common dielectrics, we have predicted the optimum choice of gate-dielectrics for nanowire-based electronic devices. [4pt] [1] M. V. Fischetti et. al J. Appl. Phys. 90 4581 (2001). [0pt] [2] A. Konar et. al. arXiv: 0902.0819.

  1. Monitoring of Postoperative Bone Healing Using Smart Trauma-Fixation Device With Integrated Self-Powered Piezo-Floating-Gate Sensors.

    Science.gov (United States)

    Borchani, Wassim; Aono, Kenji; Lajnef, Nizar; Chakrabartty, Shantanu

    2016-07-01

    Achieving better surgical outcomes in cases of traumatic bone fractures requires postoperative monitoring of changes in the growth and mechanical properties of the tissue and bones during the healing process. While current in-vivo imaging techniques can provide a snapshot of the extent of bone growth, it is unable to provide a history of the healing process, which is important if any corrective surgery is required. Monitoring the time evolution of in-vivo mechanical loads using existing technology is a challenge due to the need for continuous power while maintaining patient mobility and comfort. This paper investigates the feasibility of self-powered monitoring of the bone-healing process using our previously reported piezo-floating-gate (PFG) sensors. The sensors are directly integrated with a fixation device and operate by harvesting energy from microscale strain variations in the fixation structure. We show that the sensors can record and store the statistics of the strain evolution during the healing process for offline retrieval and analysis. Additionally, we present measurement results using a biomechanical phantom comprising of a femur fracture fixation plate; bone healing is emulated by inserting different materials, with gradually increasing elastic moduli, inside a fracture gap. The PFG sensor can effectively sense, compute, and record continuously evolving statistics of mechanical loading over a typical healing period of a bone, and the statistics could be used to differentiate between different bone-healing conditions. The proposed sensor presents a reliable objective technique to assess bone-healing progress and help decide on the removal time of the fixation device.

  2. Memory window widening of Pt/SrBi2Ta2O9/HfO2/Si ferroelectric-gate field-effect transistors by nitriding Si

    Science.gov (United States)

    Horiuchi, Takeshi; Takahashi, Mitsue; Ohhashi, Kentaro; Sakai, Shigeki

    2009-10-01

    The optimum temperature of rapid thermal nitridation (RTN) of Si substrates was investigated for minimizing an equivalent oxide thickness (EOT) of an interfacial layer (IL) which was grown between HfO2 and Si of Pt/SrBi2Ta2O9(SBT)/HfO2/Si ferroelectric-gate field-effect transistors (FeFETs) during a post-annealing process. The RTN was performed in NH3 gas at various temperatures ranging from 800 °C to 1190 °C. As the RTN temperature was raised from 800 °C to 1080 °C, memory windows of drain current-gate voltage curves became wider. Large memory windows were obtained at the range from 1020 °C to 1130 °C. The maximum was 1.36 V obtained at 1080 °C. It was 10% larger than the typical values of Pt/SBT/HfO2/Si FeFETs without the RTN. At higher RTN temperatures than 1080 °C, the memory windows tended to decrease. At 800 °C and 1190 °C, all layer boundaries among SBT-HfO2-IL-Si seemed unclear in scanning transmission electron microscopic views probably due to material diffusions. The optimum RTN temperature for minimizing the EOT of the IL and maximizing the memory window of the Pt/SBT/HfO2/SiNx/Si FeFET was 1080 °C. The FeFET using the Si processed by the RTN at 1080 °C also showed good retentions without significant degradations over two days.

  3. Quasi-two-dimensional subthreshold current model of deep submicrometer SOI drive-in gate controlled hybrid transistors with lateral non-uniform doping profile

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    We have analyzed the operating mechanism of the novel deep submicrometer SOI drive-in gate controlled hybrid transistor (DGCHT), which can effectively alleviate the contradiction between speed enhancement and power reduction in conventional MOS devices and can improve the output resistance. On the basis of this, the subthreshold current model of DGCHTs is proposed. The model takes into account the impact of lateral non-uniform doping profile on body effect, short-channel effect and carrier mobility. Considering the mobile charge, two-dimensional Poisson equation is solved with quasi-two-dimensional analysis and parabolic approximation of surface potential. With the surface potential obtained, the subthreshold current is figured out, including both the diffusion and drift component. The calculated results are in good agreement with the MEDICI numerical simulation results, indicating the correct description of the current characteristics of SOI DGCHT by the presented model. The model can also be considered as an important reference to the current simulation of deep submicrometer MOSFET with pocket implantation.

  4. Study on Preparation of High-k Organic-Inorganic Thin Film for Organic-Inorganic Thin Film Transistor Gate Dielectric Application

    Science.gov (United States)

    Lee, Wen-Hsi; Liu, Chao-Te; Lee, Ying-Chieh

    2012-06-01

    A simple solution-based deposition technique combined with spin-coating is a plausible way to prepare ultra-thin organic-inorganic nanocomposite films. In this study, we describe the spin-coating deposition of a colloidal nanoparticle suspension to obtain an ultra-thin organic-inorganic composite film as a gate insulator for organic thin film transistor (O-TFT) application. To obtain a homogenous organic-inorganic composite film, well-dispersed TiO2 nanoparticles in γ-butyrolactone and polyimide are important; therefore, several dispersants were assessed on the basis of the measurement of the rheological behavior of slurries. The thickness of the organic-inorganic composite film is mainly determined by the speed of spin-coating and viscosity of slurries. An approximately 4000-Å-thick nanocomposite film with homogeneous distribution of TiO2 nanoparticles in polyimide and low roughness was obtained after curing at 200 °C, resulting in a low leakage current density of the nano-composite film, when less than 2 vol % TiO2 nanoparticles were well dispersed in polyimide slurry. The dielectric constant of the organic-inorganic nanocomposite increases with increasing TiO2 content in polyimide, being situated in the range between 4 and 5.

  5. Characteristics of Extended-Gate Field-Effect Transistor (EGFET) Based on Porous n-Type (111) Silicon for Use in pH Sensors

    Science.gov (United States)

    Ahmed, Naser M.; Kabaa, E. A.; Jaafar, M. S.; Omar, A. F.

    2017-10-01

    Following the advances in pH sensors based on porous silicon (p-Si) in the late 20th century, several studies have been carried out to take advantage of the intrinsic properties of p-Si for development of chemical sensors. This study investigates the characteristics and pH sensitivity of an extended-gate field-effect transistor (EGFET) based on n-type p-Si with (111) orientation. Porous silicon was applied directly without coating. The x-ray diffractogram revealed only n-type (111) crystal orientation. p-Si was comparatively analyzed against a silicon wafer (flat and porous surface) in the pH range from 2 to 12. Regarding EGFET operation, p-Si exhibited significantly enhanced pH sensitivity of 56.13 mV/pH and linearity of 0.9857 (at drain-source current I DS of 0.1 mA, temperature of 300 K, and immersion time of 300 s) because of its high surface area, whereas the silicon wafer (flat and porous surface) exhibited comparatively poor sensitivity of 25.41 mV/pH and linearity of 0.99 under similar conditions. In addition, we demonstrate use of current as a second parameter with high linearity for pH sensing. The low hysteresis depth (9 mV) of the EGFET sensor based on p-Si indicates good stability and reversibility.

  6. Progress of p-channel bottom-gate poly-Si thin-film transistor by nickel silicide seed-induced lateral crystallization

    Science.gov (United States)

    Lee, Sol Kyu; Seok, Ki Hwan; Park, Jae Hyo; Kim, Hyung Yoon; Chae, Hee Jae; Jang, Gil Su; Lee, Yong Hee; Han, Ji Su; Joo, Seung Ki

    2016-06-01

    Excimer laser annealing (ELA) is known to be the most common crystallization technology for the fabrication of low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) in the mass production industry. This technology, however, cannot be applied to bottom-gate (BG) TFTs, which are well developed for the liquid-crystal display (LCD) back-planes, because strong laser energy of ELA can seriously damage the other layers. Here, we propose a novel high-performance BG poly-Si TFT using Ni silicide seed-induced lateral crystallization (SILC). The SILC technology renders it possible to ensure low damage in the layers, smooth surface, and longitudinal large grains in the channel. It was observed that the electrical properties exhibited a steep subthreshold slope of 110 mV/dec, high field-effect mobility of 304 cm2/Vsec, high I on/ I off ratio of 5.9 × 107, and a low threshold voltage of -3.9 V.

  7. Effect of oxygen plasma treatment on horizontally aligned carbon nanotube thin film as pH-sensing membrane of extended-gate field-effect transistor

    Science.gov (United States)

    Wang, Kuang-Yu; Tsai, Wan-Lin; Yang, Po-Yu; Chou, Chia-Hsin; Li, Yu-Ren; Liao, Chan-Yu; Cheng, Huang-Chung

    2015-04-01

    The high-performance pH-sensing membrane of extended-gate field-effect transistors (EGFET) composed of high-conductivity horizontally aligned carbon nanotube thin films (HACNTFs) after oxygen plasma treatment is successfully demonstrated. The 10-µm-wide catalytic metal lines with 60 µm interspace produced CNT vertical plates, and the plates were mechanically pulled down and densified to form HACNTFs. A large amount of oxygen-containing functional groups are decorated on the CNTs after the oxygen plasma treatment. These functional groups act as the sensing sites and respond to the H+ or OH- ions in solutions with different pH values. Therefore, these functionalized HACNTFs as pH-EGFET-sensing membranes can achieve a high voltage sensitivity of 40 mV/pH and high current sensitivity of 0.78 µA1/2/pH. Moreover, large linearity of 0.998 is measured in a wide sensing range from pH 1 to 13. These results reveal that the oxygen plasma treatment is an effective way to improve the CNT-sensing characteristics in pH-EGFET sensors.

  8. Reverse Gate Bias-Induced Degradation of AlGaN/GaN High Electron Mobility Transistors

    Science.gov (United States)

    2010-09-23

    contributions from hot electrons and self-heating.13,19,20 In this article, we report on the degradation of AlGaN/ GaN HEMTs under step-stressing of...characteristic of the AlGaN/ GaN HEMTs before and after stress. FIG. 6. !Color online" PL spectra of stressed and unstressed devices. FIG. 7. EL images of stressed...high electric fields present under reverse bias stressing of AlGaN/ GaN HEMTs , the devices exhibit a five order of magnitude increase in gate current

  9. Precursor- route ZnO films from mixed casting solvent for high performance aqueous electrolyte- gated transistors

    OpenAIRE

    Grell, M.; Althagafi, T.M.; Algarni, S.A.; Al Naim, A.; Mazher, J.

    2015-01-01

    We significantly improved the properties of semiconducting zinc oxide (ZnO) films resulting from the thermal conversion of a soluble precursor, zinc acetate (ZnAc), by using a mixed casting solvent for the precursor. ZnAc dissolves more readily in a 1:1 mix of ethanol (EtOH) and acetone than in either pure EtOH, pure acetone, or pure isopropanol, and ZnO films converted from mixed solvent cast ZnAc are more homogeneous. When gated with a biocompatible electrolyte, phosphate buffered saline (P...

  10. Effect of zirconium or titanium component on electrical properties of PbZr1‑x Ti x O3 gated negative capacitance ferroelectric field-effect transistors

    Science.gov (United States)

    Xiao, Y. G.; Wang, J.; Ma, D. B.; Li, Z.; Tang, M. H.

    2016-10-01

    The electrical characteristics of PbZr1‑x Ti x O3 (PZT) gated negative capacitance ferroelectric field-effect transistor (NC-FeFET) were investigated by considering the titanium component (x). The derived results indicated that the semiconductor silicon surface potential, the gate capacitance and the transfer characteristics of the NC-FeFET are significantly influenced by the titanium component x. The average value of subthreshold swing (SS) over six orders of current from source to drain increases from 58 to 70 mV dec–1 when x increases from 0.035 to 0.065. It is hoped that these results can shed light on the design of PZT gated NC-FeFETs for low power dissipation application.

  11. Low-Programmable-Voltage Nonvolatile Memory Devices Based on Omega-shaped Gate Organic Ferroelectric P(VDF-TrFE) Field Effect Transistors Using p-type Silicon Nanowire Channels

    Institute of Scientific and Technical Information of China (English)

    Ngoc Huynh Van; Jae-Hyun Lee; Dongmok Whang; Dae Joon Kang

    2015-01-01

    A facile approach was demonstrated for fabricating high-performance nonvolatile memory devices based on ferroelectric-gate field effect transistors using a p-type Si nanowire coated with omega-shaped gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)). We overcame the interfacial layer problem by incorporating P(VDF-TrFE) as a ferroelectric gate using a low-temperature fabrication process. Our memory devices exhibited excellent memory characteristics with a low programming voltage of ±5 V, a large modulation in channel conductance between ON and OFF states exceeding 105, a long retention time greater than 3 9 104 s, and a high endurance of over 105 programming cycles while maintaining an ION/IOFF ratio higher than 102.

  12. Transparent nanoscale floating gate memory using self-assembled bismuth nanocrystals in Bi(2) Mg(2/3) Nb(4/3) O(7) (BMN) pyrochlore thin films grown at room temperature.

    Science.gov (United States)

    Jung, Hyun-June; Yoon, Soon-Gil; Hong, Soon-Ku; Lee, Jeong-Yong

    2012-07-01

    Bismuth nanocrystals for a nanoscale floating gate memory device are self-assembled in Bi(2) Mg(2/3) Nb(4/3) O(7) (BMN) dielectric films grown at room temperature by radio-frequency sputtering. The TEM cross-sectional image shows the "real" structure grown on a Si (001) substrate. The image magnified from the dotted box (red color) in the the cross-sectional image clearly shows bismuth nanoparticles at the interface between the Al(2) O(3) and HfO(2) layer (right image). Nanoparticles approximately 3 nm in size are regularly distributed at the interface.

  13. Carrier-Number-Fluctuation Induced Ultralow 1/f Noise Level in Top-Gated Graphene Field Effect Transistor.

    Science.gov (United States)

    Peng, Songang; Jin, Zhi; Zhang, Dayong; Shi, Jingyuan; Mao, Dacheng; Wang, Shaoqing; Yu, Guanghui

    2017-03-01

    A top-gated graphene FET with an ultralow 1/f noise level of 1.8 × 10(-12) μm(2)Hz(1-) (f = 10 Hz) has been fabricated. The noise has the least value at Dirac point, it then increases fast when the current deviates from that at Dirac point, the noise slightly decreases at large current. The phenomenon can be understood by the carrier-number-fluctuation induced low frequency noise, which caused by the trapping-detrapping processes of the carriers. Further analysis suggests that the effect trap density depends on the location of Fermi level in graphene channel. The study has provided guidance for suppressing the 1/f noise in graphene-based applications.

  14. Step buffer layer of Al0.25Ga0.75N/Al0.08Ga0.92N on P-InAlN gate normally-off high electron mobility transistors

    Science.gov (United States)

    Shrestha, Niraj M.; Li, Yiming; Chang, E. Y.

    2016-07-01

    Normally-off AlGaN/GaN high electron mobility transistors (HEMTs) are indispensable devices for power electronics as they can greatly simplify circuit designs in a cost-effective way. In this work, the electrical characteristics of p-type InAlN gate normally-off AlGaN/GaN HEMTs with a step buffer layer of Al0.25Ga0.75N/Al0.1Ga0.9N is studied numerically. Our device simulation shows that a p-InAlN gate with a step buffer layer allows the transistor to possess normally-off behavior with high drain current and high breakdown voltage simultaneously. The gate modulation by the p-InAlN gate and the induced holes appearing beneath the gate at the GaN/Al0.25Ga0.75N interface is because a hole appearing in the p-InAlN layer can effectively vary the threshold voltage positively. The estimated threshold voltage of the normally-off HEMTs explored is 2.5 V at a drain bias of 25 V, which is 220% higher than the conventional p-AlGaN normally-off AlGaN/GaN gate injection transistor (GIT). Concurrently, the maximum current density of the explored HEMT at a drain bias of 10 V slightly decreases by about 7% (from 240 to 223 mA mm-1). At a drain bias of 15 V, the current density reached 263 mA mm-1. The explored structure is promising owing to tunable positive threshold voltage and the maintenance of similar current density; notably, its breakdown voltage significantly increases by 36% (from 800 V, GIT, to 1086 V). The engineering findings of this study indicate that novel p-InAlN for both the gate and the step buffer layer can feature a high threshold voltage, large current density and high operating voltage for advanced AlGaN/GaN HEMT devices.

  15. Novel Nanocrystal Floating Gate Memory

    OpenAIRE

    Zhou, Huimei

    2012-01-01

    This work is devoted to investigating the feasibility of engineering nanocrystals and tunnel oxide layer with a novel structure. Several novel devices are demonstrated to improve the performance of the novel nanocrystal memories.A novel TiSi2 nanocrystal memory was demonstrated. TiSi2 nanocrystals were synthesized on SiO2 by annealing Ti covered Si nanocrystals. Compared to the reference Si nanocrystal memory, both experiment and simulation results show that TiSi2 nanocrystal memory exhibits ...

  16. Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography

    Energy Technology Data Exchange (ETDEWEB)

    Han, Bin, E-mail: hanbin@imr.tohoku.ac.jp; Takamizawa, Hisashi, E-mail: takamizawa.hisashi@jaea.go.jp; Shimizu, Yasuo; Inoue, Koji; Nagai, Yasuyoshi [The Oarai Center, Institute for Materials Research, Tohoku University, 2145-2 Narita, Oarai, Ibaraki 311-1313 (Japan); Yano, Fumiko [Department of Electrical Engineering, Faculty of Engineering, Tokyo City University, 1-28-1 Tamazutsumi, Setagaya-ku, Tokyo 158-8557 (Japan); Kunimune, Yorinobu [Renesas Semiconductor Manufacturing Co., Ltd., 1120 Shimokuzawa, Sagamihara, Kanagawa 252-5298 (Japan); Inoue, Masao; Nishida, Akio [Renesas Electronics Corporation, 751 Horiguchi, Hitachinaka, Ibaraki 312-8504 (Japan)

    2015-07-13

    The dopant (P and B) diffusion path in n- and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated using atom probe tomography, based on the annealing time dependence of the dopant distribution at 900 °C. Remarkable differences were observed between P and B diffusion behavior. In the initial stage of diffusion, P atoms diffuse into deeper regions from the implanted region along grain boundaries in the n-type polycrystalline-Si gate. With longer annealing times, segregation of P on the grain boundaries was observed; however, few P atoms were observed within the large grains or on the gate/gate oxide interface distant from grain boundaries. These results indicate that P atoms diffuse along grain boundaries much faster than through the bulk or along the gate/gate oxide interface. On the other hand, in the p-type polycrystalline-Si gate, segregation of B was observed only at the initial stage of diffusion. After further annealing, the B atoms became uniformly distributed, and no clear segregation of B was observed. Therefore, B atoms diffuse not only along the grain boundary but also through the bulk. Furthermore, B atoms diffused deeper than P atoms along the grain boundaries under the same annealing conditions. This information on the diffusion behavior of P and B is essential for optimizing annealing conditions in order to control the P and B distributions in the polycrystalline-Si gates of trench-type 3D MOSFETs.

  17. Immobilized rolling circle amplification on extended-gate field-effect transistors with integrated readout circuits for early detection of platelet-derived growth factor.

    Science.gov (United States)

    Lin, Ming-Yu; Hsu, Wen-Yang; Yang, Yuh-Shyong; Huang, Jo-Wen; Chung, Yueh-Lin; Chen, Hsin

    2016-07-01

    Detection of tumor-related proteins with high specificity and sensitivity is important for early diagnosis and prognosis of cancers. While protein sensors based on antibodies are not easy to keep for a long time, aptamers (single-stranded DNA) are found to be a good alternative for recognizing tumor-related protein specifically. This study investigates the feasibility of employing aptamers to recognize the platelet-derived growth factor (PDGF) specifically and subsequently triggering rolling circle amplification (RCA) of DNAs on extended-gate field-effect transistors (EGFETs) to enhance the sensitivity. The EGFETs are fabricated by the standard CMOS technology and integrated with readout circuits monolithically. The monolithic integration not only avoids the wiring complexity for a large sensor array but also enhances the sensor reliability and facilitates massive production for commercialization. With the RCA primers immobilized on the sensory surface, the protein signal is amplified as the elongation of DNA, allowing the EGFET to achieve a sensitivity of 8.8 pM, more than three orders better than that achieved by conventional EGFETs. Moreover, the responses of EGFETs are able to indicate quantitatively the reaction rates of RCA, facilitating the estimation on the protein concentration. Our experimental results demonstrate that immobilized RCA on EGFETs is a useful, label-free method for early diagnosis of diseases related to low-concentrated tumor makers (e.g., PDGF) for serum sample, as well as for monitoring the synthesis of various DNA nanostructures in real time. Graphical Abstract The tumor-related protein, PDGF, is detected by immobilizing rolling circle amplification on an EGFET with integrated readout circuit.

  18. Label-free C-reactive protein electronic detection with an electrolyte-gated organic field-effect transistor-based immunosensor.

    Science.gov (United States)

    Magliulo, Maria; De Tullio, Donato; Vikholm-Lundin, Inger; Albers, Willem M; Munter, Tony; Manoli, Kyriaki; Palazzo, Gerardo; Torsi, Luisa

    2016-06-01

    In this contribution, we propose a label-free immunosensor, based on a novel type of electrolyte-gated field-effect transistor (EGOFET), for ultrasensitive detection of the C-reactive protein (CRP). The recognition layer of the biosensor is fabricated by physical adsorption of the anti-CRP monoclonal antibody onto a poly-3-hexyl thiophene (P3HT) organic semiconductor surface. A supplementary nonionic hydrophilic polymer is used as a blocking agent preventing nonspecific interactions and allowing a better orientation of the antibodies immobilized onto the P3HT surface. The whole biomolecule immobilization procedure does not require any pretreatment of the organic semiconductor surface, and the whole functionalization process is completed in less than 30 min. Surface plasmon resonance (SPR) measurements were performed to assess the amount of biomolecules physisorbed onto the P3HT and to evaluate the CRP binding proprieties of the deposited anti-CRP layer. A partial surface coverage of about 23 % of adsorbed antibody molecules was found to most efficiently sense the CRP. The electrical performance of the EGOFET immunosensor was comparable to that of a bare P3HT EGOFET device, and the obtained CRP calibration curve was linear over six orders of magnitude (from 4 pM to 2 μM). The relative standard deviation of the individual calibration points, measured on immunosensors fabricated on different chips, ranged between 1 and 14 %, and a detection limit of 2 pM (220 ng/L) was established. The novel electronic immunosensor is compatible with low-cost fabrication procedures and was successfully employed for the detection of the CRP biomarker in the clinically relevant matrix serum. Graphical abstract Schematic of the EGOFET immunosensor for CRP detection. The anti-CRP monoclonal antibody layer is physisorbed on the P3HT organic semiconductor and the CRP is directly measured by a label-free electronic EGOFET transducer.

  19. Electrical performance of silicon-on-insulator field-effect transistors with multiple top-gate organic layers in electrolyte solution.

    Science.gov (United States)

    Khamaisi, Bassam; Vaknin, Oshri; Shaya, Oren; Ashkenasy, Nurit

    2010-08-24

    The utilization of field-effect transistor (FET) devices in biosensing applications have been extensively studied in recent years. Qualitative and quantitative understanding of the contribution of the organic layers constructed on the device gate, and the electrolyte media, on the behavior of the device is thus crucial. In this work we analyze the contribution of different organic layers on the pH sensitivity, threshold voltage, and gain of a silicon-on-insulator based FET device. We further monitor how these properties change as function of the electrolyte screening length. Our results show that in addition to electrostatic effects, changes in the amphoteric nature of the surface also affect the device threshold voltage. These effects were found to be additive for the first (3-aminopropyl)trimethoxysilane linker layer and second biotin receptor layer. For the top streptavidin protein layer, these two effects cancel each other. The number and nature of amphoteric groups on the surface, which changes upon the formation of the layers, was shown also to affect the pH sensitivity of the device. The pH sensitivity reduces with the construction of the first two layers. However, after the formation of the streptavidin protein layer, the protein's multiple charged side chains induce an increase in the sensitivity at low ionic strengths. Furthermore, the organic layers were found to influence the device gain due to their dielectric properties, reducing the gain with the successive construction of each layer. These results demonstrate the multilevel influence of organic layers on the behavior of the FET devices.

  20. Memory and negative-resistance effects in a strained metal-gate high-k n-type field-effect-transistor from 375 K down to 77 K

    Science.gov (United States)

    Gutiérrez-D, E. A.; Vega-G, V. H.; García-R, P. J.; Huerta-G, O. V.

    2016-12-01

    We introduce an experimental alternative way of looking into the charging and discharging mechanism inside a high-k stacked oxide of a metal-gate strained n-type Field-Effect-Transistor (nFET). This alternative way reproduces a memory and negative resistance effect by biasing the nFET device in a non-conventional way. This is achieved by forward-biasing the drain-bulk junction and by setting the gate electrode in a high-impedance mode. The produced negative resistance effect (NRE) has a controllable peak-to-valley current ratio (PVCR) that goes from about 3.0 up to a value of 5.5 at room temperature. The PVCR increases up to 8.35 at T = 225 K and reduces to 2.84 at T = 375 K in a linear trend. The memory effect is observed when the drain-bulk junction voltage is swept from low to high values and back from high to low values. From low to high forward drain-bulk bias the NRE shows up and vanishes when coming back from high to low forward drain-bulk bias. The NRE and memory effects are attributed to a coupled-gate oxide charging/discharging mechanism with an induced bipolar transistor action in the channel of the FET.