Development of measurement system for radiation effect on static random access memory based field programmable gate array

International Nuclear Information System (INIS)

Yao Zhibin; He Baoping; Zhang Fengqi; Guo Hongxia; Luo Yinhong; Wang Yuanming; Zhang Keying

2009-01-01

Based on the detailed investigation in field programmable gate array(FPGA) radiation effects theory, a measurement system for radiation effects on static random access memory(SRAM)-based FPGA was developed. The testing principle of internal memory, function and power current was introduced. The hardware and software implement means of system were presented. Some important parameters for radiation effects on SRAM-based FPGA, such as configuration RAM upset section, block RAM upset section, function fault section and single event latchup section can be gained with this system. The transmission distance of the system can be over 50 m and the maximum number of tested gates can reach one million. (authors)

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Directory of Open Access Journals (Sweden)

Stephen Brown

1996-01-01

Full Text Available This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits.

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

Science.gov (United States)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

International Nuclear Information System (INIS)

Hu, Kun; Wang, Xu; Li, Feng; Jin, Ge; Lu, Houbing; Liang, Futian

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability

The impact of software and CAE tools on SEU in field programmable gate arrays

International Nuclear Information System (INIS)

Katz, R.; Wang, J.; McCollum, J.; Cronquist, B.

1999-01-01

Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements

Nine-channel mid-power bipolar pulse generator based on a field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Haylock, Ben, E-mail: benjamin.haylock2@griffithuni.edu.au; Lenzini, Francesco; Kasture, Sachin; Fisher, Paul; Lobino, Mirko [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Queensland Micro and Nanotechnology Centre, Griffith University, Brisbane (Australia); Streed, Erik W. [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Institute for Glycomics, Griffith University, Gold Coast (Australia)

2016-05-15

Many channel arbitrary pulse sequence generation is required for the electro-optic reconfiguration of optical waveguide networks in Lithium Niobate. Here we describe a scalable solution to the requirement for mid-power bipolar parallel outputs, based on pulse patterns generated by an externally clocked field programmable gate array. Positive and negative pulses can be generated at repetition rates up to 80 MHz with pulse width adjustable in increments of 1.6 ns across nine independent outputs. Each channel can provide 1.5 W of RF power and can be synchronised with the operation of other components in an optical network such as light sources and detectors through an external clock with adjustable delay.

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

Science.gov (United States)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Field-programmable gate array based controller for multi spot light-addressable potentiometric sensors with integrated signal correction mode

Energy Technology Data Exchange (ETDEWEB)

Werner, Carl Frederik; Schusser, Sebastian; Spelthahn, Heiko [Aachen University of Applied Sciences, Juelich Campus, Institute of Nano- and Biotechnologies, Heinrich-Mussmann-Strasse 1, 52428 Juelich (Germany); Institute of Bio- and Nanosystems (IBN-2), Research Centre Juelich GmbH, 52425 Juelich (Germany); Wagner, Torsten; Yoshinobu, Tatsuo [Tohoku University, Department of Electronic Engineering, 6-6-05 Aramaki Aza Aoba, Aoba-ku, Sendai, Miyagi 980-8579 (Japan); Schoening, Michael J., E-mail: schoening@fh-aachen.de [Aachen University of Applied Sciences, Juelich Campus, Institute of Nano- and Biotechnologies, Heinrich-Mussmann-Strasse 1, 52428 Juelich (Germany); Institute of Bio- and Nanosystems (IBN-2), Research Centre Juelich GmbH, 52425 Juelich (Germany)

2011-11-01

Highlights: > Flexible up-scalable design of a light-addressable potentiometric sensor set-up. > Utilisation of a field-programmable gate array to address LAPS measurement spots. > Measurements in amplitude-mode and phase-mode for different pH solutions. > Amplitude, phase and frequency behaviour of LAPS for single and multiple light stimulus. > Signal calibration method by brightness control to compensated systematic errors. - Abstract: A light-addressable potentiometric sensor (LAPS) can measure the concentration of one or several analytes at the sensor surface simultaneously in a spatially resolved manner. A modulated light pointer stimulates the semiconductor structure at the area of interest and a responding photocurrent can be read out. By simultaneous stimulation of several areas with light pointers of different modulation frequencies, the read out can be performed at the same time. With the new proposed controller electronic based on a field-programmable gate array (FPGA), it is possible to control the modulation frequencies, phase shifts, and light brightness of multiple light pointers independently and simultaneously. Thus, it is possible to investigate the frequency response of the sensor, and to examine the analyte concentration by the determination of the surface potential with the help of current/voltage curves and phase/voltage curves. Additionally, the ability to individually change the light intensities of each light pointer is used to perform signal correction.

Design and Implementation of Video Shot Detection on Field Programmable Gate Arrays

Directory of Open Access Journals (Sweden)

Jharna Majumdar

2012-09-01

Full Text Available Video has become an interactive medium of communication in everyday life. The sheer volume of video makes it extremely difficult to browse through and find the required data. Hence extraction of key frames from the video which represents the abstract of the entire video becomes necessary. The aim of the video shot detection is to find the position of the shot boundaries, so that key frames can be selected from each shot for subsequent processing such as video summarization, indexing etc. For most of the surveillance applications like video summery, face recognition etc., the hardware (real time implementation of these algorithms becomes necessary. Here in this paper we present the architecture for simultaneous accessing of consecutive frames, which are then used for the implementation of various Video Shot Detection algorithms. We also present the real time implementation of three video shot detection algorithms using the above mentioned architecture on FPGA (Field Programmable Gate Arrays.

Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

Science.gov (United States)

Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

2013-01-01

This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

Application of Field Programmable Gate Arrays in Instrumentation and Control Systems of Nuclear Power Plants

International Nuclear Information System (INIS)

2016-01-01

Field programmable gate arrays (FPGAs) are gaining increased attention worldwide for application in nuclear power plant (NPP) instrumentation and control (I&C) systems, particularly for safety and safety related applications, but also for non-safety ones. NPP operators and equipment suppliers see potential advantages of FPGA based digital I&C systems as compared to microprocessor based applications. This is because FPGA based systems can be made simpler, more testable and less reliant on complex software (e.g. operating systems), and are easier to qualify for safety and safety related applications. This publication results from IAEA consultancy meetings covering the various aspects, including design, qualification, implementation, licensing, and operation, of FPGA based I&C systems in NPPs

Field programmable gate array reliability analysis using the dynamic flow graph methodology

Energy Technology Data Exchange (ETDEWEB)

McNelles, Phillip; Lu, Lixuan [Faculty of Energy Systems and Nuclear Science, University of Ontario Institute of Technology (UOIT), Ontario (Canada)

2016-10-15

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the 'IEEE 1164 standard', registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Science.gov (United States)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

International Nuclear Information System (INIS)

Jinyuan Wu; Zonghan Shi; Irena Y Wang

2003-01-01

A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

Energy Technology Data Exchange (ETDEWEB)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp [Quantum Metrology Laboratory, RIKEN, Wako-shi, Saitama 351-0198 (Japan); Katori, Hidetoshi [Quantum Metrology Laboratory, RIKEN, Wako-shi, Saitama 351-0198 (Japan); Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656 (Japan); Department of Applied Physics, Graduate School of Engineering, The University of Tokyo, Bunkyo-ku, Tokyo 113-8656 (Japan)

2015-11-15

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Design of readout drivers for ATLAS pixel detectors using field programmable gate arrays

CERN Document Server

Sivasubramaniyan, Sriram

Microstrip detectors are an integral patt of high energy physics research . Special protocols are used to transmit the data from these detectors . To readout the data from such detectors specialized instrumentation have to be designed . To achieve this task, creative and innovative high speed algorithms were designed simulated and implemented in Field Programmable gate arrays, using CAD/CAE tools. The simulation results indicated that these algorithms would be able to perform all the required tasks quickly and efficiently. This thesis describes the design of data acquisition system called the Readout Drivers (ROD) . It focuses on the ROD data path for ATLAS Pixel detectors. The data path will be an integrated part of Readout Drivers setup to decode the data from the silicon micro strip detectors and pixel detectors. This research also includes the design of Readout Driver controller. This Module is used to control the operation of the ROD. This module is responsible for the operation of the Pixel decoders bas...

Design of a Tritium-in-air-monitor using field programmable gate arrays

International Nuclear Information System (INIS)

McNelles, Phillip; Lu, Lixuan

2015-01-01

Field Programmable Gate Arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field. Some applications of these devices include Instrumentation and Control (I and C) systems, pulse measurement systems, particle detectors and health physics purposes. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to the increased production of Tritium, which poses a health risk and must be monitored by Tritium-In-Air Monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of Carbon-14 and the addition of noble gas compensation are incorporated into a new FPGA-based TAM. Additionally, all of the standard functions included in the original microprocessor-based TAM, such as tritium detection, gamma compensation, pump and air flow control, and background and thermal drift corrections were also implemented. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. (author)

Three-channel phase meters based on the AD8302 and field programmable gate arrays for heterodyne millimeter wave interferometer

Czech Academy of Sciences Publication Activity Database

Varavin, A.V.; Ermak, G.P.; Vasiliev, A.S.; Fateev, A.V.; Varavin, Mykyta; Žáček, František; Zajac, Jaromír

2016-01-01

Roč. 75, č. 11 (2016), s. 1009-1025 ISSN 0040-2508 Institutional support: RVO:61389021 Keywords : AD8302 * Interferometer * Millimeter wave * Phase meter * Programmable gate array * Tokamak Subject RIV: BL - Plasma and Gas Discharge Physics

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

International Nuclear Information System (INIS)

Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-01-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-03-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver

Science.gov (United States)

Cornetta, Gianluca; Touhafi, Abdellah; Santos, David J.; Vázquez, José M.

2010-12-01

An architecture for a low-cost, low-complexity digital transceiver is presented in this article. The proposed architecture targets the IEEE 802.15.4 standard for short-range wireless personal area networks and has been implemented as a synthesisable VHDL register transfer level description. The system has been evaluated and tested using a Xilinx 90 nm Virtex-4 field-programmable gate array as the target technology. Bit error rate (BER) and error vector magnitude (EVM) have been used as the figures of merit for modem performance. Simulations show that the recommended minimum BER is achieved at E b/N 0 = 8.7 dB, whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44 mW in transmit mode and 53 mW in receiver mode.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

Science.gov (United States)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Design of acoustic logging signal source of imitation based on field programmable gate array

Science.gov (United States)

Zhang, K.; Ju, X. D.; Lu, J. Q.; Men, B. Y.

2014-08-01

An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes.

A new data acquisition and imaging system for nuclear microscopy based on a Field Programmable Gate Array card

International Nuclear Information System (INIS)

Bettiol, A.A.; Udalagama, C.; Watt, F.

2009-01-01

The introduction of the new Field Programmable Gate Array (FPGA) cards by National Instruments has made it possible for the first time to develop reconfigurable custom data acquisition hardware easily with the LabVIEW programming environment. Data acquisition issues such as precise timing for scanning and operating system latencies can now be easily overcome using this new technology because the data acquisition software is embedded in the FPGA chip on the card. In this paper we present the first results of the new data acquisition system developed at the Centre for Ion Beam Applications (CIBA), National University of Singapore using the new National Instruments cards in conjunction with rack mountable Wilkinson type ADCs.

Development and simulation of soft morphological operators for a field programmable gate array

Science.gov (United States)

Tickle, Andrew J.; Harvey, Paul K.; Smith, Jeremy S.; Wu, Q. Henry

2013-04-01

In image processing applications, soft mathematical morphology (MM) can be employed for both binary and grayscale systems and is derived from set theory. Soft MM techniques have improved behavior over standard morphological operations in noisy environments, as they can preserve small details within an image. This makes them suitable for use in image processing applications on portable field programmable gate arrays for tasks such as robotics and security. We explain how the systems were developed using Altera's DSP Builder in order to provide optimized code for the many different devices currently on the market. Also included is how the circuits can be inserted and combined with previously developed work in order to increase their functionality. The testing procedures involved loading different images into these systems and analyzing the outputs against MATLAB-generated validation images. A set of soft morphological operations are described, which can then be applied to various tasks and easily modified in size via altering the line buffer settings inside the system to accommodate a range of image attributes ranging from image sizes such as 320×240 pixels for basic webcam imagery up to high quality 4000×4000 pixel images for military applications.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Xu Zhouxiang; Zhang Xian; Huang Kaikai; Lu Xuanhui [Physics Department, Zhejiang University, Hangzhou, 310027 (China)

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A field programmable gate array unit for the diagnosis and control of neoclassical tearing modes on MAST

Energy Technology Data Exchange (ETDEWEB)

O' Gorman, T.; Gibson, K. J.; Snape, J. A. [York Plasma Institute, Department of Physics, University of York, York YO10 5DD (United Kingdom); Naylor, G.; Huang, B.; McArdle, G. J.; Scannell, R.; Shibaev, S.; Thomas-Davies, N. [EURATOM/CCFE Fusion Association, Culham Science Centre, Oxfordshire OX14 3DB (United Kingdom)

2012-10-15

A real-time system has been developed to trigger both the MAST Thomson scattering (TS) system and the plasma control system on the phase and amplitude of neoclassical tearing modes (NTMs), extending the capabilities of the original system. This triggering system determines the phase and amplitude of a given NTM using magnetic coils at different toroidal locations. Real-time processing of the raw magnetic data occurs on a low cost field programmable gate array (FPGA) based unit which permits triggering of the TS lasers on specific amplitudes and phases of NTM evolution. The MAST plasma control system can receive a separate trigger from the FPGA unit that initiates a vertical shift of the MAST magnetic axis. Such shifts have fully removed m/n= 2/1 NTMs instabilities on a number of MAST discharges.

Evaluation of the Leon3 soft-core processor within a Xilinx radiation-hardened field-programmable gate array.

Energy Technology Data Exchange (ETDEWEB)

Learn, Mark Walter

2012-01-01

The purpose of this document is to summarize the work done to evaluate the performance of the Leon3 soft-core processor in a radiation environment while instantiated in a radiation-hardened static random-access memory based field-programmable gate array. This evaluation will look at the differences between two soft-core processors: the open-source Leon3 core and the fault-tolerant Leon3 core. Radiation testing of these two cores was conducted at the Texas A&M University Cyclotron facility and Lawrence Berkeley National Laboratory. The results of these tests are included within the report along with designs intended to improve the mitigation of the open-source Leon3. The test setup used for evaluating both versions of the Leon3 is also included within this document.

Design of acoustic logging signal source of imitation based on field programmable gate array

International Nuclear Information System (INIS)

Zhang, K; Ju, X D; Lu, J Q; Men, B Y

2014-01-01

An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes. (paper)

Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA; Desenvolvimento de sistema de protecao para reator nuclear de pesquisa baseado em Field Programmable Gate Array - FPGA

Energy Technology Data Exchange (ETDEWEB)

Martins, Roque Hudson da Silva

2016-07-01

This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

Field programmable gate array-based real-time optical Doppler tomography system for in vivo imaging of cardiac dynamics in the chick embryo

DEFF Research Database (Denmark)

Thrane, Lars; Larsen, Henning Engelbrecht; Norozi, Kambiz

2009-01-01

efficient and compact implementation by combining the conversion to an analytic signal with a pulse shaping function without the need for extra resources as compared to the Hilbert transform method. The conversion of the analytic signal to amplitude and phase is done by use of the coordinate rotation......We demonstrate a field programmable gate-array-based real-time optical Doppler tomography system. A complex-valued bandpass filter is used for the first time in optical coherence tomography signal processing to create the analytic signal. This method simplifies the filter design, and allows...

Development of field programmable gate array-based reactor trip functions using systems engineering approach

Energy Technology Data Exchange (ETDEWEB)

Jung, Jae Cheon; Ahmed, Ibrahim [Nuclear Power Plant Engineering, KEPCO International Nuclear Graduate School, Ulsan (Korea, Republic of)

2016-08-15

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

Full image-processing pipeline in field-programmable gate array for a small endoscopic camera

Science.gov (United States)

Mostafa, Sheikh Shanawaz; Sousa, L. Natércia; Ferreira, Nuno Fábio; Sousa, Ricardo M.; Santos, Joao; Wäny, Martin; Morgado-Dias, F.

2017-01-01

Endoscopy is an imaging procedure used for diagnosis as well as for some surgical purposes. The camera used for the endoscopy should be small and able to produce a good quality image or video, to reduce discomfort of the patients, and to increase the efficiency of the medical team. To achieve these fundamental goals, a small endoscopy camera with a footprint of 1 mm×1 mm×1.65 mm is used. Due to the physical properties of the sensors and human vision system limitations, different image-processing algorithms, such as noise reduction, demosaicking, and gamma correction, among others, are needed to faithfully reproduce the image or video. A full image-processing pipeline is implemented using a field-programmable gate array (FPGA) to accomplish a high frame rate of 60 fps with minimum processing delay. Along with this, a viewer has also been developed to display and control the image-processing pipeline. The control and data transfer are done by a USB 3.0 end point in the computer. The full developed system achieves real-time processing of the image and fits in a Xilinx Spartan-6LX150 FPGA.

Case for a field-programmable gate array multicore hybrid machine for an image-processing application

Science.gov (United States)

Rakvic, Ryan N.; Ives, Robert W.; Lira, Javier; Molina, Carlos

2011-01-01

General purpose computer designers have recently begun adding cores to their processors in order to increase performance. For example, Intel has adopted a homogeneous quad-core processor as a base for general purpose computing. PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high level. Can modern image-processing algorithms utilize these additional cores? On the other hand, modern advancements in configurable hardware, most notably field-programmable gate arrays (FPGAs) have created an interesting question for general purpose computer designers. Is there a reason to combine FPGAs with multicore processors to create an FPGA multicore hybrid general purpose computer? Iris matching, a repeatedly executed portion of a modern iris-recognition algorithm, is parallelized on an Intel-based homogeneous multicore Xeon system, a heterogeneous multicore Cell system, and an FPGA multicore hybrid system. Surprisingly, the cheaper PS3 slightly outperforms the Intel-based multicore on a core-for-core basis. However, both multicore systems are beaten by the FPGA multicore hybrid system by >50%.

Design techniques for a stable operation of cryogenic field-programmable gate arrays

Science.gov (United States)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

Directory of Open Access Journals (Sweden)

Ion Stiharu

2010-08-01

Full Text Available Computer numerically controlled (CNC machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA-based sensor node.

A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

Science.gov (United States)

Moreno-Tapia, Sandra Veronica; Vera-Salas, Luis Alberto; Osornio-Rios, Roque Alfredo; Dominguez-Gonzalez, Aurelio; Stiharu, Ion; de Jesus Romero-Troncoso, Rene

2010-01-01

Computer numerically controlled (CNC) machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA)-based sensor node. PMID:22163602

Use of Field Programmable Gate Array Technology in Future Space Avionics

Science.gov (United States)

Ferguson, Roscoe C.; Tate, Robert

2005-01-01

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Field application of smart SHM using field programmable gate array technology to monitor an RC bridge in New Mexico

International Nuclear Information System (INIS)

Azarbayejani, M; Jalalpour, M; Reda Taha, M M; El-Osery, A I

2011-01-01

In this paper, an innovative field application of a structural health monitoring (SHM) system using field programmable gate array (FPGA) technology and wireless communication is presented. The new SHM system was installed to monitor a reinforced concrete (RC) bridge on Interstate 40 (I-40) in Tucumcari, New Mexico. This newly installed system allows continuous remote monitoring of this bridge using solar power. Details of the SHM component design and installation are discussed. The integration of FPGA and solar power technologies make it possible to remotely monitor infrastructure with limited access to power. Furthermore, the use of FPGA technology enables smart monitoring where data communication takes place on-need (when damage warning signs are met) and on-demand for periodic monitoring of the bridge. Such a system enables a significant cut in communication cost and power demands which are two challenges during SHM operation. Finally, a three-dimensional finite element (FE) model of the bridge was developed and calibrated using a static loading field test. This model is then used for simulating damage occurrence on the bridge. Using the proposed automation process for SHM will reduce human intervention significantly and can save millions of dollars currently spent on prescheduled inspection of critical infrastructure worldwide

Field application of smart SHM using field programmable gate array technology to monitor an RC bridge in New Mexico

Science.gov (United States)

Azarbayejani, M.; Jalalpour, M.; El-Osery, A. I.; Reda Taha, M. M.

2011-08-01

In this paper, an innovative field application of a structural health monitoring (SHM) system using field programmable gate array (FPGA) technology and wireless communication is presented. The new SHM system was installed to monitor a reinforced concrete (RC) bridge on Interstate 40 (I-40) in Tucumcari, New Mexico. This newly installed system allows continuous remote monitoring of this bridge using solar power. Details of the SHM component design and installation are discussed. The integration of FPGA and solar power technologies make it possible to remotely monitor infrastructure with limited access to power. Furthermore, the use of FPGA technology enables smart monitoring where data communication takes place on-need (when damage warning signs are met) and on-demand for periodic monitoring of the bridge. Such a system enables a significant cut in communication cost and power demands which are two challenges during SHM operation. Finally, a three-dimensional finite element (FE) model of the bridge was developed and calibrated using a static loading field test. This model is then used for simulating damage occurrence on the bridge. Using the proposed automation process for SHM will reduce human intervention significantly and can save millions of dollars currently spent on prescheduled inspection of critical infrastructure worldwide.

Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA

International Nuclear Information System (INIS)

Martins, Roque Hudson da Silva

2016-01-01

This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

International Nuclear Information System (INIS)

Chen, Yuan-Ho

2017-01-01

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Using field programmable gate array hardware for the performance improvement of ultrasonic wave propagation imaging system

Energy Technology Data Exchange (ETDEWEB)

Shan, Jaffry Syed [Hamdard University, Karachi (Pakistan); Abbas, Syed Haider; Lee, Jung Ryul [Dept. of Aerospace Engineering, Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); Kang, Dong Hoon [Advanced Materials Research Team, Korea Railroad Research Institute, Uiwang (Korea, Republic of)

2015-12-15

Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of 100x100mm{sup 2} with 0.5 mm interval) to 87.5% (scanning of 200x200mm{sup 2} with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection.

Using field programmable gate array hardware for the performance improvement of ultrasonic wave propagation imaging system

International Nuclear Information System (INIS)

Shan, Jaffry Syed; Abbas, Syed Haider; Lee, Jung Ryul; Kang, Dong Hoon

2015-01-01

Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of 100x100mm 2 with 0.5 mm interval) to 87.5% (scanning of 200x200mm 2 with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

Energy Technology Data Exchange (ETDEWEB)

Chen, Yuan-Ho, E-mail: chenyh@mail.cgu.edu.tw [Department of Electronic Engineering, Chang Gung University, Tao-Yuan 333, Taiwan (China); Department of Radiation Oncology, Chang Gung Memorial Hospital, Tao-Yuan 333, Taiwan (China); Center for Reliability Sciences and Technologies, Chang Gung University, Tao-Yuan 333, Taiwan (China)

2017-05-11

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

International Nuclear Information System (INIS)

Nolida Yussup; Maslina Mohd Ibrahim; Lojius Lombigit; Nur Aira Abdul Rahman; Muhammad Rawi Mohamed Zin

2013-01-01

Full-text: Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed. (author)

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

International Nuclear Information System (INIS)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

2014-01-01

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed

[Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].

Science.gov (United States)

Wang, Jinlong; Lu, Mai; Hu, Yanwen; Chen, Xiaoqiang; Pan, Qiangqiang

2015-12-01

Neuron is the basic unit of the biological neural system. The Hodgkin-Huxley (HH) model is one of the most realistic neuron models on the electrophysiological characteristic description of neuron. Hardware implementation of neuron could provide new research ideas to clinical treatment of spinal cord injury, bionics and artificial intelligence. Based on the HH model neuron and the DSP Builder technology, in the present study, a single HH model neuron hardware implementation was completed in Field Programmable Gate Array (FPGA). The neuron implemented in FPGA was stimulated by different types of current, the action potential response characteristics were analyzed, and the correlation coefficient between numerical simulation result and hardware implementation result were calculated. The results showed that neuronal action potential response of FPGA was highly consistent with numerical simulation result. This work lays the foundation for hardware implementation of neural network.

Development of a fast time-to-digital converter (TDC) using a programmable gate array

International Nuclear Information System (INIS)

Mine, Shun-ichi; Tokushuku, Katsuo; Yamada, Sakue.

1994-09-01

A fast time-to-digital converter with a 5 ns step was designed and tested by utilizing a user-programmable gate array. The stabilities against temperature and supply voltage variation were measured. A module was built with this TDC, and was successfully used in the first-level trigger system of the ZEUS detector to reject proton-beam induced background events. (author)

Theory and implementation of a very high throughput true random number generator in field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Hui, Cong; Liu, Chong; Xu, Chao [Department of Modern Physics, University of Science and Technology of China, Hefei 230026 (China)

2016-04-15

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation

Science.gov (United States)

Kyrkou, Christos; Theocharides, Theocharis

2016-07-01

Object detection is a major step in several computer vision applications and a requirement for most smart camera systems. Recent advances in hardware acceleration for real-time object detection feature extensive use of reconfigurable hardware [field programmable gate arrays (FPGAs)], and relevant research has produced quite fascinating results, in both the accuracy of the detection algorithms as well as the performance in terms of frames per second (fps) for use in embedded smart camera systems. Detecting objects in images, however, is a daunting task and often involves hardware-inefficient steps, both in terms of the datapath design and in terms of input/output and memory access patterns. We present how a visual-feature-directed search cascade composed of motion detection, depth computation, and edge detection, can have a significant impact in reducing the data that needs to be examined by the classification engine for the presence of an object of interest. Experimental results on a Spartan 6 FPGA platform for face detection indicate data search reduction of up to 95%, which results in the system being able to process up to 50 1024×768 pixels images per second with a significantly reduced number of false positives.

Failure mode taxonomy for assessing the reliability of Field Programmable Gate Array based Instrumentation and Control systems

International Nuclear Information System (INIS)

McNelles, Phillip; Zeng, Zhao Chang; Renganathan, Guna; Chirila, Marius; Lu, Lixuan

2017-01-01

Highlights: • The use FPGAs in I&C systems in Nuclear Power Plants is an important issue (IAEA). • OECD-NEA published a failure mode taxonomy for software-based digital I&C systems. • This paper extends the OECD-NEA taxonomy to model FPGA-based systems. • FPGA failure modes, failure effects, uncovering methods are categorized/described. • Provides an example of modelling an FPGA-Based RTS/ESFAS using the FPGA taxonomy. - Abstract: Field Programmable Gate Arrays (FPGAs) are a form of programmable digital hardware configured to perform digital logic functions. This configuration (programming) is performed using Hardware Description Language (HDL), making FPGAs a form of HDL Programmed Device (HPD). In the nuclear field, FPGAs have seen use in upgrades and replacements of obsolete Instrumentation and Control (I&C) systems. This paper expands upon previous work that resulted in extensive FPGA failure mode data, to allow for the application of the OECD-NEA failure modes taxonomy. The OECD-NEA taxonomy presented a method to model digital (software-based) I&C systems, based on the hardware and software failure modes, failure uncovering effects and levels of abstraction, using a Reactor Trip System/Engineering Safety Feature Actuation System (RTS/ESFAS) as an example system. To create the FPGA taxonomy, this paper presents an additional “sub-component” level of abstraction, to demonstrate the effect of the FPGA failure modes and failure categories on an FPGA-based system. The proposed FPGA taxonomy is based on the FPGA failure modes, failure categories, failure effects and uncovering situations. The FPGA taxonomy is applied to the RTS/ESFAS test system, to demonstrate the effects of the anticipated FPGA failure modes on a digital I&C system, and to provide a modelling example for this proposed taxonomy.

Fringe pattern demodulation using the one-dimensional continuous wavelet transform: field-programmable gate array implementation.

Science.gov (United States)

Abid, Abdulbasit

2013-03-01

This paper presents a thorough discussion of the proposed field-programmable gate array (FPGA) implementation for fringe pattern demodulation using the one-dimensional continuous wavelet transform (1D-CWT) algorithm. This algorithm is also known as wavelet transform profilometry. Initially, the 1D-CWT is programmed using the C programming language and compiled into VHDL using the ImpulseC tool. This VHDL code is implemented on the Altera Cyclone IV GX EP4CGX150DF31C7 FPGA. A fringe pattern image with a size of 512×512 pixels is presented to the FPGA, which processes the image using the 1D-CWT algorithm. The FPGA requires approximately 100 ms to process the image and produce a wrapped phase map. For performance comparison purposes, the 1D-CWT algorithm is programmed using the C language. The C code is then compiled using the Intel compiler version 13.0. The compiled code is run on a Dell Precision state-of-the-art workstation. The time required to process the fringe pattern image is approximately 1 s. In order to further reduce the execution time, the 1D-CWT is reprogramed using Intel Integrated Primitive Performance (IPP) Library Version 7.1. The execution time was reduced to approximately 650 ms. This confirms that at least sixfold speedup was gained using FPGA implementation over a state-of-the-art workstation that executes heavily optimized implementation of the 1D-CWT algorithm.

A Soft Computing Approach to Crack Detection and Impact Source Identification with Field-Programmable Gate Array Implementation

Directory of Open Access Journals (Sweden)

Arati M. Dixit

2013-01-01

Full Text Available The real-time nondestructive testing (NDT for crack detection and impact source identification (CDISI has attracted the researchers from diverse areas. This is apparent from the current work in the literature. CDISI has usually been performed by visual assessment of waveforms generated by a standard data acquisition system. In this paper we suggest an automation of CDISI for metal armor plates using a soft computing approach by developing a fuzzy inference system to effectively deal with this problem. It is also advantageous to develop a chip that can contribute towards real time CDISI. The objective of this paper is to report on efforts to develop an automated CDISI procedure and to formulate a technique such that the proposed method can be easily implemented on a chip. The CDISI fuzzy inference system is developed using MATLAB’s fuzzy logic toolbox. A VLSI circuit for CDISI is developed on basis of fuzzy logic model using Verilog, a hardware description language (HDL. The Xilinx ISE WebPACK9.1i is used for design, synthesis, implementation, and verification. The CDISI field-programmable gate array (FPGA implementation is done using Xilinx’s Spartan 3 FPGA. SynaptiCAD’s Verilog Simulators—VeriLogger PRO and ModelSim—are used as the software simulation and debug environment.

Field programmable gate array based hardware implementation of a gradient filter for edge detection in colour images with subpixel precision

International Nuclear Information System (INIS)

Schellhorn, M; Rosenberger, M; Correns, M; Blau, M; Goepfert, A; Rueckwardt, M; Linss, G

2010-01-01

Within the field of industrial image processing the use of colour cameras becomes ever more common. Increasingly the established black and white cameras are replaced by economical single-chip colour cameras with Bayer pattern. The use of the additional colour information is particularly important for recognition or inspection. Become interesting however also for the geometric metrology, if measuring tasks can be solved more robust or more exactly. However only few suitable algorithms are available, in order to detect edges with the necessary precision. All attempts require however additional computation expenditure. On the basis of a new filter for edge detection in colour images with subpixel precision, the implementation on a pre-processing hardware platform is presented. Hardware implemented filters offer the advantage that they can be used easily with existing measuring software, since after the filtering a single channel image is present, which unites the information of all colour channels. Advanced field programmable gate arrays represent an ideal platform for the parallel processing of multiple channels. The effective implementation presupposes however a high programming expenditure. On the example of the colour filter implementation, arising problems are analyzed and the chosen solution method is presented.

All optical programmable logic array (PLA)

Science.gov (United States)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

Science.gov (United States)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

International Nuclear Information System (INIS)

Szplet, R; Kalisz, J; Jachna, Z

2009-01-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second

A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

Science.gov (United States)

Berger, Andrew J; Page, Michael R; Jacob, Jan; Young, Justin R; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P; Johnston-Halperin, Ezekiel; Pelekhov, Denis V; Hammel, P Chris

2014-12-01

Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

Increasing feasibility of the field-programmable gate array implementation of an iterative image registration using a kernel-warping algorithm

Science.gov (United States)

Nguyen, An Hung; Guillemette, Thomas; Lambert, Andrew J.; Pickering, Mark R.; Garratt, Matthew A.

2017-09-01

Image registration is a fundamental image processing technique. It is used to spatially align two or more images that have been captured at different times, from different sensors, or from different viewpoints. There have been many algorithms proposed for this task. The most common of these being the well-known Lucas-Kanade (LK) and Horn-Schunck approaches. However, the main limitation of these approaches is the computational complexity required to implement the large number of iterations necessary for successful alignment of the images. Previously, a multi-pass image interpolation algorithm (MP-I2A) was developed to considerably reduce the number of iterations required for successful registration compared with the LK algorithm. This paper develops a kernel-warping algorithm (KWA), a modified version of the MP-I2A, which requires fewer iterations to successfully register two images and less memory space for the field-programmable gate array (FPGA) implementation than the MP-I2A. These reductions increase feasibility of the implementation of the proposed algorithm on FPGAs with very limited memory space and other hardware resources. A two-FPGA system rather than single FPGA system is successfully developed to implement the KWA in order to compensate insufficiency of hardware resources supported by one FPGA, and increase parallel processing ability and scalability of the system.

Development of field programmable gate array–based encryption module to mitigate man-in-the-middle attack for nuclear power plant data communication network

Directory of Open Access Journals (Sweden)

Mohamed Abdallah Elakrat

2018-06-01

Full Text Available This article presents a security module based on a field programmable gate array (FPGA to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA. Keywords: AES-128, Cyber Security, Encryption, Field Programmable Gate Array, I&C

Image processing with cellular nonlinear networks implemented on field-programmable gate arrays for real-time applications in nuclear fusion

International Nuclear Information System (INIS)

Palazzo, S.; Vagliasindi, G.; Arena, P.; Murari, A.; Mazon, D.; De Maack, A.

2010-01-01

In the past years cameras have become increasingly common tools in scientific applications. They are now quite systematically used in magnetic confinement fusion, to the point that infrared imaging is starting to be used systematically for real-time machine protection in major devices. However, in order to guarantee that the control system can always react rapidly in case of critical situations, the time required for the processing of the images must be as predictable as possible. The approach described in this paper combines the new computational paradigm of cellular nonlinear networks (CNNs) with field-programmable gate arrays and has been tested in an application for the detection of hot spots on the plasma facing components in JET. The developed system is able to perform real-time hot spot recognition, by processing the image stream captured by JET wide angle infrared camera, with the guarantee that computational time is constant and deterministic. The statistical results obtained from a quite extensive set of examples show that this solution approximates very well an ad hoc serial software algorithm, with no false or missed alarms and an almost perfect overlapping of alarm intervals. The computational time can be reduced to a millisecond time scale for 8 bit 496x560-sized images. Moreover, in our implementation, the computational time, besides being deterministic, is practically independent of the number of iterations performed by the CNN - unlike software CNN implementations.

A Fastbus module for trigger applications based on a digital signal processor and on programmable gate arrays

International Nuclear Information System (INIS)

Battaiotto, P.; Colavita, A.; Fratnik, F.; Lanceri, L.; Udine Univ.

1991-01-01

The new generation of DSP microprocessors based on RISC and Harvard-like architectures can conveniently take the place of specially built processors in fast trigger circuits for high-energy physics experiments. Presently available programmable gate arrays are well matched to them in speed and contribute to simplify the design of trigger circuits. Using these components, we designed and constructed a Fastbus module. We describe an application for the total-energy trigger of DELPHI, performing the readout of digitized calorimeter trigger data and some simple computations in less than 3 μs. (orig.)

CMOS gate array characterization procedures

Science.gov (United States)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

Physiologically gated microbeam radiation using a field emission x-ray source array

Energy Technology Data Exchange (ETDEWEB)

Chtcheprov, Pavel, E-mail: PavelC@unc.edu, E-mail: zhou@email.unc.edu [Department of Biomedical Engineering, University of North Carolina, 152 MacNider Hall, Campus Box 7575, Chapel Hill, North Carolina 27599 (United States); Burk, Laurel; Inscoe, Christina; Ger, Rachel; Hadsell, Michael; Lu, Jianping [Department of Physics and Astronomy, University of North Carolina, Phillips Hall, CB #3255, 120 East Cameron Avenue, Chapel Hill, North Carolina 27599 (United States); Yuan, Hong [Department of Radiology, University of North Carolina, 2006 Old Clinic, CB #7510, Chapel Hill, North Carolina 27599 (United States); Zhang, Lei [Department of Applied Physical Sciences, University of North Carolina, Chapman Hall, CB#3216, Chapel Hill, North Carolina 27599 (United States); Chang, Sha [Department of Radiation Oncology, University of North Carolina, 101 Manning Drive, Chapel Hill, North Carolina 27514 and UNC Lineberger Comprehensive Cancer Center, University of North Carolina, 101 Manning Drive, Chapel Hill, North Carolina 27514 (United States); Zhou, Otto, E-mail: PavelC@unc.edu, E-mail: zhou@email.unc.edu [Department of Physics and Astronomy, University of North Carolina, Phillips Hall, CB #3255, 120 East Cameron Avenue, Chapel Hill, North Carolina 27599 and UNC Lineberger Comprehensive Cancer Center, University of North Carolina, 101 Manning Drive, Chapel Hill, North Carolina 27514 (United States)

2014-08-15

Purpose: Microbeam radiation therapy (MRT) uses narrow planes of high dose radiation beams to treat cancerous tumors. This experimental therapy method based on synchrotron radiation has been shown to spare normal tissue at up to 1000 Gy of peak entrance dose while still being effective in tumor eradication and extending the lifetime of tumor-bearing small animal models. Motion during treatment can lead to significant movement of microbeam positions resulting in broader beam width and lower peak to valley dose ratio (PVDR), which reduces the effectiveness of MRT. Recently, the authors have demonstrated the feasibility of generating microbeam radiation for small animal treatment using a carbon nanotube (CNT) x-ray source array. The purpose of this study is to incorporate physiological gating to the CNT microbeam irradiator to minimize motion-induced microbeam blurring. Methods: The CNT field emission x-ray source array with a narrow line focal track was operated at 160 kVp. The x-ray radiation was collimated to a single 280 μm wide microbeam at entrance. The microbeam beam pattern was recorded using EBT2 Gafchromic{sup ©} films. For the feasibility study, a strip of EBT2 film was attached to an oscillating mechanical phantom mimicking mouse chest respiratory motion. The servo arm was put against a pressure sensor to monitor the motion. The film was irradiated with three microbeams under gated and nongated conditions and the full width at half maximums and PVDRs were compared. An in vivo study was also performed with adult male athymic mice. The liver was chosen as the target organ for proof of concept due to its large motion during respiration compared to other organs. The mouse was immobilized in a specialized mouse bed and anesthetized using isoflurane. A pressure sensor was attached to a mouse's chest to monitor its respiration. The output signal triggered the electron extraction voltage of the field emission source such that x-ray was generated only

Design verification enhancement of field programmable gate array-based safety-critical I&C system of nuclear power plant

Energy Technology Data Exchange (ETDEWEB)

Ahmed, Ibrahim [Department of Nuclear Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin-si, Gyeonggi-do 17104 (Korea, Republic of); Jung, Jaecheon, E-mail: jcjung@kings.ac.kr [Department of Nuclear Power Plant Engineering, KEPCO International Nuclear Graduate School, 658-91 Haemaji-ro, Seosang-myeon, Ulju-gun, Ulsan 45014 (Korea, Republic of); Heo, Gyunyoung [Department of Nuclear Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin-si, Gyeonggi-do 17104 (Korea, Republic of)

2017-06-15

Highlights: • An enhanced, systematic and integrated design verification approach is proposed for V&V of FPGA-based I&C system of NPP. • RPS bistable fixed setpoint trip algorithm is designed, analyzed, verified and discussed using the proposed approaches. • The application of integrated verification approach simultaneously verified the entire design modules. • The applicability of the proposed V&V facilitated the design verification processes. - Abstract: Safety-critical instrumentation and control (I&C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. However, safety analysis for FPGA-based I&C systems, and verification and validation (V&V) assessments still remain important issues to be resolved, which are now become a global research point of interests. In this work, we proposed a systematic design and verification strategies from start to ready-to-use in form of model-based approaches for FPGA-based reactor protection system (RPS) that can lead to the enhancement of the design verification and validation processes. The proposed methodology stages are requirement analysis, enhanced functional flow block diagram (EFFBD) models, finite state machine with data path (FSMD) models, hardware description language (HDL) code development, and design verifications. The design verification stage includes unit test – Very high speed integrated circuit Hardware Description Language (VHDL) test and modified condition decision coverage (MC/DC) test, module test – MATLAB/Simulink Co-simulation test, and integration test – FPGA hardware test beds. To prove the adequacy of the proposed

Design verification enhancement of field programmable gate array-based safety-critical I&C system of nuclear power plant

International Nuclear Information System (INIS)

Ahmed, Ibrahim; Jung, Jaecheon; Heo, Gyunyoung

2017-01-01

Highlights: • An enhanced, systematic and integrated design verification approach is proposed for V&V of FPGA-based I&C system of NPP. • RPS bistable fixed setpoint trip algorithm is designed, analyzed, verified and discussed using the proposed approaches. • The application of integrated verification approach simultaneously verified the entire design modules. • The applicability of the proposed V&V facilitated the design verification processes. - Abstract: Safety-critical instrumentation and control (I&C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. However, safety analysis for FPGA-based I&C systems, and verification and validation (V&V) assessments still remain important issues to be resolved, which are now become a global research point of interests. In this work, we proposed a systematic design and verification strategies from start to ready-to-use in form of model-based approaches for FPGA-based reactor protection system (RPS) that can lead to the enhancement of the design verification and validation processes. The proposed methodology stages are requirement analysis, enhanced functional flow block diagram (EFFBD) models, finite state machine with data path (FSMD) models, hardware description language (HDL) code development, and design verifications. The design verification stage includes unit test – Very high speed integrated circuit Hardware Description Language (VHDL) test and modified condition decision coverage (MC/DC) test, module test – MATLAB/Simulink Co-simulation test, and integration test – FPGA hardware test beds. To prove the adequacy of the proposed

Field-programmable beam reconfiguring based on digitally-controlled coding metasurface

Science.gov (United States)

Wan, Xiang; Qi, Mei Qing; Chen, Tian Yi; Cui, Tie Jun

2016-02-01

Digital phase shifters have been applied in traditional phased array antennas to realize beam steering. However, the phase shifter deals with the phase of the induced current; hence, it has to be in the path of each element of the antenna array, making the phased array antennas very expensive. Metamaterials and/or metasurfaces enable the direct modulation of electromagnetic waves by designing subwavelength structures, which opens a new way to control the beam scanning. Here, we present a direct digital mechanism to control the scattered electromagnetic waves using coding metasurface, in which each unit cell loads a pin diode to produce binary coding states of “1” and “0”. Through data lines, the instant communications are established between the coding metasurface and the internal memory of field-programmable gate arrays (FPGA). Thus, we realize the digital modulation of electromagnetic waves, from which we present the field-programmable reflective antenna with good measurement performance. The proposed mechanism and functional device have great application potential in new-concept radar and communication systems.

Single event upset susceptibilities of latchup immune CMOS process programmable gate arrays

Science.gov (United States)

Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.; Tsubota, T. K.

Single event upsets (SEU) and latchup susceptibilities of complementary metal oxide semiconductor programmable gate arrays (CMOS PPGA's) were measured at the Lawrence Berkeley Laboratory 88-in. cyclotron facility with Xe (603 MeV), Cu (290 MeV), and Ar (180 MeV) ion beams. The PPGA devices tested were those which may be used in space. Most of the SEU measurements were taken with a newly constructed tester called the Bus Access Storage and Comparison System (BASACS) operating via a Macintosh II computer. When BASACS finds that an output does not match a prerecorded pattern, the state of all outputs, position in the test cycle, and other necessary information is transmitted and stored in the Macintosh. The upset rate was kept between 1 and 3 per second. After a sufficient number of errors are stored, the test is stopped and the total fluence of particles and total errors are recorded. The device power supply current was closely monitored to check for occurrence of latchup. Results of the tests are presented, indicating that some of the PPGA's are good candidates for selected space applications.

Programmable architecture for quantum computing

NARCIS (Netherlands)

Chen, J.; Wang, L.; Charbon, E.; Wang, B.

2013-01-01

A programmable architecture called “quantum FPGA (field-programmable gate array)” (QFPGA) is presented for quantum computing, which is a hybrid model combining the advantages of the qubus system and the measurement-based quantum computation. There are two kinds of buses in QFPGA, the local bus and

Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

Energy Technology Data Exchange (ETDEWEB)

Nylund, Gustav; Storm, Kristian; Torstensson, Henrik; Wallentin, Jesper; Borgström, Magnus T.; Hessman, Dan; Samuelson, Lars [Solid State Physics, Nanometer Structure Consortium, Lund University, Box 118, S-221 00 Lund (Sweden)

2013-12-04

We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Science.gov (United States)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Innovative Columnar Type of Grid Array SJ BIST HALT Method, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Ridgetop will develop a superior method for testing and qualifying columnar type of grid arrays such as field programmable gate arrays (FPGAs) packaged in column...

Gated field-emitter cathodes for high-power microwave applications

International Nuclear Information System (INIS)

Barasch, E.F.; Demroff, H.P.; Elliott, T.S.; Kasprowicz, T.B.; Lee, B.; Mazumdar, T.; McIntyre, P.M.; Pang, Y.; Smith, D.D.; Trost, H.J.

1992-01-01

Gated field-emitter cathodes have been fabricated on silicon wafers. Two fabrication approaches have been employed: a knife-edge array and a porous silicon structure. The knife-edge array consists of a pattern of knife-edges, sharpened to ∼200 A radius, configured with an insulated metal gate structure at a gap of ∼500 A. The porous silicon cathode consists of an insulating porous layer, containing pores of ∼50 A diameter, densely spaced in the native silicon, biased for field emission by a thin gate metallization on the surface. Emission current density of 20 A/cm 2 has been obtained with only 10 V bias. Fabrication processes and test results are presented. (Author) 4 figs., tab., 12 refs

Development of multi-channel gated integrator and PXI-DAQ system for nuclear detector arrays

International Nuclear Information System (INIS)

Kong Jie; Su Hong; Chen Zhiqiang; Dong Chengfu; Qian Yi; Gao Shanshan; Zhou Chaoyang; Lu Wan; Ye Ruiping; Ma Junbing

2010-01-01

A multi-channel gated integrator and PXI based data acquisition system have been developed for nuclear detector arrays with hundreds of detector units. The multi-channel gated integrator can be controlled by a programmable GI controller. The PXI-DAQ system consists of NI PXI-1033 chassis with several PXI-DAQ cards. The system software has a user-friendly GUI which is written in C language using LabWindows/CVI under Windows XP operating system. The performance of the PXI-DAQ system is very reliable and capable of handling event rate up to 40 kHz.

SWNT array resonant gate MOS transistor.

Science.gov (United States)

Arun, A; Campidelli, S; Filoramo, A; Derycke, V; Salet, P; Ionescu, A M; Goffman, M F

2011-02-04

We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

SWNT array resonant gate MOS transistor

International Nuclear Information System (INIS)

Arun, A; Salet, P; Ionescu, A M; Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F

2011-01-01

We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

Science.gov (United States)

Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

2013-01-01

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

Directory of Open Access Journals (Sweden)

Santiago T. Pérez Suárez

2013-12-01

Full Text Available This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Solar cell array for driving MOS type FET gate. MOS gata EFT gate kudoyo taiyo denchi array

Energy Technology Data Exchange (ETDEWEB)

Murakami, S; Yoshida, K; Yoshiki, T; Yamaguchi, Y; Nakayama, T; Owada, Y

1990-03-12

There has been a semiconductor relay utilizing MOS type FET (field effect transistor). Concerning the solar cells used for a semiconductor relay, it is required to separate the cells by forming insulating oxide films first and to form semiconductor layers by using many mask patterns, since a crystal semiconductor is used. Thereby its manufacturing process becomes complicated and laminification as well as thin film formation are difficult, In view of the above, this invention proposes a solar cell array for driving a MOS type FET gate consisting of amorphous silicon semiconductor cells, which are used for a semiconductor relay with solar cells generating electromotive power by the light of a light emitting diode and a MOS type FET that the power output of the above solar cells is supplied to its gate, and which are connected in series with many steps. 9 figs.

SWNT array resonant gate MOS transistor

Energy Technology Data Exchange (ETDEWEB)

Arun, A; Salet, P; Ionescu, A M [NanoLab, Ecole Polytechnique Federale de Lausanne, CH-1015, Lausanne (Switzerland); Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F, E-mail: marcelo.goffman@cea.fr [Laboratoire d' Electronique Moleculaire, SPEC (CNRS URA 2454), IRAMIS, CEA, Gif-sur-Yvette (France)

2011-02-04

We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

Science.gov (United States)

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

Science.gov (United States)

Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

2009-01-01

Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

Compensated readout for high-density MOS-gated memristor crossbar array

KAUST Repository

Zidan, Mohammed A.

2015-01-01

Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory readout process for high-density arrays, and analyze the tradeoff between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage-current effect in the high-density gated memristor array.

Field-Programmable Logic Devices with Optical Input Output

Science.gov (United States)

Szymanski, Ted H.; Saint-Laurent, Martin; Tyan, Victor; Au, Albert; Supmonchai, Boonchuay

2000-02-01

A field-programmable logic device (FPLD) with optical I O is described. FPLD s with optical I O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA s) on a 2 mm 2 mm die. The devices were fabricated through the Lucent Technologies Advanced Research Projects Agency Consortium for Optical and Optoelectronic Technologies in Computing (Lucent ARPA COOP) workshop by use of 0.5- m complementary metal-oxide semiconductor self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 4 crossbar switches, which can realize more than 190 10 6 unique programmable input output permutations. The same device scaled to a 2 cm 2 cm substrate could support as many as 4000 optical I O and 1 Tbit s of optical I O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

Science.gov (United States)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

Isotropic gates and large gamma detector arrays versus angular distributions

International Nuclear Information System (INIS)

Iacob, V.E.; Duchene, G.

1997-01-01

Angular information extracted from in-beam γ ray measurements are of great importance for γ ray multipolarity and nuclear spin assignments. In our days large Ge detector arrays became available allowing the measurements of extremely weak γ rays in almost 4π sr solid angle (e.g., EUROGAM detector array). Given the high detector efficiency it is common for the mean suppressed coincidence multiplicity to reach values as high as 4 to 6. Thus, it is possible to gate on particular γ rays in order to enhance the relative statistics of a definite reaction channel and/or a definite decaying path in the level scheme of the selected residual nucleus. As compared to angular correlations, the conditioned angular distribution spectra exhibit larger statistics because in the latter the gate-setting γ ray may be observed by all the detectors in the array, relaxing somehow the geometrical restrictions of the angular correlations. Since the in-beam γ ray emission is anisotropic one could inquire that gate setting as mentioned above, based on anisotropic γ ray which would perturb the angular distributions in the unfolded events. As our work proved, there is no reason to worry about this if the energy gate runs over the whole solid angle in an ideal 4π sr detector, i.e., if the gate is isotropic. In real quasi 4π sr detector arrays the corresponding quasi isotropic gate preserves the angular properties of the unfolded data, too. However extraction of precise angular distribution coefficient especially a 4 , requires the consideration of the deviation of the quasi isotropic gate relative to the (ideal) isotropic gate

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

Science.gov (United States)

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Developing a gate-array capability at a research and development laboratory

Science.gov (United States)

Balch, J. W.; Current, K. W.; Magnuson, W. G., Jr.; Pocha, M. D.

1983-03-01

Experiences in developing a gate array capability for low volume applications in a research and development (R and D) laboratory are described. By purchasing unfinished wafers and doing the customization steps in-house. Turnaround time was shortened to as little as one week and the direct costs reduced to as low as $5K per design. Designs generally require fast turnaround (a few weeks to a few months) and very low volumes (1 to 25). Design costs must be kept at a minimum. After reviewing available commercial gate array design and fabrication services, it was determined that objectives would best be met by using existing internal integrated circuit fabrication facilities, the COMPUTERVISION interactive graphics layout system, and extensive computational capabilities. The reasons and the approach taken for; selection for a particular gate array wafer, adapting a particular logic simulation program, and how layout aids were enhanced are discussed. Testing of the customized chips is described. The content, schedule, and results of the internal gate array course recently completed are discussed. Finally, problem areas and near term plans are presented.

Gate protective device for SOS array

Science.gov (United States)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

National Research Council Canada - National Science Library

Mumbru, Jose

2004-01-01

... holograms for these modules. The first chapter makes the case that a direct interface between an optical memory and a chip integrating detectors and logic circuitry can better utilize the high parallelism inherent in holographic modules...

Design and analysis of a dual mode CMOS field programmable analog array

International Nuclear Information System (INIS)

Cheng Xiaoyan; Yang Haigang; Yin Tao; Wu Qisong; Zhang Hongfeng; Liu Fei

2014-01-01

This paper presents a novel field-programmable analog array (FPAA) architecture featuring a dual mode including discrete-time (DT) and continuous-time (CT) operation modes, along with a highly routable connection boxes (CBs) based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted optimal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%. (semiconductor integrated circuits)

A prototype of programmable associative memory for track finding

International Nuclear Information System (INIS)

Bardi, A.; Belforte, S.; Dell'Orso, M.

1999-01-01

The authors present a device, based on the concept of associative memory for pattern recognition, dedicated to on-line track finding in high-energy physics experiments. A large pattern bank, describing all possible tracks, can be organized into Field Programmable Gate Arrays where all patterns are compared in parallel to data coming from the detector during readout. Patterns, recognized among 2 66 possible combinations, are output in a few 30 MHz clock cycles. Programmability results in a flexible, simple architecture and it allows them to keep up smoothly with technology improvements. A 64 PAM array has been assembled on a prototype VME board and fully tested up to 30 MHz

Photon-Counting Arrays for Time-Resolved Imaging

Directory of Open Access Journals (Sweden)

I. Michel Antolovic

2016-06-01

Full Text Available The paper presents a camera comprising 512 × 128 pixels capable of single-photon detection and gating with a maximum frame rate of 156 kfps. The photon capture is performed through a gated single-photon avalanche diode that generates a digital pulse upon photon detection and through a digital one-bit counter. Gray levels are obtained through multiple counting and accumulation, while time-resolved imaging is achieved through a 4-ns gating window controlled with subnanosecond accuracy by a field-programmable gate array. The sensor, which is equipped with microlenses to enhance its effective fill factor, was electro-optically characterized in terms of sensitivity and uniformity. Several examples of capture of fast events are shown to demonstrate the suitability of the approach.

A programmable associative memory for track finding

International Nuclear Information System (INIS)

Bardi, A.; Belforte, S.; Donati, S.; Galeotti, S.; Giannetti, P.; Morsani, F.; Passuello, D.; Spinella, F.; Cerri, A.; Punzi, G.; Ristori, L.; Dell'Orso, M.; Meschi, E.; Leger, A.; Speer, T.; Wu, X.

1998-01-01

We present a device, based on the concept of associative memory for pattern recognition, dedicated to on-line track finding in high-energy physics experiments. A large pattern bank, describing all possible tracks, can be organized into field programmable gate arrays where all patterns are compared in parallel to data coming from the detector during readout. Patterns, recognized among 2 66 possible combinations, are output in a few 30 MHz clock cycles. Programmability results in a flexible, simple architecture and it allows to keep up smoothly with technology improvements. (orig.)

Laser-assisted electron emission from gated field-emitters

CERN Document Server

Ishizuka, H; Yokoo, K; Mimura, H; Shimawaki, H; Hosono, A

2002-01-01

Enhancement of electron emission by illumination of gated field-emitters was studied using a 100 mW cw YAG laser at a wavelength of 532 nm, intensities up to 10 sup 7 W/m sup 2 and mechanically chopped with a rise time of 4 mu s. When shining an array of 640 silicon emitters, the emission current responded quickly to on-off of the laser. The increase of the emission current was proportional to the basic emission current at low gate voltages, but it was saturated at approx 3 mu A as the basic current approached 100 mu A with the increase of gate voltage. The emission increase was proportional to the square root of laser power at low gate voltages and to the laser power at elevated gate voltages. For 1- and 3-tip silicon emitters, the rise and fall of the current due to on-off of the laser showed a significant time lag. The magnitude of emission increase was independent of the position of laser spot on the emitter base and reached 2 mu A at a basic current of 5 mu A without showing signs of saturation. The mech...

Design Principles of A Sigma-delta Flux-gate Magnetometer

Science.gov (United States)

Magnes, W.; Valavanoglou, A.; Pierce, D.; Frank, A.; Schwingenschuh, K.

A state-of-the-art flux-gate magnetometer is characterised by magnetic field resolution of several pT in a wide frequency range, low power consumption, low weight and high robustness. Therefore, flux-gate magnetometers are frequently used for ground-based Earth's field observation as well as for measurements aboard scientific space missions. But both traditional analogue and recently developed digital flux-gate magnetometers need low power and high-resolution analogue-to-digital converters for signal quan- tization. The disadvantage of such converters is the low radiation hardness. This fact has led to the idea of combining a traditional analogue flux-gate regulation circuit with that of a discretely realized sigma-delta converter in order to get a radiation hard and further miniaturized magnetometer. The name sigma-delta converter is derived from putting an integrator in front of a 1-bit delta modulator which forms the sigma-delta loop. It is followed by a digital decimation filter realized in a field-programmable gate array (FPGA). The flux-gate regulation and the sigma-delta loop are quite similar in the way of realizing the integrator and feedback circuit, which makes it easy to com- bine these two systems. The presented talk deals with the design principles and the results of a first bread board model.

Nano/CMOS architectures using a field-programmable nanowire interconnect

International Nuclear Information System (INIS)

Snider, Gregory S; Williams, R Stanley

2007-01-01

A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 x to 25 x), reduced power, slightly lower clock speeds, and high defect tolerance-an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires

The oxidized porous silicon field emission array

International Nuclear Information System (INIS)

Smith, D.D.; Demroff, H.P.; Elliott, T.S.; Kasprowicz, T.B.; Lee, B.; Mazumdar, T.K.; McIntyre, P.M.; Pang, Y.; Trost, H.J.

1993-01-01

The goal of developing a highly efficient microwave power source has led the authors to investigate new methods of electron field emission. One method presently under consideration involves the use of oxidized porous silicon thin films. The authors have used this technology to fabricate the first working field emission arrays from this substance. This approach reduces the diameter of an individual emitter to the nanometer scale. Tests of the first samples are encouraging, with extracted electron currents to nearly 1 mA resulting from less than 20 V of pulsed DC gate voltage. Modulated emission at 5 MHz was also observed. Developments of a full-scale emission array capable of delivering an electron beam at 18 GHz of minimum density 100 A/cm 2 is in progress

Direct protein detection with a nano-interdigitated array gate MOSFET.

Science.gov (United States)

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

Programmable cellular arrays. Faults testing and correcting in cellular arrays

International Nuclear Information System (INIS)

Cercel, L.

1978-03-01

A review of some recent researches about programmable cellular arrays in computing and digital processing of information systems is presented, and includes both combinational and sequential arrays, with full arbitrary behaviour, or which can realize better implementations of specialized blocks as: arithmetic units, counters, comparators, control systems, memory blocks, etc. Also, the paper presents applications of cellular arrays in microprogramming, in implementing of a specialized computer for matrix operations, in modeling of universal computing systems. The last section deals with problems of fault testing and correcting in cellular arrays. (author)

Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

CERN Document Server

Bonacini, Sandro; Kloukinas, Kostas

2007-01-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

Respiratory gating and multi field technique radiotherapy for esophageal cancer

International Nuclear Information System (INIS)

Ohta, Atsushi; Kaidu, Motoki; Tanabe, Satoshi

2017-01-01

To investigate the effects of a respiratory gating and multi field technique on the dose-volume histogram (DVH) in radiotherapy for esophageal cancer. Twenty patients who underwent four-dimensional computed tomography for esophageal cancer were included. We retrospectively created the four treatment plans for each patient, with or without the respiratory gating and multi field technique: No gating-2-field, No gating-4-field, Gating-2-field, and Gating-4-field plans. We compared the DVH parameters of the lung and heart in the No gating-2-field plan with the other three plans.Result In the comparison of the parameters in the No gating-2-field plan, there are significant differences in the Lung V 5Gy , V 20Gy , mean dose with all three plans and the Heart V 25Gy -V 40Gy with Gating-2-field plan, V 35Gy , V 40Gy , mean dose with No Gating-4-field plan and V 30Gy -V 40Gy , and mean dose with Gating-4-field plan. The lung parameters were smaller in the Gating-2-field plan and larger in the No gating-4-field and Gating-4-field plans. The heart parameters were all larger in the No gating-2-field plan. The lung parameters were reduced by the respiratory gating technique and increased by the multi field technique. The heart parameters were reduced by both techniques. It is important to select the optimal technique according to the risk of complications. (author)

A high performance gate drive for large gate turn off thyristors

Energy Technology Data Exchange (ETDEWEB)

Szilagyi, C.P.

1993-01-01

Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.

Universal programmable logic gate and routing method

Science.gov (United States)

Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

The Advanced Gamma-ray Imaging System (AGIS): Real Time Stereoscopic Array Trigger

Science.gov (United States)

Byrum, K.; Anderson, J.; Buckley, J.; Cundiff, T.; Dawson, J.; Drake, G.; Duke, C.; Haberichter, B.; Krawzcynski, H.; Krennrich, F.; Madhavan, A.; Schroedter, M.; Smith, A.

2009-05-01

Future large arrays of Imaging Atmospheric Cherenkov telescopes (IACTs) such as AGIS and CTA are conceived to comprise of 50 - 100 individual telescopes each having a camera with 10**3 to 10**4 pixels. To maximize the capabilities of such IACT arrays with a low energy threshold, a wide field of view and a low background rate, a sophisticated array trigger is required. We describe the design of a stereoscopic array trigger that calculates image parameters and then correlates them across a subset of telescopes. Fast Field Programmable Gate Array technology allows to use lookup tables at the array trigger level to form a real-time pattern recognition trigger tht capitalizes on the multiple view points of the shower at different shower core distances. A proof of principle system is currently under construction. It is based on 400 MHz FPGAs and the goal is for camera trigger rates of up to 10 MHz and a tunable cosmic-ray background suppression at the array level.

Isotropic gates in large gamma detector arrays versus angular distributions

International Nuclear Information System (INIS)

Iacob, V.E.; Duchene, G.

1997-01-01

The quality of the angular distribution information extracted from high-fold gamma-gamma coincidence events is analyzed. It is shown that a correct quasi-isotropic gate setting, available at the modern large gamma-ray detector arrays, essentially preserves the quality of the angular information. (orig.)

A FPGA-based signal processing unit for a GEM array detector

International Nuclear Information System (INIS)

Yen, W.W.; Chou, H.P.

2013-06-01

in the present study, a signal processing unit for a GEM one-dimensional array detector is presented to measure the trajectory of photoelectrons produced by cosmic X-rays. The present GEM array detector system has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies. The prototype of the processing unit is implemented using commercial field programmable gate array circuit boards. The FPGA based system is linked to a personal computer for testing and data analysis. Tests using simulated signals indicated that the FPGA-based signal processing unit has a good linearity and is flexible for parameter adjustment for various experimental conditions (authors)

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

Science.gov (United States)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

The Advanced Gamma-ray Imaging System (AGIS): Topological Array Trigger

Science.gov (United States)

Smith, Andrew W.

2010-03-01

AGIS is a concept for the next-generation ground-based gamma-ray observatory. It will be an array of 36 imaging atmospheric Cherenkov telescopes (IACTs) sensitive in the energy range from 50 GeV to 200 TeV. The required improvements in sensitivity, angular resolution, and reliability of operation relative to the present generation instruments imposes demanding technological and cost requirements on the design of the telescopes and on the triggering and readout systems for AGIS. To maximize the capabilities of large arrays of IACTs with a low energy threshold, a wide field of view and a low background rate, a sophisticated array trigger is required. We outline the status of the development of a stereoscopic array trigger that calculates image parameters and correlates them across a subset of telescopes. Field Programmable Gate Arrays (FPGAs) implement the real-time pattern recognition to suppress cosmic rays and night-sky background events. A proof of principle system is being developed to run at camera trigger rates up to 10MHz and array-level rates up to 10kHz.

FPGAs for software programmers

CERN Document Server

Hannig, Frank; Ziener, Daniel

2016-01-01

This book makes powerful Field Programmable Gate Array (FPGA) and reconfigurable technology accessible to software engineers by covering different state-of-the-art high-level synthesis approaches (e.g., OpenCL and several C-to-gates compilers). It introduces FPGA technology, its programming model, and how various applications can be implemented on FPGAs without going through low-level hardware design phases. Readers will get a realistic sense for problems that are suited for FPGAs and how to implement them from a software designer’s point of view. The authors demonstrate that FPGAs and their programming model reflect the needs of stream processing problems much better than traditional CPU or GPU architectures, making them well-suited for a wide variety of systems, from embedded systems performing sensor processing to large setups for Big Data number crunching. This book serves as an invaluable tool for software designers and FPGA design engineers who are interested in high design productivity through behavi...

DBPM signal processing with field programmable gate arrays

International Nuclear Information System (INIS)

Lai Longwei; Yi Xing; Zhang Ning; Yang Guisen; Wang Baopeng; Xiong Yun; Leng Yongbin; Yan Yingbing

2011-01-01

DBPM system performance is determined by the design and implementation of beam position signal processing algorithm. In order to develop the system, a beam position signal processing algorithm is implemented on FPGA. The hardware is a PMC board ICS-1554A-002 (GE Corp.) with FPGA chip XC5VSX95T. This paper adopts quadrature frequency mixing to down convert high frequency signal to base. Different from conventional method, the mixing is implemented by CORDIC algorithm. The algorithm theory and implementation details are discussed in this paper. As the board contains no front end gain controller, this paper introduces a published patent-pending technique that has been adopted to realize the function in digital logic. The whole design is implemented with VHDL language. An on-line evaluation has been carried on SSRF (Shanghai Synchrotron Radiation Facility)storage ring. Results indicate that the system turn-by-turn data can measure the real beam movement accurately,and system resolution is 1.1μm. (authors)

Nitrogen incorporated ultrananocrystalline diamond based field emitter array for a flat-panel x-ray source

International Nuclear Information System (INIS)

Posada, Chrystian M.; Grant, Edwin J.; Lee, Hyoung K.; Castaño, Carlos H.; Divan, Ralu; Sumant, Anirudha V.; Rosenmann, Daniel; Stan, Liliana

2014-01-01

A field emission based flat-panel transmission x-ray source is being developed as an alternative for medical and industrial imaging. A field emitter array (FEA) prototype based on nitrogen incorporated ultrananocrystalline diamond film has been fabricated to be used as the electron source of this flat panel x-ray source. The FEA prototype was developed using conventional microfabrication techniques. The field emission characteristics of the FEA prototype were evaluated. Results indicated that emission current densities of the order of 6 mA/cm 2 could be obtained at electric fields as low as 10 V/μm to 20 V/μm. During the prototype microfabrication process, issues such as delamination of the extraction gate and poor etching of the SiO 2 insulating layer located between the emitters and the extraction layer were encountered. Consequently, alternative FEA designs were investigated. Experimental and simulation data from the first FEA prototype were compared and the results were used to evaluate the performance of alternative single and double gate designs that would yield better field emission characteristics compared to the first FEA prototype. The best simulation results are obtained for the double gate FEA design, when the diameter of the collimator gate is around 2.6 times the diameter of the extraction gate

Structured-gate organic field-effect transistors

International Nuclear Information System (INIS)

Aljada, Muhsen; Pandey, Ajay K; Velusamy, Marappan; Burn, Paul L; Meredith, Paul; Namdas, Ebinazar B

2012-01-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO 2 ) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends. (paper)

Structured-gate organic field-effect transistors

Science.gov (United States)

Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

2012-06-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

Rapid wide-field Mueller matrix polarimetry imaging based on four photoelastic modulators with no moving parts.

Science.gov (United States)

Alali, Sanaz; Gribble, Adam; Vitkin, I Alex

2016-03-01

A new polarimetry method is demonstrated to image the entire Mueller matrix of a turbid sample using four photoelastic modulators (PEMs) and a charge coupled device (CCD) camera, with no moving parts. Accurate wide-field imaging is enabled with a field-programmable gate array (FPGA) optical gating technique and an evolutionary algorithm (EA) that optimizes imaging times. This technique accurately and rapidly measured the Mueller matrices of air, polarization elements, and turbid phantoms. The system should prove advantageous for Mueller matrix analysis of turbid samples (e.g., biological tissues) over large fields of view, in less than a second.

Roll Angle Estimation Using Thermopiles for a Flight Controlled Mortar

Science.gov (United States)

2012-06-01

Using Xilinx’s System generator, the entire design was implemented at a relatively high level within Malab’s Simulink. This allowed VHDL code to...thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA). These results demonstrate the...accurately estimated by processing the thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA

Investigation of Electromagnetic Signatures of a FPGA Using an APREL EM-ISIGHT System

Science.gov (United States)

2015-12-01

shelf (COTS) field- programmable gate array (FPGA) at the optimized factor levels established from the DOE and varying the programmed signal. This...signature using APREL’s EM-ISight automated system is hypothesized to be a novel way to accomplish this task. Research Questions The research...a field programmable gate array (FPGA) is the circuit board utilized for testing the inherent electromagnetic signature. Every device produces an

Multi-gated field emitters for a micro-column

International Nuclear Information System (INIS)

Mimura, Hidenori; Kioke, Akifumi; Aoki, Toru; Neo, Yoichiro; Yoshida, Tomoya; Nagao, Masayoshi

2011-01-01

We have developed a multi-gated field emitter (FE) such as a quadruple-gated FE with a three-stacked electrode lens and a quintuple-gated FE with a four-stacked electrode lens. Both the FEs can focus the electron beam. However, the quintuple-gated FE has a stronger electron convergence than the quadruple-gated FE, and a beam crossover is clearly observed for the quintuple-gated FE.

Field Emitter Arrays for a Free Electron Laser Application

CERN Document Server

Shing-Bruce-Li, Kevin; Ganter, Romain; Gobrecht, Jens; Raguin, Jean Yves; Rivkin, Leonid; Wrulich, Albin F

2004-01-01

The development of a new electron gun with the lowest possible emittance would help reducing the total length and cost of a free electron laser. Field emitter arrays (FEAs) are an attractive technology for electron sources of ultra high brightness. Indeed, several thousands of microscopic tips can be deposited on a 1 mm diameter area. Electrons are then extracted by applying voltage to a first grid layer close to the tip apexes, the so called gate layer, and focused by a second grid layer one micrometer above the tips. The typical aperture diameter of the gate and the focusing layer is in the range of one micrometer. One challenge for such cathodes is to produce peak currents in the ampere range since the usual applications of FEAs require less than milliampere. Encouraging peak current performances have been obtained by applying voltage pulses at low frequency between gate and tips. In this paper we report on different tip materials available on the market: diamond FEAs from Extreme Devices Inc., ZrC single ...

Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

Energy Technology Data Exchange (ETDEWEB)

Clément, N., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr; Han, X. L. [Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d' Ascq (France); Larrieu, G., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr [Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, Universite de Toulouse, 7 Avenue Colonel Roche, 31077 Toulouse (France)

2013-12-23

Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.

Trapped-ion quantum logic gates based on oscillating magnetic fields.

Science.gov (United States)

Ospelkaus, C; Langer, C E; Amini, J M; Brown, K R; Leibfried, D; Wineland, D J

2008-08-29

Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multiqubit quantum gates for trapped-ion quantum information processing (QIP). With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances between the ion crystal and the electrode surface. Magnetic-field-mediated gates have the potential to significantly reduce the overhead in laser-beam control and motional-state initialization compared to current QIP experiments with trapped ions and will eliminate spontaneous scattering, a fundamental source of decoherence in laser-mediated gates.

Programmable Input Mode Instrumentation Amplifier Using Multiple Output Current Conveyors

Directory of Open Access Journals (Sweden)

Pankiewicz Bogdan

2017-03-01

Full Text Available In this paper a programmable input mode instrumentation amplifier (IA utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field programmable gate array (FPGA, which shall condition analogue signals to be next converted by an analogue-to-digital converter (ADC. IA is designed in AMS 0.35 µm CMOS technology and the power supply is 3.3 V; the power consumption is approximately 9.1 mW. A linear input range in the voltage mode reaches ± 1.68 V or ± 250 µA in current mode. A passband of the IA is above 11 MHz. The amplifier works in class A, so its current supply is almost constant and does not cause noise disturbing nearby working precision analogue circuits.

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

Science.gov (United States)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Programmable delay unit incorporating a semi-custom integrated circuit

International Nuclear Information System (INIS)

Linstadt, E.

1985-04-01

The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

Graphical Environment Tools for Application to Gamma-Ray Energy Tracking Arrays

Energy Technology Data Exchange (ETDEWEB)

Todd, Richard A. [RIS Corp.; Radford, David C. [ORNL Physics Div.

2013-12-30

Highly segmented, position-sensitive germanium detector systems are being developed for nuclear physics research where traditional electronic signal processing with mixed analog and digital function blocks would be enormously complex and costly. Future systems will be constructed using pipelined processing of high-speed digitized signals as is done in the telecommunications industry. Techniques which provide rapid algorithm and system development for future systems are desirable. This project has used digital signal processing concepts and existing graphical system design tools to develop a set of re-usable modular functions and libraries targeted for the nuclear physics community. Researchers working with complex nuclear detector arrays such as the Gamma-Ray Energy Tracking Array (GRETA) have been able to construct advanced data processing algorithms for implementation in field programmable gate arrays (FPGAs) through application of these library functions using intuitive graphical interfaces.

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

Energy Technology Data Exchange (ETDEWEB)

Bonacini, S

2007-11-15

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

Science.gov (United States)

Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

2018-02-01

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

A programmable delay unit incorporating a semi-custom integrated circuit

International Nuclear Information System (INIS)

Linstadt, E.

1985-01-01

The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

A synchronous serial bus for multidimensional array acoustic logging tool

Science.gov (United States)

Men, Baiyong; Ju, Xiaodong; Lu, Junqiang; Qiao, Wenxiao

2016-12-01

In high-temperature and spatial borehole applications, a distributed structure is employed in a multidimensional array acoustic logging tool (MDALT) based on a phased array technique for electronic systems. However, new challenges, such as synchronous multichannel data acquisition, multinode real-time control and bulk data transmission in a limited interval, have emerged. To address these challenges, we developed a synchronous serial bus (SSB) in this study. SSB works in a half-duplex mode via a master-slave architecture. It also consists of a single master, several slaves, a differential clock line and a differential data line. The clock line is simplex, whereas the data line is half-duplex and synchronous to the clock line. A reliable communication between the master and the slaves with real-time adjustment of synchronisation is achieved by rationally designing the frame format and protocol of communication and by introducing a scramble code and a Hamming error-correcting code. The control logic of the master and the slaves is realized in field programmable gate array (FPGA) or complex programmable logic device (CPLD). The clock speed of SSB is 10 MHz, the effective data rate of the bulk data transmission is over 99%, and the synchronous errors amongst the slaves are less than 10 ns. Room-temperature test, high-temperature test (175 °C) and field test demonstrate that the proposed SSB is qualified for MDALT.

Tests of the gated mode for Belle II pixel detector

Energy Technology Data Exchange (ETDEWEB)

Prinker, Eduard [Max-Planck-Institute for Physics, Munich (Germany); Collaboration: Belle II-Collaboration

2015-07-01

DEPFET pixel detectors offer intrinsic amplification and very high signal to noise ratio. They form an integral building block for the vertex detector system of the Belle II experiment, which will start data taking in the year 2017 at the SuperKEKB Collider in Japan. A special Test board (Hybrid4) is used, which contains a small version of the DEPFET sensor with a read-out (DCD) and a steering chip (Switcher) attached, both controlled by a field-programmable gate array (FPGA) as the central interface to the computer. In order to keep the luminosity of the collider constant over time, the particle bunch currents have to be topped off by injecting additional bunches at a rate of 50 Hz. The particles in the daughter bunches produce a high rate of background (noisy bunches) for a short period of time, saturating the occupancy of the sensor. Operating the DEPFET sensor in a Gated Mode allows preserving the signals from collisions of normal bunches while protecting the pixels from background signals of the passing noisy bunches. An overview of the Gated Mode and first results is presented.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

Science.gov (United States)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

High Performance Systolic Array Core Architecture Design for DNA Sequencer

Directory of Open Access Journals (Sweden)

Saiful Nurdin Dayana

2018-01-01

Full Text Available This paper presents a high performance systolic array (SA core architecture design for Deoxyribonucleic Acid (DNA sequencer. The core implements the affine gap penalty score Smith-Waterman (SW algorithm. This time-consuming local alignment algorithm guarantees optimal alignment between DNA sequences, but it requires quadratic computation time when performed on standard desktop computers. The use of linear SA decreases the time complexity from quadratic to linear. In addition, with the exponential growth of DNA databases, the SA architecture is used to overcome the timing issue. In this work, the SW algorithm has been captured using Verilog Hardware Description Language (HDL and simulated using Xilinx ISIM simulator. The proposed design has been implemented in Xilinx Virtex -6 Field Programmable Gate Array (FPGA and improved in the core area by 90% reduction.

An evaluation of gating window size, delivery method, and composite field dosimetry of respiratory-gated IMRT

International Nuclear Information System (INIS)

Hugo, Geoffrey D.; Agazaryan, Nzhde; Solberg, Timothy D.

2002-01-01

A respiratory gating system has been developed based on a commercial patient positioning system. The purpose of this study is to investigate the ability of the gating system to reproduce normal, nongated IMRT operation and to quantify the errors produced by delivering a nongated IMRT treatment onto a moving target. A moving phantom capable of simultaneous two-dimensional motion was built, and an analytical liver motion function was used to drive the phantom. Studies were performed to assess the effect of gating window size and choice of delivery method (segmented and dynamic multileaf collimation). Additionally, two multiple field IMRT cases were delivered to quantify the error in gated and nongated IMRT with motion. Dosimetric error between nonmoving and moving deliveries is related to gating window size. By reducing the window size, the error can be reduced. Delivery error can be reduced for both dynamic and segmented delivery with gating. For the implementation of dynamic IMRT delivery in this study, dynamic delivery was found to generate larger delivery errors than segmented delivery in most cases studied. For multiple field IMRT delivery, the largest errors were generated in regions where high field modulation was present parallel to the axis of motion. Gating was found to reduce these large errors to clinically acceptable levels

Trapped-ion quantum logic gates based on oscillating magnetic fields

Science.gov (United States)

Ospelkaus, Christian; Langer, Christopher E.; Amini, Jason M.; Brown, Kenton R.; Leibfried, Dietrich; Wineland, David J.

2009-05-01

Oscillating magnetic fields and field gradients can be used to implement single-qubit rotations and entangling multiqubit quantum gates for trapped-ion quantum information processing. With fields generated by currents in microfabricated surface-electrode traps, it should be possible to achieve gate speeds that are comparable to those of optically induced gates for realistic distances between the ions and the electrode surface. Magnetic-field-mediated gates have the potential to significantly reduce the overhead in laser-beam control and motional-state initialization compared to current QIP experiments with trapped ions and will eliminate spontaneous scattering decoherence, a fundamental source of decoherence in laser-mediated gates. A potentially beneficial environment for the implementation of such schemes is a cryogenic ion trap, because small length scale traps with low motional heating rates can be realized. A cryogenic ion trap experiment is currently under construction at NIST.

Dependable Design Flow for Protection Systems using Programmable Logic Devices

CERN Document Server

Kwiatkowski, M

2011-01-01

Programmable Logic Devices (PLD) such as Field Programmable Gate Arrays (FPGA) are becoming more prevalent in protection and safety-related electronic systems. When employing such programmable logic devices, extra care and attention needs to be taken. The final synthesis result, used to generate the bit-stream to program the device, must be shown to meet the design’s requirements. This paper describes how to maximize confidence using techniques such as Formal Methods, exhaustive Hardware Description Language (HDL) code simulation and hardware testing. An example is given for one of the critical functions of the Safe Machine Parameters (SMP) system, used in the protection of the Large Hadron Collider (LHC) at CERN. CERN is also working towards an adaptation of the IEC- 61508 lifecycle designed for Machine Protection Systems (MPS), and the High Energy Physics environment, implementation of a protection function in FPGA code is only one small step of this lifecycle. The ultimate aim of this project is to cre...

Programmable logic controller performance enhancement by field programmable gate array based design.

Science.gov (United States)

Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

2015-01-01

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

Enhanced transconductance in a double-gate graphene field-effect transistor

Science.gov (United States)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Integration of biomolecular logic gates with field-effect transducers

Energy Technology Data Exchange (ETDEWEB)

Poghossian, A., E-mail: a.poghossian@fz-juelich.de [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Institute of Bio- and Nanosystems, Research Centre Juelich GmbH, D-52425 Juelich (Germany); Malzahn, K. [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Abouzar, M.H. [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Institute of Bio- and Nanosystems, Research Centre Juelich GmbH, D-52425 Juelich (Germany); Mehndiratta, P. [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Katz, E. [Department of Chemistry and Biomolecular Science, NanoBio Laboratory (NABLAB), Clarkson University, Potsdam, NY 13699-5810 (United States); Schoening, M.J. [Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, Campus Juelich, Heinrich-Mussmann-Str. 1, D-52428 Juelich (Germany); Institute of Bio- and Nanosystems, Research Centre Juelich GmbH, D-52425 Juelich (Germany)

2011-11-01

Highlights: > Enzyme-based AND/OR logic gates are integrated with a capacitive field-effect sensor. > The AND/OR logic gates compose of multi-enzyme system immobilised on sensor surface. > Logic gates were activated by different combinations of chemical inputs (analytes). > The logic output (pH change) produced by the enzymes was read out by the sensor. - Abstract: The integration of biomolecular logic gates with field-effect devices - the basic element of conventional electronic logic gates and computing - is one of the most attractive and promising approaches for the transformation of biomolecular logic principles into macroscopically useable electrical output signals. In this work, capacitive field-effect EIS (electrolyte-insulator-semiconductor) sensors based on a p-Si-SiO{sub 2}-Ta{sub 2}O{sub 5} structure modified with a multi-enzyme membrane have been used for electronic transduction of biochemical signals processed by enzyme-based OR and AND logic gates. The realised OR logic gate composes of two enzymes (glucose oxidase and esterase) and was activated by ethyl butyrate or/and glucose. The AND logic gate composes of three enzymes (invertase, mutarotase and glucose oxidase) and was activated by two chemical input signals: sucrose and dissolved oxygen. The developed integrated enzyme logic gates produce local pH changes at the EIS sensor surface as a result of biochemical reactions activated by different combinations of chemical input signals, while the pH value of the bulk solution remains unchanged. The pH-induced charge changes at the gate-insulator (Ta{sub 2}O{sub 5}) surface of the EIS transducer result in an electronic signal corresponding to the logic output produced by the immobilised enzymes. The logic output signals have been read out by means of a constant-capacitance method.

Integration of biomolecular logic gates with field-effect transducers

International Nuclear Information System (INIS)

Poghossian, A.; Malzahn, K.; Abouzar, M.H.; Mehndiratta, P.; Katz, E.; Schoening, M.J.

2011-01-01

Highlights: → Enzyme-based AND/OR logic gates are integrated with a capacitive field-effect sensor. → The AND/OR logic gates compose of multi-enzyme system immobilised on sensor surface. → Logic gates were activated by different combinations of chemical inputs (analytes). → The logic output (pH change) produced by the enzymes was read out by the sensor. - Abstract: The integration of biomolecular logic gates with field-effect devices - the basic element of conventional electronic logic gates and computing - is one of the most attractive and promising approaches for the transformation of biomolecular logic principles into macroscopically useable electrical output signals. In this work, capacitive field-effect EIS (electrolyte-insulator-semiconductor) sensors based on a p-Si-SiO 2 -Ta 2 O 5 structure modified with a multi-enzyme membrane have been used for electronic transduction of biochemical signals processed by enzyme-based OR and AND logic gates. The realised OR logic gate composes of two enzymes (glucose oxidase and esterase) and was activated by ethyl butyrate or/and glucose. The AND logic gate composes of three enzymes (invertase, mutarotase and glucose oxidase) and was activated by two chemical input signals: sucrose and dissolved oxygen. The developed integrated enzyme logic gates produce local pH changes at the EIS sensor surface as a result of biochemical reactions activated by different combinations of chemical input signals, while the pH value of the bulk solution remains unchanged. The pH-induced charge changes at the gate-insulator (Ta 2 O 5 ) surface of the EIS transducer result in an electronic signal corresponding to the logic output produced by the immobilised enzymes. The logic output signals have been read out by means of a constant-capacitance method.

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

International Nuclear Information System (INIS)

Bonacini, S.

2007-11-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

Science.gov (United States)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Protected gates for topological quantum field theories

International Nuclear Information System (INIS)

Beverland, Michael E.; Pastawski, Fernando; Preskill, John; Buerschaper, Oliver; Koenig, Robert; Sijher, Sumit

2016-01-01

We study restrictions on locality-preserving unitary logical gates for topological quantum codes in two spatial dimensions. A locality-preserving operation is one which maps local operators to local operators — for example, a constant-depth quantum circuit of geometrically local gates, or evolution for a constant time governed by a geometrically local bounded-strength Hamiltonian. Locality-preserving logical gates of topological codes are intrinsically fault tolerant because spatially localized errors remain localized, and hence sufficiently dilute errors remain correctable. By invoking general properties of two-dimensional topological field theories, we find that the locality-preserving logical gates are severely limited for codes which admit non-abelian anyons, in particular, there are no locality-preserving logical gates on the torus or the sphere with M punctures if the braiding of anyons is computationally universal. Furthermore, for Ising anyons on the M-punctured sphere, locality-preserving gates must be elements of the logical Pauli group. We derive these results by relating logical gates of a topological code to automorphisms of the Verlinde algebra of the corresponding anyon model, and by requiring the logical gates to be compatible with basis changes in the logical Hilbert space arising from local F-moves and the mapping class group

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

Millar James

2006-01-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

James Millar

2006-10-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

A Sea-of-Gates Style FPGA Placement Algorithm

Directory of Open Access Journals (Sweden)

Kalapi Roy

1996-01-01

Full Text Available Field Programmable Gate Arrays (FPGAs have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool developed specifically for this architecture.

Microscopy refocusing and dark-field imaging by using a simple LED array

OpenAIRE

Zheng, Guoan; Kolner, Christopher; Yang, Changhuei

2011-01-01

The condenser is one of the main components in most transmitted light compound microscopes. In this Letter, we show that such a condenser can be replaced by a programmable LED array to achieve greater imaging flexibility and functionality. Without mechanically scanning the sample or changing the microscope setup, the proposed approach can be used for dark-field imaging, bright-field imaging, microscopy sectioning, and digital refocusing. Images of a starfish embryo were acquired by using such...

Probing Dense Sprays with Gated, Picosecond, Digital Particle Field Holography

Directory of Open Access Journals (Sweden)

James Trolinger

2011-12-01

Full Text Available This paper describes work that demonstrated the feasibility of producing a gated digital holography system that is capable of producing high-resolution images of three-dimensional particle and structure details deep within dense particle fields of a spray. We developed a gated picosecond digital holocamera, using optical Kerr cell gating, to demonstrate features of gated digital holography that make it an exceptional candidate for this application. The Kerr cell gate shuttered the camera after the initial burst of ballistic and snake photons had been recorded, suppressing longer path, multiple scattered illumination. By starting with a CW laser without gating and then incorporating a picosecond laser and an optical Kerr gate, we were able to assess the imaging quality of the gated holograms, and determine improvement gained by gating. We produced high quality images of 50–200 μm diameter particles, hairs and USAF resolution charts from digital holograms recorded through turbid media where more than 98% of the light was scattered from the field. The system can gate pulses as short as 3 mm in pathlength (10 ps, enabling image-improving features of the system. The experiments lead us to the conclusion that this method has an excellent capability as a diagnostics tool in dense spray combustion research.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

Science.gov (United States)

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-12-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Leakage and field emission in side-gate graphene field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.; Cucolo, A. M. [Physics Department “E.R. Caianiello,” University of Salerno, via G. Paolo II, 84084 Fisciano (Italy); CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Giubileo, F. [CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Russo, S.; Unal, S. [Physics Department, University of Exeter, Stocker Road 6, Exeter, Devon EX4 4QL (United Kingdom); Passacantando, M.; Grossi, V. [Department of Physical and Chemical Sciences, University of L' Aquila, Via Vetoio, 67100 Coppito, L' Aquila (Italy)

2016-07-11

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current density as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.

Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

Science.gov (United States)

Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

Virtual Field Programmable Gate Array Triple Modular Redundant Cell Design

National Research Council Canada - National Science Library

Marty, Barbara

2004-01-01

.... A hardened microcontroller manages the configurations of each of the three FPGAs and monitors upset statistics. Advanced packaging is used to form a component that seems similar in form to the single FPGAs that the concept intends to replace.

Regulatory issues on using programmable logic device in nuclear power plants

International Nuclear Information System (INIS)

Park, G. Y.; Yu, Y. J.; Kim, H. T.; Kwon, Y. I.; Park, H. S.; Jeong, C. H.

2012-01-01

For replacing obsolete analog equipment in nuclear power plant, the Programmable Logic Devices (PLDs) using Hardware Description Language (HDL) have been widely adopted in digitalized Instrumentation and Control (I and C) systems because of its flexibility. For safety reviews on Nuclear Power Plants (NPPs,) qualifying digitalized safety I and C system using PLDs is an important issue. As an effort to provide regulatory position on using PLDs in safety I and C system, there is a research project to provide the regulatory positions against emerging issues involved with digitalisation of I and C system including using PLDs. Therefore, this paper addresses the important considerations for using PLDs in safety I and C systems such as diversity, independence and qualification, etc. In this point, this study focuses on technical reports for Field Programmable Gate Array (FPGA) from EPRI,. U.S. NRC, and relevant technical standards

Regulatory issues on using programmable logic device in nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

Park, G. Y.; Yu, Y. J.; Kim, H. T.; Kwon, Y. I.; Park, H. S.; Jeong, C. H. [Korea Institute of Nuclear Safety, Daejeon (Korea, Republic of)

2012-10-15

For replacing obsolete analog equipment in nuclear power plant, the Programmable Logic Devices (PLDs) using Hardware Description Language (HDL) have been widely adopted in digitalized Instrumentation and Control (I and C) systems because of its flexibility. For safety reviews on Nuclear Power Plants (NPPs,) qualifying digitalized safety I and C system using PLDs is an important issue. As an effort to provide regulatory position on using PLDs in safety I and C system, there is a research project to provide the regulatory positions against emerging issues involved with digitalisation of I and C system including using PLDs. Therefore, this paper addresses the important considerations for using PLDs in safety I and C systems such as diversity, independence and qualification, etc. In this point, this study focuses on technical reports for Field Programmable Gate Array (FPGA) from EPRI,. U.S. NRC, and relevant technical standards.

The Bill & Melinda Gates Foundation's grant-making programme for global health.

Science.gov (United States)

McCoy, David; Kembhavi, Gayatri; Patel, Jinesh; Luintel, Akish

2009-05-09

The Bill & Melinda Gates Foundation is a major contributor to global health; its influence on international health policy and the design of global health programmes and initiatives is profound. Although the foundation's contribution to global health generally receives acclaim, fairly little is known about its grant-making programme. We undertook an analysis of 1094 global health grants awarded between January, 1998, and December, 2007. We found that the total value of these grants was US$8.95 billion, of which $5.82 billion (65%) was shared by only 20 organisations. Nevertheless, a wide range of global health organisations, such as WHO, the GAVI Alliance, the World Bank, the Global Fund to Fight AIDS, Tuberculosis and Malaria, prominent universities, and non-governmental organisations received grants. $3.62 billion (40% of all funding) was given to supranational organisations. Of the remaining amount, 82% went to recipients based in the USA. Just over a third ($3.27 billion) of funding was allocated to research and development (mainly for vaccines and microbicides), or to basic science research. The findings of this report raise several questions about the foundation's global health grant-making programme, which needs further research and assessment.

Universal programmable quantum circuit schemes to emulate an operator

Energy Technology Data Exchange (ETDEWEB)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos [Department of Computer Science, Purdue University, West Lafayette, Indiana 47907 (United States); Kais, Sabre [Department of Chemistry, Department of Physics and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); Qatar Environment and Energy Research Institute, Doha (Qatar)

2012-12-21

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

Universal programmable quantum circuit schemes to emulate an operator

International Nuclear Information System (INIS)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos; Kais, Sabre

2012-01-01

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix–which can be non-unitary–in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e −iHt for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

Modelling of critical functions of nuclear reactors using Fild Programmable Gate Array; Modelagem de funcoes criticas de reatores nucleares utilizando Fild Programmable Gate Array

Energy Technology Data Exchange (ETDEWEB)

Teixeira, Pamela Iara Nolasco

2016-07-01

This paper proposes the development of a method using FPGA for critical security functions of a nuclear reactor. It was implemented two critical safety functions in VHDL, which is a way to describe, through a program, the behavior of a circuit or digital component. Two critical security functions, FCS Core Cooling, responsible for cooling the reactor core in the charts of the plant and also in the event of accidents involving loss of coolant and FCS Heat Transfer, responsible for cooling the reactor core in the event an accident with loss of coolant were implemented. In this Dissertation it was chosen the use of FPGA, because - due to the effects of aging, obsolescence issues, environmental degradation and mechanical failures - nuclear power plants need to replace their older systems by new ones based on digital technology. The technologies obtained using a system described in hardware language can be implemented in a programmable device, having the advantage of changing the code at any time. (author)

Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

Science.gov (United States)

Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

2016-01-26

Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

CERN Document Server

Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

2010-01-01

We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

High-speed two-frame gated camera for parameters measurement of Dragon-Ⅰ LIA

International Nuclear Information System (INIS)

Jiang Xiaoguo; Wang Yuan; Zhang Kaizhi; Shi Jinshui; Deng Jianjun; Li Jin

2012-01-01

The time-resolved measurement system which can work at very high speed is necessary in electron beam parameter diagnosis for Dragon-Ⅰ linear induction accelerator (LIA). A two-frame gated camera system has been developed and put into operation. The camera system adopts the optical principle of splitting the imaging light beam into two parts in the imaging space of a lens with long focus length. It includes lens coupled gated image intensifier, CCD camera, high speed shutter trigger device based on large scale field programmable gate array. The minimum exposure time for each image is about 3 ns, and the interval time between two images can be adjusted with a step of about 0.5 ns. The exposure time and the interval time can be independently adjusted and can reach about 1 s. The camera system features good linearity, good response uniformity, equivalent background illumination (EBI) as low as about 5 electrons per pixel per second, large adjustment range of sensitivity, and excel- lent flexibility and adaptability in applications. The camera system can capture two frame images at one time with the image size of 1024 x 1024. It meets the requirements of measurement for Dragon-Ⅰ LIA. (authors)

Tunnel field-effect transistor with two gated intrinsic regions

Directory of Open Access Journals (Sweden)

Y. Zhang

2014-07-01

Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.

Biological applications of an LCoS-BASED PROGRAMMABLE ARRAY MICROSCOPE (PAM)

NARCIS (Netherlands)

Hagen, G.M.; Caarls, W.; Thomas, M.; Hill, A.; Lidke, K.A.; Rieger, B.; Fritsch, C.; Van Geest, B.; Jovin, T.M.; Arndt-Jovin, D.J.

2007-01-01

We report on a new generation, commercial prototype of a programmable array optical sectioning fluorescence microscope (PAM) for rapid, light efficient 3D imaging of living specimens. The stand-alone module, including light source(s) and detector(s), features an innovative optical design and a

Nanofabrication of Arrays of Silicon Field Emitters with Vertical Silicon Nanowire Current Limiters and Self-Aligned Gates

Science.gov (United States)

2016-08-19

limiters, MEMS, NEMS, field emission, cold cathodes (Some figures may appear in colour only in the online journal) 1. Introduction Dense arrays of silicon... attention has been given to densely packed, highly ordered, top-down fabricated, single crystal vertical silicon nanowire devices that are embedded

Mechanical design of SST-GATE, a dual-mirror telescope for the Cherenkov Telescope Array

Science.gov (United States)

Dournaux, Jean-Laurent; Huet, Jean-Michel; Amans, Jean-Philippe; Dumas, Delphine; Laporte, Philippe; Sol, Hélène; Blake, Simon

2014-07-01

The Cherenkov Telescope Array (CTA) project aims to create the next generation Very High Energy (VHE) gamma-ray telescope array. It will be devoted to the observation of gamma rays over a wide band of energy, from a few tens of GeV to more than 100 TeV. Two sites are foreseen to view the whole sky where about 100 telescopes, composed of three different classes, related to the specific energy region to be investigated, will be installed. Among these, the Small Size class of Telescopes, SSTs, are devoted to the highest energy region, to beyond 100 TeV. Due to the large number of SSTs, their unit cost is an important parameter. At the Observatoire de Paris, we have designed a prototype of a Small Size Telescope named SST-GATE, based on the dual-mirror Schwarzschild-Couder optical formula, which has never before been implemented in the design of a telescope. Over the last two years, we developed a mechanical design for SST-GATE from the optical and preliminary mechanical designs made by the University of Durham. The integration of this telescope is currently in progress. Since the early stages of mechanical design of SST-GATE, finite element method has been used employing shape and topology optimization techniques to help design several elements of the telescope. This allowed optimization of the mechanical stiffness/mass ratio, leading to a lightweight and less expensive mechanical structure. These techniques and the resulting mechanical design are detailed in this paper. We will also describe the finite element analyses carried out to calculate the mechanical deformations and the stresses in the structure under observing and survival conditions.

Designing for Reuse of Configurable Logic

National Research Council Canada - National Science Library

Elm, Joseph P

2005-01-01

Field-programmable gate arrays (FPGAs) offer electronic systems designers the opportunity to reduce development cost, reduce time-to-market, increase system performance, and improve system adaptability...

Operating scheme for the light-emitting diode array of a volumetric display that exhibits multiple full-color dynamic images

Science.gov (United States)

Hirayama, Ryuji; Shiraki, Atsushi; Nakayama, Hirotaka; Kakue, Takashi; Shimobaba, Tomoyoshi; Ito, Tomoyoshi

2017-07-01

We designed and developed a control circuit for a three-dimensional (3-D) light-emitting diode (LED) array to be used in volumetric displays exhibiting full-color dynamic 3-D images. The circuit was implemented on a field-programmable gate array; therefore, pulse-width modulation, which requires high-speed processing, could be operated in real time. We experimentally evaluated the developed system by measuring the luminance of an LED with varying input and confirmed that the system works appropriately. In addition, we demonstrated that the volumetric display exhibits different full-color dynamic two-dimensional images in two orthogonal directions. Each of the exhibited images could be obtained only from the prescribed viewpoint. Such directional characteristics of the system are beneficial for applications, including digital signage, security systems, art, and amusement.

Apertureless near-field/far-field CW two-photon microscope for biological and material imaging and spectroscopic applications.

Science.gov (United States)

Nowak, Derek B; Lawrence, A J; Sánchez, Erik J

2010-12-10

We present the development of a versatile spectroscopic imaging tool to allow for imaging with single-molecule sensitivity and high spatial resolution. The microscope allows for near-field and subdiffraction-limited far-field imaging by integrating a shear-force microscope on top of a custom inverted microscope design. The instrument has the ability to image in ambient conditions with optical resolutions on the order of tens of nanometers in the near field. A single low-cost computer controls the microscope with a field programmable gate array data acquisition card. High spatial resolution imaging is achieved with an inexpensive CW multiphoton excitation source, using an apertureless probe and simplified optical pathways. The high-resolution, combined with high collection efficiency and single-molecule sensitive optical capabilities of the microscope, are demonstrated with a low-cost CW laser source as well as a mode-locked laser source.

Implementation of fractional order integrator/differentiator on field programmable gate array

OpenAIRE

K.P.S. Rana; V. Kumar; N. Mittra; N. Pramanik

2016-01-01

Concept of fractional order calculus is as old as the regular calculus. With the advent of high speed and cost effective computing power, now it is possible to model the real world control and signal processing problems using fractional order calculus. For the past two decades, applications of fractional order calculus, in system modeling, control and signal processing, have grown rapidly. This paper presents a systematic procedure for hardware implementation of the basic operators of fractio...

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

Science.gov (United States)

2008-07-01

Cruickshank, J. E. Gaffney and R. D. Melbourne, Australia : ACM, 1992. Proceedings of the 14th International Conference on Software Engineering. pp. 327-337... Ridge Compiler Collection Stone Ridge Technology 48 A.3 FPGA Architecture Survey Company Niche 3P plus 1 Technology Coarse-grain configurable IP

Nonlinear properties of gated graphene in a strong electromagnetic field

Energy Technology Data Exchange (ETDEWEB)

Avetisyan, A. A., E-mail: artakav@ysu.am; Djotyan, A. P., E-mail: adjotyan@ysu.am [Yerevan State University, Department of Physics (Armenia); Moulopoulos, K., E-mail: cos@ucy.ac.cy [University of Cyprus, Department of Physics (Cyprus)

2017-03-15

We develop a microscopic theory of a strong electromagnetic field interaction with gated bilayer graphene. Quantum kinetic equations for density matrix are obtained using a tight binding approach within second quantized Hamiltonian in an intense laser field. We show that adiabatically changing the gate potentials with time may produce (at resonant photon energy) a full inversion of the electron population with high density between valence and conduction bands. In the linear regime, excitonic absorption of an electromagnetic radiation in a graphene monolayer with opened energy gap is also studied.

Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Sanne, A.; Movva, H. C. P.; Kang, S.; McClellan, C.; Corbet, C. M.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

2014-02-24

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

Science.gov (United States)

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Dynamic Reconfiguration Of FPGA Nodes In A Distributed Computing System: A Preliminary Investigation

National Research Council Canada - National Science Library

Nixon, Patrick

2002-01-01

This report results from a contract tasking Trinity College, Dublin to investigate a specialized portion of a heterogeneous information system, specifically, Field Programmable Gate Array (FPGA)-based nodes...

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

Science.gov (United States)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Wind loads on flat plate photovoltaic array fields

Science.gov (United States)

Miller, R. D.; Zimmerman, D. K.

1981-01-01

The results of an experimental analysis (boundary layer wind tunnel test) of the aerodynamic forces resulting from winds acting on flat plate photovoltaic arrays are presented. Local pressure coefficient distributions and normal force coefficients on the arrays are shown and compared to theoretical results. Parameters that were varied when determining the aerodynamic forces included tilt angle, array separation, ground clearance, protective wind barriers, and the effect of the wind velocity profile. Recommended design wind forces and pressures are presented, which envelop the test results for winds perpendicular to the array's longitudinal axis. This wind direction produces the maximum wind loads on the arrays except at the array edge where oblique winds produce larger edge pressure loads. The arrays located at the outer boundary of an array field have a protective influence on the interior arrays of the field. A significant decrease of the array wind loads were recorded in the wind tunnel test on array panels located behind a fence and/or interior to the array field compared to the arrays on the boundary and unprotected from the wind. The magnitude of this decrease was the same whether caused by a fence or upwind arrays.

A programmable systolic trigger processor for FERA bus data

International Nuclear Information System (INIS)

Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

1992-09-01

A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

International Nuclear Information System (INIS)

Chen Kai; Liu Shubin; An Qi

2010-01-01

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA's Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable. (authors)

Reconfigurable Environmentally Aware Computing Technology for Earth Observing Systems (7284-060), Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Over the past decade, many research groups have developed reconfigurable computing systems built from Field Programmable Gate Arrays (FPGAs) for on-board processing...

Radiation-Tolerant Reprogrammable FPGA for Digital Signal Processing Circuits, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — Field Programmable Gate Arrays are a widely used technology; however, they are generally limited in reprogrammability. Radiation hard, low power and high density...

A comparative design view for accurate control of servos using a field programmable gate array

International Nuclear Information System (INIS)

Tickle, A J; Harvey, P K; Smith, J S; Wu, F; Buckle, J R

2009-01-01

An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions. Altera DSP Builder presents designers and users with an alternate approach when creating their systems by employing a blockset similar to that already used in Simulink. The application considered in this paper is the design of a Pulse Width Modulation (PWM) system for use in stereo vision. PWM can replace a digital-to-analogue converter to control audio speakers, LED intensity, motor speed, and servo position. Rather than the conventional HDL coding approach this Simulink approach provides an easy understanding platform to the PWM design. This paper includes a comparison between two approaches regarding resource usage and flexibility etc. Included is how DSP Builder manipulates an onboard clock signal, in order to create the control pulses to the 'raw' coding of a PWM generator in VHDL. Both methods were shown to a selection of people and their views on which version they would subsequently use in their relative fields is discussed.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

Science.gov (United States)

Foster, D. L.

2012-01-01

For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

Rad-Hard and ULP FPGA with "Full" Functionality, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

Digital acquisition and wavelength control of seed laser for space-based Lidar applications, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — This SBIR Phase I proposes to establish the feasibility of using a space qualifiable Field Programmable Gate Array (FPGA) based digital controller to autonomously...

Modeling nanowire and double-gate junctionless field-effect transistors

CERN Document Server

Jazaeri, Farzan

2018-01-01

The first book on the topic, this is a comprehensive introduction to the modeling and design of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages and limitations of the technology, the authors also provide a thorough overview of published analytical models for double-gate and nanowire configurations, before offering a general introduction to the EPFL charge-based model of junctionless FETs. Important features are introduced gradually, including nanowire versus double-gate equivalence, technological design space, junctionless FET performances, short channel effects, transcapacitances, asymmetric operation, thermal noise, interface traps, and the junction FET. Additional features compatible with biosensor applications are also discussed. This is a valuable resource for students and researchers looking to understand more about this new and fast developing field.

Field computation for two-dimensional array transducers with limited diffraction array beams.

Science.gov (United States)

Lu, Jian-Yu; Cheng, Jiqi

2005-10-01

A method is developed for calculating fields produced with a two-dimensional (2D) array transducer. This method decomposes an arbitrary 2D aperture weighting function into a set of limited diffraction array beams. Using the analytical expressions of limited diffraction beams, arbitrary continuous wave (cw) or pulse wave (pw) fields of 2D arrays can be obtained with a simple superposition of these beams. In addition, this method can be simplified and applied to a 1D array transducer of a finite or infinite elevation height. For beams produced with axially symmetric aperture weighting functions, this method can be reduced to the Fourier-Bessel method studied previously where an annular array transducer can be used. The advantage of the method is that it is accurate and computationally efficient, especially in regions that are not far from the surface of the transducer (near field), where it is important for medical imaging. Both computer simulations and a synthetic array experiment are carried out to verify the method. Results (Bessel beam, focused Gaussian beam, X wave and asymmetric array beams) show that the method is accurate as compared to that using the Rayleigh-Sommerfeld diffraction formula and agrees well with the experiment.

Microscopic gate-modulation imaging of charge and field distribution in polycrystalline organic transistors

Science.gov (United States)

Matsuoka, Satoshi; Tsutsumi, Jun'ya; Kamata, Toshihide; Hasegawa, Tatsuo

2018-04-01

In this work, a high-resolution microscopic gate-modulation imaging (μ-GMI) technique is successfully developed to visualize inhomogeneous charge and electric field distributions in operating organic thin-film transistors (TFTs). We conduct highly sensitive and diffraction-limit gate-modulation sensing for acquiring difference images of semiconducting channels between at gate-on and gate-off states that are biased at an alternate frequency of 15 Hz. As a result, we observe unexpectedly inhomogeneous distribution of positive and negative local gate-modulation (GM) signals at a probe photon energy of 1.85 eV in polycrystalline pentacene TFTs. Spectroscopic analyses based on a series of μ-GMI at various photon energies reveal that two distinct effects appear, simultaneously, within the polycrystalline pentacene channel layers: Negative GM signals at 1.85 eV originate from the second-derivative-like GM spectrum which is caused by the effect of charge accumulation, whereas positive GM signals originate from the first-derivative-like GM spectrum caused by the effect of leaked gate fields. Comparisons with polycrystalline morphologies indicate that grain centers are predominated by areas with high leaked gate fields due to the low charge density, whereas grain edges are predominantly high-charge-density areas with a certain spatial extension as associated with the concentrated carrier traps. Consequently, it is reasonably understood that larger grains lead to higher device mobility, but with greater inhomogeneity in charge distribution. These findings provide a clue to understand and improve device characteristics of polycrystalline TFTs.

An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

Directory of Open Access Journals (Sweden)

Chao Chen

2014-01-01

Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

Terahertz modulation based on surface plasmon resonance by self-gated graphene

Science.gov (United States)

Qian, Zhenhai; Yang, Dongxiao; Wang, Wei

2018-05-01

We theoretically and numerically investigate the extraordinary optical transmission through a terahertz metamaterial composed of metallic ring aperture arrays. The physical mechanism of different transmission peaks is elucidated to be magnetic polaritons or propagation surface plasmons with the help of surface current and electromagnetic field distributions at respective resonance frequencies. Then, we propose a high performance terahertz modulator based on the unique PSP resonance and combined with the metallic ring aperture arrays and a self-gated parallel-plate graphene capacitor. Because, to date, few researches have exhibited gate-controlled graphene modulation in terahertz region with low insertion losses, high modulation depth and low control voltage at room temperature. Here, we propose a 96% amplitude modulation with 0.7 dB insertion losses and ∼5.5 V gate voltage. Besides, we further study the absorption spectra of the modulator. When the transmission of modulator is very low, a 91% absorption can be achieved for avoiding damaging the source devices.

SpaceVPX Switch-Controller, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Crossfield Technology proposes a SpaceVPX (VITA 78) Switch-Controller Module implemented in a state-of-the-art Field Programmable Gate Array (FPGA) System on Chip...

Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

National Research Council Canada - National Science Library

Bardouleau, Graham; Kulp, James

2005-01-01

In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment...

Gate-induced carrier delocalization in quantum dot field effect transistors.

Science.gov (United States)

Turk, Michael E; Choi, Ji-Hyuk; Oh, Soong Ju; Fafarman, Aaron T; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R; Kikkawa, James M

2014-10-08

We study gate-controlled, low-temperature resistance and magnetotransport in indium-doped CdSe quantum dot field effect transistors. We show that using the gate to accumulate electrons in the quantum dot channel increases the "localization product" (localization length times dielectric constant) describing transport at the Fermi level, as expected for Fermi level changes near a mobility edge. Our measurements suggest that the localization length increases to significantly greater than the quantum dot diameter.

Shielding in ungated field emitter arrays

Energy Technology Data Exchange (ETDEWEB)

Harris, J. R. [U.S. Navy Reserve, Navy Operational Support Center New Orleans, New Orleans, Louisiana 70143 (United States); Jensen, K. L. [Code 6854, Naval Research Laboratory, Washington, D.C. 20375 (United States); Shiffler, D. A. [Directed Energy Directorate, Air Force Research Laboratory, Albuquerque, New Mexico 87117 (United States); Petillo, J. J. [Leidos, Billerica, Massachusetts 01821 (United States)

2015-05-18

Cathodes consisting of arrays of high aspect ratio field emitters are of great interest as sources of electron beams for vacuum electronic devices. The desire for high currents and current densities drives the cathode designer towards a denser array, but for ungated emitters, denser arrays also lead to increased shielding, in which the field enhancement factor β of each emitter is reduced due to the presence of the other emitters in the array. To facilitate the study of these arrays, we have developed a method for modeling high aspect ratio emitters using tapered dipole line charges. This method can be used to investigate proximity effects from similar emitters an arbitrary distance away and is much less computationally demanding than competing simulation approaches. Here, we introduce this method and use it to study shielding as a function of array geometry. Emitters with aspect ratios of 10{sup 2}–10{sup 4} are modeled, and the shielding-induced reduction in β is considered as a function of tip-to-tip spacing for emitter pairs and for large arrays with triangular and square unit cells. Shielding is found to be negligible when the emitter spacing is greater than the emitter height for the two-emitter array, or about 2.5 times the emitter height in the large arrays, in agreement with previously published results. Because the onset of shielding occurs at virtually the same emitter spacing in the square and triangular arrays, the triangular array is preferred for its higher emitter density at a given emitter spacing. The primary contribution to shielding in large arrays is found to come from emitters within a distance of three times the unit cell spacing for both square and triangular arrays.

High-Performance Linear Algebra Processor using FPGA

National Research Council Canada - National Science Library

Johnson, J

2004-01-01

With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

CMOS Active-Pixel Image Sensor With Simple Floating Gates

Science.gov (United States)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

The FPGA Pixel Array Detector

International Nuclear Information System (INIS)

Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

2013-01-01

A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

Implementation of an EPICS IOC on an Embedded Soft Core Processor Using Field Programmable Gate Arrays

International Nuclear Information System (INIS)

Douglas Curry; Alicia Hofler; Hai Dong; Trent Allison; J. Hovater; Kelly Mahoney

2005-01-01

At Jefferson Lab, we have been evaluating soft core processors running an EPICS IOC over μClinux on our custom hardware. A soft core processor is a flexible CPU architecture that is configured in the FPGA as opposed to a hard core processor which is fixed in silicon. Combined with an on-board Ethernet port, the technology incorporates the IOC and digital control hardware within a single FPGA. By eliminating the general purpose computer IOC, the designer is no longer tied to a specific platform, e.g. PC, VME, or VXI, to serve as the intermediary between the high level controls and the field hardware. This paper will discuss the design and development process as well as specific applications for JLab's next generation low-level RF controls and Machine Protection Systems

Field Emission of ITO-Coated Vertically Aligned Nanowire Array.

KAUST Repository

Lee, Changhwa

2010-04-29

An indium tin oxide (ITO)-coated vertically aligned nanowire array is fabricated, and the field emission characteristics of the nanowire array are investigated. An array of vertically aligned nanowires is considered an ideal structure for a field emitter because of its parallel orientation to the applied electric field. In this letter, a vertically aligned nanowire array is fabricated by modified conventional UV lithography and coated with 0.1-μm-thick ITO. The turn-on electric field intensity is about 2.0 V/μm, and the field enhancement factor, β, is approximately 3,078 when the gap for field emission is 0.6 μm, as measured with a nanomanipulator in a scanning electron microscope.

Field Emission of ITO-Coated Vertically Aligned Nanowire Array.

KAUST Repository

Lee, Changhwa; Lee, Seokwoo; Lee, Seung S

2010-01-01

An indium tin oxide (ITO)-coated vertically aligned nanowire array is fabricated, and the field emission characteristics of the nanowire array are investigated. An array of vertically aligned nanowires is considered an ideal structure for a field emitter because of its parallel orientation to the applied electric field. In this letter, a vertically aligned nanowire array is fabricated by modified conventional UV lithography and coated with 0.1-μm-thick ITO. The turn-on electric field intensity is about 2.0 V/μm, and the field enhancement factor, β, is approximately 3,078 when the gap for field emission is 0.6 μm, as measured with a nanomanipulator in a scanning electron microscope.

High-throughput gated photon counter with two detection windows programmable down to 70 ps width

Energy Technology Data Exchange (ETDEWEB)

Boso, Gianluca; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Zappa, Franco [Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza Leonardo Da Vinci 32, 20133 Milano (Italy); Mora, Alberto Dalla [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo Da Vinci 32, 20133 Milano (Italy)

2014-01-15

We present the design and characterization of a high-throughput gated photon counter able to count electrical pulses occurring within two well-defined and programmable detection windows. We extensively characterized and validated this instrument up to 100 Mcounts/s and with detection window width down to 70 ps. This instrument is suitable for many applications and proves to be a cost-effective and compact alternative to time-correlated single-photon counting equipment, thanks to its easy configurability, user-friendly interface, and fully adjustable settings via a Universal Serial Bus (USB) link to a remote computer.

High-throughput gated photon counter with two detection windows programmable down to 70 ps width

International Nuclear Information System (INIS)

Boso, Gianluca; Tosi, Alberto; Zappa, Franco; Mora, Alberto Dalla

2014-01-01

We present the design and characterization of a high-throughput gated photon counter able to count electrical pulses occurring within two well-defined and programmable detection windows. We extensively characterized and validated this instrument up to 100 Mcounts/s and with detection window width down to 70 ps. This instrument is suitable for many applications and proves to be a cost-effective and compact alternative to time-correlated single-photon counting equipment, thanks to its easy configurability, user-friendly interface, and fully adjustable settings via a Universal Serial Bus (USB) link to a remote computer

FPGA fabric specific optimization for RLT design

International Nuclear Information System (INIS)

Perwaiz, A.; Khan, S.A.

2010-01-01

This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced re configurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned Index Terms: Field Programmable Gate Arrays (FPGA), Compression Tree, Bit Width Reduction, Look Ahead Pipelining. (author)

Physical Fault Injection and Monitoring Methods for Programmable Devices

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00510096; Ferencei, Jozef

A method of detecting faults for evaluating the fault cross section of any field programmable gate array (FPGA) was developed and is described in the thesis. The incidence of single event effects in FPGAs was studied for different probe particles (proton, neutron, gamma) using this method. The existing accelerator infrastructure of the Nuclear Physics Institute in Rez was supplemented by more sensitive beam monitoring system to ensure that the tests are done under well defined beam conditions. The bit cross section of single event effects was measured for different types of configuration memories, clock signal phase and beam energies and intensities. The extended infrastructure served also for radiation testing of components which are planned to be used in the new Inner Tracking System (ITS) detector of the ALICE experiment and for selecting optimal fault mitigation techniques used for securing the design of the FPGA-based ITS readout unit against faults induced by ionizing radiation.

Pramana – Journal of Physics | Indian Academy of Sciences

Indian Academy of Sciences (India)

A new 4D chaotic system with hidden attractor and its engineering applications: Analog circuit design and field programmable gate array implementation .... On synchronisation of a class of complex chaotic systems with complex unknown ...

A Compression Algorithm for Field Programmable Gate Arrays in the Space Environment

Science.gov (United States)

2011-12-01

Decimation in Frequency DIT Decimation in Time DSP Digital Signal Processing DTFT Discrete Time Fourier Transform EDIF Electronic Data Interchange...standard electronic data interchange format ( EDIF ), compilation directly to bitstream for direct implementation on an FPGA, and hardware cosimulation

HARDWARE REALIZATION OF CANNY EDGE DETECTION ALGORITHM FOR UNDERWATER IMAGE SEGMENTATION USING FIELD PROGRAMMABLE GATE ARRAYS

Directory of Open Access Journals (Sweden)

ALEX RAJ S. M.

2017-09-01

Full Text Available Underwater images raise new challenges in the field of digital image processing technology in recent years because of its widespread applications. There are many tangled matters to be considered in processing of images collected from water medium due to the adverse effects imposed by the environment itself. Image segmentation is preferred as basal stage of many digital image processing techniques which distinguish multiple segments in an image and reveal the hidden crucial information required for a peculiar application. There are so many general purpose algorithms and techniques that have been developed for image segmentation. Discontinuity based segmentation are most promising approach for image segmentation, in which Canny Edge detection based segmentation is more preferred for its high level of noise immunity and ability to tackle underwater environment. Since dealing with real time underwater image segmentation algorithm, which is computationally complex enough, an efficient hardware implementation is to be considered. The FPGA based realization of the referred segmentation algorithm is presented in this paper.

Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

Energy Technology Data Exchange (ETDEWEB)

Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

2014-10-20

High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

International Nuclear Information System (INIS)

Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

2014-01-01

High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

Modelling of critical functions of nuclear reactors using Fild Programmable Gate Array

International Nuclear Information System (INIS)

Teixeira, Pamela Iara Nolasco

2016-01-01

This paper proposes the development of a method using FPGA for critical security functions of a nuclear reactor. It was implemented two critical safety functions in VHDL, which is a way to describe, through a program, the behavior of a circuit or digital component. Two critical security functions, FCS Core Cooling, responsible for cooling the reactor core in the charts of the plant and also in the event of accidents involving loss of coolant and FCS Heat Transfer, responsible for cooling the reactor core in the event an accident with loss of coolant were implemented. In this Dissertation it was chosen the use of FPGA, because - due to the effects of aging, obsolescence issues, environmental degradation and mechanical failures - nuclear power plants need to replace their older systems by new ones based on digital technology. The technologies obtained using a system described in hardware language can be implemented in a programmable device, having the advantage of changing the code at any time. (author)

Magnetomicrofluidics Circuits for Organizing Bioparticle Arrays

Science.gov (United States)

Abedini-Nassab, Roozbeh

Single-cell analysis (SCA) tools have important applications in the analysis of phenotypic heterogeneity, which is difficult or impossible to analyze in bulk cell culture or patient samples. SCA tools thus have a myriad of applications ranging from better credentialing of drug therapies to the analysis of rare latent cells harboring HIV infection or in Cancer. However, existing SCA systems usually lack the required combination of programmability, flexibility, and scalability necessary to enable the study of cell behaviors and cell-cell interactions at the scales sufficient to analyze extremely rare events. To advance the field, I have developed a novel, programmable, and massively-parallel SCA tool which is based on the principles of computer circuits. By integrating these magnetic circuits with microfluidics channels, I developed a platform that can organize a large number of single particles into an array in a controlled manner. My magnetophoretic circuits use passive elements constructed in patterned magnetic thin films to move cells along programmed tracks with an external rotating magnetic field. Cell motion along these tracks is analogous to the motion of charges in an electrical conductor, following a rule similar to Ohm's law. I have also developed asymmetric conductors, similar to electrical diodes, and storage sites for cells that behave similarly to electrical capacitors. I have also developed magnetophoretic circuits which use an overlaid pattern of microwires to switch single cells between different tracks. This switching mechanism, analogous to the operation of electronic transistors, is achieved by establishing a semiconducting gap in the magnetic pattern which can be changed from an insulating state to a conducting state by application of electrical current to an overlaid electrode. I performed an extensive study on the operation of transistors to optimize their geometry and minimize the required gate currents. By combining these elements into

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

Science.gov (United States)

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Phase retrieval in near-field measurements by array synthesis

DEFF Research Database (Denmark)

Wu, Jian; Larsen, Flemming Holm

1991-01-01

The phase retrieval problem in near-field antenna measurements is formulated as an array synthesis problem. As a test case, a particular synthesis algorithm has been used to retrieve the phase of a linear array......The phase retrieval problem in near-field antenna measurements is formulated as an array synthesis problem. As a test case, a particular synthesis algorithm has been used to retrieve the phase of a linear array...

Development and characterization of vertical double-gate MOS field-effect transistors

International Nuclear Information System (INIS)

Trellenkamp, S.

2004-07-01

Planar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 μA/μm and transconductances up to 480 μS/μm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated. (orig.)

New Developments in Error Detection and Correction Strategies for Critical Applications

Science.gov (United States)

Berg, Melanie; Label, Ken

2017-01-01

The presentation will cover a variety of mitigation strategies that were developed for critical applications. An emphasis is placed on strengths and weaknesses per mitigation technique as it pertains to different Field programmable gate array (FPGA) device types.

Flexible, fpga-based electronics for modular robots

DEFF Research Database (Denmark)

Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

2008-01-01

In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

A Time Domain Reflectometer with 100 ps precision implemented in a cost-effective FPGA for the test of the KLOE-2 Inner Tracker readout anodes

Energy Technology Data Exchange (ETDEWEB)

Bencivenni, G. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Czerwinski, E. [Institute of Physics, Jagiellonian University, Krakow (Poland); De Lucia, E. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); De Robertis, G. [INFN Sezione di Bari, Bari (Italy); Domenici, D. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Erriquez, O. [INFN Sezione di Bari, Bari (Italy); Dipartimento di Fisica, Università degli Studi di Bari, Bari (Italy); Fanizzi, G., E-mail: Giampiero.Fanizzi@ba.infn.it [INFN Sezione di Bari, Bari (Italy); Dipartimento di Fisica, Università degli Studi di Bari, Bari (Italy); Felici, G. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Liuzzi, R.; Loddo, F.; Mongelli, M. [INFN Sezione di Bari, Bari (Italy); Morello, G. [INFN gruppo collegato di Cosenza, Cosenza (Italy); Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Ranieri, A.; Valentino, V. [INFN Sezione di Bari, Bari (Italy)

2013-01-11

A Time Domain Reflectometer implemented in a single cost-effective Field Programmable Gate Array device is shown to achieve a precision around 100 ps. The Time to Digital Converter section of the device is based on a tapped delay line followed by an encoder and shows both Differential and Integral Non-Linearity below one least significant bit. The same Field Programmable Gate Array houses an 8051 8-bits microprocessor, for the control of the pulse signals generation, the acquisition and the first treatment of raw data. Principles of operation, architecture, performance and preliminary trials on the prototype are presented in this paper. As an example of possible application, the proposed circuit has been usefully used to perform the quality control of the micro-strip anodic planes of the Gas Electron Multiplier Inner Tracker of the KLOE-2 experiment.

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

Science.gov (United States)

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

Frequency Response of Graphene Electrolyte-Gated Field-Effect Transistors

Directory of Open Access Journals (Sweden)

Charles Mackin

2018-02-01

Full Text Available This work develops the first frequency-dependent small-signal model for graphene electrolyte-gated field-effect transistors (EGFETs. Graphene EGFETs are microfabricated to measure intrinsic voltage gain, frequency response, and to develop a frequency-dependent small-signal model. The transfer function of the graphene EGFET small-signal model is found to contain a unique pole due to a resistive element, which stems from electrolyte gating. Intrinsic voltage gain, cutoff frequency, and transition frequency for the microfabricated graphene EGFETs are approximately 3.1 V/V, 1.9 kHz, and 6.9 kHz, respectively. This work marks a critical step in the development of high-speed chemical and biological sensors using graphene EGFETs.

VHDL, FPGA and the master trigger controller of BES

International Nuclear Information System (INIS)

Guo Yanan; Wang Jufang; Zhao Dixin

1996-01-01

A Master Trigger Controller was made using fast FPGA (Field-Programmable Gate Array) instead of ECLIC (Emitter-Coupled Logic Integrated Circuit). VHDL (Verilog Hardware Description Language) was used in its design. The same performance was obtained with increased flexibility

Characterization of switching field distributions in Ising-like magnetic arrays

Science.gov (United States)

Fraleigh, Robert D.; Kempinger, Susan; Lammert, Paul E.; Zhang, Sheng; Crespi, Vincent H.; Schiffer, Peter; Samarth, Nitin

2017-04-01

The switching field distribution within arrays of single-domain ferromagnetic islands incorporates both island-island interactions and quenched disorder in island geometry. Separating these two contributions is important for disentangling the effects of disorder and interactions in the magnetization dynamics of island arrays. Using submicron, spatially resolved Kerr imaging in an external magnetic field for islands with perpendicular magnetic anisotropy, we map out the evolution of island arrays during hysteresis loops. Resolving and tracking individual islands across four different lattice types and a range of interisland spacings, we can extract the individual switching fields of every island and thereby quantitatively determine the contributions of interactions and quenched disorder in the arrays. The width of the switching field distribution is found to be well fitted by a simple model comprising the sum of an array-independent contribution (interpreted as disorder induced) and a term proportional to the maximum field the entire rest of the array could exert on a single island, i.e., in a fully polarized state. This supports the claim that disorder in these arrays is primarily a single-island property and provides a methodology by which to quantify such disorder.

Reconfigurable digital receiver design and application for instantaneous polarimetric measurement

NARCIS (Netherlands)

Wang, Z.; Krasnov, O.A.; Babur, G.P.; Ligthart, L.P.; Van der Zwan, F.

2011-01-01

This paper presents the development of a reconfigurable receiver to undertake challenging signal processing tasks for a novel polarimetric radar system. The field-programmable gate arrays (FPGAs)-based digital receiver samples incoming signals at intermediate frequency (IF) and processes signals

Browse Title Index

African Journals Online (AJOL)

Items 51 - 100 of 546 ... Vol 9, No 1 (2011), Application of Field programmable Gate Array to ... Vol 5, No 1 (2007), Barriers To Choice Of Women Occupation In ... Road Transport – Study Of Gibraltar Engineering Company, Aba, Nigeria, Abstract.

Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications

DEFF Research Database (Denmark)

Hegner, Jonas Stenbæk; Sindholt, Joakim; Nannarelli, Alberto

2012-01-01

Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation...

Reconstruction of sound fields with a spherical microphone array

DEFF Research Database (Denmark)

Fernandez Grande, Efren; Walton, Tim

2014-01-01

waves traveling in any direction. In particular, rigid sphere microphone arrays are robust, and have the favorable property that the scattering introduced by the array can be compensated for - making the array virtually transparent. This study examines a recently proposed sound field reconstruction...... method based on a point source expansion, i.e. equivalent source method, using a rigid spherical array. The study examines the capability of the method to distinguish between sound waves arriving from different directions (i.e., as a sound field separation method). This is representative of the potential...

Modeling of a quantized current and gate field-effect in gated three-terminal Cu2-αS electrochemical memristors

Directory of Open Access Journals (Sweden)

Y. Zhang

2015-02-01

Full Text Available Memristors exhibit very sharp off-to-on transitions with a large on/off resistance ratio. These remarkable characteristics coupled with their long retention time and very simple device geometry make them nearly ideal for three-terminal devices where the gate voltage can change their on/off voltages and/or simply turn them off, eliminating the need for bipolar operations. In this paper, we propose a cation migration-based computational model to explain the quantized current conduction and the gate field-effect in Cu2-αS memristors. Having tree-shaped conductive filaments inside a memristor is the reason for the quantized current conduction effect. Applying a gate voltage causes a deformation of the conductive filaments and thus controls the SET and the RESET process of the device.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

Science.gov (United States)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Field emission properties of ZnO nanosheet arrays

International Nuclear Information System (INIS)

Naik, Kusha Kumar; Rout, Chandra Sekhar; Khare, Ruchita; More, Mahendra A.; Chakravarty, Disha; Late, Dattatray J.; Thapa, Ranjit

2014-01-01

Electron emission properties of electrodeposited ZnO nanosheet arrays grown on Indium tin oxide coated glass substrates have been studied. Influence of oxygen vacancies on electronic structures and field emission properties of ZnO nanosheets are investigated using density functional theory. The oxygen vacancies produce unshared d electrons which form an impurity energy state; this causes shifting of Fermi level towards the vacuum, and so the barrier energy for electron extraction reduces. The ZnO nanosheet arrays exhibit a low turn-on field of 2.4 V/μm at 0.1 μA/cm 2 and current density of 50.1 μA/cm 2 at an applied field of 6.4 V/μm with field enhancement factor, β = 5812 and good field emission current stability. The nanosheet arrays grown by a facile electrodeposition process have great potential as robust high performance vertical structure electron emitters for future flat panel displays and vacuum electronic device applications

Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators

CERN Document Server

Kwiatkowski, Maciej; Todd, Benjamin

The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable firmware implementation and to use that method to implement a new firmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis. For that reason the reliable SMP hardware was preserved unchanged. The first version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP firmware was objectionable. There were new requirements and therefore the SMP specification was extended. On that occasion it was decided that the existing SMP firmware will not be continued and ...

Methods for the application of programmable logic devices in electronic protection systems for high energy particle accelerators

CERN Document Server

Kwiatkowski, M

2014-01-01

The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable rmware implementation and to use that method to implement a new rmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis [1]. For that reason the reliable SMP hardware was preserved unchanged. The rst version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP rmware was objectionable. There were new requirements and therefore the SMP speci cation was extended. On that occasion it was decided that the existing SMP rmware will not be continued and that it...

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Science.gov (United States)

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

Pulsed laser deposition of oxide gate dielectrics for pentacene organic field-effect transistors

International Nuclear Information System (INIS)

Yaginuma, S.; Yamaguchi, J.; Itaka, K.; Koinuma, H.

2005-01-01

We have fabricated Al 2 O 3 , LaAlO 3 (LAO), CaHfO 3 (CHO) and CaZrO 3 (CZO) thin films for the dielectric layers of field-effect transistors (FETs) by pulsed laser deposition (PLD). The films exhibited very smooth surfaces with root-mean-squares (rms) roughnesses of ∼1.3 A as evaluated by using atomic force microscopy (AFM). The breakdown electric fields of Al 2 O 3 , LAO, CHO and CZO films were 7, 6, 10 and 2 MV/cm, respectively. The magnitude of the leak current in each film was low enough to operate FET. We performed a comparative study of pentacene FET fabricated using these oxide dielectrics as gate insulators. High field-effect mobility of 1.4 cm 2 /V s and on/off current ratio of 10 7 were obtained in the pentacene FET using LAO gate insulating film. Use of the LAO films as gate dielectrics has been found to suppress the hysteresis of pentacene FET operations. The LAO films are relevant to the dielectric layer of organic FETs

GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping.

Science.gov (United States)

Alser, Mohammed; Hassan, Hasan; Xin, Hongyi; Ergin, Oguz; Mutlu, Onur; Alkan, Can

2017-11-01

High throughput DNA sequencing (HTS) technologies generate an excessive number of small DNA segments -called short reads- that cause significant computational burden. To analyze the entire genome, each of the billions of short reads must be mapped to a reference genome based on the similarity between a read and 'candidate' locations in that reference genome. The similarity measurement, called alignment, formulated as an approximate string matching problem, is the computational bottleneck because: (i) it is implemented using quadratic-time dynamic programming algorithms and (ii) the majority of candidate locations in the reference genome do not align with a given read due to high dissimilarity. Calculating the alignment of such incorrect candidate locations consumes an overwhelming majority of a modern read mapper's execution time. Therefore, it is crucial to develop a fast and effective filter that can detect incorrect candidate locations and eliminate them before invoking computationally costly alignment algorithms. We propose GateKeeper, a new hardware accelerator that functions as a pre-alignment step that quickly filters out most incorrect candidate locations. GateKeeper is the first design to accelerate pre-alignment using Field-Programmable Gate Arrays (FPGAs), which can perform pre-alignment much faster than software. When implemented on a single FPGA chip, GateKeeper maintains high accuracy (on average >96%) while providing, on average, 90-fold and 130-fold speedup over the state-of-the-art software pre-alignment techniques, Adjacency Filter and Shifted Hamming Distance (SHD), respectively. The addition of GateKeeper as a pre-alignment step can reduce the verification time of the mrFAST mapper by a factor of 10. https://github.com/BilkentCompGen/GateKeeper. mohammedalser@bilkent.edu.tr or onur.mutlu@inf.ethz.ch or calkan@cs.bilkent.edu.tr. Supplementary data are available at Bioinformatics online. © The Author (2017). Published by Oxford University Press

Time-area efficient multiplier-free recursive filter architectures for FPGA implementation

DEFF Research Database (Denmark)

Shajaan, Mohammad; Sørensen, John Aasted

1996-01-01

Simultaneous design of multiplier-free recursive filters (IIR filters) and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The hardware design methodology leads to high performance recursive filters with sampling frequencies in the interval 15-21 MHz (...

Complex envelope control of pulsed accelerating fields in superconducting cavities

CERN Document Server

Czarski, T

2010-01-01

A digital control system for superconducting cavities of a linear accelerator is presented in this work. FPGA (Field Programmable Gate Arrays) based controller, managed by MATLAB, was developed to investigate a novel firmware implementation. The LLRF - Low Level Radio Frequency system for FLASH project in DESY is introduced. Essential modeling of a cavity resonator with signal and power analysis is considered as a key approach to the control methods. An electrical model is represented by the non-stationary state space equation for the complex envelope of the cavity voltage driven by the current generator and the beam loading. The electromechanical model of the superconducting cavity resonator including the Lorentz force detuning has been developed for a simulation purpose. The digital signal processing is proposed for the field vector detection. The field vector sum control is considered for multiple cavities driven by one klystron. An algebraic, complex domain model is proposed for the system analysis. The c...

Supplement analysis for Greenville Gate access to Kirschbaum Field at Lawrence Livermore National Laboratory

International Nuclear Information System (INIS)

1997-01-01

The National Ignition Facility (NIF) Program proposes to provide additional access to the Kirschbaum Field construction laydown area. This additional access would alleviate traffic congestion at the East Gate entrance to Lawrence Livermore National Laboratory (LLNL) from Greenville Road during periods of heavy construction for the NIF. The new access would be located along the northeastern boundary of LLNL, about 305 m (1,000 ft) north of the East Gate entrance. The access road would extend from Greenville Road to the Kirschbaum Field construction laydown area and would traverse an existing storm water drainage channel. Two culverts, side by side, and a compacted road base would be installed across the channel. The security fence that runs parallel to Greenville Road would be modified to accommodate this new entrance and a vehicle gate would be installed at the entrance of Kirschbaum Field. The exiting shoulder along Greenville Road would be converted into a new turn lane for trucks entering the new gate. This analysis evaluates the impacts of constructing the Kirschbaum Field bridge and access gate at a different location than was analyzed in the NIF Project specific Analysis in the Final Programmatic environmental Impact Statement for Stockpile Stewardship and Management (SS and M PEIS) published in September 1996 (DOE/EIS-0236) and the Record of Decision published on December 19, 1996. Issues of concern addressed in this supplement analysis include potential impacts to wetlands downstream of the access bridge, potential impacts to the California red-legged frog (Rana aurora draytonii) listed as threatened on the federal listing pursuant to the Endangered Species Act of 1974, and potential impacts on the 100-yr floodplain along the Arroyo Las Positas

Generalized filtering of laser fields in optimal control theory: application to symmetry filtering of quantum gate operations

International Nuclear Information System (INIS)

Schroeder, Markus; Brown, Alex

2009-01-01

We present a modified version of a previously published algorithm (Gollub et al 2008 Phys. Rev. Lett.101 073002) for obtaining an optimized laser field with more general restrictions on the search space of the optimal field. The modification leads to enforcement of the constraints on the optimal field while maintaining good convergence behaviour in most cases. We demonstrate the general applicability of the algorithm by imposing constraints on the temporal symmetry of the optimal fields. The temporal symmetry is used to reduce the number of transitions that have to be optimized for quantum gate operations that involve inversion (NOT gate) or partial inversion (Hadamard gate) of the qubits in a three-dimensional model of ammonia.

Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

Directory of Open Access Journals (Sweden)

He Chen

2011-12-01

Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

Benchmark Modeling of the Near-Field and Far-Field Wave Effects of Wave Energy Arrays

Energy Technology Data Exchange (ETDEWEB)

Rhinefrank, Kenneth E; Haller, Merrick C; Ozkan-Haller, H Tuba

2013-01-26

This project is an industry-led partnership between Columbia Power Technologies and Oregon State University that will perform benchmark laboratory experiments and numerical modeling of the near-field and far-field impacts of wave scattering from an array of wave energy devices. These benchmark experimental observations will help to fill a gaping hole in our present knowledge of the near-field effects of multiple, floating wave energy converters and are a critical requirement for estimating the potential far-field environmental effects of wave energy arrays. The experiments will be performed at the Hinsdale Wave Research Laboratory (Oregon State University) and will utilize an array of newly developed Buoys' that are realistic, lab-scale floating power converters. The array of Buoys will be subjected to realistic, directional wave forcing (1:33 scale) that will approximate the expected conditions (waves and water depths) to be found off the Central Oregon Coast. Experimental observations will include comprehensive in-situ wave and current measurements as well as a suite of novel optical measurements. These new optical capabilities will include imaging of the 3D wave scattering using a binocular stereo camera system, as well as 3D device motion tracking using a newly acquired LED system. These observing systems will capture the 3D motion history of individual Buoys as well as resolve the 3D scattered wave field; thus resolving the constructive and destructive wave interference patterns produced by the array at high resolution. These data combined with the device motion tracking will provide necessary information for array design in order to balance array performance with the mitigation of far-field impacts. As a benchmark data set, these data will be an important resource for testing of models for wave/buoy interactions, buoy performance, and far-field effects on wave and current patterns due to the presence of arrays. Under the proposed project we will initiate

Operational method of a ferroelectric (Fe)-NAND flash memory array

International Nuclear Information System (INIS)

Wang, Shouyu; Takahashi, Mitue; Li, Qiu-Hong; Sakai, Shigeki; Takeuchi, Ken

2009-01-01

Operations of arrayed ferroelectric (Fe)-NAND flash memory cells: erase, program and read were demonstrated for the first time using a small cell array of four word lines by two NAND strings. The memory cells and select-gate transistors were all n-channel Pt/SrBi 2 Ta 2 O 9 /Hf-Al-O/Si ferroelectric-gate field effect transistors. The erase was performed by applying 10 µs wide 7 V pulses to n- and p-wells. The program was performed by applying 10 µs wide 7 V pulses to selected word lines. Accumulated read currents of 51 programmed patterns in the Fe-NAND flash memory cell array successfully showed distribution of the two distinguishable '0' and '1' states. The margin between the two states became wider by applying a verification technique in programming a cell out of the eight. Retention times of bit-line currents were obtained over 33 h for both the '0' and '1' states in a program pattern

Detection beyond Debye's length with an electrolyte-gated organic field-effect transistor.

Science.gov (United States)

Palazzo, Gerardo; De Tullio, Donato; Magliulo, Maria; Mallardi, Antonia; Intranuovo, Francesca; Mulla, Mohammad Yusuf; Favia, Pietro; Vikholm-Lundin, Inger; Torsi, Luisa

2015-02-04

Electrolyte-gated organic field-effect transistors are successfully used as biosensors to detect binding events occurring at distances from the transistor electronic channel that are much larger than the Debye length in highly concentrated solutions. The sensing mechanism is mainly capacitive and is due to the formation of Donnan's equilibria within the protein layer, leading to an extra capacitance (CDON) in series to the gating system. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and fabrication of carbon nanotube field-emission cathode with coaxial gate and ballast resistor.

Science.gov (United States)

Sun, Yonghai; Yeow, John T W; Jaffray, David A

2013-10-25

A low density vertically aligned carbon nanotube-based field-emission cathode with a ballast resistor and coaxial gate is designed and fabricated. The ballast resistor can overcome the non-uniformity of the local field-enhancement factor at the emitter apex. The self-aligned fabrication process of the coaxial gate can avoid the effects of emitter tip misalignment and height non-uniformity. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and implementation of a radiation hardened silicon on sapphire (SOS) embedded signal conditioning unit controller (SCUC) for the RAPID instrument on the Cluster satellites

International Nuclear Information System (INIS)

Ersland, L.

1992-07-01

The Cluster mission consistens of four spacecrafts equipped with instruments capable of making comprehensive measurements of plasma particles and electromagnetic fields. The RAPID (Research with Adaptive Particle Imaging Detectors) spectrometer is one of many instruments on board the Cluster satellites. It is designed for fast analysis of energetic electrons and ions with a complete coverage of the unit sphere in phase space. This thesis describes the development and testing of an embedded controller for the Spectroscopic Camera for Electrons, Neutral and Ion Compositions (SCENIC), which is a part of the RAPID instrument. The design is implemented in two different CMOS circuit technologies, namely Actel's Field Programmable Gate Arrays and GEC Plessey's CMOS Silicon On Sapphire (SOS) gate array. The prototypes of the SOS gate array have been verified and characterized. This includes measurements of DC and AC parameters under different conditions, including total dose of gamma irradiation. 42 refs., 92 figs., 44 tabs

Empirical Verification of Fault Models for FPGAs Operating in the Subcritical Voltage Region

DEFF Research Database (Denmark)

Birklykke, Alex Aaen; Koch, Peter; Prasad, Ramjee

2013-01-01

We present a rigorous empirical study of the bit-level error behavior of field programmable gate arrays operating in the subcricital voltage region. This region is of significant interest as voltage-scaling under normal circumstances is halted by the first occurrence of errors. However, accurate...

High speed numerical integration algorithm using FPGA | Razak ...

African Journals Online (AJOL)

Conventionally, numerical integration algorithm is executed in software and time consuming to accomplish. Field Programmable Gate Arrays (FPGAs) can be used as a much faster, very efficient and reliable alternative to implement the numerical integration algorithm. This paper proposed a hardware implementation of four ...

Phosphorus oxide gate dielectric for black phosphorus field effect transistors

Science.gov (United States)

Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

2018-04-01

The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

A Secure and Reliable High-Performance Field Programmable Gate Array for Information Processing

Science.gov (United States)

2012-03-01

receives a data token from its control input (shown as a horizontal arrow above). The value of this data token is used to select an input port. The input...dual of a merge. It receives a data token from its control input (shown as a horizontal arrow above). The value of this data token is used to select...Transactions on Computer-Aided Design of Intergrated Circuits and Systems, Vol. 26, No. 2, February 2007. [12] Cadence Design Systems, “Clock Domain

On photonic controlled phase gates

International Nuclear Information System (INIS)

Kieling, K; Eisert, J; O'Brien, J L

2010-01-01

As primitives for entanglement generation, controlled phase gates have a central role in quantum computing. Especially in ideas realizing instances of quantum computation in linear optical gate arrays, a closer look can be rewarding. In such architectures, all effective nonlinearities are induced by measurements. Hence the probability of success is a crucial parameter of such quantum gates. In this paper, we discuss this question for controlled phase gates that implement an arbitrary phase with one and two control qubits. Within the class of post-selected gates in dual-rail encoding with vacuum ancillas, we identify the optimal success probabilities. We construct networks that allow for implementation using current experimental capabilities in detail. The methods employed here appear specifically useful with the advent of integrated linear optical circuits, providing stable interferometers on monolithic structures.

LC-lens array with light field algorithm for 3D biomedical applications

Science.gov (United States)

Huang, Yi-Pai; Hsieh, Po-Yuan; Hassanfiroozi, Amir; Martinez, Manuel; Javidi, Bahram; Chu, Chao-Yu; Hsuan, Yun; Chu, Wen-Chun

2016-03-01

In this paper, liquid crystal lens (LC-lens) array was utilized in 3D bio-medical applications including 3D endoscope and light field microscope. Comparing with conventional plastic lens array, which was usually placed in 3D endoscope or light field microscope system to record image disparity, our LC-lens array has higher flexibility of electrically changing its focal length. By using LC-lens array, the working distance and image quality of 3D endoscope and microscope could be enhanced. Furthermore, the 2D/3D switching ability could be achieved if we turn off/on the electrical power on LClens array. In 3D endoscope case, a hexagonal micro LC-lens array with 350um diameter was placed at the front end of a 1mm diameter endoscope. With applying electric field on LC-lens array, the 3D specimen would be recorded as from seven micro-cameras with different disparity. We could calculate 3D construction of specimen with those micro images. In the other hand, if we turn off the electric field on LC-lens array, the conventional high resolution 2D endoscope image would be recorded. In light field microscope case, the LC-lens array was placed in front of the CMOS sensor. The main purpose of LC-lens array is to extend the refocusing distance of light field microscope, which is usually very narrow in focused light field microscope system, by montaging many light field images sequentially focusing on different depth. With adjusting focal length of LC-lens array from 2.4mm to 2.9mm, the refocusing distance was extended from 1mm to 11.3mm. Moreover, we could use a LC wedge to electrically shift the optics axis and increase the resolution of light field.

Comprehensive study of gate-terminated and source-terminated field-plate 0.13 µm NMOS transistors

International Nuclear Information System (INIS)

Chiu, Hsien-Chin; Lin, Shao-Wei; Cheng, Chia-Shih; Wei, Chien-Cheng

2008-01-01

This study systematically investigated microwave noise, power and linearity characteristics of field-plate (FP) 0.13 µm CMOS transistors in which the field-plate metal is connected to the gate terminal and the source terminal. The gate-terminated FP NMOS (FP-G NMOS) provided the best noise figure (NF) at 6 GHz compared with standard devices and the source-terminated FP device (FP-S NMOS) as the lowest gate resistance (R g ) was obtained by this structure. By adopting the field-plate metal in NMOS, both FP-S and FP-G devices achieved higher current density at high gate bias voltages. Moreover, these two devices also had higher efficiency under high drain-to-source voltages at the high input power swing. The third-order inter-modulation product (IM3) is −39.4 dBm for FP-S NMOS at P in of −20 dBm; the corresponding values for FP-G and standard devices are −34.9 dBm and −37.3 dBm, respectively. Experimental results indicate that the FP-G architecture is suitable for low noise applications and FP-S is suitable for high power and high linearity operation

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

Science.gov (United States)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Field-programmable custom computing technology architectures, tools, and applications

CERN Document Server

Luk, Wayne; Pocek, Ken

2000-01-01

Field-Programmable Custom Computing Technology: Architectures, Tools, and Applications brings together in one place important contributions and up-to-date research results in this fast-moving area. In seven selected chapters, the book describes the latest advances in architectures, design methods, and applications of field-programmable devices for high-performance reconfigurable systems. The contributors to this work were selected from the leading researchers and practitioners in the field. It will be valuable to anyone working or researching in the field of custom computing technology. It serves as an excellent reference, providing insight into some of the most challenging issues being examined today.

Microwave metamaterials—from passive to digital and programmable controls of electromagnetic waves

Science.gov (United States)

Cui, Tie Jun

2017-08-01

functions. We realised that when the digital state of a coding unit is controlled by a field programmable gate array, the programmable metamaterial, which is capable of manipulating electromagnetic waves in real time, can generate many different functions.

Engineering a spin-fet: spin-orbit phenomena and spin transport induced by a gate electric field

OpenAIRE

Cardoso, J. L.; Hernández-Saldaña, H.

2012-01-01

In this work, we show that a gate electric field, applied in the base of the field-effect devices, leads to inducing spin-orbit interactions (Rashba and linear Dresselhauss) and confines the transport electrons in a two-dimensional electron gas. On the basis of these phenomena we solve analytically the Pauli equation when the Rashba strength and the linear Dresselhaus one are equal, for a tuning value of the gate electric field $\\mathcal{E}_g^*$. Using the transfer matrix approach, we provide...

Multiplier-free DCT approximations for RF multi-beam digital aperture-array space imaging and directional sensing

International Nuclear Information System (INIS)

Potluri, U S; Madanayake, A; Rajapaksha, N; Cintra, R J; Bayer, F M

2012-01-01

Multi-beamforming is an important requirement for broadband space imaging applications based on dense aperture arrays (AAs). Usually, the discrete Fourier transform is the transform of choice for AA electromagnetic imaging. Here, the discrete cosine transform (DCT) is proposed as an alternative, enabling the use of emerging fast algorithms that offer greatly reduced complexity in digital arithmetic circuits. We propose two novel high-speed digital architectures for recently proposed fast algorithms (Bouguezel, Ahmad and Swamy 2008 Electron. Lett. 44 1249–50) (BAS-2008) and (Cintra and Bayer 2011 IEEE Signal Process. Lett. 18 579–82) (CB-2011) that provide good approximations to the DCT at zero multiplicative complexity. Further, we propose a novel DCT approximation having zero multiplicative complexity that is shown to be better for multi-beamforming AAs when compared to BAS-2008 and CB-2011. The far-field array pattern of ideal DCT, BAS-2008, CB-2011 and proposed approximation are investigated with error analysis. Extensive hardware realizations, implementation details and performance metrics are provided for synchronous field programmable gate array (FPGA) technology from Xilinx. The resource consumption and speed metrics of BAS-2008, CB-2011 and the proposed approximation are investigated as functions of system word size. The 8-bit versions are mapped to emerging asynchronous FPGAs leading to significantly increased real-time throughput with clock rates at up to 925.6 MHz implying the fastest DCT approximations using reconfigurable logic devices in the literature. (paper)

Optimization study on the magnetic field of superconducting Halbach Array magnet

Science.gov (United States)

Shen, Boyang; Geng, Jianzhao; Li, Chao; Zhang, Xiuchang; Fu, Lin; Zhang, Heng; Ma, Jun; Coombs, T. A.

2017-07-01

This paper presents the optimization on the strength and homogeneity of magnetic field from superconducting Halbach Array magnet. Conventional Halbach Array uses a special arrangement of permanent magnets which can generate homogeneous magnetic field. Superconducting Halbach Array utilizes High Temperature Superconductor (HTS) to construct an electromagnet to work below its critical temperature, which performs equivalently to the permanent magnet based Halbach Array. The simulations of superconducting Halbach Array were carried out using H-formulation based on B-dependent critical current density and bulk approximation, with the FEM platform COMSOL Multiphysics. The optimization focused on the coils' location, as well as the geometry and numbers of coils on the premise of maintaining the total amount of superconductor. Results show Halbach Array configuration based superconducting magnet is able to generate the magnetic field with intensity over 1 Tesla and improved homogeneity using proper optimization methods. Mathematical relation of these optimization parameters with the intensity and homogeneity of magnetic field was developed.

The transient electric field measurement system for EAST device

Energy Technology Data Exchange (ETDEWEB)

Wang, Y., E-mail: wayong@ipp.ac.cn [Institute of Plasma Physics, Chinese Academy of Sciences, Hefei, Anhui (China); Ji, Z.S. [Institute of Plasma Physics, Chinese Academy of Sciences, Hefei, Anhui (China); Zhu, C.M. [The Experiment & Verification Center of State Grid Electric Power Research Institute (The Automation Equipment EMC Lab. of State Grid Co.), Nanjing, Jiangsu (China); Zhang, Z.C.; Ma, T.F.; Xu, Z.H. [Institute of Plasma Physics, Chinese Academy of Sciences, Hefei, Anhui (China)

2016-11-15

The electromagnetic environment around the Experimental Advanced Superconducting Tokamak (EAST) device is very complex during plasma discharge experiment. In order to fully monitor the changes of electric field around the EAST device during plasma discharge, a transient electric field measurement system based on PCI eXtensions for Instrumentation (PXI) platform has been designed. A digitizer is used for high-speed data acquisition of raw signals from electric field sensors, and a Field Programmable Gate Array (FPGA) module is used for realizing an on-the-fly fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) algorithm including a beforehand identified antenna factor (AF) to achieve finally a calibrated and filtered electric field measurement, then these signals can be displayed and easily analyzed. The raw signals from electric field sensors are transferred through optical fiber by optical isolation to reduce electromagnetic interference (EMI). The high speed data streaming technology is used for data storage. A prototype of this system has been realized to measure the transient electric field strength, with the real-time processing and continuous acquisition ability of one channel of 14-bit resolution and up to 50 MHz sampling rate, and 6 KHz FFT frequency resolution.

Nucleic acid programmable protein array a just-in-time multiplexed protein expression and purification platform.

Science.gov (United States)

Qiu, Ji; LaBaer, Joshua

2011-01-01

Systematic study of proteins requires the availability of thousands of proteins in functional format. However, traditional recombinant protein expression and purification methods have many drawbacks for such study at the proteome level. We have developed an innovative in situ protein expression and capture system, namely NAPPA (nucleic acid programmable protein array), where C-terminal tagged proteins are expressed using an in vitro expression system and efficiently captured/purified by antitag antibodies coprinted at each spot. The NAPPA technology presented in this chapter enable researchers to produce and display fresh proteins just in time in a multiplexed high-throughput fashion and utilize them for various downstream biochemical researches of interest. This platform could revolutionize the field of functional proteomics with it ability to produce thousands of spatially separated proteins in high density with narrow dynamic rand of protein concentrations, reproducibly and functionally. Copyright © 2011 Elsevier Inc. All rights reserved.

Smith-Purcell radiation experiment using a field-emission array cathode

International Nuclear Information System (INIS)

Ishizuka, H.; Kawamura, Y.; Yokoo, K.; Shimawaki, H.; Hosono, A.

2000-01-01

We have recently started an experiment on visible Smith-Purcell (SP) radiation to examine practical applicability of a field-emission array (FEA) cathode to compact free electron lasers, placing emphasis on safe operation of the cathode as well as beam quality. The electron beam was generated by a 5 cm long triode which employed either a single- or double-gated FEA. Accelerating voltages of up to -40 and -100 kV were applied to the cathode by a regulated power supply and a small Van der Graaff generator, respectively. A 25 μA beam of up to 45 keV was routinely produced and a 5 μA 80 keV beam was also attained. The beam passed through a 1 mm wide slit in the anode and grazed the surface of a 2.5 cm long replica grating with a period of either 0.56 or 0.83 μm. The SP radiation has not been identified owing to irrelevant luminescence caused by the beam at the grating. Still it was confirmed that the FEA cathode is adequately durable and electron beams generated therefrom are sufficiently stable to be used for systematic measurements of radiation

Real-Time Plasma Control Tools for Advanced Tokamak Operation

International Nuclear Information System (INIS)

Varandas, C. A. F.; Sousa, J.; Rodrigues, A. P.; Carvalho, B. B.; Fernandes, H.; Batista, A. J.; Cruz, N.; Combo, A.; Pereira, R. C.

2006-01-01

Real-time control will play an important role in the operation and scientific exploitation of the new generation fusion devices. This paper summarizes the real-time systems and diagnostics developed by the Portuguese Fusion Euratom Association based on digital signal processors and field programmable gate arrays

Time-area efficient multiplier-free filter architectures for FPGA implementation

DEFF Research Database (Denmark)

Shajaan, Mohammad; Nielsen, Karsten; Sørensen, John Aasted

1995-01-01

Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is 𝒪 (filter o...

Dual field effects in electrolyte-gated spinel ferrite: electrostatic carrier doping and redox reactions.

Science.gov (United States)

Ichimura, Takashi; Fujiwara, Kohei; Tanaka, Hidekazu

2014-07-24

Controlling the electronic properties of functional oxide materials via external electric fields has attracted increasing attention as a key technology for next-generation electronics. For transition-metal oxides with metallic carrier densities, the electric-field effect with ionic liquid electrolytes has been widely used because of the enormous carrier doping capabilities. The gate-induced redox reactions revealed by recent investigations have, however, highlighted the complex nature of the electric-field effect. Here, we use the gate-induced conductance modulation of spinel ZnxFe₃₋xO₄ to demonstrate the dual contributions of volatile and non-volatile field effects arising from electronic carrier doping and redox reactions. These two contributions are found to change in opposite senses depending on the Zn content x; virtual electronic and chemical field effects are observed at appropriate Zn compositions. The tuning of field-effect characteristics via composition engineering should be extremely useful for fabricating high-performance oxide field-effect devices.

Real-time heterogeneous video transcoding for low-power applications

CERN Document Server

Elarabi, Tarek; Bayoumi, Magdy

2014-01-01

This book introduces a novel transcoding algorithm for real time video applications, designed to overcome inter-operability problems between MPEG-2 to H.264/AVC. The new algorithm achieves 92.8% reduction in the transcoding run time at a price of an acceptable Peak Signal-to-Noise Ratio (PSNR) degradation, enabling readers to use it for real time video applications. The algorithm described is evaluated through simulation and experimental results. In addition, the authors present a hardware implementation of the new algorithm using Field Programmable Gate Array (FPGA) and Application-specific standard products (ASIC).   • Describes a novel transcoding algorithm for real time video applications, designed to overcome inter-operability problems between H.264/AVC to MPEG-2; • Implements algorithm presented using Field Programmable Gate Array (FPGA) and Application-specific Integrated Circuit (ASIC); • Demonstrates the solution to real problems, with verification through simulation and experimental result...

Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

Energy Technology Data Exchange (ETDEWEB)

Aunet, Snorre

2002-06-01

This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

Digital Signal Processing Applications and Implementation for Accelerators Digital Notch Filter with Programmable Delay and Betatron Phase Adjustment for the PS, SPS and LHC Transverse Dampers

CERN Document Server

Rossi, V

2002-01-01

In the framework of the LHC project and the modifications of the SPS as its injector, I present the concept of global digital signal processing applied to a particle accelerator, using Field Programmable Gate Array (FPGA) technology. The approach of global digital synthesis implements in numerical form the architecture of a system, from the start up of a project and the very beginning of the signal flow. It takes into account both the known parameters and the future evolution, whenever possible. Due to the increased performance requirements of today's projects, the CAE design methodology becomes more and more necessary to handle successfully the added complexity and speed of modern electronic circuits. Simulation is performed both for behavioural analysis, to ensure conformity to functional requirements, and for time signal analysis (speed requirements). The digital notch filter with programmable delay for the SPS Transverse Damper is now fully operational with fixed target and LHC-type beams circulating in t...

Sensing small neurotransmitter-enzyme interaction with nanoporous gated ion-sensitive field effect transistors.

Science.gov (United States)

Kisner, Alexandre; Stockmann, Regina; Jansen, Michael; Yegin, Ugur; Offenhäusser, Andreas; Kubota, Lauro Tatsuo; Mourzina, Yulia

2012-01-15

Ion-sensitive field effect transistors with gates having a high density of nanopores were fabricated and employed to sense the neurotransmitter dopamine with high selectivity and detectability at micromolar range. The nanoporous structure of the gates was produced by applying a relatively simple anodizing process, which yielded a porous alumina layer with pores exhibiting a mean diameter ranging from 20 to 35 nm. Gate-source voltages of the transistors demonstrated a pH-dependence that was linear over a wide range and could be understood as changes in surface charges during protonation and deprotonation. The large surface area provided by the pores allowed the physical immobilization of tyrosinase, which is an enzyme that oxidizes dopamine, on the gates of the transistors, and thus, changes the acid-base behavior on their surfaces. Concentration-dependent dopamine interacting with immobilized tyrosinase showed a linear dependence into a physiological range of interest for dopamine concentration in the changes of gate-source voltages. In comparison with previous approaches, a response time relatively fast for detecting dopamine was obtained. Additionally, selectivity assays for other neurotransmitters that are abundantly found in the brain were examined. These results demonstrate that the nanoporous structure of ion-sensitive field effect transistors can easily be used to immobilize specific enzyme that can readily and selectively detect small neurotransmitter molecule based on its acid-base interaction with the receptor. Therefore, it could serve as a technology platform for molecular studies of neurotransmitter-enzyme binding and drugs screening. Copyright © 2011 Elsevier B.V. All rights reserved.

COHERENTLY DEDISPERSED GATED IMAGING OF MILLISECOND PULSARS

International Nuclear Information System (INIS)

Roy, Jayanta; Bhattacharyya, Bhaswati

2013-01-01

Motivated by the need for rapid localization of newly discovered faint millisecond pulsars (MSPs), we have developed a coherently dedispersed gating correlator. This gating correlator accounts for the orbital motions of MSPs in binaries while folding the visibilities with a best-fit topocentric rotational model derived from a periodicity search in a simultaneously generated beamformer output. Unique applications of the gating correlator for sensitive interferometric studies of MSPs are illustrated using the Giant Metrewave Radio Telescope (GMRT) interferometric array. We could unambiguously localize five newly discovered Fermi MSPs in the on-off gated image plane with an accuracy of ±1''. Immediate knowledge of such a precise position enables the use of sensitive coherent beams of array telescopes for follow-up timing observations which substantially reduces the use of telescope time (∼20× for the GMRT). In addition, a precise a priori astrometric position reduces the effect of large covariances in the timing fit (with discovery position, pulsar period derivative, and an unknown binary model), which in-turn accelerates the convergence to the initial timing model. For example, while fitting with the precise a priori position (±1''), the timing model converges in about 100 days, accounting for the effect of covariance between the position and pulsar period derivative. Moreover, such accurate positions allow for rapid identification of pulsar counterparts at other wave bands. We also report a new methodology of in-beam phase calibration using the on-off gated image of the target pulsar, which provides optimal sensitivity of the coherent array removing possible temporal and spacial decoherences.

COHERENTLY DEDISPERSED GATED IMAGING OF MILLISECOND PULSARS

Energy Technology Data Exchange (ETDEWEB)

Roy, Jayanta; Bhattacharyya, Bhaswati [National Centre for Radio Astrophysics, Pune 411007 (India)

2013-03-10

Motivated by the need for rapid localization of newly discovered faint millisecond pulsars (MSPs), we have developed a coherently dedispersed gating correlator. This gating correlator accounts for the orbital motions of MSPs in binaries while folding the visibilities with a best-fit topocentric rotational model derived from a periodicity search in a simultaneously generated beamformer output. Unique applications of the gating correlator for sensitive interferometric studies of MSPs are illustrated using the Giant Metrewave Radio Telescope (GMRT) interferometric array. We could unambiguously localize five newly discovered Fermi MSPs in the on-off gated image plane with an accuracy of {+-}1''. Immediate knowledge of such a precise position enables the use of sensitive coherent beams of array telescopes for follow-up timing observations which substantially reduces the use of telescope time ({approx}20 Multiplication-Sign for the GMRT). In addition, a precise a priori astrometric position reduces the effect of large covariances in the timing fit (with discovery position, pulsar period derivative, and an unknown binary model), which in-turn accelerates the convergence to the initial timing model. For example, while fitting with the precise a priori position ({+-}1''), the timing model converges in about 100 days, accounting for the effect of covariance between the position and pulsar period derivative. Moreover, such accurate positions allow for rapid identification of pulsar counterparts at other wave bands. We also report a new methodology of in-beam phase calibration using the on-off gated image of the target pulsar, which provides optimal sensitivity of the coherent array removing possible temporal and spacial decoherences.

Ferroelectric polymer gates for non-volatile field effect control of ferromagnetism in (Ga, Mn)As layers

International Nuclear Information System (INIS)

Stolichnov, I; Riester, S W E; Mikheev, E; Setter, N; Rushforth, A W; Edmonds, K W; Campion, R P; Foxon, C T; Gallagher, B L; Jungwirth, T; Trodahl, H J

2011-01-01

(Ga, Mn)As and other diluted magnetic semiconductors (DMS) attract a great deal of attention for potential spintronic applications because of the possibility of controlling the magnetic properties via electrical gating. Integration of a ferroelectric gate on the DMS channel adds to the system a non-volatile memory functionality and permits nanopatterning via the polarization domain engineering. This topical review is focused on the multiferroic system, where the ferromagnetism in the (Ga, Mn)As DMS channel is controlled by the non-volatile field effect of the spontaneous polarization. Use of ferroelectric polymer gates in such heterostructures offers a viable alternative to the traditional oxide ferroelectrics generally incompatible with DMS. Here we review the proof-of-concept experiments demonstrating the ferroelectric control of ferromagnetism, analyze the performance issues of the ferroelectric gates and discuss prospects for further development of the ferroelectric/DMS heterostructures toward the multiferroic field effect transistor. (topical review)

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

Directory of Open Access Journals (Sweden)

Chen Yang

2017-06-01

Full Text Available With the development of satellite load technology and very large scale integrated (VLSI circuit technology, onboard real-time synthetic aperture radar (SAR imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT, which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array−application-specific integrated circuit (FPGA-ASIC hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

A high performance cost-effective digital complex correlator for an X-band polarimetry survey.

Science.gov (United States)

Bergano, Miguel; Rocha, Armando; Cupido, Luís; Barbosa, Domingos; Villela, Thyrso; Boas, José Vilas; Rocha, Graça; Smoot, George F

2016-01-01

The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals. The update of the global sky models describing radio emissions over a very large spectral band requires high sensitivity experiments capable of observing large sky areas with long integration times. Here, we present the design of a new 10 GHz (X-band) polarimeter digital back-end to map the polarization components of the galactic synchrotron radiation field of the Northern Hemisphere sky. The design follows the digital processing trends in radio astronomy and implements a large bandwidth (1 GHz) digital complex cross-correlator to extract the Stokes parameters of the incoming synchrotron radiation field. The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. The implementation is based on the simultaneous digitized acquisition of the Cartesian components of the two linear receiver polarization channels. The design strategy involves a double data rate acquisition of the ADC interleaved parallel bus, and field programmable gate array device programming at the register transfer mode. The digital core of the back-end is capable of processing 32 Gbps and is built around an Altera field programmable gate array clocked at 250 MHz, 1 GSps analog to digital converters and a clock generator. The control of the field programmable gate array internal signal delays and a convenient use of its phase locked loops provide the timing requirements to achieve the target bandwidths and sensitivity. This solution is convenient for radio astronomy experiments requiring large bandwidth, high functionality, high volume availability and low cost. Of particular interest, this correlator was developed for the Galactic Emission Mapping project and is suitable for large sky area polarization continuum surveys. The solutions may also be adapted to be used at signal processing

Evaluation of delivered monitor unit accuracy of gated step-and-shoot IMRT using a two-dimensional detector array

Energy Technology Data Exchange (ETDEWEB)

Cheong, Kwang-Ho; Kang, Sei-Kwon; Lee, MeYeon; Kim, Su SSan; Park, SoAh; Hwang, Tae-Jin; Kim, Kyoung Ju; Oh, Do Hoon; Bae, Hoonsik; Suh, Tae-Suk [Department of Radiation Oncology, Hallym University College of Medicine, Seoul, 431070 (Korea, Republic of) and Department of Biomedical Engineering, College of Medicine, Catholic University of Korea, Seoul 137701 (Korea, Republic of); Department of Radiation Oncology, Hallym University College of Medicine, Seoul 431070 (Korea, Republic of); Department of Biomedical Engineering, College of Medicine, Catholic University of Korea, Seoul 137701 (Korea, Republic of)

2010-03-15

Purpose: To overcome the problem of organ motion in intensity-modulated radiation therapy (IMRT), gated IMRT is often used for the treatment of lung cancer. In this study, the authors investigated the accuracy of the delivered monitor units (MUs) from each segment during gated IMRT using a two-dimensional detector array for user-specific verification purpose. Methods: The authors planned a 6 MV photon, seven-port step-and-shoot lung IMRT delivery. The respiration signals for gated IMRT delivery were obtained from the one-dimensional moving phantom using the real-time position management (RPM) system (Varian Medical Systems, Palo Alto, CA). The beams were delivered using a Clinac iX (Varian Medical Systems, Palo Alto, CA) with the Millennium 120 MLC. The MatriXX (IBA Dosimetry GmbH, Germany) was validated through consistency and reproducibility tests as well as comparison with measurements from a Farmer-type ion chamber. The authors delivered beams with varying dose rates and duty cycles and analyzed the MatriXX data to evaluate MU delivery accuracy. Results: There was quite good agreement between the planned segment MUs and the MUs computed from the MatriXX within {+-}2% error. The beam-on times computed from the MatriXX data were almost identical for all cases, and they matched well with the RPM beam-on and beam-off signals. A slight difference was observed between them, but it was less than 40 ms. The gated IMRT delivery demonstrated an MU delivery accuracy that was equivalent to ungated IMRT, and the delivered MUs with a gating signal agreed with the planned MUs within {+-}0.5 MU regardless of dose rate and duty cycle. Conclusions: The authors can conclude that gated IMRT is able to deliver an accurate dose to a patient during a procedure. The authors believe that the methodology and results can be transferred to other vendors' devices, particularly those that do not provide MLC log data for a verification purpose.

Cardiac gated ventilation

International Nuclear Information System (INIS)

Hanson, C.W. III; Hoffman, E.A.

1995-01-01

There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart

A Mirnov loop array for field-reversed configurations

International Nuclear Information System (INIS)

Tuszewski, M.

1990-01-01

An array of 64 magnetic pick-up loops has been used for stability studies of large field-reversed configurations in the FRX-C/LSM device. This array proved reliable, could resolve signals of a few Gauss, and allowed the detection of several plasma instabilities. 3 refs., 4 figs

Predictive digital peak current mode controller for DC-DC converters capable of operating over the full 0-100% duty cycle range

DEFF Research Database (Denmark)

Andersen, Karsten Holm; Nymand, Morten

2017-01-01

) and discontinuous conduction mode (DCM) and supports high switching frequencies even with low cost A/D converters. The proposed controller is implemented in a Field Programmable Gate Array (FPGA) to control a 450 W buck converter and the experimental results verify the controller's capability to operate in the full...

Real-time gigabit DMT transmission over plastic optical fibre

NARCIS (Netherlands)

Lee, S.C.J.; Breyer, F.; Cárdenas, D.; Randel, S.; Koonen, A.M.J.

2009-01-01

For the first time, a real-time 1.25 Gbit/s discrete multitone (DMT) transmitter implemented in a field-programmable gate array is demonstrated for use in low-cost, standard 1 mm step-index plastic optical fibre applications based on a commercial resonant-cavity LED and a large-diameter

FPGA Based Efficient Design of Traffic Light Controller using Frequency Scaling for Family of HSTL

DEFF Research Database (Denmark)

Sharma, Shivani; Khan, Sadiq; Das, Bhagwan

2016-01-01

utilizes least amount of power and is well tested in hardware using Xilinx Virtex6 Field Programmable gate array. FPGA designs are not only cheaper than ASIC designs but have many positive features like speed and performance. So the factors that contribute to power consumption for family of HSTL...

FPGA Implementation of Decimal Processors for Hardware Acceleration

DEFF Research Database (Denmark)

Borup, Nicolas; Dindorp, Jonas; Nannarelli, Alberto

2011-01-01

Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial trans...... execution on the CPU of the hosting computer....

Modified impedance source inverter for power conditioning system

Indian Academy of Sciences (India)

DC link voltage boost, reduced total harmonic distortion of output current and voltage, better voltage gain and wide range of output voltage controlcan be achieved easily with improved power quality. Experimental set-up of the modified impedance source inverter with Field Programmable Gate Array (FPGA) controller has ...

Mobility overestimation due to gated contacts in organic field-effect transistors

Science.gov (United States)

Bittle, Emily G.; Basham, James I.; Jackson, Thomas N.; Jurchescu, Oana D.; Gundlach, David J.

2016-01-01

Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current–voltage characteristics and interpreted by using the classical metal oxide–semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm2 V−1 s−1), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current–voltage characterization are overestimated by one order of magnitude or more. PMID:26961271

SU-E-T-350: Verification of Gating Performance of a New Elekta Gating Solution: Response Kit and Catalyst System

Energy Technology Data Exchange (ETDEWEB)

Xie, X; Cao, D; Housley, D; Mehta, V; Shepard, D [Swedish Cancer Institute, Seattle, WA (United States)

2014-06-01

Purpose: In this work, we have tested the performance of new respiratory gating solutions for Elekta linacs. These solutions include the Response gating and the C-RAD Catalyst surface mapping system.Verification measurements have been performed for a series of clinical cases. We also examined the beam on latency of the system and its impact on delivery efficiency. Methods: To verify the benefits of tighter gating windows, a Quasar Respiratory Motion Platform was used. Its vertical-motion plate acted as a respiration surrogate and was tracked by the Catalyst system to generate gating signals. A MatriXX ion-chamber array was mounted on its longitudinal-moving platform. Clinical plans are delivered to a stationary and moving Matrix array at 100%, 50% and 30% gating windows and gamma scores were calculated comparing moving delivery results to the stationary result. It is important to note that as one moves to tighter gating windows, the delivery efficiency will be impacted by the linac's beam-on latency. Using a specialized software package, we generated beam-on signals of lengths of 1000ms, 600ms, 450ms, 400ms, 350ms and 300ms. As the gating windows get tighter, one can expect to reach a point where the dose rate will fall to nearly zero, indicating that the gating window is close to beam-on latency. A clinically useful gating window needs to be significantly longer than the latency for the linac. Results: As expected, the use of tighter gating windows improved delivery accuracy. However, a lower limit of the gating window, largely defined by linac beam-on latency, exists at around 300ms. Conclusion: The Response gating kit, combined with the C-RAD Catalyst, provides an effective solution for respiratorygated treatment delivery. Careful patient selection, gating window design, even visual/audio coaching may be necessary to ensure both delivery quality and efficiency. This research project is funded by Elekta.

Dual-gated volumetric modulated arc therapy

International Nuclear Information System (INIS)

Fahimian, Benjamin; Wu, Junqing; Wu, Huanmei; Geneser, Sarah; Xing, Lei

2014-01-01

Gated Volumetric Modulated Arc Therapy (VMAT) is an emerging radiation therapy modality for treatment of tumors affected by respiratory motion. However, gating significantly prolongs the treatment time, as delivery is only activated during a single respiratory phase. To enhance the efficiency of gated VMAT delivery, a novel dual-gated VMAT (DG-VMAT) technique, in which delivery is executed at both exhale and inhale phases in a given arc rotation, is developed and experimentally evaluated. Arc delivery at two phases is realized by sequentially interleaving control points consisting of MUs, MLC sequences, and angles of VMAT plans generated at the exhale and inhale phases. Dual-gated delivery is initiated when a respiration gating signal enters the exhale window; when the exhale delivery concludes, the beam turns off and the gantry rolls back to the starting position for the inhale window. The process is then repeated until both inhale and exhale arcs are fully delivered. DG-VMAT plan delivery accuracy was assessed using a pinpoint chamber and diode array phantom undergoing programmed motion. DG-VMAT delivery was experimentally implemented through custom XML scripting in Varian’s TrueBeam™ STx Developer Mode. Relative to single gated delivery at exhale, the treatment time was improved by 95.5% for a sinusoidal breathing pattern. The pinpoint chamber dose measurement agreed with the calculated dose within 0.7%. For the DG-VMAT delivery, 97.5% of the diode array measurements passed the 3%/3 mm gamma criterion. The feasibility of DG-VMAT delivery scheme has been experimentally demonstrated for the first time. By leveraging the stability and natural pauses that occur at end-inspiration and end-exhalation, DG-VMAT provides a practical method for enhancing gated delivery efficiency by up to a factor of two

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

Science.gov (United States)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

International Nuclear Information System (INIS)

Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon; Choi, Woon-Seop

2010-01-01

Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility (μ) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of μ and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on μ, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

Prospects for quantum computing with an array of ultracold polar paramagnetic molecules.

Science.gov (United States)

Karra, Mallikarjun; Sharma, Ketan; Friedrich, Bretislav; Kais, Sabre; Herschbach, Dudley

2016-03-07

Arrays of trapped ultracold molecules represent a promising platform for implementing a universal quantum computer. DeMille [Phys. Rev. Lett. 88, 067901 (2002)] has detailed a prototype design based on Stark states of polar (1)Σ molecules as qubits. Herein, we consider an array of polar (2)Σ molecules which are, in addition, inherently paramagnetic and whose Hund's case (b) free-rotor pair-eigenstates are Bell states. We show that by subjecting the array to combinations of concurrent homogeneous and inhomogeneous electric and magnetic fields, the entanglement of the array's Stark and Zeeman states can be tuned and the qubit sites addressed. Two schemes for implementing an optically controlled CNOT gate are proposed and their feasibility discussed in the face of the broadening of spectral lines due to dipole-dipole coupling and the inhomogeneity of the electric and magnetic fields.

Two-dimensional non-volatile programmable p-n junctions

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Triggering the Electrolyte-Gated Organic Field-Effect Transistor output characteristics through gate functionalization using diazonium chemistry: Application to biodetection of 2,4-dichlorophenoxyacetic acid.

Science.gov (United States)

Nguyen, T T K; Nguyen, T N; Anquetin, G; Reisberg, S; Noël, V; Mattana, G; Touzeau, J; Barbault, F; Pham, M C; Piro, B

2018-04-26

We investigated an Electrolyte-Gated Organic Field-Effect transistor based on poly(N-alkyldiketopyrrolo-pyrrole dithienylthieno[3,2-b]thiophene) as organic semiconductor whose gate electrode was functionalized by electrografting a functional diazonium salt capable to bind an antibody specific to 2,4-dichlorophenoxyacetic acid (2,4-D), an herbicide well-known to be a soil and water pollutant. Molecular docking computations were performed to design the functional diazonium salt to rationalize the antibody capture on the gate surface. Sensing of 2,4-D was performed through a displacement immunoassay. The limit of detection was estimated at around 2.5 fM. Copyright © 2018 Elsevier B.V. All rights reserved.

Review The Ooty Wide Field Array

Indian Academy of Sciences (India)

c Indian Academy of Sciences. DOI 10.1007/s12036-017-9430-4. Review. The Ooty Wide Field ... salient features of the upgrade, as well as its main science drivers. There are three ..... tecture for low frequency arrays, Ph.D. thesis, Jawaharalal.

System Realization of Broad Band Digital Beam Forming for Digital Array Radar

Directory of Open Access Journals (Sweden)

Wang Feng

2013-09-01

Full Text Available Broad band Digital Beam Forming (DBF is the key technique for the realization of Digital Array Radar (DAR. We propose the method of combination realization of the channel equalization and DBF time delay filter function by using adaptive Sample Matrix Inversion algorithm. The broad band DBF function is realized on a new DBF module based on parallel fiber optic engines and Field Program Gate Array (FPGA. Good performance is achieved when it is used to some radar products.

Evaluation of state-of-the-art hardware architectures for fast cone-beam CT reconstruction

CERN Document Server

Scherl, Holger

2011-01-01

Holger Scherl introduces the reader to the reconstruction problem in computed tomography and its major scientific challenges that range from computational efficiency to the fulfillment of Tuy's sufficiency condition. The assessed hardware architectures include multi- and many-core systems, cell broadband engine architecture, graphics processing units, and field programmable gate arrays.

Column Grid Array Rework for High Reliability

Science.gov (United States)

Mehta, Atul C.; Bodie, Charles C.

2008-01-01

Due to requirements for reduced size and weight, use of grid array packages in space applications has become common place. To meet the requirement of high reliability and high number of I/Os, ceramic column grid array packages (CCGA) were selected for major electronic components used in next MARS Rover mission (specifically high density Field Programmable Gate Arrays). ABSTRACT The probability of removal and replacement of these devices on the actual flight printed wiring board assemblies is deemed to be very high because of last minute discoveries in final test which will dictate changes in the firmware. The questions and challenges presented to the manufacturing organizations engaged in the production of high reliability electronic assemblies are, Is the reliability of the PWBA adversely affected by rework (removal and replacement) of the CGA package? and How many times can we rework the same board without destroying a pad or degrading the lifetime of the assembly? To answer these questions, the most complex printed wiring board assembly used by the project was chosen to be used as the test vehicle, the PWB was modified to provide a daisy chain pattern, and a number of bare PWB s were acquired to this modified design. Non-functional 624 pin CGA packages with internal daisy chained matching the pattern on the PWB were procured. The combination of the modified PWB and the daisy chained packages enables continuity measurements of every soldered contact during subsequent testing and thermal cycling. Several test vehicles boards were assembled, reworked and then thermal cycled to assess the reliability of the solder joints and board material including pads and traces near the CGA. The details of rework process and results of thermal cycling are presented in this paper.

Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System

OpenAIRE

Yen, Mao-Hsu; Chen, Sao-Jie; Lan, Sanko H.

2001-01-01

The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size. But the design of an MCM system usually requires weeks of engineering effort, thus we need a generic MCM substrate with programmable interconnections to accelerate system prototyping. In this paper, we propose a Symmetric and Programmable MCM (SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interco...

Implementation of a two-qubit controlled-rotation gate based on unconventional geometric phase with a constant gating time

International Nuclear Information System (INIS)

Yabu-uti, B.F.C.; Roversi, J.A.

2011-01-01

We propose an alternative scheme to implement a two-qubit controlled-R (rotation) gate in the hybrid atom-CCA (coupled cavities array) system. Our scheme results in a constant gating time and, with an adjustable qubit-bus coupling (atom-resonator), one can specify a particular rotation R on the target qubit. We believe that this proposal may open promising perspectives for networking quantum information processors and implementing distributed and scalable quantum computation. -- Highlights: → We propose an alternative two-qubit controlled-rotation gate implementation. → Our gate is realized in a constant gating time for any rotation. → A particular rotation on the target qubit can be specified by an adjustable qubit-bus coupling. → Our proposal may open promising perspectives for implementing distributed and scalable quantum computation.

Spatial Steering of Cyclotron-Resonance Maser Array Antenna by Magnetic Fields

International Nuclear Information System (INIS)

Kesar, A.; Jerby, E.

2001-01-01

The novel concept of radiation lobe generation and steering by cyclotron-resonance maser (CRM) array is presented. In this scheme the gain and phase of each CRM-element in the array are tuned by magnetic fields which control the cyclotron synchronism condition and the pitch-ratio of each CRM-element. These operating parameters are controlled by the magnetic fields of the solenoid and the kicker, respectively. A numerical example of a CRM-array operating in a gyro-TWT mode is presented. The radiation pattern of a 10-element CRM phased array (15 kV, 1A each) is calculated. The radiation lobe steering by the magnetic field controls is demonstrated in this analysis. A 40 lobe steering range is shown for the 10-element CRM-array at 7.3 GHz. An experimental device is built in our laboratory to demonstrate the active CRM-array antenna concept. Preliminary experimental results of gain and phase-delay of a single CRM-element, as function of electron-beam parameters are presented. These results are compared to the numerical model

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

International Nuclear Information System (INIS)

Besleaga, C.; Stan, G.E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

2016-01-01

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

Energy Technology Data Exchange (ETDEWEB)

Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

2016-08-30

Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

Development and field practical performance of smart array probe

International Nuclear Information System (INIS)

Maeda, Kotaro; Shimone, Junri; Akagawa, Junichi; Nagata, Yasuyuki; Harada, Yutaka; Sera, Takehiko; Hirano, Shinro

2011-01-01

In 1999, NEL developed the transmit-receive type ECT array probe for steam generator (SG) tubing, called 'X-probe', in cooperation with foreign firms. Recently NEL has developed the advanced ECT array probe, 'Smart Array Probe', characterized with a significantly improved resolution for circumferential cracks. The doubled channels in the circumferential mode have greatly improved the circumferential resolution of Smart Array Probe. With all the circumferential mode channels on the same circle, there is no need for axial position correction of inspection data. This report describes both the field practical performance and the compliance assessment to a Japanese SG-ECT guideline 'JEAG4208' of Smart Array ECT System, composed of Smart Array Probe, pusher-in-tester 'OMNI-200', and NEL's ECT Analysis System. (author)

Universal core model for multiple-gate field-effect transistors with short channel and quantum mechanical effects

Science.gov (United States)

Shin, Yong Hyeon; Bae, Min Soo; Park, Chuntaek; Park, Joung Won; Park, Hyunwoo; Lee, Yong Ju; Yun, Ilgu

2018-06-01

A universal core model for multiple-gate (MG) field-effect transistors (FETs) with short channel effects (SCEs) and quantum mechanical effects (QMEs) is proposed. By using a Young’s approximation based solution for one-dimensional Poisson’s equations the total inversion charge density (Q inv ) in the channel is modeled for double-gate (DG) and surrounding-gate SG (SG) FETs, following which a universal charge model is derived based on the similarity of the solutions, including for quadruple-gate (QG) FETs. For triple-gate (TG) FETs, the average of DG and QG FETs are used. A SCEs model is also proposed considering the potential difference between the channel’s surface and center. Finally, a QMEs model for MG FETs is developed using the quantum correction compact model. The proposed universal core model is validated on commercially available three-dimensional ATLAS numerical simulations.

Scaling Trapped Ion Quantum Computers Using Fast Gates and Microtraps

Science.gov (United States)

Ratcliffe, Alexander K.; Taylor, Richard L.; Hope, Joseph J.; Carvalho, André R. R.

2018-06-01

Most attempts to produce a scalable quantum information processing platform based on ion traps have focused on the shuttling of ions in segmented traps. We show that an architecture based on an array of microtraps with fast gates will outperform architectures based on ion shuttling. This system requires higher power lasers but does not require the manipulation of potentials or shuttling of ions. This improves optical access, reduces the complexity of the trap, and reduces the number of conductive surfaces close to the ions. The use of fast gates also removes limitations on the gate time. Error rates of 10-5 are shown to be possible with 250 mW laser power and a trap separation of 100 μ m . The performance of the gates is shown to be robust to the limitations in the laser repetition rate and the presence of many ions in the trap array.

Beyond the Nernst-limit with dual-gate ZnO ion-sensitive field-effect transistors

NARCIS (Netherlands)

Spijkman, M.; Smits, E.C.P.; Cillessen, J.F.M.; Biscarini, F.; Blom, P.W.M.; Leeuw, D.M. de

2011-01-01

The sensitivity of conventional ion-sensitive field-effect transistors (ISFETs) is limited to 59 mV/pH, which is the maximum detectable change in electrochemical potential according to the Nernst equation. Here we demonstrate a transducer based on a ZnO dual-gate field-effect transistor that

Effects Of Local Oscillator Errors On Digital Beamforming

Science.gov (United States)

2016-03-01

processor EF element factor EW electronic warfare FFM flicker frequency modulation FOV field-of-view FPGA field-programmable gate array FPM flicker...frequencies and also more difficult to measure [15]. 2. Flicker frequency modulation The source for flicker frequency modulation ( FFM ) is attributed to...a physical resonance mechanism of an oscillator or issues controlling electronic components. Some oscillators might not show FFM noise, which might

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Chi, Li-Feng, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn [Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

2015-03-23

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

International Nuclear Information System (INIS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-01-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process

Lessons learnt from a three-year pilot field epidemiology training programme

Directory of Open Access Journals (Sweden)

Damian Hoy

2017-09-01

Full Text Available Problem: The Pacific region has widely dispersed populations, limited financial and human resources and a high burden of disease. There is an urgent need to improve the availability, reliability and timeliness of useable health data. Context: The purpose of this paper is to share lessons learnt from a three-year pilot field epidemiology training programme that was designed to respond to these Pacific health challenges. The pilot programme built on and further developed an existing field epidemiology training programme for Pacific health staff. Action: The programme was delivered in country by epidemiologists working for Pacific Public Health Surveillance Network partners. The programme consisted of five courses: four one-week classroom-based courses and one field epidemiology project. Sessions were structured so that theoretical understanding was achieved through interaction and reinforced through practical hands-on group activities, case studies and other interactive practical learning methods. Outcome: As of September 2016, 258 students had commenced the programme. Twenty-six course workshops were delivered and one cohort of students had completed the full five-course programme. The programme proved popular and gained a high level of student engagement. Discussion: Face-to-face delivery, a low student-to-facilitator ratio, substantial group work and practical exercises were identified as key factors that contributed to the students developing skills and confidence. Close engagement of leaders and the need to quickly evaluate and adapt the curriculum were important lessons, and the collaboration between external partners was considered important for promoting a harmonized approach to health needs in the Pacific.

Lessons learnt from a three-year pilot field epidemiology training programme.

Science.gov (United States)

Hoy, Damian; Durand, A Mark; Hancock, Thane; Cash, Haley L; Hardie, Kate; Paterson, Beverley; Paulino, Yvette; White, Paul; Merritt, Tony; Fitzgibbons, Dawn; Gopalani, Sameer Vali; Flint, James; Edwin A Merilles, Onofre; Kashiwabara, Mina; Biaukula, Viema; Lepers, Christelle; Souares, Yvan; Nilles, Eric; Batikawai, Anaseini; Huseynova, Sevil; Patel, Mahomed; Saketa, Salanieta T; Durrheim, David; Henderson, Alden; Roth, Adam

2017-01-01

The Pacific region has widely dispersed populations, limited financial and human resources and a high burden of disease. There is an urgent need to improve the availability, reliability and timeliness of useable health data. The purpose of this paper is to share lessons learnt from a three-year pilot field epidemiology training programme that was designed to respond to these Pacific health challenges. The pilot programme built on and further developed an existing field epidemiology training programme for Pacific health staff. The programme was delivered in country by epidemiologists working for Pacific Public Health Surveillance Network partners. The programme consisted of five courses: four one-week classroom-based courses and one field epidemiology project. Sessions were structured so that theoretical understanding was achieved through interaction and reinforced through practical hands-on group activities, case studies and other interactive practical learning methods. As of September 2016, 258 students had commenced the programme. Twenty-six course workshops were delivered and one cohort of students had completed the full five-course programme. The programme proved popular and gained a high level of student engagement. Face-to-face delivery, a low student-to-facilitator ratio, substantial group work and practical exercises were identified as key factors that contributed to the students developing skills and confidence. Close engagement of leaders and the need to quickly evaluate and adapt the curriculum were important lessons, and the collaboration between external partners was considered important for promoting a harmonized approach to health needs in the Pacific.

Development of a Crosstalk Suppression Algorithm for KID Readout

Science.gov (United States)

Lee, Kyungmin; Ishitsuka, H.; Oguri, S.; Suzuki, J.; Tajima, O.; Tomita, N.; Won, Eunil; Yoshida, M.

2018-06-01

The GroundBIRD telescope aims to detect B-mode polarization of the cosmic microwave background radiation using the kinetic inductance detector array as a polarimeter. For the readout of the signal from detector array, we have developed a frequency division multiplexing readout system based on a digital down converter method. These techniques in general have the leakage problems caused by the crosstalks. The window function was applied in the field programmable gate arrays to mitigate the effect of these problems and tested it in algorithm level.

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea; Svendsen, Winnie Edith; Dimaki, Maria

2016-01-01

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

Low-cost modular array-field designs for flat-panel and concentrator photovoltaic systems

Science.gov (United States)

Post, H. N.; Carmichael, D. C.; Alexander, G.; Castle, J. A.

1982-09-01

Described are the design and development of low-cost, modular array fields for flat-panel and concentrator photovoltaic (PV) systems. The objective of the work was to reduce substantially the cost of the array-field Balance-of-System (BOS) subsystems and site-specific design costs as compared to previous PV installations. These subsystems include site preparation, foundations, support structures, electrical writing, grounding, lightning protection, electromagnetic interference considerations, and controls. To reduce these BOS and design costs, standardized modular (building-block) designs for flat-panel and concentrator array fields have been developed that are fully integrated and optimized for lowest life-cycle costs. Using drawings and specifications now available, these building-block designs can be used in multiples to install various size array fields. The developed designs are immediately applicable (1982) and reduce the array-field BOS costs to a fraction of previous costs.

100-nm gate lithography for double-gate transistors

Science.gov (United States)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

Hardware and Software Integration in Project Development of Automated Controller System Using LABVIEW FPGA

International Nuclear Information System (INIS)

Mohd Khairulezwan Abd Manan; Mohd Sabri Minhat; Izhar Abu Hussin

2014-01-01

The Field-Programmable Gate Array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows user to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field, hence the name field-programmable. This project developed a control system using LabVIEW FPGA. LabVIEW FPGA is easier where it is programmed by using drag and drop icon. Then it will be integrated with the hardware input and output. (author)

Radio frequency interference noise reduction using a field programmable gate array for SQUID applications

International Nuclear Information System (INIS)

Sakuta, K; Narita, Y; Itozaki, H

2007-01-01

It is important to remove large environmental noise in superconducting quantum interference device (SQUID) measurement without magnetic shielding. Active noise control (ANC) is one of the effective methods to reduce environmental noise. Recently, SQUIDs have been used in various applications at high frequencies, such as nuclear quadrupole resonance (NQR). The NQR frequency from explosives is in the range 0.5-5 MHz. In this case, an NQR sensor is exposed to AM radio frequency interference (RFI). The feasibility of the ANC system for RFI that used digital signal processing was studied. Our investigation showed that this digital ANC system can be applied to SQUID measurements for RFI suppression

Field Programmable Gate Array Based Parallel Strapdown Algorithm Design for Strapdown Inertial Navigation Systems

Directory of Open Access Journals (Sweden)

Long-Hua Ma

2011-08-01

Full Text Available A new generalized optimum strapdown algorithm with coning and sculling compensation is presented, in which the position, velocity and attitude updating operations are carried out based on the single-speed structure in which all computations are executed at a single updating rate that is sufficiently high to accurately account for high frequency angular rate and acceleration rectification effects. Different from existing algorithms, the updating rates of the coning and sculling compensations are unrelated with the number of the gyro incremental angle samples and the number of the accelerometer incremental velocity samples. When the output sampling rate of inertial sensors remains constant, this algorithm allows increasing the updating rate of the coning and sculling compensation, yet with more numbers of gyro incremental angle and accelerometer incremental velocity in order to improve the accuracy of system. Then, in order to implement the new strapdown algorithm in a single FPGA chip, the parallelization of the algorithm is designed and its computational complexity is analyzed. The performance of the proposed parallel strapdown algorithm is tested on the Xilinx ISE 12.3 software platform and the FPGA device XC6VLX550T hardware platform on the basis of some fighter data. It is shown that this parallel strapdown algorithm on the FPGA platform can greatly decrease the execution time of algorithm to meet the real-time and high precision requirements of system on the high dynamic environment, relative to the existing implemented on the DSP platform.

Hardware, Software and Data Analysis Techniques for SRAM-based Field Programmable Gate Array Circuits

National Research Council Canada - National Science Library

Hockenberry, Eugene B

2008-01-01

The main objective of this research is to accomplish two objectives; first, develop a robust test methodology to successfully allow researchers to isolate errors occurring in SRAM-based FPGAs and other memory devices...

Review on structured optical field generated from array beams

Science.gov (United States)

Hou, Tianyue; Zhou, Pu; Ma, Yanxing; Zhi, Dong

2018-03-01

Structured optical field (SOF), which includes vortex beams, non-diffraction beams, cylindrical vector beams and so on, has been under intensive investigation theoretically and experimentally in recent years. Generally, current research focus on the extraordinary properties (non-diffraction propagation, helical wavefront, rotation of electrical field, et al), which can be widely applied in micro-particle manipulation, super-resolution imaging, free-space communication and so on. There are mainly two technical routes, that is, inner-cavity and outer-cavity (spatial light modulators, diffractive phase holograms, q-plates). To date, most of the SOFs generated from both technical routes involves with single monolithic beam. As a novel technical route, SOF based on array beams has the advantage in more flexible freedom degree and power scaling potential. In this paper, research achievements in SOF generation based on array beams are arranged and discussed in detail. Moreover, experiment of generating exotic beam by array beams is introduced, which illustrates that SOF generated from array beams is theoretically valid and experimentally feasible. SOF generated from array beams is also beneficial for capacity increasing and data receiving for free-space optical communication systems at long distance.

Photon-gated spin transistor

OpenAIRE

Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

2017-01-01

Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

Multiple Independent Gate FETs: How Many Gates Do We Need?

OpenAIRE

Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni

2015-01-01

Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...

Extended-gate organic field-effect transistor for the detection of histamine in water

Science.gov (United States)

Minamiki, Tsukuru; Minami, Tsuyoshi; Yokoyama, Daisuke; Fukuda, Kenjiro; Kumaki, Daisuke; Tokito, Shizuo

2015-04-01

As part of our ongoing research program to develop health care sensors based on organic field-effect transistor (OFET) devices, we have attempted to detect histamine using an extended-gate OFET. Histamine is found in spoiled or decayed fish, and causes foodborne illness known as scombroid food poisoning. The new OFET device possesses an extended gate functionalized by carboxyalkanethiol that can interact with histamine. As a result, we have succeeded in detecting histamine in water through a shift in OFET threshold voltage. This result indicates the potential utility of the designed OFET devices in food freshness sensing.

A high-speed bioelectrical impedance spectroscopy system based on the digital auto-balancing bridge method

International Nuclear Information System (INIS)

Li, Nan; Xu, Hui; Zhou, Zhou; Wang, Wei; Qiao, Guofeng; Li, David D-U

2013-01-01

A novel bioelectrical impedance spectroscopy system based on the digital auto-balancing bridge method improved from the conventional analogue auto-balancing method is presented for bioelectrical impedance measurements. The hardware of the proposed system consists of a reference source, a null detector, a variable source, a field programmable gate array, a clock generator, a flash and a USB controller. Software implemented in the field programmable gate array includes three major blocks: clock management, peripheral control and digital signal processing. The principle and realization of the least-mean-squares-based digital auto-balancing algorithm is introduced in detail. The performances of our system were examined by comparing with a commercial impedance analyzer. The results reveal that the proposed system has high speed (less than 3.5 ms per measurement) and high accuracy in the frequency range of 1 kHz–10 MHz. Compared with the commercial instrument based on the traditional analogue auto-balancing method, our system shows advantages in measurement speed, compactness and flexibility, making it suitable for various bioelectrical impedance measurement applications. (paper)

High-performance computing for airborne applications

International Nuclear Information System (INIS)

Quinn, Heather M.; Manuzatto, Andrea; Fairbanks, Tom; Dallmann, Nicholas; Desgeorges, Rose

2010-01-01

Recently, there has been attempts to move common satellite tasks to unmanned aerial vehicles (UAVs). UAVs are significantly cheaper to buy than satellites and easier to deploy on an as-needed basis. The more benign radiation environment also allows for an aggressive adoption of state-of-the-art commercial computational devices, which increases the amount of data that can be collected. There are a number of commercial computing devices currently available that are well-suited to high-performance computing. These devices range from specialized computational devices, such as field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), to traditional computing platforms, such as microprocessors. Even though the radiation environment is relatively benign, these devices could be susceptible to single-event effects. In this paper, we will present radiation data for high-performance computing devices in a accelerated neutron environment. These devices include a multi-core digital signal processor, two field-programmable gate arrays, and a microprocessor. From these results, we found that all of these devices are suitable for many airplane environments without reliability problems.

Mesoscopic Field-Effect-Induced Devices in Depleted Two-Dimensional Electron Systems

Science.gov (United States)

Bachsoliani, N.; Platonov, S.; Wieck, A. D.; Ludwig, S.

2017-12-01

Nanoelectronic devices embedded in the two-dimensional electron system (2DES) of a GaAs /(Al ,Ga )As heterostructure enable a large variety of applications ranging from fundamental research to high-speed transistors. Electrical circuits are thereby commonly defined by creating barriers for carriers by the selective depletion of a preexisting 2DES. We explore an alternative approach: we deplete the 2DES globally by applying a negative voltage to a global top gate and screen the electric field of the top gate only locally using nanoscale gates placed on the wafer surface between the plane of the 2DES and the top gate. Free carriers are located beneath the screen gates, and their properties can be controlled by means of geometry and applied voltages. This method promises considerable advantages for the definition of complex circuits by the electric-field effect, as it allows us to reduce the number of gates and simplify gate geometries. Examples are carrier systems with ring topology or large arrays of quantum dots. We present a first exploration of this method pursuing field effect, Hall effect, and Aharonov-Bohm measurements to study electrostatic, dynamic, and coherent properties.

Embedded SoPC Design with Nios II Processor and Verilog Examples

CERN Document Server

Chu, Pong P

2012-01-01

Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog An SoPC (system on a programmable chip) integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well-allowing us to configure the soft-core processor, create tailored I/O interfaces, and develop s

Viability of Using Diamond Field Emitter Array Cathodes in Free Electron Lasers

Science.gov (United States)

2010-06-01

essential component of a field emitter array is the shape of the electric field lines and equipotential lines at the surface of the array. The...BARRIER AND QUANTUM TUNNELING ...........25 B. FIELD ENHANCEMENT AND SURFACE PROTRUSIONS .........26 C. ELECTRIC FIELDS AND ELECTRON TRAVEL...26 Figure 4. Diagram of a protrusion (triangular in shape) from the surface of a cathode. The protrusion is of height h, with a

Fully transparent conformal organic thin-film transistor array and its application as LED front driving.

Science.gov (United States)

Cui, Nan; Ren, Hang; Tang, Qingxin; Zhao, Xiaoli; Tong, Yanhong; Hu, Wenping; Liu, Yichun

2018-02-22

A fully transparent conformal organic thin-film field-effect transistor array is demonstrated based on a photolithography-compatible ultrathin metallic grid gate electrode and a solution-processed C 8 -BTBT film. The resulting organic field-effect transistor array exhibits a high optical transparency of >80% over the visible spectrum, mobility up to 2 cm 2 V -1 s -1 , on/off ratio of 10 5 -10 6 , switching current of >0.1 mA, and excellent light stability. The transparent conformal transistor array is demonstrated to adhere well to flat and curved LEDs as front driving. These results present promising applications of the solution-processed wide-bandgap organic semiconductor thin films in future large-scale transparent conformal active-matrix displays.

Numerical study of self-field effects on dynamics of Josephson-junction arrays

International Nuclear Information System (INIS)

Phillips, J.R.; Van der Zant, H.S.J.; White, J.; Orlando, T.P.

1994-01-01

We consider the influence of self-induced magnetic fields on dynamic properties of arrays of resistively and capacitively shunted Josephson junctions. Self-field effects are modeled by including mutual inductance interactions between every cell in the array. We find that it is important to include all mutual inductance interactions in order to understand the dynamic properties of the array, in particular subharmonic structure arising under AC current bias. (orig.)

25th Annual International Symposium on Field-Programmable Custom Computing Machines

CERN Document Server

The IEEE Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems.

Memory, microprocessor, and ASIC

CERN Document Server

Chen, Wai-Kai

2003-01-01

System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application

Science.gov (United States)

Navlakha, Nupur; Kranti, Abhinav

2017-07-01

Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1 = SM × RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2 = SM × CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM.

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

Directory of Open Access Journals (Sweden)

Sungho Kang

1996-01-01

Full Text Available In order to reduce cost and to achieve high speed a new hardware accelerator for fault simulation has been designed. The architecture of the new accelerator is based on a reconfigurabl mesh type processing element (PE array. Circuit elements at the same topological level are simulated concurrently, as in a pipelined process. A new parallel simulation algorithm expands all of the gates to two input gates in order to limit the number of faults to two at each gate, so that the faults can be distributed uniformly throughout the PE array. The PE array reconfiguration operation provides a simulation speed advantage by maximizing the use of each PE cell.

Detailed simulation study of a dual material gate carbon nanotube field-effect transistor

Science.gov (United States)

Orouji, Ali A.; Arefinia, Zahra

2009-02-01

For the first time, a new type of carbon nanotube field-effect transistor (CNTFET), the dual material gate (DMG)-CNTFET, is proposed and simulated using quantum simulation that is based on self-consistent solution between two-dimensional Poisson equation and Schrödinger equation with open boundary conditions, within the nonequilibrium Green's function (NEGF) framework. The proposed structure is similar to that of the conventional coaxial CNTFET with the exception that the gate of the DMG-CNTFET consists of two laterally contacting metals with different work functions. Simulation results show DMG-CNTFET significantly decreases leakage current, drain conductance and subthreshold swing, and increases on-off current ratio and voltage gain as compared to conventional CNTFET. We demonstrate that the potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed short-channel effects like the drain-induced barrier lowering (DIBL) and hot-carrier effect.

Influence of the gate position on source-to-drain resistance in AlGaN/AlN/GaN heterostructure field-effect transistors

Directory of Open Access Journals (Sweden)

Yan Liu

2017-08-01

Full Text Available Using a suitable dual-gate structure, the source-to-drain resistance (RSD of AlGaN/AlN/GaN heterostructure field-effect transistor (HFET with varying gate position has been studied at room temperature. The theoretical and experimental results have revealed a dependence of RSD on the gate position. The variation of RSD with the gate position is found to stem from the polarization Coulomb field (PCF scattering. This finding is of great benefit to the optimization of the performance of AlGaN/AlN/GaN HFET. Especially, when the AlGaN/AlN/GaN HFET works as a microwave device, it is beneficial to achieve the impedance matching by designing the appropriate gate position based on PCF scattering.

Control of Turing patterns and their usage as sensors, memory arrays, and logic gates

Science.gov (United States)

Muzika, František; Schreiber, Igor

2013-10-01

We study a model system of three diffusively coupled reaction cells arranged in a linear array that display Turing patterns with special focus on the case of equal coupling strength for all components. As a suitable model reaction we consider a two-variable core model of glycolysis. Using numerical continuation and bifurcation techniques we analyze the dependence of the system's steady states on varying rate coefficient of the recycling step while the coupling coefficients of the inhibitor and activator are fixed and set at the ratios 100:1, 1:1, and 4:5. We show that stable Turing patterns occur at all three ratios but, as expected, spontaneous transition from the spatially uniform steady state to the spatially nonuniform Turing patterns occurs only in the first case. The other two cases possess multiple Turing patterns, which are stabilized by secondary bifurcations and coexist with stable uniform periodic oscillations. For the 1:1 ratio we examine modular spatiotemporal perturbations, which allow for controllable switching between the uniform oscillations and various Turing patterns. Such modular perturbations are then used to construct chemical computing devices utilizing the multiple Turing patterns. By classifying various responses we propose: (a) a single-input resettable sensor capable of reading certain value of concentration, (b) two-input and three-input memory arrays capable of storing logic information, (c) three-input, three-output logic gates performing combinations of logical functions OR, XOR, AND, and NAND.

[A capillary blood flow velocity detection system based on linear array charge-coupled devices].

Science.gov (United States)

Zhou, Houming; Wang, Ruofeng; Dang, Qi; Yang, Li; Wang, Xiang

2017-12-01

In order to detect the flow characteristics of blood samples in the capillary, this paper introduces a blood flow velocity measurement system based on field-programmable gate array (FPGA), linear charge-coupled devices (CCD) and personal computer (PC) software structure. Based on the analysis of the TCD1703C and AD9826 device data sheets, Verilog HDL hardware description language was used to design and simulate the driver. Image signal acquisition and the extraction of the real-time edge information of the blood sample were carried out synchronously in the FPGA. Then a series of discrete displacement were performed in a differential operation to scan each of the blood samples displacement, so that the sample flow rate could be obtained. Finally, the feasibility of the blood flow velocity detection system was verified by simulation and debugging. After drawing the flow velocity curve and analyzing the velocity characteristics, the significance of measuring blood flow velocity is analyzed. The results show that the measurement of the system is less time-consuming and less complex than other flow rate monitoring schemes.

Multiplexed charge-locking device for large arrays of quantum devices

Energy Technology Data Exchange (ETDEWEB)

Puddy, R. K., E-mail: rkp27@cam.ac.uk; Smith, L. W; Chong, C. H.; Farrer, I.; Griffiths, J. P.; Ritchie, D. A.; Smith, C. G. [Cavendish Laboratory, University of Cambridge, Cambridge CB3 0HE (United Kingdom); Al-Taie, H.; Kelly, M. J. [Cavendish Laboratory, University of Cambridge, Cambridge CB3 0HE (United Kingdom); Centre for Advanced Photonics and Electronics, Electrical Engineering Division, Department of Engineering, 9 J. J. Thomson Avenue, University of Cambridge, Cambridge CB3 0FA (United Kingdom); Pepper, M. [Department of Electronic and Electrical Engineering, University College London, WC1E 7JE (United Kingdom)

2015-10-05

We present a method of forming and controlling large arrays of gate-defined quantum devices. The method uses an on-chip, multiplexed charge-locking system and helps to overcome the restraints imposed by the number of wires available in cryostat measurement systems. The device architecture that we describe here utilises a multiplexer-type scheme to lock charge onto gate electrodes. The design allows access to and control of gates whose total number exceeds that of the available electrical contacts and enables the formation, modulation and measurement of large arrays of quantum devices. We fabricate such devices on n-type GaAs/AlGaAs substrates and investigate the stability of the charge locked on to the gates. Proof-of-concept is shown by measurement of the Coulomb blockade peaks of a single quantum dot formed by a floating gate in the device. The floating gate is seen to drift by approximately one Coulomb oscillation per hour.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

Science.gov (United States)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

International Nuclear Information System (INIS)

Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

2014-01-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

Implementation of FPGA-Based Diverse Protection System

International Nuclear Information System (INIS)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

2015-01-01

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

Implementation of FPGA-Based Diverse Protection System

Energy Technology Data Exchange (ETDEWEB)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

2015-10-15

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

Design and implementation of the NaI(Tl)/CsI(Na) detectors output signal generator

Science.gov (United States)

Zhou, Xu; Liu, Cong-Zhan; Zhao, Jian-Ling; Zhang, Fei; Zhang, Yi-Fei; Li, Zheng-Wei; Zhang, Shuo; Li, Xu-Fang; Lu, Xue-Feng; Xu, Zhen-Ling; Lu, Fang-Jun

2014-02-01

We designed and implemented a signal generator that can simulate the output of the NaI(Tl)/CsI(Na) detectors' pre-amplifier onboard the Hard X-ray Modulation Telescope (HXMT). Using the development of the FPGA (Field Programmable Gate Array) with VHDL language and adding a random constituent, we have finally produced the double exponential random pulse signal generator. The statistical distribution of the signal amplitude is programmable. The occurrence time intervals of the adjacent signals contain negative exponential distribution statistically.

A novel optical gating method for laser gated imaging

Science.gov (United States)

Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

2013-06-01

For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

Near-field/far-field array manifold of an acoustic vector-sensor near a reflecting boundary.

Science.gov (United States)

Wu, Yue Ivan; Lau, Siu-Kit; Wong, Kainam Thomas

2016-06-01

The acoustic vector-sensor (a.k.a. the vector hydrophone) is a practical and versatile sound-measurement device, with applications in-room, open-air, or underwater. It consists of three identical uni-axial velocity-sensors in orthogonal orientations, plus a pressure-sensor-all in spatial collocation. Its far-field array manifold [Nehorai and Paldi (1994). IEEE Trans. Signal Process. 42, 2481-2491; Hawkes and Nehorai (2000). IEEE Trans. Signal Process. 48, 2981-2993] has been introduced into the technical field of signal processing about 2 decades ago, and many direction-finding algorithms have since been developed for this acoustic vector-sensor. The above array manifold is subsequently generalized for outside the far field in Wu, Wong, and Lau [(2010). IEEE Trans. Signal Process. 58, 3946-3951], but only if no reflection-boundary is to lie near the acoustic vector-sensor. As for the near-boundary array manifold for the general case of an emitter in the geometric near field, the far field, or anywhere in between-this paper derives and presents that array manifold in terms of signal-processing mathematics. Also derived here is the corresponding Cramér-Rao bound for azimuth-elevation-distance localization of an incident emitter, with the reflected wave shown to play a critical role on account of its constructive or destructive summation with the line-of-sight wave. The implications on source localization are explored, especially with respect to measurement model mismatch in maximum-likelihood direction finding and with regard to the spatial resolution between coexisting emitters.

Pulling the trigger on LHC electronics

CERN Document Server

CERN. Geneva

2001-01-01

The conditions at CERN's Large Hadron Collider pose severe challenges for the designers and builders of front-end, trigger and data acquisition electronics. A recent workshop reviewed the encouraging progress so far and discussed what remains to be done. The LHC experiments have addressed level one trigger systems with a variety of high-speed hardware. The CMS Calorimeter Level One Regional Trigger uses 160 MHz logic boards plugged into the front and back of a custom backplane, which provides point-to-point links between the cards. Much of the processing in this system is performed by five types of 160 MHz digital applications-specific integrated circuits designed using Vitesse submicron high-integration gallium arsenide gate array technology. The LHC experiments make extensive use of field programmable gate arrays (FPGAs). These offer programmable reconfigurable logic, which has the flexibility that trigger designers need to be able to alter algorithms so that they can follow the physics and detector perform...

Field emission properties of an array of pyramidal structures

Energy Technology Data Exchange (ETDEWEB)

De Assis, Thiago A [Departamento de QuImica, Universidad Autonoma de Madrid, Cantoblanco, 28049 Madrid (Spain); Borondo, F [Departamento de QuImica, Instituto Mixto de Ciencias Matematicas CSIC-UAM-UC3M-UCM, Universidad Autonoma de Madrid, Cantoblanco, 28049 Madrid (Spain); De Castilho, C M C; Brito Mota, F [Grupo de Fisica de SuperfIcies e Materiais, Instituto de Fisica, Universidade Federal da Bahia, Campus Universitario da Federacao, 40210-340, Salvador, BA (Brazil); Benito, R M, E-mail: t.albuquerque@uam.e, E-mail: f.borondo@uam.e, E-mail: caio@ufba.b, E-mail: fbmota@ufba.b, E-mail: rosamaria.benito@upm.e [Grupo de Sistemas Complejos, Departamento de Fisica y Mecanica, Escuela Tecnica Superior de Ingenieros Agronomos, Universidad Politecnica de Madrid, Ciudad Universitaria, 28040 Madrid (Spain)

2009-10-07

The properties and efficiency of the emission current density produced by a metallic array of pyramidal structures are investigated. The theoretical results obtained by numerical integration of the corresponding Laplace equation using a finite differences scheme offer useful information for the optimization of field emission devices based on cathodes with this geometry. Our study shows that the inter-pyramidal distance strongly affects the current density, and even more important for this issue is the protrusion characteristics of these structures. Another relevant, although less important, parameter determining this density is the anode-cathode distance. The effect of the array characteristics on the maximum local electric field intensity is also discussed.

The Nordic safety programme in the nuclear field

International Nuclear Information System (INIS)

Wahlstroem, B.; Marcus, F.

1987-01-01

Safety of nuclear installations has been a concern of all the Nordic countries, although only Finland and Sweden have selected to build nuclear power plants. It was recognized early that the resources in a single country were limited and previous Nordic cooperation in the nuclear field was therefore followed up through a safety programme which started ten years ago. This research cooperation has been intensified during the years, and today more than 70 organizations in Denmark, Finland, Norway, and Sweden participate. The present programme is the third in a row and it will continue until 1989. Human factors and operational experience are touched upon in the RAS (safety philosophy) and the INF (advanced information technology) subprogrammes. The paper gives a brief overview of the Nordic safety programme in general and the RAS and INF subprogrammes. 11 refs. (author)

Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays. Final Report

Energy Technology Data Exchange (ETDEWEB)

Britton, Jr., Charles L. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ericson, Milton Nance [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Bobrek, Miljko [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Blalock, Benjamin [Univ. of Tennessee, Knoxville, TN (United States)

2015-12-01

As the recent accident at Fukushima Daiichi so vividly demonstrated, telerobotic technologies capable of withstanding high radiation environments need to be readily available to enable operations, repair, and recovery under severe accident scenarios where human entry is extremely dangerous or not possible. Telerobotic technologies that enable remote operation in high dose rate environments have undergone revolutionary improvement over the past few decades. However, much of this technology cannot be employed in nuclear power environments due the radiation sensitivity of the electronics and the organic insulator materials currently in use. This is the final report of the activities involving the NEET 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays. We present a detailed functional block diagram of the proposed data acquisition system, the thought process leading to technical decisions, the implemented system, and the tested results from the systems. This system will be capable of monitoring at least three parameters of importance to nuclear reactor monitoring: temperature, radiation level, and pressure.

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

Energy Technology Data Exchange (ETDEWEB)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

Enhanced field emission properties of vertically aligned double-walled carbon nanotube arrays

International Nuclear Information System (INIS)

Chen, Guohai; Shin, Dong Hoon; Lee, Cheol Jin; Iwasaki, Takayuki; Kawarada, Hiroshi

2008-01-01

Vertically aligned double-walled carbon nanotube (VA-DWCNT) arrays were synthesized by point-arc microwave plasma chemical vapor deposition on Cr/n-Si and SiO 2 /n-Si substrates. The outer tube diameters of VA-DWCNTs are in the range of 2.5-3.8 nm, and the average interlayer spacing is approximately 0.42 nm. The field emission properties of these VA-DWCNTs were studied. It was found that a VA-DWCNT array grown on a Cr/n-Si substrate had better field emission properties as compared with a VA-DWCNT array grown on a SiO 2 /n-Si substrate and randomly oriented DWCNTs, showing a turn-on field of about 0.85 V μm -1 at the emission current density of 0.1 μA cm -2 and a threshold field of 1.67 V μm -1 at the emission current density of 1.0 mA cm -2 . The better field emission performance of the VA-DWCNT array was mainly attributed to the vertical alignment of DWCNTs on the Cr/n-Si substrate and the low contact resistance between CNTs and the Cr/n-Si substrate

High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

Directory of Open Access Journals (Sweden)

Murali Gedda

2013-11-01

Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain

Science.gov (United States)

Liu, Liang-kui; Shi, Cheng; Zhang, Yi-bo; Sun, Lei

2017-04-01

A tri gate Ge-based tunneling field-effect transistor (TFET) has been numerically studied with technology computer aided design (TCAD) tools. Dopant segregated Schottky source/drain is applied to the device structure design (DS-TFET). The characteristics of the DS-TFET are compared and analyzed comprehensively. It is found that the performance of n-channel tri gate DS-TFET with a positive bias is insensitive to the dopant concentration and barrier height at n-type drain, and that the dopant concentration and barrier height at a p-type source considerably affect the device performance. The domination of electron current in the entire BTBT current of this device accounts for this phenomenon and the tri-gate DS-TFET is proved to have a higher performance than its dual-gate counterpart.

Rad-Hard Structured ASIC Body of Knowledge

Science.gov (United States)

Heidecker, Jason

2013-01-01

Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

Analyzing System on A Chip Single Event Upset Responses using Single Event Upset Data, Classical Reliability Models, and Space Environment Data

Science.gov (United States)

Berg, Melanie; LaBel, Kenneth; Campola, Michael; Xapsos, Michael

2017-01-01

We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)

Study on Oscillations during Short Circuit of MW-Scale IGBT Power Modules by Means of a 6-kA/1.1-kV Nondestructive Testing System

DEFF Research Database (Denmark)

Wu, Rui; Diaz Reigosa, Paula; Iannuzzo, Francesco

2015-01-01

This paper uses a 6-kA/1.1-kV nondestructive testing system for the analysis of the short-circuit behavior of insulated-gate bipolar transistor (IGBT) power modules. A field-programmable gate array enables the definition of control signals to an accuracy of 10 ns. Multiple 1.7-kV/1-kA IGBT power...... modules displayed severe divergent oscillations, which were subsequently characterized. Experimental tests indicate that nonnegligible circuit stray inductance plays an important role in the divergent oscillations. In addition, the temperature dependence of the transconductance is proposed as an important...

Influence of gate dielectric on the ambipolar characteristics of solution-processed organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Ribierre, J C; Ghosh, S; Takaishi, K; Muto, T; Aoyama, T, E-mail: jcribierre@ewha.ac.kr, E-mail: taoyama@riken.jp [Advanced Science Institute, RIKEN, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan)

2011-05-25

Solution-processed ambipolar organic field-effect transistors based on dicyanomethylene-substituted quinoidal quaterthiophene derivative [QQT(CN)4] are fabricated using various gate dielectric materials including cross-linked polyimide and poly-4-vinylphenol. Devices with spin-coated polymeric gate dielectric layers show a reduced hysteresis in their transfer characteristics. Among the insulating polymers examined in this study, a new fluorinated polymer with a low dielectric constant of 2.8 significantly improves both hole and electron field-effect mobilities of QQT(CN)4 thin films to values as high as 0.04 and 0.002 cm{sup 2} V{sup -1} s{sup -1}. These values are close to the best mobilities obtained in QQT(CN)4 devices fabricated on SiO{sub 2} treated with octadecyltrichlorosilane. The influence of the metal used for source/drain metal electrodes on the device performance is also investigated. Whereas best device performances are achieved with gold electrodes, more balanced electron and hole field-effect mobilities could be obtained using chromium.

Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

Science.gov (United States)

Ramezani, Zeinab; Orouji, Ali A.

2018-01-01

A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

Proposal for quantum gates in permanently coupled antiferromagnetic spin rings without need of local fields.

Science.gov (United States)

Troiani, Filippo; Affronte, Marco; Carretta, Stefano; Santini, Paolo; Amoretti, Giuseppe

2005-05-20

We propose a scheme for the implementation of quantum gates which is based on the qubit encoding in antiferromagnetic molecular rings. We show that a proper engineering of the intercluster link would result in an effective coupling that vanishes as far as the system is kept in the computational space, while it is turned on by a selective excitation of specific auxiliary states. These are also shown to allow the performing of single-qubit and two-qubit gates without an individual addressing of the rings by means of local magnetic fields.

Top-gated field-effect LaAlO{sub 3}/SrTiO{sub 3} devices made by ion-irradiation

Energy Technology Data Exchange (ETDEWEB)

Hurand, S.; Jouan, A.; Feuillet-Palma, C.; Singh, G.; Malnou, M.; Lesueur, J.; Bergeal, N. [Laboratoire de Physique et d' Etude des Matériaux-CNRS-ESPCI ParisTech-UPMC, PSL Research University, 10 Rue Vauquelin - 75005 Paris (France); Lesne, E.; Reyren, N.; Barthélémy, A.; Bibes, M.; Villegas, J. E. [Unité Mixte de Physique CNRS-Thales, 1 Av. A. Fresnel, 91767 Palaiseau (France); Ulysse, C. [Laboratoire de Photonique et de Nanostructures LPN-CNRS, Route de Nozay, 91460 Marcoussis and Universit Paris Sud, 91405 Orsay (France); Pannetier-Lecoeur, M. [DSM/IRAMIS/SPEC - CNRS UMR 3680, CEA Saclay, F-91191 Gif-sur-Yvette Cedex (France)

2016-02-01

We present a method to fabricate top-gated field-effect devices in a LaAlO{sub 3}/SrTiO{sub 3} two-dimensional electron gas (2-DEG). Prior to the gate deposition, the realisation of micron size conducting channels in the 2-DEG is achieved by an ion-irradiation with high-energy oxygen ions. After identifying the ion fluence as the key parameter that determines the electrical transport properties of the channels, we demonstrate the field-effect operation. At low temperature, the normal state resistance and the superconducting T{sub c} can be tuned over a wide range by a top-gate voltage without any leakage. A superconductor-to-insulator quantum phase transition is observed for a strong depletion of the 2-DEG.

Vertically aligned zinc selenide nanoribbon arrays: microstructure and field emission

International Nuclear Information System (INIS)

Zhao Lijuan; Pang Qi; Cai Yuan; Wang Ning; Ge Weikun; Wang Jiannong; Yang Shihe

2007-01-01

Uniform ZnSe precursor (ZnSe : 0.38en, en = ethylenediamine) nanoribbon arrays are grown vertically on Zn foils in ethylenediamine (en) using a solvothermal method. After the annealing treatment in N 2 , the ZnSe nanoribbon arrays can be obtained without an obvious morphology change and the crystallinity of ribbons is greatly improved. The microstructures of both individual ZnSe precursor and ZnSe nanoribbons are investigated. Field emission characteristics show that the onset field required drawing a current density of ∼0.1 μ A cm -2 from the ZnSe nanoribbons is 5.0 V μm -1 and the field enhancement factors are determined to be ∼1382

CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

International Nuclear Information System (INIS)

Ginet, Patrick; Akiyama, Sho; Takama, Nobuyuki; Fujita, Hiroyuki; Kim, Beomjoon

2011-01-01

Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL −1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors

Chemo-Electrical Signal Transduction by Using Stimuli-Responsive Polymer Gate-Modified Field Effect Transistor

Directory of Open Access Journals (Sweden)

Akira Matsumoto

2014-03-01

Full Text Available A glucose-responsive polymer brush was designed on a gold electrode and exploited as an extended gate for a field effect transistor (FET based biosensor. A permittivity change at the gate interface due to the change in hydration upon specific binding with glucose was detectable. The rate of response was markedly enhanced compared to the previously studied cross-linked or gel-coupled electrode, owing to its kinetics involving no process of the polymer network diffusion. This finding may offer a new strategy of the FET-based biosensors effective not only for large molecules but also for electrically neutral molecules such as glucose with improved kinetics.

Dual field effects in electrolyte-gated spinel ferrite: electrostatic carrier doping and redox reactions

OpenAIRE

Takashi Ichimura; Kohei Fujiwara; Hidekazu Tanaka

2014-01-01

Controlling the electronic properties of functional oxide materials via external electric fields has attracted increasing attention as a key technology for next-generation electronics. For transition-metal oxides with metallic carrier densities, the electric-field effect with ionic liquid electrolytes has been widely used because of the enormous carrier doping capabilities. The gate-induced redox reactions revealed by recent investigations have, however, highlighted the complex nature of the ...

Design and implementation of the NaI(Tl)/CsI(Na) detectors output signal generator

International Nuclear Information System (INIS)

Zhou Xu; Liu Congzhan; Zhao Jianling

2014-01-01

We designed and implemented a signal generator that can simulate the output of the NaI(Tl)/CsI(Na) detectors' pre-amplifier onboard the Hard X-ray Modulation Telescope (HXMT). Using the development of the FPGA (Field Programmable Gate Array) with VHDL language and adding a random constituent, we have finally produced the double exponential random pulse signal generator. The statistical distribution of the signal amplitude is programmable. The occurrence time intervals of the adjacent signals contain negative exponential distribution statistically. (authors)

Efficient Implementation of Nested-Loop Multimedia Algorithms

Directory of Open Access Journals (Sweden)

Kittitornkun Surin

2001-01-01

Full Text Available A novel dependence graph representation called the multiple-order dependence graph for nested-loop formulated multimedia signal processing algorithms is proposed. It allows a concise representation of an entire family of dependence graphs. This powerful representation facilitates the development of innovative implementation approach for nested-loop formulated multimedia algorithms such as motion estimation, matrix-matrix product, 2D linear transform, and others. In particular, algebraic linear mapping (assignment and scheduling methodology can be applied to implement such algorithms on an array of simple-processing elements. The feasibility of this new approach is demonstrated in three major target architectures: application-specific integrated circuit (ASIC, field programmable gate array (FPGA, and a programmable clustered VLIW processor.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

Science.gov (United States)

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

NASA Electronic Parts and Packaging Field Programmable Gate Array Single Event Effects Test Guideline Update

Science.gov (United States)

Berg, Melanie D.; LaBel, Kenneth A.

2018-01-01

The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.

Field Programmable Gate Array (FPGA Respiratory Monitoring System Using a Flow Microsensor and an Accelerometer

Directory of Open Access Journals (Sweden)

Mellal Idir

2017-04-01

Full Text Available This paper describes a non-invasive system for respiratory monitoring using a Micro Electro Mechanical Systems (MEMS flow sensor and an IMU (Inertial Measurement Unit accelerometer. The designed system is intended to be wearable and used in a hospital or at home to assist people with respiratory disorders. To ensure the accuracy of our system, we proposed a calibration method based on ANN (Artificial Neural Network to compensate the temperature drift of the silicon flow sensor. The sigmoid activation functions used in the ANN model were computed with the CORDIC (COordinate Rotation DIgital Computer algorithm. This algorithm was also used to estimate the tilt angle in body position. The design was implemented on reconfigurable platform FPGA.

A high-resolution programmable Vernier delay generator based on carry chains in FPGA.

Science.gov (United States)

Cui, Ke; Li, Xiangyu; Zhu, Rihong

2017-06-01

This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 20  ° C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

A high-resolution programmable Vernier delay generator based on carry chains in FPGA

Science.gov (United States)

Cui, Ke; Li, Xiangyu; Zhu, Rihong

2017-06-01

This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 2 0°C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

Characteristics of dual-gate thin-film transistors for applications in digital radiology

International Nuclear Information System (INIS)

Waechter, D.; Huang, Z.; Zhao, W.; Blevis, I.; Rowlands, J.A.

1996-01-01

A large-area flat-panel detector for digital radiology is being developed. The detector uses an array of dual-gate thin-film transistors (TFTs) to read out X-ray-generated charge produced in an amorphous selenium (a-Se) layer. The TFTs use CdSe as the semiconductor and use the bottom gate for row selection. The top gate can be divided into a 'deliberate' gate, covering most of the channel length, and small 'parasitic' gates that consist of: overlap of source or drain metal over the top-gate oxide; and gap regions in the metal that are covered only by the a-Se. In this paper we present the properties of dual-gate TFTs and examine the effect of both the deliberate and parasitic gates on the detector operation. Various options for controlling the top-gate potential are analyzed and discussed. (author)

Extended Gate Field-Effect Transistor Biosensors for Point-Of-Care Testing of Uric Acid.

Science.gov (United States)

Guan, Weihua; Reed, Mark A

2017-01-01

An enzyme-free redox potential sensor using off-chip extended-gate field effect transistor (EGFET) with a ferrocenyl-alkanethiol modified gold electrode has been used to quantify uric acid concentration in human serum and urine. Hexacyanoferrate (II) and (III) ions are used as redox reagent. The potentiometric sensor measures the interface potential on the ferrocene immobilized gold electrode, which is modulated by the redox reaction between uric acid and hexacyanoferrate ions. The device shows a near Nernstian response to uric acid and is highly specific to uric acid in human serum and urine. The interference that comes from glucose, bilirubin, ascorbic acid, and hemoglobin is negligible in the normal concentration range of these interferents. The sensor also exhibits excellent long term reliability and is regenerative. This extended gate field effect transistor based sensor is promising for point-of-care detection of uric acid due to the small size, low cost, and low sample volume consumption.

Programme of basic nuclear research and associated fields 1977-1981

International Nuclear Information System (INIS)

1978-01-01

Nuclear research and development have been intensively pursued in West Germany by the Government and the Laender since 1955. In this period, the aims and official measures for fostering the research and use of nuclear power for peaceful purposes were laid down in four nuclear programmes. The 4th Nuclear Programme covers the period 1973 to 1976. From 1977, nuclear development became part of the energy research programme which was published by the West German Government in the spring of 1977. The basic nuclear research, however, was regarded as part of a total concept for fostering basic research (to be developed). While all the activities of research in the natural sciences and arts fostered by the West German Ministry of Research and Technology were to be co-ordinated in a more schematic form in the plan for 'Basic Research', it is the aim of the present statement to take stock of the present situation in 'Basic Nuclear Research' including the associated fields of 'Nuclear Solid Research' and 'Synchrotron Radiation', to analyse their structure, to describe the scientific aims for the next five years and to determine the total financial requirements. The basis for determining the financial programme worked out by the expert committee on 'Physical Research in the Nuclear Field' and the other committees in this field. The plans are in agreement with the medium term plan of the West German Ministry of Research and Technology (at 27.10.1977) and their contents correspond to the state of affairs at the end of 1977. (orig./UA) [de

Gate Engineering in SOI LDMOS for Device Reliability

Directory of Open Access Journals (Sweden)

Aanand

2016-01-01

Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

Science.gov (United States)

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

Sound field control with a circular double-layer array of loudspeakers

DEFF Research Database (Denmark)

Chang, Jiho; Jacobsen, Finn

2012-01-01

, and their performance is examined using computer simulations. Two performance indices are used in this work, (a) the level difference between the average sound energy density in the listening zone and that in the quiet zone (sometimes called “the acoustic contrast”), and (b) a normalized measure of the deviations...... between the desired and the generated sound field in the listening zone. It is concluded that the best compromise is obtained with a method that combines pure contrast maximization with a pressure matching technique.......This paper describes a method of generating a controlled sound field for listeners inside a circular array of loudspeakers without disturbing people outside the array appreciably. To achieve this objective, a double-layer array of loudspeakers is used. Several solution methods are suggested...

A Label-Free Immunosensor for IgG Based on an Extended-Gate Type Organic Field Effect Transistor

Directory of Open Access Journals (Sweden)

Tsukuru Minamiki

2014-09-01

Full Text Available A novel biosensor for immunoglobulin G (IgG detection based on an extended-gate type organic field effect transistor (OFET has been developed that possesses an anti-IgG antibody on its extended-gate electrode and can be operated below 3 V. The titration results from the target IgG in the presence of a bovine serum albumin interferent, clearly exhibiting a negative shift in the OFET transfer curve with increasing IgG concentration. This is presumed to be due an interaction between target IgG and the immobilized anti-IgG antibody on the extended-gate electrode. As a result, a linear range from 0 to 10 µg/mL was achieved with a relatively low detection limit of 0.62 µg/mL (=4 nM. We believe that these results open up opportunities for applying extended-gate-type OFETs to immunosensing.

FPGA Based Acceleration of Decimal Operations

DEFF Research Database (Denmark)

Nannarelli, Alberto

2011-01-01

Field Programmable Gate-Arrays (FPGAs) can efficiently implement application specific processors in nonconventional number systems, such as the decimal (Binary- Coded Decimal, or BCD) number system required for accounting accuracy in financial applications. The main purpose of this work is to show...... an advanced input/output interface, can achieve a speed-up of about 10 over its execution on the CPU of the hosting computer....

Performance evaluation of coherent Ising machines against classical neural networks

Science.gov (United States)

Haribara, Yoshitaka; Ishikawa, Hitoshi; Utsunomiya, Shoko; Aihara, Kazuyuki; Yamamoto, Yoshihisa

2017-12-01

The coherent Ising machine is expected to find a near-optimal solution in various combinatorial optimization problems, which has been experimentally confirmed with optical parametric oscillators and a field programmable gate array circuit. The similar mathematical models were proposed three decades ago by Hopfield et al in the context of classical neural networks. In this article, we compare the computational performance of both models.

New efficient five-input majority gate for quantum-dot cellular automata

International Nuclear Information System (INIS)

Farazkish, Razieh; Navi, Keivan

2012-01-01

A novel fault-tolerant five-input majority gate for quantum-dot cellular automata is presented. Quantum-dot cellular automata (QCA) is an emerging technology which is considered to be presented in future computers. Two principle logic elements in QCA are “majority gate” and “inverter.” In this paper, we propose a new approach to the design of fault-tolerant five-input majority gate by considering two-dimensional arrays of QCA cells. We analyze fault tolerance properties of such block five-input majority gate in terms of misalignment, missing, and dislocation cells. Some physical proofs are used for verifying five-input majority gate circuit layout and functionality. Our results clearly demonstrate that the redundant version of the block five-input majority gate is more robust than the standard style for this gate.

Improving Tumor Treating Fields Treatment Efficacy in Patients With Glioblastoma Using Personalized Array Layouts

International Nuclear Information System (INIS)

Wenger, Cornelia; Salvador, Ricardo; Basser, Peter J.; Miranda, Pedro C.

2016-01-01

Purpose: To investigate tumors of different size, shape, and location and the effect of varying transducer layouts on Tumor Treating Fields (TTFields) distribution in an anisotropic model. Methods and Materials: A realistic human head model was generated from MR images of 1 healthy subject. Four different virtual tumors were placed at separate locations. The transducer arrays were modeled to mimic the TTFields-delivering commercial device. For each tumor location, varying array layouts were tested. The finite element method was used to calculate the electric field distribution, taking into account tissue heterogeneity and anisotropy. Results: In all tumors, the average electric field induced by either of the 2 perpendicular array layouts exceeded the 1-V/cm therapeutic threshold value for TTFields effectiveness. Field strength within a tumor did not correlate with its size and shape but was higher in more superficial tumors. Additionally, it always increased when the array was adapted to the tumor's location. Compared with a default layout, the largest increase in field strength was 184%, and the highest average field strength induced in a tumor was 2.21 V/cm. Conclusions: These results suggest that adapting array layouts to specific tumor locations can significantly increase field strength within the tumor. Our findings support the idea of personalized treatment planning to increase TTFields efficacy for patients with GBM.

Improving Tumor Treating Fields Treatment Efficacy in Patients With Glioblastoma Using Personalized Array Layouts

Energy Technology Data Exchange (ETDEWEB)

Wenger, Cornelia, E-mail: cwenger@fc.ul.pt [Institute of Biophysics and Biomedical Engineering, Faculdade de Ciências, Universidade de Lisboa, Lisbon (Portugal); Salvador, Ricardo [Institute of Biophysics and Biomedical Engineering, Faculdade de Ciências, Universidade de Lisboa, Lisbon (Portugal); Basser, Peter J. [Section on Tissue Biophysics and Biomimetics, Eunice Kennedy Shriver National Institute of Child Health and Human Development, National Institutes of Health, Bethesda, Maryland (United States); Miranda, Pedro C. [Institute of Biophysics and Biomedical Engineering, Faculdade de Ciências, Universidade de Lisboa, Lisbon (Portugal)

2016-04-01

Purpose: To investigate tumors of different size, shape, and location and the effect of varying transducer layouts on Tumor Treating Fields (TTFields) distribution in an anisotropic model. Methods and Materials: A realistic human head model was generated from MR images of 1 healthy subject. Four different virtual tumors were placed at separate locations. The transducer arrays were modeled to mimic the TTFields-delivering commercial device. For each tumor location, varying array layouts were tested. The finite element method was used to calculate the electric field distribution, taking into account tissue heterogeneity and anisotropy. Results: In all tumors, the average electric field induced by either of the 2 perpendicular array layouts exceeded the 1-V/cm therapeutic threshold value for TTFields effectiveness. Field strength within a tumor did not correlate with its size and shape but was higher in more superficial tumors. Additionally, it always increased when the array was adapted to the tumor's location. Compared with a default layout, the largest increase in field strength was 184%, and the highest average field strength induced in a tumor was 2.21 V/cm. Conclusions: These results suggest that adapting array layouts to specific tumor locations can significantly increase field strength within the tumor. Our findings support the idea of personalized treatment planning to increase TTFields efficacy for patients with GBM.

Robustness of holonomic quantum gates

International Nuclear Information System (INIS)

Solinas, P.; Zanardi, P.; Zanghi, N.

2005-01-01

Full text: If the driving field fluctuates during the quantum evolution this produces errors in the applied operator. The holonomic (and geometrical) quantum gates are believed to be robust against some kind of noise. Because of the geometrical dependence of the holonomic operators can be robust against this kind of noise; in fact if the fluctuations are fast enough they cancel out leaving the final operator unchanged. I present the numerical studies of holonomic quantum gates subject to this parametric noise, the fidelity of the noise and ideal evolution is calculated for different noise correlation times. The holonomic quantum gates seem robust not only for fast fluctuating fields but also for slow fluctuating fields. These results can be explained as due to the geometrical feature of the holonomic operator: for fast fluctuating fields the fluctuations are canceled out, for slow fluctuating fields the fluctuations do not perturb the loop in the parameter space. (author)

The effect of scattering on sound field control with a circular double-layer array of loudspeakers

DEFF Research Database (Denmark)

Chang, Jiho; Jacobsen, Finn

2012-01-01

A recent study has shown that a circular double-layer array of loudspeakers makes it possible to achieve a sound field control that can generate a controlled field inside the array and reduce sound waves propagating outside the array. This is useful if it is desirable not to disturb people outside...... the array or to prevent the effect of reflections from the room. The study assumed free field condition, however in practice a listener will be located inside the array. The listener scatters sound waves, which propagate outward. Consequently, the scattering effect can be expected to degrade the performance...

Field emission from optimized structure of carbon nanotube field emitter array

International Nuclear Information System (INIS)

Chouhan, V.; Noguchi, T.; Kato, S.

2016-01-01

The authors report a detail study on the emission properties of field emitter array (FEA) of micro-circular emitters of multiwall carbon nanotubes (CNTs). The FEAs were fabricated on patterned substrates prepared with an array of circular titanium (Ti) islands on titanium nitride coated tantalum substrates. CNTs were rooted into these Ti islands to prepare an array of circular emitters. The circular emitters were prepared in different diameters and pitches in order to optimize their structure for acquiring a high emission current. The pitch was varied from 0 to 600 μm, while a diameter of circular emitters was kept constant to be 50 μm in order to optimize a pitch. For diameter optimization, a diameter was changed from 50 to 200 μm while keeping a constant edge-to-edge distance of 150 μm between the circular emitters. The FEA with a diameter of 50 μm and a pitch of 120 μm was found to be the best to achieve an emission current of 47 mA corresponding to an effective current density of 30.5 A/cm"2 at 7 V/μm. The excellent emission current was attributed to good quality of CNT rooting into the substrate and optimized FEA structure, which provided a high electric field on a whole circular emitter of 50 μm and the best combination of the strong edge effect and CNT coverage. The experimental results were confirmed with computer simulation.

Field emission from optimized structure of carbon nanotube field emitter array

Energy Technology Data Exchange (ETDEWEB)

Chouhan, V., E-mail: vchouhan@post.kek.jp, E-mail: vijaychouhan84@gmail.com [School of High Energy Accelerator, The Graduate University for Advanced Studies, Tsukuba 305-0801 (Japan); Noguchi, T. [High Energy Accelerator Research Organization (KEK), Tsukuba 305-0801 (Japan); Kato, S. [School of High Energy Accelerator, The Graduate University for Advanced Studies, Tsukuba 305-0801 (Japan); High Energy Accelerator Research Organization (KEK), Tsukuba 305-0801 (Japan)

2016-04-07

The authors report a detail study on the emission properties of field emitter array (FEA) of micro-circular emitters of multiwall carbon nanotubes (CNTs). The FEAs were fabricated on patterned substrates prepared with an array of circular titanium (Ti) islands on titanium nitride coated tantalum substrates. CNTs were rooted into these Ti islands to prepare an array of circular emitters. The circular emitters were prepared in different diameters and pitches in order to optimize their structure for acquiring a high emission current. The pitch was varied from 0 to 600 μm, while a diameter of circular emitters was kept constant to be 50 μm in order to optimize a pitch. For diameter optimization, a diameter was changed from 50 to 200 μm while keeping a constant edge-to-edge distance of 150 μm between the circular emitters. The FEA with a diameter of 50 μm and a pitch of 120 μm was found to be the best to achieve an emission current of 47 mA corresponding to an effective current density of 30.5 A/cm{sup 2} at 7 V/μm. The excellent emission current was attributed to good quality of CNT rooting into the substrate and optimized FEA structure, which provided a high electric field on a whole circular emitter of 50 μm and the best combination of the strong edge effect and CNT coverage. The experimental results were confirmed with computer simulation.

A PILOT FOR A VERY LARGE ARRAY H I DEEP FIELD

International Nuclear Information System (INIS)

Fernández, Ximena; Van Gorkom, J. H.; Schiminovich, David; Hess, Kelley M.; Pisano, D. J.; Kreckel, Kathryn; Momjian, Emmanuel; Popping, Attila; Oosterloo, Tom; Chomiuk, Laura; Verheijen, M. A. W.; Henning, Patricia A.; Bershady, Matthew A.; Wilcots, Eric M.; Scoville, Nick

2013-01-01

High-resolution 21 cm H I deep fields provide spatially and kinematically resolved images of neutral hydrogen at different redshifts, which are key to understanding galaxy evolution across cosmic time and testing predictions of cosmological simulations. Here we present results from a pilot for an H I deep field done with the Karl G. Jansky Very Large Array (VLA). We take advantage of the newly expanded capabilities of the telescope to probe the redshift interval 0 < z < 0.193 in one observation. We observe the COSMOS field for 50 hr, which contains 413 galaxies with optical spectroscopic redshifts in the imaged field of 34' × 34' and the observed redshift interval. We have detected neutral hydrogen gas in 33 galaxies in different environments spanning the probed redshift range, including three without a previously known spectroscopic redshift. The detections have a range of H I and stellar masses, indicating the diversity of galaxies we are probing. We discuss the observations, data reduction, results, and highlight interesting detections. We find that the VLA's B-array is the ideal configuration for H I deep fields since its long spacings mitigate radio frequency interference. This pilot shows that the VLA is ready to carry out such a survey, and serves as a test for future H I deep fields planned with other Square Kilometer Array pathfinders.

A PILOT FOR A VERY LARGE ARRAY H I DEEP FIELD

Energy Technology Data Exchange (ETDEWEB)

Fernandez, Ximena; Van Gorkom, J. H.; Schiminovich, David [Department of Astronomy, Columbia University, New York, NY 10027 (United States); Hess, Kelley M. [Department of Astronomy, Astrophysics, Cosmology and Gravity Centre, University of Cape Town, Private Bag X3, Rondebosch 7701 (South Africa); Pisano, D. J. [Department of Physics, West Virginia University, P.O. Box 6315, Morgantown, WV 26506 (United States); Kreckel, Kathryn [Max Planck Institute for Astronomy, Koenigstuhl 17, D-69117 Heidelberg (Germany); Momjian, Emmanuel [National Radio Astronomy Observatory, Socorro, NM 87801 (United States); Popping, Attila [International Centre for Radio Astronomy Research (ICRAR), The University of Western Australia, 35 Stirling Hwy, Crawley, WA 6009 (Australia); Oosterloo, Tom [Netherlands Institute for Radio Astronomy (ASTRON), Postbus 2, NL-7990 AA Dwingeloo (Netherlands); Chomiuk, Laura [Department of Physics and Astronomy, Michigan State University, East Lansing, MI 48824 (United States); Verheijen, M. A. W. [Kapteyn Astronomical Institute, University of Groningen, Postbus 800, NL-9700 AV Groningen (Netherlands); Henning, Patricia A. [Department of Physics and Astronomy, University of New Mexico, Albuquerque, NM 87131 (United States); Bershady, Matthew A.; Wilcots, Eric M. [Department of Astronomy, University of Wisconsin-Madison, Madison, WI 53706 (United States); Scoville, Nick, E-mail: ximena@astro.columbia.edu [Department of Astronomy, California Institute of Technology, Pasadena, CA 91125 (United States)

2013-06-20

High-resolution 21 cm H I deep fields provide spatially and kinematically resolved images of neutral hydrogen at different redshifts, which are key to understanding galaxy evolution across cosmic time and testing predictions of cosmological simulations. Here we present results from a pilot for an H I deep field done with the Karl G. Jansky Very Large Array (VLA). We take advantage of the newly expanded capabilities of the telescope to probe the redshift interval 0 < z < 0.193 in one observation. We observe the COSMOS field for 50 hr, which contains 413 galaxies with optical spectroscopic redshifts in the imaged field of 34' Multiplication-Sign 34' and the observed redshift interval. We have detected neutral hydrogen gas in 33 galaxies in different environments spanning the probed redshift range, including three without a previously known spectroscopic redshift. The detections have a range of H I and stellar masses, indicating the diversity of galaxies we are probing. We discuss the observations, data reduction, results, and highlight interesting detections. We find that the VLA's B-array is the ideal configuration for H I deep fields since its long spacings mitigate radio frequency interference. This pilot shows that the VLA is ready to carry out such a survey, and serves as a test for future H I deep fields planned with other Square Kilometer Array pathfinders.

Array-level stability enhancement of 50 nm AlxOy ReRAM

Science.gov (United States)

Iwasaki, Tomoko Ogura; Ning, Sheyang; Yamazawa, Hiroki; Takeuchi, Ken

2015-12-01

ReRAM's low voltage and low current programmability are attractive features to solve the scaling issues of conventional floating gate Flash. However, read instability in ReRAM is a critical issue, due to random telegraph noise (RTN), sensitivity to disturb and retention. In this work, the array-level characteristics of read stability in 50 nm AlxOy ReRAM are investigated and a circuit technique to improve stability is proposed and evaluated. First, in order to quantitatively assess memory cell stability, a method of stability characterization is defined. Next, based on this methodology, a proposal to improve read stability, called ;stability check loop; is evaluated. The stability check loop is a stability verification procedure, by which, instability improvement of 7×, and read error rate improvement of 40% are obtained.

Gated x-ray detector for the National Ignition Facility

International Nuclear Information System (INIS)

Oertel, John A.; Aragonez, Robert; Archuleta, Tom; Barnes, Cris; Casper, Larry; Fatherley, Valerie; Heinrichs, Todd; King, Robert; Landers, Doug; Lopez, Frank; Sanchez, Phillip; Sandoval, George; Schrank, Lou; Walsh, Peter; Bell, Perry; Brown, Matt; Costa, Robert; Holder, Joe; Montelongo, Sam; Pederson, Neal

2006-01-01

Two new gated x-ray imaging cameras have recently been designed, constructed, and delivered to the National Ignition Facility in Livermore, CA. These gated x-Ray detectors are each designed to fit within an aluminum airbox with a large capacity cooling plane and are fitted with an array of environmental housekeeping sensors. These instruments are significantly different from earlier generations of gated x-ray images due, in part, to an innovative impedance matching scheme, advanced phosphor screens, pulsed phosphor circuits, precision assembly fixturing, unique system monitoring, and complete remote computer control. Preliminary characterization has shown repeatable uniformity between imaging strips, improved spatial resolution, and no detectable impedance reflections

Wide field and diffraction limited array camera for SIRTF

International Nuclear Information System (INIS)

Fazio, G.G.; Koch, D.G.; Melnick, G.J.

1986-01-01

The Infrared Array Camera for the Space Infrared Telescope Facility (SIRTF/IRAC) is capable of two-dimensional photometry in either a wide field or diffraction-limited mode over the wavelength interval from 2 to 30 microns. Three different two-dimensional direct readout (DRO) array detectors are being considered: Band 1-InSb or Si:In (2-5 microns) 128 x 128 pixels, Band 2-Si:Ga (5-18 microns) 64 x 64 pixels, and Band 3-Si:Sb (18-30 microns) 64 x 64 pixels. The hybrid DRO readout architecture has the advantages of low read noise, random pixel access with individual readout rates, and nondestructive readout. The scientific goals of IRAC are discussed, which are the basis for several important requirements and capabilities of the array camera: (1) diffraction-limited resolution from 2-30 microns, (2) use of the maximum unvignetted field of view of SIRTF, (3) simultaneous observations within the three infrared spectral bands, and (4) the capability for broad and narrow bandwidth spectral resolution. A strategy has been developed to minimize the total electronic and environmental noise sources to satisfy the scientific requirements. 7 references

Modulation of electromagnetic fields by a depolarizer of random polarizer array

DEFF Research Database (Denmark)

Ma, Ning; Hanson, Steen Grüner; Wang, Wei

2016-01-01

The statistical properties of the electric fields with random changes of the polarization state in space generated by a depolarizer are investigated on the basis of the coherence matrix. The depolarizer is a polarizer array composed of a multitude of contiguous square cells of polarizers with ran......The statistical properties of the electric fields with random changes of the polarization state in space generated by a depolarizer are investigated on the basis of the coherence matrix. The depolarizer is a polarizer array composed of a multitude of contiguous square cells of polarizers...... with randomly distributed polarization angles, where the incident fields experience a random polarization modulation after passing through the depolarizer. The propagation of the modulated electric fields through any quadratic optical system is examined within the framework of the complex ABCD matrix to show...

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

Directory of Open Access Journals (Sweden)

Ning Cui

2012-06-01

Full Text Available Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs. In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.

Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

International Nuclear Information System (INIS)

Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo; Kim, Hwajeong; Lee, Joon-Hyung; Park, Soo-Young; Kang, Inn-Kyu

2014-01-01

We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4 ′ -pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm 2 /Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V D ) and gate (V G ) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V D and V G . The best voltage combination was V D = −0.2 V and V G = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.; Smith, Casey; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2011-01-01

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.

2011-10-12

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

Directory of Open Access Journals (Sweden)

Alisson C. D. de Souza

2014-09-01

Full Text Available This paper proposes a parallel fixed point radial basis function (RBF artificial neural network (ANN, implemented in a field programmable gate array (FPGA trained online with a least mean square (LMS algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx, with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.

New methods for trigger electronics development

Energy Technology Data Exchange (ETDEWEB)

Cleland, W.E.; Stern, E.G. [Univ. of Pittsburgh, PA (United States)

1991-12-31

The large and complex nature of RHIC experiments and the tight time schedule for their construction requires that new techniques for designing the electronics should be employed. This is particularly true of the trigger and data acquisition electronics which has to be ready for turn-on of the experiment. We describe the use of the Workview package from VIEWlogic Inc. for design, simulation, and verification of a flash ADC readout system. We also show how field-programmable gate arrays such as the Xilinx 4000 might be employed to construct or prototype circuits with a large number of gates while preserving flexibility.

Active gated imaging in driver assistance system

Science.gov (United States)

Grauer, Yoav

2014-04-01

In this paper, we shall present the active gated imaging system (AGIS) in relation to the automotive field. AGIS is based on a fast-gated camera and pulsed illuminator, synchronized in the time domain to record images of a certain range of interest. A dedicated gated CMOS imager sensor and near infra-red (NIR) pulsed laser illuminator, is presented in this paper to provide active gated technology. In recent years, we have developed these key components and learned the system parameters, which are most beneficial to nighttime (in all weather conditions) driving in terms of field of view, illumination profile, resolution, and processing power. We shall present our approach of a camera-based advanced driver assistance systems (ADAS) named BrightEye™, which makes use of the AGIS technology in the automotive field.

Development of a prototype PET scanner with depth-of-interaction measurement using solid-state photomultiplier arrays and parallel readout electronics.

Science.gov (United States)

Shao, Yiping; Sun, Xishan; Lan, Kejian A; Bircher, Chad; Lou, Kai; Deng, Zhi

2014-03-07

In this study, we developed a prototype animal PET by applying several novel technologies to use solid-state photomultiplier (SSPM) arrays to measure the depth of interaction (DOI) and improve imaging performance. Each PET detector has an 8 × 8 array of about 1.9 × 1.9 × 30.0 mm(3) lutetium-yttrium-oxyorthosilicate scintillators, with each end optically connected to an SSPM array (16 channels in a 4 × 4 matrix) through a light guide to enable continuous DOI measurement. Each SSPM has an active area of about 3 × 3 mm(2), and its output is read by a custom-developed application-specific integrated circuit to directly convert analogue signals to digital timing pulses that encode the interaction information. These pulses are transferred to and are decoded by a field-programmable gate array-based time-to-digital convertor for coincident event selection and data acquisition. The independent readout of each SSPM and the parallel signal process can significantly improve the signal-to-noise ratio and enable the use of flexible algorithms for different data processes. The prototype PET consists of two rotating detector panels on a portable gantry with four detectors in each panel to provide 16 mm axial and variable transaxial field-of-view (FOV) sizes. List-mode ordered subset expectation maximization image reconstruction was implemented. The measured mean energy, coincidence timing and DOI resolution for a crystal were about 17.6%, 2.8 ns and 5.6 mm, respectively. The measured transaxial resolutions at the center of the FOV were 2.0 mm and 2.3 mm for images reconstructed with and without DOI, respectively. In addition, the resolutions across the FOV with DOI were substantially better than those without DOI. The quality of PET images of both a hot-rod phantom and mouse acquired with DOI was much higher than that of images obtained without DOI. This study demonstrates that SSPM arrays and advanced readout/processing electronics can be used to develop a practical DOI

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

International Nuclear Information System (INIS)

Jiang Zhi; Zhuang Yi-Qi; Li Cong; Wang Ping; Liu Yu-Qi

2016-01-01

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (D it ) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current. (paper)

A compact electron gun using field emitter array

International Nuclear Information System (INIS)

Asakawa, M.R.; Ikeda, A.; Miyabe, N.; Yamaguchi, S.; Kusaba, M.; Tsunawaki, Y.

2008-01-01

A compact electron gun using field emitter array has been developed. With a simple triode configuration consisting of FEA, mid-electrode and anode electrode, the electron gun produces a parallel beam with a diameter of 0.5 mm. This electron gun is applicable for compact radiation sources such as Cherenkov free-electron lasers

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

Science.gov (United States)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

High performance top-gated ferroelectric field effect transistors based on two-dimensional ZnO nanosheets

Science.gov (United States)

Tian, Hongzheng; Wang, Xudong; Zhu, Yuankun; Liao, Lei; Wang, Xianying; Wang, Jianlu; Hu, Weida

2017-01-01

High quality ultrathin two-dimensional zinc oxide (ZnO) nanosheets (NSs) are synthesized, and the ZnO NS ferroelectric field effect transistors (FeFETs) are demonstrated based on the P(VDF-TrFE) polymer film used as the top gate insulating layer. The ZnO NSs exhibit a maximum field effect mobility of 588.9 cm2/Vs and a large transconductance of 2.5 μS due to their high crystalline quality and ultrathin two-dimensional structure. The polarization property of the P(VDF-TrFE) film is studied, and a remnant polarization of >100 μC/cm2 is achieved with a P(VDF-TrFE) thickness of 300 nm. Because of the ultrahigh remnant polarization field generated in the P(VDF-TrFE) film, the FeFETs show a large memory window of 16.9 V and a high source-drain on/off current ratio of more than 107 at zero gate voltage and a source-drain bias of 0.1 V. Furthermore, a retention time of >3000 s of the polarization state is obtained, inspiring a promising candidate for applications in data storage with non-volatile features.

FPGA Vision Data Architecture

Science.gov (United States)

Morfopoulos, Arin C.; Pham, Thang D.

2013-01-01

JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

Event Pre Processor for the CZT Detector on MIRAX

International Nuclear Information System (INIS)

Kendziorra, Eckhard; Schanz, Thomas; Distratis, Giuseppe; Suchy, Slawomir

2006-01-01

We describe the Event Pre Processor (EPP) for the Hard X-ray Imager (HXI) on MIRAX. The EPP provides on board data reduction and event filtering for the HXI Cadmium Zinc Telluride strip detector. Emphasis is placed upon the EPP requirements, its implementation as VHDL design in a Field Programmable Gate Array (FPGA), and the description of a test environment for both the VHDL code and the FPGA hardware

Dessign and Implementation of Hardened Reconfiguration Controller for Self-Healing Systems on SRAM-Based FPGAs

OpenAIRE

DERAKHSHAN, NASER

2013-01-01

As digital systems become large and complex, their dependability is getting more important, particularly in mission-critical and safety‐critical applications. Among various available platforms for implementing a digital system, SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly adopted in embedded systems due to their flexibility in achieving multiple requirements such as low cost, high performance, and fast turnaround time compared to Fixed Application Specific Integrated Cir...

Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

DEFF Research Database (Denmark)

Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

2012-01-01

This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

Implementation and Testing of the JANUS Standard with SSC Pacific’s Software-Defined Acoustic Modem

Science.gov (United States)

2017-10-01

JANUS limit) was typed from the keyboard by the user. Next, the transmitter bash script was run and the user typed the ASCII text of choice, or the...FDECO Forward Deployed Energy and Communications Outpost CONOPS concept of operation DSP digital signal processor FPGA field programmable gate array...deployed by U.S. and international military and civilian organizations have for decades operated without any type of widely adopted standards or

Signal compression in radar using FPGA

OpenAIRE

Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

2010-01-01

We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

High-Bandwidth Tactical-Network Data Analysis in a High-Performance-Computing (HPC) Environment: Packet-Level Analysis

Science.gov (United States)

2015-09-01

individual fragments using the hash-based method. In general, fragments 6 appear in order and relatively close to each other in the file. A fragment...data product derived from the data model is shown in Fig. 5, a Google Earth12 Keyhole Markup Language (KML) file. This product includes aggregate...System BLOb binary large object FPGA field-programmable gate array HPC high-performance computing IP Internet Protocol KML Keyhole Markup Language

Optimizing Gas Generator Efficiency in a Forward Operating Base Using an Energy Management System

Science.gov (United States)

2013-06-01

Bus Battery Chargers Routers Security Systems Laptops Radios Flat Panel Displays LED Lighting Fluorescent Lighting "Generator 2" 15kW Non...custom printed circuit board (PCB), field- programmable gate array (FPGA) development board and signal processing board. The battery pack is visible...source selection decisions are based upon system states such as load demand, generator capacity, and battery bank SoC. A simple RC circuit was used to

Algorithmic strategies for FPGA-based vision

OpenAIRE

Lim, Yoong Kang

2016-01-01

As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

Analysis of Surface Electric Field Measurements from an Array of Electric Field Mills

Science.gov (United States)

Lucas, G.; Thayer, J. P.; Deierling, W.

2016-12-01

Kennedy Space Center (KSC) has operated an distributed array of over 30 electric field mills over the past 18 years, providing a unique data set of surface electric field measurements over a very long timespan. In addition to the electric field instruments there are many meteorological towers around KSC that monitor the local meteorological conditions. Utilizing these datasets we have investigated and found unique spatial and temporal signatures in the electric field data that are attributed to local meteorological effects and the global electric circuit. The local and global scale influences on the atmospheric electric field will be discussed including the generation of space charge from the ocean surf, local cloud cover, and a local enhancement in the electric field that is seen at sunrise.

Electrical characterization of Ω-gated uniaxial tensile strained Si nanowire-array metal-oxide-semiconductor field effect transistors with - and channel orientations

International Nuclear Information System (INIS)

Habicht, Stefan; Feste, Sebastian; Zhao, Qing-Tai; Buca, Dan; Mantl, Siegfried

2012-01-01

Nanowire-array metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated along and crystal directions on (001) un-/strained silicon-on-insulator substrates. Lateral strain relaxation through patterning was employed to transform biaxial tensile strain into uniaxial tensile strain along the nanowire. Devices feature ideal subthreshold swings and maximum on-current/off-current ratios of 10 11 for n and p-type transistors on both substrates. Electron and hole mobilities were extracted by split C–V method. For p-MOSFETs an increased mobility is observed for channel direction devices compared to devices. The n-MOSFETs showed a 45% increased electron mobility compared to devices. The comparison of strained and unstrained n-MOSFETs along and clearly demonstrates improved electron mobilities for strained channels of both channel orientations.

FPGA Implementation of the stepwise shutdown system

International Nuclear Information System (INIS)

Lotjonen, L.

2012-01-01

This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and standards can be used to some extent but the hardware aspects bring new challenges that cannot be tackled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation process from the requirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)