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Sample records for fast fpga controller

  1. FPGA based, modular, configurable controller with fast synchronous optical network

    Energy Technology Data Exchange (ETDEWEB)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

    2006-07-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  2. FPGA based, modular, configurable controller with fast synchronous optical network

    International Nuclear Information System (INIS)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S.

    2006-01-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  3. A novel integrated renewable energy system modelling approach, allowing fast FPGA controller prototyping

    DEFF Research Database (Denmark)

    Teodorescu, Remus; Ruiz, Alberto Parera; Cirstea, Marcian

    2008-01-01

    The paper describes a new holistic approach to the modeling of integrated renewable energy systems. The method is using the DK5 modeling/design environment from Celoxica and is based on the new Handel-C programming language. The goal of the work carried out was to achieve a combined model...... containing a Xilinx Spartan II FPGA and was successfully experimentally tested. This approach enables the design and fast hardware implementation of efficient controllers for Distributed Energy Resource (DER) hybrid systems....... of a photovoltaic energy system and a wind power system, which would allow an optimized holistic digital control system design, followed by rapid prototyping of the controller into a single Field Programmable Gate Array (FPGA). Initially, the system was simulated using Matlab / Simulink, to create a reference...

  4. Fast digital feedback control systems for accelerator RF system using FPGA

    International Nuclear Information System (INIS)

    Bagduwal, Pritam Singh; Sharma, Dheeraj; Tiwari, Nitesh; Lad, M.; Hannurkar, P.R.

    2012-01-01

    Feedback control system plays important role for proper injection and acceleration of beam in particle accelerators by providing the required amplitude and phase stability of RF fields in accelerating structures. Advancement in the field of digital technology enables us to develop fast digital feedback control system for RF applications. Digital Low Level RF (LLRF) system offers the inherent advantages of Digital System like flexibility, adaptability, good repeatability and reduced long time drift errors compared to analog system. To implement the feedback control algorithm, I/Q control scheme is used. By properly sampling the down converted IF signal using fast ADC we get accurate feedback signal and also eliminates the need of two separate detectors for amplitude and phase detection. Controller is implemented in Vertex-4 FPGA. Codes for control algorithms which controls the amplitude and phase in all four quadrants with good accuracy are written in the VHDL. I/Q modulator works as common actuator for both amplitude and phase correction. Synchronization between RF, LO and ADC clock is indispensable and has been achieved by deriving the clock and LO signal from RF signal itself. Control system has been successfully tested in lab with phase and amplitude stability better then ±1% and ±1° respectively. High frequency RF signal is down converted to IF using the super heterodyne technique. Super heterodyne principal not only brings the RF signal to the Low IF frequency at which it can be easily processed but also enables us to use the same hardware and software for other RF frequencies with some minor modification. (author)

  5. High performance image acquisition and processing architecture for fast plant system controllers based on FPGA and GPU

    International Nuclear Information System (INIS)

    Nieto, J.; Sanz, D.; Guillén, P.; Esquembri, S.; Arcas, G. de; Ruiz, M.; Vega, J.; Castro, R.

    2016-01-01

    Highlights: • To test an image acquisition and processing system for Camera Link devices based in a FPGA, compliant with ITER fast controllers. • To move data acquired from the set NI1483-NIPXIe7966R directly to a NVIDIA GPU using NVIDIA GPUDirect RDMA technology. • To obtain a methodology to include GPUs processing in ITER Fast Plant Controllers, using EPICS integration through Nominal Device Support (NDS). - Abstract: The two dominant technologies that are being used in real time image processing are Field Programmable Gate Array (FPGA) and Graphical Processor Unit (GPU) due to their algorithm parallelization capabilities. But not much work has been done to standardize how these technologies can be integrated in data acquisition systems, where control and supervisory requirements are in place, such as ITER (International Thermonuclear Experimental Reactor). This work proposes an architecture, and a development methodology, to develop image acquisition and processing systems based on FPGAs and GPUs compliant with ITER fast controller solutions. A use case based on a Camera Link device connected to an FPGA DAQ device (National Instruments FlexRIO technology), and a NVIDIA Tesla GPU series card has been developed and tested. The architecture proposed has been designed to optimize system performance by minimizing data transfer operations and CPU intervention thanks to the use of NVIDIA GPUDirect RDMA and DMA technologies. This allows moving the data directly between the different hardware elements (FPGA DAQ-GPU-CPU) avoiding CPU intervention and therefore the use of intermediate CPU memory buffers. A special effort has been put to provide a development methodology that, maintaining the highest possible abstraction from the low level implementation details, allows obtaining solutions that conform to CODAC Core System standards by providing EPICS and Nominal Device Support.

  6. High performance image acquisition and processing architecture for fast plant system controllers based on FPGA and GPU

    Energy Technology Data Exchange (ETDEWEB)

    Nieto, J., E-mail: jnieto@sec.upm.es [Grupo de Investigación en Instrumentación y Acústica Aplicada, Universidad Politécnica de Madrid, Crta. Valencia Km-7, Madrid 28031 (Spain); Sanz, D.; Guillén, P.; Esquembri, S.; Arcas, G. de; Ruiz, M. [Grupo de Investigación en Instrumentación y Acústica Aplicada, Universidad Politécnica de Madrid, Crta. Valencia Km-7, Madrid 28031 (Spain); Vega, J.; Castro, R. [Asociación EURATOM/CIEMAT para Fusión, Madrid (Spain)

    2016-11-15

    Highlights: • To test an image acquisition and processing system for Camera Link devices based in a FPGA, compliant with ITER fast controllers. • To move data acquired from the set NI1483-NIPXIe7966R directly to a NVIDIA GPU using NVIDIA GPUDirect RDMA technology. • To obtain a methodology to include GPUs processing in ITER Fast Plant Controllers, using EPICS integration through Nominal Device Support (NDS). - Abstract: The two dominant technologies that are being used in real time image processing are Field Programmable Gate Array (FPGA) and Graphical Processor Unit (GPU) due to their algorithm parallelization capabilities. But not much work has been done to standardize how these technologies can be integrated in data acquisition systems, where control and supervisory requirements are in place, such as ITER (International Thermonuclear Experimental Reactor). This work proposes an architecture, and a development methodology, to develop image acquisition and processing systems based on FPGAs and GPUs compliant with ITER fast controller solutions. A use case based on a Camera Link device connected to an FPGA DAQ device (National Instruments FlexRIO technology), and a NVIDIA Tesla GPU series card has been developed and tested. The architecture proposed has been designed to optimize system performance by minimizing data transfer operations and CPU intervention thanks to the use of NVIDIA GPUDirect RDMA and DMA technologies. This allows moving the data directly between the different hardware elements (FPGA DAQ-GPU-CPU) avoiding CPU intervention and therefore the use of intermediate CPU memory buffers. A special effort has been put to provide a development methodology that, maintaining the highest possible abstraction from the low level implementation details, allows obtaining solutions that conform to CODAC Core System standards by providing EPICS and Nominal Device Support.

  7. Commercial FPGA based multipurpose controller: implementation perspective

    International Nuclear Information System (INIS)

    Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

    2012-01-01

    This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

  8. Fpga As A Part Of Ms Windows Control Environment

    Directory of Open Access Journals (Sweden)

    Krzysztof Kołek

    2007-01-01

    Full Text Available The attention is focused on the Windows operating system (OS used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS.Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

  9. Fast semivariogram computation using FPGA architectures

    Science.gov (United States)

    Lagadapati, Yamuna; Shirvaikar, Mukul; Dong, Xuanliang

    2015-02-01

    The semivariogram is a statistical measure of the spatial distribution of data and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. The semivariogram is a plot of semivariances for different lag distances between pixels. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O(n2). Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform tens of thousands of calculations per clock cycle while operating in the low range of power. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. The design consists of several modules dedicated to the constituent computational tasks. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. Anisotropic semivariogram implementation is anticipated to be an extension of the current architecture, ostensibly based on refinements to the current modules. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from MRI scans are utilized for the experiments

  10. VHDL, FPGA and the master trigger controller of BES

    International Nuclear Information System (INIS)

    Guo Yanan; Wang Jufang; Zhao Dixin

    1996-01-01

    A Master Trigger Controller was made using fast FPGA (Field-Programmable Gate Array) instead of ECLIC (Emitter-Coupled Logic Integrated Circuit). VHDL (Verilog Hardware Description Language) was used in its design. The same performance was obtained with increased flexibility

  11. Fast FPGA Implementation of an Original Impedance Analyser

    Directory of Open Access Journals (Sweden)

    Abdulrahman HAMED

    2011-02-01

    Full Text Available This article describes in detail the design and rapid prototyping of an embedded impedance analyzer. The measurement principle is based on the feedback control of the excitation voltage VD during a fast frequency sweeping. This function is carried out by a high precision synthesizer whose output resistance RG is digitally adjustable. Real and imaginary parts of the dipole impedance are determined from RG and the phase of VD. The digital architecture design uses the hardware-in-the-loop simulation in which the dipole is modeled using an RLC parallel circuit and a Butterworth Van Dyke structure. All digital functions are implemented on a Stratix II FPGA board with a 100 MHz frequency clock. The parameters taken into account are the frequency range (0 to 5 MHz, speed and resolution of the analysis and the quality factor of the resonant dipole. To reduce the analysis duration, the frequency sweeping rate is adjusted in real time.

  12. Protection and Control with FPGA technology

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-03-15

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

  13. Protection and Control with FPGA technology

    International Nuclear Information System (INIS)

    Sohn, K. Y.; Yi, W. J.; Koo, I. S.

    2012-01-01

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper

  14. FPGA based Smart Wireless MIMO Control System

    International Nuclear Information System (INIS)

    Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-01-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

  15. Prototyping Advanced Control Systems on FPGA

    Directory of Open Access Journals (Sweden)

    Simard Stéphane

    2009-01-01

    Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

  16. FPGA controlled artificial vascular system

    Directory of Open Access Journals (Sweden)

    Laqua D.

    2015-09-01

    Full Text Available Monitoring the oxygen saturation of an unborn child is an invasive procedure, so far. Transabdominal fetal pulse oximetry is a promising method under research, used to estimate the oxygen saturation of a fetus noninvasively. Due to the nature of the method, the fetal information needs to be extracted from a mixed signal. To properly evaluate signal processing algorithms, a phantom modeling fetal and maternal blood circuits and tissue layers is necessary. This paper presents an improved hardware concept for an artificial vascular system, utilizing an FPGA based CompactRIO System from National Instruments. The experimental model to simulate the maternal and fetal blood pressure curve consists of two identical hydraulic circuits. Each of these circuits consists of a pre-pressure system and an artificial vascular system. Pulse curves are generated by proportional valves, separating these two systems. The dilation of the fetal and maternal artificial vessels in tissue substitutes is measured by transmissive and reflective photoplethysmography. The measurement results from the pressure sensors and the transmissive optical sensors are visualized to show the functionality of the pulse generating systems. The trigger frequency for the maternal valve was set to 1 per second, the fetal valve was actuated at 0.7 per second for validation. The reflective curve, capturing pulsations of the fetal and maternal circuit, was obtained with a high power LED (905 nm as light source. The results show that the system generates pulse curves, similar to its physiological equivalent. Further, the acquired reflective optical signal is modulated by the alternating diameter of the tubes of both circuits, allowing for tests of signal processing algorithms.

  17. Superconducting cavity driving with FPGA controller

    International Nuclear Information System (INIS)

    Czarski, Tomasz; Koprek, Waldemar; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Simrock, Stefan; Brandt, Alexander; Chase, Brian; Carcagno, Ruben; Cancelo, Gustavo; Koeth, Timothy W.

    2006-01-01

    A digital control of superconducting cavities for a linear accelerator is presented. FPGA-based controller, supported by Matlab system, was applied. Electrical model of a resonator was used for design of a control system. Calibration of the signal path is considered. Identification of cavity parameters has been carried out for adaptive control algorithm. Feed-forward and feedback modes were applied in operating the cavities. Required performance has been achieved; i.e. driving on resonance during filling and field stabilization during flattop time, while keeping reasonable level of the power consumption. Representative results of the experiments are presented for different levels of the cavity field gradient

  18. Superconducting cavity driving with FPGA controller

    Energy Technology Data Exchange (ETDEWEB)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland); Simrock, S.; Brand, A. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Chase, B.; Carcagno, R.; Cancelo, G. [Fermi National Accelerator Lab., Batavia, IL (United States); Koeth, T.W. [Rutgers - the State Univ. of New Jersey, NJ (United States)

    2006-07-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

  19. Superconducting cavity driving with FPGA controller

    International Nuclear Information System (INIS)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S.; Simrock, S.; Brand, A.; Chase, B.; Carcagno, R.; Cancelo, G.; Koeth, T.W.

    2006-01-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

  20. FPGA based Control of a Production Cell System

    NARCIS (Netherlands)

    Groothuis, M.A.; van Zuijlen, Jasper J.P.; Broenink, Johannes F.

    Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control

  1. Control de acceso usando FPGA y RFID

    Directory of Open Access Journals (Sweden)

    Dora Luz Almanza Ojeda

    2012-10-01

    Full Text Available Este trabajo presenta el diseño e implementación de un sistema de control de acceso mediante Identificación por Radiofrecuencia (RFID, Radio Frequency Identification controlado por una Matriz de compuertas programables (FPGA, Field Programmable Gate Array. El sistema está constituido por un par de dispositivos de adquisición de radiofrecuencia, una FPGA, un juego de etiquetas y tarjetas pasivas de identificación. Mediante una interfaz gráfica de usuario es posible controlar todo movimiento dentro de una zona determinada, desde los accesos hasta la disponibilidad de equipo; utilizando los dispositivos de adquisición de radiofrecuencia se puede acceder a la información de los usuarios autorizados, así como al control del equipo. Con este sistema es posible monitorear, administrar y reportar todo acceso de personal, movimiento de equipo o plagio de manera eficiente y evitando un gran número de errores humanos.  

  2. Development of FPGA-Based Control Board

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Yoon Hee; Jeong, See Chae; Choi, Woong Seock; Lee, Chang Jae; Jeong, Jin Kwon; Ha, Jae Hong [Korea Power Engineering Company Inc., Daejeon (Korea, Republic of)

    2009-10-15

    It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a FPGAbased control board performing user-defined control functions. An Actel ProASIC{sup plus} FPGA platform is implemented as the comparator of Plant Protection System (PPS). Functional simulation is implemented for the comparator.

  3. fpga controller design and simulation of a portable dough mixing

    African Journals Online (AJOL)

    modelled and simulated with Matlab/Simulink. Synthesizable VHDL ... Keywords: FPGA, VHDL, PID controller, Pulse Width Modulation, Full H-Bridge DC motor driver. 1. ... and (b) to simulate the control process in a virtual environment, using.

  4. Fpga-based control of piezoelectric actuators

    Directory of Open Access Journals (Sweden)

    Juhász László

    2011-01-01

    Full Text Available In many industrial applications like semiconductor production and optical inspection systems, the availability of positioning systems capable to follow trajectory paths in the range of several centimetres, featuring at the same time a nanometre-range precision, is demanding. Pure piezoelectric stages and standard positioning systems with motor and spindle are not able to meet such requirements, because of the small operation range and inadequacies like backlash and friction. One concept for overcoming these problems consists of a hybrid positioning system built through the integration of a DC-drive in series with a piezoelectric actuator. The wide range of potential applications enables a considerable market potential for such an actuator, but due to the high variety of possible positioned objects and dynamic requirements, the required control complexity may be significant. In this paper, a real-time capable state-space control concept for the piezoelectric actuators, embedded in such a hybrid micropositioning system, is presented. The implementation of the controller together with a real-time capable hysteresis compensation measure is performed using a low-budget FPGA-board, whereas the superimposed integrated controller is realized with a dSPACE RCP-system. The advantages of the designed control over a traditional proportional-integral control structure are proven through experimental results using a commercially available hybrid micropositioning system. Positioning results by different dynamic requirements featuring positioning velocities from 1 μm/s up to 5 cm/s are given.

  5. Design of optical axis jitter control system for multi beam lasers based on FPGA

    Science.gov (United States)

    Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

    2018-02-01

    A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

  6. Burst-Mode Asynchronous Controllers on FPGA

    Directory of Open Access Journals (Sweden)

    Duarte L. Oliveira

    2008-01-01

    Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

  7. FPGA based fast synchronous serial multi-wire links synchronization

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2013-10-01

    The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

  8. LAPACKrc: Fast linear algebra kernels/solvers for FPGA accelerators

    International Nuclear Information System (INIS)

    Gonzalez, Juan; Nunez, Rafael C

    2009-01-01

    We present LAPACKrc, a family of FPGA-based linear algebra solvers able to achieve more than 100x speedup per commodity processor on certain problems. LAPACKrc subsumes some of the LAPACK and ScaLAPACK functionalities, and it also incorporates sparse direct and iterative matrix solvers. Current LAPACKrc prototypes demonstrate between 40x-150x speedup compared against top-of-the-line hardware/software systems. A technology roadmap is in place to validate current performance of LAPACKrc in HPC applications, and to increase the computational throughput by factors of hundreds within the next few years.

  9. FPGA implementation of adaptive ANN controller for speed regulation of permanent magnet stepper motor drives

    Energy Technology Data Exchange (ETDEWEB)

    Hasanien, Hany M., E-mail: Hanyhasanien@ieee.or [Dept. of Elec. Power and Machines, Faculty of Eng., Ain Shams Univ., Cairo (Egypt)

    2011-02-15

    This paper presents a novel adaptive artificial neural network (ANN) controller, which applies on permanent magnet stepper motor (PMSM) for regulating its speed. The dynamic response of the PMSM with the proposed controller is studied during the starting process under the full load torque and under load disturbance. The effectiveness of the proposed adaptive ANN controller is then compared with that of the conventional PI controller. The proposed methodology solves the problem of nonlinearities and load changes of PMSM drives. The proposed controller ensures fast and accurate dynamic response with an excellent steady state performance. Matlab/Simulink tool is used for this dynamic simulation study. The main contribution of this work is the implementation of the proposed controller on field programmable gate array (FPGA) hardware to drive the stepper motor. The driver is built on FPGA Spartan-3E Starter from Xilinx. Experimental results are presented to demonstrate the validity and effectiveness of the proposed control scheme.

  10. FPGA implementation of adaptive ANN controller for speed regulation of permanent magnet stepper motor drives

    International Nuclear Information System (INIS)

    Hasanien, Hany M.

    2011-01-01

    This paper presents a novel adaptive artificial neural network (ANN) controller, which applies on permanent magnet stepper motor (PMSM) for regulating its speed. The dynamic response of the PMSM with the proposed controller is studied during the starting process under the full load torque and under load disturbance. The effectiveness of the proposed adaptive ANN controller is then compared with that of the conventional PI controller. The proposed methodology solves the problem of nonlinearities and load changes of PMSM drives. The proposed controller ensures fast and accurate dynamic response with an excellent steady state performance. Matlab/Simulink tool is used for this dynamic simulation study. The main contribution of this work is the implementation of the proposed controller on field programmable gate array (FPGA) hardware to drive the stepper motor. The driver is built on FPGA Spartan-3E Starter from Xilinx. Experimental results are presented to demonstrate the validity and effectiveness of the proposed control scheme.

  11. FPGA-based fully digital fast power switch fault detection and compensation for three-phase shunt active filters

    Energy Technology Data Exchange (ETDEWEB)

    Karimi, S.; Saadate, S. [Groupe de Recherche en Electrotechnique et Electronique de Nancy, GREEN-UHP, CNRS UMR 7037 (France); Poure, P. [Laboratoire d' Instrumentation Electronique de Nancy, LIEN, EA 3440, France Nancy Universite - Universite Henri Poincare de Nancy I, BP 239, 54506 Vandoeuvre les Nancy cedex (France)

    2008-11-15

    This paper discusses the design, implementation, experimental validation and performances of a fully digital fast power switch fault detection and compensation for three-phase shunt active power filters. The approach introduced in this paper minimizes the time interval between the fault occurrence and its diagnosis. This paper demonstrates the possibility to detect a faulty switch of the active filter in less than 10 {mu}s by using simultaneously a ''time criterion'' and a ''voltage criterion''. In order to attain this fast detection time a FPGA (Field Programmable Gate Array) is used. The other feature introduced in this approach is that the control scheme used to compensate the current load harmonics and fault tolerant scheme are both programmed in only one FPGA. ''FPGA in the loop'' prototyping results and fully experimental results based on a real active power filter verify satisfactory performances of the proposed method. (author)

  12. Photoelectric radar servo control system based on ARM+FPGA

    Science.gov (United States)

    Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

    2016-01-01

    In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

  13. FPGA Mezzanine Cards for CERN’s Accelerator Control System

    CERN Document Server

    Alvarez, P R; Lewis, J; Serrano, J; Wlostowski, T

    2009-01-01

    Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, PCI and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed...

  14. FPGA based VME boards for Indus-2 timing control system

    International Nuclear Information System (INIS)

    Lulani, Nitin; Barpande, K.; Fatnani, P.; Sheth, Y.

    2009-01-01

    FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards. (author)

  15. Fast neuromimetic object recognition using FPGA outperforms GPU implementations.

    Science.gov (United States)

    Orchard, Garrick; Martin, Jacob G; Vogelstein, R Jacob; Etienne-Cummings, Ralph

    2013-08-01

    Recognition of objects in still images has traditionally been regarded as a difficult computational problem. Although modern automated methods for visual object recognition have achieved steadily increasing recognition accuracy, even the most advanced computational vision approaches are unable to obtain performance equal to that of humans. This has led to the creation of many biologically inspired models of visual object recognition, among them the hierarchical model and X (HMAX) model. HMAX is traditionally known to achieve high accuracy in visual object recognition tasks at the expense of significant computational complexity. Increasing complexity, in turn, increases computation time, reducing the number of images that can be processed per unit time. In this paper we describe how the computationally intensive and biologically inspired HMAX model for visual object recognition can be modified for implementation on a commercial field-programmable aate Array, specifically the Xilinx Virtex 6 ML605 evaluation board with XC6VLX240T FPGA. We show that with minor modifications to the traditional HMAX model we can perform recognition on images of size 128 × 128 pixels at a rate of 190 images per second with a less than 1% loss in recognition accuracy in both binary and multiclass visual object recognition tasks.

  16. A fast readout algorithm for Cluster Counting/Timing drift chambers on a FPGA board

    Energy Technology Data Exchange (ETDEWEB)

    Cappelli, L. [Università di Cassino e del Lazio Meridionale (Italy); Creti, P.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Pepino, A., E-mail: Aurora.Pepino@le.infn.it [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Tassielli, G. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Fermilab, Batavia, IL (United States); Università Marconi, Roma (Italy)

    2013-08-01

    A fast readout algorithm for Cluster Counting and Timing purposes has been implemented and tested on a Virtex 6 core FPGA board. The algorithm analyses and stores data coming from a Helium based drift tube instrumented by 1 GSPS fADC and represents the outcome of balancing between cluster identification efficiency and high speed performance. The algorithm can be implemented in electronics boards serving multiple fADC channels as an online preprocessing stage for drift chamber signals.

  17. Modular and reconfigurable common PCB-platform of FPGA based LLRF control system for TESLA test facility

    Energy Technology Data Exchange (ETDEWEB)

    Pozniak, K.T.; Romaniuk, R.S. [Institute of Electronic Systems, Warsaw (Poland); Kierzkowski, K. [Institute of Experimental Physics, Warsaw (Poland)

    2005-07-01

    The paper includes a description of predicted functionalities to be implemented in a universal motherboard (MB) for the next generation of LLRF control system for TESLA. The motherboard bases on a number of quasi-autonomous embedded executive modules. The modules are implemented in a few FPGA chips featured by the MB. The paper presents a practical design of the MB. The initial (basic) solution of the MB has the Cyclone as the chip where the board management is embedded. The board features communication modules - VME and micro, single chip PC with Ethernet. The board provides power supply for the FPGA chips. The board has fast internal communication between particular modules. (orig.)

  18. Modular and reconfigurable common PCB-platform of FPGA based LLRF control system for TESLA test facility

    International Nuclear Information System (INIS)

    Pozniak, K.T.; Romaniuk, R.S.; Kierzkowski, K.

    2005-01-01

    The paper includes a description of predicted functionalities to be implemented in a universal motherboard (MB) for the next generation of LLRF control system for TESLA. The motherboard bases on a number of quasi-autonomous embedded executive modules. The modules are implemented in a few FPGA chips featured by the MB. The paper presents a practical design of the MB. The initial (basic) solution of the MB has the Cyclone as the chip where the board management is embedded. The board features communication modules - VME and micro, single chip PC with Ethernet. The board provides power supply for the FPGA chips. The board has fast internal communication between particular modules. (orig.)

  19. Realization of manchester encoding and decoding and fast-speed communication for digital power supply based on FPGA

    International Nuclear Information System (INIS)

    Chen Huanguang; Xu Ruinian; Shen Tianjian; Li Deming

    2008-01-01

    A design and simulation to realize the process of Manchester encoding and decoding, to realize the process of SPI communication between FPGA and DSP, using Altera company's Quartus II IDE on FPGA is presented in this paper. And the application on the digital power supply controller with Manchester communication by optical fiber is introduced. (authors)

  20. A fast improved fat tree encoder for wave union TDC in an FPGA

    International Nuclear Information System (INIS)

    Shen Qi; Zhao Lei; Liu Shubin; Qi Binxiang; Hu Xueye; An Qi; Liao Shengkai; Peng Chengzhi

    2013-01-01

    Up to now, the wave union method can achieve the best timing performance in FPGA-based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands that the encoder convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder (IFTE) to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constraints were required; therefore, this IFTE structure could also be further applied in other delay-chain-based FPGA TDCs. (authors)

  1. Enhanced Temperature Control Method Using ANFIS with FPGA

    Directory of Open Access Journals (Sweden)

    Chiung-Wei Huang

    2014-01-01

    Full Text Available Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS using a field-programmable gate array (FPGA to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV inductively-coupled plasma- (ICP- type etcher.

  2. Optical network and FPGA/DSP based control system for free electron laser

    International Nuclear Information System (INIS)

    Romaniuk, R.S.; Pozniak, K.T.; Czarski, T.; Czuba, K.; Giergusiewicz, W.; Kasprowicz, G.; Koprek, W.

    2005-01-01

    The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to

  3. Hardware and Software Integration in Project Development of Automated Controller System Using LABVIEW FPGA

    International Nuclear Information System (INIS)

    Mohd Khairulezwan Abd Manan; Mohd Sabri Minhat; Izhar Abu Hussin

    2014-01-01

    The Field-Programmable Gate Array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows user to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field, hence the name field-programmable. This project developed a control system using LabVIEW FPGA. LabVIEW FPGA is easier where it is programmed by using drag and drop icon. Then it will be integrated with the hardware input and output. (author)

  4. FPGA platform for MEMS Disc Resonance Gyroscope (DRG) control

    Science.gov (United States)

    Keymeulen, Didier; Peay, Chris; Foor, David; Trung, Tran; Bakhshi, Alireza; Withington, Phil; Yee, Karl; Terrile, Rich

    2008-04-01

    Inertial navigation systems based upon optical gyroscopes tend to be expensive, large, power consumptive, and are not long lived. Micro-Electromechanical Systems (MEMS) based gyros do not have these shortcomings; however, until recently, the performance of MEMS based gyros had been below navigation grade. Boeing and JPL have been cooperating since 1997 to develop high performance MEMS gyroscopes for miniature, low power space Inertial Reference Unit applications. The efforts resulted in demonstration of a Post Resonator Gyroscope (PRG). This experience led to the more compact Disc Resonator Gyroscope (DRG) for further reduced size and power with potentially increased performance. Currently, the mass, volume and power of the DRG are dominated by the size of the electronics. This paper will detail the FPGA based digital electronics architecture and its implementation for the DRG which will allow reduction of size and power and will increase performance through a reduction in electronics noise. Using the digital control based on FPGA, we can program and modify in real-time the control loop to adapt to the specificity of each particular gyro and the change of the mechanical characteristic of the gyro during its life time.

  5. FPGA Implementation of Real-Time Ethernet for Motion Control

    Directory of Open Access Journals (Sweden)

    Chen Youdong

    2013-01-01

    Full Text Available This paper provides an applicable implementation of real-time Ethernet named CASNET, which modifies the Ethernet medium access control (MAC to achieve the real-time requirement for motion control. CASNET is the communication protocol used for motion control system. Verilog hardware description language (VHDL has been used in the MAC logic design. The designed MAC serves as one of the intellectual properties (IPs and is applicable to various industrial controllers. The interface of the physical layer is RJ45. The other layers have been implemented by using C programs. The real-time Ethernet has been implemented by using field programmable gate array (FPGA technology and the proposed solution has been tested through the cycle time, synchronization accuracy, and Wireshark testing.

  6. Fast SPT-Term Allocation and Efficient FPGA Implementation of FIR Filters for Software Defined Radio Applications

    OpenAIRE

    Bae, Choonghoon; Moteki, Takayuki; Kim, Minseok; Ichige, Koichi; Arai, Hiroyuki

    2009-01-01

    This paper presents a fast SPT-term allocation scheme and an efficient FPGA implementation of FIR filters for Software Defined Radio (SDR) applications. Direct conversion method based on RF direct sampling is nowadays widely used in SDR applications. Fast and accurate digital filters are required for RF direct sampling and processing in direct conversion, however such filters often require large digital circuit area. Signed-Power-of-Two (SPT) terms will be suitable for fast processing and eff...

  7. A minimal SATA III Host Controller based on FPGA

    Science.gov (United States)

    Liu, Hailiang

    2018-03-01

    SATA (Serial Advanced Technology Attachment) is an advanced serial bus which has a outstanding performance in transmitting high speed real-time data applied in Personal Computers, Financial Industry, astronautics and aeronautics, etc. In this express, a minimal SATA III Host Controller based on Xilinx Kintex 7 serial FPGA is designed and implemented. Compared to the state-of-art, registers utilization are reduced 25.3% and LUTs utilization are reduced 65.9%. According to the experimental results, the controller works precisely and steady with the reading bandwidth of up to 536 MB per second and the writing bandwidth of up to 512 MB per second, both of which are close to the maximum bandwidth of the SSD(Solid State Disk) device. The host controller is very suitable for high speed data transmission and mass data storage.

  8. Central FPGA-based destination and load control in the LHCb MHz event readout

    Science.gov (United States)

    Jacobsson, R.

    2012-10-01

    The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

  9. Central FPGA-based destination and load control in the LHCb MHz event readout

    International Nuclear Information System (INIS)

    Jacobsson, R.

    2012-01-01

    The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

  10. New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project

    CERN Document Server

    Mendez, Julian Maxime; Caratelli, Alessandro; Leitao, Pedro Vicente

    2018-01-01

    The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

  11. An FPGA based control unit for synchronization of laser Thomson scattering measurements to plasma events on MAST

    International Nuclear Information System (INIS)

    Naylor, G.A.

    2010-01-01

    The power and flexibility of modern Field Programmable Gate Arrays (FPGAs) is now being recognised in many areas of instrumentation and control . The high performance of modern ADCs and the high throughput of FPGAs allow the emulation of many specialised analogue instruments. The functions of heterodyne detection, phase measurements, spectrum analyzers, phase sensitive detectors, counters, etc. can be achieved in relatively simple hardware using an FPGA. The complex filtering functions can be efficiently performed digitally in the FPGA, without recourse to a separate DSP chip. This paper describes the use of a custom off the shelf FPGA board with a collection of custom interface boards to produce a powerful custom trigger system. This has been developed for agile triggering of YAG lasers on MAST. This unit allows various analogue inputs including magnetics data to be processed in real-time and allow Thomson scattering data to be collected at accurate times with respect to randomly occurring MHD phenomena such as neoclassical tearing modes (NTMs). The FPGA allows a 'System On a Chip' architecture in order to perform fast filtering in logic coupled to a dedicated soft processor for real-time fixed latency operations and a second soft processor to handle external communications with the control system for system configuration and reporting of status/archived data. The use of such a generic structure in order to provide a common approach, with reduced software development times, for diverse diagnostic situations will be discussed.

  12. FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments

    CERN Document Server

    Pozniak, Krzysztof T

    2004-01-01

    The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY) . A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.

  13. Fuzzy Controller Design Using FPGA for Photovoltaic Maximum Power Point Tracking

    OpenAIRE

    Basil M Hamed; Mohammed S. El-Moghany

    2012-01-01

    The cell has optimum operating point to be able to get maximum power. To obtain Maximum Power from photovoltaic array, photovoltaic power system usually requires Maximum Power Point Tracking (MPPT) controller. This paper provides a small power photovoltaic control system based on fuzzy control with FPGA technology design and implementation for MPPT. The system composed of photovoltaic module, buck converter and the fuzzy logic controller implemented on FPGA for controlling on/off time of MOSF...

  14. High Performance and Energy Efficient Traffic Light Controller Design Using FPGA

    DEFF Research Database (Denmark)

    Pandey, Sujeet; Shrivastav, Vivek Kumar; Sharma, Rashmi

    2017-01-01

    and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER......In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA...

  15. Development of an FPGA-Based Motion Control IC for Caving Machine

    Directory of Open Access Journals (Sweden)

    Chiu-Keng Lai

    2014-03-01

    Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

  16. Implementation of FPGA based PID Controller for DC Motor Speed Control System

    Directory of Open Access Journals (Sweden)

    Savita SONOLI

    2010-03-01

    Full Text Available In this paper, the implementation of software module using ‘VHDL’ for Xilinx FPGA (XC3S400 based PID controller for DC motor speed control system is presented. The tools used for building and testing the software modules are Xilinx ISE 9.2i and ModelSim XE III 6.3c. Before verifying the design on FPGA the complete design is simulated using Modelsim Simulation tool. A test bench is written where the set speed can be changed for the motor. It is observed that the motor speed gradually changes to the set speed and locks to the set speed.

  17. A parallel FPGA implementation for real-time 2D pixel clustering for the ATLAS Fast Tracker Processor

    International Nuclear Information System (INIS)

    Sotiropoulou, C L; Gkaitatzis, S; Kordas, K; Nikolaidis, S; Petridou, C; Annovi, A; Beretta, M; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility makes the implementation suitable for a variety of demanding image processing applications. The implementation is robust against bit errors in the input data stream and drops all data that cannot be identified. In the unlikely event of missing control words, the implementation will ensure stable data processing by inserting the missing control words in the data stream. The 2D pixel clustering implementation is developed and tested in both single flow and parallel versions. The first parallel version with 16 parallel cluster identification engines is presented. The input data from the RODs are received through S-Links and the processing units that follow the clustering implementation also require a single data stream, therefore data parallelizing (demultiplexing) and serializing (multiplexing) modules are introduced in order to accommodate the parallelized version and restore the data stream afterwards. The results of the first hardware tests of

  18. An FPGA- Based General-Purpose Data Acquisition Controller

    Science.gov (United States)

    Robson, C. C. W.; Bousselham, A.; Bohm

    2006-08-01

    System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems

  19. FPGA-based real time implementation of MPPT-controller for photovoltaic systems

    Energy Technology Data Exchange (ETDEWEB)

    Mellit, A.; Rezzouk, H.; Medjahed, B. [Faculty of Sciences and Technology, Jijel University, Ouled-aissa, P.O. Box 98, Jijel 18000 (Algeria); Messai, A. [CRNB Ain Oussera, P.O. Box 180, 17200 Djelfa (Algeria)

    2011-05-15

    In this paper an FPGA-based implementation of a real time perturb and observe (P and O) algorithm for tracking the Maximum Power Point (MPP) of a photovoltaic (PV) generator is presented. The P and O algorithm has been designed using the very high-speed description language (VHDL) and implemented on Xilinx Virtex-II-Pro(xc2v1000-4fg456) - Field Programmable Gate Array (FPGA). The algorithm and the hardware have been simulated and tested by conditioning the power produced by the PV-modules installed on the rooftop of the ''Hall of Technology Laboratory'' at Jijel University. The main advantages of the developed MPPT are low cost, good velocity, acceptable reliability, and easy implementation. However, its main disadvantage is related to the fact that for fast changes in irradiance it may fail to track the maximum power point. The efficiency of the implemented P and O controller is about 96%. (author)

  20. An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

    International Nuclear Information System (INIS)

    Jung, Sejin; Kim, Eui-Sub; Yoo, Junbeom; Kim, Jang-Yeol; Choi, Jong Gyun

    2016-01-01

    Highlights: • All direct/indirect COTS SW should be dedicated. • FPGA synthesis tools are important for the safety of new digital I&Cs. • No standards/reports are yet available to deal with the indirect SW – FPGA synthesis tools. • This paper proposes a new evaluation/acceptance process and criteria for indirect SW. - Abstract: FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

  1. A New FPGA Architecture of FAST and BRIEF Algorithm for On-Board Corner Detection and Matching

    Directory of Open Access Journals (Sweden)

    Jingjin Huang

    2018-03-01

    Full Text Available Although some researchers have proposed the Field Programmable Gate Array (FPGA architectures of Feature From Accelerated Segment Test (FAST and Binary Robust Independent Elementary Features (BRIEF algorithm, there is no consideration of image data storage in these traditional architectures that will result in no image data that can be reused by the follow-up algorithms. This paper proposes a new FPGA architecture that considers the reuse of sub-image data. In the proposed architecture, a remainder-based method is firstly designed for reading the sub-image, a FAST detector and a BRIEF descriptor are combined for corner detection and matching. Six pairs of satellite images with different textures, which are located in the Mentougou district, Beijing, China, are used to evaluate the performance of the proposed architecture. The Modelsim simulation results found that: (i the proposed architecture is effective for sub-image reading from DDR3 at a minimum cost; (ii the FPGA implementation is corrected and efficient for corner detection and matching, such as the average value of matching rate of natural areas and artificial areas are approximately 67% and 83%, respectively, which are close to PC’s and the processing speed by FPGA is approximately 31 and 2.5 times faster than those by PC processing and by GPU processing, respectively.

  2. A New FPGA Architecture of FAST and BRIEF Algorithm for On-Board Corner Detection and Matching.

    Science.gov (United States)

    Huang, Jingjin; Zhou, Guoqing; Zhou, Xiang; Zhang, Rongting

    2018-03-28

    Although some researchers have proposed the Field Programmable Gate Array (FPGA) architectures of Feature From Accelerated Segment Test (FAST) and Binary Robust Independent Elementary Features (BRIEF) algorithm, there is no consideration of image data storage in these traditional architectures that will result in no image data that can be reused by the follow-up algorithms. This paper proposes a new FPGA architecture that considers the reuse of sub-image data. In the proposed architecture, a remainder-based method is firstly designed for reading the sub-image, a FAST detector and a BRIEF descriptor are combined for corner detection and matching. Six pairs of satellite images with different textures, which are located in the Mentougou district, Beijing, China, are used to evaluate the performance of the proposed architecture. The Modelsim simulation results found that: (i) the proposed architecture is effective for sub-image reading from DDR3 at a minimum cost; (ii) the FPGA implementation is corrected and efficient for corner detection and matching, such as the average value of matching rate of natural areas and artificial areas are approximately 67% and 83%, respectively, which are close to PC's and the processing speed by FPGA is approximately 31 and 2.5 times faster than those by PC processing and by GPU processing, respectively.

  3. Design and implementation of FPGA-based LQ control of active magnetic bearings

    Energy Technology Data Exchange (ETDEWEB)

    Jastrzebski, R.

    2007-07-01

    The need for high performance, high precision, and energy saving in rotating machinery demands an alternative solution to traditional bearings. Because of the contactless operation principle, the rotating machines employing active magnetic bearings (AMBs) provide many advantages over the traditional ones. The advantages such as contamination-free operation, low maintenance costs, high rotational speeds, low parasitic losses, programmable stiffness and damping, and vibration insulation come at expense of high cost, and complex technical solution. All these properties make the use of AMBs appropriate primarily for specific and highly demanding applications. High performance and high precision control requires model-based control methods and accurate models of the flexible rotor. In turn, complex models lead to high-order controllers and feature considerable computational burden. Fortunately, in the last few years the advancements in signal processing devices provide new perspective on the real-time control of AMBs. The design and the real-time digital implementation of the high-order LQ controllers, which focus on fast execution times, are the subjects of this work. In particular, the control design and implementation in the field programmable gate array (FPGA) circuits are investigated. The optimal design is guided by the physical constraints of the system for selecting the optimal weighting matrices. The plant model is complemented by augmenting appropriate disturbance models. The compensation of the force-field nonlinearities is proposed for decreasing the uncertainty of the actuator. A disturbance-observer-based unbalance compensation for canceling the magnetic force vibrations or vibrations in the measured positions is presented. The theoretical studies are verified by the practical experiments utilizing a custom-built laboratory test rig. The test rig uses a prototyping control platform developed in the scope of this work. To sum up, the work makes a step in

  4. A FPGA Approach in a Motorised Linear Stage Remote Controlled Experiment

    Directory of Open Access Journals (Sweden)

    Stamen Gadzhanov

    2013-04-01

    Full Text Available In recent years, an advanced motion control software for rapid development has been introduced by National Instruments, accompanied by innovative and improved FPGA-based hardware platforms. Compared to the well-known standard NI DAQ PCI/USB board solutions, this new approach offers robust stability in a deterministic real-time environment combined with the highest possible performance and re-configurability of the FPGA core. The NI Compact RIO (cRIO Real Time Controller utilises two distinctive interface modes of functionality: Scan and FPGA modes. This paper presents an application of a motion control flexible workbench based on the FPGA module, and analyses the advantages and disadvantages in comparison to another approach - the LabVIEW NI SoftMotion module run in scan interface mode. The workbench replicates real industrial applications and is very useful for experimentation with Brushless DC/ Permanent Magnet Synchronous motors and drives, and feedback devices.

  5. Development of FPGA-based safety-related instrumentation and control systems

    Energy Technology Data Exchange (ETDEWEB)

    Oda, N.; Tanaka, A.; Izumi, M.; Tarumi, T.; Sato, T. [Toshiba Corporation, Isogo Nuclear Engineering Center, Yokohama (Japan)

    2004-07-01

    Toshiba has developed systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related instrumentation and control systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  6. Compatibility of Anfis controller and FPGA in solar power generation for a domestic oad

    Directory of Open Access Journals (Sweden)

    Arulprakash Andigounder

    2016-06-01

    Full Text Available Among other soft computing techniques, the Adaptive Neuro Fuzzy Inference System (Anfis gives a significant and advantageous result in solar power generation, especially in tracking the maximum power point. Due to the dynamic nature of solar irradiance and temperature, efficient energy conversion is not possible. However, advancements in the areas of artificial intelligence have made it possible to overcome the hurdles. The Maximum Power Point Tracking (MPPT technique adopting the advantages of Anfis has been proven to be more successful with a fast dynamic response and high accuracy. The complete system is modeled using Matlab/Simulink; the hardware results are validated with the benefits of Field Programmable Logic Array (FPGA instead of ordinary micro-controllers.

  7. Embedded system in FPGA-based LLRF controller for FLASH

    Science.gov (United States)

    Szewinski, Jaroslaw; Pucyk, Piotr; Jalmuzna, Wojciech; Fafara, Przemyslaw; Pieciukiewicz, Marcin; Romaniuk, Ryszard; Pozniak, Krzysztof T.

    2006-10-01

    FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

  8. Innovative approach to implementation of FPGA-based NPP instrumentation and control systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Siora, Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper. (author)

  9. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; SIORA Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper

  10. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    Energy Technology Data Exchange (ETDEWEB)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir [Centre for Safety Infrastructure-Oriented Research and Analysis, Kharkov (Ukraine); SIORA Alexander [Research and Production Corporation Radiy, Kirovograd (Ukraine)

    2011-08-15

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper.

  11. Development of an FPGA-based controller for safety critical application

    International Nuclear Information System (INIS)

    Xing, A.; De Grosbois, J.; Sklyar, V.; Archer, P.; Awwal, A.

    2011-01-01

    In implementing safety functions, Field Programmable Gate Arrays (FPGA) technology offers a distinct combination of benefits and advantages over microprocessor-based systems. FPGAs can be designed such that the final product is purely hardware, without any overhead runtime software, bringing the design closer to a conventional hardware-based solution. On the other hand, FPGAs can implement more complex safety logic that would generally require microprocessor-based safety systems. There are now qualified FPGA-based platforms available on the market with a credible use history in safety applications in nuclear power plants. Atomic Energy of Canada (AECL), in collaboration with RPC Radiy, has initiated a development program to define a vigorous FPGA engineering process suitable for implementing safety critical functions at the application development level. This paper provides an update on the FPGA development program along with the proposed design model using function block diagrams for the development of safety controllers in CANDU applications. (author)

  12. Application of the Information Encryption Technology in the Industrial Control Network Based on FPGA

    Directory of Open Access Journals (Sweden)

    Guo Yao-Hua

    2014-07-01

    Full Text Available With the rapid development of information technology industry, Information encryption is an effective means of information security. Data encryption system based on FPGA in the field of industry is elaborated in this paper, and the data acquisition module, the basic principle of 3DES algorithm, its implementation in FPGA and PMC bus interface module are introduced. Based on the function simulation, test and analysis of the design results, this scheme has the characteristics of high reliability, fast algorithm and less hardware resources, and it can be widely used in industrial networks.

  13. A PMSM current controller system on FPGA platform | Ahmadian ...

    African Journals Online (AJOL)

    Journal of Fundamental and Applied Sciences ... Proposed system architecture and computational blocks are described and system level and RTL simulation results are presented. Simulation results show that the total computation cycle time of implemented system on Altera Cyclone II FPGA is 456ns. Keywords: PMSM ...

  14. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    Energy Technology Data Exchange (ETDEWEB)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I. [Research and Production Corporation Radiy, 29 Geroev Stalingrada Str., Kirovograd 25006 (Ukraine); Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A., E-mail: marketing@radiy.co [Center for Safety Infrastructure-Oriented Research and Analysis, 37 Astronomicheskaya Str., Kharkiv 61085 (Ukraine)

    2010-10-15

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY{sup TM} platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY{sup TM} platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY{sup TM} platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  15. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    International Nuclear Information System (INIS)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I.; Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A.

    2010-10-01

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY TM platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY TM platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY TM platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  16. Real Time Implementation of a DC Motor Speed Control by Fuzzy Logic Controller and PI Controller Using FPGA

    Directory of Open Access Journals (Sweden)

    G. Sakthivel

    2010-10-01

    Full Text Available Fuzzy logic control has met with growing interest in many motor control applications due to its non-linearity, handling features and independence of plant modelling. The hardware implementation of fuzzy logic controller (FLC on FPGA is very important because of the increasing number of fuzzy applications requiring highly parallel and high speed fuzzy processing. Implementation of a fuzzy logic controller and conventional PI controller on an FPGA using VHDL for DC motor speed control is presented in this paper. The proposed scheme is to improve tracking performance of D.C. motor as compared to the conventional (PI control strategy .This paper describes the hardware implementation of two inputs (error and change in error, one output fuzzy logic controller based on PI controller and conventional PI controller using VHDL. Real time implementation FLC and conventional PI controller is made on Spartan-3A DSP FPGA (XC3SD1800A FPGA for the speed control of DC motor. It is observed that fuzzy logic based controllers give better responses than the conventional PI controller for the speed control of dc motor.

  17. Remote monitoring and fault recovery for FPGA-based field controllers of telescope and instruments

    Science.gov (United States)

    Zhu, Yuhua; Zhu, Dan; Wang, Jianing

    2012-09-01

    As the increasing size and more and more functions, modern telescopes have widely used the control architecture, i.e. central control unit plus field controller. FPGA-based field controller has the advantages of field programmable, which provide a great convenience for modifying software and hardware of control system. It also gives a good platform for implementation of the new control scheme. Because of multi-controlled nodes and poor working environment in scattered locations, reliability and stability of the field controller should be fully concerned. This paper mainly describes how we use the FPGA-based field controller and Ethernet remote to construct monitoring system with multi-nodes. When failure appearing, the new FPGA chip does self-recovery first in accordance with prerecovery strategies. In case of accident, remote reconstruction for the field controller can be done through network intervention if the chip is not being restored. This paper also introduces the network remote reconstruction solutions of controller, the system structure and transport protocol as well as the implementation methods. The idea of hardware and software design is given based on the FPGA. After actual operation on the large telescopes, desired results have been achieved. The improvement increases system reliability and reduces workload of maintenance, showing good application and popularization.

  18. DOOCS environment for FPGA-based cavity control system and control algorithms development

    International Nuclear Information System (INIS)

    Pucyk, P.; Koprek, W.; Kaleta, P.; Szewinski, J.; Pozniak, K.T.; Czarski, T.; Romaniuk, R.S.

    2005-01-01

    The paper describes the concept and realization of the DOOCS control software for FPGAbased TESLA cavity controller and simulator (SIMCON). It bases on universal software components, created for laboratory purposes and used in MATLAB based control environment. These modules have been recently adapted to the DOOCS environment to ensure a unified software to hardware communication model. The presented solution can be also used as a general platform for control algorithms development. The proposed interfaces between MATLAB and DOOCS modules allow to check the developed algorithm in the operation environment before implementation in the FPGA. As the examples two systems have been presented. (orig.)

  19. TESLA cavity modeling and digital implementation in FPGA technology for control system development

    International Nuclear Information System (INIS)

    Czarski, T.; Pozniak, K.T.; Romaniuk, R.S.; Simrock, S.

    2006-01-01

    The electromechanical model of the TESLA cavity has been implemented in FPGA technology for real-time testing of the control system. The model includes Lorentz force detuning and beam loading effects. Step operation and vector stimulus operation modes are applied for the evaluation of a FPGA cavity simulator operated by a digital controller. The performance of the cavity hardware model is verified by comparing with a software model of the cavity implemented in the MATLAB system. The numerical aspects are considered for an optimal DSP calculation. Some experimental results are presented for different cavity operational conditions. (orig.)

  20. An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

    Directory of Open Access Journals (Sweden)

    Lai Chiu-Keng

    2016-01-01

    Full Text Available A Field Programmable Gate Array based system is a great hardware platform to support the implementation of hardware controllers such as PID controller and fuzzy controller. It is also programmed as hardware accelerator to speed up the mathematic calculation and greatly enhance the performance as applied to motor drive and motion control. Furthermore, the open structure of FPGA-based system is suitable for those designs with the ability of parallel processing or soft code processor embedded. In this paper, we apply the FPGA to a multi-axis velocity controller design. The developed system integrated three functions inside the FPGA chip, which are respectively the stepping motor drive, the multi-axis motion controller and the motion planning. Furthermore, an embedded controller with a soft code processor compatible to 8051 micro-control unit (MCU is built to handle the data transfer between the FPGA board and host PC. The MCU is also used to initialize the motion control and run the interpolator. The designed system is practically applied to a XYZ motion platform which is driven by stepping motors to verify its performance.

  1. FPGA based Fuzzy Logic Controller for plasma position control in ADITYA Tokamak

    International Nuclear Information System (INIS)

    Suratia, Pooja; Patel, Jigneshkumar; Rajpal, Rachana; Kotia, Sorum; Govindarajan, J.

    2012-01-01

    Highlights: ► Evaluation and comparison of the working performance of FLC is done with that of PID Controller. ► FLC is designed using MATLAB Fuzzy Logic Toolbox, and validated on ADITYA RZIP model. ► FLC was implemented on a FPGA. The close-loop testing is done by interfacing FPGA to MATLAB/Simulink. ► Developed FLC controller is able to maintain the plasma column within required range of ±0.05 m and was found to give robust control against various disturbances and faster and smoother response compared to PID Controller. - Abstract: Tokamaks are the most promising devices for obtaining nuclear fusion energy from high-temperature, ionized gas termed as Plasma. The successful operation of tokamak depends on its ability to confine plasma at the geometric center of vacuum vessel with sufficient stability. The quality of plasma discharge in ADITYA Tokamak is strongly related to the radial position of the plasma column in the vacuum vessel. If the plasma column approaches too near to the wall of vacuum vessel, it leads to minor or complete disruption of plasma. Hence the control of plasma position throughout the entire plasma discharge duration is a fundamental requirement. This paper describes Fuzzy Logic Controller (FLC) which is designed for radial plasma position control. This controller is tested and evaluated on the ADITYA RZIP control model. The performance of this FLC was compared with that of Proportional–Integral–Derivative (PID) Controller and the response was found to be faster and smoother. FLC was implemented on a Field Programmable Gate Array (FPGA) chip with the use of a Very High-Speed Integrated-Circuits Hardware Description-Language (VHDL).

  2. Modeling and control of isolated full bridge boost DC-DC converter implemented in FPGA

    DEFF Research Database (Denmark)

    Taeed, Fazel; Nymand, M.

    2013-01-01

    design are discussed. In the next step a digital PI controller is designed and implemented in a FPGA to control the output voltage. Using the injection transformer method the open loop transfer function in closed loop is measured and modeling results are verified by experimental results....

  3. Using an FPGA for Fast Bit Accurate SoC Simulation

    NARCIS (Netherlands)

    Wolkotte, P.T.; Holzenspies, P.K.F.; Smit, Gerardus Johannes Maria

    In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit

  4. Development of automated controller system for controlling reactivity by using FPGA in research reactor application

    International Nuclear Information System (INIS)

    Mohd Sabri Minhat; Izhar Abu Hussin; Mohd Idris Taib

    2012-01-01

    The scope for this research paper is to produce a detail design for Development of Automated Controller System for Controlling Reactivity by using FPGA in Research Reactor Application for high safety nuclear operation. The development of this project including design, purchasing, fabrication, installation, testing and validation and verification for one prototype automated controller system for controlling reactivity in industry local technology for human capacity and capability development towards the first Nuclear Power Programme (NPP) in Malaysia. The specific objectives of this research paper are to Development of Automated Controller System for Controlling Reactivity (ACSCR) in Research Reactor Application (PUSPATI TRIGA Reactor) by using simultaneous movement method; To design, fabricate and produce the accuracy of Control Rods Drive Mechanism to 0.1 mm resolution using a stepper motor as an actuator; To design, install and produce the system response to be more faster by using Field Programmable Gate Array (FPGA) and High Speed Computer; and to improve the Safety Level of the Research Reactor in high safety nuclear operation condition. (author)

  5. High-Speed Computation using FPGA for Excellent Performance of Direct Torque Control of Induction Machines

    Directory of Open Access Journals (Sweden)

    Tole Sutikno

    2016-03-01

    Full Text Available The major problems in hysteresis-based DTC are high torque ripple and variable switching frequency. In order to minimize the torque ripple, high sampling time and fast digital realization should be applied. The high sampling and fast digital realization time can be achieved by utilizing high-speed processor where the operation of the discrete hysteresis regulator is becoming similar to the operation of analog-based comparator. This can be achieved by utilizing field programmable gate array (FPGA which can perform a sampling at a very high speed, compared to the fact that developing an ASIC chip is expensive and laborious.

  6. Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

    International Nuclear Information System (INIS)

    Magazzù, G; Borgese, G; Costantino, N; Fanucci, L; Saponara, S; Incandela, J

    2013-01-01

    In many research fields as high energy physics (HEP), astrophysics, nuclear medicine or space engineering with harsh operating conditions, the use of fast and flexible digital communication protocols is becoming more and more important. The possibility to have a smart and tested top-down design flow for the design of a new protocol for control/readout of front-end electronics is very useful. To this aim, and to reduce development time, costs and risks, this paper describes an innovative design/verification flow applied as example case study to a new communication protocol called FF-LYNX. After the description of the main FF-LYNX features, the paper presents: the definition of a parametric SystemC-based Integrated Simulation Environment (ISE) for high-level protocol definition and validation; the set up of figure of merits to drive the design space exploration; the use of ISE for early analysis of the achievable performances when adopting the new communication protocol and its interfaces for a new (or upgraded) physics experiment; the design of VHDL IP cores for the TX and RX protocol interfaces; their implementation on a FPGA-based emulator for functional verification and finally the modification of the FPGA-based emulator for testing the ASIC chipset which implements the rad-tolerant protocol interfaces. For every step, significant results will be shown to underline the usefulness of this design and verification approach that can be applied to any new digital protocol development for smart detectors in physics experiments.

  7. Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

    Science.gov (United States)

    Magazzù, G.; Borgese, G.; Costantino, N.; Fanucci, L.; Incandela, J.; Saponara, S.

    2013-02-01

    In many research fields as high energy physics (HEP), astrophysics, nuclear medicine or space engineering with harsh operating conditions, the use of fast and flexible digital communication protocols is becoming more and more important. The possibility to have a smart and tested top-down design flow for the design of a new protocol for control/readout of front-end electronics is very useful. To this aim, and to reduce development time, costs and risks, this paper describes an innovative design/verification flow applied as example case study to a new communication protocol called FF-LYNX. After the description of the main FF-LYNX features, the paper presents: the definition of a parametric SystemC-based Integrated Simulation Environment (ISE) for high-level protocol definition and validation; the set up of figure of merits to drive the design space exploration; the use of ISE for early analysis of the achievable performances when adopting the new communication protocol and its interfaces for a new (or upgraded) physics experiment; the design of VHDL IP cores for the TX and RX protocol interfaces; their implementation on a FPGA-based emulator for functional verification and finally the modification of the FPGA-based emulator for testing the ASIC chipset which implements the rad-tolerant protocol interfaces. For every step, significant results will be shown to underline the usefulness of this design and verification approach that can be applied to any new digital protocol development for smart detectors in physics experiments.

  8. A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

    Science.gov (United States)

    Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

    2014-01-01

    This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. PMID:24379047

  9. FPGA cluster for high-performance AO real-time control system

    Science.gov (United States)

    Geng, Deli; Goodsell, Stephen J.; Basden, Alastair G.; Dipper, Nigel A.; Myers, Richard M.; Saunter, Chris D.

    2006-06-01

    Whilst the high throughput and low latency requirements for the next generation AO real-time control systems have posed a significant challenge to von Neumann architecture processor systems, the Field Programmable Gate Array (FPGA) has emerged as a long term solution with high performance on throughput and excellent predictability on latency. Moreover, FPGA devices have highly capable programmable interfacing, which lead to more highly integrated system. Nevertheless, a single FPGA is still not enough: multiple FPGA devices need to be clustered to perform the required subaperture processing and the reconstruction computation. In an AO real-time control system, the memory bandwidth is often the bottleneck of the system, simply because a vast amount of supporting data, e.g. pixel calibration maps and the reconstruction matrix, need to be accessed within a short period. The cluster, as a general computing architecture, has excellent scalability in processing throughput, memory bandwidth, memory capacity, and communication bandwidth. Problems, such as task distribution, node communication, system verification, are discussed.

  10. A FPGA embedded web server for remote monitoring and control of smart sensors networks.

    Science.gov (United States)

    Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

    2013-12-27

    This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

  11. A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

    Directory of Open Access Journals (Sweden)

    Eduardo Magdaleno

    2013-12-01

    Full Text Available This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI. The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A. Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

  12. Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control

    Directory of Open Access Journals (Sweden)

    E.A. Ramadan

    2014-09-01

    Full Text Available This paper presents an improved adaptive fuzzy logic speed controller for a DC motor, based on field programmable gate array (FPGA hardware implementation. The developed controller includes an adaptive fuzzy logic control (AFLC algorithm, which is designed and verified with a nonlinear model of DC motor. Then, it has been synthesised, functionally verified and implemented using Xilinx Integrated Software Environment (ISE and Spartan-3E FPGA. The performance of this controller has been successfully validated with good tracking results under different operating conditions.

  13. Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

    Directory of Open Access Journals (Sweden)

    Paolo Meloni

    2012-01-01

    Full Text Available Application Specific Instruction-set Processors (ASIPs expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

  14. Synchronic, optical transmission data link integrated with FPGA circuits (for TESLA LLRF control system)

    Energy Technology Data Exchange (ETDEWEB)

    Zielinski, J.S.

    2006-07-15

    The X-ray free-electron laser X-FEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short X-ray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new possibilities for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated to the LLRF1 system in VUV FEL experiment It is being developed by the ELHEP2 group in the Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller to stabilize the vector sum of fields in cavities of one cryo-module in the experiment. The device can be also used as the simulator of the cavity and test bench for other devices. The synchronic, optical link project was made for the accelerator X-FEL laser TESLA, the LLRF control system experiment at DESY, Hamburg. The control and diagnostic data is transmitted up to 2.5Gbit/s through a plastic fiber in a distance up to a few hundred meters. The link is synchronized once after power up, and never resynchronized when data is transmitted with maximum speed. The one way link bit error rate is less then 10{sup -15}. The transceiver component written in VHDL that works in the dedicated Altera registered Stratix registered GX FPGA circuit. During the work in the PERG laboratory a 2,5Gbit/s serial link with the long vector parallel interface transceiver was created. Long-Data-Vector transceiver transmits 16bit vector each 8ns with 120ns latency. (orig.)

  15. Synchronic, optical transmission data link integrated with FPGA circuits (for TESLA LLRF control system)

    International Nuclear Information System (INIS)

    Zielinski, J.S.

    2006-05-01

    The X-ray free-electron laser X-FEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short X-ray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new possibilities for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated to the LLRF1 system in VUV FEL experiment It is being developed by the ELHEP2 group in the Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller to stabilize the vector sum of fields in cavities of one cryo-module in the experiment. The device can be also used as the simulator of the cavity and test bench for other devices. The synchronic, optical link project was made for the accelerator X-FEL laser TESLA, the LLRF control system experiment at DESY, Hamburg. The control and diagnostic data is transmitted up to 2.5Gbit/s through a plastic fiber in a distance up to a few hundred meters. The link is synchronized once after power up, and never resynchronized when data is transmitted with maximum speed. The one way link bit error rate is less then 10 -15 . The transceiver component written in VHDL that works in the dedicated Altera registered Stratix registered GX FPGA circuit. During the work in the PERG laboratory a 2,5Gbit/s serial link with the long vector parallel interface transceiver was created. Long-Data-Vector transceiver transmits 16bit vector each 8ns with 120ns latency. (orig.)

  16. A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

    CERN Document Server

    Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. ...

  17. A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

    CERN Document Server

    Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. T...

  18. A low power flash-FPGA based brain implant micro-system of PID control.

    Science.gov (United States)

    Lijuan Xia; Fattah, Nabeel; Soltan, Ahmed; Jackson, Andrew; Chester, Graeme; Degenaar, Patrick

    2017-07-01

    In this paper, we demonstrate that a low power flash FPGA based micro-system can provide a low power programmable interface for closed-loop brain implant inter- faces. The proposed micro-system receives recording local field potential (LFP) signals from an implanted probe, performs closed-loop control using a first order control system, then converts the signal into an optogenetic control stimulus pattern. Stimulus can be implemented through optoelectronic probes. The long term target is for both fundamental neuroscience applications and for clinical use in treating epilepsy. Utilizing our device, closed-loop processing consumes only 14nJ of power per PID cycle compared to 1.52μJ per cycle for a micro-controller implementation. Compared to an application specific digital integrated circuit, flash FPGA's are inherently programmable.

  19. Migration of a Real-Time Optimal-Control Algorithm: From MATLAB (Trademark) to Field Programmable Gate Array (FPGA)

    National Research Council Canada - National Science Library

    Moon, II, Ron L

    2005-01-01

    ...) development environment into an FPGA-based embedded-platform development board. Research at the Naval Postgraduate School has produced a revolutionary time-optimal spacecraft control algorithm based upon the Legendre Pseudospectral method...

  20. FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

    International Nuclear Information System (INIS)

    Messai, A.; Mellit, A.; Massi Pavan, A.; Guessoum, A.; Mekki, H.

    2011-01-01

    Research highlights: → FL-MPPT controller is implemented on FPGA. → Results obtained with ModelSim show a satisfactory performance. → Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

  1. FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

    Energy Technology Data Exchange (ETDEWEB)

    Messai, A. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mellit, A., E-mail: a.mellit@yahoo.co.u [Department of Electronics, Faculty of Sciences and Technology, Jijel University, Ouled-aissa, P.O. Box 98, Jijel 18000 (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Massi Pavan, A. [Department of Materials and Natural Resources, University of Trieste, Via A. Valerio, 2 - 34127 Trieste (Italy); Guessoum, A. [Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mekki, H. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria)

    2011-07-15

    Research highlights: {yields} FL-MPPT controller is implemented on FPGA. {yields} Results obtained with ModelSim show a satisfactory performance. {yields} Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

  2. FPGA implementation of high-frequency multiple PWM for variable voltage variable frequency controller

    Energy Technology Data Exchange (ETDEWEB)

    Boumaaraf, Abdelâali, E-mail: aboumaaraf@yahoo.fr [Université Abbès Laghrour, Laboratoire des capteurs, Instrumentations et procédés (LCIP), Khenchela (Algeria); University of Farhat Abbas Setif1, Sétif, 19000 (Algeria); Mohamadi, Tayeb [University of Farhat Abbas Setif1, Sétif, 19000 (Algeria); Gourmat, Laïd [Université Abbès Laghrour, Khenchela, 40000 (Algeria)

    2016-07-25

    In this paper, we present the FPGA implementation of the multiple pulse width modulation (MPWM) signal generation with repetition of data segments, applied to the variable frequency variable voltage systems and specially at to the photovoltaic water pumping system, in order to generate a signal command very easily between 10 Hz to 60 Hz with a small frequency and reduce the cost of the control system.

  3. A low-cost, FPGA-based servo controller with lock-in amplifier

    International Nuclear Information System (INIS)

    Yang, G; Barry, J F; Shuman, E S; Steinecker, M H; DeMille, D

    2012-01-01

    We describe the design and implementation of a low-cost, FPGA-based servo controller with an integrated waveform synthesizer and lock-in amplifier. This system has been designed with the specific application of laser frequency locking in mind but should be adaptable to a variety of other purposes as well. The system incorporates an onboard waveform synthesizer, a lock-in amplifier, two channels of proportional-integral (PI) servo control, and a ramp generator on a single FPGA chip. The system is based on an inexpensive, off-the-shelf FPGA evaluation board with a wide variety of available accessories, allowing the system to interface with standard laser controllers and detectors while minimizing the use of custom hardware and electronics. Gains, filter constants, and other relevant parameters are adjustable via onboard knobs and switches. These parameters and other information are displayed to the user via an integrated LCD, allowing full operation of the device without an accompanying computer. We demonstrate the performance of the system in a test setup, in which the frequency of a tunable external-cavity diode laser (ECDL) is locked to a resonant optical transmission peak of a Fabry-Perot cavity. In this setup, we achieve a total servo-loop bandwidth of ∼ 7 kHz and achieve locking of the ECDL to the cavity with a full-width-at-half-maximum (FWHM) linewidth of ∼ 200 kHz.

  4. FPGA and optical-network-based LLRF distributed control system for TESLA-XFEL linear accelerator

    Science.gov (United States)

    Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Czarski, Tomasz; Giergusiewicz, Wojciech; Jalmuzna, Wojciech; Olowski, Krysztof; Perkuszewski, Karol; Zielinski, Jerzy; Simrock, Stefan

    2005-02-01

    The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control system for the TESLA-XFEL accelerator. The design of a system basing on the FPGA chips and multi-gigabit optical network was debated. The system design approach was fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of the, DSP enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. Initial parameters of the system model under the design are presented.

  5. FPGA implementation of bit controller in double-tick architecture

    Science.gov (United States)

    Kobylecki, Michał; Kania, Dariusz

    2017-11-01

    This paper presents a comparison of the two original architectures of programmable bit controllers built on FPGAs. Programmable Logic Controllers (which include, among other things programmable bit controllers) built on FPGAs provide a efficient alternative to the controllers based on microprocessors which are expensive and often too slow. The presented and compared methods allow for the efficient implementation of any bit control algorithm written in Ladder Diagram language into the programmable logic system in accordance with IEC61131-3. In both cases, we have compared the effect of the applied architecture on the performance of executing the same bit control program in relation to its own size.

  6. Force to Rebalance Control of HRG and Suppression of Its Errors on the Basis of FPGA

    Directory of Open Access Journals (Sweden)

    Qingan Jiang

    2011-12-01

    Full Text Available A novel design of force to rebalance control for a hemispherical resonator gyro (HRG based on FPGA is demonstrated in this paper. The proposed design takes advantage of the automatic gain control loop and phase lock loop configuration in the drive mode while making full use of the quadrature control loop and rebalance control loop in controlling the oscillating dynamics in the sense mode. First, the math model of HRG with inhomogeneous damping and frequency split is theoretically analyzed. In addition, the major drift mechanisms in the HRG are described and the methods that can suppress the gyro drift are mentioned. Based on the math model and drift mechanisms suppression method, four control loops are employed to realize the manipulation of the HRG by using a FPGA circuit. The reference-phase loop and amplitude control loop are used to maintain the vibration of primary mode at its natural frequency with constant amplitude. The frequency split is readily eliminated by the quadrature loop with a DC voltage feedback from the quadrature component of the node. The secondary mode response to the angle rate input is nullified by the rebalance control loop. In order to validate the effect of the digital control of HRG, experiments are carried out with a turntable. The experimental results show that the design is suitable for the control of HRG which has good linearity scale factor and bias stability.

  7. Force to rebalance control of HRG and suppression of its errors on the basis of FPGA.

    Science.gov (United States)

    Wang, Xu; Wu, Wenqi; Luo, Bing; Fang, Zhen; Li, Yun; Jiang, Qingan

    2011-01-01

    A novel design of force to rebalance control for a hemispherical resonator gyro (HRG) based on FPGA is demonstrated in this paper. The proposed design takes advantage of the automatic gain control loop and phase lock loop configuration in the drive mode while making full use of the quadrature control loop and rebalance control loop in controlling the oscillating dynamics in the sense mode. First, the math model of HRG with inhomogeneous damping and frequency split is theoretically analyzed. In addition, the major drift mechanisms in the HRG are described and the methods that can suppress the gyro drift are mentioned. Based on the math model and drift mechanisms suppression method, four control loops are employed to realize the manipulation of the HRG by using a FPGA circuit. The reference-phase loop and amplitude control loop are used to maintain the vibration of primary mode at its natural frequency with constant amplitude. The frequency split is readily eliminated by the quadrature loop with a DC voltage feedback from the quadrature component of the node. The secondary mode response to the angle rate input is nullified by the rebalance control loop. In order to validate the effect of the digital control of HRG, experiments are carried out with a turntable. The experimental results show that the design is suitable for the control of HRG which has good linearity scale factor and bias stability.

  8. FPGA-based Upgrade to RITS-6 Control System, Designed with EMP Considerations

    International Nuclear Information System (INIS)

    Anderson, Harold D.; Williams, John T.

    2009-01-01

    The existing control system for the RITS-6, a 20-MA 3-MV pulsed-power accelerator located at Sandia National Laboratories, was built as a system of analog switches because the operators needed to be close enough to the machine to hear pulsed-power breakdowns, yet the electromagnetic pulse (EMP) emitted would disable any processor-based solutions. The resulting system requires operators to activate and deactivate a series of 110-V relays manually in a complex order. The machine is sensitive to both the order of operation and the time taken between steps. A mistake in either case would cause a misfire and possible machine damage. Based on these constraints, a field-programmable gate array (FPGA) was chosen as the core of a proposed upgrade to the control system. An FPGA is a series of logic elements connected during programming. Based on their connections, the elements can mimic primitive logic elements, a process called synthesis. The circuit is static; all paths exist simultaneously and do not depend on a processor. This should make it less sensitive to EMP. By shielding it and using good electromagnetic interference-reduction practices, it should continue to operate well in the electrically noisy environment. The FPGA has two advantages over the existing system. In manual operation mode, the synthesized logic gates keep the operators in sequence. In addition, a clock signal and synthesized countdown circuit provides an automated sequence, with adjustable delays, for quickly executing the time-critical portions of charging and firing. The FPGA is modeled as a set of states, each state being a unique set of values for the output signals. The state is determined by the input signals, and in the automated segment by the value of the synthesized countdown timer, with the default mode placing the system in a safe configuration. Unlike a processor-based system, any system stimulus that results in an abort situation immediately executes a shutdown, with only a tens

  9. Design & Development of FPGA Based VME Bus Controller

    OpenAIRE

    Himali Patel; Poornima Talwai

    2015-01-01

    The VME bus interface Controller (VIC068A) is used to interface Local CPU bus and VME bus. VME Bus Controller is used in wide application areas where high reliability, good accuracy and high speed are desired to withstand industrial environment like nuclear power plant and process industries. VME Bus controller can configure as Master, Slave, Interrupt Handler, arbiter as well as power monitor. Commercial VME Bus interface controller chips are available from a few vend...

  10. Controlling Electronics Boards with PVS

    CERN Multimedia

    2005-01-01

    - Introduction - Control System Architecture - Device Description - FPGA Programming - Register Control - Data Subscription - Examples of Graphics User Interfaces - Parameter - Register Translation - Application on the LHCb Timing Fast Control System

  11. FPGA-based implementation of a cavity field controller for FLASH and X-FEL

    Science.gov (United States)

    Fafara, Przemyslaw; Jalmuzna, Wojciech; Koprek, Waldemar; Pozniak, Krzysztof; Romaniuk, Ryszard; Szewinski, Jaroslaw; Cichalewski, Wojciech

    2007-08-01

    The subject of this paper is the design and construction of a new generation of superconducting cavity accelerator measurement and control system. The old system is based on a single digital signal processor (DSP). The new system uses a large programmable array circuit (FPGA) instead, with a multi-gigabit optical link. Both systems now work in parallel in the Free Electron Laser in Hamburg (FLASH). The differences between the systems are shown, based on the measurement results of the working machine. The major advantage of the new system is a bigger area of stability of the machine control loop.

  12. Efficient Processing of a Rainfall Simulation Watershed on an FPGA-Based Architecture with Fast Access to Neighbourhood Pixels

    Directory of Open Access Journals (Sweden)

    Yeong LeeSeng

    2009-01-01

    Full Text Available This paper describes a hardware architecture to implement the watershed algorithm using rainfall simulation. The speed of the architecture is increased by utilizing a multiple memory bank approach to allow parallel access to the neighbourhood pixel values. In a single read cycle, the architecture is able to obtain all five values of the centre and four neighbours for a 4-connectivity watershed transform. The storage requirement of the multiple bank implementation is the same as a single bank implementation by using a graph-based memory bank addressing scheme. The proposed rainfall watershed architecture consists of two parts. The first part performs the arrowing operation and the second part assigns each pixel to its associated catchment basin. The paper describes the architecture datapath and control logic in detail and concludes with an implementation on a Xilinx Spartan-3 FPGA.

  13. Prototyping of concurrent control systems implemented in FPGA devices

    CERN Document Server

    Wiśniewski, Remigiusz

    2017-01-01

    This book focuses on prototyping aspects of concurrent control systems and their further implementation and partial reconfiguration in programmable devices. Further, it lays out a full prototyping flow for concurrent control systems. Based on a given primary specification, a system is described with an interpreted Petri net, which naturally reflects the concurrent and sequential relationships of the design. The book shows that, apart from the traditional option of static configuration of the entire system, the latest programmable devices (especially FPGAs) offer far more sophistication. Partial reconfiguration allows selected parts of the system to be replaced without having to reprogram the entire structure of the device. Approaches to dynamic and static partial reconfiguration of concurrent control systems are presented and described in detail.< The theoretical work is illustrated by examples drawn from various applications, with a milling machine and a traffic-light controller highlighted as representat...

  14. Integrated optical switch circuit operating under FPGA control

    NARCIS (Netherlands)

    Stabile, R.; Zal, M.; Williams, K.A.; Bienstman, P.; Morthier, G.; Roelkens, G.; et al., xx

    2011-01-01

    Integrated photonic circuits are enabling an abrupt step change in networking systems providing massive bandwidth and record transmission. The increasing complexity of high connectivity photonic integrated switches requires sophisticated control planes and more intimate high speed electronics. Here

  15. An FPGA Implementation of a Robot Control System with an Integrated 3D Vision System

    Directory of Open Access Journals (Sweden)

    Yi-Ting Chen

    2015-05-01

    Full Text Available Robot decision making and motion control are commonly based on visual information in various applications. Position-based visual servo is a technique for vision-based robot control, which operates in the 3D workspace, uses real-time image processing to perform tasks of feature extraction, and returns the pose of the object for positioning control. In order to handle the computational burden at the vision sensor feedback, we design a FPGA-based motion-vision integrated system that employs dedicated hardware circuits for processing vision processing and motion control functions. This research conducts a preliminary study to explore the integration of 3D vision and robot motion control system design based on a single field programmable gate array (FPGA chip. The implemented motion-vision embedded system performs the following functions: filtering, image statistics, binary morphology, binary object analysis, object 3D position calculation, robot inverse kinematics, velocity profile generation, feedback counting, and multiple-axes position feedback control.

  16. FPGA Controller Design and Simulation of a Portable Dough Mixing ...

    African Journals Online (AJOL)

    With the advent of Microcontrollers, Application Specic Integrated Circuits, Digital Signal Processors (DSP) and Programmable Logic Devices, complex industrial systems and controls can now be integrated into portable embedded household electronic systems. In this paper, the design and simulation of a Dough Mixer ...

  17. FPGA implementation of PCI to CAMAC interface for Embedded CAMAC Controller (ECC)

    International Nuclear Information System (INIS)

    Jha, K.; Behere, Anita; Ghodgaonkar, M.D.

    2005-01-01

    CAMAC controllers are used for control systems and nuclear physics experiments. Control applications need more number of physically distributed crates with regular scanning of all the parameters, the control being with a centralized computer. On the other hand, nuclear physics experiments need a high throughput with a large number of parameters in one or more crates. The nature of events is random hence buffering of data in LIST mode acquisition is needed. For a large number of parameters, this translates to high transfer rate. Hence it is essential that the CAMAC readout time is minimized and also the data transfer speed is improved to achieve maximum effective throughput. The ECC is designed to achieve these objectives using an embedded controller with PC architecture having PCI bus as interface for add on logic. The PCI Add-on to CAMAC interface protocol has been implemented in an AL TERA FPGA and all the functionality coded in VHDL. This paper discusses the design aspects of the FPGA implementation of the PCI to CAMAC interface. (author)

  18. Embedded harmonic control for dynamic trajectory planning on FPGA

    OpenAIRE

    Girau , Bernard; Boumaza , Amine

    2007-01-01

    International audience; This paper presents a parallel hardware implementation of a well-known navigation control method on reconfigurable digital circuits. Trajectories are estimated after an iterated computation of the harmonic functions, given the goal and obstacle positions of the navigation problem. The proposed massively distributed implementation locally computes the direction to choose to get to the goal position at any point of the environment. Changes in this environment may be imme...

  19. FPGA-based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    Science.gov (United States)

    Perkuszewski, Karol; Pozniak, Krzysztof T.; Jalmuzna, Wojciech; Koprek, Waldemar; Szewinski, Jaroslaw; Romaniuk, Ryszard S.; Simrock, Stefan

    2006-10-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented.

  20. FPGA based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    International Nuclear Information System (INIS)

    Perkuszewski, K.; Pozniak, K.T.; Jalmuzna, W.; Koprek, W.; Szewinski, J.; Romaniuk, R.S.

    2006-01-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented. (orig.)

  1. FPGA based multichannel optical concentrator SIMCON 4.0 for TESLA cavities LLRF control system

    Energy Technology Data Exchange (ETDEWEB)

    Perkuszewski, K.; Pozniak, K.T.; Jalmuzna, W.; Koprek, W.; Szewinski, J.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems; Simrock, S. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany)

    2006-07-01

    The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented. (orig.)

  2. A FPGA-based Fast Converging Digital Adaptive Filter for Real-time RFI Mitigation on Ground Based Radio Telescopes

    Science.gov (United States)

    Finger, R.; Curotto, F.; Fuentes, R.; Duan, R.; Bronfman, L.; Li, D.

    2018-02-01

    Radio Frequency Interference (RFI) is a growing concern in the radio astronomy community. Single-dish telescopes are particularly susceptible to RFI. Several methods have been developed to cope with RF-polluted environments, based on flagging, excision, and real-time blanking, among others. All these methods produce some degree of data loss or require assumptions to be made on the astronomical signal. We report the development of a real-time, digital adaptive filter implemented on a Field Programmable Gate Array (FPGA) capable of processing 4096 spectral channels in a 1 GHz of instantaneous bandwidth. The filter is able to cancel a broad range of interference signals and quickly adapt to changes on the RFI source, minimizing the data loss without any assumption on the astronomical or interfering signal properties. The speed of convergence (for a decrease to a 1%) was measured to be 208.1 μs for a broadband noise-like RFI signal and 125.5 μs for a multiple-carrier RFI signal recorded at the FAST radio telescope.

  3. Control de un péndulo invertido mediante FPGA

    OpenAIRE

    Mate Castro, Óscar

    2017-01-01

    El presente Trabajo Fin de Grado (TFG) aborda el diseño y construcción de un péndulo invertido lineal sobre carro guiado, así como el desarrollo del sistema de control correspondiente basado en hardware (HW). Este proyecto surge en un contexto de gran desarrollo de los sistemas basados en HW como respuesta a la demanda de plataformas más rápidas y robustas a la vez que más económicas, características cada vez más difíciles de satisfacer con sistemas basados en software (SW) debido al impe...

  4. FPGA implementation of a ZigBee wireless network control interface to transmit biomedical signals

    Science.gov (United States)

    Gómez López, M. A.; Goy, C. B.; Bolognini, P. C.; Herrera, M. C.

    2011-12-01

    In recent years, cardiac hemodynamic monitors have incorporated new technologies based on wireless sensor networks which can implement different types of communication protocols. More precisely, a digital conductance catheter system recently developed adds a wireless ZigBee module (IEEE 802.15.4 standards) to transmit cardiac signals (ECG, intraventricular pressure and volume) which would allow the physicians to evaluate the patient's cardiac status in a noninvasively way. The aim of this paper is to describe a control interface, implemented in a FPGA device, to manage a ZigBee wireless network. ZigBee technology is used due to its excellent performance including simplicity, low-power consumption, short-range transmission and low cost. FPGA internal memory stores 8-bit signals with which the control interface prepares the information packets. These data were send to the ZigBee END DEVICE module that receives and transmits wirelessly to the external COORDINATOR module. Using an USB port, the COORDINATOR sends the signals to a personal computer for displaying. Each functional block of control interface was assessed by means of temporal diagrams. Three biological signals, organized in packets and converted to RS232 serial protocol, were sucessfully transmitted and displayed in a PC screen. For this purpose, a custom-made graphical software was designed using LabView.

  5. FPGA implementation of a ZigBee wireless network control interface to transmit biomedical signals

    International Nuclear Information System (INIS)

    López, M A Gómez; Goy, C B; Bolognini, P C; Herrera, M C

    2011-01-01

    In recent years, cardiac hemodynamic monitors have incorporated new technologies based on wireless sensor networks which can implement different types of communication protocols. More precisely, a digital conductance catheter system recently developed adds a wireless ZigBee module (IEEE 802.15.4 standards) to transmit cardiac signals (ECG, intraventricular pressure and volume) which would allow the physicians to evaluate the patient's cardiac status in a noninvasively way. The aim of this paper is to describe a control interface, implemented in a FPGA device, to manage a ZigBee wireless network. ZigBee technology is used due to its excellent performance including simplicity, low-power consumption, short-range transmission and low cost. FPGA internal memory stores 8-bit signals with which the control interface prepares the information packets. These data were send to the ZigBee END DEVICE module that receives and transmits wirelessly to the external COORDINATOR module. Using an USB port, the COORDINATOR sends the signals to a personal computer for displaying. Each functional block of control interface was assessed by means of temporal diagrams. Three biological signals, organized in packets and converted to RS232 serial protocol, were successfully transmitted and displayed in a PC screen. For this purpose, a custom-made graphical software was designed using LabView.

  6. Bridging FPGA and GPU technologies for AO real-time control

    Science.gov (United States)

    Perret, Denis; Lainé, Maxime; Bernard, Julien; Gratadour, Damien; Sevin, Arnaud

    2016-07-01

    Our team has developed a common environment for high performance simulations and real-time control of AO systems based on the use of Graphics Processors Units in the context of the COMPASS project. Such a solution, based on the ability of the real time core in the simulation to provide adequate computing performance, limits the cost of developing AO RTC systems and makes them more scalable. A code developed and validated in the context of the simulation may be injected directly into the system and tested on sky. Furthermore, the use of relatively low cost components also offers significant advantages for the system hardware platform. However, the use of GPUs in an AO loop comes with drawbacks: the traditional way of offloading computation from CPU to GPUs - involving multiple copies and unacceptable overhead in kernel launching - is not well suited in a real time context. This last application requires the implementation of a solution enabling direct memory access (DMA) to the GPU memory from a third party device, bypassing the operating system. This allows this device to communicate directly with the real-time core of the simulation feeding it with the WFS camera pixel stream. We show that DMA between a custom FPGA-based frame-grabber and a computation unit (GPU, FPGA, or Coprocessor such as Xeon-phi) across PCIe allows us to get latencies compatible with what will be needed on ELTs. As a fine-grained synchronization mechanism is not yet made available by GPU vendors, we propose the use of memory polling to avoid interrupts handling and involvement of a CPU. Network and Vision protocols are handled by the FPGA-based Network Interface Card (NIC). We present the results we obtained on a complete AO loop using camera and deformable mirror simulators.

  7. High-frequency, three-phase current controller implementation in an FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Hartmann, M.; Round, S. D.; Kolar, J. W.

    2008-07-01

    Three phase rectifiers with switching frequencies of 500 kHz or more require high speed current controllers. At such high switching frequencies analog controllers as well as high speed digital signal processing (DSP) systems have limited performance. In this paper, two high speed current controller implementations using two different field-programmable gate arrays (FPGA) - one for switching frequencies up to 1 MHz and one for switching frequencies beyond 1 MHz - are presented to overcome this performance limitation. Starting with the digital system design all the blocks of the signal chain, containing analog-to-digital (A/D) interface, digital controller implementation using HW-multipliers and implementation of a novel high speed, high resolution pulse width modulation (PWM) are discussed and compared. Final measurements verify the performance of the controllers. (author)

  8. DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation

    Directory of Open Access Journals (Sweden)

    Gustavo Sanchez

    2012-01-01

    Full Text Available This paper presents a new fast motion estimation (ME algorithm targeting high resolution digital videos and its efficient hardware architecture design. The new Dynamic Multipoint Diamond Search (DMPDS algorithm is a fast algorithm which increases the ME quality when compared with other fast ME algorithms. The DMPDS achieves a better digital video quality reducing the occurrence of local minima falls, especially in high definition videos. The quality results show that the DMPDS is able to reach an average PSNR gain of 1.85 dB when compared with the well-known Diamond Search (DS algorithm. When compared to the optimum results generated by the Full Search (FS algorithm the DMPDS shows a lose of only 1.03 dB in the PSNR. On the other hand, the DMPDS reached a complexity reduction higher than 45 times when compared to FS. The quality gains related to DS caused an expected increase in the DMPDS complexity which uses 6.4-times more calculations than DS. The DMPDS architecture was designed focused on high performance and low cost, targeting to process Quad Full High Definition (QFHD videos in real time (30 frames per second. The architecture was described in VHDL and synthesized to Altera Stratix 4 and Xilinx Virtex 5 FPGAs. The synthesis results show that the architecture is able to achieve processing rates higher than 53 QFHD fps, reaching the real-time requirements. The DMPDS architecture achieved the highest processing rate when compared to related works in the literature. This high processing rate was obtained designing an architecture with a high operation frequency and low numbers of cycles necessary to process each block.

  9. Implementation and Performance of FPGA based track fitting for the Atlas Fast TracKer

    CERN Document Server

    Zou, Rui; The ATLAS collaboration

    2018-01-01

    The Fast TracKer (FTK) within the ATLAS trigger system provides global track reconstruction for all events passing the ATLAS Level 1 trigger by dividing the detector into parallel processing pipelines that implement pattern matching in custom integrated circuits and data routing, reduction, and parameter extraction in FPGAs. In this presentation we will describe the implementation of a critical component of the system which does partial track fitting using a method based on a principal component analysis at a rate of greater than 1 fit per 10 ps, system-wide, to reduce the output of the pattern matching. Firmware design, timing performance and preliminary results will be discussed.

  10. A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems

    DEFF Research Database (Denmark)

    Pezzarossa, Luca; Schoeberl, Martin; Sparsø, Jens

    2017-01-01

    -source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes......In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading....... The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example...

  11. FPGA implementation of optimal and approximate model predictive control for a buck-boost DC-DC converter

    NARCIS (Netherlands)

    Spinu, V.; Oliveri, A.; Lazar, M.; Storace, M.

    2012-01-01

    This paper proposes a method for FPGA implementation of explicit, piecewise af¿ne (PWA) model predictive control (MPC) laws for non-inverting buck-boost DC-DC converters. A novel approach to obtain a PWA model of the power converter is proposed and two explicit MPC laws are derived, i.e., one based

  12. A Study of BUS Architecture Design for Controller of Nuclear Power Plant Using FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Yun, Donghwa; Hwang, Sungjae; Kim, Myeongyun; Lee, Dongyun [PONUTech Co. Ltd., Seoul (Korea, Republic of)

    2014-05-15

    CPU (Central Processing Unit) operating speed and communication rate have been more technically improved than before. However, whole system is been a degradation of performance by electronic and structural limitation of parallel bus. Transmission quantity and speed have a limit and need arbiter in order to do arbitration because several boards shared parallel bus. Arbiter is a high complexity in implementing so it increases component per chip. If a parallel bus uses, it will occurs some problems what are reflection noise, power/ground noise (or ground bounce) as SSN (Simultaneous Switching Noise) and crosstalk noise like magnetic coupling. In this paper, in order to solve a problem of parallel bus in controller of NPP (Nuclear Power Plant), proposes the bus architecture design using FPGA (Field Programmable Gate Array) based on LVDS (Low Voltage Differential Signaling)

  13. A Study of BUS Architecture Design for Controller of Nuclear Power Plant Using FPGA

    International Nuclear Information System (INIS)

    Lee, Dongil; Yun, Donghwa; Hwang, Sungjae; Kim, Myeongyun; Lee, Dongyun

    2014-01-01

    CPU (Central Processing Unit) operating speed and communication rate have been more technically improved than before. However, whole system is been a degradation of performance by electronic and structural limitation of parallel bus. Transmission quantity and speed have a limit and need arbiter in order to do arbitration because several boards shared parallel bus. Arbiter is a high complexity in implementing so it increases component per chip. If a parallel bus uses, it will occurs some problems what are reflection noise, power/ground noise (or ground bounce) as SSN (Simultaneous Switching Noise) and crosstalk noise like magnetic coupling. In this paper, in order to solve a problem of parallel bus in controller of NPP (Nuclear Power Plant), proposes the bus architecture design using FPGA (Field Programmable Gate Array) based on LVDS (Low Voltage Differential Signaling)

  14. Modular version of SIMCON, FPGA based, DSP integrated, LLRF control system for TESLA FEL part II: measurement of SIMCON 3.0 DSP daughterboard

    Science.gov (United States)

    Giergusiewicz, Wojciech; Koprek, Waldemar; Jalmuzna, Wojciech; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.

    2006-02-01

    The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the W-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layer, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACCl module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0. encouraged us to enter the design of SIMCON 3.1. possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0. is a modular solution, while SIMCON 3.1. will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one - after branching off in this version of the Simcon, will be continued.

  15. Design and realization of the real-time spectrograph controller for LAMOST based on FPGA

    Science.gov (United States)

    Wang, Jianing; Wu, Liyan; Zeng, Yizhong; Dai, Songxin; Hu, Zhongwen; Zhu, Yongtian; Wang, Lei; Wu, Zhen; Chen, Yi

    2008-08-01

    A large Schmitt reflector telescope, Large Sky Area Multi-Object Fiber Spectroscopic Telescope(LAMOST), is being built in China, which has effective aperture of 4 meters and can observe the spectra of as many as 4000 objects simultaneously. To fit such a large amount of observational objects, the dispersion part is composed of a set of 16 multipurpose fiber-fed double-beam Schmidt spectrographs, of which each has about ten of moveable components realtimely accommodated and manipulated by a controller. An industrial Ethernet network connects those 16 spectrograph controllers. The light from stars is fed to the entrance slits of the spectrographs with optical fibers. In this paper, we mainly introduce the design and realization of our real-time controller for the spectrograph, our design using the technique of System On Programmable Chip (SOPC) based on Field Programmable Gate Array (FPGA) and then realizing the control of the spectrographs through NIOSII Soft Core Embedded Processor. We seal the stepper motor controller as intellectual property (IP) cores and reuse it, greatly simplifying the design process and then shortening the development time. Under the embedded operating system μC/OS-II, a multi-tasks control program has been well written to realize the real-time control of the moveable parts of the spectrographs. At present, a number of such controllers have been applied in the spectrograph of LAMOST.

  16. Design of FPGA Based Neural Network Controller for Earth Station Power System

    Directory of Open Access Journals (Sweden)

    Hassen T. Dorrah

    2012-06-01

    Full Text Available Automation of generating hardware description language code from neural networks models can highly decrease time of implementation those networks into a digital devices, thus significant money savings. To implement the neural network into hardware designer, it is required to translate generated model into device structure. VHDL language is used to describe those networks into hardware. VHDL code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic of the earth station and the satellite power systems using ModelSim PE 6.6 simulator tool. Integration between MATLAB and VHDL is used to save execution time of computation. The results shows that a good agreement between MATLAB and VHDL and a fast/flexible feed forward NN which is capable of dealing with floating point arithmetic operations; minimum number of CLB slices; and good speed of performance. FPGA synthesis results are obtained with view RTL schematic and technology schematic from Xilinix tool. Minimum number of utilized resources is obtained by using Xilinix VERTIX5.

  17. FPGA design

    CERN Document Server

    Simpson, Philip

    2010-01-01

    This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

  18. FPGA based control system for -100 kV, 25 A Crowbarless DC power supply

    International Nuclear Information System (INIS)

    Upadhyay, R.; Tripathi, A.; Badapanda, M.K.; Lad, M.

    2015-01-01

    FPGA based digital control system has been developed for -100 kV, 25 A solid state modular crowbarless DC klystron bias power supply of 1 MW, 352.2 MHz RF test stand. The control system has capability to operate this power supply either in CW or pulse mode. Central controller, PSM controller and graphical user interface are key parts of this control system. Central controller monitors the status of various subsystems of this power supply like 11 kV step start unit, four numbers of main transformers each having 44 numbers of secondary windings and 176 numbers of switch power modules for deciding the number of power modules to be put ON and their duty cycles depending on the set output voltage and current. PSM controller sends appropriate control signal to the switch power modules through fibre optic lines and communicates it to the central controller. Linux based graphical user interface has been developed which enables the user to set the operating parameters along with their trip limits and displays the information of critical parameters of this power supply on a local touch screen panel. Provision for remote control and supervision is also provided through a separate PC connected to the main control system via Ethernet. The control system has capability to trip the power supply within 5 μsec in case any parameter exceeds its set limit. Suitable data logging feature is incorporated for offline fault analysis. The control system architecture along with its software protection interlocks are presented in this paper. The performance of the control system has been verified during operation of -100 kV, 25 A DC power supply with 1 MW, 352.2 MHz klystron amplifier. (author)

  19. An intelligent vehicular traffic signal control system with state flow chart design and fpga prototyping

    International Nuclear Information System (INIS)

    Solangi, U.S.; Memon, T.D.; Noonari, A.S.; Ansari, O.A.

    2017-01-01

    The problem of vehicular traffic congestion is a persistent constraint in the socio-economic development of Pakistan. This paper presents design and implementation of an intelligent traffic controller based on FPGA (Field Programmable Gate Array) to provide an efficient traffic management by optimizing functioning of traffic lights which will result in minimizing traffic congestion at intersections. The existent Traffic Signal system in Pakistan is fixed-time based and offers only Open Loop method for Traffic Control. The Intelligent Traffic Controller presented here uses feedback sensors to read the Traffic density present at a four way intersection to provide an efficient alternative for better supervisory Control of Traffic flow. The traffic density based control logic has been developed in a State Flow Chart for improved visualization of State Machine based operation, and implemented as a Subsystem in Simulink and transferred into VHDL (Hardware Description Language) code using HDL Coder for reducing development time and time to market, which are essential to capitalize Embedded Systems Market. The VHDL code is synthesized with Altera QUARTUS, simulated timing waveform is obtained to verify correctness of the algorithm for different Traffic Scenarios. For implementation purpose estimations were obtained for Cyclone-III and Stratix-III. (author)

  20. An Intelligent Vehicular Traffic Signal Control System with State Flow Chart Design and FPGA Prototyping

    Directory of Open Access Journals (Sweden)

    UMAIR SAEEDSOLANGI

    2017-04-01

    Full Text Available The problem of vehicular traffic congestion is a persistent constraint in the socio-economic development of Pakistan. This paper presents design and implementation of an intelligent traffic controller based on FPGA (Field Programmable Gate Array to provide an efficient traffic management by optimizing functioning of traffic lights which will result in minimizing traffic congestion at intersections. The existent Traffic Signal system in Pakistan is fixed-time based and offers only Open Loop method for Traffic Control. The Intelligent Traffic Controller presented here uses feedback sensors to read the Traffic density present at a four way intersection to provide an efficient alternative for better supervisory Control of Traffic flow. The traffic density based control logic has been developed in a State Flow Chart for improved visualization of State Machine based operation, and implemented as a Subsystem in Simulink and transferred into VHDL (Hardware Description Language code using HDL Coder for reducing development time and time to market, which are essential to capitalize Embedded Systems Market. The VHDL code is synthesized with Altera QUARTUS, simulated timing waveform is obtained to verify correctness of the algorithm for different Traffic Scenarios. For implementation purpose estimations were obtained for Cyclone-III and Stratix-III.

  1. SUMAC: A monitor and control tree for multi-FPGA systems

    International Nuclear Information System (INIS)

    Gao, Mingshen

    1999-01-01

    The BTeV pixel trigger is a data acquisition system capable of finding tracks and vertices in real time in the BTeV pixel detector array. The trigger uses some 3000 processing elements (DSPs) arranged in three processing levels to handle a raw data rate of nearly 100 Gigabytes per second and bring the trigger rate down to 10 KHz. The trigger system has more than 6000 programmable elements, including Field Programmable Logic Arrays (FPGAs), microprocessors (DSPs, interface to the monitor and control tree through FPGAs), and others. Sumac (Serial Utility Monitor and Control tree) is used for configuring and monitoring of these devices. Its primary function is the downloading of FPGA bit streams, microprocessor programs, chip configurations, and test data. In addition, remote cpus and other devices can send messages and status back to the host. The Sumac system is capable of handling several thousand remote devices from a single host PC. Because it stores configuration data in local flash eeproms, it will be capable of achieving a complete system reboot in less than 1 second. The Sumac system is a tree hierarchy connected via high-speed serial links. Typically each board in the system will have a control node which accepts a single upstream serial link and fans out to as many as 32 downstream links. The downstream links can connect to FPGAs or to other control nodes for further fanout

  2. FPGA development board for applications in cosmic rays physics

    International Nuclear Information System (INIS)

    Angelov, Ivo; Damov, Krasimir; Dimitrova, Svetla

    2013-01-01

    The modern experiments in cosmic rays and particle physics are usually performed with large number of detectors and signal processing have to be done by complex electronics. The analog signals from the detectors are converted to digital (by discriminators or fast ADC) and connected to different type of logic implemented in FPGA (Field Programmable Gate Arrays). A FPGA development board based on Xilinx XC3S50AN was designed, assembled and tested. The board will be used for developing a modern registering controller (to replace the existing now) for the muon telescope in the University and can be used for other experiments in cosmic rays physics when fast digital pulses have to be processed. Keywords: FPGA, Spartan3A, muon telescope, cosmic rays variations

  3. Verification of BGA type FPGA logic applied to a control equipment with Safety Class using the special socket

    International Nuclear Information System (INIS)

    Chung, YounHu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa

    2015-01-01

    This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. This device converts to the different module from the input signals for both digital and analogue of the equipment in the field and outputs their data. In addition, it should perform the logical controls such as backplane communication control and data communication. We suggest acquiring method of the data signal with efficient logic using the socket in this article. Proposed test socket is made by simpler process than former one, and the process is done in batches by which cost can be reduces, and the test socket can be quickly produced in response to any request. Also, it is possible to reduce the wear by reducing the contact force of the ball phenomenon. The structure on the basis of silicon can be reduced the modification, and it has excellent linearity. At the logic verification, the operation that state data block is designed in the FPGA could be easily confirmed by using a socket

  4. Central FPGA-based Destination and Load Control in the LHCb MHz Event Readout

    CERN Document Server

    Jacobsson, Richard

    2012-01-01

    The readout strategy of the LHCb experiment [1] is based on complete event readout at 1 MHz [2]. Over 300 sub-detector readout boards transmit event fragments at 1 MHz over a commercial 70 Gigabyte/s switching network to a distributed event building and trigger processing farm with 1470 individual multi-core computer nodes [3]. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a powerful non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. A high-speed FPGA-based central master module controls the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load balancing and trigger rate regulation as a function of the global farm load. It also ...

  5. Implementation of FPGA-Based Charge Control for a Self-Sufficient Solar Tracking Power Supply System

    Directory of Open Access Journals (Sweden)

    Jui-Ho Chen

    2016-02-01

    Full Text Available This study used a field-programmable gate array (FPGA with a Xilinx Spartan-3 FPGA to implement Reflex charge control in a dual-axis solar tracking system with maximum power point tracking (MPPT. The chaos embedded particle swarm optimization method was used to search for the optimum gain constants of the PI controller and the Reflex charging frequency. This scheme not only increases the output power of solar panels but also has a significant effect on switching loss and oscillation of solar charging. The experiment results showed that the proposed method can also significantly improve temperature rise, and that charging efficiency is also better than it is in a traditional charge mode. The results also showed that charging power was enough for solar tracking and the requirements of the charging system. The most significant contribution of this paper is that the scheme can be applied to any active solar tracking and charging system.

  6. Radiation tolerance studies using fault injection on the Readout Control FPGA design of the ALICE TPC detector

    Science.gov (United States)

    Alme, J.; Fehlker, D.; Lippmann, C.; Mager, M.; Rehman, A. U.; Røed, K.; Röhrich, D.; Ullaland, K.

    2013-01-01

    Single Event Upsets (SEUs) are a major concern for the TPC Readout Control Unit (RCU) of the ALICE experiment. A SEU is defined as a radiation related bit-flip in a memory cell, and a SEU in the onboard SRAM based FPGA of the RCU may lead to corrupted data or, even worse, a system malfunction. The latter situation will affect the operation of the ALICE detector since it causes a premature end of data taking. Active partial reconfiguration is utilized in a dedicated reconfiguration solution on the RCU, and this makes it possible to implement fault injection. Fault injection means inserting bit flips in the configuration memory of the FPGA in a controlled laboratory environment. This paper presents the results of the fault injection study and shows how this result can be combined with SEU measurements to estimate the functional failure rate as a function of luminosity.

  7. Flexible experimental FPGA based platform

    DEFF Research Database (Denmark)

    Andersen, Karsten Holm; Nymand, Morten

    2016-01-01

    This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

  8. FPGA implementation of a configurable neuromorphic CPG-based locomotion controller.

    Science.gov (United States)

    Barron-Zambrano, Jose Hugo; Torres-Huitzil, Cesar

    2013-09-01

    Neuromorphic engineering is a discipline devoted to the design and development of computational hardware that mimics the characteristics and capabilities of neuro-biological systems. In recent years, neuromorphic hardware systems have been implemented using a hybrid approach incorporating digital hardware so as to provide flexibility and scalability at the cost of power efficiency and some biological realism. This paper proposes an FPGA-based neuromorphic-like embedded system on a chip to generate locomotion patterns of periodic rhythmic movements inspired by Central Pattern Generators (CPGs). The proposed implementation follows a top-down approach where modularity and hierarchy are two desirable features. The locomotion controller is based on CPG models to produce rhythmic locomotion patterns or gaits for legged robots such as quadrupeds and hexapods. The architecture is configurable and scalable for robots with either different morphologies or different degrees of freedom (DOFs). Experiments performed on a real robot are presented and discussed. The obtained results demonstrate that the CPG-based controller provides the necessary flexibility to generate different rhythmic patterns at run-time suitable for adaptable locomotion. Copyright © 2013 Elsevier Ltd. All rights reserved.

  9. A High Performance Multi-Core FPGA Implementation for 2D Pixel Clustering for the ATLAS Fast TracKer (FTK) Processor

    CERN Document Server

    Sotiropoulou, C-L; The ATLAS collaboration; Beretta, M; Gkaitatzis, S; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

    2014-01-01

    The high performance multi-core 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors read out drivers (RODs) at 760Gbps, the full rate of level 1 triggers. Clustering is required as a method to reduce the high rate of the received data before further processing, as well as to determine the cluster centroid for obtaining obtain the best spatial measurement. Our implementation targets the pixel detectors and uses a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The design is fully generic and the cluster detection window size can be adjusted for optimizing the cluster identification process. Τhe implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility mak...

  10. DOOCS based control system for FPGA based cavity simulator and controller in VUV FEL

    International Nuclear Information System (INIS)

    Pucyk, P.

    2005-09-01

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short X-ray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF 1 system in VUV FEL experiment It is being developed by ELHEP 2 group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryo module in the experiment. The device can be also used as the simulator of the cavity and test bench for other devices. Ths paper describes the concept, implementation and tests of the DOOCS based control system for SIMCON. The designed system is based the concept of autonomic and extendable modules connected by well defined, unified interfaces. The communication module controls the access to the hardware. It is crucial, that all modules (this presented in thesis and developed in the future) use this interface. Direct access to the control tables let the engineers to perform algorithm development or diagnostic measurements of the LLRF system. Default control tables generator makes the whole SIMCON an autonomic device, which can start immediately the operation without any additional tools. (orig.)

  11. DOOCS based control system for FPGA based cavity simulator and controller in VUV FEL

    International Nuclear Information System (INIS)

    Pucyk, P.D.

    2006-03-01

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short X-ray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF 1 system in VUV FEL experiment It is being developed by ELHEP 2 group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryo module in the experiment. The device can be also used as the simulator of the cavity and test bench for other devices. This paper describes the concept, implementation and tests of the DOOCS based control system for SIMCON. The designed system is based the concept of autonomic and extendable modules connected by well defined, unified interfaces. The communication module controls the access to the hardware. It is crucial, that all modules (this presented in thesis and developed in the future) use this interface. Direct access to the control tables let the engineers to perform algorithm development or diagnostic measurements of the LLRF system. Default control tables generator makes the whole SIMCON an autonomic device, which can start immediately the operation without any additional tools. (Orig.)

  12. FPGA communications based on Gigabit Ethernet

    International Nuclear Information System (INIS)

    Doolittle, L.R.; Serrano, C.

    2012-01-01

    The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

  13. Design of a dedicated processor for AC motor control implemented in a low cost FPGA

    DEFF Research Database (Denmark)

    Jakobsen, Uffe; Matzen, Torben N.

    2008-01-01

    of drives. Furthermore the softcore processor is designed with a system for plug in of external logic. Doing so shortens development time, since functionality is simply added to or removed from the softcore. The designer can then choose between resource usage on the FPGA and execution speed in more degrees....... The approach is tested for two different motor types, synchronousand hybrid switched reluctance motors, using a Spartan 3E FPGA. The impact of having ADC-communication in VHDL versus in assembler is also presented....

  14. The FPGA Pixel Array Detector

    International Nuclear Information System (INIS)

    Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

    2013-01-01

    A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

  15. Evaluation and application of a fast module in a PLC based interlock and control system

    International Nuclear Information System (INIS)

    Zaera-Sanz, M

    2009-01-01

    The LHC Beam Interlock system requires a controller performing a simple matrix function to collect the different beam dump requests. To satisfy the expected safety level of the Interlock, the system should be robust and reliable. The PLC is a promising candidate to fulfil both aspects but too slow to meet the expected response time which is of the order of μseconds. Siemens has introduced a 'so called' fast module (FM352-5 Boolean Processor). It provides independent and extremely fast control of a process within a larger control system using an onboard processor, a Field Programmable Gate Array (FPGA), to execute code in parallel which results in extremely fast scan times. It is interesting to investigate its features and to evaluate it as a possible candidate for the beam interlock system. This paper publishes the results of this study. As well, this paper could be useful for other applications requiring fast processing using a PLC.

  16. FPGA Based Efficient Design of Traffic Light Controller using Frequency Scaling for Family of HSTL

    DEFF Research Database (Denmark)

    Sharma, Shivani; Khan, Sadiq; Das, Bhagwan

    2016-01-01

    utilizes least amount of power and is well tested in hardware using Xilinx Virtex6 Field Programmable gate array. FPGA designs are not only cheaper than ASIC designs but have many positive features like speed and performance. So the factors that contribute to power consumption for family of HSTL...

  17. Performance Analysis of Video PHY Controller Using Unidirection and Bi-directional IO Standard via 7 Series FPGA

    DEFF Research Database (Denmark)

    Das, Bhagwan; Abdullah, M F L; Hussain, Dil muhammed Akbar

    2017-01-01

    graphics consumes more power, this creates a need of designing the low power design for Video PHY controller. In this paper, the performance of Video PHY controller is analyzed by comparing the power consumption of unidirectional and bi-directional IO Standard over 7 series FPGA. It is determined...... that total on-chip power is reduced for unidirectional IO Standard based Video PHY controller compared to bidirectional IO Standard based Video PHY controller. The most significant achievement of this work is that it is concluded that unidirectional IO Standard based Video PHY controller consume least...... standby power compared to bidirectional IO Standard based Video PHY controller. It is defined that for 6 GHz operated frequency Video PHY controller, the 32% total on-chip power is reduced using unidirectional IO Standard based Video PHY controller is less compared to bidirectional IO Standard based Video...

  18. Hazard Analysis of Software Requirements Specification for Process Module of FPGA-based Controllers in NPP

    Energy Technology Data Exchange (ETDEWEB)

    Jung; Sejin; Kim, Eui-Sub; Yoo, Junbeom [Konkuk University, Seoul (Korea, Republic of); Keum, Jong Yong; Lee, Jang-Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2016-10-15

    Software in PLC, FPGA which are used to develop I and C system also should be analyzed to hazards and risks before used. NUREG/CR-6430 proposes the method for performing software hazard analysis. It suggests analysis technique for software affected hazards and it reveals that software hazard analysis should be performed with the aspects of software life cycle such as requirements analysis, design, detailed design, implements. It also provides the guide phrases for applying software hazard analysis. HAZOP (Hazard and operability analysis) is one of the analysis technique which is introduced in NUREG/CR-6430 and it is useful technique to use guide phrases. HAZOP is sometimes used to analyze the safety of software. Analysis method of NUREG/CR-6430 had been used in Korea nuclear power plant software for PLC development. Appropriate guide phrases and analysis process are selected to apply efficiently and NUREG/CR-6430 provides applicable methods for software hazard analysis is identified in these researches. We perform software hazard analysis of FPGA software requirements specification with two approaches which are NUREG/CR-6430 and HAZOP with using general GW. We also perform the comparative analysis with them. NUREG/CR-6430 approach has several pros and cons comparing with the HAZOP with general guide words and approach. It is enough applicable to analyze the software requirements specification of FPGA.

  19. Verification of FPGA-Signal using the test board which is applied to Safety-related controller

    Energy Technology Data Exchange (ETDEWEB)

    Chung, Youn-Hu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa [SOOSAN ENS, Seoul (Korea, Republic of)

    2016-10-15

    This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. Saftety-related PLC must meet the international standard specifications. With this reason, we use V and V according to an international standard in order to secure high reliability and safety. By using this, we are supposed to proceed to a variety of verification courses for extra reliability and safety analysis. In order to have efficient verification of test results, we propose the test using the newly changed BGA socket which can resolve the problems of the conventional socket on this paper. The Verification of processes is divided into verification of Hardware and firmware. That processes are carried out in the unit testing and integration testing. The proposed test method is simple, the effect of cost reductions by batch process. In addition, it is advantageous to measure the signal from the Hi-speed-IC due to its short length of the pins and it was plated with the copper around it. Further, it also to prevent abrasion on the IC ball because it has no direct contact with the PCB. Therefore, it can be actually applied is to the BGA package test and we can easily verify logic as well as easily checking the operation of the designed data.

  20. Use of FPGA embedded processors for fast cluster reconstruction in the NA62 liquid krypton electromagnetic calorimeter

    Science.gov (United States)

    Badoni, D.; Bizzarri, M.; Bonaiuto, V.; Checcucci, B.; De Simone, N.; Federici, L.; Fucci, A.; Paoluzzi, G.; Papi, A.; Piccini, M.; Salamon, A.; Salina, G.; Santovetti, E.; Sargeni, F.; Venditti, S.

    2014-01-01

    The goal of the NA62 experiment at the CERN SPS is the measurement of the Branching Ratio of the very rare kaon decay K+→π+ ν bar nu with a 10% accuracy by collecting 100 events in two years of data taking. An efficient photon veto system is needed to reject the K+→π+ π0 background and a liquid krypton electromagnetic calorimeter will be used for this purpose in the 1-10 mrad angular region. The L0 trigger system for the calorimeter consists of a peak reconstruction algorithm implemented on FPGA by using a mixed parallel architecture based on soft core Altera NIOS II embedded processors together with custom VHDL modules. This solution allows an efficient and flexible reconstruction of the energy-deposition peak. The system will be totally composed of 36 TEL62 boards, 108 mezzanine cards and 215 high-performance FPGAs. We describe the design, current status and the results of the first performance tests.

  1. Use of FPGA embedded processors for fast cluster reconstruction in the NA62 liquid krypton electromagnetic calorimeter

    International Nuclear Information System (INIS)

    Badoni, D; Fucci, A; Paoluzzi, G; Salamon, A; Salina, G; Bizzarri, M; Bonaiuto, V; Simone, N De; Federici, L; Sargeni, F; Checcucci, B; Papi, A; Piccini, M; Santovetti, E; Venditti, S

    2014-01-01

    The goal of the NA62 experiment at the CERN SPS is the measurement of the Branching Ratio of the very rare kaon decay K + →π +  ν ν-bar with a 10% accuracy by collecting 100 events in two years of data taking. An efficient photon veto system is needed to reject the K + →π +  π 0 background and a liquid krypton electromagnetic calorimeter will be used for this purpose in the 1-10 mrad angular region. The L0 trigger system for the calorimeter consists of a peak reconstruction algorithm implemented on FPGA by using a mixed parallel architecture based on soft core Altera NIOS II embedded processors together with custom VHDL modules. This solution allows an efficient and flexible reconstruction of the energy-deposition peak. The system will be totally composed of 36 TEL62 boards, 108 mezzanine cards and 215 high-performance FPGAs. We describe the design, current status and the results of the first performance tests

  2. A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System.

    Science.gov (United States)

    Zhang, Zhen; Ma, Cheng; Zhu, Rong

    2017-08-23

    Artificial Neural Networks (ANNs), including Deep Neural Networks (DNNs), have become the state-of-the-art methods in machine learning and achieved amazing success in speech recognition, visual object recognition, and many other domains. There are several hardware platforms for developing accelerated implementation of ANN models. Since Field Programmable Gate Array (FPGA) architectures are flexible and can provide high performance per watt of power consumption, they have drawn a number of applications from scientists. In this paper, we propose a FPGA-based, granularity-variable neuromorphic processor (FBGVNP). The traits of FBGVNP can be summarized as granularity variability, scalability, integrated computing, and addressing ability: first, the number of neurons is variable rather than constant in one core; second, the multi-core network scale can be extended in various forms; third, the neuron addressing and computing processes are executed simultaneously. These make the processor more flexible and better suited for different applications. Moreover, a neural network-based controller is mapped to FBGVNP and applied in a multi-input, multi-output, (MIMO) real-time, temperature-sensing and control system. Experiments validate the effectiveness of the neuromorphic processor. The FBGVNP provides a new scheme for building ANNs, which is flexible, highly energy-efficient, and can be applied in many areas.

  3. A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System

    Directory of Open Access Journals (Sweden)

    Zhen Zhang

    2017-08-01

    Full Text Available Artificial Neural Networks (ANNs, including Deep Neural Networks (DNNs, have become the state-of-the-art methods in machine learning and achieved amazing success in speech recognition, visual object recognition, and many other domains. There are several hardware platforms for developing accelerated implementation of ANN models. Since Field Programmable Gate Array (FPGA architectures are flexible and can provide high performance per watt of power consumption, they have drawn a number of applications from scientists. In this paper, we propose a FPGA-based, granularity-variable neuromorphic processor (FBGVNP. The traits of FBGVNP can be summarized as granularity variability, scalability, integrated computing, and addressing ability: first, the number of neurons is variable rather than constant in one core; second, the multi-core network scale can be extended in various forms; third, the neuron addressing and computing processes are executed simultaneously. These make the processor more flexible and better suited for different applications. Moreover, a neural network-based controller is mapped to FBGVNP and applied in a multi-input, multi-output, (MIMO real-time, temperature-sensing and control system. Experiments validate the effectiveness of the neuromorphic processor. The FBGVNP provides a new scheme for building ANNs, which is flexible, highly energy-efficient, and can be applied in many areas.

  4. A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

    Science.gov (United States)

    Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

    2015-10-01

    Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

  5. Control electronic platform based on floating-point DSP and FPGA for a NPC multilevel back-to-back converter

    Energy Technology Data Exchange (ETDEWEB)

    Rodriguez, Francisco J.; Cobreces, Santiago; Bueno, Emilio J.; Hernandez, Alvaro; Mateos, Raul; Espinosa, Felipe [Department of Electronics, University of Alcala, Alcala de Henares, Madrid (Spain)

    2008-09-15

    Modern energy concepts as Distributed Power Generation are changing the appearance of electric distribution and transmission and challenging power electronics researchers, which try to develop new solutions of electronic controllers. The aim is to enable the implementation of new and more complex control algorithms to verify the last standards related to the grid energy quality for new power converters, and, also, for equipments which nowadays are operating. This paper presents the design, implementation and test of a novel real-time controller for a Neutral Point Clamped (NPC) (three-level) multilevel converter based on a floating-point Digital Signal Processor (DSP) and on a Field-Programmable Gate Array (FPGA), by operating in a cooperative way. Although the proposed system can be readily applied to any power electronic application, in this work, it is focused on the next system: a 150 kVA back-to-back three-level NPC Voltage Source Converter (VSC) for wind power applications. (author)

  6. FPGA implementation of a single-input fuzzy logic controller for boost converter with the absence of an external analog-to-digital converter

    DEFF Research Database (Denmark)

    Taeed, Fazel; Salam, Z.; Ayob, S.

    2012-01-01

    converter (ADC). Instead, a simple analog-to-digital conversion scheme is implemented using the FPGA itself. Due to the simplicity of the SIFLC algorithm and the absence of an external ADC, the overall implementation requires only 408 logic elements and five input-output pins of the FPGA.......) and applied on a 50-W boost converter. The SIFLC is compared to the proportional-integral controller; the simulation and practical results indicate that SIFLC exhibits excellent performance for step load and input reference changes. Another feature of this work is the absence of an external analog-to-digital...

  7. RADIOMETRIC CALIBRATION OF MARS HiRISE HIGH RESOLUTION IMAGERY BASED ON FPGA

    Directory of Open Access Journals (Sweden)

    Y. Hou

    2016-06-01

    Full Text Available Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

  8. A High-Performance FPGA-Based Image Feature Detector and Matcher Based on the FAST and BRIEF Algorithms

    Directory of Open Access Journals (Sweden)

    Michał Fularz

    2015-10-01

    Full Text Available Image feature detection and matching is a fundamental operation in image processing. As the detected and matched features are used as input data for high-level computer vision algorithms, the matching accuracy directly influences the quality of the results of the whole computer vision system. Moreover, as the algorithms are frequently used as a part of a real-time processing pipeline, the speed at which the input image data are handled is also a concern. The paper proposes an embedded system architecture for feature detection and matching. The architecture implements the FAST feature detector and the BRIEF feature descriptor and is capable of establishing key point correspondences in the input image data stream coming from either an external sensor or memory at a speed of hundreds of frames per second, so that it can cope with most demanding applications. Moreover, the proposed design is highly flexible and configurable, and facilitates the trade-off between the processing speed and programmable logic resource utilization. All the designed hardware blocks are designed to use standard, widely adopted hardware interfaces based on the AMBA AXI4 interface protocol and are connected using an underlying direct memory access (DMA architecture, enabling bottleneck-free inter-component data transfers.

  9. SEU mitigation exploratory tests in a ITER related FPGA

    International Nuclear Information System (INIS)

    Batista, Antonio J.N.; Leong, Carlos; Santos, Bruno; Fernandes, Ana; Ramos, Ana Rita; Santos, Joana P.; Marques, José G.; Teixeira, Isabel C.; Teixeira, João P.; Sousa, Jorge; Gonçalves, Bruno

    2017-01-01

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  10. SEU mitigation exploratory tests in a ITER related FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

    2017-05-15

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  11. Digital Controller Development Methodology Based on Real-Time Simulations with LabVIEW FPGA Hardware-Software Toolset

    Directory of Open Access Journals (Sweden)

    Tommaso Caldognetto

    2013-12-01

    Full Text Available In this paper, we exemplify the use of NI Lab-VIEW FPGA as a rapid prototyping environment for digital controllers. In our power electronics laboratory, it has been successfully employed in the development, debugging, and test of different power converter controllers for microgrid applications.The paper shows how this high level programming language,together with its target hardware platforms, including CompactRIO and Single Board RIO systems, allows researchers and students to develop even complex applications in reasonable times. The availability of efficient drivers for the considered hardware platforms frees the users from the burden of low level programming. At the same time, the high level programming approach facilitates software re-utilization, allowing the laboratory know-how to steadily grow along time. Furthermore, it allows hardware-in-the-loop real-time simulation, that proved to be effective, and safe, in debugging even complex hardware and software co-designed controllers. To illustrate the effectiveness of these hardware-software toolsets and of the methodology based upon them, two case studies are

  12. Digitally Controlled Point of Load Converter with Very Fast Transient Response

    DEFF Research Database (Denmark)

    Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

    2007-01-01

    voltage mode control and very fast transient response. The DiSOM modulator is combined with a digital PID compensator algorithm is implemented in a hybrid CPLD/FPGA and is used to control a synchronous Buck converter, which is used in typical Point of Load applications. The computational time is only......This paper presents a new Digital Self-Oscillating Modulator (DiSOM) that allows the duty cycle to be changed instantly. The DiSOM modulator is shown to have variable switching that is a function of the duty cycle. Compared to a more traditional digital PWM modulator based on a counter...... and comparator the DiSOM modulator allows the sampling frequency of the output voltage control loop to be higher than the switching frequency of the power converter, typically a DC/DC converter. The features of the DiSOM modulator makes it possible to design a digitally controlled DC/DC converter with linear...

  13. FPGA Design and Verification Procedure for Nuclear Power Plant MMIS

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Yoo, Kawnwoo; Ryoo, Kwangki [Hanbat National Univ., Daejeon (Korea, Republic of)

    2013-05-15

    In this paper, it is shown that it is possible to ensure reliability by performing the steps of the verification based on the FPGA development methodology, to ensure the safety of application to the NPP MMIS of the FPGA run along the step. Currently, the PLC (Programmable Logic Controller) which is being developed is composed of the FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit). As the importance of the FPGA in the NPP (Nuclear Power Plant) MMIS (Man-Machine Interface System) has been increasing than before, the research on the verification of the FPGA has being more and more concentrated recently.

  14. A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline

    International Nuclear Information System (INIS)

    Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Wilson, Peter; Phillips, Thomas J.

    2005-01-01

    We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR), FERMILAB-Pub-96/390-E. The TDC described here is intended as a further upgrade beyond that described in the TDR] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2ns, a minimum input pulse width of 4.8ns and a minimum separation of 4.8ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47Mbytes/s. The TDC module also produces prompt trigger data every Tevatron crossing via a deadtimeless fast logic path that can be easily reprogrammed. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and

  15. Qualification of FPGA-Based Safety-Related PRM System

    International Nuclear Information System (INIS)

    Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

    2011-01-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

  16. Development of 8K-MCA Add-on based on FPGA technique with a control of VB6 software application under windows environment

    International Nuclear Information System (INIS)

    Dang Lanh; Nguyen Nhi Dien; Nguyen Xuan Hai; Nguyen Bach Viet; Pham Ngoc Son; Huynh Minh; Vuong Huu Tan; Pham Dinh Khang; Phan Nam Anh

    2003-01-01

    The multichannel analyzer is the heart of most experimental measurements. Today, it becomes popular and convenient. It can play a role of getting, processing data and easily interfacing to PC. Some standard-alone multichannel analysis systems can be replaced by Add-on MCA card. Especially, MCA card is necessary for application in nuclear physics research. The main aim of this sub-project is to focus on a design and construction of an 8K-MCA Add-on served for studying nuclear structure, for development of Gamma spectroscopy system, and for a production of low-cost electronics instruments as well. Some experimental results were obtained through the aforementioned card combining with other needed functional analog units. A multichannel data processing (MCD) circuit for nuclear spectroscopy application was developed using a field programmable gate arrays (FPGA) as the central processing element. In addition to the first role, A 13-bit analog-to-digital converter (8k ADC) circuit for nuclear spectroscopy application was also developed using a successive approximation ADC with a control of FPGA technology. The FPGA operates a program that builds the distributed functions of data collected by the ADC and then corrects the ADC differential non-linearity (DNL) via the sliding scale method. The acquisition routine runs in 3.7μ s. the conversion time is approximated 2.2μ s, and the integral non-linearity ≤ 0.14%. (author)

  17. ATCA/AXIe compatible board for fast control and data acquisition in nuclear fusion experiments

    International Nuclear Information System (INIS)

    Batista, A.J.N.; Leong, C.; Bexiga, V.; Rodrigues, A.P.; Combo, A.; Carvalho, B.B.; Fortunato, J.; Correia, M.; Teixeira, J.P.; Teixeira, I.C.; Sousa, J.; Gonçalves, B.; Varandas, C.A.F.

    2012-01-01

    Highlights: ► High performance board for fast control and data acquisition. ► Large IO channel number per board with galvanic isolation. ► Optimized for high reliability and availability. ► Targeted for nuclear fusion experiments with long duration discharges. ► To be used on the ITER Fast Plant System Controller prototype. - Abstract: An in-house development of an Advanced Telecommunications Computing Architecture (ATCA) board for fast control and data acquisition, with Input/Output (IO) processing capability, is presented. The architecture, compatible with the ATCA (PICMG 3.4) and ATCA eXtensions for Instrumentation (AXIe) specifications, comprises a passive Rear Transition Module (RTM) for IO connectivity to ease hot-swap maintenance and simultaneously to increase cabling life cycle. The board complies with ITER Fast Plant System Controller (FPSC) guidelines for rear IO connectivity and redundancy, in order to provide high levels of reliability and availability to the control and data acquisition systems of nuclear fusion devices with long duration plasma discharges. Simultaneously digitized data from all Analog to Digital Converters (ADC) of the board can be filtered/decimated in a Field Programmable Gate Array (FPGA), decreasing data throughput, increasing resolution, and sent through Peripheral Component Interconnect (PCI) Express to multi-core processors in the ATCA shelf hub slots. Concurrently the multi-core processors can update the board Digital to Analog Converters (DAC) in real-time. Full-duplex point-to-point communication links between all FPGAs, of peer boards inside the shelf, allow the implementation of distributed algorithms and Multi-Input Multi-Output (MIMO) systems. Support for several timing and synchronization solutions is also provided. Some key features are onboard ADC or DAC modules with galvanic isolation, Xilinx Virtex 6 FPGA, standard Dual Data Rate (DDR) 3 SODIMM memory, standard CompactFLASH memory card, Intelligent

  18. Design and Implementation of Neuro-Fuzzy Controller Using FPGA for Sun Tracking System

    OpenAIRE

    Ammar A. Aldair; Adel A. Obed; Ali F. Halihal

    2016-01-01

    Nowadays, renewable energy is being used increasingly because of the global warming and destruction of the environment. Therefore, the studies are concentrating on gain of maximum power from this energy such as the solar energy. A sun tracker is device which rotates a photovoltaic (PV) panel to the sun to get the maximum power. Disturbances which are originated by passing the clouds are one of great challenges in design of the controller in addition to the losses power due to energy consumpti...

  19. DOOCS patterns, reusable software components for FPGA based RF GUN field controller

    International Nuclear Information System (INIS)

    Pucyk, P.

    2006-01-01

    Modern accelerator technology combines software and hardware solutions to provide distributed, high efficiency digital systems for High Energy Physics experiments. Providing flexible, maintainable software is crucial for ensuring high availability of the whole system. In order to fulfil all these requirements, appropriate design and development techniques have to be used. Software patterns are well known solution for common programming issues, providing proven development paradigms, which can help to avoid many design issues. DOOCS patterns introduces new concepts of reusable software components for control system algorithms development and implementation in DOOCS framework. Chosen patterns have been described and usage examples have been presented in this paper. (orig.)

  20. DOOCS patterns, reusable software components for FPGA based RF GUN field controller

    Energy Technology Data Exchange (ETDEWEB)

    Pucyk, P. [Institute of Electronic Systems, Warsaw (Poland)

    2006-07-01

    Modern accelerator technology combines software and hardware solutions to provide distributed, high efficiency digital systems for High Energy Physics experiments. Providing flexible, maintainable software is crucial for ensuring high availability of the whole system. In order to fulfil all these requirements, appropriate design and development techniques have to be used. Software patterns are well known solution for common programming issues, providing proven development paradigms, which can help to avoid many design issues. DOOCS patterns introduces new concepts of reusable software components for control system algorithms development and implementation in DOOCS framework. Chosen patterns have been described and usage examples have been presented in this paper. (orig.)

  1. Tethered Forth system for FPGA applications

    Science.gov (United States)

    Goździkowski, Paweł; Zabołotny, Wojciech M.

    2013-10-01

    This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

  2. Fast-acting nuclear reactor control device

    International Nuclear Information System (INIS)

    Kotlyar, O.M.; West, P.B.

    1993-01-01

    A fast-acting nuclear reactor control device is described for controlling a safety control rod within the core of a nuclear reactor, the reactor controlled by a reactor control system, the device comprising: a safety control rod drive shaft and an electromagnetic clutch co-axial with the drive shaft operatively connected to the safety control rod for driving and positioning the safety control rod within or without the reactor core during reactor operation, the safety rod being oriented in a substantially vertical position to allow the rod to fall into the reactor core under the influence of gravity during shutdown of the reactor; the safety control rod drive shaft further operatively connected to a hydraulic pump such that operation of the drive shaft simultaneously drives and positions the safety control rod and operates the hydraulic pump such that a hydraulic fluid is forced into an accumulator, filling the accumulator with oil for the storage and supply of primary potential energy for safety control rod insertion such that the release of potential energy in the accumulator causes hydraulic fluid to flow through the hydraulic pump, converting the hydraulic pump to a hydraulic motor having speed and power capable of full length insertion and high speed driving of the safety control rod into the reactor core; a solenoid valve interposed between the hydraulic pump and the accumulator, said solenoid valve being a normally open valve, actuated to close when the safety control rod is out of the reactor during reactor operation; and further wherein said solenoid opens in response to a signal from the reactor control system calling for shutdown of the reactor and rapid insertion of the safety control rod into the reactor core, such that the opening of the solenoid releases the potential energy in the accumulator to place the safety control rod in a safe shutdown position

  3. Design of a temperature control system using incremental PID algorithm for a special homemade shortwave infrared spatial remote sensor based on FPGA

    Science.gov (United States)

    Xu, Zhipeng; Wei, Jun; Li, Jianwei; Zhou, Qianting

    2010-11-01

    An image spectrometer of a spatial remote sensing satellite requires shortwave band range from 2.1μm to 3μm which is one of the most important bands in remote sensing. We designed an infrared sub-system of the image spectrometer using a homemade 640x1 InGaAs shortwave infrared sensor working on FPA system which requires high uniformity and low level of dark current. The working temperature should be -15+/-0.2 Degree Celsius. This paper studies the model of noise for focal plane array (FPA) system, investigated the relationship with temperature and dark current noise, and adopts Incremental PID algorithm to generate PWM wave in order to control the temperature of the sensor. There are four modules compose of the FPGA module design. All of the modules are coded by VHDL and implemented in FPGA device APA300. Experiment shows the intelligent temperature control system succeeds in controlling the temperature of the sensor.

  4. Test results of an ITER relevant FPGA when irradiated with neutrons

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J. N.; Santos, Bruno; Fernandes, Ana; Goncalves, Bruno [Instituto de Plasmas e Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Leong, Carlos; Teixeira, Joao P. [Instituto de Engenharia de Sistemas e Computadores - Investigacao e Desenvolvimento, 1000-029 Lisboa, (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, Jose G. [Centro de Ciencias e Tecnologias Nucleares, Instituto Superior Tecnico, Universidade de Lisboa, 2695-066 Bobadela, (Portugal)

    2015-07-01

    The data acquisition and control instrumentation cubicles room of the ITER tokamak will be irradiated with neutrons during the fusion reactor operation. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of I and C products - Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), functional data stored in dedicated Block RAM (BRAM) and functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons causes soft errors, unintended changes (bit-flips) to the values stored in state elements of the FPGA. The SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA configuration memory. Novel SEU sensors with Error Correction Code (ECC) detect and repair the BRAM memories. Proper management of SEU can increase reliability and availability of control instrumentation hardware for nuclear applications. The results of the tests performed using the SEM controller and the BRAM SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU errors in the configuration and BRAM memories. (authors)

  5. An FPGA-Based High-Speed Error Resilient Data Aggregation and Control for High Energy Physics Experiment

    Science.gov (United States)

    Mandal, Swagata; Saini, Jogender; Zabołotny, Wojciech M.; Sau, Suman; Chakrabarti, Amlan; Chattopadhyay, Subhasis

    2017-03-01

    Due to the dramatic increase of data volume in modern high energy physics (HEP) experiments, a robust high-speed data acquisition (DAQ) system is very much needed to gather the data generated during different nuclear interactions. As the DAQ works under harsh radiation environment, there is a fair chance of data corruption due to various energetic particles like alpha, beta, or neutron. Hence, a major challenge in the development of DAQ in the HEP experiment is to establish an error resilient communication system between front-end sensors or detectors and back-end data processing computing nodes. Here, we have implemented the DAQ using field-programmable gate array (FPGA) due to some of its inherent advantages over the application-specific integrated circuit. A novel orthogonal concatenated code and cyclic redundancy check (CRC) have been used to mitigate the effects of data corruption in the user data. Scrubbing with a 32-b CRC has been used against error in the configuration memory of FPGA. Data from front-end sensors will reach to the back-end processing nodes through multiple stages that may add an uncertain amount of delay to the different data packets. We have also proposed a novel memory management algorithm that helps to process the data at the back-end computing nodes removing the added path delays. To the best of our knowledge, the proposed FPGA-based DAQ utilizing optical link with channel coding and efficient memory management modules can be considered as first of its kind. Performance estimation of the implemented DAQ system is done based on resource utilization, bit error rate, efficiency, and robustness to radiation.

  6. Computer vision camera with embedded FPGA processing

    Science.gov (United States)

    Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

    2000-03-01

    Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

  7. Signal compression in radar using FPGA

    OpenAIRE

    Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

    2010-01-01

    We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

  8. FPGA Implementation of Computer Vision Algorithm

    OpenAIRE

    Zhou, Zhonghua

    2014-01-01

    Computer vision algorithms, which play an significant role in vision processing, is widely applied in many aspects such as geology survey, traffic management and medical care, etc.. Most of the situations require the process to be real-timed, in other words, as fast as possible. Field Programmable Gate Arrays (FPGAs) have a advantage of parallelism fabric in programming, comparing to the serial communications of CPUs, which makes FPGA a perfect platform for implementing vision algorithms. The...

  9. Development and applications of a multi-purpose digital controller with a System-on-Chip FPGA for accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Kurimoto, Yoshinori, E-mail: kurimoto@post.j-parc.jp [High Energy Accelerator Research Organization (KEK), Ibaraki 319-1195 (Japan); Nakamura, Keigo [Department of Physics, Kyoto University, Kyoto 606-8502 (Japan)

    2016-12-21

    J-PARC Main Ring (MR) is a high intensity proton synchrotron which accelerates protons from 3 GeV to 30 GeV. It has operated at a beam intensity of 390 kW and an upgrade toward the megawatt rating is scheduled. For higher beam intensity, some of the accelerator components require more intelligent and complicated functions. To consolidate such functions among various components, we developed multi-purpose digital boards using a System-on-Chip Field-Programmable Gated Array (SoC FPGA). In this paper, we describe the details of our developed boards as well as their possible applications. As an application of the boards, we have successfully performed the measurement of the betatron amplitude function during beam acceleration in J-PARC MR. The experimental setup and results of the measurement are also described in detail.

  10. The Timing and Fast Control Demonstrator

    CERN Document Server

    Chen, Jiheng; Gustafsson, Leif

    In this thesis, the feasibility of an FPGA to host a system for generating and distributing clocks as well as distributing synchronous and asynchronous commands is tested. This system will be an imitation of the SHiP (Search for Hidden Particle) DAQ (Data Acquisition) system led by CERN. The practical implementation is to mainly apply Altera Cyclone V GT development board attached with SFP+ daughter card to achieve accurate timing and high speed performance. Experiments include three loopback test implementations. Loopback test is the simplest technique to assess a channel’s integration. The first one is the Ethernet loopback test. An Ethernet card daughter board is inserted to the HSMC port of the Cyclone V GT development board. After that, a SFP card is applied alternatively on the same port to do the similar loopback test but at a much higher speed via optical fibers. And finally, a more advanced XAUI to SFP+ card daughter board will be used to replace the previous SFP card in order to get a further spee...

  11. Real-time digital simulation of power electronics systems with Neutral Point Piloted multilevel inverter using FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Rakotozafy, Mamianja [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France); Poure, Philippe [Laboratoire d' Instrumentation Electronique de Nancy (LIEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Saadate, Shahrokh [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Bordas, Cedric; Leclere, Loic [CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France)

    2011-02-15

    Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling complexities. Therefore, simulation of fast switching converters' instantaneous models requires smaller computing time step. The approach presented in this paper proposes an answer to such limited modeling accuracies and computational bandwidth of the currently available digital simulators.As an example, the authors present a low cost, flexible and high performance FPGA-based real-time digital simulator for a complete complex power system with Neutral Point Piloted (NPP) three-level inverter. The proposed real-time simulator can model accurately and efficiently the complete power system, reducing costs, physical space and avoiding any damage to the actual equipment in the case of any dysfunction of the digital controller prototype. The converter model is computed at a small fixed time step as low as 100 ns. Such a computation time step allows high precision account of the gating signals and thus avoids averaging methods and event compensations. Moreover, a novel high performance model of the NPP three-level inverter has also been proposed for FPGA implementation. The proposed FPGA-based simulator models the environment of the NPP converter: the dc link, the RLE load and the digital controller and gating signals. FPGA-based real time simulation results are presented and compared with offline results obtained using PLECS software. They validate the efficiency and accuracy of the modeling for the proposed high performance FPGA-based real-time simulation approach. This paper also introduces new potential FPGA-based applications such as low cost real time simulator for power systems by developing a library of flexible and portable models for power converters, electrical machines and drives. (author)

  12. Real-time FPGA architectures for computer vision

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar

    2000-03-01

    This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

  13. Development of an On-Line Self-Tuning FPGA-PID-PWM Control Algorithm Design for DC-DC Buck Converter in Mobile Applications

    Directory of Open Access Journals (Sweden)

    Ahmed Sabah Al-Araji

    2017-08-01

    Full Text Available This paper presents a new development of an on-line hybrid self-tuning control algorithm of the Field Programmable Gate Array - Proportional Integral Derivative - Pulse Width Modulation (FPGA-PID-PWM controller for DC-DC buck converter which is used in battery operation of mobile applications. The main goal in this work is to propose structure of the hybrid Bees-PSO tuning control algorithm which has a capability of quickly and precisely searching in the global regions in order to obtain optimal gain parameters for the proposed controller to generate the best voltage control action to achieve the desired performance of the Buck converter output. Matlab simulation results and Xilinx development tool Integrated Software Environment (ISE experimental work show the robustness and effectiveness of the proposed on-line hybrid Bees-PSO tuning control algorithm in terms of obtaining smooth and unsaturated state voltage control action and minimizing the tracking voltage error of the Buck converter output. Moreover, the fitness evaluation number is reduced.

  14. Autonomous Lawnmower using FPGA implementation.

    Science.gov (United States)

    Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

    2016-11-01

    Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

  15. Video Watermarking Implementation Based on FPGA

    International Nuclear Information System (INIS)

    EL-ARABY, W.S.M.S.

    2012-01-01

    The sudden increase in watermarking interest is most likely due to the increase in concern over copyright protection of content. With the rapid growth of the Internet and the multimedia systems in distributed environments, digital data owners are now easier to transfer multimedia documents across the Internet. However, current technology does not protect their copyrights properly. This leads to wide interest of multimedia security and multimedia copyright protection and it has become a great concern to the public in recent years. In the early days, encryption and control access techniques were used to protect the ownership of media. Recently, the watermarking techniques are utilized to keep safely the copyrights. In this thesis, a fast and secure invisible video watermark technique has been introduced. The technique based mainly on DCT and Low Frequency using pseudo random number (PN) sequence generator for embedding algorithm. The system has been realized using VHDL and the results have been verified using MATLAB. The implementation of the introduced watermark system done using Xilinx chip (XCV800). The implementation results show that the total area of watermark technique is 45% of total FPGA area with maximum delay equals 16.393ns. The experimental results show that the two techniques have mean square error (MSE) equal to 0.0133 and peak signal to noise ratio (PSNR) equal to 66.8984db. The results have been demonstrated and compared with conventional watermark technique using DCT.

  16. Application of reflective memory network in Tokamak fast controller

    International Nuclear Information System (INIS)

    Weng Chuqiao; Zhang Ming; Liu Rui; Zheng Wei; Zhuang Ge

    2014-01-01

    A specific application of reflective memory network in Tokamak fast controller was introduced in this paper. The PMC-5565 reflective memory card and ACC-5565 network hub were used to build a reflective memory real-time network to test its real- time function. The real-time, rapidity and determinacy of the time delay for fast controller controlling power device under the reflective memory network were tested in the LabVIEW RT real-time operation system. Depending on the reflective memory technology, the data in several fast controllers were synchronized, and multiple control tasks using a single control task were finished. The experiment results show that the reflective memory network can meet the real-time requirements for fast controller to perform the feedback control over devices. (authors)

  17. Specification of requirements for the implementation of ASICs and FPGA in instrumentation and control systems important to safety in German NPPs

    International Nuclear Information System (INIS)

    Schnurer, G.

    2007-01-01

    This paper gives an overview concerning the design as well as the verification and validation of Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGA) in German NPPs which are applied to carry out I and C functions. The qualification procedures dealt with restricted on ASICs without any microcontroller core. Dependent on the different safety categories, recommendations concerning the qualification level and procedures are elaborated which have to be achieved for ASICs and FPGA. Important aspects within the framework of the expert judgement for upgrading of safety relevant I and C by ASICs and FPGA are dealt with. These aspects are of general character and are mainly focused on suitability test procedures and robustness requirements of ASICs and FPGA

  18. FPGA Vision Data Architecture

    Science.gov (United States)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  19. Real-Time Control System for Improved Precision and Throughput in an Ultrafast Carbon Fiber Placement Robot Using a SoC FPGA Extended Processing Platform

    Directory of Open Access Journals (Sweden)

    Gilberto Ochoa-Ruiz

    2017-01-01

    Full Text Available We present an architecture for accelerating the processing and execution of control commands in an ultrafast fiber placement robot. The system consists of a robotic arm designed by Coriolis Composites whose purpose is to move along a surface, on which composite fibers are deposed, via an independently controlled head. In first system implementation, the control commands were sent via Profibus by a PLC, limiting the reaction time and thus the precision of the fiber placement and the maximum throughput. Therefore, a custom real-time solution was imperative in order to ameliorate the performance and to meet the stringent requirements of the target industry (avionics, aeronautical systems. The solution presented in this paper is based on the use of a SoC FPGA processing platform running a real-time operating system (FreeRTOS, which has enabled an improved comamnd retrieval mechanism. The system’s placement precision was improved by a factor of 20 (from 1 mm to 0.05 mm, while the maximum achievable throughput was 1 m/s, compared to the average 30 cm/s provided by the original solution, enabling fabricating more complex and larger pieces in a significant fraction of the time.

  20. From OO to FPGA :

    Energy Technology Data Exchange (ETDEWEB)

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  1. Realise of PWM-generating based on FPGA

    International Nuclear Information System (INIS)

    Su Rongfeng; Xu Ruinian; Huang Maomao

    2012-01-01

    The power supply digital controllers of Shanghai Synchrotron Radiation Facility(SSRF) make use of the PWM (pulse width modulation) wave as the feedback to the power-electrical devices, so as to obtain constant current of high accuracy and stability. The design of PWM wave generation structure in FPGA is good for a compact controller,and the reduction of the usage of Integrated Circuits (ICs) decreases the interference from the noise among the ICs, hence better performance of the controller. In addition, FPGA can be programmed circularly at any time,so as to optimize the structure design and make a maximum use of the advantage of FPGA. As a part of transplanting the complete function of the DSP (digital signal processor/processing), realizing the generation of PWM wave in FPGA is feasible. In this paper, we report progress in this regard at SSRF. (authors)

  2. FPGA programming using FX3

    CERN Document Server

    Calleja, Stefano

    2014-01-01

    An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

  3. Intermittent fasting: a "new" historical strategy for controlling seizures?

    Science.gov (United States)

    Hartman, Adam L; Rubenstein, James E; Kossoff, Eric H

    2013-05-01

    In antiquity, fasting was a treatment for epilepsy and a rationale for the ketogenic diet (KD). Preclinical data indicate the KD and intermittent fasting do not share identical anticonvulsant mechanisms. We implemented an intermittent fasting regimen in six children with an incomplete response to a KD. Three patients adhered to the combined intermittent fasting/KD regimen for 2 months and four had transient improvement in seizure control, albeit with some hunger-related adverse reactions. Copyright © 2012 Elsevier B.V. All rights reserved.

  4. Multichannel analyzer embedded in FPGA; Analizador multicanal embebido en FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98060 Zacatecas, Zac. (Mexico); Ordaz G, O. O. [Universidad de Cordoba, Departamento de Arquitectura de Computadores, Electronica y Tecnologia Electronica, Campus de Rabanales, Ctra. N-IVa Km 396, 14071 Cordoba (Spain); Bravo M, I., E-mail: angelogarciad@hotmail.com [Universidad de Alcala de Henares, Departamento de Electronica, Campus Universitario, Carretera Madrid-Barcelona Km 33.600, 28801 Alcala de Henares, Madrid (Spain)

    2017-10-15

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  5. Design of a fast runback feature for PRISM control

    International Nuclear Information System (INIS)

    Wagner, W.K.; Rhow, S.K.; Daniel, W.R.; Dayal, Y.; Gaubatz, D.C.

    1988-01-01

    The nine power reactor inherently safe modules (PRISM) are controlled and their operation coordinated by a hierarchical, distributed, digital plant control system (PCS). This paper describes the fast runback features of the PCS. Fast runback consists of PCS directed reactor module shutdown with accompanying reductions of coolant flows. Analyses have shown that the PCS fast runback adequately terminates duty cycle events initiated in the balance of plant and the steam generating system, results in lower thermal shock to the reactor than scram, and reduces the number of scrams by approximately a factor of five

  6. Engineering Design of ITER Prototype Fast Plant System Controller

    Science.gov (United States)

    Goncalves, B.; Sousa, J.; Carvalho, B.; Rodrigues, A. P.; Correia, M.; Batista, A.; Vega, J.; Ruiz, M.; Lopez, J. M.; Rojo, R. Castro; Wallander, A.; Utzel, N.; Neto, A.; Alves, D.; Valcarcel, D.

    2011-08-01

    The ITER control, data access and communication (CODAC) design team identified the need for two types of plant systems. A slow control plant system is based on industrial automation technology with maximum sampling rates below 100 Hz, and a fast control plant system is based on embedded technology with higher sampling rates and more stringent real-time requirements than that required for slow controllers. The latter is applicable to diagnostics and plant systems in closed-control loops whose cycle times are below 1 ms. Fast controllers will be dedicated industrial controllers with the ability to supervise other fast and/or slow controllers, interface to actuators and sensors and, if necessary, high performance networks. Two prototypes of a fast plant system controller specialized for data acquisition and constrained by ITER technological choices are being built using two different form factors. This prototyping activity contributes to the Plant Control Design Handbook effort of standardization, specifically regarding fast controller characteristics. Envisaging a general purpose fast controller design, diagnostic use cases with specific requirements were analyzed and will be presented along with the interface with CODAC and sensors. The requirements and constraints that real-time plasma control imposes on the design were also taken into consideration. Functional specifications and technology neutral architecture, together with its implications on the engineering design, were considered. The detailed engineering design compliant with ITER standards was performed and will be discussed in detail. Emphasis will be given to the integration of the controller in the standard CODAC environment. Requirements for the EPICS IOC providing the interface to the outside world, the prototype decisions on form factor, real-time operating system, and high-performance networks will also be discussed, as well as the requirements for data streaming to CODAC for visualization and

  7. Multichannel analyzer embedded in FPGA

    International Nuclear Information System (INIS)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Bravo M, I.

    2017-10-01

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  8. Harmonic analysis and FPGA implementation of SHE controlled three phase CHB 11-level inverter in MV drives using deterministic and stochastic optimization techniques.

    Science.gov (United States)

    Vesapogu, Joshi Manohar; Peddakotla, Sujatha; Kuppa, Seetha Rama Anjaneyulu

    2013-01-01

    With the advancements in semiconductor technology, high power medium voltage (MV) Drives are extensively used in numerous industrial applications. Challenging technical requirements of MV Drives is to control multilevel inverter (MLI) with less Total harmonic distortion (%THD) which satisfies IEEE standard 519-1992 harmonic guidelines and less switching losses. Among all modulation control strategies for MLI, Selective harmonic elimination (SHE) technique is one of the traditionally preferred modulation control technique at fundamental switching frequency with better harmonic profile. On the other hand, the equations which are formed by SHE technique are highly non-linear in nature, may exist multiple, single or even no solution at particular modulation index (MI). However, in some MV Drive applications, it is required to operate over a range of MI. Providing analytical solutions for SHE equations during the whole range of MI from 0 to 1, has been a challenging task for researchers. In this paper, an attempt is made to solve SHE equations by using deterministic and stochastic optimization methods and comparative harmonic analysis has been carried out. An effective algorithm which minimizes %THD with less computational effort among all optimization algorithms has been presented. To validate the effectiveness of proposed MPSO technique, an experiment is carried out on a low power proto type of three phase CHB 11- level Inverter using FPGA based Xilinx's Spartan -3A DSP Controller. The experimental results proved that MPSO technique has successfully solved SHE equations over all range of MI from 0 to 1, the %THD obtained over major range of MI also satisfies IEEE 519-1992 harmonic guidelines too.

  9. A software radio platform based on ARM and FPGA

    Directory of Open Access Journals (Sweden)

    Yang Xin.

    2016-01-01

    Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

  10. Robust fast controller design via nonlinear fractional differential equations.

    Science.gov (United States)

    Zhou, Xi; Wei, Yiheng; Liang, Shu; Wang, Yong

    2017-07-01

    A new method for linear system controller design is proposed whereby the closed-loop system achieves both robustness and fast response. The robustness performance considered here means the damping ratio of closed-loop system can keep its desired value under system parameter perturbation, while the fast response, represented by rise time of system output, can be improved by tuning the controller parameter. We exploit techniques from both the nonlinear systems control and the fractional order systems control to derive a novel nonlinear fractional order controller. For theoretical analysis of the closed-loop system performance, two comparison theorems are developed for a class of fractional differential equations. Moreover, the rise time of the closed-loop system can be estimated, which facilitates our controller design to satisfy the fast response performance and maintain the robustness. Finally, numerical examples are given to illustrate the effectiveness of our methods. Copyright © 2017 ISA. Published by Elsevier Ltd. All rights reserved.

  11. Multifunctional data acquisition system based on USB and FPGA

    International Nuclear Information System (INIS)

    Huang Tuchen; Gong Hui; Shao Beibei

    2013-01-01

    A multifunctional data acquisition system based on USB and FPGA was developed. The system has four analog inputs digitalized by fast ADC. Based on flexibility of FPGA, different functions can be implemented such as waveform sampling, pulse counting, multi-channel pulse height analysis, and charge division readout process. The hardware communicates with host PC via USB interface. The Labview based user soft ware initializes the hardware, configures the running parameters, reads and processes the data as well as displays the result online. (authors)

  12. Using FPGA coprocessor for ATLAS level 2 trigger application

    International Nuclear Information System (INIS)

    Khomich, Andrei; Hinkelbein, Christian; Kugel, Andreas; Maenner, Reinhard; Mueller, Matthias

    2006-01-01

    Tracking has a central role in the event selection for the High-Level Triggers of ATLAS. It is particularly important to have fast tracking algorithms in the trigger system. This paper investigates the feasibility of using FPGA coprocessor for speeding up of the TRT LUT algorithm-one of the tracking algorithms for second level trigger for ATLAS experiment (CERN). Two realisations of the same algorithm have been compared: one in C++ and a hybrid C++/VHDL implementation. Using a FPGA coprocessor gives an increase of speed by a factor of two compared to a CPU-only implementation

  13. FPGA Flash Memory High Speed Data Acquisition

    Science.gov (United States)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  14. The fast correction coil feedback control system

    International Nuclear Information System (INIS)

    Coffield, F.; Caporaso, G.; Zentler, J.M.

    1989-01-01

    A model-based feedback control system has been developed to correct beam displacement errors in the Advanced Test Accelerator (ATA) electron beam accelerator. The feedback control system drives an X/Y dipole steering system that has a 40-MHz bandwidth and can produce ±300-Gauss-cm dipole fields. A simulator was used to develop the control algorithm and to quantify the expected performance in the presence of beam position measurement noise and accelerator timing jitter. The major problem to date has been protecting the amplifiers from the voltage that is inductively coupled to the steering bars by the beam. 3 refs., 8 figs

  15. FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

    Directory of Open Access Journals (Sweden)

    Tomyslav Sledevič

    2013-05-01

    Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

  16. Advanced feeder control using fast simulation models

    NARCIS (Netherlands)

    Verheijen, O.S.; Op den Camp, O.M.G.C.; Beerkens, R.G.C.; Backx, A.C.P.M.; Huisman, L.; Drummond, C.H.

    2005-01-01

    For the automatic control of glass quality in glass production, the relation between process variable and product or glass quality and process conditions/process input parameters must be known in detail. So far, detailed 3-D glass melting simulation models were used to predict the effect of process

  17. Development of a fast voltage control method for electrostatic accelerators

    International Nuclear Information System (INIS)

    Lobanov, Nikolai R.; Linardakis, Peter; Tsifakis, Dimitrios

    2014-01-01

    The concept of a novel fast voltage control loop for tandem electrostatic accelerators is described. This control loop utilises high-frequency components of the ion beam current intercepted by the image slits to generate a correction voltage that is applied to the first few gaps of the low- and high-energy acceleration tubes adjoining the high voltage terminal. New techniques for the direct measurement of the transfer function of an ultra-high impedance structure, such as an electrostatic accelerator, have been developed. For the first time, the transfer function for the fast feedback loop has been measured directly. Slow voltage variations are stabilised with common corona control loop and the relationship between transfer functions for the slow and new fast control loops required for optimum operation is discussed. The main source of terminal voltage instabilities, which are due to variation of the charging current caused by mechanical oscillations of charging chains, has been analysed

  18. An FPGA-based torus communication network

    Energy Technology Data Exchange (ETDEWEB)

    Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

    2011-02-15

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  19. Moessbauer spectrometric data acquisition based on FPGA

    International Nuclear Information System (INIS)

    Zhang Yuan; Li Shimin; Chen Nan; Zhu Jingbo; Xia Yuanfu

    2008-01-01

    FPGA(Field Programmable Gate Array) is a programmable device with strong logical function and timing control ability. It is extremely potent in acquiring and processing timing signals. By replacing the traditional used SCM (Single-Chip Microcomputer) with FPGA, counting speed of Moessbauer spectrometric data acquisition can be improved markedly with significantly decreased size of the spectrometer. The counter, RAM and RS-232 communication of the module are developed on Altera Cyclone series chip EP1C6T144C8 with Quartus II. EP1C6T144C8 has 5980 logical units accompanied by 92160 bits of memory space. It is so powerful that all needs in data acquisition of the Moessbauer spectrometer can be perfectly satisfied while allowing modifications in functions and parameters. (authors)

  20. An FPGA-based torus communication network

    International Nuclear Information System (INIS)

    Pivanti, Marcello; Schifano, Sebastiano Fabio; Simma, Hubert

    2011-02-01

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  1. 8-channel, FPGA based, DSP integrated cavity simulator and controller for VUV-FEL. SIMCON 3.0 Ver. 3.0. rev. 1, 06.2005 - Hardware manual

    International Nuclear Information System (INIS)

    Pozniak, K.T.; Czarski, T.; Koprek, W.; Giergusiewicz, W.; Romaniuk, R.S.

    2005-01-01

    The note describes integrated, eight channel system of hardware controller and simulator of the resonant superconducting, narrowband niobium cavity, originally considered for the TTF and TESLA in DESY, Hamburg (now tested for the VUV FEL and developed for X-Ray FEL). The controller bases on a programmable circuit Xilinx VirtexII V4000. The solution uses DSP EMBEDDED BOARD module positioned on a Modular LLRF Control Platform. The algorithm and FPGA circuit configuration was done in the VHDL language. The internal hardware multiplication components, present in Virtex II chips, were used, to improve the floating point calculation efficiency. The implementation was achieved of a device working in the real time, according to the demands of the LLRF control system for the TESLA Test Facility (now associated with the VUV FEL machine). The device under consideration will be referred to as superconducting cavity (SCCav) SIMCON throughout this work. The manual describes hardware features of SIMCON, ver. 3.0 in modular solution. The following components are described here in detail: functional layer, parameter programming, foundations of control of particular blocks and monitoring of the real time processes. This note is accompanied by the one describing the multichannel DOOCS interface for the described hardware system. The interface was prepared in DOOCS for Solaris and in Windows. The hardware and software of 8-channel SIMCON was tested in CHECIA and ACC1 module of VUV FEL linac. The measurements results are presented. While giving all necessary technical details required to understand the work of the integrated hardware controller and simulator and to enable its practical copying, this document is a unity with other TESLA technical notes published by the same team on the subject. Thus, some modeling and other subjects were omitted, as they were addressed in detail in the quoted references. Keywords: Super conducting cavity, cavity simulator, CAVITIES CONTROLLER, SIMCON

  2. FPGA-Based Sonar Processing

    National Research Council Canada - National Science Library

    Graham, Paul; Nelson, Brent

    1998-01-01

    This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays...

  3. The phase detection and calculation for low hybrid wave phase-feedback control system

    International Nuclear Information System (INIS)

    Liu Qiang; Liang Hao; Zhou Yongzhao; Shan Jiafang

    2008-01-01

    A method of phase detection and calculation for low hybrid wave phase-feedback control system and the implementing the algorithms on DSP cores embedded in FPGA is introduced. By taking the advantages of matlab-aided design and algorithms optimization to carry out parallel processing of multi-channel phase calculation in FPGA with rich resources, the purposed of fast phase-feedback control is achieved under the need of complicated mathematical operations. (authors)

  4. Exploration of Heterogeneous FPGA Architectures

    Directory of Open Access Journals (Sweden)

    Umer Farooq

    2011-01-01

    mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

  5. Adaptive Hardware Cryptography Engine Based on FPGA

    International Nuclear Information System (INIS)

    Afify, M.A.A.

    2011-01-01

    In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

  6. Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

    Directory of Open Access Journals (Sweden)

    He Chen

    2011-12-01

    Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

  7. Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System

    Directory of Open Access Journals (Sweden)

    Juan José Raygoza-Panduro

    2008-01-01

    Full Text Available This paper presents the design and implementation of an automatically generated mathematical unit, from a program developed in Java that describes the VHDL circuit, ready to be synthesized with the Xilinx ISE tool. The core contains diverse complex operations such as mathematical functions including sine and cosine, among others. The proposed unit is used to synthesize a sliding mode controller for a magnetic levitation system. This kind of systems is used in industrial applications requiring high level of mathematical calculations in small time periods. The core is designed to calculate trigonometric and arithmetic operations in such a way that each function is performed in a clock cycle. In this paper, the results of the mathematical core are shown in terms of implementation, utilization, and application to control a magnetic levitation system.

  8. An innovative modular device and wireless control system enabling thermal and pressure sensors using FPGA on real-time fault diagnostics of steam turbine functional deterioration

    Science.gov (United States)

    Devi, S.; Saravanan, M.

    2018-03-01

    It is necessary that the condition of the steam turbines is continuously monitored on a scheduled basis for the safe operation of the steam turbines. The review showed that steam turbine fault detection and operation maintenance system (STFDOMS) is gaining importance recently. In this paper, novel hardware architecture is proposed for STFDOMS that can be communicated through the GSM network. Arduino is interfaced with the FPGA so as to transfer the message. The design has been simulated using the Verilog programming language and implemented in hardware using FPGA. The proposed system is shown to be a simple, cost effective and flexible and thereby making it suitable for the maintenance of steam turbines. This system forewarns the experts to access to data messages and take necessary action in a short period with great accuracy. The hardware developed is promised as a real-time test bench, specifically for investigations of long haul effects with different parameter settings.

  9. Development of Methods and Means of Configuration Data Transfer For Use in an FPGA Based Trigger Controller Device

    International Nuclear Information System (INIS)

    2010-01-01

    To determine if klystrons will perform to the specifications of the LCLS (Linac Coherent Light Source) project, a new digital trigger controller is needed for the Klystron/Microwave Department Test Laboratory. The controller needed to be programmed and Windows based user interface software needed to be written to interface with the device over a USB (Universal Serial Bus). Programming the device consisted of writing logic in VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language), and the Windows interface software was written in C++. Xilinx ISE (Integrated Software Environment) was used to compile the VHDL code and program the device, and Microsoft Visual Studio 2005 was used to compile the C++ based Windows software. The device was programmed in such a way as to easily allow read/write operations to it using a simple addressing model, and Windows software was developed to interface with the device over a USB connection. A method of setting configuration registers in the trigger device is absolutely necessary to the development of a new triggering system, and the method developed will fulfill this need adequately. More work is needed before the new trigger system is ready for use. The configuration registers in the device need to be fully integrated with the logic that will generate the RF signals, and this system will need to be tested extensively to determine if it meets the requirements for low noise trigger outputs.

  10. Development of A Low-Cost FPGA-Based Measurement System for Real-Time Processing of Acoustic Emission Data: Proof of Concept Using Control of Pulsed Laser Ablation in Liquids.

    Science.gov (United States)

    Wirtz, Sebastian F; Cunha, Adauto P A; Labusch, Marc; Marzun, Galina; Barcikowski, Stephan; Söffker, Dirk

    2018-06-01

    Today, the demand for continuous monitoring of valuable or safety critical equipment is increasing in many industrial applications due to safety and economical requirements. Therefore, reliable in-situ measurement techniques are required for instance in Structural Health Monitoring (SHM) as well as process monitoring and control. Here, current challenges are related to the processing of sensor data with a high data rate and low latency. In particular, measurement and analyses of Acoustic Emission (AE) are widely used for passive, in-situ inspection. Advantages of AE are related to its sensitivity to different micro-mechanical mechanisms on the material level. However, online processing of AE waveforms is computationally demanding. The related equipment is typically bulky, expensive, and not well suited for permanent installation. The contribution of this paper is the development of a Field Programmable Gate Array (FPGA)-based measurement system using ZedBoard devlopment kit with Zynq-7000 system on chip for embedded implementation of suitable online processing algorithms. This platform comprises a dual-core Advanced Reduced Instruction Set Computer Machine (ARM) architecture running a Linux operating system and FPGA fabric. A FPGA-based hardware implementation of the discrete wavelet transform is realized to accelerate processing the AE measurements. Key features of the system are low cost, small form factor, and low energy consumption, which makes it suitable to serve as field-deployed measurement and control device. For verification of the functionality, a novel automatically realized adjustment of the working distance during pulsed laser ablation in liquids is established as an example. A sample rate of 5 MHz is achieved at 16 bit resolution.

  11. Fpga based L-band pulse doppler radar design and implementation

    Science.gov (United States)

    Savci, Kubilay

    As its name implies RADAR (Radio Detection and Ranging) is an electromagnetic sensor used for detection and locating targets from their return signals. Radar systems propagate electromagnetic energy, from the antenna which is in part intercepted by an object. Objects reradiate a portion of energy which is captured by the radar receiver. The received signal is then processed for information extraction. Radar systems are widely used for surveillance, air security, navigation, weather hazard detection, as well as remote sensing applications. In this work, an FPGA based L-band Pulse Doppler radar prototype, which is used for target detection, localization and velocity calculation has been built and a general-purpose Pulse Doppler radar processor has been developed. This radar is a ground based stationary monopulse radar, which transmits a short pulse with a certain pulse repetition frequency (PRF). Return signals from the target are processed and information about their location and velocity is extracted. Discrete components are used for the transmitter and receiver chain. The hardware solution is based on Xilinx Virtex-6 ML605 FPGA board, responsible for the control of the radar system and the digital signal processing of the received signal, which involves Constant False Alarm Rate (CFAR) detection and Pulse Doppler processing. The algorithm is implemented in MATLAB/SIMULINK using the Xilinx System Generator for DSP tool. The field programmable gate arrays (FPGA) implementation of the radar system provides the flexibility of changing parameters such as the PRF and pulse length therefore it can be used with different radar configurations as well. A VHDL design has been developed for 1Gbit Ethernet connection to transfer digitized return signal and detection results to PC. An A-Scope software has been developed with C# programming language to display time domain radar signals and detection results on PC. Data are processed both in FPGA chip and on PC. FPGA uses fixed

  12. Fast betatron tune controller for circulating beam in a synchrotron

    International Nuclear Information System (INIS)

    Endo, Takuyuki; Hatanaka, Kichiji; Sato, Kenji

    1997-01-01

    When rf quadrupole (RFQ) electric field is applied to the circulating beam in a synchrotron, an equation of motion is reduced to Mathieu's Equation. A new analytical method to obtain an approximate solution has been developed, while a numerical computation was usually applied. Translating the behavior of approximate solution into terms of an RFQ electric field and betatron oscillation, a fast tune control can be achieved by rapid tuning of both amplitude and frequency of rf voltage. This process could be applied to suppress a tune shift caused by a space charge effect and to control a slow beam extraction with a low ripple. We have started another analytical computation using Hamiltonian with perturbation of RFQ and the results of this computation also suggest that it is applicable to slow beam extraction. The fast tune controller has been constructed and the beam test will be performed at HIMAC synchrotron in cooperation of RCNP and NIRS. (author)

  13. Logic synthesis for FPGA-based finite state machines

    CERN Document Server

    Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

    2016-01-01

    This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

  14. Control rod studies in small and medium sized fast reactors

    International Nuclear Information System (INIS)

    John, T.M.; Mohanakrishnan, P.; Mahalakshmi, B.; Singh, R.S.

    1988-01-01

    Control rods are the primary safety mechanism in the operation of fast reactors. Neutronic parameters associated with the control rods have to be evaluated precisely for studying the behaviour of the reactor under various operating conditions. Control rods are strong neutron absorbers discretely distributed in the reactor core. Accurate estimation of control rod parameters demand, in principle transport theory solutions in exact geometry. But computer codes for such evaluations usually consume exorbitantly large computer time and memory for even a single parameter evaluation. During the design of reactors, evaluation of these parameters will be required for many configurations of control rods. In this paper, the method used at Indira Gandhi Centre for Atomic Research for estimating the parameters associated with control rods is presented. Diffusion theory solutions were used for computations. A scheme using three dimensional geometry represented by triangular meshes and diffusion theory solutions in few energy groups for control rod parameter evaluation is presented. This scheme was employed in estimating the control rod parameters in a 500 Mw(e) fast reactor. Error due to group collapsing is estimated by comparing with 25 group calculations in three dimensions for typical cases. (author). 5 refs, 4 figs, 3 tabs

  15. CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

    CERN Document Server

    Zhu, Yu

    2010-01-01

    Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

  16. Application of Integrated Verification Approach to FPGA-based Safety-Critical I and C System of Nuclear Power Plant

    Energy Technology Data Exchange (ETDEWEB)

    Ahmed, Ibrahim; Heo, Gyunyoung [Kyunghee Univ., Yongin (Korea, Republic of); Jung, Jaecheon [KEPCO, Ulsan (Korea, Republic of)

    2016-10-15

    Safety-critical instrumentation and control (I and C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. Generally in FPGA design verification, the designers make use of verification techniques by writing the test benches which involved various stages of verification activities of register-transfer level (RTL), gate-level, and place and route. Writing the test benches is considerably time consuming and require a lot of efforts to achieve a satisfied desire results. Furthermore, performing the verification at each stage is a major bottleneck and demanded much activities and time. In addition, verification is conceivably, the most difficult and complicated aspect of any design. Therefore, in view of these, this work applied an integrated verification approach to the verification of FPGA-based I and C system in NPP that simultaneously verified the whole design modules using MATLAB/Simulink HDL Co-simulation models. Verification is conceivably, the most difficult and complicated aspect of any design, and an FPGA design is not an exception. Therefore, in this work, we introduced and discussed how an application of integrated verification technique to the verification and testing of FPGA-based I and C system design in NPP can facilitate the verification processes, and verify the entire design modules of the system simultaneously using MATLAB/Simulink HDL co-simulation models. In conclusion, the results showed that, the integrated verification approach through MATLAB/Simulink models, if applied to any design to be verified, could speed up the design verification and reduce the V and V tasks.

  17. Application of Integrated Verification Approach to FPGA-based Safety-Critical I and C System of Nuclear Power Plant

    International Nuclear Information System (INIS)

    Ahmed, Ibrahim; Heo, Gyunyoung; Jung, Jaecheon

    2016-01-01

    Safety-critical instrumentation and control (I and C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. Generally in FPGA design verification, the designers make use of verification techniques by writing the test benches which involved various stages of verification activities of register-transfer level (RTL), gate-level, and place and route. Writing the test benches is considerably time consuming and require a lot of efforts to achieve a satisfied desire results. Furthermore, performing the verification at each stage is a major bottleneck and demanded much activities and time. In addition, verification is conceivably, the most difficult and complicated aspect of any design. Therefore, in view of these, this work applied an integrated verification approach to the verification of FPGA-based I and C system in NPP that simultaneously verified the whole design modules using MATLAB/Simulink HDL Co-simulation models. Verification is conceivably, the most difficult and complicated aspect of any design, and an FPGA design is not an exception. Therefore, in this work, we introduced and discussed how an application of integrated verification technique to the verification and testing of FPGA-based I and C system design in NPP can facilitate the verification processes, and verify the entire design modules of the system simultaneously using MATLAB/Simulink HDL co-simulation models. In conclusion, the results showed that, the integrated verification approach through MATLAB/Simulink models, if applied to any design to be verified, could speed up the design verification and reduce the V and V tasks

  18. Design and development of FPGA based TCP/IP module for real time computers in nuclear power plants

    International Nuclear Information System (INIS)

    Balasri, G. Janani; Santhana Raj, A.; Gour, Aditya; Murali, N.; Manikandan, J.

    2013-01-01

    An VME (Virtual Module Europa) bus based Real Time Computer's (RTC's) are being developed for Prototype Fast Breeder Reactor (PFBR) which is in an advanced stage of construction at Kalpakkam, where the RTC's have to communicate to the central process computer on the data collected from the field instrument and receive data from the central process computer. A Distributed Digital Control System (DDSC) architecture has been designed for this communication which is based on Transfer Communication Protocol/Internet Protocol (TCP/IP) over Ethernet. Currently the RTC's uses 'Wiznet Module', a bought out chip which implements the TCP/IP stack in hardware. This project concentrates on the design and development of Field Programmable Gate Array (FPGA) based TCP/IP module that runs on Microblaze, a 32-bit softcore processor, to take care of the communication as that of Wiznet module. Advantage of switching over to FPGA based system are its reconfigurability, desired number of sockets, and the design is stable even if the FPGA's get obsolete. (author)

  19. Implementation of Adaptive Digital Controllers on Programmable Logic Devices

    Science.gov (United States)

    Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

    2002-01-01

    Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment

  20. FPGA based, DSP board for LLRF 8-Channel SIMCON 3.0 Part I: Hardware

    Science.gov (United States)

    Giergusiewicz, Wojciech; Koprek, Waldemar; Jalmuzna, Wojciech; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.

    2005-09-01

    The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the VUV-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layers, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACC1 module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0 encouraged us to enter the design of SIMCON 3.1 possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0 is a modular solution, while SIMCON 3.1 will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one, after branching off in this version of the SIMCON, will be continued.

  1. The integration of FPGA TDC inside White Rabbit node

    International Nuclear Information System (INIS)

    Li, H.; Xue, T.; Gong, G.; Li, J.

    2017-01-01

    White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

  2. The integration of FPGA TDC inside White Rabbit node

    Science.gov (United States)

    Li, H.; Xue, T.; Gong, G.; Li, J.

    2017-04-01

    White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

  3. Flexible, fpga-based electronics for modular robots

    DEFF Research Database (Denmark)

    Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

    2008-01-01

    In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

  4. Possible approaches to fast quality control of IFE targets

    International Nuclear Information System (INIS)

    Koresheva, E.R.; Nikitenko, A.I.; Aleksandrova, I.V.; Bazdenkov, S.V.; Belolipetskiy, A.A.; Chtcherbakov, V.I.; Osipov, I.E.

    2006-01-01

    In recent years, research into the development of reliable methods and techniques for characterization and quality control of ICF/IFE targets has been carried out very actively. This is motivated by the need to provide the means for precise and accurate knowledge of cryogenic target parameters. On the other hand, particular emphasis should be paid to the fact that fuelling of a commercial power plant requires ∼6 targets each second. This indicates that the development of fast quality control techniques is of critical importance as well. Therefore, in this report we discuss the issues underlying the construction of different algorithms for characterization and quality control of ICF/IFE targets. Among them are: (a) algorithm banks and their structure, (b) algorithm testing, (c) target reconstruction experiments. The algorithm bank incorporates the algorithms for two stages of target production: the stage of fuel layering technique development (motionless target) and the stage of cryogenic target delivery (injected target). In the first case an inverse algorithm for individual target characterization (3D target reconstruction) and two threshold algorithms for fast control of target quality are presented. They are based on tomographic information processing methods. Experimentally, tomographic data acquisition is carried out by a hundred projections microtomograph. The spatial resolution of the optical system of the microtomograph is 1 μm for 490 nm wavelength, the accuracy of target angular positioning is ±1.5-2.5 min. In the second case we describe the algorithm based on Fourier transform holography for ultra fast target characterization during its injection. The performed computer experiments have demonstrated much promise of this approach in the following directions: recognition of the target imperfections in both low- and high- harmonics; quality control of both a single target and a target batch; simultaneous control of both an injected target quality and

  5. Status of fast reactor control rod development in the United Kingdom

    International Nuclear Information System (INIS)

    Kelly, B.T.

    1984-01-01

    The two large fast reactors constructed in the United Kingdom, that is the Dounreay Fast Reactor (DFR) and the Prototype Fast Reactor (PFR) differed substantially in their control systems. DFR was controlled by variation of the neutron leakage from the core while PFR uses conventional control rods containing neutron absorbing materials. This paper describes the development of the PFR control systems, the progressive design of the control systems for the prototype Civil Fast Reactor (CFR) and the supporting research and development programmes. (author)

  6. High speed FPGA-based Phasemeter for the far-infrared laser interferometers on EAST

    Science.gov (United States)

    Yao, Y.; Liu, H.; Zou, Z.; Li, W.; Lian, H.; Jie, Y.

    2017-12-01

    The far-infrared laser-based HCN interferometer and POlarimeter/INTerferometer\\break (POINT) system are important diagnostics for plasma density measurement on EAST tokamak. Both HCN and POINT provide high spatial and temporal resolution of electron density measurement and used for plasma density feedback control. The density is calculated by measuring the real-time phase difference between the reference beams and the probe beams. For long-pulse operations on EAST, the calculation of density has to meet the requirements of Real-Time and high precision. In this paper, a Phasemeter for far-infrared laser-based interferometers will be introduced. The FPGA-based Phasemeter leverages fast ADCs to obtain the three-frequency signals from VDI planar-diode Mixers, and realizes digital filters and an FFT algorithm in FPGA to provide real-time, high precision electron density output. Implementation of the Phasemeter will be helpful for the future plasma real-time feedback control in long-pulse discharge.

  7. An Update on ConSys Including a New LabVIEW FPGA Based LLRF System

    DEFF Research Database (Denmark)

    Worm, Torben; Nielsen, Jørgen S.

    . This system use a National Instruments NI-PCIe7852R DAQ card, which includes an on-board FPGA and are hosted in a standard PC. The fast (50 kHz) amplitude loop has been implemented on the FPGA, whereas the slower tuning and phase loops are implemented in the real-time system. An operator interface including......ConSys, the Windows based control system for ASTRID and ASTRID2, is now a mature system, having been in operation for more than 15 years. All the standard programs (Console, plots, data logging, control setting store/restore etc.) are fully general and are configured through a database or file. Con......Sys is a standard publisher/subscriber system, where all nodes can act both as client and server. One very strong feature is the easy ability to make virtual devices (devices which do not depend on hardware directly, but combine hardware parameters.) For ASTRID2 a new LabVIEW based Low-Level RF system has been made...

  8. Porting VIRTEX4 data acquisition design to SPARTAN6 FPGA

    International Nuclear Information System (INIS)

    Suetoe, J.; Hegyesi, G.

    2012-01-01

    Complete text of publication follows. The Atomki's Virtex 4 based 4 channel data acquisition card (LIR) card was used in many applications (miniPET-II, miniPET-III, data acquisition system for the multichannel plate installed at the ECR lab). The goal of the work was to improve the LIR using a higher performance FPGA (Spartan6 Trenz module). The Trenz module based system also supports ADC channels up to 16 channels. This work also implied the porting of the Virtex4 based VHDL code to Spartan 6. Further advantage of the proposed system, besides the improvement in the number of ADC channels, that the Spartan6 FPGA is able to run more complex digital signal processing algorithms than the Virtex 4 FPGA. Easy access to the control parameters (via serial interface or Ethernet), flexibility and high performance were considered during the development. SPARTAN6 FPGA based data acquisition provides more facilities than the VIRTEX4 based. SPARTAN6 is a newer generation of XILINX’s FPGAs, which excellent into the high-speed data acquisition. We ported the HDL code, which runs on LIR module (VIRTEX4 based), to the Trenz module (SPARTAN6 based). The main parts of the whole program code are the command line interpreter, GMII interface, DHCP process, ARP process and the data read out. Those parts were implemented by picoblaze embedded system. Figure 1 shows the command line interpreter process in the Hyper Terminal. The command line interpreter communicates with the PC via serial port. In addition, the AdamIOSetting software also use the serial communication, which was created to the VIRTEX FPGA based data collector. In the Wireshark network analyzer software we examined the DHCP and ARP process and using the AdamIOSettings software we tested the data read out from the flash memory of FPGA board. Figure 2 shows the AdamIOSettings program. Acknowledgements. This work was supported by the ENIAC CSI Project (No.120209).

  9. Control rod homogenization in heterogeneous sodium-cooled fast reactors

    International Nuclear Information System (INIS)

    Andersson, Mikael

    2016-01-01

    The sodium-cooled fast reactor is one of the candidates for a sustainable nuclear reactor system. In particular, the French ASTRID project employs an axially heterogeneous design, proposed in the so-called CFV (low sodium effect) core, to enhance the inherent safety features of the reactor. This thesis focuses on the accurate modeling of the control rods, through the homogenization method. The control rods in a sodium-cooled fast reactor are used for reactivity compensation during the cycle, power shaping, and to shutdown the reactor. In previous control rod homogenization procedures, only a radial description of the geometry was implemented, hence the axially heterogeneous features of the CFV core could not be taken into account. This thesis investigates the different axial variations the control rod experiences in a CFV core, to determine the impact that these axial environments have on the control rod modeling. The methodology used in this work is based on previous homogenization procedures, the so-called equivalence procedure. The procedure was newly implemented in the PARIS code system in order to be able to use 3D geometries, and thereby be take axial effects into account. The thesis is divided into three parts. The first part investigates the impact of different neutron spectra on the homogeneous control-rod cross sections. The second part investigates the cases where the traditional radial control-rod homogenization procedure is no longer applicable in the CFV core, which was found to be 5-10 cm away from any material interface. In the third part, based on the results from the second part, a 3D model of the control rod is used to calculate homogenized control-rod cross sections. In a full core model, a study is made to investigate the impact these axial effects have on control rod-related core parameters, such as the control rod worth, the capture rates in the control rod, and the power in the adjacent fuel assemblies. All results were compared to a Monte

  10. Design and implementation of universal mathematical library supporting algorithm development for FPGA based systems in high energy physics experiments

    International Nuclear Information System (INIS)

    Jalmuzna, W.

    2006-02-01

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short Xray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF system in VUV FEL experiment based on modern FPGA chips It is being developed by ELHEP group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryomodule in the experiment. The device can be also used as the simulator of the cavity and testbench for other devices. Flexibility and computation power of this device allow implementation of fast mathematical algorithms. This paper describes the concept, implementation and tests of universal mathematical library for FPGA algorithm implementation. It consists of many useful components such as IQ demodulator, division block, library for complex and floating point operations, etc. It is able to speed up implementation time of many complicated algorithms. Library have already been tested using real accelerator signals and the performance achieved is satisfactory. (Orig.)

  11. Design and implementation of universal mathematical library supporting algorithm development for FPGA based systems in high energy physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Jalmuzna, W.

    2006-02-15

    The X-ray free-electron laser XFEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short Xray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new perspectives for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated for LLRF system in VUV FEL experiment based on modern FPGA chips It is being developed by ELHEP group in Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller for stabilizing the vector sum of fields in cavities of one cryomodule in the experiment. The device can be also used as the simulator of the cavity and testbench for other devices. Flexibility and computation power of this device allow implementation of fast mathematical algorithms. This paper describes the concept, implementation and tests of universal mathematical library for FPGA algorithm implementation. It consists of many useful components such as IQ demodulator, division block, library for complex and floating point operations, etc. It is able to speed up implementation time of many complicated algorithms. Library have already been tested using real accelerator signals and the performance achieved is satisfactory. (Orig.)

  12. A fast PID controller Design for Modern PLC for Process Control Application

    International Nuclear Information System (INIS)

    Mirza, A.; Nafis, A.; Anees, R.M.; Idris, S.

    2004-01-01

    PID is the most widely used control scheme in the process industry. Pill controllers are utilized for the control of such varied parameters as pressure, flow, temperature, etc. One characteristic of these parameters is that they posses slow dynamics. Most of the available digital controllers can manipulate only a single parameter- multiple controllers are required for control of more than one parameter. The Fast PID Controller for Modem PLC (Programmable Logic Controller) developed by the authors, provides control of several parameters at a time (through a single Pill control element), enhanced programmability including variable sampling period, parameter monitoring and data storage, which may be easily implemented in a PLC. (author)

  13. FAST

    DEFF Research Database (Denmark)

    Zuidmeer-Jongejan, Laurian; Fernandez-Rivas, Montserrat; Poulsen, Lars K.

    2012-01-01

    ABSTRACT: The FAST project (Food Allergy Specific Immunotherapy) aims at the development of safe and effective treatment of food allergies, targeting prevalent, persistent and severe allergy to fish and peach. Classical allergen-specific immunotherapy (SIT), using subcutaneous injections with aqu...

  14. ITER Fast Plant System Controller prototype based on PXIe platform

    International Nuclear Information System (INIS)

    Ruiz, M.; Vega, J.; Castro, R.; Sanz, D.; López, J.M.; Arcas, G. de; Barrera, E.; Nieto, J.; Gonçalves, B.; Sousa, J.; Carvalho, B.; Utzel, N.; Makijarvi, P.

    2012-01-01

    Highlights: ► Implementation of Fast Plant System Controller (FPSC) for ITER CODAC. ► Efficient data acquisition and data movement using EPICS. ► Performance of PCIe technologies in the implementation of FPSC. - Abstract: The ITER Fast Plant System Controller (FPSC) is based on embedded technologies. The FPSC will be devoted to both data acquisition tasks (sampling rates higher than 1 kHz) and control purposes (feedback loop actuators). Some of the essential requirements of these systems are: (a) data acquisition and data preprocessing; (b) interfacing with different networks and high speed links (Plant Operation Network, timing network based on IEEE1588, synchronous data transference and streaming/archiving networks); and (c) system setup and operation using EPICS (Experimental Physics and Industrial Control System) process variables. CIEMAT and UPM have implemented a prototype of FPSC using a PXIe (PCI eXtension for Instrumentation) form factor in a R and D project developed in two phases. The paper presents the main features of the two prototypes developed that have been named alpha and beta. The former was implemented using LabVIEW development tools as it was focused on modeling the FPSC software modules, using the graphical features of LabVIEW applications, and measuring the basic performance in the system. The alpha version prototype implements data acquisition with time-stamping, EPICS monitoring using waveform process variables (PVs), and archiving. The beta version prototype is a complete IOC implemented using EPICS with different software functional blocks. These functional blocks are integrated and managed using an ASYN driver solution and provide the basic functionalities required by ITER FPSC such as data acquisition, data archiving, data pre-processing (using both CPU and GPU) and streaming.

  15. Development of FPGA-based safety-related I and C systems

    Energy Technology Data Exchange (ETDEWEB)

    Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S. [08, Shinsugita-cho, Isogo-ku, Yokohama 235-8523 (Japan); 1, Toshiba-cho, Fuchu, Tokyo 183-8511 (Japan)

    2006-07-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  16. Verification of FPGA-based NPP I and C systems. General approach and techniques

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Reva, Lubov; Siora, Alexander

    2011-01-01

    This paper presents a general approach and techniques for design and verification of Field Programmable Gates Arrays (FPGA)-based Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP). Appropriate regulatory documents used for I and C systems design, development, verification and validation (V and V) are discussed considering the latest international standards and guidelines. Typical development and V and V processes of FPGA electronic design for FPGA-based NPP I and C systems are presented. Some safety-related features of implementation process are discussed. Corresponding development artifacts, related to design and implementation activities are outlined. An approach to test-based verification of FPGA electronic design algorithms, used in FPGA-based reactor trip systems is proposed. The results of application of test-based techniques for assessment of FPGA electronic design algorithms for reactor trip system (RTS) produced by Research and Production Corporation (RPC) 'Radiy' are presented. Some principles of invariant-oriented verification for FPGA-based safety-critical systems are outlined. (author)

  17. The new FPGA based discriminator board for the CBELSA/TAPS experiment

    Energy Technology Data Exchange (ETDEWEB)

    Fix, Eugenia [HISKP, Universitaet Bonn (Germany); Collaboration: CBELSA/TAPS-Collaboration

    2016-07-01

    The Crystal Barrel calorimeter at ELSA, which consists of 1320 CsI(Tl) crystals has been upgraded by a new Avalanche Photo Diode (APD) crystal readout.The APD readout electronics will provide a fast trigger signal down to 10 MeV energy deposit per single crystal. The processing of these trigger signals requires the development of a previously not existent timing branch of the readout chain of the Crystal Barrel calorimeter. Core component of the timing branch is a newly developed, FPGA based discriminator board. Its firmware contains modules for time to digital conversion, rise time compensation and parts of a cluster finder. In addition the reference voltages and discriminator thresholds are controlled and monitored. This poster presents the design and the achievable accuracy of the new discriminator.

  18. Desain Protokol Suara Sebagai Pengendali Dalam Smart Home Menggunakan FPGA

    Directory of Open Access Journals (Sweden)

    Barlian Henryranu Prasetio

    2017-05-01

    Smart home is a system that uses computers and information technology to control home-like equipment such as windows and lights. The system can be a simple control system to a complex system. Computer / microcontroller based on internet/ethernet network equipped with intelligent system and automation system so as to make home to work automatically. Many computer devices / microcontrollers that can be implemented as a controller in the smart home. Smart home control system in this study using Xilinx xpartan-3e that controls the equipment in the house through LAN (Local Area Networking. This control system communicates using broadcast voice on the local network. The Controller System is designed to be able to transmit a voice signal packet from the microphone input and then send it using the ethernet protocol in the home local network using the FPGA. The FPGA is programmed to transmit and encode data packets, converting digital data into analog data to be able to control the equipment in the home. From the simulation test results using ISIM, it is seen that the system works in realtime. Keywords: smart home, voice, fpga, control

  19. Fast, controlled stepping drive for D2 filament ejection

    International Nuclear Information System (INIS)

    Amenda, W.; Lang, R.S.

    1985-01-01

    Centrifugal pellet injectors are required to refuel plasma machines. The pellet feed into the centrifuge should, if possible, be direct to keep the exit angle divergence small. The D 2 filaments used are first stored in a cryostat and then rapidly transported to the intake region of the centrifuge. An intermittent drive for fast, controlled ejection of D 2 filaments is described here. Mean filament speed of up to 0.6 m/s per step (1.2 mm) are achieved for the centrifugal pellet injector which refuels the ASDEX tokamak at Garching. The timing of the (81) step shifts can be synchronized with the rotor motion. The drive allows rates of up to 50 pellets per second. The drive method also seems to be suitable for direct feeding of other known centrifugal pellet injectors

  20. Instrumentation and control of the fast breeder reactors

    International Nuclear Information System (INIS)

    Juengst, U.

    1982-01-01

    Generally the Liquid Metal Fast Breeder Reactor (LMFBR) in comparison to the Leight Water Reactors hasn't exceptionally different requirements to the instrumentation and control systems. There fore the paper restricts itself to outline the peculiarities of LMFBR's exemplified at the design of the German Breeder SNR-300 beeing under construction. The special sodium instrumentation for temperature level, flow and pressure in the main systems is described. The automatic control system enabled the plant to follow the bad demand of the grid immidiately. The nuclear power production itself is stabilized by inherent coefficients of the core. An exceptional high reliability of the shut down systems is necessary; there fore all LMFBR's have two completely independant and diverse shut down systems. In the SNR-300 also the control of decay heat removal and the active safety systems for enclosure of radioactivity are distributed to two independent and diverse plant protection systems (PPS) so that the first system covered the accidents due to internal events and the second systems managed the external events such as earthquake and aircraft crash. (orig.)

  1. Estimation of channel impulse response and FPGA simulation

    Directory of Open Access Journals (Sweden)

    YU Longjie

    2015-02-01

    Full Text Available Wideband code division multiple access (WCDMA is a 3G wireless communication network.The common pilot channel in downlink of WCDMA provides an effective method to estimate the channel impulse response.In this paper,universal software radio peripheral (USRP is utilized to sample and process WCDMA signal which is emitted by China Unicom base station.Firstly,the received signal is pre-processed with filtering and down-sampling.Secondly,fast algorithm of WCDMA cell search is fulfilled.Thirdly,frequency shift caused by USRP′s crystal oscillator is checked and compensated.Eventually,channel impulse response is estimated.In this paper,MATLAB is used to describe the above algorithm and field programmable gate array (FPGA is used to simulate algorithm.In the process of simulation,pipeline and IP core multiplexing are introduced.In the case of 32 MHz clock frequency,FPGA simulation time is 80.861 ms.Simulation results show that FPGA is able to estimate the channel impulse response quickly and accurately with less hardware resources.

  2. A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

    Directory of Open Access Journals (Sweden)

    Gabriel J. García

    2014-03-01

    Full Text Available The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc., reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

  3. A survey on FPGA-based sensor systems: towards intelligent and reconfigurable low-power sensors for computer vision, control and signal processing.

    Science.gov (United States)

    García, Gabriel J; Jara, Carlos A; Pomares, Jorge; Alabdo, Aiman; Poggi, Lucas M; Torres, Fernando

    2014-03-31

    The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

  4. The MCD circuit based on FPGA

    International Nuclear Information System (INIS)

    Vu Quoc Trong

    2003-01-01

    Two MCD circuits based on different FPGA are presented as results of the study of the MAX+PLUS II software and FPGA devices. An external memory like 62256 and programmed EPM7064S will be able to form a MCD with 8 kilo channels. (NHA)

  5. Fast calculation of the `ILC norm' in iterative learning control

    Science.gov (United States)

    Rice, Justin K.; van Wingerden, Jan-Willem

    2013-06-01

    In this paper, we discuss and demonstrate a method for the exploitation of matrix structure in computations for iterative learning control (ILC). In Barton, Bristow, and Alleyne [International Journal of Control, 83(2), 1-8 (2010)], a special insight into the structure of the lifted convolution matrices involved in ILC is used along with a modified Lanczos method to achieve very fast computational bounds on the learning convergence, by calculating the 'ILC norm' in ? computational complexity. In this paper, we show how their method is equivalent to a special instance of the sequentially semi-separable (SSS) matrix arithmetic, and thus can be extended to many other computations in ILC, and specialised in some cases to even faster methods. Our SSS-based methodology will be demonstrated on two examples: a linear time-varying example resulting in the same ? complexity as in Barton et al., and a linear time-invariant example where our approach reduces the computational complexity to ?, thus decreasing the computation time, for an example, from the literature by a factor of almost 100. This improvement is achieved by transforming the norm computation via a linear matrix inequality into a check of positive definiteness - which allows us to further exploit the almost-Toeplitz properties of the matrix, and additionally provides explicit upper and lower bounds on the norm of the matrix, instead of the indirect Ritz estimate. These methods are now implemented in a MATLAB toolbox, freely available on the Internet.

  6. An Optimal Control Modification to Model-Reference Adaptive Control for Fast Adaptation

    Science.gov (United States)

    Nguyen, Nhan T.; Krishnakumar, Kalmanje; Boskovic, Jovan

    2008-01-01

    This paper presents a method that can achieve fast adaptation for a class of model-reference adaptive control. It is well-known that standard model-reference adaptive control exhibits high-gain control behaviors when a large adaptive gain is used to achieve fast adaptation in order to reduce tracking error rapidly. High gain control creates high-frequency oscillations that can excite unmodeled dynamics and can lead to instability. The fast adaptation approach is based on the minimization of the squares of the tracking error, which is formulated as an optimal control problem. The necessary condition of optimality is used to derive an adaptive law using the gradient method. This adaptive law is shown to result in uniform boundedness of the tracking error by means of the Lyapunov s direct method. Furthermore, this adaptive law allows a large adaptive gain to be used without causing undesired high-gain control effects. The method is shown to be more robust than standard model-reference adaptive control. Simulations demonstrate the effectiveness of the proposed method.

  7. SRF cavity testing using a FPGA Self Excited Loop

    CERN Document Server

    Ben-Zvi, Ilan

    2018-01-01

    This document provides a detailed description of procedures for very-high precision calibration and testing of superconducting RF cavities using digital Low-Level RF (LLRF) electronics based on Field Programmable Gate Arrays (FPGA). The use of a Self-Excited Loop with an innovative procedure for fast turn-on allows the measurement of the forward, reflected and transmitted power from a single port of the directional coupler in front of the cavity, thus eliminating certain measurement errors. Various procedures for measuring the quality factor as a function of cavity fields are described, including a single RF pulse technique. Errors are estimated for the measurements.

  8. FPGA based, DSP integrated, 8-channel SIMCON, ver. 3.0. Initial results for 8-channel algorithm

    Energy Technology Data Exchange (ETDEWEB)

    Giergusiewicz, W.; Koprek, W.; Jalmuzna, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

    2005-07-01

    The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the VUV-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layer, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACC1 module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0. encouraged us to enter the design of SIMCON 3.1. possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0. is a modular solution, while SIMCON 3.1. will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one, after branching off in this version of the Simcon, will be continued. (orig.)

  9. Compact wireless control network protocol with fast path switching

    Directory of Open Access Journals (Sweden)

    Yasutaka Kawamoto

    2017-08-01

    Full Text Available Sensor network protocol stacks require the addition or adjustment of functions based on customer requirements. Sensor network protocols that require low delay and low packet error rate (PER, such as wireless control networks, often adopt time division multiple access (TDMA. However, it is difficult to add or adjust functions in protocol stacks that use TDMA methods. Therefore, to add or adjust functions easily, we propose NES-SOURCE, a compact wireless control network protocol with a fast path-switching function. NES-SOURCE is implemented using carrier sense multiple access/collision avoidance (CSMA/CA rather than TDMA. Wireless control networks that use TDMA prevent communication failure by duplicating the communication path. If CSMA/CA networks use duplicate paths, collisions occur frequently, and communication will fail. NES-SOURCE switches paths quickly when communication fails, which reduces the effect of communication failures. Since NES-SOURCE is implemented using CSMA/CA rather than TDMA, the implementation scale is less than one-half that of existing network stacks. Furthermore, since NES-SOURCE’s code complexity is low, functions can be added or adjusted easily and quickly. Communication failures occur owing to changes in the communication environment and collisions. Experimental results demonstrate that the proposed NES-SOURCE’s path-switching function reduces the amount of communication failures when the communication environment changes owing to human movement and others. Furthermore, we clarify the relationships among the probability of a changing communication environment, the collision occurrence rate, and the PER of NES-SOURCE.

  10. Intermittent fasting: A “new” historical strategy for controlling seizures?

    Science.gov (United States)

    Hartman, Adam L.; Rubenstein, James E.; Kossoff, Eric H.

    2013-01-01

    Summary In antiquity, fasting was a treatment for epilepsy and a rationale for the ketogenic diet (KD). Preclinical data indicate the KD and intermittent fasting do not share identical anticonvulsant mechanisms. We implemented an intermittent fasting regimen in six children with an incomplete response to a KD. Three patients adhered to the combined intermittent fasting/KD regimen for 2 months and four had transient improvement in seizure control, albeit with some hunger-related adverse reactions. PMID:23206889

  11. Intermittent fasting: A “new” historical strategy for controlling seizures?

    OpenAIRE

    Hartman, Adam L.; Rubenstein, James E.; Kossoff, Eric H.

    2012-01-01

    In antiquity, fasting was a treatment for epilepsy and a rationale for the ketogenic diet (KD). Preclinical data indicate the KD and intermittent fasting do not share identical anticonvulsant mechanisms. We implemented an intermittent fasting regimen in six children with an incomplete response to a KD. Three patients adhered to the combined intermittent fasting/KD regimen for 2 months and four had transient improvement in seizure control, albeit with some hunger-related adverse reactions.

  12. Radiation control and safety of fast reactor; Radijaciona kontrola i sigurnost postrojenja sa brzim reaktorom

    Energy Technology Data Exchange (ETDEWEB)

    Pesic, M; Antic, D [Boris Kidric Institute of Nuclear Sciences Vinca, Belgrade (Yugoslavia)

    1983-07-01

    The fundamental activities for safeguard of radiation control and safety and the necessary staff for them for fast reactor plant are shown. The basic systems for the plant radiation control are counted, especially with regards to poisoning of some fuel materials. The particular characteristics of the plant radiation control determined by the fast reactor are pointed out. (author)

  13. FPGA Authentication Methods.

    Energy Technology Data Exchange (ETDEWEB)

    Brotz, Jay Kristoffer [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Hymel, Ross W [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Punnoose, Ratish J. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Mannos, Tom [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Grant, Neil [Atomic Weapons Establishment (AWE), Berkshire (United Kingdom); Evans, Neil [Atomic Weapons Establishment (AWE), Berkshire (United Kingdom)

    2017-05-01

    One of the greatest challenges facing designers of equipment to be used in a nuclear arms control treaty is how to convince the other party in the treaty to trust its results and functionality. Whether the host provides equipment meant to prove treaty obligations and the inspector needs to gain that trust (commonly referred to as authentication), or the inspector provides this equipment and the host needs to gain this trust (commonly considered to be included in certification), one party generally has higher confidence in the equipment at the start of a treaty regime and the other party needs to gain that confidence prior to use. While we focus on authentication in this document—that is, the inspector gaining confidence in host-provided equipment—our conclusions will likely apply to host certification of inspector-provided equipment.

  14. The digital backend of FAST

    Science.gov (United States)

    Yu, Xinying; Zhang, Xia; Duan, Ran; li, di; Hao, Jie

    2015-08-01

    The receiver system is an important part of FAST (Five-hundred-meter Aperture Spherical Radio Telescope) and plays a key role in determining the performance of the telescope.This research covers three major aspects: establishment of system synchronization and timestamps, field-programmable gate array (FPGA)-based data transmission and analysis, and the rear receiver monitoring system. We intend to combine the use of GPS and a frequency standard instrument with network access to Unix timestamps to form actual timestamps. The data are stored with timestamps that contain integer and fractional seconds to be precise and headers, which are primarily intended to distinguish the data from each other.The data analysis procedures includes converting the timestamp information to real-time information, and merging the 8 channels’ data conversion results into frequency and energy data using corresponding conversion formulae. We must develop tailored monitoring software for the FAST receiver to customize the data format and perform data transmission. Signals on the front-end and back-end of the receiver can be monitored and controlled by adjusting the parameters on the software to increase the flexibility of the receiver.Most operations are performed on FPGA board, which can be shown from the figure, including the analog-to-digital conversion (ADC), fast Fourier transform (FFT), and pulse per second (1PPS) and Unix timestamp access operations.When analog data arrive, we initialize two ADCs at a sampling rate of 3Gsps, following by 8-channel FFT parallel processing.In collaboration with the Institute of Automation, we have developed a custom FPGA board which we call "FDB"("FAST Digital Backend"). The board is integrated with two Virtex-6 and one Virtex-5 high-speed Xilinx chips. The main function of the two Virtex-6 devices is to run the FFT and PFB programs, whereas the main function of Virtex-5 is configuration of the board.This research is indispensable for realizing the

  15. FPGA Congestion-Driven Placement Refinement

    Energy Technology Data Exchange (ETDEWEB)

    Vicente de, J.

    2005-07-01

    The routing congestion usually limits the complete proficiency of the FPGA logic resources. A key question can be formulated regarding the benefits of estimating the congestion at placement stage. In the last years, it is gaining acceptance the idea of a detailed placement taking into account congestion. In this paper, we resort to the Thermodynamic Simulated Annealing (TSA) algorithm to perform a congestion-driven placement refinement on the top of the common Bounding-Box pre optimized solution. The adaptive properties of TSA allow the search to preserve the solution quality of the pre optimized solution while improving other fine-grain objectives. Regarding the cost function two approaches have been considered. In the first one Expected Occupation (EO), a detailed probabilistic model to account for channel congestion is evaluated. We show that in spite of the minute detail of EO, the inherent uncertainty of this probabilistic model impedes to relieve congestion beyond the sole application of the Bounding-Box cost function. In the second approach we resort to the fast Rectilinear Steiner Regions algorithm to perform not an estimation but a measurement of the global routing congestion. This second strategy allows us to successfully reduce the requested channel width for a set of benchmark circuits with respect to the widespread Versatile Place and Route (VPR) tool. (Author) 31 refs.

  16. Multi-Softcore Architecture on FPGA

    Directory of Open Access Journals (Sweden)

    Mouna Baklouti

    2014-01-01

    Full Text Available To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication.

  17. FPGA applications for single dish activity at Medicina radio telescopes

    Science.gov (United States)

    Bartolini, M.; Naldi, G.; Mattana, A.; Maccaferri, A.; De Biaggi, M.

    FPGA technologies are gaining major attention in the recent years in the field of radio astronomy. At Medicina radio telescopes, FPGAs have been used in the last ten years for a number of purposes and in this article we will take into exam the applications developed and installed for the Medicina Single Dish 32m Antenna: these range from high performance digital signal processing to instrument control developed on top of smaller FPGAs.

  18. Design of a synthesizer for magnetic resonance equipment using FPGA

    International Nuclear Information System (INIS)

    Sonora A

    2006-01-01

    This paper exposes the design of a direct digital synthesizer in FPGA. This desing can generate a sine wave output up to 4MHZ with 3,33 mHz of precision. The frequency is set by 32bit word of phase increment in 350ns. The desing was made for Magnetic Resonance scanners and uses a 97% of logic resources of device. Functions for the synthesizer control are implemented in the same chip

  19. Wire Position Monitoring with FPGA based Electronics

    International Nuclear Information System (INIS)

    Eddy, N.; Lysenko, O.

    2009-01-01

    collects the WPM data and transmits it to the VME controller. The VME front-end processes the raw data to calculate positions and perform FFT. It is also provides the raw data to LabView running on a PC upon request. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is connected with realization of average and decimation filter algorithm in the integrator operation in the FPGA. The second is connected with development of alternative tool for WPM measurements in the PC. We will discuss how these modifications were performed and test results of a new design.

  20. Using Simulated Partial Dynamic Run-Time Reconfiguration to Share Embedded FPGA Compute and Power Resources across a Swarm of Unpiloted Airborne Vehicles

    Directory of Open Access Journals (Sweden)

    Kearney David

    2007-01-01

    Full Text Available We show how the limited electrical power and FPGA compute resources available in a swarm of small UAVs can be shared by moving FPGA tasks from one UAV to another. A software and hardware infrastructure that supports the mobility of embedded FPGA applications on a single FPGA chip and across a group of networked FPGA chips is an integral part of the work described here. It is shown how to allocate a single FPGA's resources at run time and to share a single device through the use of application checkpointing, a memory controller, and an on-chip run-time reconfigurable network. A prototype distributed operating system is described for managing mobile applications across the swarm based on the contents of a fuzzy rule base. It can move applications between UAVs in order to equalize power use or to enable the continuous replenishment of fully fueled planes into the swarm.

  1. Design Verification Enhancement of FPGA-based Plant Protection System Trip Logics for Nuclear Power Plant

    International Nuclear Information System (INIS)

    Ahmed, Ibrahim; Jung, Jae Cheon; Heo, Gyun Young

    2016-01-01

    As part of strengthening the application of FPGA technology and find solution to its challenges in NPPs, international atomic energy agency (IAEA) has indicated interest by joining sponsorship of Topical Group on FPGA Applications in NPPs (TG-FAN) that hold meetings up to 7th times until now, in form of workshop (International workshop on the application of FPGAs in NPPs) annually since 2008. The workshops attracted a significant interest and had a broad representation of stakeholders such as regulators, utilities, research organizations, system designers, and vendors, from various countries that converge to discuss the current issues regarding instrumentation and control (I and C) systems as well as FPGA applications. Two out of many technical issues identified by the group are lifecycle of FPGA-based platforms, systems, and applications; and methods and tools for V and V. Therefore, in this work, several design steps that involved the use of model-based systems engineering process as well as MATLAB/SIMULINK model which lead to the enhancement of design verification are employed. The verified and validated design output works correctly and effectively. Conclusively, the model-based systems engineering approach and the structural step-by-step design modeling techniques including SIMULINK model utilized in this work have shown how FPGA PPS trip logics design verification can be enhanced. If these design approaches are employ in the design of FPGA-based I and C systems, the design can be easily verified and validated

  2. Fast control and data acquisition in the neutral beam test facility

    International Nuclear Information System (INIS)

    Luchetta, A.; Manduchi, G.; Taliercio, C.

    2014-01-01

    Highlights: • The paper describes the fast control and data acquisition in the ITER neutral beam test facility. • The usage of real time control in ion beam generation and extraction is proposed. • Real time management of breakdowns is described. • The implementation of event-driven data acquisition is reported. - Abstract: Fast control and data acquisition are required in the ion source test bed of the ITER neutral beam test facility, referred to as SPIDER. Fast control will drive the operation of the power supply systems with particular reference to special asynchronous events, such as the breakdowns. These are short-circuits among grids or between grids and vessel that can occur repeatedly during beam operation. They are normal events and, as such, they will be managed by the fast control system. Cycle time associated to such fast control is down to hundreds of microseconds. Fast data acquisition is required when breakdowns occur. Event-driven data acquisition is triggered in real time by fast control at the occurrence of each breakdown. Pre- and post-event samples are acquired, allowing capturing information on transient phenomena in a whole time-window centered on the event. Sampling rate of event-driven data acquisition is up to 5 MS/s. Fast data acquisition may also be independent of breakdowns as in the case of the cavity ring-down spectroscopy where data chunks are acquired at 100 MS/s in bursts of 1.5 ms every 100 ms and are processed in real time to produce derived measurements. The paper after the description of the SPIDER fast control and data acquisition application will report the system design based on commercially available hardware and the MARTe and MDSplus software frameworks. The results obtained by running a full prototype of the fast control and data acquisition system are also reported and discussed. They demonstrate that all SPIDER fast control and data acquisition requirements can be met in the prototype solution

  3. Fast control and data acquisition in the neutral beam test facility

    Energy Technology Data Exchange (ETDEWEB)

    Luchetta, A., E-mail: adriano.luchetta@igi.cnr.it; Manduchi, G.; Taliercio, C.

    2014-05-15

    Highlights: • The paper describes the fast control and data acquisition in the ITER neutral beam test facility. • The usage of real time control in ion beam generation and extraction is proposed. • Real time management of breakdowns is described. • The implementation of event-driven data acquisition is reported. - Abstract: Fast control and data acquisition are required in the ion source test bed of the ITER neutral beam test facility, referred to as SPIDER. Fast control will drive the operation of the power supply systems with particular reference to special asynchronous events, such as the breakdowns. These are short-circuits among grids or between grids and vessel that can occur repeatedly during beam operation. They are normal events and, as such, they will be managed by the fast control system. Cycle time associated to such fast control is down to hundreds of microseconds. Fast data acquisition is required when breakdowns occur. Event-driven data acquisition is triggered in real time by fast control at the occurrence of each breakdown. Pre- and post-event samples are acquired, allowing capturing information on transient phenomena in a whole time-window centered on the event. Sampling rate of event-driven data acquisition is up to 5 MS/s. Fast data acquisition may also be independent of breakdowns as in the case of the cavity ring-down spectroscopy where data chunks are acquired at 100 MS/s in bursts of 1.5 ms every 100 ms and are processed in real time to produce derived measurements. The paper after the description of the SPIDER fast control and data acquisition application will report the system design based on commercially available hardware and the MARTe and MDSplus software frameworks. The results obtained by running a full prototype of the fast control and data acquisition system are also reported and discussed. They demonstrate that all SPIDER fast control and data acquisition requirements can be met in the prototype solution.

  4. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  5. Control Design and Digital Implementation of a Fast 2-Degree-of-Freedom Translational Optical Image Stabilizer for Image Sensors in Mobile Camera Phones.

    Science.gov (United States)

    Wang, Jeremy H-S; Qiu, Kang-Fu; Chao, Paul C-P

    2017-10-13

    This study presents design, digital implementation and performance validation of a lead-lag controller for a 2-degree-of-freedom (DOF) translational optical image stabilizer (OIS) installed with a digital image sensor in mobile camera phones. Nowadays, OIS is an important feature of modern commercial mobile camera phones, which aims to mechanically reduce the image blur caused by hand shaking while shooting photos. The OIS developed in this study is able to move the imaging lens by actuating its voice coil motors (VCMs) at the required speed to the position that significantly compensates for imaging blurs by hand shaking. The compensation proposed is made possible by first establishing the exact, nonlinear equations of motion (EOMs) for the OIS, which is followed by designing a simple lead-lag controller based on established nonlinear EOMs for simple digital computation via a field-programmable gate array (FPGA) board in order to achieve fast response. Finally, experimental validation is conducted to show the favorable performance of the designed OIS; i.e., it is able to stabilize the lens holder to the desired position within 0.02 s, which is much less than previously reported times of around 0.1 s. Also, the resulting residual vibration is less than 2.2-2.5 μm, which is commensurate to the very small pixel size found in most of commercial image sensors; thus, significantly minimizing image blur caused by hand shaking.

  6. Irradiation test of FPGA for BES III

    International Nuclear Information System (INIS)

    Chen Yixin; Liang Hao; Xue Jundong; Liu Baoying; Liu Qiang; Yu Xiaoqi; Zhou Yongzhao; Hou Long

    2005-01-01

    The irradiation effect of FPGA, applied in Front-end Electronics for experiments of High-Energy Physics, is a serious problem. The performance of FPGA, used in the front-end card of Muon Counters of BES III project, needs to be evaluated under irradiation. SEUs on Altera ACEX 1K FPGA, observed in the experiment under the irradiation of γ ray, 14 and 2.5 MeV neutrons, was investigated. The authors calculated involved cross-section and provided reasonable analysis and evaluation for the result of the experiment. The conclusion about feasibility of applying ACEX 1K FPGA in the front-end card of the readout system of Muon Counters for BES III was given. (authors)

  7. Fast Nonconvex Model Predictive Control for Commercial Refrigeration

    DEFF Research Database (Denmark)

    Hovgaard, Tobias Gybel; Larsen, Lars F. S.; Jørgensen, John Bagterp

    2012-01-01

    in fewer than 5 or so iterations. We employ a fast convex quadratic programming solver to carry out the iterations, which is more than fast enough to run in real-time. We demonstrate our method on a realistic model, with a full year simulation, using real historical data. These simulations show substantial...... cost savings, and reveal how the method exhibits sophisticated response to real-time variations in electricity prices. This demand response is critical to help balance real-time uncertainties associated with large penetration of intermittent renewable energy sources in a future smart grid....

  8. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    International Nuclear Information System (INIS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Cicero, F. Lo; Lonardo, A; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Simula, F.; Tosoratto, L.; Vicini, P.; Rossetti, D.

    2015-01-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology.The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network.The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols.Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design. (paper)

  9. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    Science.gov (United States)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

    2015-12-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

  10. Algorithmic strategies for FPGA-based vision

    OpenAIRE

    Lim, Yoong Kang

    2016-01-01

    As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

  11. Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support

    Directory of Open Access Journals (Sweden)

    Burhan Khurshid

    2015-05-01

    Full Text Available Modern Field Programmable Gate Arrays (FPGA are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC primarily because of the low Non-recurring Engineering (NRE costs associated with FPGA platforms. This has prompted FPGA vendors to improve the capacity and flexibility of the underlying primitive fabric and include specialized macro support and intellectual property (IP cores in their offerings. However, most of the work related to FPGA implementations does not take full advantage of these offerings. This is primarily because designers rely mainly on the technology-independent optimization to enhance the performance of the system and completely neglect the speed-up that is achievable using these embedded primitives and macro support. In this paper, we consider the technology-dependent optimization of fixed-point bit-parallel multipliers by carrying out their implementations using embedded primitives and macro support that are inherent in modern day FPGAs. Our implementation targets three different FPGA families viz. Spartan-6, Virtex-4 and Virtex-5. The implementation results indicate that a considerable speed up in performance is achievable using these embedded FPGA resources.

  12. Effect of Ramadan fasting on glycemic control in patients with Type 2 diabetes.

    Science.gov (United States)

    Norouzy, A; Mohajeri, S M R; Shakeri, S; Yari, F; Sabery, M; Philippou, E; Varasteh, A-R; Nematy, M

    2012-09-01

    Although Muslim patients with Type 2 diabetes may be exempt from fasting during Ramadan for medical reasons, a high proportion of them fast. To investigate the association between Ramadan fasting and glycemic control in patients with Type 2 diabetes. A prospective cohort clinical trial was designed. Eighty-eight patients with Type 2 diabetes (45 male, 43 female, age 51±10 yr) who opted to fast for at least 10 days during the month of Ramadan were recruited. Fasting blood samples were taken at the beginning and end of Ramadan, and 1 month after Ramadan, to assess fasting blood glucose (FBG), fasting insulin, full blood count, glycated hemoglobin (HbA(1c)) and fasting lipid profile. Insulin resistance was estimated using the homeostatic model assessment. Anthropometrics and blood pressure were also measured. There was a significant deterioration in FBG and HbA(1c) (p=0.002 and p≤0.001, respectively) and significant improvements in HDL and LDL cholesterol and body mass index after Ramadan (pRamadan (9.4±2% at the end of Ramadan vs 8.4±2.5% 1 month after Ramadan; pRamadan deteriorated the glycemic control in Type 2 diabetes patients. This was more evident in patients using oral hypoglycemic medication than diet- controlled patients. However, Ramadan fasting had small positive effects on lipid profile and body weight.

  13. Development of Integral Environment in Matlab/Simulink for FPGA

    Directory of Open Access Journals (Sweden)

    Dejan Jokic

    2014-01-01

    Full Text Available In this paper is presented realization of integral environment which consists of software and hardware components for the purpose of programming Altera DE boards. Software component is Toolbox FPGA Real Time which enables simple use of Matlab/Simulink with DSP Builder for the purpose of realization of control structures. Hardware component are Interface cards that make connection of DE board with object of control possible. Simulation and experimental results of DC motor control indicate the usefulness of the proposed concept.

  14. The effect of Ramadan fasting on glycaemic control in insulin dependent diabetic patients: A literature review.

    Science.gov (United States)

    Alabbood, Majid H; Ho, Kenneth W; Simons, Mary R

    Ramadan fasting is one of the five pillars of Islam. People with diabetes are exempted from fasting according to Islamic rules. However, many people with diabetes wish to fast. Physicians are asked frequently by their patients about their ability to fast and the possible impact of fasting on their glycaemic control. Studies about the effect of Ramadan on people with insulin-treated diabetes are scarce. This review aims to provide clinicians with the best recommendations for their patients with insulin-treated diabetes who wish to fast. Four databases (Medline, EMBASE, Scopus and PubMed) were searched using the following MeSH terms and keywords: "insulin dependent diabetes mellitus", "type 1 diabetes mellitus", 'Ramadan' "and" "fasting". In addition, a hand search of key journals and reference lists was performed. Sixteen full text articles were selected for review and critical analysis. All of the included studies except one found improvement or no change in glycaemic control parameters during Ramadan fasting. The incidence of major complications were negligible. Minor hypoglycaemic events were reported in some studies but did not adversely affect fasting. Postprandial hyperglycaemia was a major concern in other studies. However, the incidence of severe hyperglycaemia and diabetic ketoacidosis were trivial. Ramadan fasting is feasible for insulin dependent diabetic patient who wish to fast. Clinicians should advise their patients about the importance of adequate glycaemic control before Ramadan and frequent glucose monitoring during fasting. Certain types of Insulin seem to be more beneficial than other. Copyright © 2016 Diabetes India. Published by Elsevier Ltd. All rights reserved.

  15. Economical Implementation of a Filter Engine in an FPGA

    Science.gov (United States)

    Kowalski, James E.

    2009-01-01

    A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be

  16. A numerically stable, finite memory, fast array recursive least squares algorithm for broadband active noise control

    NARCIS (Netherlands)

    van Ophem, S.; Berkhoff, Arthur P.

    2016-01-01

    For broadband active noise control applications with a rapidly changing primary path, it is desirable to find algorithms with a rapid convergence, a fast tracking performance, and a low computational cost. Recently, a promising algorithm has been presented, called the fast-array Kalman filter, which

  17. A numerically stable, finite memory, fast array recursive least squares filter for broadband active noise control

    NARCIS (Netherlands)

    Ophem, S. van; Berkhoff, A.P.

    2016-01-01

    Summary For broadband active noise control applications with a rapidly changing primary path, it is desirable to find algorithms with a rapid convergence, a fast tracking performance, and a low computational cost. Recently, a promising algorithm has been presented, called the fast-array Kalman

  18. Fast Coordinated Control of DFIG Wind Turbine Generators for Low and High Voltage Ride-Through

    DEFF Research Database (Denmark)

    Wang, Yun; Wu, Qiuwei; Xu, Honghua

    2014-01-01

    This paper presents a fast coordinated control scheme of the rotor side converter (RSC), the DC chopper and the grid side converter (GSC) of doubly fed induction generator (DFIG) wind turbine generators (WTGs) which is to improve the low voltage ride through (LVRT) and high voltage ride through...... were proposed considering the characteristics of the DFIG WTGs during voltage changes. The fast coordinated control of RSC and GSC were developed based on the characteristic analysis in order to realize efficient LVRT and HVRT of the DFIG WTGs. The proposed fast coordinated control schemes were...

  19. On fast-ion transport and burn control in Tokamaks

    International Nuclear Information System (INIS)

    Wising, F.

    1994-01-01

    Fast ions, generated by e.g. neutral beam injection (NBI), radio frequency (RF) heating or nuclear reactions, play an important role in all large tokamaks. Several issues related to fast ions and burning fusion plasmas are addressed in this thesis. Firstly, a new model of sawtooth oscillations is developed which explains the recent observations that q 0 remains below unity during the entire sawtooth cycle. The model features full reconnection in two current layers and provides a self-consistent description of the plasma states before and after the sawtooth crash. It is applied to the redistribution of fast NBI-ions in JET and comparisons are made with global as well as line-of-sight integrated D-D neutron measurements. Both the new model and the classical Kadomtsev model are found to be in agreement with the measurements. A simplified redistribution model is developed and applied to the redistribution of tritons and thermal ions, again giving reasonable agreement with D-T/D-D neutron measurements. Using a separate method, earlier results on expulsion of NBI-ions are confirmed. Secondly, a numerical study has been carried out of the coupled nonlinear evolution of alpha-particle driven kinetic Alfven wave turbulence and associated alpha transport. The saturated fluctuation spectrum consists of two peaks and results from nonlinear ion Compton scattering-induced transfer of energy from longer to shorter wavelengths. An analytical solution of the saturated spectrum, and estimates of the anomalous alpha diffusion coefficient, are given. The final paper addresses the problem of determining whether an initial temperature profile, established by e.g. auxiliary heating, will evolve to thermonuclear burn or quench under the influence of alpha particle heating and thermal conduction. Explicit burn criteria are presented and the beneficial effects of density and temperature peaking are discussed. 110 refs

  20. Fast, cheap and in control: spectral imaging with handheld devices

    Science.gov (United States)

    Gooding, Edward A.; Deutsch, Erik R.; Huehnerhoff, Joseph; Hajian, Arsen R.

    2017-05-01

    Remote sensing has moved out of the laboratory and into the real world. Instruments using reflection or Raman imaging modalities become faster, cheaper and more powerful annually. Enabling technologies include virtual slit spectrometer design, high power multimode diode lasers, fast open-loop scanning systems, low-noise IR-sensitive array detectors and low-cost computers with touchscreen interfaces. High-volume manufacturing assembles these components into inexpensive portable or handheld devices that make possible sophisticated decision-making based on robust data analytics. Examples include threat, hazmat and narcotics detection; remote gas sensing; biophotonic screening; environmental remediation and a host of other applications.

  1. Fault injection as a test method for an FPGA in charge of data readout for a large tracking detector

    CERN Document Server

    Roed, K; Richter, M; Fehlker, D; Helstrup, H; Alme, J; Ullaland, K

    2011-01-01

    This paper describes how fault injection has been implemented as a test method for an FPGA in an existing hardware configuration setup. As this FPGA is in charge of data readout for a large tracking detector, the reliability of this FPGA is of high importance. Due to the complexity of the readout electronics, irradiation testing is technically difficult at this stage of the system commissioning. The work presented in this paper is therefore motivated by introducing fault injection as an alternative method to characterize failures caused by SEUs. It is a method to study the effect that a configuration upset may have on the operation of the FPGA. The target platform consists of two independent modules for data acquisition and detector control functionality. Fault injection to test the response of the data acquisition module is made possible by implementing the solution as part of the detector control functionality. Correct implementation is validated by a simple shift register design. Our results demonstrate th...

  2. Fault tolerance based on serial communication of FPGA

    International Nuclear Information System (INIS)

    Peng Jing; Fang Zongliang; Xu Quanzhou; Hu Jiewei; Ma Guizhen

    2012-01-01

    There maybe appear mistake in serial communication. This paper was described the intellectual detector of γ dose ratemeter communication with FPGA. The software of FPGA designed the code about fault tolerance, prevented mistake effectively. (authors)

  3. FPGA fault tolerance in particle physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Gebelein, Jano; Engel, Heiko; Kebschull, Udo [Kirchhoff-Institute for Physics, Heidelberg University (Germany)

    2010-07-01

    The behavior of matter in physically extreme conditions is in focus of many high-energy-physics experiments. For this purpose, high energy charged particles (ions) are collided with each other and energy- or baryon densities are created similar to those at the beginning of the universe or to those which can be found in the center of neutron stars. In both cases a plasma of quarks and gluons (QGP) is present, which immediately decomposes to hadrons within a short period of time. At this process, particles are formed, which allow statements about the beginning of the universe when captured by large detectors, but which also lead to the massive occurance of hardware failures within the detector's electronic devices. This contribution is about methods to mitigate radiation susceptibility for Field Programmable Gate Arrays (FPGA), enabling them to be used within particle detector systems to directly gain valid data in the readout chain or to be used as detector-control-system.

  4. Controlling multi-bunches by a fast phase switching

    International Nuclear Information System (INIS)

    Decker, F.J.; Jobe, R.K.; Merminga, N.; Thompson, K.A.

    1990-09-01

    In linear accelerators with two or more bunches the beam loading of one bunch will influence the energy and energy spread the following bunches. This can be corrected by quickly changing the phase of a traveling wave-structure, so that each bunch receives a slightly different net phase. At the SLAC Linear Collider (SLC) three bunches, two (e + ,e - ) for the high energy collisions and one (e - -scavenger) for producing positrons should sit at different phases, due to their different tasks. The two e - -bunches are extracted from the damping ring at the same cycle time about 60 ns apart. Fast phase switching of the RF to the bunch length compressor in the Ring-To-Linac (RTL) section can produce the necessary advance of the scavenger bunch (about 6 degree in phase). This allows a low energy spread of this third bunch at the e + -production region at 2/3 of the linac length, while the other bunches are not influenced. The principles and possible other applications of this fast phase switching as using it for multi-bunches, as well as the experimental layout for the actual RTL compressor are presented

  5. FPGA based algorithms for data reduction at Belle II

    Energy Technology Data Exchange (ETDEWEB)

    Muenchow, David; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liu, Ming; Spruck, Bjoern [II. Physikalisches Institut, Universitaet Giessen (Germany)

    2011-07-01

    Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e{sup +}e{sup -} collider with a design luminosity of 8.10{sup 35}cm{sup -2}s{sup -1}. At Belle II the estimated event rate is {<=}30 kHz. The resulting data rate at the Pixel Detector (PXD) will be {<=}7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for buffering and storing the data. The status of the implementation and performance tests of the memory manager and data reduction algorithm is presented.

  6. Flight Research into Simple Adaptive Control on the NASA FAST Aircraft

    Science.gov (United States)

    Hanson, Curtis E.

    2011-01-01

    A series of simple adaptive controllers with varying levels of complexity were designed, implemented and flight tested on the NASA Full-Scale Advanced Systems Testbed (FAST) aircraft. Lessons learned from the development and flight testing are presented.

  7. Quality control of sputum microscopic examinations for acid fast ...

    African Journals Online (AJOL)

    Preferred Customer

    in the Southern Region of Ethiopia, and quality control has been initiated as part of this effort. Objective: To evaluate the ... National Tuberculosis and Leprosy Control Programme. (TLCP) manual for ..... laboratories in Mexico. Int J Tuberc Lung ...

  8. An integrated gyrotron controller

    Energy Technology Data Exchange (ETDEWEB)

    Michel, Georg, E-mail: michel@ipp.mpg.de; Sachtleben, Juergen

    2011-10-15

    The ECRH system of W7-X is composed of 10 independent gyrotron modules. Each module consists of one gyrotron and its peripherals such as power supplies, cooling plants and distributed PLC systems. The fast real-time control functions such as the timing of the two high voltage supplies, trigger pulses, protection, modulation and communication with the central control of W7-X, is implemented in an integrated controller which is described in this paper. As long-term maintainability and sustainability are important for nuclear fusion experiments, the choice fell on an FPGA-based design which is exclusively based on free (as in 'freedom') software and configuration code. The core of the controller consists of a real-time Java virtual machine (JVM) that provides the TCP-IP connectivity as well as more complicated control functions, and which interacts with the gyrotron-specific hardware. Both the gyrotron-specific hardware and the JVM are implemented on the same FPGA, which is the main component of the controller. All 10 controllers are currently completed and operational. All parameters and functions are accessible via Ethernet. Due to the open, FPGA-based design, most hardware modifications can be made via the network as well. This paper discusses the capabilities of the controllers and their integration into the central W7-X control.

  9. Fast Control Channel Decoding for LTE UE Power Saving

    DEFF Research Database (Denmark)

    Lauridsen, Mads; Jensen, Anders Riis; Mogensen, Preben

    2012-01-01

    in the current TTI. The cost is that some reference signals are not received leading to a degraded channel estimate. Calculations show that this causes an SINR degradation of approximately 0.5 dB, which will result in maximum 4 % throughput loss. Comparing this with energy saving potentials of 5 %-25...... % it is concluded that the FCCD method is a valuable aid to prolong LTE phones' battery lifetime. The results are generated using a two state Markov chain model to simulate traffic and scheduling, and verified mathematically. The work also includes an examination of various data traffic types' on/off relation...... and an evaluation of how the relation affects power consumption. The FCCD method can complement DRX sleep mode since it is applicable when the signal is too aperiodic or fast switching for DRX....

  10. Motion camera based on a custom vision sensor and an FPGA architecture

    Science.gov (United States)

    Arias-Estrada, Miguel

    1998-09-01

    A digital camera for custom focal plane arrays was developed. The camera allows the test and development of analog or mixed-mode arrays for focal plane processing. The camera is used with a custom sensor for motion detection to implement a motion computation system. The custom focal plane sensor detects moving edges at the pixel level using analog VLSI techniques. The sensor communicates motion events using the event-address protocol associated to a temporal reference. In a second stage, a coprocessing architecture based on a field programmable gate array (FPGA) computes the time-of-travel between adjacent pixels. The FPGA allows rapid prototyping and flexible architecture development. Furthermore, the FPGA interfaces the sensor to a compact PC computer which is used for high level control and data communication to the local network. The camera could be used in applications such as self-guided vehicles, mobile robotics and smart surveillance systems. The programmability of the FPGA allows the exploration of further signal processing like spatial edge detection or image segmentation tasks. The article details the motion algorithm, the sensor architecture, the use of the event- address protocol for velocity vector computation and the FPGA architecture used in the motion camera system.

  11. Catecholamine levels in a Ramadan fasting model in rats: a case control study

    Directory of Open Access Journals (Sweden)

    Pakize Gamze Erten Bucaktepe

    2016-07-01

    Full Text Available Eating habits as well as physical exercise are very important for a healthy lifespan. Ramadan-type fasting, which is food and water avoidance during the daylight period for four weeks, has drawn attention due to its positive impacts on metabolism and health. The aim of this study was to compare the blood and urine catecholamine (CA levels in fasting and non-fasting rats, in terms of stress response. A total of 20 male rats were randomly divided into a fasting group and a control group. Four weeks later, blood and urine samples were taken after decapitation. Analysis of CAs was done using high-performance liquid chromatography with florescence detection (HPLC-FLD. The dopamine (DA, adrenaline (ADR and noradrenaline (NA blood and urine concentrations were found to be higher in the fasting group compared to the control group, but the difference was statistically significant only for the blood DA levels (p < 0.05. In the fasting group, the blood values of ADR and NA correlated with each other but not with the DA levels, whereas there was correlation among the urine levels of DA, ADR and NA. In the control group, the blood and urine values of DA, ADR and NA correlated with each other. The differences observed in the blood and urine CAs indicate a specific regulation of CAs in Ramadan-type fasting, which needs to be investigated thoroughly in future studies.

  12. Analysis of control rod worth in experimental fast reactor JOYO

    International Nuclear Information System (INIS)

    Arii, Y.; Aoyama, T.; Okimoto, Y.; Yoshida, A.; Mizoo, N.

    1988-01-01

    In JOYO, the measurement of control rod worths have been carried out in the beginning of the each cycle, using both period method and neutron source multiplication method. In this paper, the calculational method of control rod worths in the design stage and the comparison with the design values and measured ones are shown. The reasons that the control rod worths change slightly in each cycle, are also investigated. (author). 13 figs, 12 tabs

  13. FPGA Implementation of the stepwise shutdown system

    Energy Technology Data Exchange (ETDEWEB)

    Lotjonen, L.

    2012-07-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  14. FPGA Implementation of the stepwise shutdown system

    International Nuclear Information System (INIS)

    Lotjonen, L.

    2012-01-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and standards can be used to some extent but the hardware aspects bring new challenges that cannot be tackled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation process from the requirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  15. Design of Measurement and Control System of Composite Fast Transfer Switch Based on PLC

    Directory of Open Access Journals (Sweden)

    ZHANG Hong-yi

    2017-06-01

    Full Text Available The fast transfer switch gets more extensive application in the power supply system along with the raising of power supply requirement for continuity and reliability in the sensitivity loads such as in airport,military place,hospital and large scale industrial production line. Therefore it is important that how to make fast transfer switch run safely and reliably. The paper expatiated the structure and principle of a fast transfer switch based on mechanical and electronic compound technology,and,according to the basic requirement and the characteristic of the fast transfer switch,a PLC mastered measuring and controlling system has been designed to raise the operation reliability of the fast transfer switch.

  16. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

  17. Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Cardinali, M., E-mail: cardinal@kph.uni-mainz.de [Institut für Kernphysik, Johannes Gutenberg-University Mainz, Mainz (Germany); Helmholtz Institut Mainz, Mainz (Germany); Dzyhgadlo, R.; Gerhardt, A.; Götzen, K.; Hohler, R.; Kalicy, G.; Kumawat, H.; Lehmann, D.; Lewandowski, B.; Patsyuk, M.; Peters, K.; Schepers, G.; Schmitt, L.; Schwarz, C.; Schwiening, J.; Traxler, M.; Ugur, C.; Zühlsdorf, M. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Darmstadt (Germany); Dodokhov, V.Kh. [Joint Institute for Nuclear Research, Dubna (Russian Federation); Britting, A. [Friedrich Alexander-University of Erlangen-Nuremberg, Erlangen (Germany); and others

    2014-12-01

    The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R and D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and fast discriminators. The discriminators also provide time-over-threshold information thus enabling walk corrections to improve the timing resolution. Two types of frontend electronics cards optimised for reading out 64-channel PHOTONIS Planacon MCP-PMTs were tested: one based on the NINO ASIC and the other, called PADIWA, on FPGA discriminators. Promising results were obtained in a full characterisation using a fast laser setup and in a test experiment at MAMI, Mainz, with a small scale DIRC prototype. - Highlights: • Frontend electronics for Cherenkov detectors have been developed. • FPGA-TDCs have been used for high precision timing. • Time over threshold has been utilised for walk correction. • Single photo-electron timing resolution less than 100 ps has been achieved.

  18. FPGA implementation of adaptive beamforming in hearing aids.

    Science.gov (United States)

    Samtani, Kartik; Thomas, Jobin; Varma, G Abhinav; Sumam, David S; Deepu, S P

    2017-07-01

    Beamforming is a spatial filtering technique used in hearing aids to improve target sound reception by reducing interference from other directions. In this paper we propose improvements in an existing architecture present for two omnidirectional microphone array based adaptive beamforming for hearing aid applications and implement the same on Xilinx Artix 7 FPGA using VHDL coding and Xilinx Vivado ® 2015.2. The nulls are introduced in particular directions by combination of two fixed polar patterns. This combination can be adaptively controlled to steer the null in the direction of noise. The beamform patterns and improvements in SNR values obtained from experiments in a conference room environment are analyzed.

  19. Dynamically controlled energy dissipation for fast magnetic vortex switching

    Science.gov (United States)

    Badea, R.; Berezovsky, J.

    2017-09-01

    Manipulation of vortex states in magnetic media provides new routes towards information storage and processing technology. The typical slow relaxation times (˜100 ns) of magnetic vortex dynamics may present an obstacle to the realization of these applications. Here, we investigate how a vortex state in a ferromagnetic microdisk can be manipulated in a way that translates the vortex core while enhancing energy dissipation to rapidly damp the vortex dynamics. We use time-resolved differential magneto-optical Kerr effect microscopy to measure the motion of the vortex core in response to applied magnetic fields. We first map out how the vortex core becomes sequentially trapped by pinning sites as it translates across the disk. After applying a fast magnetic field step to translate the vortex from one pinning site to another, we observe long-lived dynamics of the vortex as it settles to the new equilibrium. We then demonstrate how the addition of a short (<10 ns) magnetic field pulse can induce additional energy dissipation, strongly damping the long-lived dynamics. A model of the vortex dynamics using the Thiele equation of motion explains the mechanism behind this effect.

  20. Diversity for security: case assessment for FPGA-based safety-critical systems

    Directory of Open Access Journals (Sweden)

    Kharchenko Vyacheslav

    2016-01-01

    Full Text Available Industrial safety critical instrumentation and control systems (I&Cs are facing more with information (in general and cyber, in particular security threats and attacks. The application of programmable logic, first of all, field programmable gate arrays (FPGA in critical systems causes specific safety deficits. Security assessment techniques for such systems are based on heuristic knowledges and the expert judgment. Main challenge is how to take into account features of FPGA technology for safety critical I&Cs including systems in which are applied diversity approach to minimize risks of common cause failure. Such systems are called multi-version (MV systems. The goal of the paper is in description of the technique and tool for case-based security assessment of MV FPGA-based I&Cs.

  1. FPGA based compute nodes for high level triggering in PANDA

    International Nuclear Information System (INIS)

    Kuehn, W; Gilardi, C; Kirschner, D; Lang, J; Lange, S; Liu, M; Perez, T; Yang, S; Schmitt, L; Jin, D; Li, L; Liu, Z; Lu, Y; Wang, Q; Wei, S; Xu, H; Zhao, D; Korcyl, K; Otwinowski, J T; Salabura, P

    2008-01-01

    PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10 7 /s and data rates of several 100 Gb/s. FPGA based compute nodes with multi-Gb/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Data connectivity is provided via optical links as well as multiple Gb Ethernet ports. The boards will support trigger algorithms such us pattern recognition for RICH detectors, EM shower analysis, fast tracking algorithms and global event characterization. Besides VHDL, high level C-like hardware description languages will be considered to implement the firmware

  2. A FPGA Implementation of the CAR-FAC Cochlear Model

    Directory of Open Access Journals (Sweden)

    Ying Xu

    2018-04-01

    Full Text Available This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC cochlear model. The CAR part simulates the basilar membrane's (BM response to sound. The FAC part models the outer hair cell (OHC, the inner hair cell (IHC, and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  3. A FPGA Implementation of the CAR-FAC Cochlear Model.

    Science.gov (United States)

    Xu, Ying; Thakur, Chetan S; Singh, Ram K; Hamilton, Tara Julia; Wang, Runchun M; van Schaik, André

    2018-01-01

    This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  4. Beam extraction control systems of the fast-cycling synchrotron

    International Nuclear Information System (INIS)

    Toumanian, A.; Zapolski, N.; Nickogosian, V.; Ananian, A.; Kazarian, A.; Khoetsian, M.; Agababian, A.; Matevosian, A.

    1992-01-01

    A compact system controlling the extraction of different beams (gamma, electron, synchrotron radiation) in single and simultaneous operation modes at high electromagnetic disturbances level based on using one computer of IBM PC/AT type is described. (author)

  5. SEU mitigation technique by Dynamic Reconfiguration method in FPGA based DSP application

    International Nuclear Information System (INIS)

    Dey, Madhusudan; Singh, Abhishek; Roy, Amitava

    2012-01-01

    Field Programmable Gate Array (FPGA), an SRAM based configurable devices meant for implementation of any digital circuits is susceptible to malfunction in the harsh radiation environment. It causes the corruption of the configuration memory of FPGA and the digital circuits starts malfunctioning. There is a need to restore the system as early as possible. This paper discusses about one such technique named dynamic partial reconfiguration (DPR) method. This paper also touches upon the signal processing by DPR method. The framework consisting of ADC, DAC and ICAP controllers designed using dedicated state machines to study the best possible downtime also for verifying the performance of digital filters for signal processing

  6. Integration of multi-interface conversion channel using FPGA for modular photonic network

    Science.gov (United States)

    Janicki, Tomasz; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.

    2010-09-01

    The article discusses the integration of different types of interfaces with FPGA circuits using a reconfigurable communication platform. The solution has been implemented in practice in a single node of a distributed measurement system. Construction of communication platform has been presented with its selected hardware modules, described in VHDL and implemented in FPGA circuits. The graphical user interface (GUI) has been described that allows a user to control the operation of the system. In the final part of the article selected practical solutions have been introduced. The whole measurement system resides on multi-gigabit optical network. The optical network construction is highly modular, reconfigurable and scalable.

  7. Design of the device of auto-measuring radon continuously based on FPGA

    International Nuclear Information System (INIS)

    Wang Yan; Shen Zhengqin; Chen Qiong

    2004-01-01

    This paper introduces the design of the device of auto-measuring radon continuously. The core of the system is the design of controlling system by FPGA, which consists of preset module, electrical calendar module and driving module. The system can automatically measure the consistence of the radon and the separating out rate of it. The information data is displayed by LCD. The high speed micro printer is used to print the measuring result. It adopts FPGA to design the measuring system of the device, which can improve the precision and stability of the system. (authors)

  8. Piecewise affine control for fast unmanned ground vehicles

    OpenAIRE

    Benine Neto , André; Grand , Christophe

    2012-01-01

    International audience; Unmanned ground vehicles (UGV) may experience skidding when moving at high speeds, and therefore have its safety jeopardized. For this reason the nonlinear dynamics of lateral tire forces must be taken into account into the design of steering controllers for autonomous vehicles. This paper presents the design of a state feedback piecewise affine controller applied to an UGV to coordinate the steering and torque distribution inputs in order to reduce vehicle skidding on...

  9. The Case for Intelligent Propulsion Control for Fast Engine Response

    Science.gov (United States)

    Litt, Jonathan S.; Frederick, Dean K.; Guo, Ten-Huei

    2009-01-01

    Damaged aircraft have occasionally had to rely solely on thrust to maneuver as a consequence of losing hydraulic power needed to operate flight control surfaces. The lack of successful landings in these cases inspired research into more effective methods of utilizing propulsion-only control. That research demonstrated that one of the major contributors to the difficulty in landing is the slow response of the engines as compared to using traditional flight control. To address this, research is being conducted into ways of making the engine more responsive under emergency conditions. This can be achieved by relaxing controller limits, adjusting schedules, and/or redesigning the regulators to increase bandwidth. Any of these methods can enable faster response at the potential expense of engine life and increased likelihood of stall. However, an example sensitivity analysis revealed a complex interaction of the limits and the difficulty in predicting the way to achieve the fastest response. The sensitivity analysis was performed on a realistic engine model, and demonstrated that significantly faster engine response can be achieved compared to standard Bill of Material control. However, the example indicates the need for an intelligent approach to controller limit adjustment in order for the potential to be fulfilled.

  10. OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

  11. Evaluation of a fast PLC module in prospect of the LHC beam interlock system

    CERN Document Server

    Zaera-Sanz, Manuel

    2005-01-01

    The LHC Beam Interlock system requires a controller performing a simple matrix function to collect the different beam dump requests. To satisfy the expected safety level of the Interlock, the system should be robust and reliable. The PLC is a promising candidate to fulfil both aspects but too slow to meet the expected response time which is of the order of mseconds. Siemens has introduced a “so called” fast module (FM352-5 Boolean Processor) that provides independent and extremely fast control of a process within a larger control system using an onboard processor, a Field Programmable Gate Array (FPGA), to execute code in parallel which results in extremely fast scan times. It is interesting to investigate its features and to evaluate it as a possible candidate for the beam interlock system. This note publishes the results of this study. As well, this note could be useful for other applications requiring fast processing using a PLC.

  12. Plant Control Concept for the Sodium Cooled Fast Reactor

    International Nuclear Information System (INIS)

    Kim, Eui Kwang; Kim, S. O.

    2010-12-01

    A power plant is designed for incorporation into a utility's grid system and follows the load demand through the steam generator, intermediate heat exchanger(IHX), from the nuclear core. During the load-following transients, various plant parameters must be controlled to protect the reactor core and other components in the plant. The purpose of this report is to review design considerations to establish SFR plant control and to design plant control concepts. The governing equations and solution procedure of the computer code to calculate plant temperature conditions during the part-load operation was reviewed and 4 types of plant operation concepts were designed, and the results of the calculations were compared

  13. Seismic appraisal test of control rod drive mechanism of China experiment fast reactor

    International Nuclear Information System (INIS)

    Song Qing; Yang Hongyi; Jing Yueqing; Wen Jing; Liu Guijuan; Sun Lei

    2008-01-01

    The structure of the control rod drive mechanism in pool type sodium-cooled fast reactor is the characterized by long, thin, and geometric nonlinearity, and the seismic load is multiple activation. The anti-seismic evaluation is always paid great attention by the countries developing the technology worldwide. This article introduces the seismic appraisal test of the control rod drive mechanism of China Experimental Fast Reactor (CEFR) performed on a seismic platform which is vertical shaft style and multiple activation. The result of the test shows the structural integrity and the function of the control rod drive mechanism could meet the design requirements of the earthquake intensity. (authors)

  14. Control fast or control smart: When should invading pathogens be controlled?

    Directory of Open Access Journals (Sweden)

    Robin N Thompson

    2018-02-01

    Full Text Available The intuitive response to an invading pathogen is to start disease management as rapidly as possible, since this would be expected to minimise the future impacts of disease. However, since more spread data become available as an outbreak unfolds, processes underpinning pathogen transmission can almost always be characterised more precisely later in epidemics. This allows the future progression of any outbreak to be forecast more accurately, and so enables control interventions to be targeted more precisely. There is also the chance that the outbreak might die out without any intervention whatsoever, making prophylactic control unnecessary. Optimal decision-making involves continuously balancing these potential benefits of waiting against the possible costs of further spread. We introduce a generic, extensible data-driven algorithm based on parameter estimation and outbreak simulation for making decisions in real-time concerning when and how to control an invading pathogen. The Control Smart Algorithm (CSA resolves the trade-off between the competing advantages of controlling as soon as possible and controlling later when more information has become available. We show-using a generic mathematical model representing the transmission of a pathogen of agricultural animals or plants through a population of farms or fields-how the CSA allows the timing and level of deployment of vaccination or chemical control to be optimised. In particular, the algorithm outperforms simpler strategies such as intervening when the outbreak size reaches a pre-specified threshold, or controlling when the outbreak has persisted for a threshold length of time. This remains the case even if the simpler methods are fully optimised in advance. Our work highlights the potential benefits of giving careful consideration to the question of when to start disease management during emerging outbreaks, and provides a concrete framework to allow policy-makers to make this decision.

  15. Control fast or control smart: When should invading pathogens be controlled?

    Science.gov (United States)

    Thompson, Robin N; Gilligan, Christopher A; Cunniffe, Nik J

    2018-02-01

    The intuitive response to an invading pathogen is to start disease management as rapidly as possible, since this would be expected to minimise the future impacts of disease. However, since more spread data become available as an outbreak unfolds, processes underpinning pathogen transmission can almost always be characterised more precisely later in epidemics. This allows the future progression of any outbreak to be forecast more accurately, and so enables control interventions to be targeted more precisely. There is also the chance that the outbreak might die out without any intervention whatsoever, making prophylactic control unnecessary. Optimal decision-making involves continuously balancing these potential benefits of waiting against the possible costs of further spread. We introduce a generic, extensible data-driven algorithm based on parameter estimation and outbreak simulation for making decisions in real-time concerning when and how to control an invading pathogen. The Control Smart Algorithm (CSA) resolves the trade-off between the competing advantages of controlling as soon as possible and controlling later when more information has become available. We show-using a generic mathematical model representing the transmission of a pathogen of agricultural animals or plants through a population of farms or fields-how the CSA allows the timing and level of deployment of vaccination or chemical control to be optimised. In particular, the algorithm outperforms simpler strategies such as intervening when the outbreak size reaches a pre-specified threshold, or controlling when the outbreak has persisted for a threshold length of time. This remains the case even if the simpler methods are fully optimised in advance. Our work highlights the potential benefits of giving careful consideration to the question of when to start disease management during emerging outbreaks, and provides a concrete framework to allow policy-makers to make this decision.

  16. FPGA Realization of Memory 10 Viterbi Decoder

    DEFF Research Database (Denmark)

    Paaske, Erik; Bach, Thomas Bo; Andersen, Jakob Dahl

    1997-01-01

    sequence mode when feedback from the Reed-Solomon decoder is available. The Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's. The overall operating speed is 30 kbit/s, and since up to three iterations are performed for each frame and only one decoder is used, the operating speed...

  17. Fast control of a M.A. 23 manipulator

    International Nuclear Information System (INIS)

    Mouhamed, Mayez al.

    1981-07-01

    The present paper deals with the problem of the control of manipulating robots. Several methodologies used to define the basic elements of a command language are described. Our main interest lies in the movement coordination level. For this purpose we shall study in more detail the functions built around a module representing a geometrical model. Then the problem of effort analysis by computer is investigated. Two heuristic methods enabling the computation of the forces applied to the effector are proposed. The functions described above are implemented in a 16 bits microprocessor unit (INTEL 8086) associated with a floating point coprocessor (INTEL 8087). Finally, the performance of the control system, particularly the 8 ms command cycle and the low cost of system are discussed [fr

  18. Fast core prediction simulator for load follow control

    International Nuclear Information System (INIS)

    Yim, Man Sung; Lee, Sang Hoon; Lee, Un Chul

    1990-01-01

    An operator-assisting system for the reactor core control under power changing operating condition was developed. The system is consisted of core simulator routine and Xenon and Iodine initial condition generation routine. The initial condition generation routine, without exactly knowing the core status, is capable of providing accurate number densities and axial offset conditions of Xenon and Iodine after several hours of predictor- corrector calculations using the plant instrumentation signals of power level and power axial offset. The core simulator routine, even with the two node core model, gives equivalently accurate results as the one-dimensional model for the core behaviour simulation under power changing condition and can provide proper control strategies for load follow operation. The core simulator can also be used by the operator to develop remedial actions to restore the distorted power distribution by using its prediction capability

  19. Controlling microwave signals by means of slow and fast light effects in SOA-EA structures

    DEFF Research Database (Denmark)

    Sales, Salvador; Öhman, Filip; Capmany, José

    2007-01-01

    We present a novel scheme for the control of microwave signals in the optical domain. We propose the use of alternating amplifying and absorbing sections to implement phase control by using fast and slow light effects in semiconductors. The potential benefits from the proposed semiconductor optic...

  20. Embedded algorithms within an FPGA-based system to process nonlinear time series data

    Science.gov (United States)

    Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

    2008-03-01

    This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better

  1. An integrated approach to the biomechanics and motor control of cricket fast bowling techniques.

    Science.gov (United States)

    Glazier, Paul S; Wheat, Jonathan S

    2014-01-01

    To date, scientific investigations into the biomechanical aspects of cricket fast bowling techniques have predominantly focused on identifying the mechanical factors that may predispose fast bowlers to lower back injury with a relative paucity of research being conducted on the technical features that underpin proficient fast bowling performance. In this review paper, we critique the scientific literature examining fast bowling performance. We argue that, although many published investigations have provided some useful insights into the biomechanical factors that contribute to a high ball release speed and, to a lesser extent, bowling accuracy, this research has not made a substantive contribution to knowledge enhancement and has only had a very minor influence on coaching practice. To significantly enhance understanding of cricket fast bowling techniques and, therefore, have greater impact on practice, we recommend that future scientific research adopts an interdisciplinary focus, integrating biomechanical measurements with the analytical tools and concepts of dynamical systems motor control theory. The use of qualitative (topological) analysis techniques, in particular, promises to increase understanding of the coordinative movement patterns that define 'technique' in cricket fast bowling and potentially help distinguish between functional and dysfunctional aspects of technique for individual fast bowlers.

  2. EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER

    International Nuclear Information System (INIS)

    HOFF, L.T.

    2005-01-01

    The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control

  3. Optimization on fixed low latency implementation of the GBT core in FPGA

    Science.gov (United States)

    Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

    2017-07-01

    In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

  4. Optimization on fixed low latency implementation of the GBT core in FPGA

    International Nuclear Information System (INIS)

    Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

    2017-01-01

    In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

  5. Hardware support for software controlled fast reconfiguration of performance counters

    Science.gov (United States)

    Salapura, Valentina; Wisniewski, Robert W.

    2013-06-18

    Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters.

  6. Fast Coordinated Control of DFIG Wind Turbine Generators for Low and High Voltage Ride-Through

    Directory of Open Access Journals (Sweden)

    Yun Wang

    2014-06-01

    Full Text Available This paper presents a fast coordinated control scheme of the rotor side converter (RSC, the Direct Current (DC chopper and the grid side converter (GSC of doubly fed induction generator (DFIG wind turbine generators (WTGs to improve the low voltage ride through (LVRT and high voltage ride through (HVRT capability of the DFIG WTGs. The characteristics of DFIG WTGs under voltage sags and swells were studied focusing on the DFIG WTG stator flux and rotor voltages during the transient periods of grid voltage changes. The protection schemes of the rotor crowbar circuit and the DC chopper circuit were proposed considering the characteristics of the DFIG WTGs during voltage changes. The fast coordinated control of RSC and GSC were developed based on the characteristic analysis in order to realize efficient LVRT and HVRT of the DFIG WTGs. The proposed fast coordinated control schemes were verified by time domain simulations using Matlab-Simulink.

  7. Design of a Hardware-Implemented Phase Calculating System for Feedback Control in the LHCD Experiments on EAST

    International Nuclear Information System (INIS)

    Liu Qiang; Liang Hao; Zhou Yongzhao

    2009-01-01

    A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive (LHCD) experiments is presented in this paper. By taking advantages of field programmable gate array (FPGA) chips with embedded digital signal processing (DSP) cores and the Matlab-aided design method, the phase calculating algorithm with a square root operation and parallel process are efficiently implemented in a single FPGA chip to complete the calculation of phase differences fast and accurately in the lower-hybrid wave (LHW) system on EAST. (fusion engineering)

  8. Slow food, fast food and the control of food intake.

    Science.gov (United States)

    de Graaf, Cees; Kok, Frans J

    2010-05-01

    This Perspective focuses on two elements of our food supply and eating environment that facilitate high energy intake: a high eating rate and distraction of attention from eating. These two elements are believed to undermine our body's capacity to regulate its energy intake at healthy levels because they impair the congruent association between sensory signals and metabolic consequences. The findings of a number of studies show that foods that can be eaten quickly lead to high food intake and low satiating effects-the reason being that these foods only provide brief periods of sensory exposure, which give the human body insufficient cues for satiation. Future research should focus on the underlying physiological, neurological and molecular mechanisms through which our current eating environment affects our control of food intake.

  9. Anti Theft Mechanism Through Face recognition Using FPGA

    Science.gov (United States)

    Sundari, Y. B. T.; Laxminarayana, G.; Laxmi, G. Vijaya

    2012-11-01

    The use of vehicle is must for everyone. At the same time, protection from theft is also very important. Prevention of vehicle theft can be done remotely by an authorized person. The location of the car can be found by using GPS and GSM controlled by FPGA. In this paper, face recognition is used to identify the persons and comparison is done with the preloaded faces for authorization. The vehicle will start only when the authorized personís face is identified. In the event of theft attempt or unauthorized personís trial to drive the vehicle, an MMS/SMS will be sent to the owner along with the location. Then the authorized person can alert the security personnel for tracking and catching the vehicle. For face recognition, a Principal Component Analysis (PCA) algorithm is developed using MATLAB. The control technique for GPS and GSM is developed using VHDL over SPTRAN 3E FPGA. The MMS sending method is written in VB6.0. The proposed application can be implemented with some modifications in the systems wherever the face recognition or detection is needed like, airports, international borders, banking applications etc.

  10. A Compact Synchronous Cellular Model of Nonlinear Calcium Dynamics: Simulation and FPGA Synthesis Results.

    Science.gov (United States)

    Soleimani, Hamid; Drakakis, Emmanuel M

    2017-06-01

    Recent studies have demonstrated that calcium is a widespread intracellular ion that controls a wide range of temporal dynamics in the mammalian body. The simulation and validation of such studies using experimental data would benefit from a fast large scale simulation and modelling tool. This paper presents a compact and fully reconfigurable cellular calcium model capable of mimicking Hopf bifurcation phenomenon and various nonlinear responses of the biological calcium dynamics. The proposed cellular model is synthesized on a digital platform for a single unit and a network model. Hardware synthesis, physical implementation on FPGA, and theoretical analysis confirm that the proposed cellular model can mimic the biological calcium behaviors with considerably low hardware overhead. The approach has the potential to speed up large-scale simulations of slow intracellular dynamics by sharing more cellular units in real-time. To this end, various networks constructed by pipelining 10 k to 40 k cellular calcium units are compared with an equivalent simulation run on a standard PC workstation. Results show that the cellular hardware model is, on average, 83 times faster than the CPU version.

  11. Bio-inspired motion detection in an FPGA-based smart camera module

    International Nuclear Information System (INIS)

    Koehler, T; Roechter, F; Moeller, R; Lindemann, J P

    2009-01-01

    Flying insects, despite their relatively coarse vision and tiny nervous system, are capable of carrying out elegant and fast aerial manoeuvres. Studies of the fly visual system have shown that this is accomplished by the integration of signals from a large number of elementary motion detectors (EMDs) in just a few global flow detector cells. We developed an FPGA-based smart camera module with more than 10 000 single EMDs, which is closely modelled after insect motion-detection circuits with respect to overall architecture, resolution and inter-receptor spacing. Input to the EMD array is provided by a CMOS camera with a high frame rate. Designed as an adaptable solution for different engineering applications and as a testbed for biological models, the EMD detector type and parameters such as the EMD time constants, the motion-detection directions and the angle between correlated receptors are reconfigurable online. This allows a flexible and simultaneous detection of complex motion fields such as translation, rotation and looming, such that various tasks, e.g., obstacle avoidance, height/distance control or speed regulation can be performed by the same compact device

  12. Read-out concepts for FPGA-based sub-systems within the CBM detector

    Energy Technology Data Exchange (ETDEWEB)

    Michel, Jan [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-Collaboration

    2015-07-01

    The Compressed Baryonic Matter experiment (CBM) to be built at FAIR consists of several individual sub-detectors. Some are based on custom ASICs as front-ends. Others employ FPGA based modules where extensive slow control features can be implemented to ease the recording of data and to allow for fast detection of any kind of error condition. Being designed as a free-running data acquisition, the demands also include a synchronized read-out, i.e. distribution of a common clock signal to all modules. To reduce the complexity of wiring, this is to be done sharing the same optical fibers as the data transport. During the past years, TrbNet has been designed and is used in various experiments, initially for the HADES experiment at FAIR. This protocol can now serve as a platform for the CBM read-out. In several steps, synchronous links with deterministic latency, as well as a free-streaming data transport can be included. At the same time, modifications to improve bandwidth and provide compatibility to the CERN GBTx links used for ASIC based sub-systems are to be developed. This contribution shows the planned steps as well as the current status of development.

  13. FPGA based hardware optimized implementation of signal processing system for LFM pulsed radar

    Science.gov (United States)

    Azim, Noor ul; Jun, Wang

    2016-11-01

    Signal processing is one of the main parts of any radar system. Different signal processing algorithms are used to extract information about different parameters like range, speed, direction etc, of a target in the field of radar communication. This paper presents LFM (Linear Frequency Modulation) pulsed radar signal processing algorithms which are used to improve target detection, range resolution and to estimate the speed of a target. Firstly, these algorithms are simulated in MATLAB to verify the concept and theory. After the conceptual verification in MATLAB, the simulation is converted into implementation on hardware using Xilinx FPGA. Chosen FPGA is Xilinx Virtex-6 (XC6LVX75T). For hardware implementation pipeline optimization is adopted and also other factors are considered for resources optimization in the process of implementation. Focusing algorithms in this work for improving target detection, range resolution and speed estimation are hardware optimized fast convolution processing based pulse compression and pulse Doppler processing.

  14. Overview of environmental control aspects for the gas-cooled fast reactor

    International Nuclear Information System (INIS)

    Nolan, A.M.

    1981-05-01

    Environmental control aspects relating to release of radionuclides have been analyzed for the Gas-Cooled Fast Reactor (GCFR). Information on environmental control systems was obtained for the most recent GCFR designs, and was used to evaluate the adequacy of these systems. The GCFR has been designed by the General Atomic Company as an alternative to other fast breeder reactor designs, such as the Liquid Metal Fast Breeder Reactor (LMFBR). The GCFR design includes mixed oxide fuel and helium coolant. The environmental impact of expected radionuclide releases from normal operation of the GCFR was evaluated using estimated collective dose equivalent commitments resulting from 1 year of plant operation. The results were compared to equivalent estimates for the Light Water Reactor (LWR) and High-Temperature Gas-Cooled Reactor (HTGR). A discussion of uncertainties in system performances, tritium production rates, and radiation quality factors for tritium is included

  15. An analysis of control scheme and test results of fast feedback power supply

    International Nuclear Information System (INIS)

    Gupta, Shivam Kumar; Gupta, C.N.; Shah, Kunal; Makwana, Moti

    2017-01-01

    Real time Plasma Position Control is essential for obtaining long duration plasma in tokamaks. For that purpose four external coils has been installed in toroidal direction. Magnetic field of these coils interact with the plasma and tries to keep it radially stable in vacuum vessel to avoid direct contact of plasma to wall of tokamak. A fast feedback power supply has been installed in Aditya Tokamak which is able to set the appropriate current in either direction and current magnitude in external coils on the fast scale. In this paper, an analysis of control scheme and testing of Fast Feedback Power Supply (FFPS) has been described. FFPS is IGBT based H-bridge inverter programmable power supply

  16. A RESEARCH ON SEAMLESS PLATFORM CHANGE OF REACTOR PROTECTION SYSTEM FROM PLC TO FPGA

    Directory of Open Access Journals (Sweden)

    JUNBEOM YOO

    2013-08-01

    Full Text Available The PLC (Programmable Logic Controller has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems. Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array. Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

  17. A Research on Seamless Platform Change of Reactor Protection System From PLC to FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Yoo, Junbeom; Lee, Jonghoon [Konkuk Univ., Seoul (Korea, Republic of); Lee, Jangsoo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2013-08-15

    The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

  18. A Research on Seamless Platform Change of Reactor Protection System From PLC to FPGA

    International Nuclear Information System (INIS)

    Yoo, Junbeom; Lee, Jonghoon; Lee, Jangsoo

    2013-01-01

    The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea

  19. A single FPGA-based portable ultrasound imaging system for point-of-care applications.

    Science.gov (United States)

    Kim, Gi-Duck; Yoon, Changhan; Kye, Sang-Bum; Lee, Youngbae; Kang, Jeeun; Yoo, Yangmo; Song, Tai-kyong

    2012-07-01

    We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

  20. Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system

    Science.gov (United States)

    Chen, Yi-Pin; Chang, Chia-Yuan; Chen, Shean-Jen

    2018-02-01

    In this study, a field programmable gate array (FPGA)-based Shack-Hartmann wavefront sensor (SHWS) programmed on LabVIEW can be highly integrated into customized applications such as adaptive optics system (AOS) for performing real-time wavefront measurement. Further, a Camera Link frame grabber embedded with FPGA is adopted to enhance the sensor speed reacting to variation considering its advantage of the highest data transmission bandwidth. Instead of waiting for a frame image to be captured by the FPGA, the Shack-Hartmann algorithm are implemented in parallel processing blocks design and let the image data transmission synchronize with the wavefront reconstruction. On the other hand, we design a mechanism to control the deformable mirror in the same FPGA and verify the Shack-Hartmann sensor speed by controlling the frequency of the deformable mirror dynamic surface deformation. Currently, this FPGAbead SHWS design can achieve a 266 Hz cyclic speed limited by the camera frame rate as well as leaves 40% logic slices for additionally flexible design.

  1. Optimizing latency in Xilinx FPGA implementations of the GBT

    International Nuclear Information System (INIS)

    Muschter, S; Bohm, C; Baron, S; Soos, C; Cachemiche, J-P

    2010-01-01

    The GigaBit Transceiver (GBT) system has been developed to replace the Timing, Trigger and Control (TTC) system, currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation. This code was optimized for resource utilization, as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

  2. Optimizing latency in Xilinx FPGA implementations of the GBT

    CERN Document Server

    Muschter, S; Bohm, C; Cachemiche, J-P; Baron, S

    2010-01-01

    The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation {[}3]. This code was optimized for resource utilization {[}4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The la...

  3. Optimizing latency in Xilinx FPGA implementations of the GBT

    Science.gov (United States)

    Muschter, S.; Baron, S.; Bohm, C.; Cachemiche, J.-P.; Soos, C.

    2010-12-01

    The GigaBit Transceiver (GBT) [1] system has been developed to replace the Timing, Trigger and Control (TTC) system [2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation [3]. This code was optimized for resource utilization [4], as the GBT protocol is very demanding. It was not, however, optimized for latency — which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board [5] equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

  4. Basic principles of accounting and control of nuclear materials in the BOR-60 experimental fast reactor

    International Nuclear Information System (INIS)

    Gryazev, V.M.; Gadzhiev, G.I.; Alekseev, I.N.

    1979-01-01

    Under a contract with the International Atomic Energy Agency, the V.I. Lenin Atomic Reactor Research Institute is currently carrying out a study of ways of organizing a nuclear materials accounting and control system for the BOR-60 fast reactor. Some results of this study are presented in the paper. The special physical and technological features of fast reactors create additional difficulties in safeguards systems and give rise to a number of new possibilities for the illicit removal of nuclear materials. These questions are discussed with reference to the BOR-60 reactor but the conclusions are probably applicable to all fast reactors. The proposed accounting and control system is based on non-destructive measurements of the amount of fissile materials in the operating fuel assemblies and screened bundles of the reactor, on the independent control of the principal facility parameters (a list of which is given) and on an automated information collection and evaluation system. Visual means of inspection can be very effective in fast reactor safeguards systems, especially for controlling storage, but they are not used with the BOR-60 reactor. (author)

  5. A Control Algorithm for Electric Vehicle Fast Charging Stations Equipped with Flywheel Energy Storage Systems

    DEFF Research Database (Denmark)

    Sun, Bo; Dragicevic, Tomislav; Freijedo Fernandez, Francisco Daniel

    2016-01-01

    This paper proposes a control strategy for plugin electric vehicle (PEV) fast charging station (FCS) equipped with a flywheel energy storage system (FESS). The main role of the FESS is not to compromise the predefined charging profile of PEV battery during the provision of a hysteresis-type active...

  6. Two-Level Control for Fast Electrical Vehicle Charging Stations with Multi Flywheel Energy Storage System

    DEFF Research Database (Denmark)

    SUN, BO; Dragicevic, Tomislav; Vasquez, Juan Carlos

    2015-01-01

    This paper applies a hierarchical control for a fast charging station (FCS) composed of paralleled PWM rectifier and dedicated paralleled multiple flywheel energy storage systems (FESSs), in order to mitigate peak power shock on grid caused by sudden connection of electrical vehicle (EV) chargers...

  7. An Improved Rotary Interpolation Based on FPGA

    Directory of Open Access Journals (Sweden)

    Mingyu Gao

    2014-08-01

    Full Text Available This paper presents an improved rotary interpolation algorithm, which consists of a standard curve interpolation module and a rotary process module. Compared to the conventional rotary interpolation algorithms, the proposed rotary interpolation algorithm is simpler and more efficient. The proposed algorithm was realized on a FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe, which uses rotary ellipse and rotary parabolic as an example. According to the theoretical analysis and practical process validation, the algorithm has the following advantages: firstly, less arithmetic items is conducive for interpolation operation; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

  8. An FPGA-Based Electronic Cochlea

    Directory of Open Access Journals (Sweden)

    M. P. Leong

    2003-06-01

    Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

  9. Guide to FPGA Implementation of Arithmetic Functions

    CERN Document Server

    Deschamps, Jean-Pierre; Cantó, Enrique

    2012-01-01

    This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components.  The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption.  This is not a book on algorithms.  It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others.  Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

  10. Global fast dynamic terminal sliding mode control for a quadrotor UAV.

    Science.gov (United States)

    Xiong, Jing-Jing; Zhang, Guo-Bao

    2017-01-01

    A control method based on global fast dynamic terminal sliding mode control (TSMC) technique is proposed to design the flight controller for performing the finite-time position and attitude tracking control of a small quadrotor UAV. Firstly, the dynamic model of the quadrotor is divided into two subsystems, i.e., a fully actuated subsystem and an underactuated subsystem. Secondly, the dynamic flight controllers of the quadrotor are formulated based on global fast dynamic TSMC, which is able to guarantee that the position and velocity tracking errors of all system state variables converge to zero in finite-time. Moreover, the global fast dynamic TSMC is also able to eliminate the chattering phenomenon caused by the switching control action and realize the high precision performance. In addition, the stabilities of two subsystems are demonstrated by Lyapunov theory, respectively. Lastly, the simulation results are given to illustrate the effectiveness and robustness of the proposed control method in the presence of external disturbances. Copyright © 2016 ISA. Published by Elsevier Ltd. All rights reserved.

  11. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  12. An FPGA-based reconfigurable DDC algorithm

    Science.gov (United States)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  13. Research on Precision Tracking on Fast Steering Mirror and Control Strategy

    Science.gov (United States)

    Di, Lin; Yi-ming, Wu; Fan, Zhu

    2018-01-01

    Fast steering mirror is a device used for controlling the beam direction precisely. Due to the short travel of the push-pull FSM, a compound fast steering mirror system driven by both limited-angle voice coil motor and push-pull FSM together is proposed. In the compound FSM system, limited-angle voice coil motor quickly swings at wide angle, while the push-pull FSM do high frequency movement in a small range, which provides the system with the high bandwidth and long travel. In the control strategy, the method of combining feed-forward control in Kalman filtering with auto-disturbance rejection control is used to improve trajectory tracking accuracy. The simulation result shows that tracking accuracy measured by the compound method can be improved by more than 5 times than that of the conventional PID.

  14. FPGA remote update for nuclear environments

    Energy Technology Data Exchange (ETDEWEB)

    Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

    2015-07-01

    The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

  15. FPGA Implementation of Heart Rate Monitoring System.

    Science.gov (United States)

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  16. Multivariable PD controller design for fast chaos synchronization of Lur'e systems

    International Nuclear Information System (INIS)

    Wen, Guilin; Wang, Qing-Guo; He, Yong; Ye, Zhen

    2007-01-01

    In this Letter, a strategy for fast master-slave synchronization is proposed for Lur'e systems under PD control based on the free-weighting matrix approach and the S-procedure. The purpose of the derivative action is to improve the closed-loop stability and speed synchronization response. The proposed strategy covers the existing result for the proportional control alone as a special case. This approach is illustrated by the Chua's chaotic circuit system

  17. Fuel cycle facility control system for the Integral Fast Reactor Program

    International Nuclear Information System (INIS)

    Benedict, R.W.; Tate, D.A.

    1993-01-01

    As part of the Integral Fast Reactor (IFR) Fuel Demonstration, a new distributed control system designed, implemented and installed. The Fuel processes are a combination of chemical and machining processes operated remotely. To meet this special requirement, the new control system provides complete sequential logic control motion and positioning control and continuous PID loop control. Also, a centralized computer system provides near-real time nuclear material tracking, product quality control data archiving and a centralized reporting function. The control system was configured to use programmable logic controllers, small logic controllers, personal computers with touch screens, engineering work stations and interconnecting networks. By following a structured software development method the operator interface was standardized. The system has been installed and is presently being tested for operations

  18. Instrumentation and control of future sodium cooled fast reactors - Design improvements

    International Nuclear Information System (INIS)

    Madhusoodanan, K.; Sakthivel, M.; Chellapandi, P.

    2013-06-01

    India's fast reactor program started with the 40 MWt Fast Breeder Test Reactor. 500 MWe Prototype Fast Breeder Reactor (PFBR) is currently under construction at Kalpakkam. Safety of PFBR is enhanced by improved design features of I and C system. Since the design of Instrumentation and control (I and C) of PFBR, considerable improvements in terms of advancement in technology and indigenization has taken place. Further improvements in I and C is proposed for solving many of the difficulties faced during the design and construction phases of PFBR. Design improvements proposed are covered in this paper which will make the implementation and maintenance of I and C of future SFRs easier. (authors)

  19. High-definition video display based on the FPGA and THS8200

    Science.gov (United States)

    Qian, Jia; Sui, Xiubao

    2014-11-01

    This paper presents a high-definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data-storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high-definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I2C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high-definition video display, which conforms to the input requirements of the new high-definition display devices.

  20. Application of hafnium hydride control rod to large sodium cooled fast breeder reactor

    Energy Technology Data Exchange (ETDEWEB)

    Ikeda, Kazumi, E-mail: kazumi_ikeda@mfbr.mhi.co.jp [Mitsubishi FBR Systems, Inc., 34-17, Jingumae 2-Chome, Shibuya-ku, Tokyo 150-0001 (Japan); Moriwaki, Hiroyuki, E-mail: hiroyuki_moriwaki@mfbr.mhi.co.jp [Mitsubishi FBR Systems, Inc., 34-17, Jingumae 2-Chome, Shibuya-ku, Tokyo 150-0001 (Japan); Ohkubo, Yoshiyuki, E-mail: yoshiyuki_okubo@mfbr.mhi.co.jp [Mitsubishi FBR Systems, Inc., 34-17, Jingumae 2-Chome, Shibuya-ku, Tokyo 150-0001 (Japan); Iwasaki, Tomohiko, E-mail: tomohiko.iwasaki@qse.tohoku.ac.jp [Department of Quantum Science and Energy Engineering, Tohoku University, Aoba, Aramaki, Aoba-ku, Sendai-shi, Miyagi-ken 980-8579 (Japan); Konashi, Kenji, E-mail: konashi@imr.tohoku.ac.jp [Institute for Materials Research, Tohoku University, Narita-cho, Oarai-machi, Higashi-Ibaraki-gun, Ibaraki-ken 311-1313 (Japan)

    2014-10-15

    Highlights: • Application of hafnium hydride control rod to large sodium cooled fast breeder reactor. • This paper treats application of an innovative hafnium hydride control rod to a large sodium cooled fast breeder reactor. • Hydrogen absorption triples the reactivity worth by neutron spectrum shift at H/Hf ratio of 1.3. • Lifetime of the control rod quadruples because produced daughters of hafnium isotopes are absorbers. • Nuclear and thermal hydraulic characteristics of the reactor are as good as or better than B-10 enriched boron carbide. - Abstract: This study treats the feasibility of long-lived hafnium hydride control rod in a large sodium-cooled fast breeder reactor by nuclear and thermal analyses. According to the nuclear calculations, it is found that hydrogen absorption of hafnium triples the reactivity by the neutron spectrum shift at the H/Hf ratio of 1.3, and a hafnium transmutation mechanism that produced daughters are absorbers quadruples the lifetime due to a low incineration rate of absorbing nuclides under irradiation. That is to say, the control rod can function well for a long time because an irradiation of 2400 EFPD reduces the reactivity by only 4%. The calculation also reveals that the hafnium hydride control rod can apply to the reactor in that nuclear and thermal characteristics become as good as or better than 80% B-10 enriched boron carbide. For example, the maximum linear heat rate becomes 3% lower. Owing to the better power distribution, the required flow rate decreases approximately by 1%. Consequently, it is concluded on desk analyses that the long lived hafnium hydride control rod is feasible in the large sodium-cooled fast breeder reactor.

  1. Implementation of FPGA-Based Diverse Protection System

    International Nuclear Information System (INIS)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

    2015-01-01

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

  2. Implementation of FPGA-Based Diverse Protection System

    Energy Technology Data Exchange (ETDEWEB)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

    2015-10-15

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

  3. Fuzzy logic type 1 and type 2 based on LabVIEW FPGA

    CERN Document Server

    Ponce-Cruz, Pedro; MacCleery, Brian

    2016-01-01

    This book is a comprehensive introduction to LabVIEW FPGA™, a package allowing the programming of intelligent digital controllers in field programmable gate arrays (FPGAs) using graphical code. It shows how both potential difficulties with understanding and programming in VHDL and the consequent difficulty and slowness of implementation can be sidestepped. The text includes a clear theoretical explanation of fuzzy logic (type 1 and type 2) with case studies that implement the theory and systematically demonstrate the implementation process. It goes on to describe basic and advanced levels of programming LabVIEW FPGA and show how implementation of fuzzy-logic control in FPGAs improves system responses. A complete toolkit for implementing fuzzy controllers in LabVIEW FPGA has been developed with the book so that readers can generate new fuzzy controllers and deploy them immediately. Problems and their solutions allow readers to practice the techniques and to absorb the theoretical ideas as they arise. Fuzzy L...

  4. Fast engineering optimization: A novel highly effective control parameterization approach for industrial dynamic processes.

    Science.gov (United States)

    Liu, Ping; Li, Guodong; Liu, Xinggao

    2015-09-01

    Control vector parameterization (CVP) is an important approach of the engineering optimization for the industrial dynamic processes. However, its major defect, the low optimization efficiency caused by calculating the relevant differential equations in the generated nonlinear programming (NLP) problem repeatedly, limits its wide application in the engineering optimization for the industrial dynamic processes. A novel highly effective control parameterization approach, fast-CVP, is first proposed to improve the optimization efficiency for industrial dynamic processes, where the costate gradient formulae is employed and a fast approximate scheme is presented to solve the differential equations in dynamic process simulation. Three well-known engineering optimization benchmark problems of the industrial dynamic processes are demonstrated as illustration. The research results show that the proposed fast approach achieves a fine performance that at least 90% of the computation time can be saved in contrast to the traditional CVP method, which reveals the effectiveness of the proposed fast engineering optimization approach for the industrial dynamic processes. Copyright © 2015 ISA. Published by Elsevier Ltd. All rights reserved.

  5. Versatile synchronized real-time MEG hardware controller for large-scale fast data acquisition

    Science.gov (United States)

    Sun, Limin; Han, Menglai; Pratt, Kevin; Paulson, Douglas; Dinh, Christoph; Esch, Lorenz; Okada, Yoshio; Hämäläinen, Matti

    2017-05-01

    Versatile controllers for accurate, fast, and real-time synchronized acquisition of large-scale data are useful in many areas of science, engineering, and technology. Here, we describe the development of a controller software based on a technique called queued state machine for controlling the data acquisition (DAQ) hardware, continuously acquiring a large amount of data synchronized across a large number of channels (>400) at a fast rate (up to 20 kHz/channel) in real time, and interfacing with applications for real-time data analysis and display of electrophysiological data. This DAQ controller was developed specifically for a 384-channel pediatric whole-head magnetoencephalography (MEG) system, but its architecture is useful for wide applications. This controller running in a LabVIEW environment interfaces with microprocessors in the MEG sensor electronics to control their real-time operation. It also interfaces with a real-time MEG analysis software via transmission control protocol/internet protocol, to control the synchronous acquisition and transfer of the data in real time from >400 channels to acquisition and analysis workstations. The successful implementation of this controller for an MEG system with a large number of channels demonstrates the feasibility of employing the present architecture in several other applications.

  6. Voluntary Fasting to Control Post-Ramadan Weight Gain among Overweight and Obese Women

    Directory of Open Access Journals (Sweden)

    Suriani Ismail

    2015-01-01

    Full Text Available Objectives: This study aimed to examine the effectiveness of an Islamic voluntary fasting intervention to control post-Ramadan weight gain. Methods: This study was conducted between July and November 2011. Two weight loss intervention programmes were developed and implemented among groups of overweight or obese Malay women living in the Malaysian cities of Putrajaya and Seremban: a standard programme promoting control of food intake according to national dietary guidelines (group B and a faith-based programme promoting voluntary fasting in addition to the standard programme (group A. Participants’ dietary practices (i.e., voluntary fasting practices, frequency of fruit/vegetable consumption per week and quantity of carbohydrates/protein consumed per day, body mass index (BMI, blood pressure, fasting blood high-density lipoprotein cholesterol (HDL-C and total cholesterol (TC:HDL-C ratio were assessed before Ramadan and three months post-Ramadan. Results: Voluntary fasting practices increased only in group A (P <0.01. Additionally, the quantity of protein/carbohydrates consumed per day, mean diastolic pressure and TC:HDL-C ratio decreased only in group A (P <0.01, 0.05, 0.02 and <0.01, respectively. Frequency of fruit/vegetable consumption per week, as well as HDL-C levels, increased only in group A (P = 0.03 and <0.01, respectively. Although changes in BMI between the groups was not significant (P = 0.08, BMI decrease among participants in group A was significant (P <0.01. Conclusion: Control of post-Ramadan weight gain was more evident in the faith-based intervention group. Healthcare providers should consider faith-based interventions to encourage weight loss during Ramadan and to prevent post-Ramadan weight gain among patients.

  7. Voluntary Fasting to Control Post-Ramadan Weight Gain among Overweight and Obese Women

    Science.gov (United States)

    Ismail, Suriani; Shamsuddin, Khadijah; Latiff, Khalib A.; Saad, Hazizi A.; Majid, Latifah A.; Othman, Fadlan M.

    2015-01-01

    Objectives: This study aimed to examine the effectiveness of an Islamic voluntary fasting intervention to control post-Ramadan weight gain. Methods: This study was conducted between July and November 2011. Two weight loss intervention programmes were developed and implemented among groups of overweight or obese Malay women living in the Malaysian cities of Putrajaya and Seremban: a standard programme promoting control of food intake according to national dietary guidelines (group B) and a faith-based programme promoting voluntary fasting in addition to the standard programme (group A). Participants’ dietary practices (i.e., voluntary fasting practices, frequency of fruit/vegetable consumption per week and quantity of carbohydrates/protein consumed per day), body mass index (BMI), blood pressure, fasting blood high-density lipoprotein cholesterol (HDL-C) and total cholesterol (TC):HDL-C ratio were assessed before Ramadan and three months post-Ramadan. Results: Voluntary fasting practices increased only in group A (P <0.01). Additionally, the quantity of protein/carbohydrates consumed per day, mean diastolic pressure and TC:HDL-C ratio decreased only in group A (P <0.01, 0.05, 0.02 and <0.01, respectively). Frequency of fruit/vegetable consumption per week, as well as HDL-C levels, increased only in group A (P = 0.03 and <0.01, respectively). Although changes in BMI between the groups was not significant (P = 0.08), BMI decrease among participants in group A was significant (P <0.01). Conclusion: Control of post-Ramadan weight gain was more evident in the faith-based intervention group. Healthcare providers should consider faith-based interventions to encourage weight loss during Ramadan and to prevent post-Ramadan weight gain among patients. PMID:25685394

  8. Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation

    Science.gov (United States)

    Yokoyama, Yoshiaki; Kim, Minseok; Arai, Hiroyuki

    At present, when using space-time processing techniques with multiple antennas for mobile radio communication, real-time weight adaptation is necessary. Due to the progress of integrated circuit technology, dedicated processor implementation with ASIC or FPGA can be employed to implement various wireless applications. This paper presents a resource and performance evaluation of the QRD-RLS systolic array processor based on fixed-point CORDIC algorithm with FPGA. In this paper, to save hardware resources, we propose the shared architecture of a complex CORDIC processor. The required precision of internal calculation, the circuit area for the number of antenna elements and wordlength, and the processing speed will be evaluated. The resource estimation provides a possible processor configuration with a current FPGA on the market. Computer simulations assuming a fading channel will show a fast convergence property with a finite number of training symbols. The proposed architecture has also been implemented and its operation was verified by beamforming evaluation through a radio propagation experiment.

  9. Multichannel FPGA based MVT system for high precision time (20 ps RMS) and charge measurement

    Science.gov (United States)

    Pałka, M.; Strzempek, P.; Korcyl, G.; Bednarski, T.; Niedźwiecki, Sz.; Białas, P.; Czerwiński, E.; Dulski, K.; Gajos, A.; Głowacz, B.; Gorgol, M.; Jasińska, B.; Kamińska, D.; Kajetanowicz, M.; Kowalski, P.; Kozik, T.; Krzemień, W.; Kubicz, E.; Mohhamed, M.; Raczyński, L.; Rudy, Z.; Rundel, O.; Salabura, P.; Sharma, N. G.; Silarski, M.; Smyrski, J.; Strzelecki, A.; Wieczorek, A.; Wiślicki, W.; Zieliński, M.; Zgardzińska, B.; Moskal, P.

    2017-08-01

    In this article it is presented an FPGA based Multi-Voltage Threshold (MVT) system which allows of sampling fast signals (1-2 ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time measurement of 20 ps RMS and reconstruct charge of signals, using a simple approach, with deviation from real value smaller than 10%. Utilization of the differential inputs of an FPGA chip as comparators together with an implementation of a TDC inside an FPGA allowed us to achieve a compact multi-channel system characterized by low power consumption and low production costs. This paper describes realization and functioning of the system comprising 192-channel TDC board and a four mezzanine cards which split incoming signals and discriminate them. The boards have been used to validate a newly developed Time-of-Flight Positron Emission Tomography system based on plastic scintillators. The achieved full system time resolution of σ(TOF) ≈ 68 ps is by factor of two better with respect to the current TOF-PET systems.

  10. FPGA Implementation of the Coupled Filtering Method and the Affine Warping Method.

    Science.gov (United States)

    Zhang, Chen; Liang, Tianzhu; Mok, Philip K T; Yu, Weichuan

    2017-07-01

    In ultrasound image analysis, the speckle tracking methods are widely applied to study the elasticity of body tissue. However, "feature-motion decorrelation" still remains as a challenge for the speckle tracking methods. Recently, a coupled filtering method and an affine warping method were proposed to accurately estimate strain values, when the tissue deformation is large. The major drawback of these methods is the high computational complexity. Even the graphics processing unit (GPU)-based program requires a long time to finish the analysis. In this paper, we propose field-programmable gate array (FPGA)-based implementations of both methods for further acceleration. The capability of FPGAs on handling different image processing components in these methods is discussed. A fast and memory-saving image warping approach is proposed. The algorithms are reformulated to build a highly efficient pipeline on FPGA. The final implementations on a Xilinx Virtex-7 FPGA are at least 13 times faster than the GPU implementation on the NVIDIA graphic card (GeForce GTX 580).

  11. Study on modulation amplitude stabilization method for PEM based on FPGA in atomic magnetometer

    Science.gov (United States)

    Wang, Qinghua; Quan, Wei; Duan, Lihong

    2017-10-01

    Atomic magnetometer which uses atoms as sensitive elements have ultra-high precision and has wide applications in scientific researches. The photoelastic modulation method based on photoelastic modulator (PEM) is used in the atomic magnetometer to detect the small optical rotation angle of a linearly polarized light. However, the modulation amplitude of the PEM will drift due to the environmental factors, which reduces the precision and long-term stability of the atomic magnetometer. Consequently, stabilizing the PEM's modulation amplitude is essential to precision measurement. In this paper, a modulation amplitude stabilization method for PEM based on Field Programmable Gate Array (FPGA) is proposed. The designed control system contains an optical setup and an electrical part. The optical setup is used to measure the PEM's modulation amplitude. The FPGA chip, with the PID control algorithm implemented in it, is used as the electrical part's micro controller. The closed loop control method based on the photoelastic modulation detection system can directly measure the PEM's modulation amplitude in real time, without increasing the additional optical devices. In addition, the operating speed of the modulation amplitude stabilization control system can be greatly improved because of the FPGA's parallel computing feature, and the PID control algorithm ensures flexibility to meet different needs of the PEM's modulation amplitude set values. The Modelsim simulation results show the correctness of the PID control algorithm, and the long-term stability of the PEM's modulation amplitude reaches 0.35% in a 3-hour continuous measurement.

  12. High-Resolution Fast-Neutron Spectrometry for Arms Control and Treaty Verification

    Energy Technology Data Exchange (ETDEWEB)

    David L. Chichester; James T. Johnson; Edward H. Seabury

    2012-07-01

    Many nondestructive nuclear analysis techniques have been developed to support the measurement needs of arms control and treaty verification, including gross photon and neutron counting, low- and high-resolution gamma spectrometry, time-correlated neutron measurements, and photon and neutron imaging. One notable measurement technique that has not been extensively studied to date for these applications is high-resolution fast-neutron spectrometry (HRFNS). Applied for arms control and treaty verification, HRFNS has the potential to serve as a complimentary measurement approach to these other techniques by providing a means to either qualitatively or quantitatively determine the composition and thickness of non-nuclear materials surrounding neutron-emitting materials. The technique uses the normally-occurring neutrons present in arms control and treaty verification objects of interest as an internal source of neutrons for performing active-interrogation transmission measurements. Most low-Z nuclei of interest for arms control and treaty verification, including 9Be, 12C, 14N, and 16O, possess fast-neutron resonance features in their absorption cross sections in the 0.5- to 5-MeV energy range. Measuring the selective removal of source neutrons over this energy range, assuming for example a fission-spectrum starting distribution, may be used to estimate the stoichiometric composition of intervening materials between the neutron source and detector. At a simpler level, determination of the emitted fast-neutron spectrum may be used for fingerprinting 'known' assemblies for later use in template-matching tests. As with photon spectrometry, automated analysis of fast-neutron spectra may be performed to support decision making and reporting systems protected behind information barriers. This paper will report recent work at Idaho National Laboratory to explore the feasibility of using HRFNS for arms control and treaty verification applications, including simulations

  13. NetCDF based data archiving system applied to ITER Fast Plant System Control prototype

    International Nuclear Information System (INIS)

    Castro, R.; Vega, J.; Ruiz, M.; De Arcas, G.; Barrera, E.; López, J.M.; Sanz, D.; Gonçalves, B.; Santos, B.; Utzel, N.; Makijarvi, P.

    2012-01-01

    Highlights: ► Implementation of a data archiving solution for a Fast Plant System Controller (FPSC) for ITER CODAC. ► Data archiving solution based on scientific NetCDF-4 file format and Lustre storage clustering. ► EPICS control based solution. ► Tests results and detailed analysis of using NetCDF-4 and clustering technologies on fast acquisition data archiving. - Abstract: EURATOM/CIEMAT and Technical University of Madrid (UPM) have been involved in the development of a FPSC (Fast Plant System Control) prototype for ITER, based on PXIe (PCI eXtensions for Instrumentation). One of the main focuses of this project has been data acquisition and all the related issues, including scientific data archiving. Additionally, a new data archiving solution has been developed to demonstrate the obtainable performances and possible bottlenecks of scientific data archiving in Fast Plant System Control. The presented system implements a fault tolerant architecture over a GEthernet network where FPSC data are reliably archived on remote, while remaining accessible to be redistributed, within the duration of a pulse. The storing service is supported by a clustering solution to guaranty scalability, so that FPSC management and configuration may be simplified, and a unique view of all archived data provided. All the involved components have been integrated under EPICS (Experimental Physics and Industrial Control System), implementing in each case the necessary extensions, state machines and configuration process variables. The prototyped solution is based on the NetCDF-4 (Network Common Data Format) file format in order to incorporate important features, such as scientific data models support, huge size files management, platform independent codification, or single-writer/multiple-readers concurrency. In this contribution, a complete description of the above mentioned solution is presented, together with the most relevant results of the tests performed, while focusing in the

  14. Model-Based Evolution of a Fast Hybrid Fuzzy Adaptive Controller for a Pneumatic Muscle Actuator

    Directory of Open Access Journals (Sweden)

    Alexander Hošovský

    2012-07-01

    Full Text Available Pneumatic artificial muscle-based robotic systems usually necessitate the use of various nonlinear control techniques in order to improve their performance. Their robustness to parameter variation, which is generally difficult to predict, should also be tested. Here a fast hybrid adaptive control is proposed, where a conventional PD controller is placed into the feedforward branch and a fuzzy controller is placed into the adaptation branch. The fuzzy controller compensates for the actions of the PD controller under conditions of inertia moment variation. The fuzzy controller of Takagi-Sugeno type is evolved through a genetic algorithm using the dynamic model of a pneumatic muscle actuator. The results confirm the capability of the designed system to provide robust performance under the conditions of varying inertia.

  15. A Decentralized Current-Sharing Controller Endows Fast Transient Response to Parallel DC-DC Converters

    DEFF Research Database (Denmark)

    Wang, Haojie; Han, Minxiao; Han, Renke

    2018-01-01

    This paper proposes a decentralized current-sharing control strategy to endow fast transient response to paralleled DC-DC converters systems, such as DC microgrids or distributed power systems. The proposed controller consist of two main control loops: an external voltage droop control for current......-sharing proposes and an internal current loop. The external droop control loop is designed as a voltage loop with embedded virtual impedance, which avoids the use of a slow voltage loop and a separate extra virtual impedance loop that may limit the system bandwidth. The internal current loop, thanks...... and the proposed embedded-virtual-impedance based I-V droop. In order to compare the dynamic response performances between two droop controllers, their state-space models have been developed and analyzed in this paper. The results show that the dynamic response of the I-V droop control is faster than...

  16. Identification and adoptive multivariable control method. Application to fast breeder nuclear reactors

    International Nuclear Information System (INIS)

    Dang Van Mien, H.; Irving, E.; Rousseau, I.

    1982-01-01

    Motivated by the limitations inherent in the standard approach, a new model reference multivariable adaptive control method is described. This latter control method utilizes as a design tool a simple vector difference equation of the controlled system. The adaptive control method is of the series-parallel direct reference model type and the adjustment algorithm is the standard least squares estimation technics with hyperstability conditions, controlled convergence speed forgetting, regularization and threshold operations. Numerical results are presented which illustrate the interest of the latter approach. The precise problem which has been tackled is the control of the steam generator of the second fast breeder French nuclear reactor called Super-Phenix. After a short description of the plant and its responses at different loads, the principles and the performances of the standard technique control scheme which has been adopted are discussed [fr

  17. Semivariogram Analysis of Bone Images Implemented on FPGA Architectures.

    Science.gov (United States)

    Shirvaikar, Mukul; Lagadapati, Yamuna; Dong, Xuanliang

    2017-03-01

    Osteoporotic fractures are a major concern for the healthcare of elderly and female populations. Early diagnosis of patients with a high risk of osteoporotic fractures can be enhanced by introducing second-order statistical analysis of bone image data using techniques such as variogram analysis. Such analysis is computationally intensive thereby creating an impediment for introduction into imaging machines found in common clinical settings. This paper investigates the fast implementation of the semivariogram algorithm, which has been proven to be effective in modeling bone strength, and should be of interest to readers in the areas of computer-aided diagnosis and quantitative image analysis. The semivariogram is a statistical measure of the spatial distribution of data, and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. A semi-variance, γ ( h ), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h . Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O ( n 2 ) Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current

  18. Optimal Orientation Planning and Control Deviation Estimation on FAST Cable-Driven Parallel Robot

    Directory of Open Access Journals (Sweden)

    Hui Li

    2014-03-01

    Full Text Available The paper is devoted theoretically to the optimal orientation planning and control deviation estimation of FAST cable-driven parallel robot. Regarding the robot characteristics, the solutions are obtained from two constrained optimizations, both of which are based on the equilibrium of the cabin and the attention on force allocation among 6 cable tensions. A kind of control algorithm is proposed based on the position and force feedbacks. The analysis proves that the orientation control depends on force feedback and the optimal tension solution corresponding to the planned orientation. Finally, the estimation of orientation deviation is given under the limit range of tension errors.

  19. Automatic generation of application specific FPGA multicore accelerators

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

    2014-01-01

    High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

  20. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    -the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

  1. Periodic boundary conditions and the error-controlled fast multipole method

    Energy Technology Data Exchange (ETDEWEB)

    Kabadshow, Ivo

    2012-08-22

    The simulation of pairwise interactions in huge particle ensembles is a vital issue in scientific research. Especially the calculation of long-range interactions poses limitations to the system size, since these interactions scale quadratically with the number of particles. Fast summation techniques like the Fast Multipole Method (FMM) can help to reduce the complexity to O(N). This work extends the possible range of applications of the FMM to periodic systems in one, two and three dimensions with one unique approach. Together with a tight error control, this contribution enables the simulation of periodic particle systems for different applications without the need to know and tune the FMM specific parameters. The implemented error control scheme automatically optimizes the parameters to obtain an approximation for the minimal runtime for a given energy error bound.

  2. Time-delayed chameleon: Analysis, synchronization and FPGA implementation

    Science.gov (United States)

    Rajagopal, Karthikeyan; Jafari, Sajad; Laarem, Guessas

    2017-12-01

    In this paper we report a time-delayed chameleon-like chaotic system which can belong to different families of chaotic attractors depending on the choices of parameters. Such a characteristic of self-excited and hidden chaotic flows in a simple 3D system with time delay has not been reported earlier. Dynamic analysis of the proposed time-delayed systems are analysed in time-delay space and parameter space. A novel adaptive modified functional projective lag synchronization algorithm is derived for synchronizing identical time-delayed chameleon systems with uncertain parameters. The proposed time-delayed systems and the synchronization algorithm with controllers and parameter estimates are then implemented in FPGA using hardware-software co-simulation and the results are presented.

  3. Method to implement the CCD timing generator based on FPGA

    Science.gov (United States)

    Li, Binhua; Song, Qian; He, Chun; Jin, Jianhui; He, Lin

    2010-07-01

    With the advance of the PFPA technology, the design methodology of digital systems is changing. In recent years we develop a method to implement the CCD timing generator based on FPGA and VHDL. This paper presents the principles and implementation skills of the method. Taking a developed camera as an example, we introduce the structure, input and output clocks/signals of a timing generator implemented in the camera. The generator is composed of a top module and a bottom module. The bottom one is made up of 4 sub-modules which correspond to 4 different operation modes. The modules are implemented by 5 VHDL programs. Frame charts of the architecture of these programs are shown in the paper. We also describe implementation steps of the timing generator in Quartus II, and the interconnections between the generator and a Nios soft core processor which is the controller of this generator. Some test results are presented in the end.

  4. FFTF [Fast Flux Test Facility] performance measurements for safety, productivity and control

    International Nuclear Information System (INIS)

    Newland, D.J.; Praetorius, P.R.; Tomaszewski, T.A.

    1987-05-01

    A useful set of performance measurements for Safety, Productivity and Control has evolved at the Fast Flux Test Facility (FFTF). In response to declining budgets and the resulting need to safely manage a manpower rampdown, an ''Early Warning System'' was developed in 1984. Its purpose was to monitor the effects of the staffing rampdown such that appropriate remedial action could be taken to correct adverse trends before a significant problem occurred. 1 tab

  5. Application of MEMS Accelerometers and Gyroscopes in Fast Steering Mirror Control Systems

    Directory of Open Access Journals (Sweden)

    Jing Tian

    2016-03-01

    Full Text Available In a charge-coupled device (CCD-based fast steering mirror (FSM tracking control system, high control bandwidth is the most effective way to enhance the closed-loop performance. However, the control system usually suffers a great deal from mechanical resonances and time delays induced by the low sampling rate of CCDs. To meet the requirements of high precision and load restriction, fiber-optic gyroscopes (FOGs are usually used in traditional FSM tracking control systems. In recent years, the MEMS accelerometer and gyroscope are becoming smaller and lighter and their performance have improved gradually, so that they can be used in a fast steering mirror (FSM to realize the stabilization of the line-of-sight (LOS of the control system. Therefore, a tentative approach to implement a CCD-based FSM tracking control system, which uses MEMS accelerometers and gyroscopes as feedback components and contains an acceleration loop, a velocity loop and a position loop, is proposed. The disturbance suppression of the proposed method is the product of the error attenuation of the acceleration loop, the velocity loop and the position loop. Extensive experimental results show that the MEMS accelerometers and gyroscopes can act the similar role as the FOG with lower cost for stabilizing the LOS of the FSM tracking control system.

  6. Correlation between pre-ramadan glycemic control and subsequent glucose fluctuation during fasting in adolescents with Type 1 diabetes.

    Science.gov (United States)

    Afandi, B; Kaplan, W; Al Hassani, N; Hadi, S; Mohamed, A

    2017-07-01

    Even though patients with type 1 diabetes mellitus (T1DM) are exempted from fasting, the vast majority elect to fast against the advice of their healthcare providers. We have previously reported the incidence of wide fluctuations in blood glucose (BG) along with "unrecognized" severe hypoglycemia during Ramadan fasting in adolescents with T1DM. This report compares the continuous glucose monitoring (CGM) data during fasting in adolescents with T1DM according to their Pre-Ramadan diabetes control. Children and adolescents with T1DM who intended to fast the month of Ramadan were asked to wear the CGM during fasting for a minimum of 3 days. Hypoglycemia, hyperglycemia, and severe hyperglycemia were identified as BG 300 mg/dL (16.7 mmol/L) respectively, while normoglycemia was identified as BG 70-200 mg/dL (3.9-11.1 mmol/L). Patients were categorized as well-controlled (Group 1) and poorly controlled (Group 2) if the pre-fasting HbA1C was ≤8% (64 mmol/mol) and >8%, respectively. We compared the mean BG and the percentages of time spent in hypoglycemia, hyperglycemia, and severe hyperglycemia between the two groups using Chi-square (significant difference when P value was fasting. Our data suggest that optimal glycemic control before Ramadan may reduce the potential risks associated with fasting and minimize glucose fluctuation.

  7. On a mean field game optimal control approach modeling fast exit scenarios in human crowds

    KAUST Repository

    Burger, Martin; Di Francesco, Marco; Markowich, Peter A.; Wolfram, Marie Therese

    2013-01-01

    The understanding of fast exit and evacuation situations in crowd motion research has received a lot of scientific interest in the last decades. Security issues in larger facilities, like shopping malls, sports centers, or festivals necessitate a better understanding of the major driving forces in crowd dynamics. In this paper we present an optimal control approach modeling fast exit scenarios in pedestrian crowds. The model is formulated in the framework of mean field games and based on a parabolic optimal control problem. We consider the case of a large human crowd trying to exit a room as fast as possible. The motion of every pedestrian is determined by minimizing a cost functional, which depends on his/her position and velocity, the overall density of people, and the time to exit. This microscopic setup leads in a mean-field formulation to a nonlinear macroscopic optimal control problem, which raises challenging questions for the analysis and numerical simulations.We discuss different aspects of the mathematical modeling and illustrate them with various computational results. ©2013 IEEE.

  8. On a mean field game optimal control approach modeling fast exit scenarios in human crowds

    KAUST Repository

    Burger, Martin

    2013-12-01

    The understanding of fast exit and evacuation situations in crowd motion research has received a lot of scientific interest in the last decades. Security issues in larger facilities, like shopping malls, sports centers, or festivals necessitate a better understanding of the major driving forces in crowd dynamics. In this paper we present an optimal control approach modeling fast exit scenarios in pedestrian crowds. The model is formulated in the framework of mean field games and based on a parabolic optimal control problem. We consider the case of a large human crowd trying to exit a room as fast as possible. The motion of every pedestrian is determined by minimizing a cost functional, which depends on his/her position and velocity, the overall density of people, and the time to exit. This microscopic setup leads in a mean-field formulation to a nonlinear macroscopic optimal control problem, which raises challenging questions for the analysis and numerical simulations.We discuss different aspects of the mathematical modeling and illustrate them with various computational results. ©2013 IEEE.

  9. Rapid-L Operator-Free Fast Reactor Concept Without Any Control Rods

    International Nuclear Information System (INIS)

    Kambe, Mitsuru; Tsunoda, Hirokazu; Mishima, Kaichiro; Iwamura, Takamichi

    2003-01-01

    The 200-kW(electric) uranium-nitride-fueled lithium-cooled fast reactor concept 'RAPID-L' to achieve highly automated reactor operation has been demonstrated. RAPID-L is designed for a lunar base power system. It is one of the variants of the RAPID (Refueling by All Pins Integrated Design) fast reactor concept, which enables quick and simplified refueling. The essential feature of the RAPID concept is that the reactor core consists of an integrated fuel assembly instead of conventional fuel subassemblies. In this small-size reactor core, 2700 fuel pins are integrated and encased in a fuel cartridge. Refueling is conducted by replacing a fuel cartridge. The reactor can be operated without refueling for up to 10 yr.Unique challenges in reactivity control systems design have been addressed in the RAPID-L concept. The reactor has no control rod but involves the following innovative reactivity control systems: lithium expansion modules (LEM) for inherent reactivity feedback, lithium injection modules (LIM) for inherent ultimate shutdown, and lithium release modules (LRM) for automated reactor startup. All these systems adopt 6 Li as a liquid poison instead of B 4 C rods. In combination with LEMs, LIMs, and LRMs, RAPID-L can be operated without an operator. This reactor concept is also applicable to the terrestrial fast reactors. In this paper, the RAPID-L reactor concept and its transient characteristics are presented

  10. A Fast Event Preprocessor and Sequencer for the Simbol-X Low Energy Detector

    Science.gov (United States)

    Schanz, T.; Tenzer, C.; Maier, D.; Kendziorra, E.; Santangelo, A.

    2009-05-01

    The Simbol-X Low Energy Detector (LED), a 128×128 pixel DEPFET (Depleted Field Effect Transistor) array, will be read out at a very high rate (8000 frames/second) and, therefore, requires a very fast on board electronics. We present an FPGA-based LED camera electronics consisting of an Event Preprocessor (EPP) for on board data preprocessing and filtering of the Simbol-X low-energy detector and a related Sequencer (SEQ) to generate the necessary signals to control the readout.

  11. A Fast Event Preprocessor and Sequencer for the Simbol-X Low Energy Detector

    International Nuclear Information System (INIS)

    Schanz, T.; Tenzer, C.; Maier, D.; Kendziorra, E.; Santangelo, A.

    2009-01-01

    The Simbol-X Low Energy Detector (LED), a 128x128 pixel DEPFET (Depleted Field Effect Transistor) array, will be read out at a very high rate (8000 frames/second) and, therefore, requires a very fast on board electronics. We present an FPGA-based LED camera electronics consisting of an Event Preprocessor (EPP) for on board data preprocessing and filtering of the Simbol-X low-energy detector and a related Sequencer (SEQ) to generate the necessary signals to control the readout.

  12. Fast helicity switching of x-ray circular polarization at beamline P09 at PETRA III

    Energy Technology Data Exchange (ETDEWEB)

    Strempfer, J., E-mail: Joerg.Strempfer@desy.de; Mardegan, J. R. L.; Francoual, S.; Veiga, L. S. I.; Spitzbart, T.; Zink, H. [Deutsches Elektronen Synchrotron (DESY), Notkestrasse 85, 22603 Hamburg (Germany); Bouchenoire, L. [XMaS, ESRF, 6 rue Jules Horowitz, BP220, Grenoble 38043 (France); Department of Physics, University of Liverpool, Liverpool, L69 7ZE (United Kingdom)

    2016-07-27

    At the resonant scattering and diffraction beamline P09 at PETRA III/DESY, polarization manipulation in the X-ray energy range 3-13 keV is possible using wave-plates. Recently, fast flipping of circular polarization helicity using the Raspberry Pi controlled FPGA (PiLC) device developed at DESY and dedicated piezo-electric flippers has been commissioned. Functionality of the PiLC for XMCD and first XMCD measurements at the Fe K-and Dy-L{sub 3} absorption edges are presented.

  13. Using of FPGA coprocessor for improving the execution speed of the pattern recognition algorithm for ATLAS - high energy physics experiment

    CERN Document Server

    Hinkelbein, C; Kugel, A; Männer, R; Miiller, M

    2004-01-01

    Pattern recognition algorithms are used in experimental High Energy physics for getting parameters (features) of particles tracks in detectors. It is particularly important to have fast algorithms in trigger system. This paper investigates the suitability of using FPGA coprocessor for speedup of the TRT-LUT algorithm - one of the feature extraction algorithms for second level trigger for ATLAS experiment (CERN). Two realization of the same algorithm have been compared: C++ realization tested on a computer equipped with dual Xeon 2.4 GHz CPU, 64-bit, 66MHz PCI bus, 1024Mb DDR RAM main memories with Red Hat Linux 7.1 and hybrid C++ - VHDL realisation tested on same PC equipped in addition by MPRACE board (FPGA-Coprocessor board based on Xilinx Virtex-II FPGA and made as 64-bit, 66 MHz PCI card developed at the University of Mannheim). Usage of the FPGA coprocessor can give some reasonable speedup in contrast to general purpose processor only for those algorithms (or parts of algorithms), for which there is a po...

  14. Hyperchaotic Chameleon: Fractional Order FPGA Implementation

    Directory of Open Access Journals (Sweden)

    Karthikeyan Rajagopal

    2017-01-01

    Full Text Available There are many recent investigations on chaotic hidden attractors although hyperchaotic hidden attractor systems and their relationships have been less investigated. In this paper, we introduce a hyperchaotic system which can change between hidden attractor and self-excited attractor depending on the values of parameters. Dynamic properties of these systems are investigated. Fractional order models of these systems are derived and their bifurcation with fractional orders is discussed. Field programmable gate array (FPGA implementations of the systems with their power and resource utilization are presented.

  15. Spacewire Routers Implemented with FPGA Technology

    Science.gov (United States)

    Habinc, Sandi; Isomaki, Marko

    2011-08-01

    Routers are an integral part of SpaceWire networks. Aeroflex Gaisler has developed a highly configurable SpaceWire router VHDL IP core to meet the needs for technology independent router designs. The main design goals have been configurability, technology independence, support of the standard and expandability. The IP core being technologically independent allows it to be used in both ASIC and FPGA technology. The latter is now being used to produce versatile standard products that can reach the market faster than for example an ASIC based product.

  16. Signal compression in radar using FPGA

    OpenAIRE

    Enrique Escamilla Hemández; Víctor Kravchenko; Volodymyr Ponomaryov; Gonzalo Duchen Sánchez; David Hernández Sánchez

    2010-01-01

    El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array). El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR). El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde n...

  17. Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

    Science.gov (United States)

    Cardinali, M.; Dzyhgadlo, R.; Gerhardt, A.; Götzen, K.; Hohler, R.; Kalicy, G.; Kumawat, H.; Lehmann, D.; Lewandowski, B.; Patsyuk, M.; Peters, K.; Schepers, G.; Schmitt, L.; Schwarz, C.; Schwiening, J.; Traxler, M.; Ugur, C.; Zühlsdorf, M.; Dodokhov, V. Kh.; Britting, A.; Eyrich, W.; Lehmann, A.; Uhlig, F.; Düren, M.; Föhl, K.; Hayrapetyan, A.; Kröck, B.; Merle, O.; Rieke, J.; Cowie, E.; Keri, T.; Montgomery, R.; Rosner, G.; Achenbach, P.; Corell, O.; Ferretti Bondy, M. I.; Hoek, M.; Lauth, W.; Rosner, C.; Sfienti, C.; Thiel, M.; Bühler, P.; Gruber, L.; Marton, J.; Suzuki, K.

    2014-12-01

    The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R&D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and fast discriminators. The discriminators also provide time-over-threshold information thus enabling walk corrections to improve the timing resolution. Two types of frontend electronics cards optimised for reading out 64-channel PHOTONIS Planacon MCP-PMTs were tested: one based on the NINO ASIC and the other, called PADIWA, on FPGA discriminators. Promising results were obtained in a full characterisation using a fast laser setup and in a test experiment at MAMI, Mainz, with a small scale DIRC prototype.

  18. Metabolomics of Ramadan fasting: an opportunity for the controlled study of physiological responses to food intake.

    Science.gov (United States)

    Mathew, Sweety; Krug, Susanne; Skurk, Thomas; Halama, Anna; Stank, Antonia; Artati, Anna; Prehn, Cornelia; Malek, Joel A; Kastenmüller, Gabi; Römisch-Margl, Werner; Adamski, Jerzy; Hauner, Hans; Suhre, Karsten

    2014-06-06

    High-throughput screening techniques that analyze the metabolic endpoints of biological processes can identify the contributions of genetic predisposition and environmental factors to the development of common diseases. Studies applying controlled physiological challenges can reveal dysregulation in metabolic responses that may be predictive for or associated with these diseases. However, large-scale epidemiological studies with well controlled physiological challenge conditions, such as extended fasting periods and defined food intake, pose logistic challenges. Culturally and religiously motivated behavioral patterns of life style changes provide a natural setting that can be used to enroll a large number of study volunteers. Here we report a proof of principle study conducted within a Muslim community, showing that a metabolomics study during the Holy Month of Ramadan can provide a unique opportunity to explore the pre-prandial and postprandial response of human metabolism to nutritional challenges. Up to five blood samples were obtained from eleven healthy male volunteers, taken directly before and two hours after consumption of a controlled meal in the evening on days 7 and 26 of Ramadan, and after an over-night fast several weeks after Ramadan. The observed increases in glucose, insulin and lactate levels at the postprandial time point confirm the expected physiological response to food intake. Targeted metabolomics further revealed significant and physiologically plausible responses to food intake by an increase in bile acid and amino acid levels and a decrease in long-chain acyl-carnitine and polyamine levels. A decrease in the concentrations of a number of phospholipids between samples taken on days 7 and 26 of Ramadan shows that the long-term response to extended fasting may differ from the response to short-term fasting. The present study design is scalable to larger populations and may be extended to the study of the metabolic response in defined patient

  19. FPGA-based distributed computing microarchitecture for complex physical dynamics investigation.

    Science.gov (United States)

    Borgese, Gianluca; Pace, Calogero; Pantano, Pietro; Bilotta, Eleonora

    2013-09-01

    In this paper, we present a distributed computing system, called DCMARK, aimed at solving partial differential equations at the basis of many investigation fields, such as solid state physics, nuclear physics, and plasma physics. This distributed architecture is based on the cellular neural network paradigm, which allows us to divide the differential equation system solving into many parallel integration operations to be executed by a custom multiprocessor system. We push the number of processors to the limit of one processor for each equation. In order to test the present idea, we choose to implement DCMARK on a single FPGA, designing the single processor in order to minimize its hardware requirements and to obtain a large number of easily interconnected processors. This approach is particularly suited to study the properties of 1-, 2- and 3-D locally interconnected dynamical systems. In order to test the computing platform, we implement a 200 cells, Korteweg-de Vries (KdV) equation solver and perform a comparison between simulations conducted on a high performance PC and on our system. Since our distributed architecture takes a constant computing time to solve the equation system, independently of the number of dynamical elements (cells) of the CNN array, it allows us to reduce the elaboration time more than other similar systems in the literature. To ensure a high level of reconfigurability, we design a compact system on programmable chip managed by a softcore processor, which controls the fast data/control communication between our system and a PC Host. An intuitively graphical user interface allows us to change the calculation parameters and plot the results.

  20. Specialists' meeting on advanced controls for fast reactors, Argonne, Illinois, USA June 20-22, 1989

    International Nuclear Information System (INIS)

    1989-01-01

    The Specialists' Meeting on ''Advanced Controls for Fast Reactors'' was held in Argonne, Illinois, USA, from June 20 to 22, 1989. The meeting was sponsored by the International Atomic Energy Agency on the recommendation of the IAEA International Working Group on Fast Reactors and was hosted by Argonne National Laboratory and the US Department of Energy. It was attended by 20 participants and observers from Argentina, France, Germany, Japan, India, the USSR, the United Kingdom, the United States of America, and the IAEA. The purpose of the meeting was to provide an opportunity for participating countries to review and discuss their views on design and technology for advanced control in fast reactors. During the meeting papers were presented by the participants on behalf of their countries and organizations. Presentations were followed by open discussions on the subjects covered by the papers and summaries of the discussions were drafted. After the formal sessions were completed, a final discussion session was held and summaries, general conclusions and recommendations were approved by consensus. A separate abstract was prepared for each of the 22 papers presented at this meeting. Refs, figs, tabs, diagrams and photos

  1. FPGA - Based Technology and Systems for I and C of Existing and Advanced Reactors

    International Nuclear Information System (INIS)

    Bachmach, E.; Siora, O.; Tokarev, V.; Reshetytsky, S.; Kharchenko, V.; Bezsalyi, V.

    2011-01-01

    Control systems of modern nuclear installations (including water-cooled, WCR) are based on programmable technologies. Most of control systems modernizations which are implemented at operating nuclear installations are also based on application of programmable technologies. Besides, a range of features and properties is defied for programmable technologies. These features and properties make licensing process more complicated, facilitate appearance of common cause failures, make safety evaluation procedures more complicated, etc. Also it is known that programmable technologies significantly extend the time periods for project realization of new power units construction and modernization of the existing power units, and also it involves rise of its value. Company RADIY has developed the Platform of digital equipment RADIY on FPGA-based technology. In the article there is a description of the features of FPGA-technology developed and applied by Company RADIY, features of the Platform RADIY and systems realized on its base, which allow to minimize significantly above-mentioned negative features and properties of programmable technologies. Technology which realized in Platform RADIY allows to solve the whole set of tasks of control (including regulation) and protection of nuclear installations. Platform RADIY is a combination of the best features of traditional programmable technologies and FPGA-technology. According to the opinion of the authors of this article the technology which is realized in Platform RADIY is the key factor for solving of control and protection tasks of nuclear installations in the nearest future. (author)

  2. FPGA-based prototype of portable environmental radiation monitor

    Energy Technology Data Exchange (ETDEWEB)

    Benahmed, A.; Elkarch, H. [CNESTEN -Centre National de l' Energie des Sciences et Techniques Nucleaires (Morocco)

    2015-07-01

    This new portable radiological environmental monitor consists of 2 main components, Gamma ionization chamber and a FPGA-based electronic enclosure linked to convivial software for treatment and analyzing. The HPIC ion chamber is the heart of this radiation measurement system and is running in range from 0 to 100 mR/h, so that the sensitivity at the output is 20 mV/μR/h, with a nearly flat energy response from 0,07 to 10 MEV. This paper presents a contribution for developing a new nuclear measurement data acquisition system based on Cyclone III FPGA Starter Kit ALTERA, and a user-friendly software to run real-time control and data processing. It was developed to substitute the older radiation monitor RSS-112 PIC installed in CNESTEN's Laboratory in order to improve some of its functionalities related to acquisition time and data memory capacity. As for the associated acquisition software, it was conceived under the virtual LabView platform from National Instrument, and offers a variety of system setup for radiation environmental monitoring. It gives choice to display both the statistical data and the dose rate. Statistical data shows a summary of current data, current time/date and dose integrator values, and the dose rate displays the current dose rate in large numbers for viewing from a distance as well as the date and time. The prototype version of this new instrument and its data processing software has been successfully tested and validated for viewing and monitoring the environmental radiation of Moroccan nuclear center. (authors)

  3. Cryogenic loss monitors with FPGA TDC signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Warner, A.; Wu, J.; /Fermilab

    2011-09-01

    Radiation hard helium gas ionization chambers capable of operating in vacuum at temperatures ranging from 5K to 350K have been designed, fabricated and tested and will be used inside the cryostats at Fermilab's Superconducting Radiofrequency beam test facility. The chamber vessels are made of stainless steel and all materials used including seals are known to be radiation hard and suitable for operation at 5K. The chambers are designed to measure radiation up to 30 kRad/hr with sensitivity of approximately 1.9 pA/(Rad/hr). The signal current is measured with a recycling integrator current-to-frequency converter to achieve a required measurement capability for low current and a wide dynamic range. A novel scheme of using an FPGA-based time-to-digital converter (TDC) to measure time intervals between pulses output from the recycling integrator is employed to ensure a fast beam loss response along with a current measurement resolution better than 10-bit. This paper will describe the results obtained and highlight the processing techniques used.

  4. FPGA implementation of image dehazing algorithm for real time applications

    Science.gov (United States)

    Kumar, Rahul; Kaushik, Brajesh Kumar; Balasubramanian, R.

    2017-09-01

    Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K_BRAM, 97 DSP_48, 6508 FFs and 8159 LUTs.

  5. An FPGA computing demo core for space charge simulation

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Huang, Yifei

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  6. An FPGA computing demo core for space charge simulation

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; Huang, Yifei; /Fermilab

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  7. FPGA-based prototype storage system with phase change memory

    Science.gov (United States)

    Li, Gezi; Chen, Xiaogang; Chen, Bomy; Li, Shunfen; Zhou, Mi; Han, Wenbing; Song, Zhitang

    2016-10-01

    With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

  8. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  9. An FPGA-Based People Detection System

    Directory of Open Access Journals (Sweden)

    James J. Clark

    2005-05-01

    Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

  10. High performance parallel backprojection on FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Pfanner, Florian; Knaup, Michael; Kachelriess, Marc [Erlangen-Nuernberg Univ., Erlangen (Germany). Inst. of Medical Physics (IMP)

    2011-07-01

    Reconstruction of tomographic images, i.e., images from a Computed Tomography scanner, is a very time consuming issue. The most calculation power is needed for the backprojection step. A closer inspection shows that the algorithm for backprojection is easy to parallelize. FPGAs are able to execute many operations in the same time, so a highly parallel algorithm is a requirement for a powerful acceleration. For data flow rate maximization, we realized the backprojection in a pipelined structure with data throughput of one clock cycle. Due the hardware limitations of the FPGA, it is not possible to reconstruct the image as a whole. So it is necessary to split up the image and reconstruct these parts separately. Despite that, a reconstruction of 512 projections into a 5122 image is calculated within 13 ms on a Virtex 5 FPGA. To save hardware resources we use fixed point arithmetic with an accuracy of 23 bit for calculation. A comparison of the result image and an image, calculated with floating point arithmetic on CPU, shows that there are no differences between these images. (orig.)

  11. Signal compression in radar using FPGA

    Directory of Open Access Journals (Sweden)

    Enrique Escamilla Hemández

    2010-01-01

    Full Text Available El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array. El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR. El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde nos centramos en obtener una mejor atenuación para los valores de lóbulos laterales. La arquitectura propuesta explota los recursos de computación paralela de los dispositivos FPGA para alcanzar una mejor velocidad de cómputo. Las investigaciones experimentales han demostrado que los mejores resultados para el funcionamiento de la compresión del pulso se han obtenido usando las funciones atómicas, mejorando el funcionamiento del sistema del radar en presencia de ruido, y consiguiendo una pequeña degradación en la resolución de rango. La puesta en práctica del tratamiento de señales en el sistema de radar en tiempo real se discute y se justifica la eficiencia de la arquitectura de hardware propuesta.

  12. Automated Metabolic P System Placement in FPGA

    Directory of Open Access Journals (Sweden)

    Kulakovskis Darius

    2016-07-01

    Full Text Available An original Very High Speed Integrated Circuit Hardware Description Language (VHDL code generation tool that can be used to automate Metabolic P (MP system implementation in hardware such as Field Programmable Gate Arrays (FPGA is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT, and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP, slice, and 4-input LUT usage.

  13. FPGA-Based Embedded Motion Estimation Sensor

    Directory of Open Access Journals (Sweden)

    Zhaoyi Wei

    2008-01-01

    Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

  14. An improved real time superresolution FPGA system

    Science.gov (United States)

    Lakshmi Narasimha, Pramod; Mudigoudar, Basavaraj; Yue, Zhanfeng; Topiwala, Pankaj

    2009-05-01

    In numerous computer vision applications, enhancing the quality and resolution of captured video can be critical. Acquired video is often grainy and low quality due to motion, transmission bottlenecks, etc. Postprocessing can enhance it. Superresolution greatly decreases camera jitter to deliver a smooth, stabilized, high quality video. In this paper, we extend previous work on a real-time superresolution application implemented in ASIC/FPGA hardware. A gradient based technique is used to register the frames at the sub-pixel level. Once we get the high resolution grid, we use an improved regularization technique in which the image is iteratively modified by applying back-projection to get a sharp and undistorted image. The algorithm was first tested in software and migrated to hardware, to achieve 320x240 -> 1280x960, about 30 fps, a stunning superresolution by 16X in total pixels. Various input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as in FPGA hardware, which gives us a fine balance between the number of bits and performance. The proposed system is robust and highly efficient. We have shown the performance improvement of the hardware superresolution over the software version (C code).

  15. Design issues on using FPGA-based I and C systems in nuclear reactors

    Energy Technology Data Exchange (ETDEWEB)

    Farias, Marcos S.; Carvalho, Paulo Victor R. de; Santos, Isaac Jose A.L. dos; Lacerda, Fabio de, E-mail: msantana@ien.gov.br, E-mail: paulov@ien.gov.br, E-mail: luquetti@ien.gov.br, E-mail: acerda@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Div. de Engenharia Nuclear

    2015-07-01

    The FPGA (field programmable gate array) is widely used in various fields of industry. FPGAs can be used to perform functions that are safety critical and require high reliability, like in automobiles, aircraft control and assistance and mission-critical applications in the aerospace industry. With these merits, FPGAs are receiving increased attention worldwide for application in nuclear plant instrumentation and control (I and C) systems, mainly for Reactor Protection System (RPS). Reasons for this include the fact that conventional analog electronics technologies are become obsolete. I and C systems of new Reactors have been designed to adopt the digital equipment such as PLC (Programmable Logic Controller) and DCS (Distributed Control System). But microprocessors-based systems may not be simply qualified because of its complex characteristics. For example, microprocessor cores execute one instruction at a time, and an operating system is needed to manage the execution of programs. In turn, FPGAs can run without an operating system and the design architecture is inherently parallel. In this paper we aim to assess these and other advantages, and the limitations, on FPGA-based solutions, considering the design guidelines and regulations on the use of FPGAs in Nuclear Plant I and C Systems. We will also examine some circuit design techniques in FPGA to help mitigate failures and provide redundancy. The objective is to show how FPGA-based systems can provide cost-effective options for I and C systems in modernization projects and to the RMB (Brazilian Multipurpose Reactor), ensuring safe and reliable operation, meeting licensing requirements, such as separation, redundancy and diversity. (author)

  16. Revealing Hidden Structural Order Controlling Both Fast and Slow Glassy Dynamics in Supercooled Liquids

    Directory of Open Access Journals (Sweden)

    Hua Tong

    2018-03-01

    Full Text Available The dynamics of a supercooled liquid near the glass transition is characterized by two-step relaxation, fast β and slow α relaxations. Because of the apparently disordered nature of glassy structures, there have been long debates over whether the origin of drastic slowing-down of the α relaxation accompanied by heterogeneous dynamics is thermodynamic or dynamic. Furthermore, it has been elusive whether there is any deep connection between fast β and slow α modes. To settle these issues, here we introduce a set of new structural order parameters characterizing sterically favored structures with high local packing capability, and then access structure-dynamics correlation by a novel nonlocal approach. We find that the particle mobility is under control of the static order parameter field. The fast β process is controlled by the instantaneous order parameter field locally, resulting in short-time particle-scale dynamics. Then the mobility field progressively develops with time t, following the initial order parameter field from disorder to more ordered regions. As is well known, the heterogeneity in the mobility field (dynamic heterogeneity is maximized with a characteristic length ξ_{4}, when t reaches the relaxation time τ_{α}. We discover that this mobility pattern can be predicted solely by a spatial coarse graining of the initial order parameter field at t=0 over a length ξ without any dynamical information. Furthermore, we find a relation ξ∼ξ_{4}, indicating that the static length ξ grows coherently with the dynamic one ξ_{4} upon cooling. This further suggests an intrinsic link between τ_{α} and ξ: the growth of the static length ξ is the origin of dynamical slowing-down. These we confirm for the first time in binary glass formers both in two and three spatial dimensions. Thus, a static structure has two intrinsic characteristic lengths, particle size and ξ, which control dynamics in local and nonlocal manners, resulting

  17. Revealing Hidden Structural Order Controlling Both Fast and Slow Glassy Dynamics in Supercooled Liquids

    Science.gov (United States)

    Tong, Hua; Tanaka, Hajime

    2018-01-01

    The dynamics of a supercooled liquid near the glass transition is characterized by two-step relaxation, fast β and slow α relaxations. Because of the apparently disordered nature of glassy structures, there have been long debates over whether the origin of drastic slowing-down of the α relaxation accompanied by heterogeneous dynamics is thermodynamic or dynamic. Furthermore, it has been elusive whether there is any deep connection between fast β and slow α modes. To settle these issues, here we introduce a set of new structural order parameters characterizing sterically favored structures with high local packing capability, and then access structure-dynamics correlation by a novel nonlocal approach. We find that the particle mobility is under control of the static order parameter field. The fast β process is controlled by the instantaneous order parameter field locally, resulting in short-time particle-scale dynamics. Then the mobility field progressively develops with time t , following the initial order parameter field from disorder to more ordered regions. As is well known, the heterogeneity in the mobility field (dynamic heterogeneity) is maximized with a characteristic length ξ4, when t reaches the relaxation time τα. We discover that this mobility pattern can be predicted solely by a spatial coarse graining of the initial order parameter field at t =0 over a length ξ without any dynamical information. Furthermore, we find a relation ξ ˜ξ4, indicating that the static length ξ grows coherently with the dynamic one ξ4 upon cooling. This further suggests an intrinsic link between τα and ξ : the growth of the static length ξ is the origin of dynamical slowing-down. These we confirm for the first time in binary glass formers both in two and three spatial dimensions. Thus, a static structure has two intrinsic characteristic lengths, particle size and ξ , which control dynamics in local and nonlocal manners, resulting in the emergence of the two

  18. V&V Plan for FPGA-based ESF-CCS Using System Engineering Approach.

    Science.gov (United States)

    Maerani, Restu; Mayaka, Joyce; El Akrat, Mohamed; Cheon, Jung Jae

    2018-02-01

    Instrumentation and Control (I&C) systems play an important role in maintaining the safety of Nuclear Power Plant (NPP) operation. However, most current I&C safety systems are based on Programmable Logic Controller (PLC) hardware, which is difficult to verify and validate, and is susceptible to software common cause failure. Therefore, a plan for the replacement of the PLC-based safety systems, such as the Engineered Safety Feature - Component Control System (ESF-CCS), with Field Programmable Gate Arrays (FPGA) is needed. By using a systems engineering approach, which ensures traceability in every phase of the life cycle, from system requirements, design implementation to verification and validation, the system development is guaranteed to be in line with the regulatory requirements. The Verification process will ensure that the customer and stakeholder’s needs are satisfied in a high quality, trustworthy, cost efficient and schedule compliant manner throughout a system’s entire life cycle. The benefit of the V&V plan is to ensure that the FPGA based ESF-CCS is correctly built, and to ensure that the measurement of performance indicators has positive feedback that “do we do the right thing” during the re-engineering process of the FPGA based ESF-CCS.

  19. FPGA Design Methodologies Applicable to Nuclear Power Plants

    International Nuclear Information System (INIS)

    Kwong, Yongil; Jeong, Choongheui

    2013-01-01

    In order to solve the above problem, NPPs in some countries such as the US, Canada and Japan have already applied FPGA-based equipment which has advantages as follows: It is easier to verify the performance because it needs only HDL code to configure logic circuits without other software, compared to microprocessor-based equipment, It is much cheaper than ASIC in a small quantity, Its logic circuits are re configurable, It has enough resources like logic blocks and memory blocks to implement I and C functions, Multiple functions can be implemented in a FPGA chip, It is stronger with respect to carboy security than microprocessor-based equipment because its configuration cannot be changed by external access, It is simple to replace it with new one when it is obsolete, Its power consumption is lower. However, FPGA-based equipment does not have only the merits. There are some issues on its application to NPPs. First of all, the experiences in applying it to NPPs are much less than to other industries, and international standards or guidelines are also very few. And there is the small number of FPGA platforms for I and C systems. Finally, the specific guidelines on FPGA design are required because the design has both hardware and software characteristics. In order to handle the above issues, KINS(Korea Institute of Nuclear Safety) built a test platform last year and have developed regulatory guidelines for FPGA-application in NPPs. I and C systems of NPPs have been increasingly using FPGA-based equipment as an alternative of microprocessor-based equipment which is not simple to be evaluated for safety due to its complexity. This paper explained the FPGA design flow and design guidelines. Those methodologies can be used as the guidelines on FPGA verification for safety of I and C systems

  20. Design and Analysis of the Power Control System of the Fast Zero Energy Reactor FR-0

    Energy Technology Data Exchange (ETDEWEB)

    Schuh, N J.H.

    1966-12-15

    This report describes the power control by means of the fine-control rod and the design of the control system of the fast zero energy reactor FR-0 located in Studsvik, Sweden. System requirements and some operational conditions were used as design criteria. Manual and automatic control is possible. Variable electronic end-stops for the control rod have been designed, because of the special construction of the reactor and control rod. Noise in the control system caused by the reactor, detector and electronics caused disturbances of the control system at the lower power levels. The noise power-spectrum was measured. Statistical design methods, using the measured noise power spectrum, were used to design filters, which will reduce the influence of the noise at the lower power levels. Root Loci sketches and Bode diagrams were used for stability analyses. The system was simulated on an analogue computer, taking into account even nonlinearities of the control system and noise. Typical cases of reactor operation were simulated and stability analysis performed.

  1. Design and Analysis of the Power Control System of the Fast Zero Energy Reactor FR-0

    International Nuclear Information System (INIS)

    Schuh, N.J.H.

    1966-12-01

    This report describes the power control by means of the fine-control rod and the design of the control system of the fast zero energy reactor FR-0 located in Studsvik, Sweden. System requirements and some operational conditions were used as design criteria. Manual and automatic control is possible. Variable electronic end-stops for the control rod have been designed, because of the special construction of the reactor and control rod. Noise in the control system caused by the reactor, detector and electronics caused disturbances of the control system at the lower power levels. The noise power-spectrum was measured. Statistical design methods, using the measured noise power spectrum, were used to design filters, which will reduce the influence of the noise at the lower power levels. Root Loci sketches and Bode diagrams were used for stability analyses. The system was simulated on an analogue computer, taking into account even nonlinearities of the control system and noise. Typical cases of reactor operation were simulated and stability analysis performed

  2. Evaluation and standardisation of fast analytical techniques for destructive radwaste control

    International Nuclear Information System (INIS)

    De Simone, A.; Troiani, F.

    2001-01-01

    The document describes the work programme carried out by the Laboratorio Nazionale per la 'Caratterizzazione dei Refit Radioattivi', in the frame of the European research project Destructive Radwaste Control. The main tasks of the research work were the evaluation of fast sample pre-treatment procedures and the development of chromatographic methods coupled to fast nuclide detection by Liquid Scintillation Counting. In order to test the High Performance Ion Chromatograph (HPIC) coupled to the Liquid Scintillation Counter (LSC) on high salt content solutions, synthetic cement solutions have been prepared and spiked with several β-emitters hard to be measured with non-destructive analyses, along with other radionuclides important for the determination of the radiological inventory in radwastes. As the validation tests for the new analytical methods involved the manipulation of radioactive solutions, a remote area for HPIC-LSC apparatus has been designed and performed, in order to operate in safe conditions. According to the research programme, fast analytical methods for the chemical separation and radionuclide detection of the radioactive elements of interest, have been developed and qualified. From the results of the work, some protocols of analysis have been defined: they contain all information about operative conditions for HPIC-LSC apparatus, field of applicability, chemical and radioactive detection limits [it

  3. Controlling type I error rate for fast track drug development programmes.

    Science.gov (United States)

    Shih, Weichung J; Ouyang, Peter; Quan, Hui; Lin, Yong; Michiels, Bart; Bijnens, Luc

    2003-03-15

    The U.S. Food and Drug Administration (FDA) Modernization Act of 1997 has a Section (No. 112) entitled 'Expediting Study and Approval of Fast Track Drugs' (the Act). In 1998, the FDA issued a 'Guidance for Industry: the Fast Track Drug Development Programs' (the FTDD programmes) to meet the requirement of the Act. The purpose of FTDD programmes is to 'facilitate the development and expedite the review of new drugs that are intended to treat serious or life-threatening conditions and that demonstrate the potential to address unmet medical needs'. Since then many health products have reached patients who suffered from AIDS, cancer, osteoporosis, and many other diseases, sooner by utilizing the Fast Track Act and the FTDD programmes. In the meantime several scientific issues have also surfaced when following the FTDD programmes. In this paper we will discuss the concept of two kinds of type I errors, namely, the 'conditional approval' and the 'final approval' type I errors, and propose statistical methods for controlling them in a new drug submission process. Copyright 2003 John Wiley & Sons, Ltd.

  4. The ITER Fast Plant System Controller ATCA prototype Real-Time Software Architecture

    International Nuclear Information System (INIS)

    Carvalho, B.B.; Santos, B.; Carvalho, P.F.; Neto, A.; Boncagni, L.; Batista, A.J.N.; Correia, M.; Sousa, J.; Gonçalves, B.

    2013-01-01

    Highlights: ► High performance ATCA systems for fast control and data acquisition. ► IEEE1588 timing system and synchronization. ► Plasma control algorithms. ► Real-time control software frameworks. ► Targeted for nuclear fusion experiments with long duration discharges. -- Abstract: IPFN is developing a prototype Fast Plant System Controller (FPSC) based in ATCA embedded technologies dedicated to ITER CODAC data acquisition and control tasks in the sub-millisecond range. The main goal is to demonstrate the usability of the ATCA standard and its enhanced specifications for the high speed, very high density parallel data acquisition needs of the most demanding ITER tokamak plasma Instrumentation and Control (I and C) systems. This effort included the in-house development of a new family of high performance ATCA I/O and timing boards. The standard ITER software system CODAC Core System (CCS) v3.1, with the control based in the EPICS system does not cover yet the real-time requirements fulfilled by this hardware, so a new set of software components was developed for this specific platform, attempting to integrate and leverage the new features in CSS, for example the Multithreaded Application Real Time executor (MARTe) software framework, the new Data Archiving Network (DAN) solution, an ATCA IEEE-1588-2008 timing interface, and the Intelligent Platform Management Interface (IPMI) for system monitoring and remote management. This paper presents the overall software architecture for the ATCA FPSC, as well a discussion on the ITER constrains and design choices and finally a detailed description of the software components already developed

  5. The ITER Fast Plant System Controller ATCA prototype Real-Time Software Architecture

    Energy Technology Data Exchange (ETDEWEB)

    Carvalho, B.B., E-mail: bernardo@ipfn.ist.utl.pt [Associacao EURATOM/IST Instituto de Plasmas e Fusao Nuclear, Instituto Superior Tecnico, Universidade Tecnica de Lisboa, P-1049-001 Lisboa (Portugal); Santos, B.; Carvalho, P.F.; Neto, A. [Associacao EURATOM/IST Instituto de Plasmas e Fusao Nuclear, Instituto Superior Tecnico, Universidade Tecnica de Lisboa, P-1049-001 Lisboa (Portugal); Boncagni, L. [Associazione Euratom-ENEA sulla Fusione, Frascati Research Centre, Division of Fusion Physics, Frascati, Rome (Italy); Batista, A.J.N.; Correia, M.; Sousa, J.; Gonçalves, B. [Associacao EURATOM/IST Instituto de Plasmas e Fusao Nuclear, Instituto Superior Tecnico, Universidade Tecnica de Lisboa, P-1049-001 Lisboa (Portugal)

    2013-10-15

    Highlights: ► High performance ATCA systems for fast control and data acquisition. ► IEEE1588 timing system and synchronization. ► Plasma control algorithms. ► Real-time control software frameworks. ► Targeted for nuclear fusion experiments with long duration discharges. -- Abstract: IPFN is developing a prototype Fast Plant System Controller (FPSC) based in ATCA embedded technologies dedicated to ITER CODAC data acquisition and control tasks in the sub-millisecond range. The main goal is to demonstrate the usability of the ATCA standard and its enhanced specifications for the high speed, very high density parallel data acquisition needs of the most demanding ITER tokamak plasma Instrumentation and Control (I and C) systems. This effort included the in-house development of a new family of high performance ATCA I/O and timing boards. The standard ITER software system CODAC Core System (CCS) v3.1, with the control based in the EPICS system does not cover yet the real-time requirements fulfilled by this hardware, so a new set of software components was developed for this specific platform, attempting to integrate and leverage the new features in CSS, for example the Multithreaded Application Real Time executor (MARTe) software framework, the new Data Archiving Network (DAN) solution, an ATCA IEEE-1588-2008 timing interface, and the Intelligent Platform Management Interface (IPMI) for system monitoring and remote management. This paper presents the overall software architecture for the ATCA FPSC, as well a discussion on the ITER constrains and design choices and finally a detailed description of the software components already developed.

  6. Long-distance configuration of FPGA based on serial communication

    International Nuclear Information System (INIS)

    Liu Xiang; Song Kezhu; Zhang Sifeng

    2010-01-01

    To solve FPGA configuration in some nuclear electronics, which works in radioactivity environment, the article introduces a way of long-distance configuration with PC and CPLD, based on serial communication. Taking CYCLONE series FPGA and EPCS configuration chip from ALTERA for example, and using the AS configuration mode, we described our design from the aspects of basic theory, hardware connection, software function and communication protocol. With this design, we could configure several FPGAs in the distance of 100 meters, or we could configure on FPGA in the distance of 150 meters. (authors)

  7. Finite Time Fault Tolerant Control for Robot Manipulators Using Time Delay Estimation and Continuous Nonsingular Fast Terminal Sliding Mode Control.

    Science.gov (United States)

    Van, Mien; Ge, Shuzhi Sam; Ren, Hongliang

    2016-04-28

    In this paper, a novel finite time fault tolerant control (FTC) is proposed for uncertain robot manipulators with actuator faults. First, a finite time passive FTC (PFTC) based on a robust nonsingular fast terminal sliding mode control (NFTSMC) is investigated. Be analyzed for addressing the disadvantages of the PFTC, an AFTC are then investigated by combining NFTSMC with a simple fault diagnosis scheme. In this scheme, an online fault estimation algorithm based on time delay estimation (TDE) is proposed to approximate actuator faults. The estimated fault information is used to detect, isolate, and accommodate the effect of the faults in the system. Then, a robust AFTC law is established by combining the obtained fault information and a robust NFTSMC. Finally, a high-order sliding mode (HOSM) control based on super-twisting algorithm is employed to eliminate the chattering. In comparison to the PFTC and other state-of-the-art approaches, the proposed AFTC scheme possess several advantages such as high precision, strong robustness, no singularity, less chattering, and fast finite-time convergence due to the combined NFTSMC and HOSM control, and requires no prior knowledge of the fault due to TDE-based fault estimation. Finally, simulation results are obtained to verify the effectiveness of the proposed strategy.

  8. Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

    Directory of Open Access Journals (Sweden)

    P. Fiala

    2015-09-01

    Full Text Available This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed.

  9. On the actual controlling of standards concerning the 'fast breeder reactor'

    International Nuclear Information System (INIS)

    Rengeling, H.W.

    1978-01-01

    If the decision of the OVG Muenster to present the case to the Federal Constitutional Court asking whether Article 7 of the atomic energy law corresponds to the constitution or not, as far as the article allows the licensing of a fast breeder reactor, two problems arise: The legal question in how far the actual controlling of standards is to be preceeded by a statement of facts given by the court of first instance, and the problem behind concerning the responsibility of decision. The Federal Constitutional Court should accept the responsibility of decision to be borne by it. (orig.) [de

  10. Fast prototyping of conducting polymer microelectrodes using resistance-controlled high precision drilling

    DEFF Research Database (Denmark)

    Kafka, Jan Robert; Geschke, Oliver; Skaarup, Steen

    2011-01-01

    We present a straightforward method for fast prototyping of microelectrode arrays in the highly conductive polymer poly(3,4-ethylenedioxythiophene) (PEDOT). Microelectrode arrays were produced by electrical resistance-controlled microdrilling through an insulating polymer layer (TOPAS® 5013...... approach the steady state currents predicted from modeling, but at a much slower rate than expected. This is shown to be caused by the use of electroactive PEDOT electrodes. Subtraction of the latter contribution gives approach to steady state currents within a few seconds, which is in very good agreement...

  11. A fast automatic power control circuit for a small form-factor pluggable laser diode drive

    Energy Technology Data Exchange (ETDEWEB)

    Wang Huan; Wang Zhigong; Xu Jian; Miao Peng; Li Wei [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China); Luo Yin; Yang Siyong, E-mail: wanghuan@seu.edu.c [Jiangsu Sino-Chip OE-IC Co. Ltd, Nanjing 210016 (China)

    2010-06-15

    A fast automatic power control (APC) circuit for a laser diode driver (LDD) has been implemented in a 0.6-{mu}m BiCMOS process. The APC circuit adopts double-loops and variable-bandwidth techniques to achieve a turn-on time of < 400 {mu}s for most kinds of TOSAs. Thus, it meets the small form-factor pluggable (SFP) agreement. Such techniques make a good tradeoff between stability, accuracy, turn-on time, noise and convenience. The measured results indicate that the APC circuit is suitable for SFP LDD. (semiconductor integrated circuits)

  12. Methods for reactor physics calculations for control rods in fast reactors

    International Nuclear Information System (INIS)

    Grimstone, M.J.; Rowlands, J.L.

    1988-12-01

    The IAEA Specialists' Meeting on ''Methods for Reactor Physics Calculations for Control Rods in Fast Reactors'' was held in Winfrith, United Kingdom, on 6-8 December, 1988. The meeting was attended by 23 participants from nine countries. The purpose of the meeting was to review the current calculational methods and their accuracy as assessed by theoretical studies and comparisons with measurements, and then to identify the requirements for improved methods or additional studies and comparisons. The control rod properties or effects to be considered were their reactivity worths, their effect on the power distribution through the core, and the reaction rates and energy deposition both within and adjacent to the rods. The meeting was divided into five sessions, in the first of which each national delegation presented a brief overview of their programme of work on calculational methods for fast reactor control rods. In the next three sessions a total of seventeen papers were presented describing calculational methods and assessments of their accuracy. The final session was a discussion to draw conclusions regarding the current status of methods and the further developments and validation work required. A separate abstract was prepared for each of the 23 papers presented at the meeting. Refs, figs and tabs

  13. Fast and reliable control of steering mirrors with application to free-space communication

    KAUST Repository

    Ibrir, Salim; Su, Chun-Yi; Ooi, Boon S.; Alouini, Mohamed-Slim

    2018-01-01

    After modeling a laser beam pointing system actuated by a piezo-electric fast steering mirror (FSM), an observer-based linear feedback controller is developed to correct the position of the laser spot communicated by the position sensing detector (PSD). The modeling and the control actions have been considered with and without the hysteresis effect induced by the piezoelectric actuators of the FSM. The design of the feedback is given through the solution of parametric matrix inequalities. It was found that the integral feedback design is very efficient in handling input and system uncertainty. The linearity of the observer-based feedback has facilitated both the real-time implementation of the control strategy and the proof of stability using dynamic-output feedbacks.

  14. Sliding Mode Control of DFIG Wind Turbines with a Fast Exponential Reaching Law

    Directory of Open Access Journals (Sweden)

    Linyun Xiong

    2017-11-01

    Full Text Available This paper proposes a novel sliding mode control (SMC technique for doubly fed induction generators (DFIGs based on the fast exponential reaching law (FERL. The proposed FERL-based SMC is capable of reducing to a large extent the chattering phenomena existing in the sliding stage. Meanwhile, the reaching stage is accelerated with the introduction of an adaptive gain. The proposed method is employed in a DFIG-based wind energy conversion system (WECS for direct power control (DPC. The FERL-based DPC approach is tested with simulations conducted in Matlab/Simulink under the scenarios of unbalanced grid voltage, grid fault conditions and highly unstable wind speed accompanied by an experimental study. The simulations and experimental results reveal the better performance of the proposed control method in active/reactive power tracking and dc-link voltage maintenance.

  15. Fast and reliable control of steering mirrors with application to free-space communication

    KAUST Repository

    Ibrir, Salim

    2018-03-15

    After modeling a laser beam pointing system actuated by a piezo-electric fast steering mirror (FSM), an observer-based linear feedback controller is developed to correct the position of the laser spot communicated by the position sensing detector (PSD). The modeling and the control actions have been considered with and without the hysteresis effect induced by the piezoelectric actuators of the FSM. The design of the feedback is given through the solution of parametric matrix inequalities. It was found that the integral feedback design is very efficient in handling input and system uncertainty. The linearity of the observer-based feedback has facilitated both the real-time implementation of the control strategy and the proof of stability using dynamic-output feedbacks.

  16. Distributed Cooperative Control of Multi Flywheel Energy Storage System for Electrical Vehicle Fast Charging Stations

    DEFF Research Database (Denmark)

    Sun, Bo; Dragicevic, Tomislav; Quintero, Juan Carlos Vasquez

    2015-01-01

    Plug-in electrical vehicles will play a critical role in future smart grid and sudden connection of electrical vehicles chargers may cause huge power-peaks with high slew-rates on grid. In order to cope with this issue, this paper applies a distributed cooperative control for fast charging station...... with dedicated paralleled flywheel-based energy storage system. The distributed DC-bus signaling method is employed in the power coordination of grid and flywheel converters, and a distributed secondary controller generates DC voltage correction term to adjust the local voltage set-point through a dynamic...... consensus based voltage observer by communicating with its neighbors. The control system can realize the power balancing and DC voltage regulation with low reliance on communications. Finally, real-time hardware-in-the-loop results have been reported in order to verify the feasibility of proposed approach....

  17. Improved Load Frequency Control Using a Fast Acting Active Disturbance Rejection Controller

    Directory of Open Access Journals (Sweden)

    Md Mijanur Rahman

    2017-10-01

    Full Text Available System frequency may change from defined values while transmitting power from one area to another in an interconnected power system due to various reasons such as load changes and faults. This frequency change causes a frequency error in the system. However, the system frequency should always be maintained close to the nominal value even in the presence of model uncertainties and physical constraints. This paper proposes an Active Disturbance Rejection Controller (ADRC-based load frequency control (LFC of an interconnected power system. The controller incorporates effects of generator inertia and generator electrical proximity to the point of disturbances. The proposed controller reduces the magnitude error of the area control error (ACE of an interconnected power system compared to the standard controller. The simulation results verify the effectiveness of proposed ADRC in the application of LFC of an interconnected power system.

  18. Real Time Computer for Plugging Indicator Control of Prototype Fast Breeder Reactor

    International Nuclear Information System (INIS)

    Manimaran, M.; Manoj, P.; Shanmugam, A.; Murali, N.; Satya Murty, S.A.V.

    2013-06-01

    Prototype Fast Breeder Reactor (PFBR) is in the advanced stage of construction at Kalpakkam, India. Liquid sodium is used as coolant to transfer the heat produced in the reactor core to steam water circuit. Impurities present in the sodium are removed using purification circuit. Plugging indicator is a device used to measure the purity of the sodium. Versa Module Europa bus based Real Time Computer (RTC) system is used for plugging indicator control. Hot standby architecture consisting of dual redundant RTC system with switch over logic system is the configuration adopted to achieve fault tolerance. Plugging indicator can be controlled in two modes namely continuous and discontinuous mode. Software based Proportional-Integral-Derivative (PID) algorithms are developed for plugging indicator control wherein the set point changes dynamically for every scan interval of the RTC system. Set points and PID constants are kept as configurable in runtime in order to control the process in very efficient manner, which calls for reliable communication between RTC system and control station, hence TCP/IP protocol is adopted. Performance of the RTC system for plugging indicator control was thoroughly studied in the laboratory by simulating the inputs and monitored the control outputs. The control outputs were also monitored for different PID constants. Continuous and discontinuous mode plots were generated. (authors)

  19. Control rod shadowing and anti-shadowing effects in a large gas-cooled fast reactor

    International Nuclear Information System (INIS)

    Girardin, G.; Chawla, R.; Rimpault, G.; Coddington, P.

    2007-01-01

    An investigation of control rod shadowing and anti-shadowing (interaction) effects has been carried out in the context of a design study of the control rod pattern for the large 2400 MWth Generation IV Gas-cooled Fast Reactor (GFR). For the calculations, the deterministic code system ERANOS-2.0 has been used, in association with a full core model including a European Fast Reactor (EFR)-type pattern for the control rods. More specifically, the core contains a total of 33 control (CSD) and safety (DSD) rods implemented in three banks: -1) a first bank of 6 CSD rods, placed at 64 cm from core centre in the inner fuel zone (Pu content 16.3 % vol.), -2) a safety bank consisting of 9 DSD rods, at an average distance of 118 cm, and -3) a third bank with 18 CSD rods, placed at 171 cm, i.e. at the interface between the inner and outer (Pu content 19.2 % vol.) core regions. Each control rod has been modelled as a homogeneous material containing 90%-enriched B 4 C, steel and helium. Considerable shadowing effects have been observed between the first bank and the safety bank, as also between individual rods within the first bank. Large anti-shadowing effects take place in an even greater number of the studied rod configurations. The largest interaction is between the two CSD banks, the anti-shadowing value being 46% in this case, implying that the total rod worth is increased by a factor of almost 2 when compared to the sum of the individual bank values. Additional investigations have been performed, in particular the computation of the first order eigenvalue and the eigenvalue separation. The main finding is that the interactions are lower when one of the control rod banks is located at a radial position corresponding to half the core radius. (authors)

  20. Design of area array CCD image acquisition and display system based on FPGA

    Science.gov (United States)

    Li, Lei; Zhang, Ning; Li, Tianting; Pan, Yue; Dai, Yuming

    2014-09-01

    With the development of science and technology, CCD(Charge-coupled Device) has been widely applied in various fields and plays an important role in the modern sensing system, therefore researching a real-time image acquisition and display plan based on CCD device has great significance. This paper introduces an image data acquisition and display system of area array CCD based on FPGA. Several key technical challenges and problems of the system have also been analyzed and followed solutions put forward .The FPGA works as the core processing unit in the system that controls the integral time sequence .The ICX285AL area array CCD image sensor produced by SONY Corporation has been used in the system. The FPGA works to complete the driver of the area array CCD, then analog front end (AFE) processes the signal of the CCD image, including amplification, filtering, noise elimination, CDS correlation double sampling, etc. AD9945 produced by ADI Corporation to convert analog signal to digital signal. Developed Camera Link high-speed data transmission circuit, and completed the PC-end software design of the image acquisition, and realized the real-time display of images. The result through practical testing indicates that the system in the image acquisition and control is stable and reliable, and the indicators meet the actual project requirements.

  1. Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Cardinali, Matteo [Helmholtz Institut Mainz (Germany); Collaboration: PANDA Cherenkov-Collaboration

    2014-07-01

    The next generation of high-luminosity experiments requires excellent Particle Identification (PID) detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected data rates. The planned PANDA experiment at FAIR expects average interaction rates of 20 MHz. A Barrel DIRC will provide PID in the central region of the Target Spectrometer. A single photo-electron timing resolution of better than 100 ps is projected for the Barrel DIRC to disentangle the complicated patterns created by the focusing optics on the image plane. The typically large amount of readout channels (approx 15,000 in case of the PANDA Barrel DIRC) places non-negligible limits on size and power consumption of the Front-End Electronics (FEE). The proposed design is based on the TRBv3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom FEE with high-bandwidth pre-amplifiers and fast discriminators. Two types of FEE cards optimised for reading out 64-channel Photonis Planacon MCP-PMTs were tested: one based on the NINO ASIC developed for the ALICE RPC readout and the other, called PaDiWa, using FPGA-based discriminators. Both types of FEE cards were tested with a small DIRC prototype comprising a radiator bar with focusing lens and an oil-filled expansion volume instrumented with 6 Planacon 64-channel MCP-PMTs. In the presentation the result of a test experiment performed at MAMI B, Mainz, are addressed.

  2. VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

    Directory of Open Access Journals (Sweden)

    Esteban Tlelo-Cuautle

    Full Text Available Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL. In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

  3. VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

    Science.gov (United States)

    Tlelo-Cuautle, Esteban; Quintas-Valles, Antonio de Jesus; de la Fraga, Luis Gerardo; Rangel-Magdaleno, Jose de Jesus

    2016-01-01

    Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

  4. FPGA fabric specific optimization for RLT design

    International Nuclear Information System (INIS)

    Perwaiz, A.; Khan, S.A.

    2010-01-01

    This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced re configurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned Index Terms: Field Programmable Gate Arrays (FPGA), Compression Tree, Bit Width Reduction, Look Ahead Pipelining. (author)

  5. FPGA Design and Implementation of a Rangefinder

    Directory of Open Access Journals (Sweden)

    ALBU Răzvan-Daniel

    2017-10-01

    Full Text Available In this paper we will present the design and implementation of an ultrasonic non-contact rangefinder with FPGA. This rangefinder can be used in numerous applications, ranging from hardly accessible spaces to electromagnetically polluted environments. The experimental implementations proved to be accurate, portable, and easy to operate. Attributable to their programmable nature, FPGAs are an ideal fit for many dissimilar markets. Even though FPGAs used to be designated for lower speed and complexity designs in the past, today’s FPGAs effortlessly push the 500 MHz performance barricade. Since they bring features, such as embedded processors, DSP blocks, clocking, and high-speed serial at lower prices, FPGAs are a convincing alternative for almost any type of design.

  6. Advanced control system for the Integral Fast Reactor fuel pin processor

    International Nuclear Information System (INIS)

    Lau, L.D.; Randall, P.F.; Benedict, R.W.; Levinskas, D.

    1993-01-01

    A computerized control system has been developed for the remotely-operated fuel pin processor used in the Integral Fast Reactor Program, Fuel Cycle Facility (FCF). The pin processor remotely shears cast EBR- reactor fuel pins to length, inspects them for diameter, straightness, length, and weight, and then inserts acceptable pins into new sodium-loaded stainless-steel fuel element jackets. Two main components comprise the control system: (1) a programmable logic controller (PLC), together with various input/output modules and associated relay ladder-logic associated computer software. The PLC system controls the remote operation of the machine as directed by the OCS, and also monitors the machine operation to make operational data available to the OCS. The OCS allows operator control of the machine, provides nearly real-time viewing of the operational data, allows on-line changes of machine operational parameters, and records the collected data for each acceptable pin on a central data archiving computer. The two main components of the control system provide the operator with various levels of control ranging from manual operation to completely automatic operation by means of a graphic touch screen interface

  7. Design and adjustment on test bed of replacing subassembly machine control system for China experimental fast reactor

    International Nuclear Information System (INIS)

    Dong Shengguo; Ma Hongsheng; Zhao Lixia

    2008-01-01

    The present research concerns in the design and adjustment of replacing sub- assembly machine control system of China Experimental Fast Reactor. The design of replacing subassembly machine control system adopts some electric equipments, such as programmable controllers, digital DC drivers. The designed control system was adjusted on the test bed. The results indicate that the operation of the control system is steady and reliable, and designed control system can meet the needs of the design specification. (authors)

  8. Automation of FBTR fuel pin inspection using FPGA

    International Nuclear Information System (INIS)

    Khare, K.M.; Pai, Siddhesh; Pant, Brijesh; Sendhil Raja, S.; Gupta, P.K.

    2011-01-01

    A non-contact metrology system for inspection of FBTR fuel pins has been developed. The system consists of a stepper motors driven mechanism for orientation and positioning of FBTR fuel pin, a telecentric imaging system, absolute linear encoder with 0.1 μm resolution and a Field Programmable Gate Array (FPCA) based controller. The FBTR pin assembly is telecentrically illuminated from bottom by a red LED and its shadow graph is imaged using a CCD camera through telecentric imaging lens system. For system control and automation we have used a FPGA that has integrated soft picoblaze processor, X-θ axis motion controller, custom IPs for encoder data acquisition, synchronization circuit, RS485 interface along with other l/Os. Using the Graphical User Interface (GUI) on a PC the system is initialized at home position and the controller provides the trigger signal for start of data acquisition of CCD camera. CCD image of pin and the corresponding X-θ information is captured. After the acquisition of one set of images, the imaging module is moved with a step size pre-programmed to ensure proper stitching of acquired images. The GUI is programmed to analyze these X-θ Images to calculate the required parameters of the fuel pin like the diameter variation, pitch and bow. The details of the instrument and measurements made with it will be presented. (author)

  9. Application-specific mesh-based heterogeneous FPGA architectures

    CERN Document Server

    Parvez, Husain

    2011-01-01

    This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

  10. Technologies for faults diagnosis of FPGA logic blocks

    Directory of Open Access Journals (Sweden)

    C. U. Ngene

    2012-08-01

    Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

  11. Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

    National Research Council Canada - National Science Library

    Bardouleau, Graham; Kulp, James

    2005-01-01

    In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment...

  12. High-Performance Linear Algebra Processor using FPGA

    National Research Council Canada - National Science Library

    Johnson, J

    2004-01-01

    With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

  13. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

  14. High Voltage, Fast-Switching Module for Active Control of Magnetic Fields and Edge Plasma Currents

    Science.gov (United States)

    Ziemba, Timothy; Miller, Kenneth; Prager, James; Slobodov, Ilia

    2016-10-01

    Fast, reliable, real-time control of plasma is critical to the success of magnetic fusion science. High voltage and current supplies are needed to mitigate instabilities in all experiments as well as disruption events in large scale tokamaks for steady-state operation. Silicon carbide (SiC) MOSFETs offer many advantages over IGBTs including lower drive energy requirements, lower conduction and switching losses, and higher switching frequency capabilities; however, these devices are limited to 1.2-1.7 kV devices. As fusion enters the long-pulse and burning plasma eras, efficiency of power switching will be important. Eagle Harbor Technologies (EHT), Inc. developing a high voltage SiC MOSFET module that operates at 10 kV. This switch module utilizes EHT gate drive technology, which has demonstrated the ability to increase SiC MOSFET switching efficiency. The module will allow more rapid development of high voltage switching power supplies at lower cost necessary for the next generation of fast plasma feedback and control. EHT is partnering with the High Beta Tokamak group at Columbia to develop detailed high voltage module specifications, to ensure that the final product meets the needs of the fusion science community.

  15. Simultaneous Perturbation Particle Swarm Optimization and Its FPGA Implementation

    OpenAIRE

    Maeda, Yutaka; Matsushita, Naoto

    2009-01-01

    In this paper, we presented hardware implementation of the particle swarm optimization algorithm which is combination of the ordinary particle swarm optimization and the simultaneous perturbation method. FPGA is used to realize the system. This algorithm utilizes local information of objective function effectively without lack of advantage of the original particle swarm optimization. Moreover, the FPGA implementation gives higher operation speed effectively using parallelism of the particle s...

  16. Temperature control characteristics analysis of lead-cooled fast reactor with natural circulation

    International Nuclear Information System (INIS)

    Yang, Minghan; Song, Yong; Wang, Jianye; Xu, Peng; Zhang, Guangyu

    2016-01-01

    Highlights: • The LFR temperature control system are analyzed with frequency domain method. • The temperature control compensator is designed according to the frequency analysis. • Dynamic simulation is performed by SIMULINK and RELAP5-HD. - Abstract: Lead-cooled Fast Reactor (LFR) with natural circulation in primary system is among the highlights in advance nuclear reactor research, due to its great superiority in reactor safety and reliability. In this work, a transfer function matrix describing coolant temperature dynamic process, obtained by Laplace transform of the one-dimensional system dynamic model is developed in order to investigate the temperature control characteristics of LFR. Based on the transfer function matrix, a close-loop coolant temperature control system without compensator is built. The frequency domain analysis indicates that the stability and steady-state of the temperature control system needs to be improved. Accordingly, a temperature compensator based on Proportion–Integration and feed-forward is designed. The dynamic simulation of the whole system with the temperature compensator for core power step change is performed with SIMULINK and RELAP5-HD. The result shows that the temperature compensator can provide superior coolant temperature control capabilities in LFR with natural circulation due to the efficiency of the frequency domain analysis method.

  17. Enhanced thermal expansion control rod drive lines for improving passive safety of fast reactors

    International Nuclear Information System (INIS)

    Edelmann, M.; Baumann, W.; Kuechle, M.; Kussmaul, G.; Vaeth, W.; Bertram, A.

    1992-01-01

    The paper presents a device for increasing the thermal expansion effect of control rod drive lines on negative reactivity feedback in fast reactors. The enhanced thermal expansion of this device can be utilized for both passive rod drop and forced insertion of absorbers in unprotected transients, e.g. ULOF. In this way the reactor is automatically brought into a permanently subcritical state and temperatures are kept well below the boiling point of the coolant. A prototype of such a device called ATHENa (German: Shut-down by THermal Expansion of Na) is presently under construction and will be tested. The paper presents the principle, design features and thermal properties of ATHENs as well as results of reactor dynamics calculations of ULOF's for EFR with enhanced thermal expansion control rod drive lines. (author)

  18. The timing of control signals underlying fast point-to-point arm movements.

    Science.gov (United States)

    Ghafouri, M; Feldman, A G

    2001-04-01

    It is known that proprioceptive feedback induces muscle activation when the facilitation of appropriate motoneurons exceeds their threshold. In the suprathreshold range, the muscle-reflex system produces torques depending on the position and velocity of the joint segment(s) that the muscle spans. The static component of the torque-position relationship is referred to as the invariant characteristic (IC). According to the equilibrium-point (EP) hypothesis, control systems produce movements by changing the activation thresholds and thus shifting the IC of the appropriate muscles in joint space. This control process upsets the balance between muscle and external torques at the initial limb configuration and, to regain the balance, the limb is forced to establish a new configuration or, if the movement is prevented, a new level of static torques. Taken together, the joint angles and the muscle torques generated at an equilibrium configuration define a single variable called the EP. Thus by shifting the IC, control systems reset the EP. Muscle activation and movement emerge following the EP resetting because of the natural physical tendency of the system to reach equilibrium. Empirical and simulation studies support the notion that the control IC shifts and the resulting EP shifts underlying fast point-to-point arm movements are gradual rather than step-like. However, controversies exist about the duration of these shifts. Some studies suggest that the IC shifts cease with the movement offset. Other studies propose that the IC shifts end early in comparison to the movement duration (approximately, at peak velocity). The purpose of this study was to evaluate the duration of the IC shifts underlying fast point-to-point arm movements. Subjects made fast (hand peak velocity about 1.3 m/s) planar arm movements toward different targets while grasping a handle. Hand forces applied to the handle and shoulder/elbow torques were, respectively, measured from a force sensor placed

  19. A Translator Verification Technique for FPGA Software Development in Nuclear Power Plants

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Jae Yeob; Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of)

    2014-10-15

    Although the FPGAs give a high performance than PLC (Programmable Logic Controller), the platform change from PLC to FPGA impose all PLC software engineers give up their experience, knowledge and practices accumulated over decades, and start a new FPGA-based hardware development from scratch. We have researched to fine the solution to this problem reducing the risk and preserving the experience and knowledge. One solution is to use the FBDtoVerilog translator, which translates the FBD programs into behavior-preserving Verilog programs. In general, the PLCs are usually designed with an FBD, while the FPGAs are described with a HDL (Hardware Description Language) such as Verilog or VHDL. Once PLC designer designed the FBD programs, the FBDtoVerilog translates the FBD into Verilog, mechanically. The designers, therefore, need not consider the rest of FPGA development process (e.g., Synthesis and Place and Routing) and can preserve the accumulated experience and knowledge. Even if we assure that the translation from FBD to Verilog is correct, it must be verified rigorously and thoroughly since it is used in nuclear power plants, which is one of the most safety critical systems. While the designer develops the FPGA software with the FBD program translated by the translator, there are other translation tools such as synthesis tool and place and routing tool. This paper also focuses to verify them rigorously and thoroughly. There are several verification techniques for correctness of translator, but they are hard to apply because of the outrageous cost and performance time. Instead, this paper tries to use an indirect verification technique for demonstrating the correctness of translator using the co-simulation technique. We intend to prove only against specific inputs which are under development for a target I and C system, not against all possible input cases.

  20. A Translator Verification Technique for FPGA Software Development in Nuclear Power Plants

    International Nuclear Information System (INIS)

    Kim, Jae Yeob; Kim, Eui Sub; Yoo, Jun Beom

    2014-01-01

    Although the FPGAs give a high performance than PLC (Programmable Logic Controller), the platform change from PLC to FPGA impose all PLC software engineers give up their experience, knowledge and practices accumulated over decades, and start a new FPGA-based hardware development from scratch. We have researched to fine the solution to this problem reducing the risk and preserving the experience and knowledge. One solution is to use the FBDtoVerilog translator, which translates the FBD programs into behavior-preserving Verilog programs. In general, the PLCs are usually designed with an FBD, while the FPGAs are described with a HDL (Hardware Description Language) such as Verilog or VHDL. Once PLC designer designed the FBD programs, the FBDtoVerilog translates the FBD into Verilog, mechanically. The designers, therefore, need not consider the rest of FPGA development process (e.g., Synthesis and Place and Routing) and can preserve the accumulated experience and knowledge. Even if we assure that the translation from FBD to Verilog is correct, it must be verified rigorously and thoroughly since it is used in nuclear power plants, which is one of the most safety critical systems. While the designer develops the FPGA software with the FBD program translated by the translator, there are other translation tools such as synthesis tool and place and routing tool. This paper also focuses to verify them rigorously and thoroughly. There are several verification techniques for correctness of translator, but they are hard to apply because of the outrageous cost and performance time. Instead, this paper tries to use an indirect verification technique for demonstrating the correctness of translator using the co-simulation technique. We intend to prove only against specific inputs which are under development for a target I and C system, not against all possible input cases

  1. FPGA BASED ASYNCHRONOUS PIPELINED MB-OFDM UWB TRANSMITTER BACKEND MODULES

    Directory of Open Access Journals (Sweden)

    M. Santhi

    2010-03-01

    Full Text Available In this paper, a novel scheme is proposed which comprises the advantages of asynchronous pipelining techniques and the advantages of FPGAs for implementing a 200Mbps MB-OFDM UWB transmitter digital backend modules. In asynchronous pipelined system, registers are used as in synchronous system. But they are controlled by handshaking signals. Since FPGAs are rich in registers, design and implementation of asynchronous pipelined MBOFDM UWB transmitter on FPGA using four-phase bundled-data protocol is considered in this paper. Novel ideas have also been proposed for designing asynchronous OFDM using Modified Radix-24 SDF and asynchronous interleaver using two RAM banks. Implementation has been performed on ALTERA STRATIX II EP2S60F1020C4 FPGA and it is operating at a speed of 350MHz. It is assured that the proposed MB-OFDM UWB system can be made to work on STRATIX III device with the operating frequency of 528MHz in compliance to the ECMA-368 standard. The proposed scheme is also applicable for FPGA from other vendors and ASIC.

  2. Design and implementation of a programming circuit in radiation-hardened FPGA

    International Nuclear Information System (INIS)

    Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Chen, Stanley L.

    2011-01-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 x 10 5 rad(Si), dose rate survivability of 1.5 x 10 11 rad(Si)/s and neutron fluence immunity of 1 x 10 14 n/cm 2 .

  3. Design and implementation of STD32-BUS based reactor protection trip unit on FPGA imbaby

    International Nuclear Information System (INIS)

    Mahmoud, I.; Elnokity, O.A.; Refai, M.K.

    2007-01-01

    This paper presents a way to design and implement the Trip Unit of a Reactor Protection System (RPS) using a Field Programmable Gate Arrays (FPGA). Instead of the traditional embedded Microprocessor based interface design method, a proposed tailor made FPGA based circuit is built to substitute the Trip Unit (TL1) existing in Egypt's 2' ' Research reactor ETRR-2. The existing embedded system is built around the STD32 field Computer Bus which used in industrial and process control applications. It is modular, rugged, reliable, and easy-to-use and is able to support a large mix of I/O cards and to easily change its configuration in the future. Therefore, the state machine of this bus is extracted from its timing diagrams and implemented in VHDL to interface the designed TU circuit. The proposed designed circuit implemented using ALTERA EPF10K10LC84-3 chip replaces the Single Board Computer which have the embedded SAY program of the TU providing the same integrated HAV and SAV functions implemented in FPGA Chip housed in an printed circuit board, which uses the same shape and specifications of STD32 boards. H/W implementation of both TU and STD32 Bus in VHDL addresses the issues of safety and reusability

  4. Design and implementation of a programming circuit in radiation-hardened FPGA

    Science.gov (United States)

    Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

    2011-08-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

  5. Definition of a Robust Supervisory Control Scheme for Sodium-Cooled Fast Reactors

    Energy Technology Data Exchange (ETDEWEB)

    Ponciroli, R.; Passerini, S.; Vilim, R. B.

    2016-04-17

    In this work, an innovative control approach for metal-fueled Sodium-cooled Fast Reactors is proposed. With respect to the classical approach adopted for base-load Nuclear Power Plants, an alternative control strategy for operating the reactor at different power levels by respecting the system physical constraints is presented. In order to achieve a higher operational flexibility along with ensuring that the implemented control loops do not influence the system inherent passive safety features, a dedicated supervisory control scheme for the dynamic definition of the corresponding set-points to be supplied to the PID controllers is designed. In particular, the traditional approach based on the adoption of tabulated lookup tables for the set-point definition is found not to be robust enough when failures of the implemented SISO (Single Input Single Output) actuators occur. Therefore, a feedback algorithm based on the Reference Governor approach, which allows for the optimization of reference signals according to the system operating conditions, is proposed.

  6. A statistical model of uplink inter-cell interference with slow and fast power control mechanisms

    KAUST Repository

    Tabassum, Hina

    2013-09-01

    Uplink power control is in essence an interference mitigation technique that aims at minimizing the inter-cell interference (ICI) in cellular networks by reducing the transmit power levels of the mobile users while maintaining their target received signal quality levels at base stations. Power control mechanisms directly impact the interference dynamics and, thus, affect the overall achievable capacity and consumed power in cellular networks. Due to the stochastic nature of wireless channels and mobile users\\' locations, it is important to derive theoretical models for ICI that can capture the impact of design alternatives related to power control mechanisms. To this end, we derive and verify a novel statistical model for uplink ICI in Generalized-K composite fading environments as a function of various slow and fast power control mechanisms. The derived expressions are then utilized to quantify numerically key network performance metrics that include average resource fairness, average reduction in power consumption, and ergodic capacity. The accuracy of the derived expressions is validated via Monte-Carlo simulations. Results are generated for multiple network scenarios, and insights are extracted to assess various power control mechanisms as a function of system parameters. © 1972-2012 IEEE.

  7. Adaptation of fast responding power supply for radial position control in SST-1

    International Nuclear Information System (INIS)

    Sharma, Dinesh Kumar; Patel, Kiritkumar B.; Singh, Akhilesh Kumar; Dhongde, Jasraj

    2013-01-01

    A high current, fast responding power supply was installed in 2005 for vertical stabilization of elongated plasmas in SST-1 tokamak. Presently, during initial experiments of SST-1 tokamak the need for radial control during current build-up was envisaged. For this purpose the existing power supply was suitable and the same was re-commissioned and control adaptations were carried as per experimental requirements. This paper highlights the capabilities of the power supply and details the modifications in the control interfaces and test programs for the radial control purpose. Details of the operation of the power supply along with control interfaces with performance measurements are provided. The re-commissioning provided an opportunity in the trouble shooting methods and sequential operation of the system. With the operational use on the actual coil the mutual effects are understood better and appropriate test programs are prepared. The power supply provided satisfactory performance for the intended use. In additional the system is suitable to simulate a plasma current loop to enable the testing and calibration of Rogowski coil used for plasma current measurement. (author)

  8. A statistical model of uplink inter-cell interference with slow and fast power control mechanisms

    KAUST Repository

    Tabassum, Hina; Yilmaz, Ferkan; Dawy, Zaher; Alouini, Mohamed-Slim

    2013-01-01

    Uplink power control is in essence an interference mitigation technique that aims at minimizing the inter-cell interference (ICI) in cellular networks by reducing the transmit power levels of the mobile users while maintaining their target received signal quality levels at base stations. Power control mechanisms directly impact the interference dynamics and, thus, affect the overall achievable capacity and consumed power in cellular networks. Due to the stochastic nature of wireless channels and mobile users' locations, it is important to derive theoretical models for ICI that can capture the impact of design alternatives related to power control mechanisms. To this end, we derive and verify a novel statistical model for uplink ICI in Generalized-K composite fading environments as a function of various slow and fast power control mechanisms. The derived expressions are then utilized to quantify numerically key network performance metrics that include average resource fairness, average reduction in power consumption, and ergodic capacity. The accuracy of the derived expressions is validated via Monte-Carlo simulations. Results are generated for multiple network scenarios, and insights are extracted to assess various power control mechanisms as a function of system parameters. © 1972-2012 IEEE.

  9. Power supply for control and instrumentation in Fast Breeder Test Reactor

    International Nuclear Information System (INIS)

    Raghavan, K.; Shanmugam, T.K.

    1977-01-01

    The design and operation of the four 'no-break' power supplies for control and instrumentation in the Fast Breeder Test Reactor (FBTR), Kalpakkam, are described. Interruptions in the power supplies are eliminated by redundancy and battery back-up source while voltage dips and transients are taken care by automatic regulation system. The four power supplies are : (1) 24 V D.C. exclusively for neutronic and safety circuits, (2) 48 V D.C. for control logic indication lamps and solenoid valves, (3) 220 V D.C. for switchgear control, control room emergency lighting and D.C. flushing oil pump for the turbine and (4) 220 V A.C. single-phase 50 H/Z for computers and electronics of control and instrumentation. Stationary lead-acid batteries (lead antimony type) in floating mode operation with rectifier/charger are used for emergency back-up. All these power supplies are fed by 415 V, 3-phase, 50 HZ emergency supply buses which are provided with diesel generator back-up. Static energy conversion system (in preference to mechanical rotation system) is used for A.C. to D.C. and also for A.C. to A.C. conversion. (M.G.B.)

  10. Research and Implementation of Automatic Fuzzy Garage Parking System Based on FPGA

    OpenAIRE

    Wang Kaiyu; Yu Zongmin; Guan Sanghai; Yang Xing; Sheng Menglin; Tang Zhenan

    2016-01-01

    Because of many common scenes of reverse parking in real life, this paper presents a fuzzy controller which accommodates front and back adjustment of vehicle’s body attitude, and based on chaotic-genetic arithmetic to optimize the membership function of this controller, and get a vertical parking fuzzy controller whose simulation result is good .The paper makes the hardware-software embedded design for system based on Field-Programmable Gate Array (FPGA), and set up a 1:10 verification platfo...

  11. An FPGA based Node-on-Chip Architecture, for Rapid Robotics Research

    DEFF Research Database (Denmark)

    Falsig, Simon; Sørensen, Anders Stengaard

    2010-01-01

    One of the major costs and inhibitors to practical robotics research is the time invested in design, implementation, integration, adjusting and debugging of the embedded control systems, that implement the discrete event control in experimental robots and robot systems. Usually researchers can...... with the compactness and integration associated with customized hardware. In this paper we present an FPGA based architecture and a framework of template modules for modular embedded control that has: • Dramatically reduced the time we spend on instrumentation of experimental robots. • Increased the quality...

  12. Research and Implementation of Automatic Fuzzy Garage Parking System Based on FPGA

    Directory of Open Access Journals (Sweden)

    Wang Kaiyu

    2016-01-01

    Full Text Available Because of many common scenes of reverse parking in real life, this paper presents a fuzzy controller which accommodates front and back adjustment of vehicle’s body attitude, and based on chaotic-genetic arithmetic to optimize the membership function of this controller, and get a vertical parking fuzzy controller whose simulation result is good .The paper makes the hardware-software embedded design for system based on Field-Programmable Gate Array (FPGA, and set up a 1:10 verification platform of smart car to verify the fuzzy garage parking system with real car. Verification results show that, the system can complete the parking task very well.

  13. Design and FPGA implementation for MAC layer of Ethernet PON

    Science.gov (United States)

    Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao

    2004-04-01

    Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.

  14. Modified source of a fast neutral atom beam with a controlled energy

    International Nuclear Information System (INIS)

    Gostev, V.A.; Elakhovskij, D.V.; Khakhaev, A.D.

    1980-01-01

    A source of a metastable helium atom beam with a controlled energy based on a phenomenon of resonant ion neutralization on the surface of a solid body is described. The neutral particle energy control is carried out by changing ion velocities before their transformation into metastable atoms. The results of experiments with a modified construction of atomic beam source are stated. These experiments were conducted to find the possibilities to control velocities of atoms in a flow as well as to elucidate the peculiarities of operation of a collimator-converter of this construction. Dependences of a halfwidth of the ion velocity distribution function on the ion source parameters have been investigated. The possibility for particle energy control in a collimated flow of fast neutral. atoms has been experimentally shown, it is also shown that a mean value of atom energy in a beam coincides with a value of mean energy of ions from which atoms are produced by the resonant neutralization method; the construction of the source provides the possibility to realize the method of ''overtaking beams'' for neutral atoms and as a result of this to give a possibility for studying atom-atom collisions in a wide energy range at relatively high densities of flows

  15. Real-Time Attitude Control Algorithm for Fast Tumbling Objects under Torque Constraint

    Science.gov (United States)

    Tsuda, Yuichi; Nakasuka, Shinichi

    This paper describes a new control algorithm for achieving any arbitrary attitude and angular velocity states of a rigid body, even fast and complicated tumbling rotations, under some practical constraints. This technique is expected to be applied for the attitude motion synchronization to capture a non-cooperative, tumbling object in such missions as removal of debris from orbit, servicing broken-down satellites for repairing or inspection, rescue of manned vehicles, etc. For this objective, we have introduced a novel control algorithm called Free Motion Path Method (FMPM) in the previous paper, which was formulated as an open-loop controller. The next step of this consecutive work is to derive a closed-loop FMPM controller, and as the preliminary step toward the objective, this paper attempts to derive a conservative state variables representation of a rigid body dynamics. 6-Dimensional conservative state variables are introduced in place of general angular velocity-attitude angle representation, and how to convert between both representations are shown in this paper.

  16. Aggregate modeling of fast-acting demand response and control under real-time pricing

    International Nuclear Information System (INIS)

    Chassin, David P.; Rondeau, Daniel

    2016-01-01

    Highlights: • Demand elasticity for fast-acting demand response load under real-time pricing. • Validated first-principles logistic demand curve matches random utility model. • Logistic demand curve suitable for diversified aggregate loads market-based transactive control systems. - Abstract: This paper develops and assesses the performance of a short-term demand response (DR) model for utility load control with applications to resource planning and control design. Long term response models tend to underestimate short-term demand response when induced by prices. This has two important consequences. First, planning studies tend to undervalue DR and often overlook its benefits in utility demand management program development. Second, when DR is not overlooked, the open-loop DR control gain estimate may be too low. This can result in overuse of load resources, control instability and excessive price volatility. Our objective is therefore to develop a more accurate and better performing short-term demand response model. We construct the model from first principles about the nature of thermostatic load control and show that the resulting formulation corresponds exactly to the Random Utility Model employed in economics to study consumer choice. The model is tested against empirical data collected from field demonstration projects and is shown to perform better than alternative models commonly used to forecast demand in normal operating conditions. The results suggest that (1) existing utility tariffs appear to be inadequate to incentivize demand response, particularly in the presence of high renewables, and (2) existing load control systems run the risk of becoming unstable if utilities close the loop on real-time prices.

  17. Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

    International Nuclear Information System (INIS)

    Jinyuan Wu; Zonghan Shi; Irena Y Wang

    2003-01-01

    A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

  18. An investigation into the equivalent parameter method for homogeneous transport equivalent parameters for use in fast reactor control assemblies

    International Nuclear Information System (INIS)

    Tullett, J.D.

    1990-01-01

    P Benoist has developed a method for calculating cross-sections for Fast Reactor control rods and their followers described by a single homogenised region (the Equivalent Parameter Method). When used in a diffusion theory calculation, these equivalent cross-sections should give the same rod worth as one would obtain from a transport theory calculation with a heterogeneous description of the control rod and the follower. In this report, Benoist's theory is described, and a comprehensive set of tests is presented. These tests show that the method gives very good results over a range of geometries and control rod positions for a model fast reactor core. (author)

  19. EPICS device support module as ATCA system manager for the ITER fast plant system controller

    Energy Technology Data Exchange (ETDEWEB)

    Carvalho, Paulo F., E-mail: pricardofc@ipfn.ist.utl.pt [Associação EURATOM/IST, Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico – Universidade Técnica de Lisboa, Lisboa (Portugal); Santos, Bruno; Gonçalves, Bruno; Carvalho, Bernardo B.; Sousa, Jorge; Rodrigues, A.P.; Batista, António J.N.; Correia, Miguel; Combo, Álvaro [Associação EURATOM/IST, Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico – Universidade Técnica de Lisboa, Lisboa (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentação, Departamento de Física, Universidade de Coimbra, Coimbra (Portugal); Varandas, Carlos A.F. [Associação EURATOM/IST, Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico – Universidade Técnica de Lisboa, Lisboa (Portugal)

    2013-10-15

    Highlights: ► In Nuclear Fusion, demanding security and high-availability requirements call for redundancy to be available. ► ATCA based Nuclear Fusion Systems are composed by several electronic and mechanical component. ► Control and monitoring of ATCA electronic systems are recommended. ► ITER Fast Plant System Controller Project CODAC system prototype. ► EPICS device support module as External ATCA system manager solution. -- Abstract: This paper presents an Enhanced Physics and Industrial Control System (EPICS) device support module for the International Thermonuclear Experimental Reactor (ITER) Fast Plant System Controller (FPSC) project based in Advanced Telecommunications Computing Architecture (ATCA) specification. The developed EPICS device support module provides an External System Manager (ESM) solution for monitoring and control the ITER FPSC ATCA shelf system and data acquisition boards in order to take proper action and report problems to a control room operator or high level management unit in case of any system failure occurrence. EPICS device support module acts as a Channel Access (CA) server to report problems and publish ATCA system data information to the control room operator, high level management unit or other CA network clients such as Control System Studio Operator Interfaces (CSS OPIs), Best Ever Alarm System Toolkit (BEAST), Best Ever Archive Utility (BEAUTY) or other CA client applications. EPICS device support module communicates with the ATCA Shelf manager (ShM) using HTTP protocol to send and receive commands through POST method in order to get and set system and shelf components properties such as fan speeds measurements, temperatures readings, module status and ATCA boards acquisition and configuration parameters. All system properties, states, commands and parameters are available through the EPICS device support module CA server in EPICS Process Variables (PV) and signals format. ATCA ShM receives the HTTP protocol

  20. Fast and error-resilient coherent control in an atomic vapor

    Science.gov (United States)

    He, Yizun; Wang, Mengbing; Zhao, Jian; Qiu, Liyang; Wang, Yuzhuo; Fang, Yami; Zhao, Kaifeng; Wu, Saijun

    2017-04-01

    Nanosecond chirped pulses from an optical arbitrary waveform generator is applied to both invert and coherently split the D1 line population of potassium vapor within a laser focal volume of 2X105 μ m3. The inversion fidelity of f>96%, mainly limited by spontaneous emission during the nanosecond pulse, is inferred from both probe light transmission and superfluorescence emission. The nearly perfect inversion is uniformly achieved for laser intensity varying over an order of magnitude, and is tolerant to detuning error of more than 1000 times the D1 transition linewidth. We further demonstrate enhanced intensity error resilience with multiple chirped pulses and ``universal composite pulses''. This fast and robust coherent control technique should find wide applications in the field of quantum optics, laser cooling, and atom interferometry. This work is supported by National Key Research Program of China under Grant No. 2016YFA0302000, and NNSFC under Grant No. 11574053.