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Sample records for external fuel processor

  1. Fuel processors for fuel cell APU applications

    Science.gov (United States)

    Aicher, T.; Lenz, B.; Gschnell, F.; Groos, U.; Federici, F.; Caprile, L.; Parodi, L.

    The conversion of liquid hydrocarbons to a hydrogen rich product gas is a central process step in fuel processors for auxiliary power units (APUs) for vehicles of all kinds. The selection of the reforming process depends on the fuel and the type of the fuel cell. For vehicle power trains, liquid hydrocarbons like gasoline, kerosene, and diesel are utilized and, therefore, they will also be the fuel for the respective APU systems. The fuel cells commonly envisioned for mobile APU applications are molten carbonate fuel cells (MCFC), solid oxide fuel cells (SOFC), and proton exchange membrane fuel cells (PEMFC). Since high-temperature fuel cells, e.g. MCFCs or SOFCs, can be supplied with a feed gas that contains carbon monoxide (CO) their fuel processor does not require reactors for CO reduction and removal. For PEMFCs on the other hand, CO concentrations in the feed gas must not exceed 50 ppm, better 20 ppm, which requires additional reactors downstream of the reforming reactor. This paper gives an overview of the current state of the fuel processor development for APU applications and APU system developments. Furthermore, it will present the latest developments at Fraunhofer ISE regarding fuel processors for high-temperature fuel cell APU systems on board of ships and aircrafts.

  2. Automotive Fuel Processor Development and Demonstration with Fuel Cell Systems

    Energy Technology Data Exchange (ETDEWEB)

    Nuvera Fuel Cells

    2005-04-15

    The potential for fuel cell systems to improve energy efficiency and reduce emissions over conventional power systems has generated significant interest in fuel cell technologies. While fuel cells are being investigated for use in many applications such as stationary power generation and small portable devices, transportation applications present some unique challenges for fuel cell technology. Due to their lower operating temperature and non-brittle materials, most transportation work is focusing on fuel cells using proton exchange membrane (PEM) technology. Since PEM fuel cells are fueled by hydrogen, major obstacles to their widespread use are the lack of an available hydrogen fueling infrastructure and hydrogen's relatively low energy storage density, which leads to a much lower driving range than conventional vehicles. One potential solution to the hydrogen infrastructure and storage density issues is to convert a conventional fuel such as gasoline into hydrogen onboard the vehicle using a fuel processor. Figure 2 shows that gasoline stores roughly 7 times more energy per volume than pressurized hydrogen gas at 700 bar and 4 times more than liquid hydrogen. If integrated properly, the fuel processor/fuel cell system would also be more efficient than traditional engines and would give a fuel economy benefit while hydrogen storage and distribution issues are being investigated. Widespread implementation of fuel processor/fuel cell systems requires improvements in several aspects of the technology, including size, startup time, transient response time, and cost. In addition, the ability to operate on a number of hydrocarbon fuels that are available through the existing infrastructure is a key enabler for commercializing these systems. In this program, Nuvera Fuel Cells collaborated with the Department of Energy (DOE) to develop efficient, low-emission, multi-fuel processors for transportation applications. Nuvera's focus was on (1) developing fuel

  3. Summary report : universal fuel processor.

    Energy Technology Data Exchange (ETDEWEB)

    Coker, Eric Nicholas; Rice, Steven F. (Sandia National Laboratories, Livermore, CA); Kemp, Richard Alan; Stewart, Constantine A.; Miller, James Edward; Cornelius, Christopher James; Staiger, Chad Lynn; Pickett, Lyle M. (Sandia National Laboratories, Livermore, CA)

    2008-01-01

    The United States produces only about 1/3 of the more than 20 million barrels of petroleum that it consumes daily. Oil imports into the country are roughly equivalent to the amount consumed in the transportation sector. Hence the nation in general, and the transportation sector in particular, is vulnerable to supply disruptions and price shocks. The situation is anticipated to worsen as the competition for limited global supplies increases and oil-rich nations become increasingly willing to manipulate the markets for this resource as a means to achieve political ends. The goal of this project was the development and improvement of technologies and the knowledge base necessary to produce and qualify a universal fuel from diverse feedstocks readily available in North America and elsewhere (e.g. petroleum, natural gas, coal, biomass) as a prudent and positive step towards mitigating this vulnerability. Three major focus areas, feedstock transformation, fuel formulation, and fuel characterization, were identified and each was addressed. The specific activities summarized herein were identified in consultation with industry to set the stage for collaboration. Two activities were undertaken in the area of feedstock transformation. The first activity focused on understanding the chemistry and operation of autothermal reforming, with an emphasis on understanding, and therefore preventing, soot formation. The second activity was focused on improving the economics of oxygen production, particularly for smaller operations, by integrating membrane separations with pressure swing adsorption. In the fuel formulation area, the chemistry of converting small molecules readily produced from syngas directly to fuels was examined. Consistent with the advice from industry, this activity avoided working on improving known approaches, giving it an exploratory flavor. Finally, the fuel characterization task focused on providing a direct and quantifiable comparison of diesel fuel and JP-8.

  4. High-pressure coal fuel processor development

    Energy Technology Data Exchange (ETDEWEB)

    Greenhalgh, M.L.

    1992-11-01

    The objective of Subtask 1.1 Engine Feasibility was to conduct research needed to establish the technical feasibility of ignition and stable combustion of directly injected, 3,000 psi, low-Btu gas with glow plug ignition assist at diesel engine compression ratios. This objective was accomplished by designing, fabricating, testing and analyzing the combustion performance of synthesized low-Btu coal gas in a single-cylinder test engine combustion rig located at the Caterpillar Technical Center engine lab in Mossville, Illinois. The objective of Subtask 1.2 Fuel Processor Feasibility was to conduct research needed to establish the technical feasibility of air-blown, fixed-bed, high-pressure coal fuel processing at up to 3,000 psi operating pressure, incorporating in-bed sulfur and particulate capture. This objective was accomplished by designing, fabricating, testing and analyzing the performance of bench-scale processors located at Coal Technology Corporation (subcontractor) facilities in Bristol, Virginia. These two subtasks were carried out at widely separated locations and will be discussed in separate sections of this report. They were, however, independent in that the composition of the synthetic coal gas used to fuel the combustion rig was adjusted to reflect the range of exit gas compositions being produced on the fuel processor rig. Two major conclusions resulted from this task. First, direct injected, ignition assisted Diesel cycle engine combustion systems can be suitably modified to efficiently utilize these low-Btu gas fuels. Second, high pressure gasification of selected run-of-the-mine coals in batch-loaded fuel processors is feasible. These two findings, taken together, significantly reduce the perceived technical risks associated with the further development of the proposed coal gas fueled Diesel cycle power plant concept.

  5. A self-sustained, complete and miniaturized methanol fuel processor for proton exchange membrane fuel cell

    Science.gov (United States)

    Yang, Mei; Jiao, Fengjun; Li, Shulian; Li, Hengqiang; Chen, Guangwen

    2015-08-01

    A self-sustained, complete and miniaturized methanol fuel processor has been developed based on modular integration and microreactor technology. The fuel processor is comprised of one methanol oxidative reformer, one methanol combustor and one two-stage CO preferential oxidation unit. Microchannel heat exchanger is employed to recover heat from hot stream, miniaturize system size and thus achieve high energy utilization efficiency. By optimized thermal management and proper operation parameter control, the fuel processor can start up in 10 min at room temperature without external heating. A self-sustained state is achieved with H2 production rate of 0.99 Nm3 h-1 and extremely low CO content below 25 ppm. This amount of H2 is sufficient to supply a 1 kWe proton exchange membrane fuel cell. The corresponding thermal efficiency of whole processor is higher than 86%. The size and weight of the assembled reactors integrated with microchannel heat exchangers are 1.4 L and 5.3 kg, respectively, demonstrating a very compact construction of the fuel processor.

  6. Shortcut model for water-balanced operation in fuel processor fuel cell systems

    NARCIS (Netherlands)

    Biesheuvel, P.M.; Kramer, G.J.

    2004-01-01

    In a fuel processor, a hydrocarbon or oxygenate fuel is catalytically converted into a mixture rich in hydrogen which can be fed to a fuel cell to generate electricity. In these fuel processor fuel cell systems (FPFCs), water is recovered from the exhaust gases and recycled back into the system. We

  7. External fuel thermionic reactor system.

    Science.gov (United States)

    Mondt, J. F.; Peelgren, M. L.

    1971-01-01

    Thermionic reactors are prime candidates for nuclear electric propulsion. The national thermionic reactor effort is concentrated on the flashlight concept with the external-fuel concept as the backup. The external-fuel concept is very adaptable to a completely modular power subsystem which is attractive for highly reliable long-life applications. The 20- to 25-cm long, externally-fueled converters have been designed, fabricated, and successfully tested with many thermal cycles by electrical heating. However, difficulties have been encountered during encapsulation for nuclear heated tests and none have been started to date. These nuclear tests are required to demonstrate the concept feasibility.

  8. Modeling and control of fuel cell systems and fuel processors

    Science.gov (United States)

    Pukrushpan, Jay Tawee

    Fuel cell systems offer clean and efficient energy production and are currently under intensive development by several manufacturers for both stationary and mobile applications. The viability, efficiency, and robustness of this technology depend on understanding, predicting, and controlling the unique transient behavior of the fuel cell system. In this thesis, we employ phenomenological modeling and multivariable control techniques to provide fast and consistent system dynamic behavior. Moreover, a framework for analyzing and evaluating different control architectures and sensor sets is provided. Two fuel cell related control problems are investigated in this study, namely, the control of the cathode oxygen supply for a high-pressure direct hydrogen Fuel Cell System (FCS) and control of the anode hydrogen supply from a natural gas Fuel Processor System (FPS). System dynamic analysis and control design is carried out using model-based linear control approaches. A system level dynamic model suitable for each control problem is developed from physics-based component models. The transient behavior captured in the model includes flow characteristics, inertia dynamics, lumped-volume manifold filling dynamics, time evolving spatially-homogeneous reactant pressure or mole fraction, membrane humidity, and the Catalytic Partial Oxidation (CPOX) reactor temperature. The goal of the FCS control problem is to effectively regulate the oxygen concentration in the cathode by quickly and accurately replenishing oxygen depleted during power generation. The features and limitations of different control configurations and the effect of various measurement on the control performance are examined. For example, an observability analysis suggests using the stack voltage measurement as feedback to the observer-based controller to improve the closed loop performance. The objective of the FPS control system is to regulate both the CPOX temperature and anode hydrogen concentration. Linear

  9. A light hydrocarbon fuel processor producing high-purity hydrogen

    Science.gov (United States)

    Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

    This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with thermal efficiency is

  10. Compact gasoline fuel processor for passenger vehicle APU

    Science.gov (United States)

    Severin, Christopher; Pischinger, Stefan; Ogrzewalla, Jürgen

    Due to the increasing demand for electrical power in today's passenger vehicles, and with the requirements regarding fuel consumption and environmental sustainability tightening, a fuel cell-based auxiliary power unit (APU) becomes a promising alternative to the conventional generation of electrical energy via internal combustion engine, generator and battery. It is obvious that the on-board stored fuel has to be used for the fuel cell system, thus, gasoline or diesel has to be reformed on board. This makes the auxiliary power unit a complex integrated system of stack, air supply, fuel processor, electrics as well as heat and water management. Aside from proving the technical feasibility of such a system, the development has to address three major barriers:start-up time, costs, and size/weight of the systems. In this paper a packaging concept for an auxiliary power unit is presented. The main emphasis is placed on the fuel processor, as good packaging of this large subsystem has the strongest impact on overall size. The fuel processor system consists of an autothermal reformer in combination with water-gas shift and selective oxidation stages, based on adiabatic reactors with inter-cooling. The configuration was realized in a laboratory set-up and experimentally investigated. The results gained from this confirm a general suitability for mobile applications. A start-up time of 30 min was measured, while a potential reduction to 10 min seems feasible. An overall fuel processor efficiency of about 77% was measured. On the basis of the know-how gained by the experimental investigation of the laboratory set-up a packaging concept was developed. Using state-of-the-art catalyst and heat exchanger technology, the volumes of these components are fixed. However, the overall volume is higher mainly due to mixing zones and flow ducts, which do not contribute to the chemical or thermal function of the system. Thus, the concept developed mainly focuses on minimization of those

  11. JP-8 catalytic cracking for compact fuel processors

    Science.gov (United States)

    Campbell, Timothy J.; Shaaban, Aly H.; Holcomb, Franklin H.; Salavani, Reza; Binder, Michael J.

    In processing heavier hydrocarbons such as military logistic fuels (JP-4, JP-5, JP-8, and JP-100), kerosene, gasoline, and diesel to produce hydrogen for fuel cell use, several issues arise. First, these fuels have high sulfur content, which can poison and deactivate components of the reforming process and the fuel cell stack; second, these fuels may contain non-volatile residue (NVR), up to 1.5 vol.%, which could potentially accumulate in a fuel processor; and third is the high coking potential of heavy hydrocarbons. Catalytic cracking of a distillate fuel prior to reforming can resolve these issues. Cracking using an appropriate catalyst can convert the various heavy organosulfur species in the fuel to lighter sulfur species such as hydrogen sulfide (H 2S), facilitating subsequent sulfur adsorption on zinc oxide (ZnO). Cracking followed by separation of light cracked gas from heavies effectively eliminates non-volatile aromatic species. Catalytic cracking can also convert heavier hydrocarbons to lights (C 1-C 3) at high conversion, which reduces the potential for coke formation in the reforming process. In this study, two types of catalysts were compared for JP-8 cracking performance: commercially-available zeolite materials similar to catalysts formulated for fluidized catalytic cracking (FCC) processes, and a novel manganese/alumina catalyst, which was previously reported to provide high selectivity to lights and low coke yield. Experiments were designed to test each catalyst's effectiveness under the high space velocity conditions necessary for use in compact, lightweight fuel processor systems. Cracking conversion results, as well as sulfur and hydrocarbon distributions in the light cracked gas, are presented for the two catalysts to provide a performance comparison.

  12. A compact and highly efficient natural gas fuel processor for 1-kW residential polymer electrolyte membrane fuel cells

    Science.gov (United States)

    Lee, Doohwan; Lee, Hyun Chul; Lee, Kang Hee; Kim, Soonho

    A compact and highly efficient natural gas fuel processor for 1-kW residential polymer electrolyte membrane fuel cells (PEMFCs) has been developed at the Samsung Advanced Institute of Technology (SAIT). The fuel processor, referred to as SFP-2, consists of a natural gas reformer, a water-gas shift reactor, a heat-exchanger and a burner, in which the overall integrated volume including insulation is exceptionally small, namely, about 14 l. The SFP-2 produces hydrogen at 1000 l h -1 (STP) at full load with the carbon monoxide concentration in the process gas below 7000 ppmv (dry gas base). The maximum thermal efficiency is ∼78% (lower heating value) at full load and even ∼72% at 25% partial load. This fuel processor of small size with high thermal efficiency is one of the best such technologies for the above given H 2 throughputs. The time required for starting up the SFP-2 is within 20 min with the addition of external heating for the shift reactor. No additional medium, such as nitrogen, is required either for start-up or for shut down of the SFP-2, which is an advantage for application in residential PEMFC co-generations systems.

  13. Diesel fuel processor for hydrogen production for 5 kW fuel cell application

    Energy Technology Data Exchange (ETDEWEB)

    Sopena, D.; Melgar, A.; Briceno, Y. [Fundacion CIDAUT. Parque Tecnologico de Boecillo, P. 209, 47151 Boecillo (Valladolid) (Spain); Navarro, R.M.; Alvarez-Galvan, M.C. [Instituto de Catalisis y Petroquimica (CSIC), C/ Marie Curie 2, Cantoblanco (Madrid) (Spain); Rosa, F. [Instituto Nacional de Tecnica Aeroespacial, Carretera San Juan del Puerto-Matalascanas, km 33, 21130 Mazagon-Moguer (Huelva) (Spain)

    2007-07-15

    The present paper describes a diesel fuel processor designed to produce hydrogen to feed a PEM fuel cell of 5 kW. The fuel processor includes three reactors in series: (1) oxidative steam reforming reactor; (2) one-step water gas shift reactor; and (3) a preferential oxidation reactor. The design of the system was accomplished by means of a one-dimensional model. A specific study of the fuel-air mixing chamber was carried out with Fluent by taking into account fuel evaporation and cool flame processes. The assembly of the installation allowed the characterisation of each component and the control of each working parameter. The first experimental results obtained in the reformer system using decaline and diesel fuels demonstrate the feasibility of the design to produce hydrogen suitable to feed a PEM fuel cell. (author)

  14. Hydrogen production with integrated microchannel fuel processor for portable fuel cell systems

    Science.gov (United States)

    Park, Gu-Gon; Yim, Sung-Dae; Yoon, Young-Gi; Lee, Won-Yong; Kim, Chang-Soo; Seo, Dong-Joo; Eguchi, Koichi

    An integrated microchannel methanol processor was developed by assembling unit reactors, which were fabricated by stacking and bonding microchannel patterned stainless steel plates, including fuel vaporizer, heat exchanger, catalytic combustor and steam reformer. Commercially available Cu/ZnO/Al 2O 3 catalyst was coated inside the microchannel of the unit reactor for steam reforming. Pt/Al 2O 3 pellets prepared by 'incipient wetness' were filled in the cavity reactor for catalytic combustion. Those unit reactors were integrated to develop the fuel processor and operated at different reaction conditions to optimize the reactor performance, including methanol steam reformer and methanol catalytic combustor. The optimized fuel processor has the dimensions of 60 mm × 40 mm × 30 mm, and produced 450sccm reformed gas containing 73.3% H 2, 24.5% CO 2 and 2.2% CO at 230-260 °C which can produce power output of 59 Wt.

  15. Ceramic Microchannel Development for Compact Fuel Processors of Hydrocarbon Fuels

    Science.gov (United States)

    Bae, J.-M.; Ahmed, S.; Kumar, R.; Doss, E.

    Fuel processing is a bridging technology for faster commercialization of fuel cell system under lack of hydrogen infrastructures. Argonne national laboratory has been developing fuel processing technologies for fuel cell based electric power. We have reported the development of novel catalysts that are active and selective for hydrocarbon reforming reactions. It has been realized, however, that with pellet or conventional honeycomb catalysts, the reforming process is mass transport limited. This paper reports the development of catalyst structures with microchannels that are able to reduce the diffusion resistance and thereby achieve the same production rate within a smaller reactor bed. These microchannel reforming catalysts were prepared and tested with natural gas and gasoline-type fuels in a microreactor (1-cm dia.) at space velocities of up to 250,000 per hour. These catalysts have also been used in engineering-scale reactors (10 kWe, 7-cm dia.) with similar product qualities. Compared to pellet catalysts, the microchannel catalysts enable a nearly 5-fold reduction in catalyst weight and volume.

  16. A natural-gas fuel processor for a residential fuel cell system

    Science.gov (United States)

    Adachi, H.; Ahmed, S.; Lee, S. H. D.; Papadias, D.; Ahluwalia, R. K.; Bendert, J. C.; Kanner, S. A.; Yamazaki, Y.

    A system model was used to develop an autothermal reforming fuel processor to meet the targets of 80% efficiency (higher heating value) and start-up energy consumption of less than 500 kJ when operated as part of a 1-kWe natural-gas fueled fuel cell system for cogeneration of heat and power. The key catalytic reactors of the fuel processor - namely the autothermal reformer, a two-stage water gas shift reactor and a preferential oxidation reactor - were configured and tested in a breadboard apparatus. Experimental results demonstrated a reformate containing ∼48% hydrogen (on a dry basis and with pure methane as fuel) and less than 5 ppm CO. The effects of steam-to-carbon and part load operations were explored.

  17. Deployable Fuel Cell Power Generator - Multi-Fuel Processor

    Science.gov (United States)

    2009-02-01

    apparent difference between the two investigations is the catalyst; however, the larger capacity of the packed-bed over that of microchannel reactor might...Steam Reforming Reactor and the Radiant Burner ................................................................... 7  6: Combustion Fuel Vaporizer...demonstrate the direct steam reforming concept. Packed-bed steam reforming reactor and coiled tube steam generator with radiant burners were used. The

  18. External cost assessment for nuclear fuel cycle

    Energy Technology Data Exchange (ETDEWEB)

    Park, Byung Heung [Korea National University of Transportation, Chungju (Korea, Republic of); Ko, Won Il [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2015-12-15

    Nuclear power is currently the second largest power supply method in Korea and the number of nuclear power plants are planned to be increased as well. However, clear management policy for spent fuels generated from nuclear power plants has not yet been established. The back-end fuel cycle, associated with nuclear material flow after nuclear reactors is a collection of technologies designed for the spent fuel management and the spent fuel management policy is closely related with the selection of a nuclear fuel cycle. Cost is an important consideration in selection of a nuclear fuel cycle and should be determined by adding external cost to private cost. Unlike the private cost, which is a direct cost, studies on the external cost are focused on nuclear reactors and not at the nuclear fuel cycle. In this research, external cost indicators applicable to nuclear fuel cycle were derived and quantified. OT (once through), DUPIC (Direct Use of PWR SF in CANDU), PWR-MOX (PWR PUREX reprocessing), and Pyro-SFR (SFR recycling with pyroprocessing) were selected as nuclear fuel cycles which could be considered for estimating external cost in Korea. Energy supply security cost, accident risk cost, and acceptance cost were defined as external cost according to precedent and estimated after analyzing approaches which have been adopted for estimating external costs on nuclear power generation.

  19. Model-Based Design of Energy Efficient Palladium Membrane Water Gas Shift Fuel Processors for PEM Fuel Cell Power Plants

    Science.gov (United States)

    Gummalla, Mallika; Vanderspurt, Thomas Henry; Emerson, Sean; She, Ying; Dardas, Zissis; Olsommer, Benoît

    An integrated, palladium alloy membrane Water-Gas Shift (WGS) reactor can significantly reduce the size, cost and complexity of a fuel processor for a Polymer Electrolyte Membrane fuel cell power system.

  20. Catalyst development and systems analysis of methanol partial oxidation for the fuel processor - fuel cell integration

    Energy Technology Data Exchange (ETDEWEB)

    Newson, E.; Mizsey, P.; Hottinger, P.; Truong, T.B.; Roth, F. von; Schucan, Th.H. [Paul Scherrer Inst. (PSI), Villigen (Switzerland)

    1999-08-01

    Methanol partial oxidation (pox) to produce hydrogen for mobile fuel cell applications has proved initially more successful than hydrocarbon pox. Recent results of catalyst screening and kinetic studies with methanol show that hydrogen production rates have reached 7000 litres/hour/(litre reactor volume) for the dry pox route and 12,000 litres/hour/(litre reactor volume) for wet pox. These rates are equivalent to 21 and 35 kW{sub th}/(litre reactor volume) respectively. The reaction engineering problems remain to be solved for dry pox due to the significant exotherm of the reaction (hot spots of 100-200{sup o}C), but wet pox is essentially isothermal in operation. Analyses of the integrated fuel processor - fuel cell systems show that two routes are available to satisfy the sensitivity of the fuel cell catalysts to carbon monoxide, i.e. a preferential oxidation reactor or a membrane separator. Targets for individual system components are evaluated for the base and best case systems for both routes to reach the combined 40% efficiency required for the integrated fuel processor - fuel cell system. (author) 2 figs., 1 tab., 3 refs.

  1. A diesel fuel processor for fuel-cell-based auxiliary power unit applications

    Science.gov (United States)

    Samsun, Remzi Can; Krekel, Daniel; Pasel, Joachim; Prawitz, Matthias; Peters, Ralf; Stolten, Detlef

    2017-07-01

    Producing a hydrogen-rich gas from diesel fuel enables the efficient generation of electricity in a fuel-cell-based auxiliary power unit. In recent years, significant progress has been achieved in diesel reforming. One issue encountered is the stable operation of water-gas shift reactors with real reformates. A new fuel processor is developed using a commercial shift catalyst. The system is operated using optimized start-up and shut-down strategies. Experiments with diesel and kerosene fuels show slight performance drops in the shift reactor during continuous operation for 100 h. CO concentrations much lower than the target value are achieved during system operation in auxiliary power unit mode at partial loads of up to 60%. The regeneration leads to full recovery of the shift activity. Finally, a new operation strategy is developed whereby the gas hourly space velocity of the shift stages is re-designed. This strategy is validated using different diesel and kerosene fuels, showing a maximum CO concentration of 1.5% at the fuel processor outlet under extreme conditions, which can be tolerated by a high-temperature PEFC. The proposed operation strategy solves the issue of strong performance drop in the shift reactor and makes this technology available for reducing emissions in the transportation sector.

  2. Performance assessment of a spiral methanol to hydrogen fuel processor for fuel cell applications

    Institute of Scientific and Technical Information of China (English)

    Foad Mehri; Majid Taghizadeh

    2012-01-01

    A novel design of plate-type microchannel reactor has been developed for fuel cell-grade hydrogen production.Commercial Cu/Zn/Al2O3 was used as catalyst for the reforming reaction,and its effectiveness was evaluated on the mole fraction of products,methanol conversion,hydrogen yield and the amount of carbon monoxide under various operating conditions.Subsequently,0.5 wt% Ru/Al2O3 as methanation catalyst was prepared by impregnation method and coupled with MSR step to evaluate the capability of methanol processor for CO reduction.Based on the experimental results,the optimum conditions were obtained as feed flow rate of 5 mL/h and temperature of 250℃,leading to a low CO selectivity and high H2 yield.The designed reformer with catalyst coated layer was compared with the conventional packed bed reformer at the same operating conditions.The constructed fuel processor had a good performance and excellent capability for on-board hydrogen production.

  3. Development of 50 kW Fuel Processor for Stationary Fuel Cell Applications

    Energy Technology Data Exchange (ETDEWEB)

    James F. Stevens; Balaji Krishnamurthy; Paolina Atanassova; Kerry Spilker

    2007-08-29

    The objective of the project was to develop and test a fuel processor capable of producing high hydrogen concentration (>98%) with less than ppm quantities of carbon dioxide and carbon monoxide at lower capital cost and higher efficiency, compared to conventional natural gas reformers. It was intended that we achieve our objective by developing simple reactor/process design, and high durability CO2 absorbents, to replace pressure swing adsorption (PSA) or membrane separators. Cost analysis indicated that we would not meet DOE cost goals so the project was terminated before construction of the full scale fuel processor. The work on adsorbent development was focused on the development of calcium oxide-based reversible CO2 absorbents with various microstructures and morphologies to determine the optimum microstructure for long-term reversible CO2 absorption. The effect of powder production process variables was systematically studied including: the final target compositions, the reagents from which the final products were derived, the pore forming additives, the processing time and temperature. The sorbent materials were characterized in terms of their performance in the reversible reaction with CO2 and correlation made to their microstructure.

  4. Metal membrane-type 25-kW methanol fuel processor for fuel-cell hybrid vehicle

    Science.gov (United States)

    Han, Jaesung; Lee, Seok-Min; Chang, Hyuksang

    A 25-kW on-board methanol fuel processor has been developed. It consists of a methanol steam reformer, which converts methanol to hydrogen-rich gas mixture, and two metal membrane modules, which clean-up the gas mixture to high-purity hydrogen. It produces hydrogen at rates up to 25 N m 3/h and the purity of the product hydrogen is over 99.9995% with a CO content of less than 1 ppm. In this fuel processor, the operating condition of the reformer and the metal membrane modules is nearly the same, so that operation is simple and the overall system construction is compact by eliminating the extensive temperature control of the intermediate gas streams. The recovery of hydrogen in the metal membrane units is maintained at 70-75% by the control of the pressure in the system, and the remaining 25-30% hydrogen is recycled to a catalytic combustion zone to supply heat for the methanol steam-reforming reaction. The thermal efficiency of the fuel processor is about 75% and the inlet air pressure is as low as 4 psi. The fuel processor is currently being integrated with 25-kW polymer electrolyte membrane fuel-cell (PEMFC) stack developed by the Hyundai Motor Company. The stack exhibits the same performance as those with pure hydrogen, which proves that the maximum power output as well as the minimum stack degradation is possible with this fuel processor. This fuel-cell 'engine' is to be installed in a hybrid passenger vehicle for road testing.

  5. Diesel fuel processor for PEM fuel cells: Two possible alternatives (ATR versus SR)

    Science.gov (United States)

    Cutillo, A.; Specchia, S.; Antonini, M.; Saracco, G.; Specchia, V.

    There are large efforts in exploring the on-board reforming technologies, which would avoid the actual lack of hydrogen infrastructure and related safety issues. From this view point, the present work deals with the comparison between two different 10 kW e fuel processors (FP) systems for the production of hydrogen-rich fuel gas starting from diesel oil, based respectively on autothermal (ATR) and steam-reforming (SR) process and related CO clean-up technologies; the obtained hydrogen rich gas is fed to the PEMFC stack of an auxiliary power unit (APU). Based on a series of simulations with Matlab/Simulink, the two systems were compared in terms of FP and APU efficiency, hydrogen concentration fed to the FC, water balance and process scheme complexity. Notwithstanding a slightly higher process scheme complexity and a slightly more difficult water recovery, the FP based on the SR scheme, as compared to the ATR one, shows higher efficiency and larger hydrogen concentration for the stream fed to the PEMFC anode, which represent key issues for auxiliary power generation based on FCs as compared, e.g. to alternators.

  6. Autothermal and partial oxidation reformer-based fuel processor, method for improving catalyst function in autothermal and partial oxidation reformer-based processors

    Science.gov (United States)

    Ahmed, Shabbir; Papadias, Dionissios D.; Lee, Sheldon H. D.; Ahluwalia, Rajesh K.

    2013-01-08

    The invention provides a fuel processor comprising a linear flow structure having an upstream portion and a downstream portion; a first catalyst supported at the upstream portion; and a second catalyst supported at the downstream portion, wherein the first catalyst is in fluid communication with the second catalyst. Also provided is a method for reforming fuel, the method comprising contacting the fuel to an oxidation catalyst so as to partially oxidize the fuel and generate heat; warming incoming fuel with the heat while simultaneously warming a reforming catalyst with the heat; and reacting the partially oxidized fuel with steam using the reforming catalyst.

  7. High-pressure coal fuel processor development. Task 1, Proof of principle testing

    Energy Technology Data Exchange (ETDEWEB)

    Greenhalgh, M.L.

    1992-11-01

    The objective of Subtask 1.1 Engine Feasibility was to conduct research needed to establish the technical feasibility of ignition and stable combustion of directly injected, 3,000 psi, low-Btu gas with glow plug ignition assist at diesel engine compression ratios. This objective was accomplished by designing, fabricating, testing and analyzing the combustion performance of synthesized low-Btu coal gas in a single-cylinder test engine combustion rig located at the Caterpillar Technical Center engine lab in Mossville, Illinois. The objective of Subtask 1.2 Fuel Processor Feasibility was to conduct research needed to establish the technical feasibility of air-blown, fixed-bed, high-pressure coal fuel processing at up to 3,000 psi operating pressure, incorporating in-bed sulfur and particulate capture. This objective was accomplished by designing, fabricating, testing and analyzing the performance of bench-scale processors located at Coal Technology Corporation (subcontractor) facilities in Bristol, Virginia. These two subtasks were carried out at widely separated locations and will be discussed in separate sections of this report. They were, however, independent in that the composition of the synthetic coal gas used to fuel the combustion rig was adjusted to reflect the range of exit gas compositions being produced on the fuel processor rig. Two major conclusions resulted from this task. First, direct injected, ignition assisted Diesel cycle engine combustion systems can be suitably modified to efficiently utilize these low-Btu gas fuels. Second, high pressure gasification of selected run-of-the-mine coals in batch-loaded fuel processors is feasible. These two findings, taken together, significantly reduce the perceived technical risks associated with the further development of the proposed coal gas fueled Diesel cycle power plant concept.

  8. Conceptual design and selection of a biodiesel fuel processor for a vehicle fuel cell auxiliary power unit

    Science.gov (United States)

    Specchia, S.; Tillemans, F. W. A.; van den Oosterkamp, P. F.; Saracco, G.

    Within the European project BIOFEAT (biodiesel fuel processor for a fuel cell auxiliary power unit for a vehicle), a complete modular 10 kW e biodiesel fuel processor capable of feeding a PEMFC will be developed, built and tested to generate electricity for a vehicle auxiliary power unit (APU). Tail pipe emissions reduction, increased use of renewable fuels, increase of hydrogen-fuel economy and efficient supply of present and future APU for road vehicles are the main project goals. Biodiesel is the chosen feedstock because it is a completely natural and thus renewable fuel. Three fuel processing options were taken into account at a conceptual design level and compared for hydrogen production: (i) autothermal reformer (ATR) with high and low temperature shift (HTS/LTS) reactors; (ii) autothermal reformer (ATR) with a single medium temperature shift (MTS) reactor; (iii) thermal cracker (TC) with high and low temperature shift (HTS/LTS) reactors. Based on a number of simulations (with the AspenPlus® software), the best operating conditions were determined (steam-to-carbon and O 2/C ratios, operating temperatures and pressures) for each process alternative. The selection of the preferential fuel processing option was consequently carried out, based on a number of criteria (efficiency, complexity, compactness, safety, controllability, emissions, etc.); the ATR with both HTS and LTS reactors shows the most promising results, with a net electrical efficiency of 29% (LHV).

  9. Vehicle Fuel-Efficiency Choices, Emission Externalities, and Urban Sprawl

    DEFF Research Database (Denmark)

    Kim, Jinwon

    of excessive sprawl arising from emission externalities is the uses of larger and less-fuel efficient vehicles by suburban residents, which is different from that of congestion externalities. We also analyze the effect of the Corporate Average Fuel Efficiency (CAFE) regulation on the urban spatial structure....

  10. Experimental study of external fuel vaporization

    Science.gov (United States)

    Szetela, E. J.; Tevelde, J. A.

    1982-01-01

    The fuel properties used in the design of a flash vaporization system for aircraft gas turbine engines were evaluated in experiments using a flowing system to determine critical temperature and pressure, boiling points, dew points, heat transfer coefficients, deposit formation rates, and deposit removal. Three fuels were included in the experiments: Jet-A, an experimental referree broad specification fuel, and a premium No. 2 diesel fuel. Engine conditions representing a NASA Energy Efficient Engine at sea-level take-off, cruise, and idle were simulated in the vaporization system and it was found that single phase flow was maintained in the heat exchanger and downstream of the throttle. Deposits encountered in the heat exchanger represented a thermal resistance as high as 1300 sq M K/watt and a deposit formation rate over 1000 gC/sq cm hr.

  11. Estimating Externalities of Natural Gas Fuel Cycles, Report 4

    Energy Technology Data Exchange (ETDEWEB)

    Barnthouse, L.W.; Cada, G.F.; Cheng, M.-D.; Easterly, C.E.; Kroodsma, R.L.; Lee, R.; Shriner, D.S.; Tolbert, V.R.; Turner, R.S.

    1998-01-01

    This report describes methods for estimating the external costs (and possibly benefits) to human health and the environment that result from natural gas fuel cycles. Although the concept of externalities is far from simple or precise, it generally refers to effects on individuals' well being, that result from a production or market activity in which the individuals do not participate, or are not fully compensated. In the past two years, the methodological approach that this report describes has quickly become a worldwide standard for estimating externalities of fuel cycles. The approach is generally applicable to any fuel cycle in which a resource, such as coal, hydro, or biomass, is used to generate electric power. This particular report focuses on the production activities, pollution, and impacts when natural gas is used to generate electric power. In the 1990s, natural gas technologies have become, in many countries, the least expensive to build and operate. The scope of this report is on how to estimate the value of externalities--where value is defined as individuals' willingness to pay for beneficial effects, or to avoid undesirable ones. This report is about the methodologies to estimate these externalities, not about how to internalize them through regulations or other public policies. Notwithstanding this limit in scope, consideration of externalities can not be done without considering regulatory, insurance, and other considerations because these institutional factors affect whether costs (and benefits) are in fact external, or whether they are already somehow internalized within the electric power market. Although this report considers such factors to some extent, much analysis yet remains to assess the extent to which estimated costs are indeed external. This report is one of a series of reports on estimating the externalities of fuel cycles. The other reports are on the coal, oil, biomass, hydro, and nuclear fuel cycles, and on general

  12. Fast start-up of microchannel fuel processor integrated with an igniter for hydrogen combustion

    Science.gov (United States)

    Ryi, Shin Kun; Park, Jong Soo; Cho, Song Ho; Kim, Sung Hyun

    A Pt-Zr catalyst coated FeCrAlY mesh is introduced into the combustion outlet conduit of a newly designed microchannel reactor (MCR) as an igniter of hydrogen combustion to decrease the start-up time. The catalyst is coated using a wash-coating method. After installing the Pt-Zr/FeCrAlY mesh, the reactor is heated to its running temperature within 1 min with hydrogen combustion. Two plate-type heat-exchangers are introduced at the combustion outlet and reforming outlet conduits of the microchannel reactor in order to recover the heat of the combustion gas and reformed gas, respectively. Using these heat-exchangers, methane steam reforming is carried out with hydrogen combustion and the reforming capacity and energy efficiency are enhanced by up to 3.4 and 1.7 times, respectively. A compact fuel processor and fuel-cell system using this reactor concept is expected to show considerable advancement.

  13. Estimating Externalities of Hydro Fuel Cycles, Report 6

    Energy Technology Data Exchange (ETDEWEB)

    Barnthouse, L.W.; Cada, G.F.; Cheng, M.-D.; Easterly, C.E.; Kroodsma, R.L.; Lee, R.; Shriner, D.S.; Tolbert, V.R.; Turner, R.S.

    1994-12-01

    There are three major objectives of this hydropower study: (1) to implement the methodological concepts that were developed in the background document (ORNL/RFF 1992) as a means of estimating the external costs and benefits of fuel cycles and, by so doing, to demonstrate their application to the hydroelectric fuel cycle (different fuel cycles have unique characteristics that need to be addressed in different ways); (2) to develop, given the time and resources, the best range of estimates of externalities associated with hydroelectric projects, using two benchmark projects at two reference sites in the US; and (3) to assess the state of the information that is available to support the estimation of externalities associated with the hydroelectric fuel cycle and, by so doing, to assist in identifying gaps in knowledge and in setting future research agendas. The main consideration in defining these objectives was a desire to have more information about externalities and a better method for estimating them. As set forth in the agreement between the US and the EC, the study is explicitly and intentionally not directed at any one audience. This study is about a methodology for estimating externalities. It is not about how to use estimates of externalities in a particular policy context.

  14. Estimating Externalities of Coal Fuel Cycles, Report 3

    Energy Technology Data Exchange (ETDEWEB)

    Barnthouse, L.W.; Cada, G.F.; Cheng, M.-D.; Easterly, C.E.; Kroodsma, R.L.; Lee, R.; Shriner, D.S.; Tolbert, V.R.; Turner, R.S.

    1994-09-01

    The agreement between the US DOE and the EC established the specific objectives of the study: (a) to develop a methodological framework that uses existing data and models to quantify the external costs and benefits of energy; (b) to demonstrate the application of the framework to estimate the externalities of the coal, biomass, oil, natural gas, hydro, nuclear, photovoltaic, and wind fuel cycles (by agreement with the EC, the US addressed the first six of these); and (c) to identify major gaps in the availability of information to quantify impacts, damages, benefits, and externalities of fuel cycles; and to suggest priorities for future research. The main consideration in defining these objectives was a desire to have more information about externalities, and a better method for estimating them.

  15. Estimating Fuel Cycle Externalities: Analytical Methods and Issues, Report 2

    Energy Technology Data Exchange (ETDEWEB)

    Barnthouse, L.W.; Cada, G.F.; Cheng, M.-D.; Easterly, C.E.; Kroodsma, R.L.; Lee, R.; Shriner, D.S.; Tolbert, V.R.; Turner, R.S.

    1994-07-01

    The activities that produce electric power typically range from extracting and transporting a fuel, to its conversion into electric power, and finally to the disposition of residual by-products. This chain of activities is called a fuel cycle. A fuel cycle has emissions and other effects that result in unintended consequences. When these consequences affect third parties (i.e., those other than the producers and consumers of the fuel-cycle activity) in a way that is not reflected in the price of electricity, they are termed ''hidden'' social costs or externalities. They are the economic value of environmental, health and any other impacts, that the price of electricity does not reflect. How do you estimate the externalities of fuel cycles? Our previous report describes a methodological framework for doing so--called the damage function approach. This approach consists of five steps: (1) characterize the most important fuel cycle activities and their discharges, where importance is based on the expected magnitude of their externalities, (2) estimate the changes in pollutant concentrations or other effects of those activities, by modeling the dispersion and transformation of each pollutant, (3) calculate the impacts on ecosystems, human health, and any other resources of value (such as man-made structures), (4) translate the estimates of impacts into economic terms to estimate damages and benefits, and (5) assess the extent to which these damages and benefits are externalities, not reflected in the price of electricity. Each step requires a different set of equations, models and analysis. Analysts generally believe this to be the best approach for estimating externalities, but it has hardly been used! The reason is that it requires considerable analysis and calculation, and to this point in time, the necessary equations and models have not been assembled. Equally important, the process of identifying and estimating externalities leads to a number

  16. PEM Fuel Cells with Bio-Ethanol Processor Systems A Multidisciplinary Study of Modelling, Simulation, Fault Diagnosis and Advanced Control

    CERN Document Server

    Feroldi, Diego; Outbib, Rachid

    2012-01-01

    An apparently appropriate control scheme for PEM fuel cells may actually lead to an inoperable plant when it is connected to other unit operations in a process with recycle streams and energy integration. PEM Fuel Cells with Bio-Ethanol Processor Systems presents a control system design that provides basic regulation of the hydrogen production process with PEM fuel cells. It then goes on to construct a fault diagnosis system to improve plant safety above this control structure. PEM Fuel Cells with Bio-Ethanol Processor Systems is divided into two parts: the first covers fuel cells and the second discusses plants for hydrogen production from bio-ethanol to feed PEM fuel cells. Both parts give detailed analyses of modeling, simulation, advanced control, and fault diagnosis. They give an extensive, in-depth discussion of the problems that can occur in fuel cell systems and propose a way to control these systems through advanced control algorithms. A significant part of the book is also given over to computer-aid...

  17. Key issues in the microchemical systems-based methanol fuel processor: Energy density, thermal integration, and heat loss mechanisms

    Science.gov (United States)

    Shah, Keyur; Besser, R. S.

    Microreactor technology is a promising approach in harnessing the high energy density of hydrocarbons and is being used to produce hydrogen-rich gases by reforming of methanol and other liquid hydrocarbons. However, on-demand H 2 generation for miniature proton exchange membrane fuel cell (PEMFC) systems has been a bottleneck problem, which has limited the development and demonstration of the PEMFC for high-performance portable power. A number of crucial challenges exist for the realization of practical portable fuel processors. Among these, the management of heat in a compact format is perhaps the most crucial challenge for portable fuel processors. In this study, a silicon microreactor-based catalytic methanol steam reforming reactor was designed, fabricated, and demonstrated in the context of complete thermal integration to understand this critical issue and develop a knowledge base required to rationally design and integrate the microchemical components of a fuel processor. Detailed thermal and reaction experiments were carried out to demonstrate the potential of microreactor-based on-demand H 2 generation. Based on thermal characterization experiments, the heat loss mechanisms and effective convective heat coefficients from the planar microreactor structure were determined and suggestions were made for scale up and implementation of packaging schemes to reduce different modes of heat losses.

  18. Development and design of experiments optimization of a high temperature proton exchange membrane fuel cell auxiliary power unit with onboard fuel processor

    Science.gov (United States)

    Karstedt, Jörg; Ogrzewalla, Jürgen; Severin, Christopher; Pischinger, Stefan

    In this work, the concept development, system layout, component simulation and the overall DOE system optimization of a HT-PEM fuel cell APU with a net electric power output of 4.5 kW and an onboard methane fuel processor are presented. A highly integrated system layout has been developed that enables fast startup within 7.5 min, a closed system water balance and high fuel processor efficiencies of up to 85% due to the recuperation of the anode offgas burner heat. The integration of the system battery into the load management enhances the transient electric performance and the maximum electric power output of the APU system. Simulation models of the carbon monoxide influence on HT-PEM cell voltage, the concentration and temperature profiles within the autothermal reformer (ATR) and the CO conversion rates within the watergas shift stages (WGSs) have been developed. They enable the optimization of the CO concentration in the anode gas of the fuel cell in order to achieve maximum system efficiencies and an optimized dimensioning of the ATR and WGS reactors. Furthermore a DOE optimization of the global system parameters cathode stoichiometry, anode stoichiometry, air/fuel ratio and steam/carbon ratio of the fuel processing system has been performed in order to achieve maximum system efficiencies for all system operating points under given boundary conditions.

  19. Fuel magnetization without external field coils (AutoMag)

    Science.gov (United States)

    Slutz, Stephen; Jennings, Christopher; Awe, Thomas; Shipley, Gabe; Lamppa, Derek; McBride, Ryan

    2016-10-01

    Magnetized Liner Inertial Fusion (MagLIF) has produced fusion-relevant plasma conditions on the Z accelerator where the fuel was magnetized using external field coils. We present a novel concept that does not need external field coils. This concept (AutoMag) magnetizes the fuel during the early part of the drive current by using a composite liner with helical conduction paths separated by insulating material. The drive is designed so the current rises slowly enough to avoid electrical breakdown of the insulators until a sufficiently strong magnetic field is established. Then the current rises more quickly, which causes the insulators to break down allowing the drive current to follow an axial path and implode the liner. Low inductance magnetically insulated power feeds can be used with AutoMag to increase the drive current without interfering with diagnostic access. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

  20. Self-sustained operation of a kW e-class kerosene-reforming processor for solid oxide fuel cells

    Science.gov (United States)

    Yoon, Sangho; Bae, Joongmyeon; Kim, Sunyoung; Yoo, Young-Sung

    In this paper, fuel-processing technologies are developed for application in residential power generation (RPG) in solid oxide fuel cells (SOFCs). Kerosene is selected as the fuel because of its high hydrogen density and because of the established infrastructure that already exists in South Korea. A kerosene fuel processor with two different reaction stages, autothermal reforming (ATR) and adsorptive desulfurization reactions, is developed for SOFC operations. ATR is suited to the reforming of liquid hydrocarbon fuels because oxygen-aided reactions can break the aromatics in the fuel and steam can suppress carbon deposition during the reforming reaction. ATR can also be implemented as a self-sustaining reactor due to the exothermicity of the reaction. The kW e self-sustained kerosene fuel processor, including the desulfurizer, operates for about 250 h in this study. This fuel processor does not require a heat exchanger between the ATR reactor and the desulfurizer or electric equipment for heat supply and fuel or water vaporization because a suitable temperature of the ATR reformate is reached for H 2S adsorption on the ZnO catalyst beds in desulfurizer. Although the CH 4 concentration in the reformate gas of the fuel processor is higher due to the lower temperature of ATR tail gas, SOFCs can directly use CH 4 as a fuel with the addition of sufficient steam feeds (H 2O/CH 4 ≥ 1.5), in contrast to low-temperature fuel cells. The reforming efficiency of the fuel processor is about 60%, and the desulfurizer removed H 2S to a sufficient level to allow for the operation of SOFCs.

  1. Estimating externalities of biomass fuel cycles, Report 7

    Energy Technology Data Exchange (ETDEWEB)

    Barnthouse, L.W.; Cada, G.F.; Cheng, M.-D.; Easterly, C.E.; Kroodsma, R.L.; Lee, R.; Shriner, D.S.; Tolbert, V.R.; Turner, R.S.

    1998-01-01

    This report documents the analysis of the biomass fuel cycle, in which biomass is combusted to produce electricity. The major objectives of this study were: (1) to implement the methodological concepts which were developed in the Background Document (ORNL/RFF 1992) as a means of estimating the external costs and benefits of fuel cycles, and by so doing, to demonstrate their application to the biomass fuel cycle; (2) to develop, given the time and resources, a range of estimates of marginal (i.e., the additional or incremental) damages and benefits associated with selected impact-pathways from a new wood-fired power plant, using a representative benchmark technology, at two reference sites in the US; and (3) to assess the state of the information available to support energy decision making and the estimation of externalities, and by so doing, to assist in identifying gaps in knowledge and in setting future research agendas. The demonstration of methods, modeling procedures, and use of scientific information was the most important objective of this study. It provides an illustrative example for those who will, in the future, undertake studies of actual energy options and sites. As in most studies, a more comprehensive analysis could have been completed had budget constraints not been as severe. Particularly affected were the air and water transport modeling, estimation of ecological impacts, and economic valuation. However, the most important objective of the study was to demonstrate methods, as a detailed example for future studies. Thus, having severe budget constraints was appropriate from the standpoint that these studies could also face similar constraints. Consequently, an important result of this study is an indication of what can be done in such studies, rather than the specific numerical estimates themselves.

  2. Analysis of the control structures for an integrated ethanol processor for proton exchange membrane fuel cell systems

    Science.gov (United States)

    Biset, S.; Nieto Deglioumini, L.; Basualdo, M.; Garcia, V. M.; Serra, M.

    The aim of this work is to investigate which would be a good preliminary plantwide control structure for the process of Hydrogen production from bioethanol to be used in a proton exchange membrane (PEM) accounting only steady-state information. The objective is to keep the process under optimal operation point, that is doing energy integration to achieve the maximum efficiency. Ethanol, produced from renewable feedstocks, feeds a fuel processor investigated for steam reforming, followed by high- and low-temperature shift reactors and preferential oxidation, which are coupled to a polymeric fuel cell. Applying steady-state simulation techniques and using thermodynamic models the performance of the complete system with two different control structures have been evaluated for the most typical perturbations. A sensitivity analysis for the key process variables together with the rigorous operability requirements for the fuel cell are taking into account for defining acceptable plantwide control structure. This is the first work showing an alternative control structure applied to this kind of process.

  3. Analysis of the control structures for an integrated ethanol processor for proton exchange membrane fuel cell systems

    Energy Technology Data Exchange (ETDEWEB)

    Biset, S.; Nieto Deglioumini, L.; Basualdo, M. [GIAIP-CIFASIS (UTN-FRRo-CONICET-UPCAM-UNR), BV. 27 de Febrero 210 Bis, S2000EZP Rosario (Argentina); Garcia, V.M.; Serra, M. [Institut de Robotica i Informatica Industrial, C. Llorens i Artigas 4-6, 08028 Barcelona (Spain)

    2009-07-01

    The aim of this work is to investigate which would be a good preliminary plantwide control structure for the process of Hydrogen production from bioethanol to be used in a proton exchange membrane (PEM) accounting only steady-state information. The objective is to keep the process under optimal operation point, that is doing energy integration to achieve the maximum efficiency. Ethanol, produced from renewable feedstocks, feeds a fuel processor investigated for steam reforming, followed by high- and low-temperature shift reactors and preferential oxidation, which are coupled to a polymeric fuel cell. Applying steady-state simulation techniques and using thermodynamic models the performance of the complete system with two different control structures have been evaluated for the most typical perturbations. A sensitivity analysis for the key process variables together with the rigorous operability requirements for the fuel cell are taking into account for defining acceptable plantwide control structure. This is the first work showing an alternative control structure applied to this kind of process. (author)

  4. Design of a Fuel Processor System for Generating Hydrogen for Automotive Applications

    Science.gov (United States)

    Kolavennu, Panini K.; Telotte, John C.; Palanki, Srinivas

    2006-01-01

    The objective of this paper is to design a train of tubular reactors that use a methane feed to produce hydrogen of the desired purity so that it can be utilized by a fuel cell for automotive applications. Reaction engineering principles, which are typically covered at the undergraduate level, are utilized to design this reactor train. It is shown…

  5. Potential External (non-DOE) Constraints on U.S. Fuel Cycle Options

    Energy Technology Data Exchange (ETDEWEB)

    Steven J. Piet

    2012-07-01

    The DOE Fuel Cycle Technologies (FCT) Program will be conducting a screening of fuel cycle options in FY2013 to help focus fuel cycle R&D activities. As part of this screening, performance criteria and go/no-go criteria are being identified. To help ensure that these criteria are consistent with current policy, an effort was initiated to identify the status and basis of potentially relevant regulations, laws, and policies that have been established external to DOE. As such regulations, laws, and policies may be beyond DOE’s control to change, they may constrain the screening criteria and internally-developed policy. This report contains a historical survey and analysis of publically available domestic documents that could pertain to external constraints on advanced nuclear fuel cycles. “External” is defined as public documents outside DOE. This effort did not include survey and analysis of constraints established internal to DOE.

  6. 2D and 3D fault basis for fuel cell diagnosis by external magnetic field measurements

    Science.gov (United States)

    Ifrek, Lyes; Cauffet, Gilles; Chadebec, Olivier; Bultel, Yann; Rosini, Sébastien; Rouveyre, Luc

    2017-07-01

    An original approach used for the identification of faults in fuel cell stacks is presented. It is based on the 3D reconstruction of the current density from external magnetic field measurements which is an ill-posed magnetostatic linear inverse problem. A suitable and original current density and magnetic field basis are proposed in order to define both local and global faults on a fuel cell stack. The inverse problem is regularized by truncated singular value decomposition (SVD) to ensure the uniqueness of the solution. Contribution to the topical issue "Electrical Engineering Symposium (SGE 2016)", edited by Adel Razek

  7. External costs of the nuclear fuel cycle. A scoping study to determine the external costs of the Dutch nuclear fuel cycle in accordance with the EC/US methodology

    Energy Technology Data Exchange (ETDEWEB)

    Dodd, D.H.

    1995-10-01

    This report describes the results of a scoping study to estimate the external costs of the Dutch nuclear fuel cycle. This study was performed within the framework of the Commission of the European Community`s External Costs of Fuel Cycles project. The external costs of a fuel cycle are those costs which are excluded from the standard calculation of the cost of electricity. These costs are borne by society as a whole and include, in particular, the health and environmental costs which result from the operation of the facilities involved in a given fuel cycle. At present the uranium enrichment, electricity generation and interim storage stages of the nuclear fuel cycle take place in the Netherlands. These stages of the Dutch nuclear fuel cycle have been studied in detail and the external costs associated with thse stages estimated using up-to-date site specific data. The other stages of the Dutch nuclear fuel cycle do not currently take place in the Netherlands. In general the external costs associated with these stages have been estimated using data from the literature. Relatively few transports of radioactive materials associated with the Dutch nuclear fuel cycle take place in the Netherlands and the external costs associated with all transports has been based on values in the literature. (orig.).

  8. Social externalities of fuel production in Paraná state -Brazil

    Directory of Open Access Journals (Sweden)

    Luiz Gustavo Antonio de Souza

    2014-12-01

    Full Text Available The accentuation of the climate change effects generates a positive prospect for the use of bioenergy at the expense of fossil fuels. There is an expansion of sugarcane in the state of Paraná. This growth combined with installation of new plants or expanding production capacity will benefit directly and indirectly the locational economic dynamics of cities. The aim of this paper is to understand the relevance of related economic activities to the production of ethanol compared to petroleum-based fuels amid new prospects. This article discusses the concept of productive agglomerations in the sectors in question from the perspective of social externalities. The indicator location quotient (LQ is used as a proxy for the presence of agglomeration and thus production of presence of social externalities. Formal Jobs data were used from the Annual List of Social Information (RAIS for sugarcane, ethanol, oil extraction and oil products sectors. In this case, it was found that the sugarcane and ethanol production sectors are relevant in the state, which leads to the inference of the presence of agglomeration and externalities economies. In the oil extraction industry and derivatives, however, its performance is incipient and timely. The results showed that the high capillarity from the sugarcane and ethanol sector can generate both a positive externality as a vulnerability.

  9. Liquid fueled external heating system for STM4-120 Stirling engine

    Science.gov (United States)

    Meijer, R. J.; Ziph, B.; Godett, T. M.

    1985-01-01

    The STM4-120 Stirling engine, currently under development at Stirling Thermal Motors, Inc., is a 40 kW variable stroke engine with indirect heating using a sodium heat pipe. The engine is functionally separated into an application independent Energy Conversion Unit (ECU) consisting of the Stirling cycle and drive heated by condensing sodium and the application dependent External Heating System (EHS), designed to supply the ECU with sodium vapor heated by the particular energy source, connected by tubes with mechanical couplings. This paper describes an External Heating System for the STM4-120 ECU designed for the combustion of liquid fuel, comprised of a recuperative preheater, a combustion chamber, and a heat exchanger/evaporator where heat is transferred from the flue gas to the sodium causing it to evaporate. The design concept and projected performance are described and discussed.

  10. Adaptation to high current using low external resistances eliminates power overshoot in microbial fuel cells

    KAUST Repository

    Hong, Yiying

    2011-10-01

    One form of power overshoot commonly observed with mixed culture microbial fuel cells (MFCs) is doubling back of the power density curve at higher current densities, but the reasons for this type of overshoot have not been well explored. To investigate this, MFCs were acclimated to different external resistances, producing a range of anode potentials and current densities. Power overshoot was observed for reactors acclimated to higher (500 and 5000. Ω) but not lower (5 and 50. Ω) resistances. Acclimation of the high external resistance reactors for a few cycles to low external resistance (5. Ω), and therefore higher current densities, eliminated power overshoot. MFCs initially acclimated to low external resistances exhibited both higher current in cyclic voltammograms (CVs) and higher levels of redox activity over a broader range of anode potentials (-0.4 to 0. V; vs. a Ag/AgCl electrode) based on first derivative cyclic voltammetry (DCV) plots. Reactors acclimated to higher external resistances produced lower current in CVs, exhibited lower redox activity over a narrower anode potential range (-0.4 to -0.2. V vs. Ag/AgCl), and failed to produce higher currents above ∼-0.3. V (vs. Ag/AgCl). After the higher resistance reactors were acclimated to the lowest resistance they also exhibited similar CV and DCV profiles. Our findings show that to avoid overshoot, prior to the polarization and power density tests the anode biofilm must adapt to low external resistances to be capable of higher currents. © 2011 Elsevier B.V.

  11. Phenomenology of break-up modes in contact free externally heated nanoparticle laden fuel droplets

    Science.gov (United States)

    Pathak, Binita; Basu, Saptarshi

    2016-12-01

    We study thermally induced atomization modes in contact free (acoustically levitated) nanoparticle laden fuel droplets. The initial droplet size, external heat supplied, and suspended particle concentration (wt. %) in droplets govern the stability criterion which ultimately determines the dominant mode of atomization. Pure fuel droplets exhibit two dominant modes of breakup namely primary and secondary. Primary modes are rather sporadic and normally do not involve shape oscillations. Secondary atomization however leads to severe shape deformations and catastrophic intense breakup of the droplets. The dominance of these modes has been quantified based on the external heat flux, dynamic variation of surface tension, acoustic pressure, and droplet size. Addition of particles alters the regimes of the primary and secondary atomization and introduces bubble induced boiling and bursting. We analyze this new mode of atomization and estimate the time scale of bubble growth up to the point of bursting using energy balance to determine the criterion suitable for parent droplet rupture. All the three different modes of breakup have been well identified in a regime map determined in terms of Weber number and the heat utilization rate which is defined as the energy utilized for transient heating, vaporization, and boiling in droplets.

  12. Model and experiments of diesel fuel HCCI combustion with external mixture formation

    Energy Technology Data Exchange (ETDEWEB)

    Canova, M.; Vosz, A.; Dumbauld, D.; Garcin, R.; Midlam-Mohler, S.; Guezennec, Y.; Rizzoni, G. [Ohio State Univ. (United States)

    2005-07-01

    Homogeneous Charge Compression Ignition represents a promising concept for achieving high efficiencies and low emissions at part-load operations. In particular, HCCI combustion can be successfully applied to conventional Direct Injection Diesel engines with very low extra costs and no modification to the DI system by performing the mixture formation in the intake manifold with a novel fuel atomizer. The present paper describes the experimental and modeling activity oriented to the control of HCCI combustion on a conventional CIDI 4-cylinder engine fitted with this external fueling device. Paralleling preliminary results obtained last year on single-cylinder engine in collaboration with FKFS at the University of Stuttgart, Diesel-fuel HCCI combustion was achieved and characterized over a range of engine speeds, loads, EGR dilution and boost pressure. Stable HCCI combustion with negligible NO{sub x} formation (10 ppm) was achieved with no modification of a high compression ratio engine (c{sub r}=18). The in-cylinder pressure traces were analyzed by performing a detailed heat release analysis while accounting for the wall heat transfer, which is substantially higher during the combustion phase than in a conventional CIDI engine. This analysis led to the joint identification of 2 sub-models: a heat transfer model, and a heat release model. It was found that under the wide range of conditions experimentally measured, the heat release can be approximated by the superposition of 3 Wiebe functions. The sub-models developed were then implemented in a combustion model based on a first-law thermodynamic analysis of in-cylinder processes, in order to identify the influence of the main control parameters on HCCI auto-ignition and to control the combustion process in a HCCI Diesel engine with external mixture formation. The model predictions were then compared to the results of a parallel experimental activity made on a 4-cylinder CIDI Diesel engine equipped with the fuel

  13. Multiple recycling of fuel in prototype fast breeder reactor in a closed fuel cycle with pressurized heavy-water reactor external feed

    Indian Academy of Sciences (India)

    G Pandikumar; A John Arul; P Puthiyavinayagam; P Chellapandi

    2015-10-01

    A fast breeder reactor (FBR) closed fuel cycle involves recycling of the discharged fuel, after reprocessing and refabrication, in order to utilize the unburnt fuel and the bred fissile material. Our previous study in this regard for the prototype fast breeder reactor (PFBR) indicated the possibility of multiple recycling with self-sufficiency. It was found that the change in Pu composition becomes negligible (less than 1%) after a few cycles. The core-1 Pu increases by 3% from the beginning of cycle-0 to that of recycle-1, the Pu increase from the beginning of the 9th cycle to that of the 10th by only 0.3%. In this work, the possibility of multiple recycling of PFBR fuel with external plutonium feed from pressurized heavy-water reactor (PHWR) is examined. Modified in-core cooling and reprocessing periods are considered. The impact of multiple recycling on PFBR core physics parameters due to the changes in the fuel composition has been brought out. Instead of separate recovery considered for the core and axial blankets in the earlier studies, combined fuel recovery is considered in this study. With these modifications and also with PHWR Pu as external feed, the study on PFBR fuel recycling is repeated. It is observed that the core-1 initial Pu inventory increases by 3.5% from cycle-0 to that of recycle-1, the Pu increase from the beginning of the 9th cycle to that of the 10th is only 0.35%. A comparison of the studies done with different external plutonium options viz., PHWR and PFBR radial blanket has also been made.

  14. Fast, Massively Parallel Data Processors

    Science.gov (United States)

    Heaton, Robert A.; Blevins, Donald W.; Davis, ED

    1994-01-01

    Proposed fast, massively parallel data processor contains 8x16 array of processing elements with efficient interconnection scheme and options for flexible local control. Processing elements communicate with each other on "X" interconnection grid with external memory via high-capacity input/output bus. This approach to conditional operation nearly doubles speed of various arithmetic operations.

  15. Modeling the burnout of solid polydisperse fuel under the conditions of external heat transfer

    Science.gov (United States)

    Skorik, I. A.; Goldobin, Yu. M.; Tolmachev, E. M.; Gal'perin, L. G.

    2013-11-01

    A self-similar burnout mode of solid polydisperse fuel is considered taking into consideration heat transfer between fuel particles, gases, and combustion chamber walls. A polydisperse composition of fuel is taken into account by introducing particle distribution functions by radiuses obtained for the kinetic and diffusion combustion modes. Equations for calculating the temperatures of particles and gases are presented, which are written for particles average with respect to their distribution functions by radiuses taking into account the fuel burnout ratio. The proposed equations take into consideration the influence of fuel composition, air excess factor, and gas recirculation ratio. Calculated graphs depicting the variation of particle and gas temperatures, and the fuel burnout ratio are presented for an anthracite-fired boiler.

  16. Roles of Radiolytic and Externally Generated H2 in the Corrosion of Fractured Spent Nuclear Fuel.

    Science.gov (United States)

    Liu, Nazhen; Wu, Linda; Qin, Zack; Shoesmith, David W

    2016-11-15

    A 2-D model for the corrosion of spent nuclear fuel inside a failed nuclear waste container has been modified to determine the influence of various redox processes occurring within fractures in the fuel. The corrosion process is driven by reaction of the fuel with the dominant α radiolysis product, H2O2. A number of reactions are shown to moderate or suppress the corrosion rate, including H2O2 decomposition and a number of reactions involving dissolved H2 produced either by α radiolysis or by the corrosion of the steel container vessel. Both sources of H2 lead to the suppression of fuel corrosion, with their relative importance being determined by the radiation dose rate, the steel corrosion rate, and the dimensions of the fractures in the fuel. The combination of H2 from these two sources can effectively prevent corrosion when only micromolar quantities of H2 are present.

  17. Thermodynamic Analyses of Biomass Gasification Integrated Externally Fired, Post-Firing and Dual-Fuel Combined Cycles

    Directory of Open Access Journals (Sweden)

    Saeed Soltani

    2015-01-01

    Full Text Available In the present work, the results are reported of the energy and exergy analyses of three biomass-related processes for electricity generation: the biomass gasification integrated externally fired combined cycle, the biomass gasification integrated dual-fuel combined cycle, and the biomass gasification integrated post-firing combined cycle. The energy efficiency for the biomass gasification integrated post-firing combined cycle is 3% to 6% points higher than for the other cycles. Although the efficiency of the externally fired biomass combined cycle is the lowest, it has an advantage in that it only uses biomass. The energy and exergy efficiencies are maximized for the three configurations at particular values of compressor pressure ratios, and increase with gas turbine inlet temperature. As pressure ratio increases, the mass of air per mass of steam decreases for the biomass gasification integrated post-firing combined cycle, but the pressure ratio has little influence on the ratio of mass of air per mass of steam for the other cycles. The gas turbine exergy efficiency is the highest for the three configurations. The combustion chamber for the dual-fuel cycle exhibits the highest exergy efficiency and that for the post-firing cycle the lowest. Another benefit of the biomass gasification integrated externally fired combined cycle is that it exhibits the highest air preheater and heat recovery steam generator exergy efficiencies.

  18. Testing and operating a multiprocessor chip with processor redundancy

    Energy Technology Data Exchange (ETDEWEB)

    Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

    2014-10-21

    A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

  19. Estimation of the external cost of energy production based on fossil fuels in Finland and a comparison with estimates of external costs of wind power

    Energy Technology Data Exchange (ETDEWEB)

    Otterstroem, T. [Ekono Energy Ltd, Helsinki (Finland)

    1995-12-31

    Ekono Energy Ltd. and Soil and Water Ltd. participated in 1993 - 1994 in the SIHTI 2 research programme of the Ministry of Trade and Industry by carrying out the project `Estimation of the extremal cost of energy production in Finland`. The aim of the survey was to assess the external costs of Finnish energy production which are incurred by the environmental impacts of emissions during the life cycles of fossil fuels. To this end, the survey studied the environmental impacts of emissions on a local level (population centres), on a national level (Finland) and on a global level. The main target was to develop a method for calculating the economic value of these impacts. The method was applied to the emissions in 1990. During the survey, the main emphasis was put on developing and applying indirect valuation methods. An indirect method proceeds through dose-response functions. The dose-response function links a certain emission quantity, concentration or deposition to the extent or intensity of the effect. When quantitative data on hazards is available, it is possible to carry out monetary valuation by means of market prices or people`s otherwise expressed willingness to pay (WTP). Monetary valuation includes many uncertainty factors, of which the most significant with regard to this study are the transferability of dose-response functions and willingness-to-pay values from different kinds of conditions, additivity of damage values, uncertainty factors and problems related to discounting

  20. Electron beam guiding by external magnetic fields in imploded fuel plasma

    Science.gov (United States)

    Johzaki, T.; Sentoku, Y.; Nagatomo, H.; Sunahara, A.; Sakagami, H.; Fujioka, S.; Shiraga, H.; Endo, T.; FIREX project Group

    2016-05-01

    For enhancing the core heating efficiency in fast ignition laser fusion, we proposed the fast electron beam by externally-applied the kilo-tesla (kT) class longitudinal magnetic field. We evaluated the imploded core and the magnetic field profiles formed through the implosion dynamics by resistive MHD radiation hydro code. Using those profiles, the guiding effect was evaluated by fast electron transport simulations, which shows that in addition to the feasible field configuration (moderate mirror ratio), the kT-class magnetic field is required at the fast electron generation point. In this case, the significant enhancement in heating efficiency is expected.

  1. Experimental investigation of homogeneous charge compression ignition combustion of biodiesel fuel with external mixture formation in a CI engine.

    Science.gov (United States)

    Ganesh, D; Nagarajan, G; Ganesan, S

    2014-01-01

    In parallel to the interest in renewable fuels, there has also been increased interest in homogeneous charge compression ignition (HCCI) combustion. HCCI engines are being actively developed because they have the potential to be highly efficient and to produce low emissions. Even though HCCI has been researched extensively, few challenges still exist. These include controlling the combustion at higher loads and the formation of a homogeneous mixture. To obtain better homogeneity, in the present investigation external mixture formation method was adopted, in which the fuel vaporiser was used to achieve excellent HCCI combustion in a single cylinder air-cooled direct injection diesel engine. In continuation of our previous works, in the current study a vaporised jatropha methyl ester (JME) was mixed with air to form a homogeneous mixture and inducted into the cylinder during the intake stroke to analyze the combustion, emission and performance characteristics. To control the early ignition of JME vapor-air mixture, cooled (30 °C) Exhaust gas recirculation (EGR) technique was adopted. The experimental result shows 81% reduction in NOx and 72% reduction in smoke emission.

  2. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  3. The influence of external source intensity in accelerator/target/blanket system on conversion ratio and fuel cycle

    Science.gov (United States)

    Kochurov, Boris P.

    1995-09-01

    The analysis of neutron balance relation for a subcritical system with external source shows that a high ratio of neutron utilization (conversion ratio, breeding ratio) much exceeding similar values for nuclear reactors (both thermal or fast spectrum) is reachable in accelerator/target/blanket system with high external neutron source intensity. An accelerator/target/blanket systems with thermal power in blanket about 1850 Mwt and operating during 30 years have been investigated. Continual feed up by plutonium (fissile material) and Tc-99 (transmuted material) was assumed. Accelerator beam intensity differed 6.3 times (16 mA-Case 1, and 100 mA-Case 2). Conversion ratio (CR) was defined as the ratio of Tc-99 nuclei transmuted to the number of Pu nuclei consumed. The results for two cases are as follows: Case 1Case 2CR 0.77 1.66N(LWR) 8.6 19.1Power MWt(el) 512 225 where N(LWR)-number of LWRs(3000 MWt(th)) from which yearly discharge of Tc-99 is transmuted during 30 years. High value of conversion ratio considerably exceeding 1 (CR=1.66) was obtained in the system with high source intensity as compared with low source system (CR=0.77). Net output of electric power of high source intensity system is about twice lower due to consumption of electric power for accelerator feed up. The loss of energy for Tc-99 transmutation is estimated as 40 Mev(el)/nuclei. Yet high conversion ratio (or breeding ratio) achievable in electronuclear installations with high intensity of external source can effectively be used to close fuel cycle (including incineration of wastes) or to develop growing nuclear power production system.

  4. The UA1 trigger processor

    CERN Document Server

    Grayer, G H

    1981-01-01

    Experiment UA1 is a large multipurpose spectrometer at the CERN proton-antiproton collider. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead-time losses due to the bunched nature of the beam. To achieve this fast 8-bit charge to digital converters have been built followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, and to transverse energy in the other. Each processor forms four sums from a chosen combination of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in...

  5. Array processors in chemistry

    Energy Technology Data Exchange (ETDEWEB)

    Ostlund, N.S.

    1980-01-01

    The field of attached scientific processors (''array processors'') is surveyed, and an attempt is made to indicate their present and possible future use in computational chemistry. The current commercial products from Floating Point Systems, Inc., Datawest Corporation, and CSP, Inc. are discussed.

  6. Enhanced performance of an air-cathode microbial fuel cell with oxygen supply from an externally connected algal bioreactor.

    Science.gov (United States)

    Kakarla, Ramesh; Kim, Jung Rae; Jeon, Byong-Hun; Min, Booki

    2015-11-01

    An algae bioreactor (ABR) was externally connected to air-cathode microbial fuel cells (MFCs) to increase power generation by supplying a high amount of oxygen to cathode electrode. The MFC with oxygen fed from ABR produced maximum cell voltage and cathode potential at a fixed loading of 459 mV and 10 mV, respectively. During polarization analysis, the MFC displayed a maximum power density of 0.63 W/m(2) (at 2.06 A/m(2)) using 39.2% O2 from ABR, which was approximately 30% higher compared with use of atmospheric air (0.44 W/m(2), 20.8% O2,). The cyclic voltammogram analysis exhibited a higher reduction current of -137 mA with 46.5% O2 compared to atmospheric air (-115 mA). Oxygen supply by algae bioreactor to air-cathode MFC could also maintain better MFC performance in long term operation by minimizing cathode potential drop over time.

  7. Electricity generation and microbial community in microbial fuel cell using low-pH distillery wastewater at different external resistances.

    Science.gov (United States)

    Kim, Hongsuck; Kim, Byunggoon; Kim, Jiyeon; Lee, Taeho; Yu, Jaecheul

    2014-09-30

    Single chamber MFC (SMFC) consisted of two separator-electrode assemblies (SEA) using low-pH distillery wastewater (DW) was operated under continuous mode. The electricity generation and microbial community were analyzed according to the external resistance (Rext; 0.1, 0.5, 1, and 5 kΩ). The two SEAs exhibited different electricity generations, despite sharing the same anodic chamber. The SMFC showed the largest maximum power density (PDmax) of 3.7 W/m(3) (SEA 1) and 12.9 W/m(3) (SEA 2) at 5 kΩ. These results demonstrated that low-pH wastewater could be sufficiently used as fuels for electricity generation. Pyrosequencing analysis showed that microbial communities at the phylum level were significantly different according to the Rext. The communities of SEA 1 were slightly different from those of SEA 2. In both SEAs, Firmicutes (>45%) were the most dominant at 0.1 kΩ, while Firmicutes (>34%) and Caldiserica (>34%) were dominant at 5 kΩ. Caldiserica sp. might significantly contribute to electricity generation under low-pH and high-Rext.

  8. Benchmarking a DSP processor

    OpenAIRE

    Lennartsson, Per; Nordlander, Lars

    2002-01-01

    This Master thesis describes the benchmarking of a DSP processor. Benchmarking means measuring the performance in some way. In this report, we have focused on the number of instruction cycles needed to execute certain algorithms. The algorithms we have used in the benchmark are all very common in signal processing today. The results we have reached in this thesis have been compared to benchmarks for other processors, performed by Berkeley Design Technology, Inc. The algorithms were programm...

  9. Hardware multiplier processor

    Science.gov (United States)

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  10. Signal processor packaging design

    Science.gov (United States)

    McCarley, Paul L.; Phipps, Mickie A.

    1993-10-01

    The Signal Processor Packaging Design (SPPD) program was a technology development effort to demonstrate that a miniaturized, high throughput programmable processor could be fabricated to meet the stringent environment imposed by high speed kinetic energy guided interceptor and missile applications. This successful program culminated with the delivery of two very small processors, each about the size of a large pin grid array package. Rockwell International's Tactical Systems Division in Anaheim, California developed one of the processors, and the other was developed by Texas Instruments' (TI) Defense Systems and Electronics Group (DSEG) of Dallas, Texas. The SPPD program was sponsored by the Guided Interceptor Technology Branch of the Air Force Wright Laboratory's Armament Directorate (WL/MNSI) at Eglin AFB, Florida and funded by SDIO's Interceptor Technology Directorate (SDIO/TNC). These prototype processors were subjected to rigorous tests of their image processing capabilities, and both successfully demonstrated the ability to process 128 X 128 infrared images at a frame rate of over 100 Hz.

  11. The Milstar Advanced Processor

    Science.gov (United States)

    Tjia, Khiem-Hian; Heely, Stephen D.; Morphet, John P.; Wirick, Kevin S.

    The Milstar Advanced Processor (MAP) is a 'drop-in' replacement for its predecessor which preserves existing interfaces with other Milstar satellite processors and minimizes the impact of such upgrading to already-developed application software. In addition to flight software development, and hardware development that involves the application of VHSIC technology to the electrical design, the MAP project is developing two sophisticated and similar test environments. High density RAM and ROM are employed by the MAP memory array. Attention is given to the fine-pitch VHSIC design techniques and lead designs used, as well as the tole of TQM and concurrent engineering in the development of the MAP manufacturing process.

  12. Real time simulator with Ti floating point digital signal processor

    Energy Technology Data Exchange (ETDEWEB)

    Razazian, K.; Bobis, J.P.; Dieckman, S.L.; Raptis, A.C.

    1994-08-01

    This paper describes the design and operation of a Real Time Simulator using Texas Instruments TMS320C30 digital signal processor. This system operates with two banks of memory which provide the input data to digital signal processor chip. This feature enables the TMS320C30 to be utilized in variety of applications for which external connections to acquire input data is not needed. In addition, some practical applications of this Real Time Simulator are discussed.

  13. Interactive Digital Signal Processor

    Science.gov (United States)

    Mish, W. H.

    1985-01-01

    Interactive Digital Signal Processor, IDSP, consists of set of time series analysis "operators" based on various algorithms commonly used for digital signal analysis. Processing of digital signal time series to extract information usually achieved by applications of number of fairly standard operations. IDSP excellent teaching tool for demonstrating application for time series operators to artificially generated signals.

  14. Beyond processor sharing

    NARCIS (Netherlands)

    Aalto, S.; Ayesta, U.; Borst, S.C.; Misra, V.; Núñez Queija, R.

    2007-01-01

    While the (Egalitarian) Processor-Sharing (PS) discipline offers crucial insights in the performance of fair resource allocation mechanisms, it is inherently limited in analyzing and designing differentiated scheduling algorithms such as Weighted Fair Queueing and Weighted Round-Robin. The Discrimin

  15. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  16. EARLY EXPERIENCE WITH A HYBRID PROCESSOR: K-MEANS CLUSTERING

    Energy Technology Data Exchange (ETDEWEB)

    M. GOKHALE; ET AL

    2001-02-01

    We discuss hardware/software coprocessing on a hybrid processor for a compute- and data-intensive hyper-spectral imaging algorithm, K-Means Clustering. The experiments are performed on the Altera Excalibur board using the soft IP core 32-bit NIOS RISC processor. In our experiments, we compare performance of the sequential algorithm with two different accelerated versions. We consider granularity and synchronization issues when mapping an algorithm to a hybrid processor. Our results show that on the Excalibur NIOS, a 15% speedup can be achieved over the sequential algorithm on images with 8 spectral bands where the pixels are divided into 8 categories. Speedup is limited by the communication cost of transferring data from external memory through the NIOS processor to the customized circuits. Our results indicate that future hybrid processors must either (1) have a clock rate 10X the speed of the configurable logic circuits or (2) include dual port memories that both the processor and configurable logic can access. If either of these conditions is met, the hybrid processor will show a factor of 10 speedup over the sequential algorithm. Such systems will combine the convenience of conventional processors with the speed of configurable logic.

  17. A Domain Specific DSP Processor

    OpenAIRE

    Tell, Eric

    2001-01-01

    This thesis describes the design of a domain specific DSP processor. The thesis is divided into two parts. The first part gives some theoretical background, describes the different steps of the design process (both for DSP processors in general and for this project) and motivates the design decisions made for this processor. The second part is a nearly complete design specification. The intended use of the processor is as a platform for hardware acceleration units. Support for this has howe...

  18. Processor register error correction management

    Science.gov (United States)

    Bose, Pradip; Cher, Chen-Yong; Gupta, Meeta S.

    2016-12-27

    Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

  19. Dual-core Itanium Processor

    CERN Multimedia

    2006-01-01

    Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

  20. New Generation Processor Architecture Research

    Institute of Scientific and Technical Information of China (English)

    Chen Hongsong(陈红松); Hu Mingzeng; Ji Zhenzhou

    2003-01-01

    With the rapid development of microelectronics and hardware,the use of ever faster micro-processors and new architecture must be continued to meet tomorrow′s computing needs. New processor microarchitectures are needed to push performance further and to use higher transistor counts effectively.At the same time,aiming at different usages,the processor has been optimized in different aspects,such as high performace,low power consumption,small chip area and high security. SOC (System on chip)and SCMP (Single Chip Multi Processor) constitute the main processor system architecture.

  1. ExternE National Implementation Finland

    Energy Technology Data Exchange (ETDEWEB)

    Pingoud, K.; Maelkki, H.; Wihersaari, M.; Pirilae, P. [VTT Energy, Espoo (Finland); Hongisto, M. [Imatran Voima Oy, Vantaa (Finland); Siitonen, S. [Ekono Energy Ltd, Espoo (Finland); Johansson, M. [Finnish Environment Institute, Helsinki (Finland)

    1999-07-01

    ExternE National Implementation is a continuation of the ExternE Project, funded in part by the European Commission's Joule III Programme. This study is the result of the ExternE National Implementation Project for Finland. Three fuel cycles were selected for the Finnish study: coal, peat and wood-derived biomass, which together are responsible for about 40% of total electricity generation in Finland and about 75% of the non-nuclear fuel based generation. The estimated external costs or damages were dominated by the global warming (GW) impacts in the coal and peat fuel cycles, but knowledge of the true GW impacts is still uncertain. From among other impacts that were valued in monetary terms the human health damages due to airborne emissions dominated in all the three fuel cycles. Monetary valuation for ecosystem impacts is not possible using the ExternE methodology at present. The Meri-Pori power station representing the coal fuel cycle is one of the world's cleanest and most efficient coal-fired power plants with a condensing turbine. The coal is imported mainly from Poland. The estimated health damages were about 4 mECU/kWh, crop damages an order of magnitude lower and damages caused to building materials two orders of magnitude lower. The power stations of the peat and biomass fuel cycles are of CHP type, generating electricity and heat for the district heating systems of two cities. Their fuels are of domestic origin. The estimated health damages allocated to electricity generation were about 5 and 6 mECU/kWh, respectively. The estimates were case-specific and thus an generalisation of the results to the whole electricity generation in Finland is unrealistic. Despite the uncertainties and limitations of the methodology, it is a promising tool in the comparison of similar kinds of fuel cycles, new power plants and pollution abatement technologies and different plant locations with each other. (orig.)

  2. Stereoscopic Optical Signal Processor

    Science.gov (United States)

    Graig, Glenn D.

    1988-01-01

    Optical signal processor produces two-dimensional cross correlation of images from steroscopic video camera in real time. Cross correlation used to identify object, determines distance, or measures movement. Left and right cameras modulate beams from light source for correlation in video detector. Switch in position 1 produces information about range of object viewed by cameras. Position 2 gives information about movement. Position 3 helps to identify object.

  3. Tiled Multicore Processors

    Science.gov (United States)

    Taylor, Michael B.; Lee, Walter; Miller, Jason E.; Wentzlaff, David; Bratt, Ian; Greenwald, Ben; Hoffmann, Henry; Johnson, Paul R.; Kim, Jason S.; Psota, James; Saraf, Arvind; Shnidman, Nathan; Strumpen, Volker; Frank, Matthew I.; Amarasinghe, Saman; Agarwal, Anant

    For the last few decades Moore’s Law has continually provided exponential growth in the number of transistors on a single chip. This chapter describes a class of architectures, called tiled multicore architectures, that are designed to exploit massive quantities of on-chip resources in an efficient, scalable manner. Tiled multicore architectures combine each processor core with a switch to create a modular element called a tile. Tiles are replicated on a chip as needed to create multicores with any number of tiles. The Raw processor, a pioneering example of a tiled multicore processor, is examined in detail to explain the philosophy, design, and strengths of such architectures. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance. Central to achieving this goal is Raw’s ability to exploit all forms of parallelism, including ILP, DLP, TLP, and Stream parallelism. Raw approaches this challenge by implementing plenty of on-chip resources - including logic, wires, and pins - in a tiled arrangement, and exposing them through a new ISA, so that the software can take advantage of these resources for parallel applications. Compared to a traditional superscalar processor, Raw performs within a factor of 2x for sequential applications with a very low degree of ILP, about 2x-9x better for higher levels of ILP, and 10x-100x better when highly parallel applications are coded in a stream language or optimized by hand.

  4. Fuel processor temperature monitoring and control

    Science.gov (United States)

    Keskula, Donald H.; Doan, Tien M.; Clingerman, Bruce J.

    2002-01-01

    In one embodiment, the method of the invention monitors one or more of the following conditions: a relatively low temperature value of the gas stream; a relatively high temperature value of the gas stream; and a rate-of-change of monitored temperature. In a preferred embodiment, the rate of temperature change is monitored to prevent the occurrence of an unacceptably high or low temperature condition. Here, at least two temperatures of the recirculating gas stream are monitored over a period of time. The rate-of-change of temperature versus time is determined. Then the monitored rate-of-change of temperature is compared to a preselected rate-of-change of value. The monitoring of rate-of-change of temperature provides proactive means for preventing occurrence of an unacceptably high temperature in the catalytic reactor.

  5. Distributed processor allocation for launching applications in a massively connected processors complex

    Science.gov (United States)

    Pedretti, Kevin

    2008-11-18

    A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

  6. A Systolic Array RLS Processor

    OpenAIRE

    Asai, T.; Matsumoto, T.

    2000-01-01

    This paper presents the outline of the systolic array recursive least-squares (RLS) processor prototyped primarily with the aim of broadband mobile communication applications. To execute the RLS algorithm effectively, this processor uses an orthogonal triangularization technique known in matrix algebra as QR decomposition for parallel pipelined processing. The processor board comprises 19 application-specific integrated circuit chips, each with approximately one million gates. Thirty-two bit ...

  7. AMD's 64-bit Opteron processor

    CERN Document Server

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  8. Emerging Trends in Embedded Processors

    Directory of Open Access Journals (Sweden)

    Gurvinder Singh

    2014-05-01

    Full Text Available An Embedded Processors is simply a µProcessors that has been “Embedded” into a device. Embedded systems are important part of human life. For illustration, one cannot visualize life without mobile phones for personal communication. Embedded systems are used in many places like healthcare, automotive, daily life, and in different offices and industries.Embedded Processors develop new research area in the field of hardware designing.

  9. Spaceborne Processor Array

    Science.gov (United States)

    Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

    2008-01-01

    A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

  10. Solid cancer mortality associated with chronic external radiation exposure at the French atomic energy commission and nuclear fuel company.

    Science.gov (United States)

    Metz-Flamant, C; Samson, E; Caër-Lorho, S; Acker, A; Laurier, D

    2011-07-01

    Studies of nuclear workers make it possible to directly quantify the risks associated with ionizing radiation exposure at low doses and low dose rates. Studies of the CEA (Commissariat à l'Energie Atomique) and AREVA Nuclear Cycle (AREVA NC) cohort, currently the most informative such group in France, describe the long-term risk to nuclear workers associated with external exposure. Our aim is to assess the risk of mortality from solid cancers among CEA and AREVA NC nuclear workers and its association with external radiation exposure. Standardized mortality ratios (SMRs) were calculated and internal Poisson regressions were conducted, controlling for the main confounding factors [sex, attained age, calendar period, company and socioeconomic status (SES)]. During the period 1968-2004, there were 2,035 solid cancers among the 36,769 CEA-AREVA NC workers. Cumulative external radiation exposure was assessed for the period 1950-2004, and the mean cumulative dose was 12.1 mSv. Mortality rates for all causes and all solid cancers were both significantly lower in this cohort than in the general population. A significant excess of deaths from pleural cancer, not associated with cumulative external dose, was observed, probably due to past asbestos exposure. We observed a significant excess of melanoma, also unassociated with dose. Although cumulative external dose was not associated with mortality from all solid cancers, the central estimated excess relative risk (ERR) per Sv of 0.46 for solid cancer mortality was higher than the 0.26 calculated for male Hiroshima and Nagasaki A-bomb survivors 50 years or older and exposed at the age of 30 years or older. The modification of our results after stratification for SES demonstrates the importance of this characteristic in occupational studies, because it makes it possible to take class-based lifestyle differences into account, at least partly. These results show the great potential of a further joint international study of

  11. External Attachment of Titanium Sheathed Thermocouples to Zirconium Nuclear Fuel Rods For The Loss-Of-Fluid-Test (LOFT) Reactor

    Science.gov (United States)

    Welty, Richard K.

    1980-10-01

    The Exxon Nuclear Company, Inc. acting as a Subcontractor to EG&G Idaho Inc.3 Idaho National Engineering Laboratory, Idaho Falls, Idaho, has developed a welding process to attach titanium sheathed thermocouples to the outside of the zircaloy clad fuel rods. The fuel rods and thermocouples are used to test simulated loss-of-coolant-accident (LOCA) conditions in a pressurized water reactor (LOFT Reactor, Idaho National Laboratory). The design goals were to (1) reliably attach thermocouples to the zircaloy fuel rods, (2) achieve or exceed a life expectancy of 6,000 hours of reactor operation in a borated water environment of 316°C at 2260 psi, (3) provide and sustain repeatable physical and metallurgical properties in the instrumented rods subjected to transient temperatures up to 1538°C with blowdown, shock, loading, and fast quench. A laser beam was selected as the optimum welding process because of the extremely high energy input per unit volume that can be achieved allowing local fusion of a small area irrespective of the difference in material thickness to be joined. A commercial pulsed laser and energy control system was installed along with specialized welding fixtures. Laser room facility requirements and tolerances were established. Performance qualifications and detailed welding procedures were also developed. Product performance tests were conducted to assure that engineering design requirements could be met on a production basis. Irradiation tests showed no degradation of thermocouples or weld structure. Fast thermal cycle and heater rod blowdown reflood tests were made to subject the weldments to high temperatures, high pressure steam, and fast water quench cycles. From the behavior of these tests, it was concluded that the attachment welds would survive a series of reactor safety tests.

  12. Embedded Processor Oriented Compiler Infrastructure

    Directory of Open Access Journals (Sweden)

    DJUKIC, M.

    2014-08-01

    Full Text Available In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture.

  13. Determination of Optimized Parameters for the Flexible Operation of a Biomass-Fueled, Microscale Externally Fired Gas Turbine (EFGT

    Directory of Open Access Journals (Sweden)

    Mathhar Bdour

    2016-10-01

    Full Text Available Biomass as a source of renewable energy is a promising solution for current problems in energy supply. Olive waste is considered as an interesting option, especially for Mediterranean countries. Within this paper, a microscale externally fired gas turbine (EFGT technology is presented as a decentralized power plant, within the range of 15 kWth, based on olive residues. It was modeled by Aspen Plus 8.6 software to provide a sufficient technical study for such a plant. Optimized parameters for pressure ratio and turbine air-mass flow have been mapped for several loads to provide information for process control. For all cases, mechanical output, efficiency curves, and back-work ratio have been calculated. Using this information, typical plant sizes and an example of power production are discussed. Additionally, achievable energy production from olive waste is estimated on the basis of this data. The results of this study show that such a plant has an electrical efficiency of 5%–17%. This variation is due to the examination being performed under several combustion temperatures, actual load, heat exchanger temperatures, and heat transfer efficiency. A cost estimation of the discussed system showed an estimated capital cost of 33,800 to 65,300 € for a 15 kWth system.

  14. Fast Forwarding with Network Processors

    OpenAIRE

    Lefèvre, Laurent; Lemoine, E.; Pham, C; Tourancheau, B.

    2003-01-01

    Forwarding is a mechanism found in many network operations. Although a regular workstation is able to perform forwarding operations it still suffers from poor performances when compared to dedicated hardware machines. In this paper we study the possibility of using Network Processors (NPs) to improve the capability of regular workstations to forward data. We present a simple model and an experimental study demonstrating that even though NPs are less powerful than Host Processors (HPs) they ca...

  15. Parallel External Memory Graph Algorithms

    DEFF Research Database (Denmark)

    Arge, Lars Allan; Goodrich, Michael T.; Sitchinava, Nodari

    2010-01-01

    In this paper, we study parallel I/O efficient graph algorithms in the Parallel External Memory (PEM) model, one o f the private-cache chip multiprocessor (CMP) models. We study the fundamental problem of list ranking which leads to efficient solutions to problems on trees, such as computing lowest...... an optimal speedup of ¿(P) in parallel I/O complexity and parallel computation time, compared to the single-processor external memory counterparts....

  16. Experimental investigation on a polymer electrolyte membrane fuel cell (PEMFC) parallel flow field design with external two-valve regulation on cathode channels

    Science.gov (United States)

    Tong, Shijie; Bachman, John C.; Santamaria, Anthony; Park, Jae Wan

    2013-11-01

    Parallel/interdigitated/serpentine flow field PEM fuel cells have similar performance under low overvoltage operation. At higher overvoltage, interdigitated/serpentine flow field performance may exceed parallel flow field designs due to better water removal and more uniform reactant distribution by convective reactant flow in the GDL under land area, i.e. cross flow. However, serpentine flow field design suffers from high pumping losses and the risk of local flooding at channel U-bends. Additionally, interdigitated flow field designs may have higher local flooding risk in the inlet channels and relatively large pumping requirement at low current densities. In this study, a novel parallel flow field design with external two-valve regulation on the cathode was presented. Two valves introduced continuous pressure differences to two separate manifolds in the cathode that induce cross flow across the land areas. Moreover, both valves remained partially open to maintain a good water removal from flow channels. Comparative test results showed the proposed design surpasses performance of both parallel and interdigitated flow field design at operation current density of 0.7 A cm-2 or higher. The performance enhancement is 10.9% at peak power density point (0.387 W cm-2 @ 0.99 A cm-2) compared to parallel flow field taking into account pumping losses.

  17. A micro-structured 5kW complete fuel processor for iso-octane as hydrogen supply system for mobile auxiliary power units Part I. Development of autothermal reforming catalyst and reactor

    OpenAIRE

    Kolb, Gunther; Baier, Tobias; Schürer, Jochen; Tiemann, David; Ziogas, Athanassios; Ehwald, Hermann; Alphonse, Pierre

    2008-01-01

    A micro-structured autothermal reformer was developed for a fuel processing/fuel cell system running on iso-octane and designed for an electrical power output of 5kWel. The target application was an automotive auxiliary power unit (APU). The work covered both catalyst and reactor development. In fixed bed screening, nickel and rhodium were identified as the best candidates for autothermal reforming of gasoline. Under higher feed flow rates applied in microchannel testing, a catalyst formul...

  18. Building custom processors with Handel-C

    CERN Document Server

    Lokier, J

    1999-01-01

    Triggering and data acquisition for the ATLAS LHC experiment requires state of the art computer hardware. Amongst other things, specialised processors may be required. To build these economically we are looking at reconfigurable computing, and a high-level hardware description language: Handel-C. We had previously implemented a specialised network hardware application in AHDL-a hardware description at the level of gates, flip-flops and state machines. As a feasibility study, we have rewritten the application in Handel-C -a language similar to C, except that it can be translated into hardware. There were problems to solve: high data throughput with complex pipelines; timing constraints; I/O interfaces to external devices; difficulties with the Altera devices. We gained valuable experience, wrote useful support tools, and discovered clean new ways to make the most of the language in the high-speed domain. (0 refs).

  19. Libera Electron Beam Position Processor

    CERN Document Server

    Ursic, Rok

    2005-01-01

    Libera is a product family delivering unprecedented possibilities for either building powerful single station solutions or architecting complex feedback systems in the field of accelerator instrumentation and controls. This paper presents functionality and field performance of its first member, the electron beam position processor. It offers superior performance with multiple measurement channels delivering simultaneously position measurements in digital format with MHz kHz and Hz bandwidths. This all-in-one product, facilitating pulsed and CW measurements, is much more than simply a high performance beam position measuring device delivering micrometer level reproducibility with sub-micrometer resolution. Rich connectivity options and innate processing power make it a powerful feedback building block. By interconnecting multiple Libera electron beam position processors one can build a low-latency high throughput orbit feedback system without adding additional hardware. Libera electron beam position processor ...

  20. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  1. Making CSB + -Trees Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  2. Cluster Algorithm Special Purpose Processor

    Science.gov (United States)

    Talapov, A. L.; Shchur, L. N.; Andreichenko, V. B.; Dotsenko, Vl. S.

    We describe a Special Purpose Processor, realizing the Wolff algorithm in hardware, which is fast enough to study the critical behaviour of 2D Ising-like systems containing more than one million spins. The processor has been checked to produce correct results for a pure Ising model and for Ising model with random bonds. Its data also agree with the Nishimori exact results for spin glass. Only minor changes of the SPP design are necessary to increase the dimensionality and to take into account more complex systems such as Potts models.

  3. Cluster algorithm special purpose processor

    Energy Technology Data Exchange (ETDEWEB)

    Talapov, A.L.; Shchur, L.N.; Andreichenko, V.B.; Dotsenko, V.S. (Landau Inst. for Theoretical Physics, GSP-1 117940 Moscow V-334 (USSR))

    1992-08-10

    In this paper, the authors describe a Special Purpose Processor, realizing the Wolff algorithm in hardware, which is fast enough to study the critical behaviour of 2D Ising-like systems containing more than one million spins. The processor has been checked to produce correct results for a pure Ising model and for Ising model with random bonds. Its data also agree with the Nishimori exact results for spin glass. Only minor changes of the SPP design are necessary to increase the dimensionality and to take into account more complex systems such as Potts models.

  4. Reconfigurable Communication Processor:A New Approach for Network Processor

    Institute of Scientific and Technical Information of China (English)

    孙华; 陈青山; 张文渊

    2003-01-01

    As the traditional RISC +ASIC/ASSP approach for network processor design can not meet the today'srequirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost theperformance to ASIC level while reserve the programmability of the traditional RISC based system. This papercovers both the hardware architecture and the software development environment architecture.

  5. An external peer review of the U.S. Department of Energy`s assessment of ``damages and benefits of the fuel cycles: Estimation methods, impacts, and values``. Final report

    Energy Technology Data Exchange (ETDEWEB)

    1993-08-09

    The need for better assessments of the ``external`` benefits and costs of environmental effects of various fuel cycles was identified during the development of the National Energy Strategy. The growing importance of this issue was emphasized by US Department of Energy (DOE) management because over half of the states were already pursuing some form of social costing in electricity regulation and a well-established technical basis for such decisions was lacking. This issue was identified as a major area of controversy--both scientifically and politically--in developing energy policies at the state and national level. In 1989, the DOE`s Office of Domestic and International Energy Policy commissioned a study of the external environmental damages and benefits of the major fuel cycles involved in electric power generation. Over the next 3-year period, Oak Ridge National Laboratory and Resources for the Future conducted the study and produced a series of documents (fuel cycle documents) evaluating the costs of environmental damages of the coal, oil, natural gas, biomass, hydroelectric, and nuclear fuel cycles, as well as the Background Document on methodological issues. These documents described work that took almost 3 years and $2.5 million to complete and whose implications could be far reaching. In 1992, the Secretary of Energy sought advice on the overall concepts underlying the studies and the means employed to estimate environmental externalities. He asked the Secretary of Energy`s Advisory Board to undertake a peer review of the fuel cycle studies and encouraged the Board to turn to outside expertise, as needed.

  6. ASSP Advanced Sensor Signal Processor.

    Science.gov (United States)

    1984-06-01

    transfer data sad cimeds . When a Processor receives the required data (Image) md/or oamand, that data will be operated on B-3 I I I autonomouly. The...BAN is provided by two separately controled DMA address generator chips (Am29o40). Each of these DMA chips create an 8 bit address. One DMA chip gene

  7. Cassava processors' awareness of occupational and environmental ...

    African Journals Online (AJOL)

    Cassava processors' awareness of occupational and environmental hazards ... Majority of the respondents also complained of lack of water (78.4%), lack of ... so as to reduce the problems faced by cassava processors during processing.

  8. SOLID STATE ENERGY CONVERSION ALLIANCE (SECA) SOLID OXIDE FUEL CELL PROGRAM

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen Minh; Jim Powers

    2003-10-01

    This report summarizes the work performed for April 2003--September 2003 reporting period under Cooperative Agreement DE-FC26-01NT41245 for the U.S. Department of Energy, National Energy Technology Laboratory (DOE/NETL) entitled ''Solid State Energy Conversion Alliance (SECA) Solid oxide Fuel Cell Program''. During this reporting period, the conceptual system design activity was completed. The system design, including strategies for startup, normal operation and shutdown, was defined. Sealant and stack materials for the solid oxide fuel cell (SOFC) stack were identified which are capable of meeting the thermal cycling and degradation requirements. A cell module was tested which achieved a stable performance of 0.238 W/cm{sup 2} at 95% fuel utilization. The external fuel processor design was completed and fabrication begun. Several other advances were made on various aspects of the SOFC system, which are detailed in this report.

  9. Post-processor for simulations of the ORIGEN program and calculation of the composition of the activity of a burnt fuel core by a BWR type reactor; Post-procesador para simulaciones del programa ORIGEN y calculo de la composicion de la actividad de un nucleo de combustible quemado por un reactor tipo BWR

    Energy Technology Data Exchange (ETDEWEB)

    Sandoval V, S. [IIE, Av. Reforma 113, Col. Palmira, 62490 Cuernavaca, Morelos (Mexico)]. e-mail: sandoval@iie.org.mx

    2006-07-01

    The composition calculation and the activity of nuclear materials subject to processes of burnt, irradiation and decay periods are of utility for diverse activities inside the nuclear industry, as they are it: the processes design and operations that manage radioactive material, the calculation of the inventory and activity of a core of burnt nuclear fuel, for studies of type Probabilistic Safety Analysis (APS), as well as for regulation processes and licensing of nuclear facilities. ORIGEN is a program for computer that calculates the composition and the activity of nuclear materials subject to periods of burnt, irradiation and decay. ORIGEN generates a great quantity of information whose processing and analysis are laborious, and it requires thoroughness to avoid errors. The automation of the extraction, conditioning and classification of that information is of great utility for the analyst. By means of the use of the post-processor presented in this work it is facilitated, it speeds up and wide the capacity of analysis of results, since diverse consultations with several classification options and filtrate of results can be made. As illustration of the utility of the post-processor, and as an analysis of interest for itself, it is also presented in this work the composition of the activity of a burned core in a BWR type reactor according to the following classification criteria: by type of radioisotope (fission products, activation products and actinides), by specie type (gassy, volatile, semi-volatile and not volatile), by element and by chemical group. The results show that the total activity of the studied core is dominated by the fission products and for the actinides, in proportion four to one, and that the gassy and volatile species conform a fifth part of the total activity of the core. (Author)

  10. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...... on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate...

  11. Emissions variability processor (EMVAP): design, evaluation, and application.

    Science.gov (United States)

    Paine, Robert; Szembek, Carlos; Heinold, David; Knipping, Eladio; Kumar, Naresh

    2014-12-01

    Emissions of pollutants such as SO2 and NOx from external combustion sources can vary widely depending on fuel sulfur content, load, and transient conditions such as startup, shutdown, and maintenance/malfunction. While monitoring will automatically reflect variability from both emissions and meteorological influences, dispersion modeling has been typically conducted with a single constant peak emission rate. To respond to the need to account for emissions variability in addressing probabilistic 1-hr ambient air quality standards for SO2 and NO2, we have developed a statistical technique, the Emissions Variability Processor (EMVAP), which can account for emissions variability in dispersion modeling through Monte Carlo sampling from a specified frequency distribution of emission rates. Based upon initial AERMOD modeling of from 1 to 5 years of actual meteorological conditions, EMVAP is used as a postprocessor to AERMOD to simulate hundreds or even thousands of years of concentration predictions. This procedure uses emissions varied hourly with a Monte Carlo sampling process that is based upon the user-specified emissions distribution, from which a probabilistic estimate can be obtained of the controlling concentration. EMVAP can also accommodate an advanced Tier 2 NO2 modeling technique that uses a varying ambient ratio method approach to determine the fraction of total oxides of nitrogen that are in the form of nitrogen dioxide. For the case of the 1-hr National Ambient Air Quality Standards (NAAQS, established for SO2 and NO2), a "critical value" can be defined as the highest hourly emission rate that would be simulated to satisfy the standard using air dispersion models assuming constant emissions throughout the simulation. The critical value can be used as the starting point for a procedure like EMVAP that evaluates the impact of emissions variability and uses this information to determine an appropriate value to use for a longer-term (e.g., 30-day) average

  12. 40 CFR 791.45 - Processors.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 31 2010-07-01 2010-07-01 true Processors. 791.45 Section 791.45 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) TOXIC SUBSTANCES CONTROL ACT (CONTINUED) DATA REIMBURSEMENT Basis for Proposed Order § 791.45 Processors. (a) Generally, processors will be...

  13. External costs related to power production technologies. ExternE national implementation for Denmark

    Energy Technology Data Exchange (ETDEWEB)

    Schleisner, L.; Sieverts Nielsen, P.

    1997-12-01

    The objective of the ExternE National Implementation project has been to establish a comprehensive and comparable set of data on externalities of power generation for all EU member states and Norway. The tasks include the application of the ExternE methodology to the most important fuel cycles for each country as well as to update the already existing results; to aggregate these site- and technology-specific results to more general figures. The current report covers the results of the national implementation for Denmark. Three different fuel cycles have been chosen as case studies. These are fuel cycles for an offshore wind farm and a wind farm on land, a decentralised CHP plant based on natural gas and a decentralised CHP plant based on biogas. The report covers all the details of the application of the methodology to these fuel cycles aggregation to a national level. (au) EU-JOULE 3. 59 tabs., 25 ills., 61 refs.

  14. A CNN-Specific Integrated Processor

    Directory of Open Access Journals (Sweden)

    Suleyman Malki

    2009-01-01

    Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  15. A CNN-Specific Integrated Processor

    Science.gov (United States)

    Malki, Suleyman; Spaanenburg, Lambert

    2009-12-01

    Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  16. Communications systems and methods for subsea processors

    Science.gov (United States)

    Gutierrez, Jose; Pereira, Luis

    2016-04-26

    A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

  17. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  18. An Experimental Digital Image Processor

    Science.gov (United States)

    Cok, Ronald S.

    1986-12-01

    A prototype digital image processor for enhancing photographic images has been built in the Research Laboratories at Kodak. This image processor implements a particular version of each of the following algorithms: photographic grain and noise removal, edge sharpening, multidimensional image-segmentation, image-tone reproduction adjustment, and image-color saturation adjustment. All processing, except for segmentation and analysis, is performed by massively parallel and pipelined special-purpose hardware. This hardware runs at 10 MHz and can be adjusted to handle any size digital image. The segmentation circuits run at 30 MHz. The segmentation data are used by three single-board computers for calculating the tonescale adjustment curves. The system, as a whole, has the capability of completely processing 10 million three-color pixels per second. The grain removal and edge enhancement algorithms represent the largest part of the pipelined hardware, operating at over 8 billion integer operations per second. The edge enhancement is performed by unsharp masking, and the grain removal is done using a collapsed Walsh-hadamard transform filtering technique (U.S. Patent No. 4549212). These two algo-rithms can be realized using four basic processing elements, some of which have been imple-mented as VLSI semicustom integrated circuits. These circuits implement the algorithms with a high degree of efficiency, modularity, and testability. The digital processor is controlled by a Digital Equipment Corporation (DEC) PDP 11 minicomputer and can be interfaced to electronic printing and/or electronic scanning de-vices. The processor has been used to process over a thousand diagnostic images.

  19. Taxonomy of Data Prefetching for Multicore Processors

    Institute of Scientific and Technical Information of China (English)

    Surendra Byna; Yong Chen; Xian-He Sun

    2009-01-01

    Data prefetching is an effective data access latency hiding technique to mask the CPU stall caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been developed for single-core processors. Recent developments in processor technology have brought multicore processors into mainstream.While some of the single-core prefetching techniques are directly applicable to multicore processors, numerous novel strategies have been proposed in the past few years to take advantage of multiple cores. This paper aims to provide a comprehensive review of the state-of-the-art prefetching techniques, and proposes a taxonomy that classifies various design concerns in developing a prefetching strategy, especially for multicore processors. We compare various existing methods through analysis as well.

  20. 49 CFR 238.423 - Fuel tanks.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Fuel tanks. 238.423 Section 238.423 Transportation....423 Fuel tanks. (a) External fuel tanks. Each type of external fuel tank must be approved by FRA's Associate Administrator for Safety upon a showing that the fuel tank provides a level of safety at...

  1. Deep geological disposal system development; mechanical structural stability analysis of spent nuclear fuel disposal canister under the internal/external pressure variation

    Energy Technology Data Exchange (ETDEWEB)

    Kwen, Y. J.; Kang, S. W.; Ha, Z. Y. [Hongik University, Seoul (Korea)

    2001-04-01

    This work constitutes a summary of the research and development work made for the design and dimensioning of the canister for nuclear fuel disposal. Since the spent nuclear fuel disposal emits high temperature heats and much radiation, its careful treatment is required. For that, a long term(usually 10,000 years) safe repository for spent fuel disposal should be securred. Usually this repository is expected to locate at a depth of 500m underground. The canister construction type introduced here is a solid structure with a cast iron insert and a corrosion resistant overpack, which is designed for spent nuclear fuel disposal in a deep repository in the crystalline bedrock, which entails an evenly distributed load of hydrostatic pressure from undergroundwater and high pressure from swelling of bentonite buffer. Hence, the canister must be designed to withstand these high pressure loads. Many design variables may affect the structural strength of the canister. In this study, among those variables array type of inner baskets and thicknesses of outer shell and lid and bottom are tried to be determined through the mechanical linear structural analysis, thicknesses of outer shell is determined through the nonlinear structural analysis, and the bentonite buffer analysis for the rock movement is conducted through the of nonlinear structural analysis Also the thermal stress effect is computed for the cast iron insert. The canister types studied here are one for PWR fuel and another for CANDU fuel. 23 refs., 60 figs., 23 tabs. (Author)

  2. Functional Verification of Enhanced RISC Processor

    OpenAIRE

    SHANKER NILANGI; SOWMYA L

    2013-01-01

    This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

  3. Digital Signal Processor For GPS Receivers

    Science.gov (United States)

    Thomas, J. B.; Meehan, T. K.; Srinivasan, J. M.

    1989-01-01

    Three innovative components combined to produce all-digital signal processor with superior characteristics: outstanding accuracy, high-dynamics tracking, versatile integration times, lower loss-of-lock signal strengths, and infrequent cycle slips. Three components are digital chip advancer, digital carrier downconverter and code correlator, and digital tracking processor. All-digital signal processor intended for use in receivers of Global Positioning System (GPS) for geodesy, geodynamics, high-dynamics tracking, and ionospheric calibration.

  4. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...... through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration....

  5. Zeolites Remove Sulfur From Fuels

    Science.gov (United States)

    Voecks, Gerald E.; Sharma, Pramod K.

    1991-01-01

    Zeolites remove substantial amounts of sulfur compounds from diesel fuel under relatively mild conditions - atmospheric pressure below 300 degrees C. Extracts up to 60 percent of sulfur content of high-sulfur fuel. Applicable to petroleum refineries, natural-gas processors, electric powerplants, and chemical-processing plants. Method simpler and uses considerably lower pressure than current industrial method, hydro-desulfurization. Yields cleaner emissions from combustion of petroleum fuels, and protects catalysts from poisoning by sulfur.

  6. The case for a generic implant processor.

    Science.gov (United States)

    Strydis, Christos; Gaydadjiev, Georgi N

    2008-01-01

    A more structured and streamlined design of implants is nowadays possible. In this paper we focus on implant processors located in the heart of implantable systems. We present a real and representative biomedical-application scenario where such a new processor can be employed. Based on a suitably selected processor simulator, various operational aspects of the application are being monitored. Findings on performance, cache behavior, branch prediction, power consumption, energy expenditure and instruction mixes are presented and analyzed. The suitability of such an implant processor and directions for future work are given.

  7. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  8. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie L.; Adam, Niklas M.; Barta, Daniel; Meyer, Caitlin E.; Pensinger, Stuart; Vega, Leticia M.; Callahan, Michael R.; Flynn, Michael; Wheeler, Ray; hide

    2013-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrification and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  9. Thermodynamic analysis and performance of a 1 kW bioethanol processor for a PEMFC operation

    Energy Technology Data Exchange (ETDEWEB)

    Benito, M.; Padilla, R.; Sanz, J.L.; Daza, L. [Instituto de Catalisis y Petroleoquimica (CSIC), C/ Marie Curie 2, Campus Cantoblanco, 28049 Madrid (Spain)

    2007-06-10

    A thermodynamic analysis of a bioethanol steam reforming processor for CO-free hydrogen production was performed. The stages selected to perform CO purification were water gas shift and CO preferential oxidation. In order to optimize the processor efficiency, several configurations were studied. A processor efficiency of 69% for a steam/carbon ratio (S/C) of 4.8 was achieved taking advantage of the heat released during the exothermic stages. An efficiency close to 28% at the same S/C ratio for a bioethanol processor-PEMFC system, which includes a heat recovery system for off-gas from the fuel cell anode, was obtained. To produce a CO-free hydrogen rich stream, a 1 kW bioethanol processor was designed, built and operated, based on previous simulation studies. A new catalyst developed in the Institute of Catalysis and Petro-chemistry (ICP-CSIC) and tested for more than 500 h, that demonstrated excellent results at laboratory scale, was selected for the steam reforming stage. From bioethanol processor operation, a hydrogen rich stream, with CO composition as low as 3 ppmV was obtained, which is able to supply a PEMFC. (author)

  10. Fuel cell commercialization issues for light-duty vehicle applications

    Science.gov (United States)

    Borroni-Bird, Christopher E.

    The major challenges facing fuel cells in light-duty vehicle applications relate to the high cost of the fuel cell stack components (membrane, electro-catalyst and bipolar plate) which dictate that new manufacturing processes and materials must be developed. Initially, the best fuel for a mass market light-duty vehicle will probably not be the best fuel for the fuel cell (hydrogen); refueling infrastructure and energy density concerns may demand the use of an on-board fuel processor for petroleum-based fuels since this will increase customer acceptance. The use of fuel processors does, however, reduce the fuel cell system's efficiency. Moreover, if such fuels are used then the emissions benefit associated with fuel cells may come with a significant penalty in terms of added complexity, weight, size and cost. However, ultimately, fuel cells powered by hydrogen do promise to be the most efficient and cleanest of automotive powertrains.

  11. Ultrafast Fourier-transform parallel processor

    Energy Technology Data Exchange (ETDEWEB)

    Greenberg, W.L.

    1980-04-01

    A new, flexible, parallel-processing architecture is developed for a high-speed, high-precision Fourier transform processor. The processor is intended for use in 2-D signal processing including spatial filtering, matched filtering and image reconstruction from projections.

  12. Adapting implicit methods to parallel processors

    Energy Technology Data Exchange (ETDEWEB)

    Reeves, L.; McMillin, B.; Okunbor, D.; Riggins, D. [Univ. of Missouri, Rolla, MO (United States)

    1994-12-31

    When numerically solving many types of partial differential equations, it is advantageous to use implicit methods because of their better stability and more flexible parameter choice, (e.g. larger time steps). However, since implicit methods usually require simultaneous knowledge of the entire computational domain, these methods axe difficult to implement directly on distributed memory parallel processors. This leads to infrequent use of implicit methods on parallel/distributed systems. The usual implementation of implicit methods is inefficient due to the nature of parallel systems where it is common to take the computational domain and distribute the grid points over the processors so as to maintain a relatively even workload per processor. This creates a problem at the locations in the domain where adjacent points are not on the same processor. In order for the values at these points to be calculated, messages have to be exchanged between the corresponding processors. Without special adaptation, this will result in idle processors during part of the computation, and as the number of idle processors increases, the lower the effective speed improvement by using a parallel processor.

  13. The TM3270 Media-processor

    NARCIS (Netherlands)

    van de Waerdt, J.W.

    2006-01-01

    I n this thesis, we present the TM3270 VLIW media-processor, the latest of TriMedia processors, and describe the innovations with respect to its prede- cessor: the TM3260. We describe enhancements to the load/store unit design, such as a new data prefetching technique, and architectural

  14. Multi-output programmable quantum processor

    OpenAIRE

    Yu, Yafei; Feng, Jian; Zhan, Mingsheng

    2002-01-01

    By combining telecloning and programmable quantum gate array presented by Nielsen and Chuang [Phys.Rev.Lett. 79 :321(1997)], we propose a programmable quantum processor which can be programmed to implement restricted set of operations with several identical data outputs. The outputs are approximately-transformed versions of input data. The processor successes with certain probability.

  15. 7 CFR 1215.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who...

  16. The TM3270 Media-processor

    NARCIS (Netherlands)

    van de Waerdt, J.W.

    2006-01-01

    I n this thesis, we present the TM3270 VLIW media-processor, the latest of TriMedia processors, and describe the innovations with respect to its prede- cessor: the TM3260. We describe enhancements to the load/store unit design, such as a new data prefetching technique, and architectural enhancements

  17. Advanced Multiple Processor Configuration Study. Final Report.

    Science.gov (United States)

    Clymer, S. J.

    This summary of a study on multiple processor configurations includes the objectives, background, approach, and results of research undertaken to provide the Air Force with a generalized model of computer processor combinations for use in the evaluation of proposed flight training simulator computational designs. An analysis of a real-time flight…

  18. The Case for a Generic Implant Processor

    NARCIS (Netherlands)

    Strydis, C.; Gaydadjiev, G.N.

    2008-01-01

    A more structured and streamlined design of implants is nowadays possible. In this paper we focus on implant processors located in the heart of implantable systems. We present a real and representative biomedical-application scenario where such a new processor can be employed. Based on a suitably se

  19. An Empirical Evaluation of XQuery Processors

    NARCIS (Netherlands)

    Manegold, S.

    2008-01-01

    This paper presents an extensive and detailed experimental evaluation of XQuery processors. The study consists of running five publicly available XQuery benchmarks --- the Michigan benchmark (MBench), XBench, XMach-1, XMark and X007 --- on six XQuery processors, three stand-alone (file-based) XQuery

  20. The Case for a Generic Implant Processor

    NARCIS (Netherlands)

    Strydis, C.; Gaydadjiev, G.N.

    2008-01-01

    A more structured and streamlined design of implants is nowadays possible. In this paper we focus on implant processors located in the heart of implantable systems. We present a real and representative biomedical-application scenario where such a new processor can be employed. Based on a suitably

  1. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  2. Verilog Implementation of 32-Bit CISC Processor

    Directory of Open Access Journals (Sweden)

    P.Kanaka Sirisha

    2016-04-01

    Full Text Available The Project deals with the design of the 32-Bit CISC Processor and modeling of its components using Verilog language. The Entire Processor uses 32-Bit bus to deal with all the registers and the memories. This Processor implements various arithmetic, logical, Data Transfer operations etc., using variable length instructions, which is the core property of the CISC Architecture. The Processor also supports various addressing modes to perform a 32-Bit instruction. Our Processor uses Harvard Architecture (i.e., to have a separate program and data memory and hence has different buses to negotiate with the Program Memory and Data Memory individually. This feature enhances the speed of our processor. Hence it has two different Program Counters to point to the memory locations of the Program Memory and Data Memory.Our processor has ‘Instruction Queuing’ which enables it to save the time needed to fetch the instruction and hence increases the speed of operation. ‘Interrupt Service Routine’ is provided in our Processor to make it address the Interrupts.

  3. 无人水下航行器外热源热机用无气体产生燃料%No-gas Generation Fuel Used in External Heat Source Engine of Unmanned Underwear Vehicle(UUV)

    Institute of Scientific and Technical Information of China (English)

    陆宏; 赵熙; 倪亚菲; 邵明臣; 李大鹏

    2015-01-01

    无人水下航行器(UUV)在军事领域正得到愈发广泛的应用,动力装置是其技术难点之一.无人水下航行器采用外热源热机,在续航力和航速上,都优于其他类型动力装置,且使用无气体产生燃料,可从根本上解决水下气体排放问题,提高航行隐蔽性,具有良好的军事应用前景.本文根据无人水下航行器的使用条件和技术要求,对适用于无人水下航行器外热源热机的无气体产生燃料进行了广泛考察,给出了可用于无人水下航行器外热源热机的无气体产生燃料和氧化剂的组合.%Unmanned underwater vehicle(UUV) is applied to the military field more and more widely, of which power plant is one of its technical difficulties. External heat source engine is better than the other types of UUV's power plants by the characters of continuous navigation capacity and navigation velocity. Employment of no-gas generation fuel for the UUV can resolve the problem of gas exhaust underwater and improve navigation stealth. According to technical requirements and working conditions of the UUV, no-gas generation fuels that can be used in the external heat source engine of the UUV are investigated, and used no-gas generation fuels and theirs oxidizers are given in this thesis.

  4. Neurovision processor for designing intelligent sensors

    Science.gov (United States)

    Gupta, Madan M.; Knopf, George K.

    1992-03-01

    A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

  5. General Motors automotive fuel cell program

    Energy Technology Data Exchange (ETDEWEB)

    Fronk, M.H.

    1995-08-01

    The objectives of the second phase of the GM/DOE fuel cell program is to develop and test a 30 kW fuel cell powerplant. This powerplant will be based on a methanol fuel processor and a proton exchange membrane PM fuel cell stack. In addition, the 10 kW system developed during phase I will be used as a {open_quotes}mule{close_quotes} to test automotive components and other ancillaries, needed for transient operation.

  6. Enabling Future Robotic Missions with Multicore Processors

    Science.gov (United States)

    Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

    2011-01-01

    Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

  7. High Throughput Bent-Pipe Processor Demonstrator

    Science.gov (United States)

    Tabacco, P.; Vernucci, A.; Russo, L.; Cangini, P.; Botticchio, T.; Angeletti, P.

    2008-08-01

    The work associated to this article is a study initiative sponsored by ESA/ESTEC that responds to the crucial need of developing new Satellite payload aimed at making rapid progresses in handling large amounts of data at a competitive price with respect to terrestrial one in the telecommunication field. Considering the quite limited band allowed to space communications at Ka band, reusing the same band in a large number of beams is mandatory: therefore beam-forming is the right technological answer. Technological progresses - mainly in the digital domain - also help greatly in increasing the satellite capacity. Next Satellite payload target are set in throughput range of 50Gbps. Despite the fact that the implementation of a wideband transparent processor for a high capacity communication payload is a very challenging task, Space Engineering team in the frame of this ESA study proposed an intermediate step of development for a scalable unit able to demonstrate both the capacity and flexibility objectives for different type of Wideband Beamforming antennas designs. To this aim the article describes the features of Wideband HW (analog and digital) platform purposely developed by Space Engineering in the frame of this ESA/ESTEC contract ("WDBFN" contract) with some preliminary system test results. The same platform and part of the associated SW will be used in the development and demonstration of the real payload digital front end Mux and Demux algorithms as well as the Beam Forming and on Board channel switching in frequency domain. At the time of this article writing, despite new FPGA and new ADC and DAC converters have become available as choices for wideband system implementation, the two HW platforms developed by Space Engineering, namely WDBFN ADC and DAC Boards, represent still the most performing units in terms of analog bandwidth, processing capability (in terms of FPGA module density), SERDES (SERiliazer DESerializers) external links density, integration form

  8. Making CSB+-Tree Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose...

  9. Processor arrays with asynchronous TDM optical buses

    Science.gov (United States)

    Li, Y.; Zheng, S. Q.

    1997-04-01

    We propose a pipelined asynchronous time division multiplexing optical bus. Such a bus can use one of the two hardwared priority schemes, the linear priority scheme and the round-robin priority scheme. Our simulation results show that the performances of our proposed buses are significantly better than the performances of known pipelined synchronous time division multiplexing optical buses. We also propose a class of processor arrays connected by pipelined asynchronous time division multiplexing optical buses. We claim that our proposed processor array not only have better performance, but also have better scalabilities than the existing processor arrays connected by pipelined synchronous time division multiplexing optical buses.

  10. Concept of a Supervector Processor: A Vector Approach to Superscalar Processor, Design and Performance Analysis

    Directory of Open Access Journals (Sweden)

    Deepak Kumar, Ranjan Kumar Behera, K. S. Pandey

    2013-07-01

    Full Text Available To maximize the available performance is always a goal in microprocessor design. In this paper a new technique has been implemented which exploits the advantage of both superscalar and vector processing technique in a proposed processor called Supervector processor. Vector processor operates on array of data called vector and can greatly improve certain task such as numerical simulation and tasks which requires huge number crunching. On other handsuperscalar processor issues multiple instructions per cyclewhich can enhance the throughput. To implement parallelism multiple vector instructions were issued and executed per cycle in superscalar fashion. Case study has been done on various benchmarks to compare the performance of proposedsupervector processor architecture with superscalar and vectorprocessor architecture. Trimaran Framework has been used in order to evaluate the performance of the proposed supervector processor scheme.

  11. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  12. Radiation Tolerant Software Defined Video Processor Project

    Data.gov (United States)

    National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....

  13. Processor-Dependent Malware... and codes

    CERN Document Server

    Desnos, Anthony; Filiol, Eric

    2010-01-01

    Malware usually target computers according to their operating system. Thus we have Windows malwares, Linux malwares and so on ... In this paper, we consider a different approach and show on a technical basis how easily malware can recognize and target systems selectively, according to the onboard processor chip. This technology is very easy to build since it does not rely on deep analysis of chip logical gates architecture. Floating Point Arithmetic (FPA) looks promising to define a set of tests to identify the processor or, more precisely, a subset of possible processors. We give results for different families of processors: AMD, Intel (Dual Core, Atom), Sparc, Digital Alpha, Cell, Atom ... As a conclusion, we propose two {\\it open problems} that are new, to the authors' knowledge.

  14. Fuel analyzer; Analisador de combustiveis

    Energy Technology Data Exchange (ETDEWEB)

    Cozzolino, Roberval [RS Motors, Indaiatuba, SP (Brazil)

    2008-07-01

    The current technology 'COMBUSTIMETRO' aims to examine the fuel through performance of the engine, as the role of the fuel is to produce energy for the combustion engine in the form of which is directly proportional to the quality and type of fuel. The 'COMBUSTIMETRO' has an engine that always keeps the same entry of air, fuel and fixed point of ignition. His operation is monitored by sensors (Sonda Lambda, RPM and Gases Analyzer) connected to a processor that performs calculations and records the information, generate reports and graphs. (author)

  15. Critical review of programmable media processor architectures

    Science.gov (United States)

    Berg, Stefan G.; Sun, Weiyun; Kim, Donglok; Kim, Yongmin

    1998-12-01

    In the past several years, there has been a surge of new programmable mediaprocessors introduced to provide an alternative solution to ASICs and dedicated hardware circuitries in the multimedia PC and embedded consumer electronics markets. These processors attempt to combine the programmability of multimedia-enhanced general purpose processors with the performance and low cost of dedicated hardware. We have reviewed five current multimedia architectures and evaluated their strengths and weaknesses.

  16. First Cluster Algorithm Special Purpose Processor

    Science.gov (United States)

    Talapov, A. L.; Andreichenko, V. B.; Dotsenko S., Vi.; Shchur, L. N.

    We describe the architecture of the special purpose processor built to realize in hardware cluster Wolff algorithm, which is not hampered by a critical slowing down. The processor simulates two-dimensional Ising-like spin systems. With minor changes the same very effective architecture, which can be defined as a Memory Machine, can be used to study phase transitions in a wide range of models in two or three dimensions.

  17. A New Echeloned Poisson Series Processor (EPSP)

    Science.gov (United States)

    Ivanova, Tamara

    2001-07-01

    A specialized Echeloned Poisson Series Processor (EPSP) is proposed. It is a typical software for the implementation of analytical algorithms of Celestial Mechanics. EPSP is designed for manipulating long polynomial-trigonometric series with literal divisors. The coefficients of these echeloned series are the rational or floating-point numbers. The Keplerian processor and analytical generator of special celestial mechanics functions based on the EPSP are also developed.

  18. Evaluating current processors performance and machines stability

    CERN Document Server

    Esposito, R; Tortone, G; Taurino, F M

    2003-01-01

    Accurately estimate performance of currently available processors is becoming a key activity, particularly in HENP environment, where high computing power is crucial. This document describes the methods and programs, opensource or freeware, used to benchmark processors, memory and disk subsystems and network connection architectures. These tools are also useful to stress test new machines, before their acquisition or before their introduction in a production environment, where high uptimes are requested.

  19. A wearable real-time image processor for a vision prosthesis.

    Science.gov (United States)

    Tsai, D; Morley, J W; Suaning, G J; Lovell, N H

    2009-09-01

    Rapid progress in recent years has made implantable retinal prostheses a promising therapeutic option in the near future for patients with macular degeneration or retinitis pigmentosa. Yet little work on devices that encode visual images into electrical stimuli have been reported to date. This paper presents a wearable image processor for use as the external module of a vision prosthesis. It is based on a dual-core microprocessor architecture and runs the Linux operating system. A set of image-processing algorithms executes on the digital signal processor of the device, which may be controlled remotely via a standard desktop computer. The results indicate that a highly flexible and configurable image processor can be built with the dual-core architecture. Depending on the image-processing requirements, general-purpose embedded microprocessors alone may be inadequate for implementing image-processing strategies required by retinal prostheses.

  20. SMART AS A CRYPTOGRAPHIC PROCESSOR

    Directory of Open Access Journals (Sweden)

    Saroja Kanchi

    2016-05-01

    Full Text Available SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algorithm on the HC12, a same-size but CISC-type off-the-shelf microcontroller, Our results show that compared to HC12, SMaRT code is only 14% longer in terms of the static number of instructions but about 10 times faster in terms of the number of clock cycles, and 7% smaller in terms of code size. Our results also show that 2.5- address instructions, a SMaRT selling point, amount to 45% of the whole R-type instructions resulting in significant improvement in static number of instructions hence code size as well as performance. Additionally, we see that the SMaRT short-branch range is sufficiently wide in 90% of cases in the SMaRT code. Our results also reveal that the SMaRT novel concept of locality of reference in using the MSBs of the registers in non-subroutine branch instructions stays valid with a remarkable hit rate of 95%!

  1. Fuel flexible fuel injector

    Science.gov (United States)

    Tuthill, Richard S; Davis, Dustin W; Dai, Zhongtao

    2015-02-03

    A disclosed fuel injector provides mixing of fuel with airflow by surrounding a swirled fuel flow with first and second swirled airflows that ensures mixing prior to or upon entering the combustion chamber. Fuel tubes produce a central fuel flow along with a central airflow through a plurality of openings to generate the high velocity fuel/air mixture along the axis of the fuel injector in addition to the swirled fuel/air mixture.

  2. Dynamic behavior of gasoline fuel cell electric vehicles

    Science.gov (United States)

    Mitchell, William; Bowers, Brian J.; Garnier, Christophe; Boudjemaa, Fabien

    As we begin the 21st century, society is continuing efforts towards finding clean power sources and alternative forms of energy. In the automotive sector, reduction of pollutants and greenhouse gas emissions from the power plant is one of the main objectives of car manufacturers and innovative technologies are under active consideration to achieve this goal. One technology that has been proposed and vigorously pursued in the past decade is the proton exchange membrane (PEM) fuel cell, an electrochemical device that reacts hydrogen with oxygen to produce water, electricity and heat. Since today there is no existing extensive hydrogen infrastructure and no commercially viable hydrogen storage technology for vehicles, there is a continuing debate as to how the hydrogen for these advanced vehicles will be supplied. In order to circumvent the above issues, power systems based on PEM fuel cells can employ an on-board fuel processor that has the ability to convert conventional fuels such as gasoline into hydrogen for the fuel cell. This option could thereby remove the fuel infrastructure and storage issues. However, for these fuel processor/fuel cell vehicles to be commercially successful, issues such as start time and transient response must be addressed. This paper discusses the role of transient response of the fuel processor power plant and how it relates to the battery sizing for a gasoline fuel cell vehicle. In addition, results of fuel processor testing from a current Renault/Nuvera Fuel Cells project are presented to show the progress in transient performance.

  3. Cost reductions of fuel cells for transport applications: fuel processing options

    Science.gov (United States)

    Teagan, W. P.; Bentley, J.; Barnett, B.

    The highly favorable efficiency/environmental characteristics of fuel cell technologies have now been verified by virtue of recent and ongoing field experience. The key issue regarding the timing and extent of fuel cell commercialization is the ability to reduce costs to acceptable levels in both stationary and transport applications. It is increasingly recognized that the fuel processing subsystem can have a major impact on overall system costs, particularly as ongoing R&D efforts result in reduction of the basic cost structure of stacks which currently dominate system costs. The fuel processing subsystem for polymer electrolyte membrane fuel cell (PEMFC) technology, which is the focus of transport applications, includes the reformer, shift reactors, and means for CO reduction. In addition to low cost, transport applications require a fuel processor that is compact and can start rapidly. This paper describes the impact of factors such as fuel choice, operating temperature, material selection, catalyst requirements, and controls on the cost of fuel processing systems. There are fuel processor technology paths which manufacturing cost analyses indicate are consistent with fuel processor subsystem costs of under 150/kW in stationary applications and 30/kW in transport applications. As such, the costs of mature fuel processing subsystem technologies should be consistent with their use in commercially viable fuel cell systems in both application categories.

  4. 49 CFR 238.223 - Locomotive fuel tanks.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Locomotive fuel tanks. 238.223 Section 238.223... Equipment § 238.223 Locomotive fuel tanks. Locomotive fuel tanks shall comply with either the following or....21: (a) External fuel tanks. External locomotive fuel tanks shall comply with the...

  5. Onboard Data Processor for Change-Detection Radar Imaging

    Science.gov (United States)

    Lou, Yunling; Muellerschoen, Ronald J.; Chien, Steve A.; Saatchi, Sasan S.; Clark, Duane

    2008-01-01

    A computer system denoted a change-detection onboard processor (CDOP) is being developed as a means of processing the digitized output of a synthetic-aperture radar (SAR) apparatus aboard an aircraft or spacecraft to generate images showing changes that have occurred in the terrain below between repeat passes of the aircraft or spacecraft over the terrain. When fully developed, the CDOP is intended to be capable of generating SAR images and/or SAR differential interferograms in nearly real time. The CDOP is expected to be especially useful for understanding some large-scale natural phenomena and/or mitigating natural hazards: For example, it could be used for near-real-time observation of surface changes caused by floods, landslides, forest fires, volcanic eruptions, earthquakes, glaciers, and sea ice movements. It could also be used to observe such longer-term surface changes as those associated with growth of vegetation (relevant to estimation of wildfire fuel loads). The CDOP is, essentially, an interferometric SAR processor designed to operate aboard a radar platform.

  6. IDSP- INTERACTIVE DIGITAL SIGNAL PROCESSOR

    Science.gov (United States)

    Mish, W. H.

    1994-01-01

    The Interactive Digital Signal Processor, IDSP, consists of a set of time series analysis "operators" based on the various algorithms commonly used for digital signal analysis work. The processing of a digital time series to extract information is usually achieved by the application of a number of fairly standard operations. However, it is often desirable to "experiment" with various operations and combinations of operations to explore their effect on the results. IDSP is designed to provide an interactive and easy-to-use system for this type of digital time series analysis. The IDSP operators can be applied in any sensible order (even recursively), and can be applied to single time series or to simultaneous time series. IDSP is being used extensively to process data obtained from scientific instruments onboard spacecraft. It is also an excellent teaching tool for demonstrating the application of time series operators to artificially-generated signals. IDSP currently includes over 43 standard operators. Processing operators provide for Fourier transformation operations, design and application of digital filters, and Eigenvalue analysis. Additional support operators provide for data editing, display of information, graphical output, and batch operation. User-developed operators can be easily interfaced with the system to provide for expansion and experimentation. Each operator application generates one or more output files from an input file. The processing of a file can involve many operators in a complex application. IDSP maintains historical information as an integral part of each file so that the user can display the operator history of the file at any time during an interactive analysis. IDSP is written in VAX FORTRAN 77 for interactive or batch execution and has been implemented on a DEC VAX-11/780 operating under VMS. The IDSP system generates graphics output for a variety of graphics systems. The program requires the use of Versaplot and Template plotting

  7. Hydrogen Generation Via Fuel Reforming

    Science.gov (United States)

    Krebs, John F.

    2003-07-01

    Reforming is the conversion of a hydrocarbon based fuel to a gas mixture that contains hydrogen. The H2 that is produced by reforming can then be used to produce electricity via fuel cells. The realization of H2-based power generation, via reforming, is facilitated by the existence of the liquid fuel and natural gas distribution infrastructures. Coupling these same infrastructures with more portable reforming technology facilitates the realization of fuel cell powered vehicles. The reformer is the first component in a fuel processor. Contaminants in the H2-enriched product stream, such as carbon monoxide (CO) and hydrogen sulfide (H2S), can significantly degrade the performance of current polymer electrolyte membrane fuel cells (PEMFC's). Removal of such contaminants requires extensive processing of the H2-rich product stream prior to utilization by the fuel cell to generate electricity. The remaining components of the fuel processor remove the contaminants in the H2 product stream. For transportation applications the entire fuel processing system must be as small and lightweight as possible to achieve desirable performance requirements. Current efforts at Argonne National Laboratory are focused on catalyst development and reactor engineering of the autothermal processing train for transportation applications.

  8. A microbial fuel cell with the three-dimensional electrode applied an external voltage for synthesis of hydrogen peroxide from organic matter

    Science.gov (United States)

    Chen, Jia-yi; Zhao, Lin; Li, Nan; Liu, Hang

    2015-08-01

    The study experimentally investigates the changing performance of three-dimensional electrode H2O2-producting MFCs coupled with simultaneous wastewater treatment at various external cell voltages from 0.1 V to 0.8 V, in order to explore the optimal applied voltage and its reasons. The graphite particle electrodes made of graphite powders with polytetrafluoroethene (PTFE) as the binder are used as three-dimensional cathode. The results indicate that applied voltage is demonstrated to increase the productive rate and output of H2O2 and the efficiency of acetate degradation. Besides, a relatively high current density caused by a high applied voltage has a positive impact on anode performance in terms of organic degradation and coulombic efficiency. In addition, a relatively high voltage leads to the reduction of H2O2 and the evolution of H2. Considering H2O2 concentration, anodic COD removal and current efficiencies of MFCs at various voltages, the optimal voltage is chosen to be 0.4 V, achieving the H2O2 generation of 705.6 mg L-1 at a rate of 2.12 kg m-3 day-1 and 76% COD removal in 8 h, with energy input of 0.659 kWh per kg H2O2. Coulombic efficiency, faradic efficiency and COD conversion efficiency are 92%, 96%, and 88% respectively.

  9. Leukaemia and low dose radiation. Is there an association between leukaemia and cumulative external dose amongst the British Nuclear Fuel plc. (BNFL) workers?

    Energy Technology Data Exchange (ETDEWEB)

    McGeoghegan, D.; Binks, K. [Westlakes Scientific Consulting, Cumbria (United Kingdom)

    2000-05-01

    A detailed examination of the BNFL leukaemia data is presented, for the period 1941-1995, using the recently assembled company wide BNFL epidemiological database and the BNFL leukaemia case-control data set. The association of this occupationally exposed cohort is examined with respect to both leukaemia mortality and leukaemia morbidity. The excess relative risk for total leukaemia excluding chronic lymphatic leukaemia amongst the BNFL radiation workers was found to be 3.64 Sv{sup -1} (90% CI -0.13-11.22); for Sellafield and Springfields this figure was 7.99 Sv{sup -1} (90% CI 1.50-29.5) and -1.97 Sv{sup -1} (90% CI<-2.23-6.11) respectively. A 14-20% increase in risk is noted when dosimetry adjusted for measurement error, is used to determine the excess relative risk. The association between leukaemia and cumulative external radiation is found to be particularly associated with the Sellafield plant; the Springfields plant gave consistently negative risk estimates. (author)

  10. Proton exchange membrane fuel cell technology for transportation applications

    Energy Technology Data Exchange (ETDEWEB)

    Swathirajan, S. [General Motors R& D Center, Warren, MI (United States)

    1996-04-01

    Proton Exchange Membrane (PEM) fuel cells are extremely promising as future power plants in the transportation sector to achieve an increase in energy efficiency and eliminate environmental pollution due to vehicles. GM is currently involved in a multiphase program with the US Department of Energy for developing a proof-of-concept hybrid vehicle based on a PEM fuel cell power plant and a methanol fuel processor. Other participants in the program are Los Alamos National Labs, Dow Chemical Co., Ballard Power Systems and DuPont Co., In the just completed phase 1 of the program, a 10 kW PEM fuel cell power plant was built and tested to demonstrate the feasibility of integrating a methanol fuel processor with a PEM fuel cell stack. However, the fuel cell power plant must overcome stiff technical and economic challenges before it can be commercialized for light duty vehicle applications. Progress achieved in phase I on the use of monolithic catalyst reactors in the fuel processor, managing CO impurity in the fuel cell stack, low-cost electrode-membrane assembles, and on the integration of the fuel processor with a Ballard PEM fuel cell stack will be presented.

  11. Solid Oxide Fuel Cells Operating on Alternative and Renewable Fuels

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Xiaoxing; Quan, Wenying; Xiao, Jing; Peduzzi, Emanuela; Fujii, Mamoru; Sun, Funxia; Shalaby, Cigdem; Li, Yan; Xie, Chao; Ma, Xiaoliang; Johnson, David; Lee, Jeong; Fedkin, Mark; LaBarbera, Mark; Das, Debanjan; Thompson, David; Lvov, Serguei; Song, Chunshan

    2014-09-30

    This DOE project at the Pennsylvania State University (Penn State) initially involved Siemens Energy, Inc. to (1) develop new fuel processing approaches for using selected alternative and renewable fuels – anaerobic digester gas (ADG) and commercial diesel fuel (with 15 ppm sulfur) – in solid oxide fuel cell (SOFC) power generation systems; and (2) conduct integrated fuel processor – SOFC system tests to evaluate the performance of the fuel processors and overall systems. Siemens Energy Inc. was to provide SOFC system to Penn State for testing. The Siemens work was carried out at Siemens Energy Inc. in Pittsburgh, PA. The unexpected restructuring in Siemens organization, however, led to the elimination of the Siemens Stationary Fuel Cell Division within the company. Unfortunately, this led to the Siemens subcontract with Penn State ending on September 23rd, 2010. SOFC system was never delivered to Penn State. With the assistance of NETL project manager, the Penn State team has since developed a collaborative research with Delphi as the new subcontractor and this work involved the testing of a stack of planar solid oxide fuel cells from Delphi.

  12. Real time processor for array speckle interferometry

    Science.gov (United States)

    Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

    1989-01-01

    The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

  13. Making CSB+-Tree Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  14. Dynamic Load Balancing using Graphics Processors

    Directory of Open Access Journals (Sweden)

    R Mohan

    2014-04-01

    Full Text Available To get maximum performance on the many-core graphics processors, it is important to have an even balance of the workload so that all processing units contribute equally to the task at hand. This can be hard to achieve when the cost of a task is not known beforehand and when new sub-tasks are created dynamically during execution. Both the dynamic load balancing methods using Static task assignment and work stealing using deques are compared to see which one is more suited to the highly parallel world of graphics processors. They have been evaluated on the task of simulating a computer move against the human move, in the famous four in a row game. The experiments showed that synchronization can be very expensive, and those new methods which use graphics processor features wisely might be required.

  15. Intrusion Detection Architecture Utilizing Graphics Processors

    Directory of Open Access Journals (Sweden)

    Branislav Madoš

    2012-12-01

    Full Text Available With the thriving technology and the great increase in the usage of computer networks, the risk of having these network to be under attacks have been increased. Number of techniques have been created and designed to help in detecting and/or preventing such attacks. One common technique is the use of Intrusion Detection Systems (IDS. Today, number of open sources and commercial IDS are available to match enterprises requirements. However, the performance of these systems is still the main concern. This paper examines perceptions of intrusion detection architecture implementation, resulting from the use of graphics processor. It discusses recent research activities, developments and problems of operating systems security. Some exploratory evidence is presented that shows capabilities of using graphical processors and intrusion detection systems. The focus is on how knowledge experienced throughout the graphics processor inclusion has played out in the design of intrusion detection architecture that is seen as an opportunity to strengthen research expertise.

  16. ETHERNET PACKET PROCESSOR FOR SOC APPLICATION

    Directory of Open Access Journals (Sweden)

    Raja Jitendra Nayaka

    2012-07-01

    Full Text Available As the demand for Internet expands significantly in numbers of users, servers, IP addresses, switches and routers, the IP based network architecture must evolve and change. The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many processor based applications. This paper describes the design of ethernet packet processor for system-on-chip (SoC which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance. Our design has been configured for use with multiple projects ttargeted to a commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.

  17. Programmable DNA-mediated multitasking processor

    CERN Document Server

    Shu, Jian-Jun; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

    2015-01-01

    Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

  18. SWIFT Privacy: Data Processor Becomes Data Controller

    Directory of Open Access Journals (Sweden)

    Edwin Jacobs

    2007-04-01

    Full Text Available Last month, SWIFT emphasised the urgent need for a solution to compliance with US Treasury subpoenas that provides legal certainty for the financial industry as well as for SWIFT. SWIFT will continue its activities to adhere to the Safe Harbor framework of the European data privacy legislation. Safe Harbor is a framework negotiated by the EU and US in 2000 to provide a way for companies in Europe, with operations in the US, to conform to EU data privacy regulations. This seems to conclude a complex privacy case, widely covered by the US and European media. A fundamental question in this case was who is a data controller and who is a mere data processor. Both the Belgian and the European privacy authorities considered SWIFT, jointly with the banks, as a data controller whereas SWIFT had considered itself as a mere data processor that processed financial data for banks. The difference between controller and processor has far reaching consequences.

  19. Scalable solid-state quantum processor using subradiant two-atom states.

    Science.gov (United States)

    Petrosyan, David; Kurizki, Gershon

    2002-11-11

    We propose a realization of a scalable, high-performance quantum processor whose qubits are represented by the ground and subradiant states of effective dimers formed by pairs of two-level systems coupled by resonant dipole-dipole interaction. The dimers are implanted in low-temperature solid host material at controllable nanoscale separations. The two-qubit entanglement either relies on the coherent excitation exchange between the dimers or is mediated by external laser fields.

  20. Efficient SIMD optimization for media processors

    Institute of Scientific and Technical Information of China (English)

    Jian-peng ZHOU; Ce SHI

    2008-01-01

    Single instruction multiple data (SIMD) instructions are often implemented in modem media processors. Although SIMD instructions are useful in multimedia applications, most compilers do not have good support for SIMD instructions. This paper focuses on SIMD instructions generation for media processors. We present an efficient code optimization approach that is integrated into a retargetable C compiler. SIMD instructions are generated by finding and combining the same operations in programs. Experimental results for the UltraSPARC VIS instruction set show that a speedup factor up to 2.639 is obtained.

  1. 8 Bit RISC Processor Using Verilog HDL

    Directory of Open Access Journals (Sweden)

    Ramandeep Kaur

    2014-03-01

    Full Text Available RISC is a design philosophy to reduce the complexity of instruction set that in turn reduces the amount of space, cycle time, cost and other parameters taken into account during the implementation of the design. The advent of FPGA has enabled the complex logical systems to be implemented on FPGA. The intent of this paper is to design and implement 8 bit RISC processor using FPGA Spartan 3E tool. This processor design depends upon design specification, analysis and simulation. It takes into consideration very simple instruction set. The momentous components include Control unit, ALU, shift registers and accumulator register.

  2. Models of Communication for Multicore Processors

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Sørensen, Rasmus Bo; Sparsø, Jens

    2015-01-01

    To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e.......g., shared caches with cache coherency protocols, core-to-core networks-on-chip, and shared scratchpad memories. In this paper we explore the different hardware mechanism for on-chip communication and how they support or favor different models of communication. Furthermore, we discuss the usability...... of the different models of communication for real-time systems....

  3. SPROC: A multiple-processor DSP IC

    Science.gov (United States)

    Davis, R.

    1991-01-01

    A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

  4. Models of Communication for Multicore Processors

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Sørensen, Rasmus Bo; Sparsø, Jens

    2015-01-01

    To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e.......g., shared caches with cache coherency protocols, core-to-core networks-on-chip, and shared scratchpad memories. In this paper we explore the different hardware mechanism for on-chip communication and how they support or favor different models of communication. Furthermore, we discuss the usability...... of the different models of communication for real-time systems....

  5. Multi-core processors - An overview

    CERN Document Server

    Venu, Balaji

    2011-01-01

    Microprocessors have revolutionized the world we live in and continuous efforts are being made to manufacture not only faster chips but also smarter ones. A number of techniques such as data level parallelism, instruction level parallelism and hyper threading (Intel's HT) already exists which have dramatically improved the performance of microprocessor cores. This paper briefs on evolution of multi-core processors followed by introducing the technology and its advantages in today's world. The paper concludes by detailing on the challenges currently faced by multi-core processors and how the industry is trying to address these issues.

  6. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  7. Inter Processor Communication for Fault Diagnosis in Multiprocessor Systems

    Directory of Open Access Journals (Sweden)

    C. D. Malleswar

    1994-04-01

    Full Text Available In the preseJlt paper a simple technique is proposed for fault diagnosis for multiprocessor and multiple system environments, wherein all microprocessors in the system are used in part to check the health of their neighbouring processors. It involves building simple fail-safe serial communication links between processors. Processors communicate with each other over these links and each processor is made to go through certain sequences of actions intended for diagnosis, under the observation of another processor .With limited overheads, fault detection can be done by this method. Also outlined are some of the popular techniques used for health check of processor-based systems.

  8. CERN Technical Training: Signal Processor

    CERN Multimedia

    HR Department

    2009-01-01

    A new training is going to be held at CERN on the ADSP SHARC Family. The "System Development and Programming with the Analog Devices’ SHARC Family" course is a 3.5-day hands-on training on Analog Devices SHARC DSPs, focusing on the latest ‘368/9 and 37x families. General DSP architecture, peripherals available, booting up process and DSP code development will be covered. Hardware tools, debugging and hardware design guidelines will be introduced as well. The course id designed for System Designers needing to make informed decisions on design tradeoffs, Hardware Designers needing to develop external interfaces, and Code Developers needing to know how to get the highest performance from their algorithms. The course will take place, in English, from 31 March to 4 April in the CERN Technical Training Center. Few places are still available. Registrations are opened on the Technical Training page. More information on our catalogue: http://cta.cern.ch/cta2/f?p=110:9 or contact us with your que...

  9. Diesel fuel to dc power: Navy & Marine Corps Applications

    Energy Technology Data Exchange (ETDEWEB)

    Bloomfield, D.P. [Analytic Power Corp., Boston, MA (United States)

    1996-12-31

    During the past year Analytic Power has tested fuel cell stacks and diesel fuel processors for US Navy and Marine Corps applications. The units are 10 kW demonstration power plants. The USN power plant was built to demonstrate the feasibility of diesel fueled PEM fuel cell power plants for 250 kW and 2.5 MW shipboard power systems. We designed and tested a ten cell, 1 kW USMC substack and fuel processor. The complete 10 kW prototype power plant, which has application to both power and hydrogen generation, is now under construction. The USN and USMC fuel cell stacks have been tested on both actual and simulated reformate. Analytic Power has accumulated operating experience with autothermal reforming based fuel processors operating on sulfur bearing diesel fuel, jet fuel, propane and natural gas. We have also completed the design and fabrication of an advanced regenerative ATR for the USMC. One of the significant problems with small fuel processors is heat loss which limits its ability to operate with the high steam to carbon ratios required for coke free high efficiency operation. The new USMC unit specifically addresses these heat transfer issues. The advances in the mill programs have been incorporated into Analytic Power`s commercial units which are now under test.

  10. Space Station Water Processor Process Pump

    Science.gov (United States)

    Parker, David

    1995-01-01

    This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

  11. A Demo Processor as an Educational Tool

    NARCIS (Netherlands)

    van Moergestel, L.; van Nieuwland, K.; Vermond, L.; Meyer, John-Jules Charles

    2014-01-01

    Explaining the workings of a processor can be done in several ways. Just a written explanation, some pictures, a simulator program or a real hardware demo. The research presented here is based on the idea that a slowly working hardware demo could be a nice tool to explain to IT students the inner

  12. Quantum Algorithm Processor For Finding Exact Divisors

    OpenAIRE

    Burger, John Robert

    2005-01-01

    Wiring diagrams are given for a quantum algorithm processor in CMOS to compute, in parallel, all divisors of an n-bit integer. Lines required in a wiring diagram are proportional to n. Execution time is proportional to the square of n.

  13. Continuous history variable for programmable quantum processors

    CERN Document Server

    Vlasov, Alexander Yu

    2010-01-01

    In this brief note is discussed application of continuous quantum history ("trash") variable for simplification of scheme of programmable quantum processor. Similar scheme may be tested also in other models of the theory of quantum algorithms and complexity, because provides modification of a standard operation: quantum function evaluation.

  14. Focal-plane sensor-processor chips

    CERN Document Server

    Zarándy, Ákos

    2011-01-01

    Focal-Plane Sensor-Processor Chips explores both the implementation and application of state-of-the-art vision chips. Presenting an overview of focal plane chip technology, the text discusses smart imagers and cellular wave computers, along with numerous examples of current vision chips.

  15. Microarchitecture of the Godson-2 Processor

    Institute of Scientific and Technical Information of China (English)

    Wei-Wu Hu; Fu-Xin Zhang; Zu-Song Li

    2005-01-01

    The Godson project is the first attempt to design high performance general-purpose microprocessors in China.This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18μm CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3ns.

  16. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  17. Practical guide to energy management for processors

    CERN Document Server

    Consortium, Energywise

    2012-01-01

    Do you know how best to manage and reduce your energy consumption? This book gives comprehensive guidance on effective energy management for organisations in the polymer processing industry. This book is one of three which support the ENERGYWISE Plastics Project eLearning platform for European plastics processors to increase their knowledge and understanding of energy management. Topics covered include: Understanding Energy,

  18. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  19. Analysis of Reconfigurable Processors Using Petri Net

    Directory of Open Access Journals (Sweden)

    Hadis Heidari

    2013-07-01

    Full Text Available In this paper, we propose Petri net models for processing elements. The processing elements include: a general-purpose processor (GPP, a reconfigurable element (RE, and a hybrid element (combining a GPP with an RE. The models consist of many transitions and places. The model and associated analysis methods provide a promising tool for modeling and performance evaluation of reconfigurable processors. The model is demonstrated by considering a simple example. This paper describes the development of a reconfigurable processor; the developed system is based on the Petri net concept. Petri nets are becoming suitable as a formal model for hardware system design. Designers can use Petri net as a modeling language to perform high level analysis of complex processors designs processing chips. The simulation does with PIPEv4.1 simulator. The simulation results show that Petri net state spaces are bounded and safe and have not deadlock and the average of number tokens in first token is 0.9901 seconds. In these models, there are only 5% errors; also the analysis time in these models is 0.016 seconds.

  20. Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths

    National Research Council Canada - National Science Library

    Abdul Rehman Buzdar; Liguo Sun; Rao Kashif; Muhammad Waqar Azhar; Muhammad Imran Khan

    2017-01-01

    We present the integration of a multimode Cyclic Redundancy Checking (CRC) accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency...

  1. Area and Energy Efficient Viterbi Accelerator for Embedded Processor Datapaths

    National Research Council Canada - National Science Library

    Abdul Rehman Buzdar; Liguo Sun; Muhammad Waqar Azhar; Muhammad Imran Khan; Rao Kashif

    2017-01-01

    .... We present the integration of a mixed hardware/software viterbi accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency...

  2. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S.; Sedukhin, S. [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I.

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  3. 49 CFR 234.275 - Processor-based systems.

    Science.gov (United States)

    2010-10-01

    ..., DEPARTMENT OF TRANSPORTATION GRADE CROSSING SIGNAL SYSTEM SAFETY AND STATE ACTION PLANS Maintenance, Inspection, and Testing Requirements for Processor-Based Systems § 234.275 Processor-based systems. (a... 49 Transportation 4 2010-10-01 2010-10-01 false Processor-based systems. 234.275 Section...

  4. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores that...

  5. gFEX, the ATLAS Calorimeter Level-1 Real Time Processor

    CERN Document Server

    Tang, Shaochun; The ATLAS collaboration; Chen, Hucheng; Lanni, Francesco; Takai, Helio; Wu, Weihao

    2015-01-01

    The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA ...

  6. gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

    CERN Document Server

    Tang, Shaochun; The ATLAS collaboration

    2015-01-01

    The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance ...

  7. Productivity and quality performance of an innovative firewood processor

    Directory of Open Access Journals (Sweden)

    Raffaele Cavalli

    2014-06-01

    Full Text Available The growing interest about wood as fuel regards not only wood chips and pellets but also firewood, especially in mountain and rural areas where domestic heating plants are widely used. Due to the increased demand for firewood, harvesting activities have extended on broadleaved high forests as well as coppice. As a consequence, the diameter of logs has increased requiring larger and larger splitting machines; nowadays it is not uncommon to find on the market splitters able to process logs with diameter up to 50-60 cm. In order to increase the productivity, the effort of machine producers is directed to obtain the complete splitting of the log into firewood in only one step using multiple ways splitting knives. This technical solution may cause some drawbacks especially when the splitting knives are not properly adapted to the log diameter; it happens that the size of firewood is not homogeneous and splinters are produced, which requires using screens to separate them from the main product. In order to evaluate the work quality of a firewood processor, equipped with multiple ways splitting knives, an experimental test has been carried out using a machine in which the log diameter is automatically detected through a laser device; according to the log diameter the multiple ways splitting knives (formed by fixed and mobile knives, the latter hydraulically operated is properly set up to obtain regularly sized firewood. Furthermore the log is automatically centred on the splitting knife set-up. The results of the experimental test showed that the firewood processor is able to produce firewood with homogeneous size and with a low production of splinters, regardless of log diameter.

  8. Finite difference programs and array processors. [High-speed floating point processing by coupling host computer to programable array processor

    Energy Technology Data Exchange (ETDEWEB)

    Rudy, T.E.

    1977-08-01

    An alternative to maxi computers for high-speed floating-point processing capabilities is the coupling of a host computer to a programable array processor. This paper compares the performance of two finite difference programs on various computers and their expected performance on commercially available array processors. The significance of balancing array processor computation, host-array processor control traffic, and data transfer operations is emphasized. 3 figures, 1 table.

  9. Cache Energy Optimization Techniques For Modern Processors

    Energy Technology Data Exchange (ETDEWEB)

    Mittal, Sparsh [ORNL

    2013-01-01

    Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems. In this book, we present novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. Also, we present cache energy saving techniques for caches designed with both conventional SRAM devices and emerging non-volatile devices such as STT-RAM (spin-torque transfer RAM). We present software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with state-of-the-art techniques and have found that our techniques outperform them in terms of energy efficiency and other relevant metrics. The techniques presented in this book have important applications in improving energy-efficiency of higher-end embedded, desktop, QoS, real-time, server processors and multitasking systems. This book is intended to be a valuable guide for both

  10. Multi-Core Processor Memory Contention Benchmark Analysis Case Study

    Science.gov (United States)

    Simon, Tyler; McGalliard, James

    2009-01-01

    Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

  11. Multiple core computer processor with globally-accessible local memories

    Energy Technology Data Exchange (ETDEWEB)

    Shalf, John; Donofrio, David; Oliker, Leonid

    2016-09-20

    A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

  12. Design of Processors with Reconfigurable Microarchitecture

    Directory of Open Access Journals (Sweden)

    Andrey Mokhov

    2014-01-01

    Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

  13. Multifunction nonlinear signal processor - Deconvolution and correlation

    Science.gov (United States)

    Javidi, Bahram; Horner, Joseph L.

    1989-08-01

    A multifuncional nonlinear optical signal processor is described that allows different types of operations, such as image deconvolution and nonlinear correlation. In this technique, the joint power spectrum of the input signal is thresholded with varying nonlinearity to produce different specific operations. In image deconvolution, the joint power spectrum is modified and hard-clip thresholded to remove the amplitude distortion effects and to restore the correct phase of the original image. In optical correlation, the Fourier transform interference intensity is thresholded to provide higher correlation peak intensity and a better-defined correlation spot. Various types of correlation signals can be produced simply by varying the severity of the nonlinearity, without the need for synthesis of specific matched filter. An analysis of the nonlinear processor for image deconvolution is presented.

  14. Model of computation for Fourier optical processors

    Science.gov (United States)

    Naughton, Thomas J.

    2000-05-01

    We present a novel and simple theoretical model of computation that captures what we believe are the most important characteristics of an optical Fourier transform processor. We use this abstract model to reason about the computational properties of the physical systems it describes. We define a grammar for our model's instruction language, and use it to write algorithms for well-known filtering and correlation techniques. We also suggest suitable computational complexity measures that could be used to analyze any coherent optical information processing technique, described with the language, for efficiency. Our choice of instruction language allows us to argue that algorithms describable with this model should have optical implementations that do not require a digital electronic computer to act as a master unit. Through simulation of a well known model of computation from computer theory we investigate the general-purpose capabilities of analog optical processors.

  15. Communication Efficient Multi-processor FFT

    Science.gov (United States)

    Lennart Johnsson, S.; Jacquemin, Michel; Krawitz, Robert L.

    1992-10-01

    Computing the fast Fourier transform on a distributed memory architecture by a direct pipelined radix-2, a bi-section, or a multisection algorithm, all yield the same communications requirement, if communication for all FFT stages can be performed concurrently, the input data is in normal order, and the data allocation is consecutive. With a cyclic data allocation, or bit-reversed input data and a consecutive allocation, multi-sectioning offers a reduced communications requirement by approximately a factor of two. For a consecutive data allocation, normal input order, a decimation-in-time FFT requires that P/ N + d-2 twiddle factors be stored for P elements distributed evenly over N processors, and the axis that is subject to transformation be distributed over 2 d processors. No communication of twiddle factors is required. The same storage requirements hold for a decimation-in-frequency FFT, bit-reversed input order, and consecutive data allocation. The opposite combination of FFT type and data ordering requires a factor of log 2N more storage for N processors. The peak performance for a Connection Machine system CM-200 implementation is 12.9 Gflops/s in 32-bit precision, and 10.7 Gflops/s in 64-bit precision for unordered transforms local to each processor. The corresponding execution rates for ordered transforms are 11.1 Gflops/s and 8.5 Gflops/s, respectively. For distributed one- and two-dimensional transforms the peak performance for unordered transforms exceeds 5 Gflops/s in 32-bit precision and 3 Gflops/s in 64-bit precision. Three-dimensional transforms execute at a slightly lower rate. Distributed ordered transforms execute at a rate of about {1}/{2}to {2}/{3} of the unordered transforms.

  16. Breadboard Signal Processor for Arraying DSN Antennas

    Science.gov (United States)

    Jongeling, Andre; Sigman, Elliott; Chandra, Kumar; Trinh, Joseph; Soriano, Melissa; Navarro, Robert; Rogstad, Stephen; Goodhart, Charles; Proctor, Robert; Jourdan, Michael; hide

    2008-01-01

    A recently developed breadboard version of an advanced signal processor for arraying many antennas in NASA s Deep Space Network (DSN) can accept inputs in a 500-MHz-wide frequency band from six antennas. The next breadboard version is expected to accept inputs from 16 antennas, and a following developed version is expected to be designed according to an architecture that will be scalable to accept inputs from as many as 400 antennas. These and similar signal processors could also be used for combining multiple wide-band signals in non-DSN applications, including very-long-baseline interferometry and telecommunications. This signal processor performs functions of a wide-band FX correlator and a beam-forming signal combiner. [The term "FX" signifies that the digital samples of two given signals are fast Fourier transformed (F), then the fast Fourier transforms of the two signals are multiplied (X) prior to accumulation.] In this processor, the signals from the various antennas are broken up into channels in the frequency domain (see figure). In each frequency channel, the data from each antenna are correlated against the data from each other antenna; this is done for all antenna baselines (that is, for all antenna pairs). The results of the correlations are used to obtain calibration data to align the antenna signals in both phase and delay. Data from the various antenna frequency channels are also combined and calibration corrections are applied. The frequency-domain data thus combined are then synthesized back to the time domain for passing on to a telemetry receiver

  17. A post-processor for Gurmukhi OCR

    Indian Academy of Sciences (India)

    G S Lehal; Chandan Singh

    2002-02-01

    A post-processing system for OCR of Gurmukhi script has been developed. Statistical information of Punjabi language syllable combinations, corpora look-up and certain heuristics based on Punjabi grammar rules have been combined to design the post-processor. An improvement of 3% in recognition rate, from 94.35% to 97.34%, has been reported on clean images using the post-processing techniques.

  18. Modules for Pipelined Mixed Radix FFT Processors

    Directory of Open Access Journals (Sweden)

    Anatolij Sergiyenko

    2016-01-01

    Full Text Available A set of soft IP cores for the Winograd r-point fast Fourier transform (FFT is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by r times. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.

  19. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  20. Intelligent trigger processor for the crystal box

    CERN Document Server

    Sanders, G H; Cooper, M D; Hart, G W; Hoffman, C M; Hogan, G E; Hughes, E B; Matis, H S; Rolfe, J; Sandberg, V D; Williams, R A; Wilson, S; Zeman, H

    1981-01-01

    A large solid angle angular modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor-changing decays of the muon. A beam of up to 10/sup 6/ muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor. Further reduction to <1 Hz is achieved by a microprocessor-based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic logic. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex ...

  1. Software-Reconfigurable Processors for Spacecraft

    Science.gov (United States)

    Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

    2005-01-01

    A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

  2. Issue Mechanism for Embedded Simultaneous Multithreading Processor

    Science.gov (United States)

    Zang, Chengjie; Imai, Shigeki; Frank, Steven; Kimura, Shinji

    Simultaneous Multithreading (SMT) technology enhances instruction throughput by issuing multiple instructions from multiple threads within one clock cycle. For in-order pipeline to each thread, SMT processors can provide large number of issued instructions close to or surpass than using out-of-order pipeline. In this work, we show an efficient issue logic for predicated instruction sequence with the parallel flag in each instruction, where the predicate register based issue control is adopted and the continuous instructions with the parallel flag of ‘0’ are executed in parallel. The flag is pre-defined by a compiler. Instructions from different threads are issued based on the round-robin order. We also introduce an Instruction Queue skip mechanism for thread if the queue is empty. Using this kind of issue logic, we designed a 6 threads, 7-stage, in-order pipeline processor. Based on this processor, we compare round-robin issue policy (RR(T1-Tn)) with other policies: thread one always has the highest priority (PR(T1)) and thread one or thread n has the highest priority in turn (PR(T1-Tn)). The results show that RR(T1-Tn) policy outperforms others and PR(T1-Tn) is almost the same to RR(T1-Tn) from the point of view of the issued instructions per cycle.

  3. Efficient searching and sorting applications using an associative array processor

    Science.gov (United States)

    Pace, W.; Quinn, M. J.

    1978-01-01

    The purpose of this paper is to describe a method of searching and sorting data by using some of the unique capabilities of an associative array processor. To understand the application, the associative array processor is described in detail. In particular, the content addressable memory and flip network are discussed because these two unique elements give the associative array processor the power to rapidly sort and search. A simple alphanumeric sorting example is explained in hardware and software terms. The hardware used to explain the application is the STARAN (Goodyear Aerospace Corporation) associative array processor. The software used is the APPLE (Array Processor Programming Language) programming language. Some applications of the array processor are discussed. This summary tries to differentiate between the techniques of the sequential machine and the associative array processor.

  4. External costs related to power production technologies. ExternE national implementation for Denmark

    Energy Technology Data Exchange (ETDEWEB)

    Schleisner, L.; Sieverts Nielsen, P. [eds.

    1997-12-01

    The objective of the ExternE National Implementation project has been to establish a comprehensive and comparable set of data on externalities of power generation for all EU member states and Norway. The tasks include the application of the ExternE methodology to the most important fuel cycles for each country as well as to update the already existing results, to aggregate these site- and technology-specific results to more general figures. The current report covers the detailed information concerning the ExternE methodology. Importance is attached to the computer system used in the project and the assessment of air pollution effects on health, materials and ecological effects. Also the assessment of global warming damages are described. Finally the report covers the detailed information concerning the national implementation for Denmark for an offshore wind farm and a wind farm on land, a decentralised CHP plant based on natural gas and a decentralised CHP plant base on biogas. (au) EU-JOULE 3. 79 tabs., 11 ills., 201 refs.

  5. Merged ozone profiles from four MIPAS processors

    Science.gov (United States)

    Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

    2017-04-01

    The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

  6. Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Dong; Giampapa, Mark; Heidelberger, Philip; Ohmacht, Martin; Satterfield, David L; Steinmacher-Burow, Burkhard; Sugavanam, Krishnan

    2013-05-21

    A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

  7. MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

    Energy Technology Data Exchange (ETDEWEB)

    Barhen, Jacob [ORNL; Kerekes, Ryan A [ORNL; ST Charles, Jesse Lee [ORNL; Buckner, Mark A [ORNL

    2008-01-01

    performs the matrix-vector multiplications, where the nominal matrix size is 256x256. The system clock is 125MHz. At each clock cycle, 128K multiply-and-add operations per second (OPS) are carried out, which yields a peak performance of 16 TeraOPS. IBM Cell Broadband Engine. The Cell processor is the extraordinary resulting product of 5 years of sustained, intensive R&D collaboration (involving over $400M investment) between IBM, Sony, and Toshiba. Its architecture comprises one multithreaded 64-bit PowerPC processor element (PPE) with VMX capabilities and two levels of globally coherent cache, and 8 synergistic processor elements (SPEs). Each SPE consists of a processor (SPU) designed for streaming workloads, local memory, and a globally coherent direct memory access (DMA) engine. Computations are performed in 128-bit wide single instruction multiple data streams (SIMD). An integrated high-bandwidth element interconnect bus (EIB) connects the nine processors and their ports to external memory and to system I/O. The Applied Software Engineering Research (ASER) Group at the ORNL is applying the Cell to a variety of text and image analysis applications. Research on Cell-equipped PlayStation3 (PS3) consoles has led to the development of a correlation-based image recognition engine that enables a single PS3 to process images at more than 10X the speed of state-of-the-art single-core processors. NVIDIA Graphics Processing Units. The ASER group is also employing the latest NVIDIA graphical processing units (GPUs) to accelerate clustering of thousands of text documents using recently developed clustering algorithms such as document flocking and affinity propagation.

  8. External Otitis (Swimmer's Ear)

    Science.gov (United States)

    ... to Pneumococcal Vaccine Additional Content Medical News External Otitis (Swimmer's Ear) By Bradley W. Kesser, MD, Associate ... the Outer Ear Ear Blockages Ear Tumors External Otitis (Swimmer's Ear) Malignant External Otitis Perichondritis External otitis ...

  9. Fuel economy and range estimates for fuel cell powered automobiles

    Energy Technology Data Exchange (ETDEWEB)

    Steinbugler, M.; Ogden, J. [Princeton Univ., NJ (United States)

    1996-12-31

    While a number of automotive fuel cell applications have been demonstrated, including a golf cart, buses, and a van, these systems and others that have been proposed have utilized differing configurations ranging from direct hydrogen fuel cell-only power plants to fuel cell/battery hybrids operating on reformed methanol. To date there is no clear consensus on which configuration, from among the possible combinations of fuel cell, peaking device, and fuel type, is the most likely to be successfully commercialized. System simplicity favors direct hydrogen fuel cell vehicles, but infrastructure is lacking. Infrastructure favors a system using a liquid fuel with a fuel processor, but system integration and performance issues remain. A number of studies have analyzed particular configurations on either a system or vehicle scale. The objective of this work is to estimate, within a consistent framework, fuel economies and ranges for a variety of configurations using flexible models with the goal of identifying the most promising configurations and the most important areas for further research and development.

  10. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  11. Message-Driven Processor Architecture Version 11

    Science.gov (United States)

    1988-08-18

    UNCLASSIFIED . $CUUIT. v A$SIf9CAYON Or IMIS SAGE ’Whlken Dese E,...’lld) __ REPO_Or T CU NT PAGE ateREAD INSTRUCTIONS REPORT DOCUmtNTATION PAGE...fields instead of 2. This reflects the change in machine topology from 2D to 3D . Also, the NNR is no longer set to zero on a reset; it is left to...an X field, a Y field and a Z field indicating the position of the node in the 3D network grid. Its value identifies the processor on the network and

  12. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  13. Active Interrogation for Spent Fuel

    Energy Technology Data Exchange (ETDEWEB)

    Swinhoe, Martyn Thomas [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Dougan, Arden [National Nuclear Security Administration (NNSA), Washington, DC (United States)

    2015-11-05

    The DDA instrument for nuclear safeguards is a fast, non-destructive assay, active neutron interrogation technique using an external 14 MeV DT neutron generator for characterization and verification of spent nuclear fuel assemblies.

  14. Active Interrogation for Spent Fuel

    Energy Technology Data Exchange (ETDEWEB)

    Swinhoe, Martyn Thomas [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Dougan, Arden [National Nuclear Security Administration (NNSA), Washington, DC (United States)

    2015-11-05

    The DDA instrument for nuclear safeguards is a fast, non-destructive assay, active neutron interrogation technique using an external 14 MeV DT neutron generator for characterization and verification of spent nuclear fuel assemblies.

  15. Hydrogen as a fuel for fuel cell vehicles: A technical and economic comparison

    Energy Technology Data Exchange (ETDEWEB)

    Ogden, J.; Steinbugler, M.; Kreutz, T. [Princeton Univ., NJ (United States). Center for Energy and Environmental Studies

    1997-12-31

    All fuel cells currently being developed for near term use in vehicles require hydrogen as a fuel. Hydrogen can be stored directly or produced onboard the vehicle by reforming methanol, ethanol or hydrocarbon fuels derived from crude oil (e.g., Diesel, gasoline or middle distillates). The vehicle design is simpler with direct hydrogen storage, but requires developing a more complex refueling infrastructure. In this paper, the authors compare three leading options for fuel storage onboard fuel cell vehicles: compressed gas hydrogen storage; onboard steam reforming of methanol; onboard partial oxidation (POX) of hydrocarbon fuels derived from crude oil. Equilibrium, kinetic and heat integrated system (ASPEN) models have been developed to estimate the performance of onboard steam reforming and POX fuel processors. These results have been incorporated into a fuel cell vehicle model, allowing us to compare the vehicle performance, fuel economy, weight, and cost for various fuel storage choices and driving cycles. A range of technical and economic parameters were considered. The infrastructure requirements are also compared for gaseous hydrogen, methanol and hydrocarbon fuels from crude oil, including the added costs of fuel production, storage, distribution and refueling stations. Considering both vehicle and infrastructure issues, the authors compare hydrogen to other fuel cell vehicle fuels. Technical and economic goals for fuel cell vehicle and hydrogen technologies are discussed. Potential roles for hydrogen in the commercialization of fuel cell vehicles are sketched.

  16. The ISS Water Processor Catalytic Reactor as a Post Processor for Advanced Water Reclamation Systems

    Science.gov (United States)

    Nalette, Tim; Snowdon, Doug; Pickering, Karen D.; Callahan, Michael

    2007-01-01

    Advanced water processors being developed for NASA s Exploration Initiative rely on phase change technologies and/or biological processes as the primary means of water reclamation. As a result of the phase change, volatile compounds will also be transported into the distillate product stream. The catalytic reactor assembly used in the International Space Station (ISS) water processor assembly, referred to as Volatile Removal Assembly (VRA), has demonstrated high efficiency oxidation of many of these volatile contaminants, such as low molecular weight alcohols and acetic acid, and is considered a viable post treatment system for all advanced water processors. To support this investigation, two ersatz solutions were defined to be used for further evaluation of the VRA. The first solution was developed as part of an internal research and development project at Hamilton Sundstrand (HS) and is based primarily on ISS experience related to the development of the VRA. The second ersatz solution was defined by NASA in support of a study contract to Hamilton Sundstrand to evaluate the VRA as a potential post processor for the Cascade Distillation system being developed by Honeywell. This second ersatz solution contains several low molecular weight alcohols, organic acids, and several inorganic species. A range of residence times, oxygen concentrations and operating temperatures have been studied with both ersatz solutions to provide addition performance capability of the VRA catalyst.

  17. Retargetable Code Generation based on Structural Processor Descriptions

    OpenAIRE

    Leupers, Rainer; Marwedel, Peter

    1998-01-01

    Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insufficient, because they do not provide flexibility with respect to different target processors and also suffer from inferior code quality....

  18. User microprogrammable processors for high data rate telemetry preprocessing

    Science.gov (United States)

    Pugsley, J. H.; Ogrady, E. P.

    1973-01-01

    The use of microprogrammable processors for the preprocessing of high data rate satellite telemetry is investigated. The following topics are discussed along with supporting studies: (1) evaluation of commercial microprogrammable minicomputers for telemetry preprocessing tasks; (2) microinstruction sets for telemetry preprocessing; and (3) the use of multiple minicomputers to achieve high data processing. The simulation of small microprogrammed processors is discussed along with examples of microprogrammed processors.

  19. On-board hydrogen generation for transport applications: the HotSpot™ methanol processor

    Science.gov (United States)

    Edwards, Neil; Ellis, Suzanne R.; Frost, Jonathan C.; Golunski, Stanislaw E.; van Keulen, Arjan N. J.; Lindewald, Nicklas G.; Reinkingh, Jessica G.

    In the absence of a hydrogen infrastructure, development of effective on-board fuel processors is likely to be critical to the commercialisation of fuel-cell cars. The HotSpot™ reactor converts methanol, water and air in a single compact catalyst bed into a reformate containing mainly CO2 and hydrogen (and unreacted nitrogen). The process occurs by a combination of exothermic partial oxidation and endothermic steam reforming of methanol, to produce 750 l of hydrogen per hour from a 245-cm3 reactor. The relative contribution of each reaction can be tuned to match the system requirements at a given time. Scale-up is achieved by the parallel combination of the required number of individual HotSpot reactors, which are fed from a central manifold. Using this modular design, the start-up and transient characteristics of a large fuel-processor are identical to that of a single reactor. When vaporised liquid feed and air are introduced into cold reactors, 100% output is achieved in 50 s; subsequent changes in throughput result in instantaneous changes in output. Surplus energy within the fuel-cell powertrain can be directed to the manifold, where it can be used to vaporise the liquid feeds and so promote steam reforming, resulting in high system efficiency. The small amount of CO that is produced by the HotSpot reactions is attenuated to <10 ppm by a catalytic clean-up unit. The HotSpot concept and CO clean-up strategy are not limited to the processing of methanol, but are being applied to other organic fuels.

  20. Variants of closing the nuclear fuel cycle

    Science.gov (United States)

    Andrianova, E. A.; Davidenko, V. D.; Tsibulskiy, V. F.; Tsibulskiy, S. V.

    2015-12-01

    Influence of the nuclear energy structure, the conditions of fuel burnup, and accumulation of new fissile isotopes from the raw isotopes on the main parameters of a closed fuel cycle is considered. The effects of the breeding ratio, the cooling time of the spent fuel in the external fuel cycle, and the separation of the breeding area and the fissile isotope burning area on the parameters of the fuel cycle are analyzed.

  1. Compact Single-Stage Fuel Processor for PEM Fuel Cells. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Rhine, Wendell E.; Ye, Neng

    2000-01-01

    Based on observations during the steam reforming of ethanol, the authors conclude that carbon was forming in the steam generator due to the thermal decomposition of ethanol. Since ethanol is being thermally decomposed, they were operating the steam generator at too high of a temperature. The thermal degradation of ethanol was confirmed by using a GC with a flame ionization detector. They observed trace amounts of additional hydrocarbons other than methane in the effluent which we assume maybe ethane and ethylene. We identified the operating conditions that allowed us to steam reform ethanol for an acceptable amount of time. These conditions were a steam temperature of 200 C and a wall temperature of 400 C at the center of the reactor. The calculated ratios of CO{sub 2}/CO indicate that we can lower the potential for carbon deposition from the Boudouard further by reducing the pressure.

  2. MPC Related Computational Capabilities of ARMv7A Processors

    DEFF Research Database (Denmark)

    Frison, Gianluca; Jørgensen, John Bagterp

    2015-01-01

    In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...

  3. Dynamically Reconfigurable Processor for Floating Point Arithmetic

    Directory of Open Access Journals (Sweden)

    S. Anbumani,

    2014-01-01

    Full Text Available Recently, development of embedded processors is toward miniaturization and energy saving for ecology. On the other hand, high performance arithmetic circuits are required in a lot of application in science and technology. Dynamically reconfigurable processors have been developed to meet these requests. They can change circuit configuration according to instructions in program instantly during operations.This paper describes, a dynamically reconfigurable circuit for floating-point arithmetic is proposed. The arithmetic circuit consists of two single precision floating-point arithmetic circuits. It performs double precision floating-point arithmetic by reconfiguration. Dynamic reconfiguration changes circuit construction at one clock cycle during operation without stopping circuits. It enables reconfiguration of circuits in a few nano seconds. The proposed circuit is reconfigured in two modes. In first mode it performs one double precision floating-point arithmetic or else the circuit will perform two parallel operations of single precision floating-point arithmetic. The new system design reduces implementation area by reconfiguring common parts of each operation. It also increases the processing speed with a very little number of clocks.

  4. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  5. Speed Scaling on Parallel Processors with Migration

    CERN Document Server

    Angel, Eric; Kacem, Fadi; Letsios, Dimitrios

    2011-01-01

    We study the problem of scheduling a set of jobs with release dates, deadlines and processing requirements (or works), on parallel speed-scaled processors so as to minimize the total energy consumption. We consider that both preemption and migration of jobs are allowed. An exact polynomial-time algorithm has been proposed for this problem, which is based on the Ellipsoid algorithm. Here, we formulate the problem as a convex program and we propose a simpler polynomial-time combinatorial algorithm which is based on a reduction to the maximum flow problem. Our algorithm runs in $O(nf(n)logP)$ time, where $n$ is the number of jobs, $P$ is the range of all possible values of processors' speeds divided by the desired accuracy and $f(n)$ is the complexity of computing a maximum flow in a layered graph with O(n) vertices. Independently, Albers et al. \\cite{AAG11} proposed an $O(n^2f(n))$-time algorithm exploiting the same relation with the maximum flow problem. We extend our algorithm to the multiprocessor speed scal...

  6. Coordinated Energy Management in Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Indrani Paul

    2014-01-01

    Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

  7. Broadband monitoring simulation with massively parallel processors

    Science.gov (United States)

    Trubetskov, Mikhail; Amotchkina, Tatiana; Tikhonravov, Alexander

    2011-09-01

    Modern efficient optimization techniques, namely needle optimization and gradual evolution, enable one to design optical coatings of any type. Even more, these techniques allow obtaining multiple solutions with close spectral characteristics. It is important, therefore, to develop software tools that can allow one to choose a practically optimal solution from a wide variety of possible theoretical designs. A practically optimal solution provides the highest production yield when optical coating is manufactured. Computational manufacturing is a low-cost tool for choosing a practically optimal solution. The theory of probability predicts that reliable production yield estimations require many hundreds or even thousands of computational manufacturing experiments. As a result reliable estimation of the production yield may require too much computational time. The most time-consuming operation is calculation of the discrepancy function used by a broadband monitoring algorithm. This function is formed by a sum of terms over wavelength grid. These terms can be computed simultaneously in different threads of computations which opens great opportunities for parallelization of computations. Multi-core and multi-processor systems can provide accelerations up to several times. Additional potential for further acceleration of computations is connected with using Graphics Processing Units (GPU). A modern GPU consists of hundreds of massively parallel processors and is capable to perform floating-point operations efficiently.

  8. Efficiency of Cache Mechanism for Network Processors

    Institute of Scientific and Technical Information of China (English)

    XU Bo; CHANG Jian; HUANG Shimeng; XUE Yibo; LI Jun

    2009-01-01

    With the explosion of network bandwidth and the ever-changing requirements for diverse net-work-based applications, the traditional processing architectures, i.e., general purpose processor (GPP) and application specific integrated circuits (ASIC) cannot provide sufficient flexibility and high performance at the same time. Thus, the network processor (NP) has emerged as an altemative to meet these dual demands for today's network processing. The NP combines embedded multi-threaded cores with a dch memory hierarchy that can adapt to different networking circumstances when customized by the application developers. In to-day's NP architectures, muitithreading prevails over cache mechanism, which has achieved great success in GPP to hide memory access latencies. This paper focuses on the efficiency of the cache mechanism in an NP. Theoretical timing models of packet processing are established for evaluating cache efficiency and experi-ments are performed based on real-life network backbone traces. Testing results show that an improvement of neady 70% can be gained in throughput with assistance from the cache mechanism. Accordingly, the cache mechanism is still efficient and irreplaceable in network processing, despite the existing of multithreading.

  9. The ATLAS Level-1 Central Trigger Processor

    CERN Document Server

    Pauly, T; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Spiwoks, R; Torga-Teixeira, R; Wengler, T; 14th IEEE-NPSS Real Time Conference 2005

    2005-01-01

    ATLAS is a multi-purpose particle physics detector at CERN’s Large Hadron Collider where two pulsed beams of protons are brought to collision at very high energy. There are collisions every 25 ns, corresponding to a rate of 40 MHz. A three-level trigger system reduces this rate to about 200 Hz while keeping bunch crossings which potentially contain interesting processes. The Level-1 trigger, implemented in electronics and firmware, makes an initial selection in under 2.5 us with an output rate of less than 100 kHz. A key element of this is the Central Trigger Processor (CTP) which combines trigger information from the calorimeter and muon trigger processors to make the final Level-1 accept decision in under 100 ns on the basis of lists of selection criteria, implemented as a trigger menu. Timing and trigger signals are fanned out to all sub-detectors, while busy signals from all sub-detector read-out systems are collected and fed into the CTP in order to throttle the generation of Level-1 triggers.

  10. Molten carbonate fuel cell

    Science.gov (United States)

    Kaun, T.D.; Smith, J.L.

    1986-07-08

    A molten electrolyte fuel cell is disclosed with an array of stacked cells and cell enclosures isolating each cell except for access to gas manifolds for the supply of fuel or oxidant gas or the removal of waste gas. The cell enclosures collectively provide an enclosure for the array and effectively avoid the problems of electrolyte migration and the previous need for compression of stack components. The fuel cell further includes an inner housing about and in cooperation with the array enclosure to provide a manifold system with isolated chambers for the supply and removal of gases. An external insulated housing about the inner housing provides thermal isolation to the cell components.

  11. Design of a dedicated processor for AC motor control implemented in a low cost FPGA

    DEFF Research Database (Denmark)

    Jakobsen, Uffe; Matzen, Torben N.

    2008-01-01

    of drives. Furthermore the softcore processor is designed with a system for plug in of external logic. Doing so shortens development time, since functionality is simply added to or removed from the softcore. The designer can then choose between resource usage on the FPGA and execution speed in more degrees....... The approach is tested for two different motor types, synchronousand hybrid switched reluctance motors, using a Spartan 3E FPGA. The impact of having ADC-communication in VHDL versus in assembler is also presented....

  12. Integrated Information Support System (IISS). Volume 5. Common Data Model Subsystem. Part 6. NDDL Processor Product Specification. Sections 1.0 through 3.10.8 CPFNXT.

    Science.gov (United States)

    1985-11-01

    Conceptual Schema to External Schema Translation or Mapping program. Conceptual Schema: (CS) Common Data Model Processor: ( CIDP ) Common Data Model: (CDM...statement was not written into the include file Itself. The most common reason for this is that the Include file comes from system libraries that were not

  13. GA103 a microprogrammable processor for online filtering

    CERN Document Server

    Calzas, A; Danon, G

    1981-01-01

    GA103 is a 16 bit microprogrammable processor, which emulates the PDP 11 instruction set. It is based on the Am2900 slices. It allows user- implemented microinstructions and addition of hardwired processors. It will perform online filtering tasks in the NA14 experiment at CERN, based on the reconstruction of transverse momentum of photons detected in a lead glass calorimeter. (3 refs).

  14. Expert System Constant False Alarm Rate (CFAR) Processor

    Science.gov (United States)

    2006-09-01

    Processor has been developed on a Sun Sparc Station 4/470 using a commercial-off-the-shelf software development package called G2 by Gensym Corporation...size of the training data set. A prototype expert system CFAR Processor has been presented which applies artificial intelligence to CFAR detection

  15. Digital Signal Processor System for AC Power Drivers

    OpenAIRE

    Ovidiu Neamtu

    2009-01-01

    DSP (Digital Signal Processor) is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulation)circuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  16. Digital Signal Processor System for AC Power Drivers

    Directory of Open Access Journals (Sweden)

    Ovidiu Neamtu

    2009-10-01

    Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  17. High speed matrix processors using floating point representation

    Energy Technology Data Exchange (ETDEWEB)

    Birkner, D.A.

    1980-01-01

    The author describes the architecture of a high-speed matrix processor which uses a floating-point format for data representation. It is shown how multipliers and other LSI devices are used in the design to obtain the high speed of the processor.

  18. Temporal Partitioning and Multi-Processor Scheduling for Reconfigurable Architectures

    DEFF Research Database (Denmark)

    Popp, Andreas; Le Moullec, Yannick; Koch, Peter

    This poster presentation outlines a proposed framework for handling mapping of signal processing applications to heterogeneous reconfigurable architectures. The methodology consists of an extension to traditional multi-processor scheduling by creating a separate HW track for generation of groups...... of tasks that are handled similarly to SW processes in a traditional multi-processor scheduling context....

  19. Message Passing on a Time-predictable Multicore Processor

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Puffitsch, Wolfgang; Schoeberl, Martin

    2015-01-01

    Real-time systems need time-predictable computing platforms. For a multicore processor to be time-predictable, communication between processor cores needs to be time-predictable as well. This paper presents a time-predictable message-passing library for such a platform. We show how to build up...

  20. A Simple and Affordable TTL Processor for the Classroom

    Science.gov (United States)

    Feinberg, Dave

    2007-01-01

    This paper presents a simple 4 bit computer processor design that may be built using TTL chips for less than $65. In addition to describing the processor itself in detail, we discuss our experience using the laboratory kit and its associated machine instruction set to teach computer architecture to high school students. (Contains 3 figures and 5…

  1. Bibliographic Pattern Matching Using the ICL Distributed Array Processor.

    Science.gov (United States)

    Carroll, David M.; And Others

    1988-01-01

    Describes the use of a highly parallel array processor for pattern matching operations in a bibliographic retrieval system. The discussion covers the hardware and software features of the processor, the pattern matching algorithm used, and the results of experimental tests of the system. (37 references) (Author/CLB)

  2. Designing a dataflow processor using CλaSH

    NARCIS (Netherlands)

    Niedermeier, Anja; Wester, Rinse; Rovers, Kenneth; Baaij, Christiaan; Kuper, Jan; Smit, Gerard

    2010-01-01

    In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

  3. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  4. Signal Processor for Spring8 Linac BPM

    CERN Document Server

    Yanagida, K; Dewa, H; Hanaki, H; Hori, T; Kobayashi, T; Mizuno, A; Sasaki, S; Suzuki, S; Takashima, T; Taniushi, T; Tomizawa, H

    2001-01-01

    A signal processor of the single shot BPM system consists of a narrow-band BPF unit, a detector unit, a P/H circuit, an S/H IC and a 16-bit ADC. The BPF unit extracts a pure 2856MHz RF signal component from a BPM and makes the pulse width longer than 100ns. The detector unit that includes a demodulating logarithmic amplifier is used to detect an S-band RF amplitude. A wide dynamic range of beam current has been achieved; 0.01 ~ 3.5nC for below 100ns input pulse width, or 0.06 ~ 20mA for above 100ns input pulse width. The maximum acquisition rate with a VME system has been achieved up to 1kHz.

  5. Efficient quantum walk on a quantum processor

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.

    2016-05-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor.

  6. Scaling the ion trap quantum processor.

    Science.gov (United States)

    Monroe, C; Kim, J

    2013-03-08

    Trapped atomic ions are standards for quantum information processing, serving as quantum memories, hosts of quantum gates in quantum computers and simulators, and nodes of quantum communication networks. Quantum bits based on trapped ions enjoy a rare combination of attributes: They have exquisite coherence properties, they can be prepared and measured with nearly 100% efficiency, and they are readily entangled with each other through the Coulomb interaction or remote photonic interconnects. The outstanding challenge is the scaling of trapped ions to hundreds or thousands of qubits and beyond, at which scale quantum processors can outperform their classical counterparts in certain applications. We review the latest progress and prospects in that effort, with the promise of advanced architectures and new technologies, such as microfabricated ion traps and integrated photonics.

  7. Efficient quantum walk on a quantum processor.

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L; Wang, Jingbo B; Matthews, Jonathan C F

    2016-05-05

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor.

  8. Water Processor and Oxygen Generation Assembly

    Science.gov (United States)

    Bedard, John

    1997-01-01

    This report documents the results of the tasks which initiated efforts on design issues relating to the Water Processor (WP) and the Oxygen Generation Assembly (OGA) Flight Hardware for the International Space Station. This report fulfills the Statement of Work deliverables requirement for contract H-29387D. The following lists the tasks required by contract H-29387D: (1) HSSSI shall coordinate a detailed review of WP/OGA Flight Hardware program requirements with personnel from MSFC to identify requirements that can be eliminated without affecting the technical integrity of the WP/OGA Hardware; (2) HSSSI shall conduct the technical interchanges with personnel from MSFC to resolve design issues related to WP/OGA Flight Hardware; (3) HSSSI will initiate discussions with Zellwegger Analytics, Inc. to address design issues related to WP and PCWQM interfaces.

  9. Face feature processor on mobile service robot

    Science.gov (United States)

    Ahn, Ho Seok; Park, Myoung Soo; Na, Jin Hee; Choi, Jin Young

    2005-12-01

    In recent years, many mobile service robots have been developed. These robots are different from industrial robots. Service robots were confronted to unexpected changes in the human environment. So many capabilities were needed to service mobile robot, for example, the capability to recognize people's face and voice, the capability to understand people's conversation, and the capability to express the robot's thinking etc. This research considered face detection, face tracking and face recognition from continuous camera image. For face detection module, it used CBCH algorithm using openCV library from Intel Corporation. For face tracking module, it used the fuzzy controller to control the pan-tilt camera movement smoothly with face detection result. A PCA-FX, which adds class information to PCA, was used for face recognition module. These three procedures were called face feature processor, which were implemented on mobile service robot OMR to verify.

  10. QERx- A Faster than Real-Time Emulator for Space Processors

    Science.gov (United States)

    Carvalho, B.; Pidgeon, A.; Robinson, P.

    2012-08-01

    Developing software for space systems is challenging. Especially because, in order to be sure it can cope with the harshness of the environment and the imperative requirements and constrains imposed by the platform were it will run, it needs to be tested exhaustively. Software Validation Facilities (SVF) are known to the industry and developers, and provide the means to run the On-Board Software (OBSW) in a realistic environment, allowing the development team to debug and test the software.But the challenge is to be able to keep up with the performance of the new processors (LEON2 and LEON3), which need to be emulated within the SVF. Such processor emulators are also used in Operational Simulators, used to support mission preparation and train mission operators. These simulators mimic the satellite and its behaviour, as realistically as possible. For test/operational efficiency reasons and because they will need to interact with external systems, both these uses cases require the processor emulators to provide real-time, or faster, performance.It is known to the industry that the performance of previously available emulators is not enough to cope with the performance of the new processors available in the market. SciSys approached this problem with dynamic translation technology trying to keep costs down by avoiding a hardware solution and keeping the integration flexibility of full software emulation.SciSys presented “QERx: A High Performance Emulator for Software Validation and Simulations” [1], in a previous DASIA event. Since then that idea has evolved and QERx has been successfully validated. SciSys is now presenting QERx as a product that can be tailored to fit different emulation needs. This paper will present QERx latest developments and current status.

  11. Structure and Control Strategies of Fuel Cell Vehicle

    Institute of Scientific and Technical Information of China (English)

    宋建国; 张承宁; 孙逢春; 钟秋海

    2004-01-01

    The structure and kinds of the fuel cell vehicle (FCV) and the mathematical model of the fuel cell processor are discussed in detail. FCV includes many parts: the fuel cell thermal and water management, fuel supply, air supply and distribution, AC motor drive, main and auxiliary power management, and overall vehicle control system. So it requires different kinds of control strategies, such as the PID method, zero-pole method, optimal control method, fuzzy control and neural network control. Along with the progress of control method, the fuel cell vehicle's stability and reliability is up-and-up. Experiment results show FCV has high energy efficiency.

  12. Conversion via software of a simd processor into a mimd processor

    Energy Technology Data Exchange (ETDEWEB)

    Guzman, A.; Gerzso, M.; Norkin, K.B.; Vilenkin, S.Y.

    1983-01-01

    A method is described which takes a pure LISP program and automatically decomposes it via automatic parallelization into several parts, one for each processor of an SIMD architecture. Each of these parts is a different execution flow, i.e., a different program. The execution of these different programs by an SIMD architecture is examined. The method has been developed in some detail for the PS-2000, an SIMD Soviet multiprocessor, making it behave like AHR, a Mexican MIMD multi-microprocessor. Both the PS-2000 and AHR execute a pure LISP program in parallel; its decomposition into >n> pieces, their synchronization, scheduling, etc., are performed by the system (hardware and software). In order to achieve simultaneous execution of different programs in an SIMD processor, the method uses a scheme of node scheduling and node exportation. 14 references.

  13. Floating-point processor for INTEL 8080A microprocessor systems

    Energy Technology Data Exchange (ETDEWEB)

    Bairstow, R.; Barlow, J.; Jires, M.; Waters, M.

    1982-03-01

    An A.M.D. 9511 Floating Point Processor has been interfaced to the Rutherford Laboratory Bubble Chamber Group's microcomputers. These computers are based on the INTEL 8080A microprocessor. The interface uses a memory mapped I/O technique to ensure rapid transfer of arguments between processors. The A.M.D. 9511 acts as a slave processor to the INTEL 8080A system. The 8080 processor is held in WAIT status until completion of the A.M.D. operation. A software Macro Processor has been written to effectively extend the basic INTEL 8080A instruction set to include the full range of A.M.D. 9511 instructions.

  14. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  15. An Efficient Graph-Coloring Algorithm for Processor Allocation

    Directory of Open Access Journals (Sweden)

    Mohammed Hasan Mahafzah

    2013-06-01

    Full Text Available This paper develops an efficient exact graph-coloring algorithm based on Maximum Independent Set (MIS for allocating processors in distributed systems. This technique represents the allocated processors in specific time in a fully connected graph and prevents each processor in multiprocessor system to be assigned to more than one process at a time. This research uses a sequential technique to distribute processes among processors. Moreover, the proposed method has been constructed by modifying the FMIS algorithm. The proposed algorithm has been programmed in Visual C++ and implemented on an Intel core i7. The experiments show that the proposed algorithm gets better performance in terms of CPU utilization, and minimum time for of graph coloring, comparing with the latest FMIS algorithm. The proposed algorithm can be developed to detect defected processor in the system.

  16. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  17. PERFORMANCE EVALUATION OF DIRECT PROCESSOR ACCESS FOR NON DEDICATED SERVER

    Directory of Open Access Journals (Sweden)

    P. S. BALAMURUGAN

    2010-10-01

    Full Text Available The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. These type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine which can parallel act as a non dedicated server and a client machine or it can be made to switch and act as client or server.

  18. Explore the Performance of the ARM Processor Using JPEG

    Directory of Open Access Journals (Sweden)

    A.D. Jadhav

    2010-01-01

    Full Text Available Recently, the evolution of embedded systems has shown a strong trend towards application- specific, single- chip solutions. The ARM processor core is a leading RISC processor architecture in the embedded domain. The ARM family of processors supports a unique feature of code size reduction. In this paper it is illustrated using an embedded platform trying to design an image encoder, more specifically a JPEG encoder using ARM7TDMI processor. Here gray scale image is used and it is coded by using keil software and same procedure is repeated by using MATLAB software for compare the results with standard one. Successfully putting a new application of JPEG on ARM7 processor.

  19. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  20. Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

    Science.gov (United States)

    Tomkins, James L.; Camp, William J.

    2009-03-17

    A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

  1. Review on studies for external cost of nuclear power generation

    Energy Technology Data Exchange (ETDEWEB)

    Park, Byung Heung [Korea National University of Transportation, Chungju (Korea, Republic of); Ko, Won Il [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2015-12-15

    External cost is cost imposed on a third party when producing or consuming a good or service. Since the 1990s, the external costs of nuclear powered electricity production have been studied. Costs are a very important factor in policy decision and the external cost is considered for cost comparison on electricity production. As for nuclear fuel cycle, a chosen technology will determine the external cost. However, there has been little research on this issue. For this study, methods for external cost on nuclear power production have been surveyed and analyzed to develop an approach for evaluating external cost on nuclear fuel cycles. Before the Fukushima accident, external cost research had focused on damage costs during normal operation of a fuel cycle. However, accident cost becomes a major concern after the accident. Various considerations for external cost including accident cost have been used to different studies, and different methods have been applied corresponding to the considerations. In this study, the results of the evaluation were compared and analyzed to identify methodological applicability to the external cost estimation with nuclear fuel cycles.

  2. The External Degree.

    Science.gov (United States)

    Houle, Cyril O.

    This book examines the external degree in relation to the extremes of attitudes, myths, and data. Emphasis is placed on the emergence of the American external degree, foreign external-degree programs, the purpose of the external degree, the current scene, institutional issues, and problems of general policy. (MJM)

  3. A Methodology Proposal to Calculate the Externalities of Liquid Biofuels

    Energy Technology Data Exchange (ETDEWEB)

    Galan, A.; Gonzalez, R.; Varela, M. [Ciemat. Madrid (Spain)

    1999-05-01

    The aim of the survey is to propose a methodology to calculate the externalities associated with the liquid bio fuels cycle. The report defines the externalities from a theoretical point of view and classifies them. The reasons to value the externalities are explained as well as the existing methods. Furthermore, an evaluation of specific environmental and non-environmental externalities is also presented. The report reviews the current situation of the transport sector, considering its environmental effects and impacts. The progress made by the ExternE and ExternE-transport projects related the externalities of transport sector is assessed. Finally, the report analyses the existence of different economic instruments to internalize the external effects of the transport sector as well as other aspects of this internalization. (Author) 58 refs.

  4. First Results of an "Artificial Retina" Processor Prototype

    Science.gov (United States)

    Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John

    2016-11-01

    We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called "artificial retina algorithm", inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate.

  5. Digital optical cellular image processor (DOCIP) - Experimental implementation

    Science.gov (United States)

    Huang, K.-S.; Sawchuk, A. A.; Jenkins, B. K.; Chavel, P.; Wang, J.-M.; Weber, A. G.; Wang, C.-H.; Glaser, I.

    1993-01-01

    We demonstrate experimentally the concept of the digital optical cellular image processor architecture by implementing one processing element of a prototype optical computer that includes a 54-gate processor, an instruction decoder, and electronic input-output interfaces. The processor consists of a two-dimensional (2-D) array of 54 optical logic gates implemented by use of a liquid-crystal light valve and a 2-D array of 53 subholograms to provide interconnections between gates. The interconnection hologram is fabricated by a computer-controlled optical system.

  6. Ethernet-Enabled Power and Communication Module for Embedded Processors

    Science.gov (United States)

    Perotti, Jose; Oostdyk, Rebecca

    2010-01-01

    The power and communications module is a printed circuit board (PCB) that has the capability of providing power to an embedded processor and converting Ethernet packets into serial data to transfer to the processor. The purpose of the new design is to address the shortcomings of previous designs, including limited bandwidth and program memory, lack of control over packet processing, and lack of support for timing synchronization. The new design of the module creates a robust serial-to-Ethernet conversion that is powered using the existing Ethernet cable. This innovation has a small form factor that allows it to power processors and transducers with minimal space requirements.

  7. Scientific Computing Kernels on the Cell Processor

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Samuel W.; Shalf, John; Oliker, Leonid; Kamil, Shoaib; Husbands, Parry; Yelick, Katherine

    2007-04-04

    The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on a 3.2GHz Cell blade. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

  8. Multipurpose silicon photonics signal processor core.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

    2017-09-21

    Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

  9. Element Load Data Processor (ELDAP) Users Manual

    Science.gov (United States)

    Ramsey, John K., Jr.; Ramsey, John K., Sr.

    2015-01-01

    Often, the shear and tensile forces and moments are extracted from finite element analyses to be used in off-line calculations for evaluating the integrity of structural connections involving bolts, rivets, and welds. Usually the maximum forces and moments are desired for use in the calculations. In situations where there are numerous structural connections of interest for numerous load cases, the effort in finding the true maximum force and/or moment combinations among all fasteners and welds and load cases becomes difficult. The Element Load Data Processor (ELDAP) software described herein makes this effort manageable. This software eliminates the possibility of overlooking the worst-case forces and moments that could result in erroneous positive margins of safety and/or selecting inconsistent combinations of forces and moments resulting in false negative margins of safety. In addition to forces and moments, any scalar quantity output in a PATRAN report file may be evaluated with this software. This software was originally written to fill an urgent need during the structural analysis of the Ares I-X Interstage segment. As such, this software was coded in a straightforward manner with no effort made to optimize or minimize code or to develop a graphical user interface.

  10. Simultaneous multithreaded processor enhanced for multimedia applications

    Science.gov (United States)

    Mombers, Friederich; Thomas, Michel

    1999-12-01

    The paper proposes a new media processor architecture specifically designed to handle state-of-the-art multimedia encoding and decoding tasks. To achieve this, the architecture efficiently exploit Data-, Instruction- and Thread-Level parallelisms while continuously adapting its computational resources to reach the most appropriate parallelism level among all the concurrent encoding/decoding processes. Looking at the implementation constraints, several critical choices were adopted that solve the interconnection delay problem, lower the cache misses and pipeline stalls effects and reduce register files and memory size by adopting a clustered Simultaneous Multithreaded Architecture. We enhanced the classic model to exploit both Instruction and Data Level Parallelism through vector instructions. The vector extension is well justified for multimedia workload and improves code density, crossbars complexity, register file ports and decoding logic area while it still provides an efficient way to fully exploit a large set of functional units. An MPEG-2 encoding algorithms based on Hybrid Genetic search has been implemented that show the efficiency of the architecture to adapt its resources allocation to better fulfill the application requirements.

  11. The ATLAS fast tracker processor design

    CERN Document Server

    Volpi, Guido; Albicocco, Pietro; Alison, John; Ancu, Lucian Stefan; Anderson, James; Andari, Nansi; Andreani, Alessandro; Andreazza, Attilio; Annovi, Alberto; Antonelli, Mario; Asbah, Needa; Atkinson, Markus; Baines, J; Barberio, Elisabetta; Beccherle, Roberto; Beretta, Matteo; Biesuz, Nicolo Vladi; Blair, R E; Bogdan, Mircea; Boveia, Antonio; Britzger, Daniel; Bryant, Partick; Burghgrave, Blake; Calderini, Giovanni; Camplani, Alessandra; Cavaliere, Viviana; Cavasinni, Vincenzo; Chakraborty, Dhiman; Chang, Philip; Cheng, Yangyang; Citraro, Saverio; Citterio, Mauro; Crescioli, Francesco; Dawe, Noel; Dell'Orso, Mauro; Donati, Simone; Dondero, Paolo; Drake, G; Gadomski, Szymon; Gatta, Mauro; Gentsos, Christos; Giannetti, Paola; Gkaitatzis, Stamatios; Gramling, Johanna; Howarth, James William; Iizawa, Tomoya; Ilic, Nikolina; Jiang, Zihao; Kaji, Toshiaki; Kasten, Michael; Kawaguchi, Yoshimasa; Kim, Young Kee; Kimura, Naoki; Klimkovich, Tatsiana; Kolb, Mathis; Kordas, K; Krizka, Karol; Kubota, T; Lanza, Agostino; Li, Ho Ling; Liberali, Valentino; Lisovyi, Mykhailo; Liu, Lulu; Love, Jeremy; Luciano, Pierluigi; Luongo, Carmela; Magalotti, Daniel; Maznas, Ioannis; Meroni, Chiara; Mitani, Takashi; Nasimi, Hikmat; Negri, Andrea; Neroutsos, Panos; Neubauer, Mark; Nikolaidis, Spiridon; Okumura, Y; Pandini, Carlo; Petridou, Chariclia; Piendibene, Marco; Proudfoot, James; Rados, Petar Kevin; Roda, Chiara; Rossi, Enrico; Sakurai, Yuki; Sampsonidis, Dimitrios; Saxon, James; Schmitt, Stefan; Schoening, Andre; Shochet, Mel; Shoijaii, Jafar; Soltveit, Hans Kristian; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Swiatlowski, Maximilian J; Tang, Fukun; Taylor, Pierre Thor Elliot; Testa, Marianna; Tompkins, Lauren; Vercesi, V; Wang, Rui; Watari, Ryutaro; Zhang, Jianhong; Zeng, Jian Cong; Zou, Rui; Bertolucci, Federico

    2015-01-01

    The extended use of tracking information at the trigger level in the LHC is crucial for the trigger and data acquisition (TDAQ) system to fulfill its task. Precise and fast tracking is important to identify specific decay products of the Higgs boson or new phenomena, as well as to distinguish the contributions coming from the many collisions that occur at every bunch crossing. However, track reconstruction is among the most demanding tasks performed by the TDAQ computing farm; in fact, complete reconstruction at full Level-1 trigger accept rate (100 kHz) is not possible. In order to overcome this limitation, the ATLAS experiment is planning the installation of a dedicated processor, the Fast Tracker (FTK), which is aimed at achieving this goal. The FTK is a pipeline of high performance electronics, based on custom and commercial devices, which is expected to reconstruct, with high resolution, the trajectories of charged-particle tracks with a transverse momentum above 1 GeV, using the ATLAS inner tracker info...

  12. Food processors requirements met by radiation processing

    Science.gov (United States)

    Durante, Raymond W.

    2002-03-01

    Processing food using irradiation provides significant advantages to food producers by destroying harmful pathogens and extending shelf life without any detectable physical or chemical changes. It is expected that through increased public education, food irradiation will emerge as a viable commercial industry. Food production in most countries involves state of the art manufacturing, packaging, labeling, and shipping techniques that provides maximum efficiency and profit. In the United States, food sales are extremely competitive and profit margins small. Most food producers have heavily invested in equipment and are hesitant to modify their equipment. Meat and poultry producers in particular utilize sophisticated production machinery that processes enormous volumes of product on a continuous basis. It is incumbent on the food irradiation equipment suppliers to develop equipment that can easily merge with existing processes without requiring major changes to either the final food product or the process utilized to produce that product. Before a food producer can include irradiation as part of their food production process, they must be certain the available equipment meets their needs. This paper will examine several major requirements of food processors that will most likely have to be provided by the supplier of the irradiation equipment.

  13. Median and Morphological Specialized Processors for a Real-Time Image Data Processing

    Directory of Open Access Journals (Sweden)

    Kazimierz Wiatr

    2002-01-01

    Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

  14. Ship emissions and their externalities for Greece

    Science.gov (United States)

    Tzannatos, Ernestos

    2010-06-01

    The existing and emerging international and European policy framework for the reduction of ship exhaust emissions dictates the need to produce reliable national, regional and global inventories in order to monitor emission trends and consequently provide the necessary support for future policy making. Furthermore, the inventories of ship exhaust emissions constitute the basis upon which their external costs are estimated in an attempt to highlight the economic burden they impose upon the society and facilitate the cost-benefit analysis of the proposed emission abatement technologies, operational measures and market-based instruments prior to their implementation. The case of Greece is of particular interest mainly because the dense ship traffic within the Greek seas directly imposes the impact of its exhaust emission pollutants (NO x, SO 2 and PM) upon the highly populated, physically sensitive and culturally precious Greek coastline, as well as upon the land and seas of Greece in general, whereas the contribution of Greece in the global CO 2 inventory at a time of climatic change awareness cannot be ignored. In this context, this paper presents the contribution of Greece in ship exhaust emissions of CO 2, NO x, SO 2 and PM from domestic and international shipping over the last 25 years (1984-2008), utilizing the fuel-based (fuel sales) emission methodology. Furthermore, the ship exhaust emissions generated within the Greek seas and their externalities are estimated for the year 2008, through utilizing the fuel-based (fuel sales) approach for domestic shipping and the activity-based (ship traffic) approach for international shipping. On this basis, it was found that during the 1984 to 2008 period the fuel-based (fuel sales) ship emission inventory for Greece increased at an average annual rate of 2.85%. In 2008, the CO 2, NO x, SO 2 and PM emissions reached 12.9 million tons (of which 12.4 million tons of CO 2) and their externalities were found to be around 3

  15. Architecture and Design of Medical Processor Units for Medical Networks

    CERN Document Server

    Ahamed, Syed V; 10.5121/ijcnc.2010.2602

    2011-01-01

    This paper introduces analogical and deductive methodologies for the design medical processor units (MPUs). From the study of evolution of numerous earlier processors, we derive the basis for the architecture of MPUs. These specialized processors perform unique medical functions encoded as medical operational codes (mopcs). From a pragmatic perspective, MPUs function very close to CPUs. Both processors have unique operation codes that command the hardware to perform a distinct chain of subprocesses upon operands and generate a specific result unique to the opcode and the operand(s). In medical environments, MPU decodes the mopcs and executes a series of medical sub-processes and sends out secondary commands to the medical machine. Whereas operands in a typical computer system are numerical and logical entities, the operands in medical machine are objects such as such as patients, blood samples, tissues, operating rooms, medical staff, medical bills, patient payments, etc. We follow the functional overlap betw...

  16. APEmille a parallel processor in the teraflop range

    CERN Document Server

    Panizzi, E

    1996-01-01

    APEmille is a SIMD parallel processor under development at the Italian National Institute for Nuclear Physics (INFN). APEmille is very well suited for Lattice QCD applications, both for its hardware characteristics and for its software and language features. APEmille is an array of custom arithmetic processors arranged on a tridimensional torus. The replicated processor is a pipelined VLIW device performing integer and single/double precision IEEE floating point operations. The processor is optimized for complex computations and has a peak performance of 528Mflop at 66MHz and of 800Mflop at 100MHz. In principle an array of 2048 nodes is able to break the Tflops barrier. A powerful programming language named TAO is provided and is highly optimized for QCD. A C++ compiler is foreseen. Specific data structures, operators and even statements can be defined by the user for each different application. Effort has been made to define the language constructs for QCD.

  17. Compiler for Fast, Accurate Mathematical Computing on Integer Processors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposers will develop a computer language compiler to enable inexpensive, low-power, integer-only processors to carry our mathematically-intensive comptutations...

  18. A Shared Memory Module for Asynchronous Arrays of Processors

    Directory of Open Access Journals (Sweden)

    Zhiyi Yu

    2007-05-01

    Full Text Available A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.

  19. 2009 Survey of Gulf of Mexico Dockside Seafood Processors

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This survey gathered and analyze economic data from seafood processors throughout the states in the Gulf region. The survey sought to collect financial variables...

  20. Baseband processor development for the Advanced Communications Satellite Program

    Science.gov (United States)

    Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

    1982-01-01

    An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

  1. A Shared Memory Module for Asynchronous Arrays of Processors

    Directory of Open Access Journals (Sweden)

    Meeuwsen MichaelJ

    2007-01-01

    Full Text Available A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.

  2. Processors' training needs on modern shea butter processing ...

    African Journals Online (AJOL)

    Processors' training needs on modern shea butter processing technologies in North Central ... South African Journal of Agricultural Extension ... The need for continual production of high quality shea butter in Nigeria through the use of modern ...

  3. Reconfigurable VLIW Processor for Software Defined Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the...

  4. Regulating multiple externalities

    DEFF Research Database (Denmark)

    Waldo, Staffan; Jensen, Frank; Nielsen, Max

    2016-01-01

    Open access is a well-known externality problem in fisheries causing excess capacity and overfishing. Due to global warming, externality problems from CO2 emissions have gained increased interest. With two externality problems, a first-best optimum can be achieved by using two regulatory instrume......Open access is a well-known externality problem in fisheries causing excess capacity and overfishing. Due to global warming, externality problems from CO2 emissions have gained increased interest. With two externality problems, a first-best optimum can be achieved by using two regulatory...

  5. External effects related to biogas and wind power

    DEFF Research Database (Denmark)

    Ibsen, Liselotte Schleisner; Nielsen, Per Sieverts

    1998-01-01

    Energy produced by wind power and biogas is today more expensive than energy produced by fossil fuels. However, by including external costs related to the technologies, the renewable technologies are expected to result in social benefits compared to the conventional power technologies. The paper...... will focus on estimates of externalities related to wind and biogas energy supplies using the ExternE methodology developed in a major study launched by the European Comission. External costs are the costs imporsed on society that are not included in the market price (e.g. effects of air pollution on health...

  6. The avoided external costs of using wind energy

    Energy Technology Data Exchange (ETDEWEB)

    Markandya, A. [Harvard Inst. for International Development, Cambridge, MA (United States)

    1995-12-31

    This article discusses the external costs of electricity generated by conventional fossil fuel sources, such as coal and nuclear power. It compares the costs of electricity generated with coal with that generated with wind. A measure of the benefits of wind energy is the difference between these two external costs. The methodology used for the estimation of the external costs, as well as the estimates of these costs, are taken from the EC ExternE study, financed by DGXII of the European Commission. The present author was a lead economist for that study. (author)

  7. Floating-point multiple data stream digital signal processor

    Energy Technology Data Exchange (ETDEWEB)

    Fortier, M.; Corinthios, M.J.

    1982-01-01

    A microprogrammed multiple data stream digital signal processor is introduced. This floating-point processor is capable of implementing optimum Wiener filtering of signals, in general, and images in particular. Generalised spectral analysis transforms such as Fourier, Walsh, Hadamard, and generalised Walsh are efficiently implemented in a bit-slice microprocessor-based architecture. In this architecture, a microprogrammed sequencing section directly controls a central floating-point signal processing unit. Throughout, computations are performed on pipelined multiple complex data streams. 12 references.

  8. Multi Microkernel Operating Systems for Multi-Core Processors

    Directory of Open Access Journals (Sweden)

    Rami Matarneh

    2009-01-01

    Full Text Available Problem statement: In the midst of the huge development in processors industry as a response to the increasing demand for high-speed processors manufacturers were able to achieve the goal of producing the required processors, but this industry disappointed hopes, because it faced problems not amenable to solution, such as complexity, hard management and large consumption of energy. These problems forced the manufacturers to stop the focus on increasing the speed of processors and go toward parallel processing to increase performance. This eventually produced multi-core processors with high-performance, if used properly. Unfortunately, until now, these processors did not use as it should be used; because of lack support of operating system and software applications. Approach: The approach based on the assumption that single-kernel operating system was not enough to manage multi-core processors to rethink the construction of multi-kernel operating system. One of these kernels serves as the master kernel and the others serve as slave kernels. Results: Theoretically, the proposed model showed that it can do much better than the existing models; because it supported single-threaded processing and multi-threaded processing at the same time, in addition, it can make better use of multi-core processors because it divided the load almost equally between the cores and the kernels which will lead to a significant improvement in the performance of the operating system. Conclusion: Software industry needed to get out of the classical framework to be able to keep pace with hardware development, this objective was achieved by re-thinking building operating systems and software in a new innovative methodologies and methods, where the current theories of operating systems were no longer capable of achieving the aspirations of future.

  9. Nanosensor Data Processor in Quantum-Dot Cellular Automata

    OpenAIRE

    Fenghui Yao; Mohamed Saleh Zein-Sabatto; Guifeng Shao; Mohammad Bodruzzaman; Mohan Malkani

    2014-01-01

    Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP). The functions of NSDP contain (i) sending the preprocessed raw data to high-level processor, (ii) counting...

  10. An Imaging Infrared (IIR) seeker using a microprogrammed processor

    Science.gov (United States)

    Richmond, K. V.

    1980-01-01

    A recently developed Imaging Infrared Seeker uses a microprogrammed processor to perform gimbal servo control and system interface while performing the seeker functions of automatic target detection, acquisition, and tracking. The automatic detection mode requires up to 80% of the available capability of a high performance microprogrammed processor. Although system complexity was increased significantly, this approach can be cost effective when the basic computation capacity is already available.

  11. Fast Parallel Computation of Polynomials Using Few Processors

    DEFF Research Database (Denmark)

    Valiant, Leslie G.; Skyum, Sven; Berkowitz, S.;

    1983-01-01

    It is shown that any multivariate polynomial of degree $d$ that can be computed sequentially in $C$ steps can be computed in parallel in $O((\\log d)(\\log C + \\log d))$ steps using only $(Cd)^{O(1)} $ processors.......It is shown that any multivariate polynomial of degree $d$ that can be computed sequentially in $C$ steps can be computed in parallel in $O((\\log d)(\\log C + \\log d))$ steps using only $(Cd)^{O(1)} $ processors....

  12. Fast parallel computation of polynomials using few processors

    DEFF Research Database (Denmark)

    Valiant, Leslie; Skyum, Sven

    1981-01-01

    It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors.......It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors....

  13. Assessment of the externalities of biomass energy for electricity production

    Energy Technology Data Exchange (ETDEWEB)

    Linares, P.; Leal, J.; Saez, R.M.

    1996-10-01

    This study presents a methodology for the quantification of the socioeconomic and environmental externalities of the biomass fuel cycle. It is based on the one developed by the ExternE Project of the European Commission, based in turn in the damage function approach, and which has been extended and modified for a better adaptation to biomass energy systems. The methodology has been applied to a 20 MW biomass power plant, fueled by Cynara cardunculus, in southern Spain. The externalities addressed have been macroeconomic effects, employment, CO{sub 2}, fixation, erosion, and non-point source pollution. The results obtained should be considered only as subtotals, since there are still other externalities to be quantified. anyway, and in spite of the uncertainty existing, these results suggest that total cost (those including internal and external costs) of biomass energy are lower than those of conventional energy sources, what, if taken into account, would make biomass more competitive than it is now. (Author)

  14. THOR Field and Wave Processor - FWP

    Science.gov (United States)

    Soucek, Jan; Rothkaehl, Hanna; Balikhin, Michael; Zaslavsky, Arnaud; Nakamura, Rumi; Khotyaintsev, Yuri; Uhlir, Ludek; Lan, Radek; Yearby, Keith; Morawski, Marek; Winkler, Marek

    2016-04-01

    If selected, Turbulence Heating ObserveR (THOR) will become the first mission ever flown in space dedicated to plasma turbulence. The Fields and Waves Processor (FWP) is an integrated electronics unit for all electromagnetic field measurements performed by THOR. FWP will interface with all fields sensors: electric field antennas of the EFI instrument, the MAG fluxgate magnetometer and search-coil magnetometer (SCM) and perform data digitization and on-board processing. FWP box will house multiple data acquisition sub-units and signal analyzers all sharing a common power supply and data processing unit and thus a single data and power interface to the spacecraft. Integrating all the electromagnetic field measurements in a single unit will improve the consistency of field measurement and accuracy of time synchronization. The feasibility of making highly sensitive electric and magnetic field measurements in space has been demonstrated by Cluster (among other spacecraft) and THOR instrumentation complemented by a thorough electromagnetic cleanliness program will further improve on this heritage. Taking advantage of the capabilities of modern electronics, FWP will provide simultaneous synchronized waveform and spectral data products at high time resolution from the numerous THOR sensors, taking advantage of the large telemetry bandwidth of THOR. FWP will also implement a plasma a resonance sounder and a digital plasma quasi-thermal noise analyzer designed to provide high cadence measurements of plasma density and temperature complementary to data from particle instruments. FWP will be interfaced with the particle instrument data processing unit (PPU) via a dedicated digital link which will enable performing on board correlation between waves and particles, quantifying the transfer of energy between waves and particles. The FWP instrument shall be designed and built by an international consortium of scientific institutes from Czech Republic, Poland, France, UK, Sweden

  15. Biomolecular simulation on thousands of processors

    Science.gov (United States)

    Phillips, James Christopher

    Classical molecular dynamics simulation is a generally applicable method for the study of biomolecular aggregates of proteins, lipids, and nucleic acids. As experimental techniques have revealed the structures of larger and more complex biomolecular machines, the time required to complete even a single meaningful simulation of such systems has become prohibitive. We have developed the program NAMD to simulate systems of 50,000--500,000 atoms efficiently with full electrostatics on parallel computers with 1000 and more processors. NAMD's scalability is achieved through latency tolerant adaptive message-driven execution and measurement-based load balancing. NAMD is implemented in C++ and uses object-oriented design and threads to shield the basic algorithms from the necessary complexity of high-performance parallel execution. Apolipoprotein A-I is the primary protein constituent of high density lipoprotein particles, which transport cholesterol in the bloodstream. In collaboration with A. Jonas, we have constructed and simulated models of the nascent discoidal form of these particles, providing theoretical insight to the debate regarding the lipid-bound structure of the protein. Recently, S. Sligar and coworkers have created 10 nm phospholipid bilayer nanoparticles comprising a small lipid bilayer disk solubilized by synthetic membrane scaffold proteins derived from apolipoprotein A-I. Membrane proteins may be embedded in the water-soluble disks, with various medical and technological applications. We are working to develop variant scaffold proteins that produce disks of greater size, stability, and homogeneity. Our simulations have demonstrated a significant deviation from idealized cylindrical structure, and are being used in the interpretation of small angle x-ray scattering data.

  16. A novel VLSI processor architecture for supercomputing arrays

    Science.gov (United States)

    Venkateswaran, N.; Pattabiraman, S.; Devanathan, R.; Ahmed, Ashaf; Venkataraman, S.; Ganesh, N.

    1993-01-01

    Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.

  17. Review of trigger and on-line processors at SLAC

    Energy Technology Data Exchange (ETDEWEB)

    Lankford, A.J.

    1984-07-01

    The role of trigger and on-line processors in reducing data rates to manageable proportions in e/sup +/e/sup -/ physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e/sup +/e/sup -/ annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e/sup +/e/sup -/ context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table.

  18. High-Speed General Purpose Genetic Algorithm Processor.

    Science.gov (United States)

    Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

    2016-07-01

    In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

  19. Reconfigurable signal processor designs for advanced digital array radar systems

    Science.gov (United States)

    Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

    2017-05-01

    The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

  20. Design and Implementation of Quintuple Processor Architecture Using FPGA

    Directory of Open Access Journals (Sweden)

    P.Annapurna

    2014-09-01

    Full Text Available The advanced quintuple processor core is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permit complex logic systems to be implemented on a single programmable device. The embedded multiprocessors face a new problem with thread synchronization. It is caused by the distributed memory, when thread synchronization is violated the processors can access the same value at the same time. Basically the processor performance can be increased by adopting clock scaling technique and micro architectural Enhancements. Therefore, Designed a new Architecture called Advanced Concurrent Computing. This is implemented on the FPGA chip using VHDL. The advanced Concurrent Computing architecture performs a simultaneous use of both parallel and distributed computing. The full architecture of quintuple processor core designed for realistic to perform arithmetic, logical, shifting and bit manipulation operations. The proposed advanced quintuple processor core contains Homogeneous RISC processors, added with pipelined processing units, multi bus organization and I/O ports along with the other functional elements required to implement embedded SOC solutions. The designed quintuple performance issues like area, speed and power dissipation and propagation delay are analyzed at 90nm process technology using Xilinx tool.

  1. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

    2014-01-01

    The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

  2. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

  3. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

  4. ASH External Web Portal (External Portal) -

    Data.gov (United States)

    Department of Transportation — The ASH External Web Portal is a web-based portal that provides single sign-on functionality, making the web portal a single location from which to be authenticated...

  5. Environmental externalities related to power production on biogas and natural gas based on the EU ExternE methodology

    DEFF Research Database (Denmark)

    Nielsen, Per Sieverts; Ibsen, Liselotte Schleisner

    1998-01-01

    This paper assesses the environmental impacts and external costs from selected electricity generation systems in Denmark. The assessment is carried out as part of the ExternE National Implementation, which is the second phase of the ExternE project and involves case studies from all Western Europ...... show that estimated damages due to the greenhouse effect are predominant, however, the uncertainty is high. The predominant damage at the local and regional level is related to emission of NOx, which results in effects on public health....... European countries. The project use a “bottom-up” methodology to evaluate the external costs associated with a wide range of different fuel cycles. The project has identified priority impacts, where most are impacts from air emissions. Externalities due to atmospheric emissions are calculated through...... the use of a software package, EcoSence, having an environmental database at both a local and regional level including population, crops, building materials and forest. The system also incorporates two air transport models, allowing local and regional scale modelling. The results of the Danish case study...

  6. Evaluation of MERIS Case-II Water Processors in the Baltic Sea

    OpenAIRE

    Arroyo Pedrero, Jaume

    2009-01-01

    Projecte realitzat en col.laboració amb Helsinki University of Technology Four MERIS Case-II Water Processors are studied, compared and evaluated: Coastal Case 2 Regional Processor, Boreal Lakes Processor, Eutrophic Lakes Processor and FUB/Wew Water Processor. In situ data from the Baltic Sea have been used to evaluate the water constituent estimations. In addition, the effect of adjacency effect ICOL on the estimation has been analyzed. For this purpose, a set of tools has been d...

  7. SCHEDULING PROBLEMS OF STATIONARY OBJECTS WITH THE PROCESSOR IN ONE-DIMENSIONAL ZONE

    Directory of Open Access Journals (Sweden)

    N. A. Dunichkina

    2015-01-01

    Full Text Available We consider the mathematical model in which an operating processor serves the set of the stationary objects positioned in a one-dimensional working zone. The processor performs two voyages between the uttermost points of the zone: the forward or direct one, where certain objects are served, and the return one, where remaining objects are served. Servicing of the object cannot start earlier than its ready date. The individual penalty function is assigned to every object, the function depending on the servicing completion time. Minimized criteria of schedule quality are assumed to be total service duration and total penalty. We formulate and study optimization problems with one and two criteria. Proposed algorithms are based on dynamic programming and Pareto principle, the implementations of these algorithms are demonstrated on numerical examples. We show that the algorithm for the problem of processing time minimization is polynomial, and that the problem of total penalty minimization is NP-hard. Correspondingly, the bicriteria problem with the mentioned evaluation criteria is fundamentally intractable, computational complexity of the schedule structure algorithm is exponential. The model describes the fuel supply processes to the diesel-electrical dredgers which extract non-metallic building materials (sand, gravel in large-scale areas of inland waterways. Similar models and optimization problems are important, for example, in applications like the control of satellite group refueling and regular civil aircraft refueling.The article is published in the author’s wording.

  8. THOR Fields and Wave Processor - FWP

    Science.gov (United States)

    Soucek, Jan; Rothkaehl, Hanna; Ahlen, Lennart; Balikhin, Michael; Carr, Christopher; Dekkali, Moustapha; Khotyaintsev, Yuri; Lan, Radek; Magnes, Werner; Morawski, Marek; Nakamura, Rumi; Uhlir, Ludek; Yearby, Keith; Winkler, Marek; Zaslavsky, Arnaud

    2017-04-01

    If selected, Turbulence Heating ObserveR (THOR) will become the first spacecraft mission dedicated to the study of plasma turbulence. The Fields and Waves Processor (FWP) is an integrated electronics unit for all electromagnetic field measurements performed by THOR. FWP will interface with all THOR fields sensors: electric field antennas of the EFI instrument, the MAG fluxgate magnetometer, and search-coil magnetometer (SCM), and perform signal digitization and on-board data processing. FWP box will house multiple data acquisition sub-units and signal analyzers all sharing a common power supply and data processing unit and thus a single data and power interface to the spacecraft. Integrating all the electromagnetic field measurements in a single unit will improve the consistency of field measurement and accuracy of time synchronization. The scientific value of highly sensitive electric and magnetic field measurements in space has been demonstrated by Cluster (among other spacecraft) and THOR instrumentation will further improve on this heritage. Large dynamic range of the instruments will be complemented by a thorough electromagnetic cleanliness program, which will prevent perturbation of field measurements by interference from payload and platform subsystems. Taking advantage of the capabilities of modern electronics and the large telemetry bandwidth of THOR, FWP will provide multi-component electromagnetic field waveforms and spectral data products at a high time resolution. Fully synchronized sampling of many signals will allow to resolve wave phase information and estimate wavelength via interferometric correlations between EFI probes. FWP will also implement a plasma resonance sounder and a digital plasma quasi-thermal noise analyzer designed to provide high cadence measurements of plasma density and temperature complementary to data from particle instruments. FWP will rapidly transmit information about magnetic field vector and spacecraft potential to the

  9. Socio-economic research on fusion. SERF 1997-98. Macro Tast E2: External costs and benefits. Task 2: Comparison of external costs

    Energy Technology Data Exchange (ETDEWEB)

    Schleisner, Lotte; Korhonen, Riitta

    1998-12-01

    This report is part of the SERF (Socio-Economic Research on Fusion) project, Macro Task E2, which covers External Costs and Benefits. The report is the documentation of Task 2, Comparison of External Costs. The aim of Task 2 Comparison of External Costs, has been to compare the external costs of the fusion energy with those from other alternative energy generation technologies. In this task identification and quantification of the external costs for wind energy and photovoltaic have been performed by Risoe, while identification and quantification of the external cost for nuclear fission and fossil fuels have been discussed by VTT. The methodology used for the assessment of the externalities of the fuel cycles selected has been the one developed within the ExternE Project. First estimates for the externalities of fusion energy have been under examination in Macrotask E2. Externalities of fossil fuels and nuclear fission have already been evaluated in the ExternE project and a vast amount of material for different sites in various countries is available. This material is used in comparison. In the case of renewable wind energy and photovoltaic are assessed separately. External costs of the various alternatives may change as new technologies are developed and costs can to a high extent be avoided (e.g. acidifying impacts but also global warming due to carbon dioxide emissions). Also fusion technology can experience major progress and some important cost components probably can be avoided already by 2050. (EG) 36 refs.

  10. Digital signal processor for silicon audio playback devices; Silicon audio saisei kikiyo digital signal processor

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital audio signal processor (DSP) TC9446F series has been developed silicon audio playback devices with a memory medium of, e.g., flash memory, DVD players, and AV devices, e.g., TV sets. It corresponds to AAC (advanced audio coding) (2ch) and MP3 (MPEG1 Layer3), as the audio compressing techniques being used for transmitting music through an internet. It also corresponds to compressed types, e.g., Dolby Digital, DTS (digital theater system) and MPEG2 audio, being adopted for, e.g., DVDs. It can carry a built-in audio signal processing program, e.g., Dolby ProLogic, equalizer, sound field controlling, and 3D sound. TC9446XB has been lined up anew. It adopts an FBGA (fine pitch ball grid array) package for portable audio devices. (translated by NEDO)

  11. 76 FR 79051 - Airworthiness Directives; Lycoming Engines, Fuel Injected Reciprocating Engines

    Science.gov (United States)

    2011-12-21

    ...-AD; Amendment 39-16894; AD 2011-26-04] RIN 2120-AA64 Airworthiness Directives; Lycoming Engines, Fuel... AD to prevent failure of the fuel injector fuel lines that would allow fuel to spray into the engine... response, any AD made applicable to TCM engines with externally mounted fuel injector lines, would have...

  12. [Improving speech comprehension using a new cochlear implant speech processor].

    Science.gov (United States)

    Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

    2009-06-01

    The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

  13. Fault tolerant, radiation hard, high performance digital signal processor

    Science.gov (United States)

    Holmann, Edgar; Linscott, Ivan R.; Maurer, Michael J.; Tyler, G. L.; Libby, Vibeke

    1990-01-01

    An architecture has been developed for a high-performance VLSI digital signal processor that is highly reliable, fault-tolerant, and radiation-hard. The signal processor, part of a spacecraft receiver designed to support uplink radio science experiments at the outer planets, organizes the connections between redundant arithmetic resources, register files, and memory through a shuffle exchange communication network. The configuration of the network and the state of the processor resources are all under microprogram control, which both maps the resources according to algorithmic needs and reconfigures the processing should a failure occur. In addition, the microprogram is reloadable through the uplink to accommodate changes in the science objectives throughout the course of the mission. The processor will be implemented with silicon compiler tools, and its design will be verified through silicon compilation simulation at all levels from the resources to full functionality. By blending reconfiguration with redundancy the processor implementation is fault-tolerant and reliable, and possesses the long expected lifetime needed for a spacecraft mission to the outer planets.

  14. A programmable systolic trigger processor for FERA-bus data

    Science.gov (United States)

    Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

    1992-09-01

    A generic CAMAC based trigger processor module for fast processing of large amounts of Analog to Digital Converter (ADC) data was designed. This module was realized using complex programmable gate arrays. The gate arrays were connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter is used for set up and control but may also be used for data output. Large numbers of ADC's can be served by a hierarchical arrangement of trigger processor modules which process ADC data with pipeline arithmetics and produce the final result at the apex of the pyramid. The trigger decision is transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was developed for the proposed neutral particle search. It was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data, and calculate the particle mass. A suitable mass cut would then deliver the trigger decision.

  15. PERFORMANCE OF PRIVATE CACHE REPLACEMENT POLICIES FOR MULTICORE PROCESSORS

    Directory of Open Access Journals (Sweden)

    Matthew Lentz

    2014-07-01

    Full Text Available Multicore processors have become ubiquitous, both in general-purpose and special-purpose applications. With the number of transistors in a chip continuing to increase, the number of cores in a processor is also expected to increase. Cache replacement policy is an important design parameter of a cache hierarchy. As most of the processor designs have become multicore, there is a need to study cache replacement policies for multi-core systems. Previous studies have focused on the shared levels of the multicore cache hierarchy. In this study, we focus on the top level of the hierarchy, which bears the brunt of the memory requests emanating from each processor core. We measure the miss rates of various cache replacement policies, as the number of cores is steadily increased from 1 to 16. The study was done by modifying the publicly available SESC simulator, which models in detail a multicore processor with a multilevel cache hierarchy. Our experimental results show that for the private L1 caches, the LRU (Least Recently Used replacement policy outperforms all of the other replacement policies. This is in contrast to what was observed in previous studies for the shared L2 cache. The results presented in this paper are useful for hardware designers to optimize their cache designs or the program codes.

  16. High Performance Ethernet Packet Processor Core for Next Generation Networks

    Directory of Open Access Journals (Sweden)

    Raja Jitendra Nayaka

    2012-10-01

    Full Text Available As the demand for high speed Internet significantly increasing to meet the requirement of large datatransfers, real-time communication and High Definition ( HD multimedia transfer over IP, the IP basednetwork products architecture must evolve and change. Application specific processors require highperformance, low power and high degree of programmability is the limitation in many general processorbased applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoCwhich performs all core packet processing functions, including segmentation and reassembly, packetizationclassification, route and queue management which will speedup switching/routing performance making itmore suitable for Next Generation Networks (NGN. Ethernet packet processor design can be configuredfor use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulatedthe required functions in FPGA.

  17. The ATLAS Level-1 Central Trigger Processor (CTP)

    CERN Document Server

    Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

    2005-01-01

    The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

  18. Architecture and Design of Medical Processor Units for Medical Networks

    Directory of Open Access Journals (Sweden)

    Syed V. Ahamed

    2010-11-01

    Full Text Available This paper1 introduces analogical and deductive methodologies for the design medical processor units(MPUs. From the study of evolution of numerous earlier processors, we derive the basis for thearchitecture of MPUs. These specialized processors perform unique medical functions encoded as medicaloperational codes (mopcs. From a pragmatic perspective, MPUs function very close to CPUs. Bothprocessors have unique operation codes that command the hardware to perform a distinct chain of subprocessesupon operands and generate a specific result unique to the opcode and the operand(s. Inmedical environments, MPU decodes the mopcs and executes a series of medical sub-processes and sendsout secondary commands to the medical machine. Whereas operands in a typical computer system arenumerical and logical entities, the operands in medical machine are objects such as such as patients, bloodsamples, tissues, operating rooms, medical staff, medical bills, patient payments, etc. We follow thefunctional overlap between the two processes and evolve the design of medical computer systems andnetworks.

  19. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  20. Floating-point systolic array including serial processors

    Energy Technology Data Exchange (ETDEWEB)

    Leeland, S.B.

    1989-10-03

    This patent describes, in a systolic array system utilizing a plurality of semiconductor chips, a semiconductor chip. It comprises: a plurality of processing elements each including a floating-point serial processor and a plurality of data storage registers; global bus means coupled to the serial processor of each of the plurality of processing elements for inputing and outputing data to and from each chip and for programming each serial processor; and a plurality of data buses coupled to each of the plurality of data storage registers of each of the plurality of processing elements. The global bus means being coupled to the plurality of data storage registers for programming the data storage registers.

  1. Stepping motor control processor reference manual. Volume I

    Energy Technology Data Exchange (ETDEWEB)

    Holloway, F.W.; VanArsdall, P.J.; Suski, G.J.; Gant, R.G.; Rash, M.

    1980-06-06

    This manual is intended to serve several purposes. The first goal is to describe the capabilities and operation of the SMC processor package from an operator or user point of view. Secondly, the manual will describe in some detail the basic hardware elements and how they can be used effectively to implement a step motor control system. Practical information on the use, installation and checkout of the hardware set is presented in the following sections along with programming suggestions. Available related system software is described in this manual for reference and as an aid in understanding the system architecture. Section two presents an overview and operations manual of the SMC processor describing its composition and functional capabilities. Section three contains hardware descriptions in some detail for the LLL-designed hardware used in the SMC processor. Basic theory of operation and important features are explained.

  2. Safety-critical Java on a time-predictable processor

    DEFF Research Database (Denmark)

    Korsholm, Stephan E.; Schoeberl, Martin; Puffitsch, Wolfgang

    2015-01-01

    For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....

  3. Modal Processor Effects Inspired by Hammond Tonewheel Organs

    Directory of Open Access Journals (Sweden)

    Kurt James Werner

    2016-06-01

    Full Text Available In this design study, we introduce a novel class of digital audio effects that extend the recently introduced modal processor approach to artificial reverberation and effects processing. These pitch and distortion processing effects mimic the design and sonics of a classic additive-synthesis-based electromechanical musical instrument, the Hammond tonewheel organ. As a reverb effect, the modal processor simulates a room response as the sum of resonant filter responses. This architecture provides precise, interactive control over the frequency, damping, and complex amplitude of each mode. Into this framework, we introduce two types of processing effects: pitch effects inspired by the Hammond organ’s equal tempered “tonewheels”, “drawbar” tone controls, vibrato/chorus circuit, and distortion effects inspired by the pseudo-sinusoidal shape of its tonewheels and electromagnetic pickup distortion. The result is an effects processor that imprints the Hammond organ’s sonics onto any audio input.

  4. A Bayesian sequential processor approach to spectroscopic portal system decisions

    Energy Technology Data Exchange (ETDEWEB)

    Sale, K; Candy, J; Breitfeller, E; Guidry, B; Manatt, D; Gosnell, T; Chambers, D

    2007-07-31

    The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waiting for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.

  5. Fault Tolerance Mechanism in Chip Many-Core Processors

    Institute of Scientific and Technical Information of China (English)

    ZHANG Lei; HAN Yinhe; LI Huawei; LI Xiaowei

    2007-01-01

    As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors'yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors'performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.

  6. The DPGA for Conbining the Superscalar and Multithreaded Processors Principal

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchroni z ation ,and the latency caused by instructions that take multiple cycles to produ ce results. To tolerate these three types of latencies, The followin g techniques was proposed to couple: coarse-grained multithreading, the supersc alar processor and a rec onfigurable device, namely the overlapping long latency operations of one thread of computation with the execution of other threads. The superscalar processor p rinciple is used to tolerate instruction latency by issuing several instructions simultaneously. The DPGA is coupled with this processor in order to improve th e context-switching overhead.

  7. Safety-Critical Java on a Time-predictable Processor

    DEFF Research Database (Denmark)

    Korsholm, Stephan Erbs; Schoeberl, Martin; Puffitsch, Wolfgang

    2015-01-01

    For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....

  8. Token-Aware Completion Functions for Elastic Processor Verification

    Directory of Open Access Journals (Sweden)

    Sudarshan K. Srinivasan

    2009-01-01

    Full Text Available We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.

  9. Processor Allocation for Optimistic Parallelization of Irregular Programs

    CERN Document Server

    Versaci, Francesco

    2012-01-01

    Optimistic parallelization is a promising approach for the parallelization of irregular algorithms: potentially interfering tasks are launched dynamically, and the runtime system detects conflicts between concurrent activities, aborting and rolling back conflicting tasks. However, parallelism in irregular algorithms is very complex. In a regular algorithm like dense matrix multiplication, the amount of parallelism can usually be expressed as a function of the problem size, so it is reasonably straightforward to determine how many processors should be allocated to execute a regular algorithm of a certain size (this is called the processor allocation problem). In contrast, parallelism in irregular algorithms can be a function of input parameters, and the amount of parallelism can vary dramatically during the execution of the irregular algorithm. Therefore, the processor allocation problem for irregular algorithms is very difficult. In this paper, we describe the first systematic strategy for addressing this pro...

  10. DM在航油管道外防腐层检测中的应用%The Application of DM at the External Anticorrosion Coating Detection of a Fuel Pipeline

    Institute of Scientific and Technical Information of China (English)

    陈智君; 李勇樊; 顾平

    2016-01-01

    本文通过研究各种管道检测技术的基本原理,对比了它们的优缺点,强调了综合检测技术的重要性。在此基础上介绍了DM(Defect Mapper)管道防腐层检测仪的基本原理和使用方法,并在某航油管道外防腐层检测中得到应用,获得良好的检测效果。%This paper introduced the basic principle of different pipeline detection technology and compared their advantages and disadvantages and emphasized the importance of comprehensive testing technology. We also introduced the basic principles and methods of DM pipeline coating detector. And get good results through its practical application in some jet fuel pipeline.

  11. External radiation surveillance

    Energy Technology Data Exchange (ETDEWEB)

    Antonio, E.J.

    1995-06-01

    This section of the 1994 Hanford Site Environmental Report describes how external radiation was measured, how surveys were performed, and the results of these measurements and surveys. External radiation exposure rates were measured at locations on and off the Hanford Site using thermoluminescent dosimeters (TLD). External radiation and contamination surveys were also performed with portable radiation survey instruments at locations on and around the Hanford Site.

  12. Benchmarking NWP Kernels on Multi- and Many-core Processors

    Science.gov (United States)

    Michalakes, J.; Vachharajani, M.

    2008-12-01

    Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

  13. Smart composite material system with sensor, actuator, and processor functions: a model of holding and releasing a ball

    Science.gov (United States)

    Oishi, Ryutaro; Yoshida, Hitoshi; Nagai, Hideki; Xu, Ya; Jang, Byung-Koog

    2002-07-01

    A smart composite material system which has three smart functions of sensor, actuator and processor has been developed intend to apply to structure of house for controlling ambient temperature and humidity, hands of robot for holding and feeling an object, and so on. A carbon fiber reinforced plastics (CFRP) is used as matrix in the smart composite. The size of the matrix is 120mm x 24mm x 0.45mm. The CFRP plate is combined two Ni-Ti shape memory alloy (SMA) wires with an elastic rubber to construct a composite material. The composite material has a characteristic of reversible response with respect to temperature. A photo-sensor and temperature sensor are embedded in the composite material. The composite material has a processor function to combine with a simple CPU (processor) unit. For demonstrating the capability of the composite material system, a model is built up for controlling certain behaviors such as gripping and releasing a spherical object. The amplitude of gripping force is (3.0 plus/minus 0.3) N in the measurement, which is consistent with our calculation of 2.7 N. Out of a variety of functions to be executed by the CPU, it is shown to exert calculation and decision making in regard to object selection, object holding, and ON-OFF control of action by external commands.

  14. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  15. The associative memory system for the FTK processor at ATLAS

    CERN Document Server

    Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M

    2014-01-01

    In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.

  16. Hardwired Logic and Multithread Design in Network Processors

    Institute of Scientific and Technical Information of China (English)

    李旭东; 徐扬; 刘斌; 王小军

    2004-01-01

    High-performance network processors are expected to play an important role in future high-speed routers. This paper focuses on two representative techniques needed for high-performance network processors: hardwired logic design and multithread design. Using hardwired logic, this paper compares a single-thread design with a multithread design, and proposes general models and principles to analyze the clock frequency and the resource cost for these environments. Then, two IP header processing schemes, one in single-thread mode and the other in double-thread mode, are developed using these principles and the implementation results verified the theoretical calculation.

  17. ARM Processor Based Embedded System for Remote Data Acquisition

    Directory of Open Access Journals (Sweden)

    Raj Kumar Tiwari

    2014-01-01

    Full Text Available The embedded systems are widely used for the data acquisition. The data acquired may be used for monitoring various activity of the system or it can be used to control the parts of the system. Accessing various signals with remote location has greater advantage for multisite operation or unmanned systems. The remote data acquisition used in this paper is based on ARM processor. The Cortex M3 processor used in this system has in-built Ethernet controller which facilitate to acquire the remote data using internet. The system developed provides high performance, low power consumption, smaller size {&} high speed

  18. Nanosensor Data Processor in Quantum-Dot Cellular Automata

    Directory of Open Access Journals (Sweden)

    Fenghui Yao

    2014-01-01

    Full Text Available Quantum-dot cellular automata (QCA is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP. The functions of NSDP contain (i sending the preprocessed raw data to high-level processor, (ii counting the number of the active majority gates, and (iii generating the approximate sigmoid function. The whole system is designed and simulated with several different input data.

  19. Matrix preconditioning: a robust operation for optical linear algebra processors.

    Science.gov (United States)

    Ghosh, A; Paparao, P

    1987-07-15

    Analog electrooptical processors are best suited for applications demanding high computational throughput with tolerance for inaccuracies. Matrix preconditioning is one such application. Matrix preconditioning is a preprocessing step for reducing the condition number of a matrix and is used extensively with gradient algorithms for increasing the rate of convergence and improving the accuracy of the solution. In this paper, we describe a simple parallel algorithm for matrix preconditioning, which can be implemented efficiently on a pipelined optical linear algebra processor. From the results of our numerical experiments we show that the efficacy of the preconditioning algorithm is affected very little by the errors of the optical system.

  20. Global synchronization of parallel processors using clock pulse width modulation

    Science.gov (United States)

    Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

    2013-04-02

    A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

  1. Parallel Processor for 3D Recovery from Optical Flow

    Directory of Open Access Journals (Sweden)

    Jose Hugo Barron-Zambrano

    2009-01-01

    Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

  2. Fast normal random number generators on vector processors

    OpenAIRE

    Brent, Richard P.

    2010-01-01

    We consider pseudo-random number generators suitable for vector processors. In particular, we describe vectorised implementations of the Box-Muller and Polar methods, and show that they give good performance on the Fujitsu VP2200. We also consider some other popular methods, e.g. the Ratio method of Kinderman and Monahan (1977) (as improved by Leva (1992)), and the method of Von Neumann and Forsythe, and show why they are unlikely to be competitive with the Polar method on vector processors.

  3. A processor sharing model for wireless data communication

    DEFF Research Database (Denmark)

    Hansen, Martin Bøgsted

    occupies these servers for an exponentially distributed holding time with mean $1/( mu)$. However, in lack of requested resources some Time Division Multiple Access (TDMA) implementations for mobile data communication like High Speed Circuit Switched Data (HSCSD) and General Packet Radio Service (GPRS......) allow already established resources for data connections to be downgraded to allow a new connection to be established. As noted by Litjens and Boucherie (2002) this resembles classical processor sharing models, and in this spirit we formulate a variant of the processor sharing model with a limited...

  4. MICROTHREAD BASED (MTB) COARSE GRAINED FAULT TOLERANCE SUPERSCALAR PROCESSOR ARCHITECTURE

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    Fault tolerance in microprocessor systems has become a popular topic of architecture research.Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance.This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.

  5. Hardware Synchronization for Embedded Multi-Core Processors

    DEFF Research Database (Denmark)

    Stoif, Christian; Schoeberl, Martin; Liccardi, Benito

    2011-01-01

    Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establi......Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper...

  6. Differences in methodologies used for externality assessment. Why are the numbers different?

    DEFF Research Database (Denmark)

    Ibsen, Liselotte Schleisner

    1999-01-01

    During the last few years, externalities related to power production technologies have been calculated making use of different methodologies. The external costs may turn out to be very different for the same fuel cycle depending on the methodology thathas been used to assess the externalities....... The report gives a review of different valuation issues, which are used in different externality studies and focuses on why the numbers often are different for the same fuel cycle, using different methodologiesfor assessment of the externalities. The review of externality valuation focuses in this report...... on the assessment of environmental externalities. Importance has been attached to health effects, as these are the dominating effects in the external costs.Other effects are only mentioned on a superior level. The report points out different parameters, which are important to consider when externalities estimated...

  7. Fossil Fuels.

    Science.gov (United States)

    Crank, Ron

    This instructional unit is one of 10 developed by students on various energy-related areas that deals specifically with fossil fuels. Some topics covered are historic facts, development of fuels, history of oil production, current and future trends of the oil industry, refining fossil fuels, and environmental problems. Material in each unit may…

  8. Fossil Fuels.

    Science.gov (United States)

    Crank, Ron

    This instructional unit is one of 10 developed by students on various energy-related areas that deals specifically with fossil fuels. Some topics covered are historic facts, development of fuels, history of oil production, current and future trends of the oil industry, refining fossil fuels, and environmental problems. Material in each unit may…

  9. CERN Technical Training: Digital Signal Processors

    CERN Multimedia

    HR Department

    2009-01-01

    A new training is going to be held at CERN on the ADSP SHARC Family. The “System Development and Programming with the Analog Devices' SHARC Family” course is a 3.5-day hands-on training on Analog Devices SHARC DSPs, focusing on the latest ‘368/9 and 37x families. General DSP architecture, peripherals available, booting up process and DSP code development will be covered. Hardware tools, debugging and hardware design guidelines will be introduced as well. The course id designed for System Designers needing to make informed decisions on design tradeoffs, Hardware Designers needing to develop external interfaces, and Code Developers needing to know how to get the highest performance from their algorithms. The course will take place, in English, from 31 March to 4 April in the CERN Technical Training Center. Few places are still available. Registrations are opened on the Technical Training page. More information on our catalogue: http://cta.cern.ch/cta2/f?p=110:9 or conta...

  10. The Trigger Processor and Trigger Processor Algorithms for the ATLAS New Small Wheel Upgrade

    CERN Document Server

    Lazovich, Tomo; The ATLAS collaboration

    2015-01-01

    The ATLAS New Small Wheel (NSW) is an upgrade to the ATLAS muon endcap detectors that will be installed during the next long shutdown of the LHC. Comprising both MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), this system will drastically improve the performance of the muon system in a high cavern background environment. The NSW trigger, in particular, will significantly reduce the rate of fake triggers coming from track segments in the endcap not originating from the interaction point. We will present an overview of the trigger, the proposed sTGC and MM trigger algorithms, and the hardware implementation of the trigger. In particular, we will discuss both the heart of the trigger, an ATCA system with FPGA-based trigger processors (using the same hardware platform for both MM and sTGC triggers), as well as the full trigger electronics chain, including dedicated cards for transmission of data via GBT optical links. Finally, we will detail the challenges of ensuring that the trigger electronics can ...

  11. DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor

    Science.gov (United States)

    Chuang, Chung-Lun; Shaffer, Scott; Smythe, Robert; Niamsuwan, Noppasin; Li, Samuel; Liao, Eric; Lim, Chester; Morfopolous, Arin; Veilleux, Louise

    2013-01-01

    The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.

  12. DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor

    Science.gov (United States)

    Chuang, Chung-Lun; Shaffer, Scott; Smythe, Robert; Niamsuwan, Noppasin; Li, Samuel; Liao, Eric; Lim, Chester; Morfopolous, Arin; Veilleux, Louise

    2013-01-01

    The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.

  13. Fuel distribution

    Energy Technology Data Exchange (ETDEWEB)

    Tison, R.R.; Baker, N.R.; Blazek, C.F.

    1979-07-01

    Distribution of fuel is considered from a supply point to the secondary conversion sites and ultimate end users. All distribution is intracity with the maximum distance between the supply point and end-use site generally considered to be 15 mi. The fuels discussed are: coal or coal-like solids, methanol, No. 2 fuel oil, No. 6 fuel oil, high-Btu gas, medium-Btu gas, and low-Btu gas. Although the fuel state, i.e., gas, liquid, etc., can have a major impact on the distribution system, the source of these fuels (e.g., naturally-occurring or coal-derived) does not. Single-source, single-termination point and single-source, multi-termination point systems for liquid, gaseous, and solid fuel distribution are considered. Transport modes and the fuels associated with each mode are: by truck - coal, methanol, No. 2 fuel oil, and No. 6 fuel oil; and by pipeline - coal, methane, No. 2 fuel oil, No. 6 oil, high-Btu gas, medium-Btu gas, and low-Btu gas. Data provided for each distribution system include component makeup and initial costs.

  14. The hardware track finder processor in CMS at CERN

    CERN Document Server

    Kluge, A

    1997-01-01

    The work covers the design of the Track Finder Processor in the high energy experiment CMS (Compact Muon Solenoid, planned for 2005) at CERN/Geneva. The task of this processor is to identify muons and measure their transverse momentum. The track finder processor makes it possible to determine the physical relevance of each high energetic collision and to forward only interesting data to the data an alysis units. Data of more than two hundred thousand detector cells are used to determine the location of muons and measure their transverse momentum. Each 25 ns a new data set is generated. Measurem ent of location and transverse momentum of the muons can be terminated within 350 ns by using an ASIC (Application Specific Integrated Circuit). A pipeline architecture processes new data sets with th e required data rate of 40 MHz to ensure dead time free operation. In the framework of this study specifications and the overall concept of the track finder processor were worked out in detail. Simul ations were performed...

  15. Scientific programming on massively parallel processor CP-PACS

    Energy Technology Data Exchange (ETDEWEB)

    Boku, Taisuke [Tsukuba Univ., Ibaraki (Japan). Inst. of Information Sciences and Electronics

    1998-03-01

    The massively parallel processor CP-PACS takes various problems of calculation physics as the object, and it has been designed so that its architecture has been devised to do various numerical processings. In this report, the outline of the CP-PACS and the example of programming in the Kernel CG benchmark in NAS Parallel Benchmarks, version 1, are shown, and the pseudo vector processing mechanism and the parallel processing tuning of scientific and technical computation utilizing the three-dimensional hyper crossbar net, which are two great features of the architecture of the CP-PACS are described. As for the CP-PACS, the PUs based on RISC processor and added with pseudo vector processor are used. Pseudo vector processing is realized as the loop processing by scalar command. The features of the connection net of PUs are explained. The algorithm of the NPB version 1 Kernel CG is shown. The part that takes the time for processing most in the main loop is the product of matrix and vector (matvec), and the parallel processing of the matvec is explained. The time for the computation by the CPU is determined. As the evaluation of the performance, the evaluation of the time for execution, the short vector processing of pseudo vector processor based on slide window, and the comparison with other parallel computers are reported. (K.I.)

  16. Concurrent Smalltalk on the Message-Driven Processor

    Science.gov (United States)

    1991-09-01

    NDPSim -x 2 -y 2 - maize Ox1O00 ::Coamoa:Coamoa.m NewFact.mdp Message-Driven Processor Simulator Version 7.0 Rev B Accompanies MDP Architecture Document...it could peel invocations of recursive functions forever. However, the sin- gle pass of inlining does not mean that functions are only inlined one

  17. Digital signal processor and processing method for GPS receivers

    Science.gov (United States)

    Thomas, Jr., Jess B. (Inventor)

    1989-01-01

    A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

  18. PVM Enhancement for Beowulf Multiple-Processor Nodes

    Science.gov (United States)

    Springer, Paul

    2006-01-01

    A recent version of the Parallel Virtual Machine (PVM) computer program has been enhanced to enable use of multiple processors in a single node of a Beowulf system (a cluster of personal computers that runs the Linux operating system). A previous version of PVM had been enhanced by addition of a software port, denoted BEOLIN, that enables the incorporation of a Beowulf system into a larger parallel processing system administered by PVM, as though the Beowulf system were a single computer in the larger system. BEOLIN spawns tasks on (that is, automatically assigns tasks to) individual nodes within the cluster. However, BEOLIN does not enable the use of multiple processors in a single node. The present enhancement adds support for a parameter in the PVM command line that enables the user to specify which Internet Protocol host address the code should use in communicating with other Beowulf nodes. This enhancement also provides for the case in which each node in a Beowulf system contains multiple processors. In this case, by making multiple references to a single node, the user can cause the software to spawn multiple tasks on the multiple processors in that node.

  19. FPGA Based Intelligent Co-operative Processor in Memory Architecture

    DEFF Research Database (Denmark)

    Ahmed, Zaki; Sotudeh, Reza; Hussain, Dil Muhammad Akbar

    2011-01-01

    In a continuing effort to improve computer system performance, Processor-In-Memory (PIM) architecture has emerged as an alternative solution. PIM architecture incorporates computational units and control logic directly on the memory to provide immediate access to the data. To exploit the potentia...

  20. All-optical digital processor based on harmonic generation phenomena

    Science.gov (United States)

    Shcherbakov, Alexandre S.; Rakovsky, Vsevolod Y.

    1990-07-01

    Digital optical processors are designed to combine ultra- parallel data procesing capabilities of optical aystems cnd high accur&cy of performed computations. The ultimate limit of the processing rate can be anticipated from all-optical parcllel erchitecturea based on networks o logic gates using materials exibiting strong electronic nonlinearities with response times less than 1O seconds1.

  1. MGSim - simulation tools for multi-core processor architectures

    NARCIS (Netherlands)

    Lankamp, M.; Poss, R.; Yang, Q.; Fu, J.; Uddin, I.; Jesshope, C.R.

    2013-01-01

    MGSim is an open source discrete event simulator for on-chip hardware components, developed at the University of Amsterdam. It is intended to be a research and teaching vehicle to study the fine-grained hardware/software interactions on many-core and hardware multithreaded processors. It includes su

  2. Interactive high-resolution isosurface ray casting on multicore processors.

    Science.gov (United States)

    Wang, Qin; JaJa, Joseph

    2008-01-01

    We present a new method for the interactive rendering of isosurfaces using ray casting on multi-core processors. This method consists of a combination of an object-order traversal that coarsely identifies possible candidate 3D data blocks for each small set of contiguous pixels, and an isosurface ray casting strategy tailored for the resulting limited-size lists of candidate 3D data blocks. While static screen partitioning is widely used in the literature, our scheme performs dynamic allocation of groups of ray casting tasks to ensure almost equal loads among the different threads running on multi-cores while maintaining spatial locality. We also make careful use of memory management environment commonly present in multi-core processors. We test our system on a two-processor Clovertown platform, each consisting of a Quad-Core 1.86-GHz Intel Xeon Processor, for a number of widely different benchmarks. The detailed experimental results show that our system is efficient and scalable, and achieves high cache performance and excellent load balancing, resulting in an overall performance that is superior to any of the previous algorithms. In fact, we achieve an interactive isosurface rendering on a 1024(2) screen for all the datasets tested up to the maximum size of the main memory of our platform.

  3. Processor Management in the Tera MTA Computer System,

    Science.gov (United States)

    1993-01-01

    This paper describes the processor scheduling issues specific to the Tera MTA (Multi Threaded Architecture) computer system and presents solutions to...classic scheduling problems. The Tera MTA exploits parallelism at all levels, from fine-grained instruction-level parallelism within a single

  4. Effective Utilization of Multicore Processor for Unified Threat Management Functions

    Directory of Open Access Journals (Sweden)

    Radhakrishnan Shanmugasundaram

    2012-01-01

    Full Text Available Problem statement: Multicore and multithreaded CPUs have become the new approach for increase in the performance of the processor based systems. Numerous applications benefit from use of multiple cores. Unified threat management is one such application that has multiple functions to be implemented at high speeds. Increasing performance of the system by knowing the nature of the functionality and effective utilization of multiple processors for each of the functions warrants detailed experimentation. In this study, some of the functions of Unified Threat Management are implemented using multiple processors for each of the functions. Approach: This evaluation was conducted on SunfireT1000 server having Sun Ultras ARC T1 multicore processor. OpenMP parallelization methods are used for scheduling the logical CPUs for the parallelized application. Results: Execution time for some of the UTM functions implemented was analyzed to arrive at an effective allocation and parallelization methodology that is dependent on the hardware and the workload. Conclusion/Recommendations: Based on the analysis, the type of parallelization method for the implemented UTM functions are suggested.

  5. A 16-Bit Fully Functional Single Cycle Processor

    Directory of Open Access Journals (Sweden)

    Nidhi Maheshwari

    2011-08-01

    Full Text Available The existing commercial microprocessors are provided as black box units, with which users are unable to monitor internal signals and operation process, neither can they modify the original structure. Inorder to solve this problem 16-bit fully functional single cycle processor is designed in terms of its architecture and its functional capabilities. The procedure of design and verification for a 16-bit processor is introduced in this paper. The key architecture elements are being described, as well as the hardware block diagram and internal structure. The summary of instruction set is presented. This processor is modify as a Very High Speed Integrated Circuit Hardware Description Language (VHDL and gives access to every internal signal. In order to consume fewer resources, the design of arithmetic logical unit (ALU is optimized. The RTL views and verified simulation results of processor are shown in this paper. The synthesis report of the design is also described. The design architecture is written in Very High Speed Integrated Circuit Hardware Description Language (VHDL code using Xilinx ISE 9.2i tool for synthesis and simulation.

  6. Processor-sharing queues and resource sharing in wireless LANs

    NARCIS (Netherlands)

    Cheung, Sing Kwong

    2007-01-01

    In the past few decades, the processor-sharing (PS) model has received considerable attention in the queueing theory community and in the field of performance evaluation of computer and communication systems. The scarce resource is simultaneously shared among all users in these systems. PS models ar

  7. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

    Science.gov (United States)

    Sharma, Anuj; Manolakos, Elias S

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

  8. Fast 2D-DCT implementations for VLIW processors

    OpenAIRE

    Sohm, OP; Canagarajah, CN; Bull, DR

    1999-01-01

    This paper analyzes various fast 2D-DCT algorithms regarding their suitability for VLIW processors. Operations for truncation or rounding which are usually neglected in proposals for fast algorithms have also been taken into consideration. Loeffler's algorithm with parallel multiplications was found to be most suitable due to its parallel structure

  9. A Digital Data Processor for Synthetic Aperture Radar

    NARCIS (Netherlands)

    Vlothuizen, W.J.; Medenblik, H.J.W.

    2007-01-01

    This paper presents a Digital Data Processor (DDP) for Synthetic Aperture Radar (SAR). The DDP captures SAR data at a 1 GHz sample rate and processes data at 350 MB/s. Data reduction is performed by a digital down converter, programmable decimating filter and a fully programmable presummer. The tota

  10. The Danish real-time SAR processor: first results

    DEFF Research Database (Denmark)

    Dall, Jørgen; Jørgensen, Jørn Hjelm; Netterstrøm, Anders;

    1993-01-01

    A real-time processor (RTP) for the Danish airborne Synthetic Aperture Radar (SAR) has been designed and constructed at the Electromagnetics Institute. The implementation was completed in mid 1992, and since then the RTP has been operated successfully on several test and demonstration flights...

  11. FPGA Based Intelligent Co-operative Processor in Memory Architecture

    DEFF Research Database (Denmark)

    Ahmed, Zaki; Sotudeh, Reza; Hussain, Dil Muhammad Akbar

    2011-01-01

    In a continuing effort to improve computer system performance, Processor-In-Memory (PIM) architecture has emerged as an alternative solution. PIM architecture incorporates computational units and control logic directly on the memory to provide immediate access to the data. To exploit the potential...

  12. Two new directions in speech processor design for cochlear implants.

    Science.gov (United States)

    Wilson, Blake S; Schatzer, Reinhold; Lopez-Poveda, Enrique A; Sun, Xiaoan; Lawson, Dewey T; Wolford, Robert D

    2005-08-01

    Two new approaches to the design of speech processors for cochlear implants are described. The first aims to represent "fine structure" or "fine frequency" information in a way that it can be perceived and used by patients, and the second aims to provide a closer mimicking than was previously possible of the signal processing that occurs in the normal cochlea.

  13. The LOGO Processor; A Guide for System Programmers.

    Science.gov (United States)

    Weiner, Walter B.; And Others

    A detailed specification of the LOGO programing system is given. The level of description is intended to enable system programers to design LOGO processors of their own. The discussion of storage allocation and garbage collection algorithms is virtually complete. An annotated LOGO system listing for the PDP-10 computer system may be obtained on…

  14. A Software Implementation of a Satellite Interface Message Processor.

    Science.gov (United States)

    Eastwood, Margaret A.; Eastwood, Lester F., Jr.

    A design for network control software for a computer network is described in which some nodes are linked by a communications satellite channel. It is assumed that the network has an ARPANET-like configuration; that is, that specialized processors at each node are responsible for message switching and network control. The purpose of the control…

  15. Performance evaluation of H.264 decoder on different processors

    Directory of Open Access Journals (Sweden)

    H.S.Prasantha

    2010-08-01

    Full Text Available H.264/AVC (Advanced Video Coding is the newest video coding standard of the moving video coding experts group. The decoder is standardized by imposing restrictions on the bit stream and syntax, and defining the process of decoding syntax elements such that every decoder conforming to the standard will produce similar output when encoded bit stream is provided as input. It uses state of art coding tools and provides enhanced coding efficiency for a wide range of applications, including video telephony, real-time video conferencing, direct-broadcast TV (television, blue-ray disc, DVB (Digital video broadcast broadcast, streaming video and others. The paper proposes to port the H.264/AVC decoder on the various processors such as TI DSP (Digital signal processor, ARM (Advanced risk machines and P4 (Pentium processors. The paper also proposesto analyze and compare Video Quality Metrics for different encoded video sequences. The paper proposes to investigate the decoder performance on different processors with and without deblocking filter and compare the performance based on different video quality measures.

  16. Optical linear algebra processors: noise and error-source modeling.

    Science.gov (United States)

    Casasent, D; Ghosh, A

    1985-06-01

    The modeling of system and component noise and error sources in optical linear algebra processors (OLAP's) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.

  17. Optical linear algebra processors - Noise and error-source modeling

    Science.gov (United States)

    Casasent, D.; Ghosh, A.

    1985-01-01

    The modeling of system and component noise and error sources in optical linear algebra processors (OLAPs) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.

  18. Multi-Constraint multi-processor Resource Allocation

    NARCIS (Netherlands)

    Behrouzian, A.R.B.; Goswami, D.; Basten, T.; Geilen, M.; Ara, H.A.

    2015-01-01

    This work proposes a Multi-Constraint Resource Allocation (MuCoRA) method for applications from multiple domains onto multi-processors. In particular, we address a mapping problem for multiple throughput-constrained streaming applications and multiple latency-constrained feedback control application

  19. Evaluation of the Intel Westmere-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing the 6-core “Westmere-EP” processor with Intel’s previous generation of the same microarchitecture, the “Nehalem-EP”. The former is produced in a new 32nm process, the latter in 45nm. Both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Simultaneous Multi-Threading (SMT), the cache sizes available, the memory configuration installed, as well...

  20. Evaluation of the Intel Nehalem-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

  1. Compact surface plasmonic waveguide component for integrated optical processor

    Science.gov (United States)

    Gogoi, Nilima; Sahu, Partha Pratim

    2015-06-01

    A compact surface plasmonic two mode interference waveguide component having silicon core and silver and GaAsInP side cladding is proposed for optical processor elements. Coupling operation is obtained by using index modulation of GaAsInP cladding with applied optical pulse.

  2. Security Checkers: Detecting Processor Malicious Inclusions at Runtime

    Science.gov (United States)

    2011-01-01

    OpenCores, http://opencores.org/. [5] AMD Processors Undocumented Debugging Features and MSRs, http://www.woodmann.com/forum/archive/index.php/t-13891...Vision for Semiconductor Failure Analysis, http://www.xradia.com/company/news/press-releases/2010-12-01. php , December 2010. [9] Abarbanel, Beer

  3. JV 38-APPLICATION OF COFIRING AND COGENERATION FOR SOUTH DAKOTA SOYBEAN PROCESSORS

    Energy Technology Data Exchange (ETDEWEB)

    Darren D. Schmidt

    2002-11-01

    Cogeneration of heat and electricity is being considered by the South Dakota Soybean Processors for its facility in Volga, South Dakota, and a new facility to be located in Brewster, Minnesota. The Energy & Environmental Research Center has completed a feasibility study, with 40% funding provided from the U.S. Department of Energy's Jointly Sponsored Research Program to determine the potential application of firing biomass fuels combined with coal and comparative economics of natural gas-fired turbines. Various biomass fuels are available at each location. The most promising options based on availability are as follows. The economic impact of firing 25% biomass with coal can increase return on investment by 0.5 to 1.5 years when compared to firing natural gas. The results of the comparative economics suggest that a fluidized-bed cogeneration system will have the best economic performance. Installation for the Brewster site is recommended based on natural gas prices not dropping below a $4.00/MMBtu annual average delivered cost. Installation at the Volga site is only recommended if natural gas prices substantially increase to $5.00/MMBtu on average. A 1- to 2-year time frame will be needed for permitting and equipment procurement.

  4. Real-time optical processor prototype for remote SAR applications

    Science.gov (United States)

    Marchese, Linda; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Bourqui, Pascal; Legros, Mathieu; Desnoyers, Nichola; Guillot, Ludovic; Mercier, Luc; Savard, Maxime; Martel, Anne; Châteauneuf, François; Bergeron, Alain

    2009-09-01

    A Compact Real-Time Optical SAR Processor has been successfully developed and tested. SAR, or Synthetic Aperture Radar, is a powerful tool providing enhanced day and night imaging capabilities. SAR systems typically generate large amounts of information generally in the form of complex data that are difficult to compress. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Indeed, the first SAR images have been optically processed. The optical processor architecture provides inherent parallel computing capabilities that can be used advantageously for the SAR data processing. Onboard SAR image generation would provide local access to processed information paving the way for real-time decision-making. This could eventually benefit navigation strategy and instrument orientation decisions. Moreover, for interplanetary missions, onboard analysis of images could provide important feature identification clues and could help select the appropriate images to be transmitted to Earth, consequently helping bandwidth management. This could ultimately reduce the data throughput requirements and related transmission bandwidth. This paper reviews the design of a compact optical SAR processor prototype that would reduce power, weight, and size requirements and reviews the analysis of SAR image generation using the table-top optical processor. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and size are reviewed. Results of image generation from simulated point targets as well as real satellite-acquired raw data are presented.

  5. A programmable sound processor for advanced hearing aid research.

    Science.gov (United States)

    McDermott, H

    1998-03-01

    A portable sound processor has been developed to facilitate research on advanced hearing aids. Because it is based on a digital signal processing integrated circuit (Motorola DSP56001), it can readily be programmed to execute novel algorithms. Furthermore, the parameters of these algorithms can be adjusted quickly and easily to suit the specific hearing characteristics of users. In the processor, microphone signals are digitized to a precision of 12 bits at a sampling rate of approximately 12 kHz for input to the DSP device. Subsequently, processed samples are delivered to the earphone by a novel, fully-digital class-D driver. This driver provides the advantages of a conventional class-D amplifier (high maximum output, low power consumption, low distortion) without some of the disadvantages (such as the need for precise analog circuitry). In addition, a cochlear implant driver is provided so that the processor is suitable for hearing-impaired people who use an implant and an acoustic hearing aid together. To reduce the computational demands on the DSP device, and therefore the power consumption, a running spectral analysis of incoming signals is provided by a custom-designed switched-capacitor integrated circuit incorporating 20 bandpass filters. The complete processor is pocket-sized and powered by batteries. An example is described of its use in providing frequency-shaped amplification for aid users with severe hearing impairment. Speech perception tests confirmed that the processor performed significantly better than the subjects' own hearing aids, probably because the digital filter provided a frequency response generally closer to the optimum for each user than the simpler analog aids.

  6. Updated NGNP Fuel Acquisition Strategy

    Energy Technology Data Exchange (ETDEWEB)

    David Petti; Tim Abram; Richard Hobbins; Jim Kendall

    2010-12-01

    A Next Generation Nuclear Plant (NGNP) fuel acquisition strategy was first established in 2007. In that report, a detailed technical assessment of potential fuel vendors for the first core of NGNP was conducted by an independent group of international experts based on input from the three major reactor vendor teams. Part of the assessment included an evaluation of the credibility of each option, along with a cost and schedule to implement each strategy compared with the schedule and throughput needs of the NGNP project. While credible options were identified based on the conditions in place at the time, many changes in the assumptions underlying the strategy and in externalities that have occurred in the interim requiring that the options be re-evaluated. This document presents an update to that strategy based on current capabilities for fuel fabrication as well as fuel performance and qualification testing worldwide. In light of the recent Pebble Bed Modular Reactor (PBMR) project closure, the Advanced Gas Reactor (AGR) fuel development and qualification program needs to support both pebble and prismatic options under the NGNP project. A number of assumptions were established that formed a context for the evaluation. Of these, the most important are: • Based on logistics associated with the on-going engineering design activities, vendor teams would start preliminary design in October 2012 and complete in May 2014. A decision on reactor type will be made following preliminary design, with the decision process assumed to be completed in January 2015. Thus, no fuel decision (pebble or prismatic) will be made in the near term. • Activities necessary for both pebble and prismatic fuel qualification will be conducted in parallel until a fuel form selection is made. As such, process development, fuel fabrication, irradiation, and testing for pebble and prismatic options should not negatively influence each other during the period prior to a decision on reactor type

  7. Architecture-level performance/power tradeoff in network processor design

    Institute of Scientific and Technical Information of China (English)

    CHEN Hong-song; JI Zhen-zhou; HU Ming-zeng

    2007-01-01

    Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. Architecture-level power conscious design must go beyond low-level circuit design. Architectural power and performance tradeoff should be considered at the same time. Simulation is an efficient method to design modern network processor before making chip. In order to achieve the tradeoff between performance and power,the processor simulator is used to design the architecture of network processor. Using Netbench, Commubench benchmark and processor simulator-SimpleScalar, the performance and power of network processor are quantitatively evaluated. New performance tradeoff evaluation metric is proposed to analyze the architecture of network processor. Based on the high performance Intel IXP 2800 Network processor configuration, optimized instruction fetch width and speed 、instruction issue width, instruction window size are analyzed and selected. Simulation results show that the tradeoff design method makes the usage of network processor more effectively. The optimal key parameters of network processor are important in architecture-level design. It is meaningful for the next generation network processor design.

  8. 77 FR 124 - Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement

    Science.gov (United States)

    2012-01-03

    ... AGENCY Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement AGENCY... Biological Processors of Alabama Superfund Site located in Decatur, Morgan County, Alabama. DATES: The Agency... name Biological Processors of Alabama Superfund Site by one of the following methods:...

  9. Externally Verifiable Oblivious RAM

    Directory of Open Access Journals (Sweden)

    Gancher Joshua

    2017-04-01

    Full Text Available We present the idea of externally verifiable oblivious RAM (ORAM. Our goal is to allow a client and server carrying out an ORAM protocol to have disputes adjudicated by a third party, allowing for the enforcement of penalties against an unreliable or malicious server. We give a security definition that guarantees protection not only against a malicious server but also against a client making false accusations. We then give modifications of the Path ORAM [15] and Ring ORAM [9] protocols that meet this security definition. These protocols both have the same asymptotic runtimes as the semi-honest original versions and require the external verifier to be involved only when the client or server deviates from the protocol. Finally, we implement externally verified ORAM, along with an automated cryptocurrency contract to use as the external verifier.

  10. External Beam Therapy (EBT)

    Science.gov (United States)

    ... Esophageal Cancer Treatment Head and Neck Cancer Treatment Lung Cancer Treatment Prostate Cancer Treatment Brain Tumor Treatment Why is ... Radiation Oncology) Breast Cancer Treatment Esophageal Cancer Treatment Lung Cancer Treatment Images related to External Beam Therapy (EBT) Sponsored ...

  11. MALIGNANT EXTERNAL OTITIS

    OpenAIRE

    Massoud Moghaddam

    1993-01-01

    Two case reports of malignant external otitis in the elderly diabetics and their complications and management with regard to our experience at Amir Alam Hospital, Department of ENT will be discussed here.

  12. Checklists for external validity

    DEFF Research Database (Denmark)

    Dyrvig, Anne-Kirstine; Kidholm, Kristian; Gerke, Oke;

    2014-01-01

    RATIONALE, AIMS AND OBJECTIVES: The quality of the current literature on external validity varies considerably. An improved checklist with validated items on external validity would aid decision-makers in judging similarities among circumstances when transferring evidence from a study setting...... to an implementation setting. In this paper, currently available checklists on external validity are identified, assessed and used as a basis for proposing a new improved instrument. METHOD: A systematic literature review was carried out in Pubmed, Embase and Cinahl on English-language papers without time restrictions....... The retrieved checklist items were assessed for (i) the methodology used in primary literature, justifying inclusion of each item; and (ii) the number of times each item appeared in checklists. RESULTS: Fifteen papers were identified, presenting a total of 21 checklists for external validity, yielding a total...

  13. Market penetration scenarios for fuel cell vehicles

    Energy Technology Data Exchange (ETDEWEB)

    Thomas, C.E.; James, B.D.; Lomax, F.D. Jr. [Directed Technologies, Inc., Arlington, VA (United States)

    1997-12-31

    Fuel cell vehicles may create the first mass market for hydrogen as an energy carrier. Directed Technologies, Inc., working with the US Department of Energy hydrogen systems analysis team, has developed a time-dependent computer market penetration model. This model estimates the number of fuel cell vehicles that would be purchased over time as a function of their cost and the cost of hydrogen relative to the costs of competing vehicles and fuels. The model then calculates the return on investment for fuel cell vehicle manufacturers and hydrogen fuel suppliers. The model also projects the benefit/cost ratio for government--the ratio of societal benefits such as reduced oil consumption, reduced urban air pollution and reduced greenhouse gas emissions to the government cost for assisting the development of hydrogen energy and fuel cell vehicle technologies. The purpose of this model is to assist industry and government in choosing the best investment strategies to achieve significant return on investment and to maximize benefit/cost ratios. The model can illustrate trends and highlight the sensitivity of market penetration to various parameters such as fuel cell efficiency, cost, weight, and hydrogen cost. It can also illustrate the potential benefits of successful R and D and early demonstration projects. Results will be shown comparing the market penetration and return on investment estimates for direct hydrogen fuel cell vehicles compared to fuel cell vehicles with onboard fuel processors including methanol steam reformers and gasoline partial oxidation systems. Other alternative fueled vehicles including natural gas hybrids, direct injection diesels and hydrogen-powered internal combustion hybrid vehicles will also be analyzed.

  14. Fuel Cell/Reformers Technology Development

    Science.gov (United States)

    2004-01-01

    NASA Glenn Research Center is interested in developing Solid Oxide Fuel Cell for use in aerospace applications. Solid oxide fuel cell requires hydrogen rich feed stream by converting commercial aviation jet fuel in a fuel processing process. The grantee's primary research activities center on designing and constructing a test facility for evaluating injector concepts to provide optimum feeds to fuel processor; collecting and analyzing literature information on fuel processing and desulfurization technologies; establishing industry and academic contacts in related areas; providing technical support to in-house SOFC-based system studies. Fuel processing is a chemical reaction process that requires efficient delivery of reactants to reactor beds for optimum performance, i.e., high conversion efficiency and maximum hydrogen production, and reliable continuous operation. Feed delivery and vaporization quality can be improved by applying NASA's expertise in combustor injector design. A 10 KWe injector rig has been designed, procured, and constructed to provide a tool to employ laser diagnostic capability to evaluate various injector concepts for fuel processing reactor feed delivery application. This injector rig facility is now undergoing mechanical and system check-out with an anticipated actual operation in July 2004. Multiple injector concepts including impinging jet, venturi mixing, discrete jet, will be tested and evaluated with actual fuel mixture compatible with reforming catalyst requirement. Research activities from September 2002 to the closing of this collaborative agreement have been in the following areas: compiling literature information on jet fuel reforming; conducting autothermal reforming catalyst screening; establishing contacts with other government agencies for collaborative research in jet fuel reforming and desulfurization; providing process design basis for the build-up of injector rig facility and individual injector design.

  15. Fuel Cells

    DEFF Research Database (Denmark)

    Smith, Anders; Pedersen, Allan Schrøder

    2014-01-01

    Fuel cells have been the subject of intense research and development efforts for the past decades. Even so, the technology has not had its commercial breakthrough yet. This entry gives an overview of the technological challenges and status of fuel cells and discusses the most promising applications...... of the different types of fuel cells. Finally, their role in a future energy supply with a large share of fluctuating sustainable power sources, e.g., solar or wind, is surveyed....

  16. Migration with fiscal externalities.

    Science.gov (United States)

    Hercowitz, Z; Pines, D

    1991-11-01

    "This paper analyses the distribution of a country's population among regions when migration involves fiscal externalities. The main question addressed is whether a decentralized decision making [by] regional governments can produce an optimal population distribution...or a centralized intervention is indispensable, as argued before in the literature.... It turns out that, while with costless mobility the fiscal externality is fully internalized by voluntary interregional transfers, with costly mobility, centrally coordinated transfers still remain indispensable for achieving the socially optimal allocation."

  17. Sen cycles and externalities

    OpenAIRE

    Piggins, Ashley; Salerno, Gillian

    2016-01-01

    It has long been understood that externalities of some kind are responsible for Sen’s (1970) theorem on the impossibility of a Paretian liberal. However, Saari and Petron (2006) show that for any social preference cycle generated by combining the weak Pareto principle and individual decisiveness, every decisive individual must suffer at least one strong negative externality. We show that this fundamental result only holds when individual preferences are strict. Building on their contribution,...

  18. Assessment of environmental external effects in the production of energy

    DEFF Research Database (Denmark)

    Schleisner, L.; Meyer, H.J.; Morthorst, P.E.

    1995-01-01

    A project in Denmark has been carried out with the purpose to assess the environmental damages and the external costs in the production of energy. The energy production technologies that will be reported in this paper are wind power and a conventional coal fired plant. In the project...... the environmental damages for the energy production technologies are compared, and externalities in the production of energy using renewable energy and fossil fuels are identified, estimated and monetized....

  19. Autonomous sensors. Microsensors without external power supply and with remote signal processing; Energieautarke Sensorik. Mikrosensorik mit autarker Energieversorgung und drahtloser Signaluebertragung

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-07-01

    The workshop discussed the development perspectives of future applications and implementation problems of autonomous sensors and microsystems for remote data acquisition and exchange without external power supply. The following subjects were discussed in 14 papers: Wireless power and signal transmission; Integrated power supply; Batteries and battery management; Radiocommunication systems for sensors; Coil-on chip for sensors; Transponder technology and development trends; Small fuel cells for mobile applications; Development trends in fuel cells; The world of nanotechnology; Inductive power and data transmission; Sensor systems for tele-rehabilitation; Self-learning systems in cardiac electrotherapy; Sensor processor for transponder applications in autonomous systems without external power supply; One-chip CMOS pressure sensor system with wireless power and data transmission. [German] Dieser Workshop-Band befasst sich mit den Entwicklungsperspektiven, zukuenftigen Anwendungen und Umsetzungsproblemen der energieautarken Sensor- oder Mikrosysteme, die drahtlos mit minimalem Aufwand Daten erfassen und Informationen austauschen. Die Themen der 14 Beitraege, die teilweise Vortragsfolien enthalten, sind: Drahtlose Energie- und Signaluebertragung (M. Klein); integrierte Energieversorgung (J. Pelka); Batterien und Batterie-Management (A. Jossen); Funksysteme fuer die Sensorik (H. Borkes); Coil-on-Chip fuer die Sensorik (G. Daalmans); Transpondertechnik und Entwicklungstendenzen (A. Miessner); kleine Brennstoffzellen fuer den mobilen Einsatz (A. Heinzel); Entwicklungstendenzen bei Brennstoffzellen (L. Joerissen); die Welt der Nanotechnologie (U. Koenig); induktive Leistungs- und Datenuebertragung (H. Bercher); Sensorsysteme fuer die Tele-Rehabilitation (D. Tietze/K.-U. Schmidt); selbstlernende Systeme in der Elektrotherapie des Herzens (M. Schaldach); Sensorprozessor fuer Transponderanwendungen in energieautarken Systemen (H. Graetz); Ein-Chip CMOS-Drucksensor-System mit

  20. Programmable retinal dynamics in a CMOS mixed-signal array processor chip

    Science.gov (United States)

    Carmona, Ricardo A.; Jimenez-Garrido, Francisco J.; Dominguez-Castro, Rafael; Espejo, Servando; Rodriguez-Vazquez, Angel

    2003-04-01

    The retina is responsible of the treatment of visual information at early stages. Visual stimuli generate patterns of activity that are transmitted through its layered structure up to the ganglion cells that interface it to the optical nerve. In this trip of micrometers, information is sustained by continuous signals that interact in excitatory and inhibitory ways. This low-level processing compresses the relevant information of the images to a manageable size. The behavior of the more external layers of the biological retina has been successfully modelled within the Cellular Neural Network framework. Interactions between cells are realized on a local basic. Each cell interacts with its nearest neighbors and every cell in the same layer follows the same interconnection pattern. Intra- and inter-layer interactions are continuous in magnitude and time. The evolution of the network can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. A CMOS Programmable Array Processor prototype chip has been designed and fabricated in a standard technology. It has been successfully tested, validating the proposed design techniques. The integrated system consists of a network of 2 coupled layers, containing 32×32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnection weights, internally coded as analog but programmed via a digital interface. Propagative, active wave phenomena and retina-lake effects can be observed in this chip. Low-level image processing tasks for early vision applications can be developed based on these high-order dynamics.

  1. FPGA-Based Reconfigurable Processor for Ultrafast Interlaced Ultrasound and Photoacoustic Imaging

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2016-01-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models. PMID:22828830

  2. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

  3. QPACE -- a QCD parallel computer based on Cell processors

    CERN Document Server

    Baier, H; Drochner, M; Eicker, N; Fischer, U; Fodor, Z; Frommer, A; Gomez, C; Goldrian, G; Heybrock, S; Hierl, D; Hüsken, M; Huth, T; Krill, B; Lauritsen, J; Lippert, T; Maurer, T; Meyer, N; Nobile, A; Ouda, I; Pivanti, M; Pleiter, D; Schäfer, A; Schick, H; Schifano, F; Simma, H; Solbrig, S; Streuer, T; Sulanke, K -H; Tripiccione, R; Vogt, J -S; Wettig, T; Winter, F

    2009-01-01

    QPACE is a novel parallel computer which has been developed to be primarily used for lattice QCD simulations. The compute power is provided by the IBM PowerXCell 8i processor, an enhanced version of the Cell processor that is used in the Playstation 3. The QPACE nodes are interconnected by a custom, application optimized 3-dimensional torus network implemented on an FPGA. To achieve the very high packaging density of 26 TFlops per rack a new water cooling concept has been developed and successfully realized. In this paper we give an overview of the architecture and highlight some important technical details of the system. Furthermore, we provide initial performance results and report on the installation of 8 QPACE racks providing an aggregate peak performance of 200 TFlops.

  4. SPP: A data base processor data communications protocol

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

  5. Formal design specification of a Processor Interface Unit

    Science.gov (United States)

    Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

    1992-01-01

    This report describes work to formally specify the requirements and design of a processor interface unit (PIU), a single-chip subsystem providing memory-interface bus-interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. The need for high-quality design assurance in such applications is an undisputed fact, given the disastrous consequences that even a single design flaw can produce. Thus, the further development and application of formal methods to fault-tolerant systems is of critical importance as these systems see increasing use in modern society.

  6. Programming massively parallel processors a hands-on approach

    CERN Document Server

    Kirk, David B

    2010-01-01

    Programming Massively Parallel Processors discusses basic concepts about parallel programming and GPU architecture. ""Massively parallel"" refers to the use of a large number of processors to perform a set of computations in a coordinated parallel way. The book details various techniques for constructing parallel programs. It also discusses the development process, performance level, floating-point format, parallel patterns, and dynamic parallelism. The book serves as a teaching guide where parallel programming is the main topic of the course. It builds on the basics of C programming for CUDA, a parallel programming environment that is supported on NVI- DIA GPUs. Composed of 12 chapters, the book begins with basic information about the GPU as a parallel computer source. It also explains the main concepts of CUDA, data parallelism, and the importance of memory access efficiency using CUDA. The target audience of the book is graduate and undergraduate students from all science and engineering disciplines who ...

  7. Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures

    Directory of Open Access Journals (Sweden)

    Ausif Mahmood

    1996-01-01

    Full Text Available The development of multi-processor architectures requires extensive behavioral simulations to verify the correctness of design and to evaluate its performance. A high level language can provide maximum flexibility in this respect if the constructs for handling concurrent processes and a time mapping mechanism are added. This paper describes a novel technique for emulating hardware processes involved in a parallel architecture such that an object-oriented description of the design is maintained. The communication and synchronization between hardware processes is handled by splitting the processes into their equivalent subprograms at the entry points. The proper scheduling of these subprograms is coordinated by a timing wheel which provides a time mapping mechanism. Finally, a high level language pre-processor is proposed so that the timing wheel and the process emulation details can be made transparent to the user.

  8. ASIC Design of Floating-Point FFT Processor

    Institute of Scientific and Technical Information of China (English)

    陈禾; 赵忠武

    2004-01-01

    An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

  9. An optical processor for object recognition and tracking

    Science.gov (United States)

    Sloan, J.; Udomkesmalee, S.

    1987-01-01

    The design and development of a miniaturized optical processor that performs real time image correlation are described. The optical correlator utilizes the Vander Lugt matched spatial filter technique. The correlation output, a focused beam of light, is imaged onto a CMOS photodetector array. In addition to performing target recognition, the device also tracks the target. The hardware, composed of optical and electro-optical components, occupies only 590 cu cm of volume. A complete correlator system would also include an input imaging lens. This optical processing system is compact, rugged, requires only 3.5 watts of operating power, and weighs less than 3 kg. It represents a major achievement in miniaturizing optical processors. When considered as a special-purpose processing unit, it is an attractive alternative to conventional digital image recognition processing. It is conceivable that the combined technology of both optical and ditital processing could result in a very advanced robot vision system.

  10. Parallel processor simulator for multiple optic channel architectures

    Science.gov (United States)

    Wailes, Tom S.; Meyer, David G.

    1992-12-01

    A parallel processing architecture based on multiple channel optical communication is described and compared with existing interconnection strategies for parallel computers. The proposed multiple channel architecture (MCA) uses MQW-DBR lasers to provide a large number of independent, selectable channels (or virtual buses) for data transport. Arbitrary interconnection patterns as well as machine partitions can be emulated via appropriate channel assignments. Hierarchies of parallel architectures and simultaneous execution of parallel tasks are also possible. Described are a basic overview of the proposed architecture, various channel allocation strategies that can be utilized by the MCA, and a summary of advantages of the MCA compared with traditional interconnection techniques. Also describes is a comprehensive multiple processor simulator that has been developed to execute parallel algorithms using the MCA as a data transport mechanism between processors and memory units. Simulation results -- including average channel load, effective channel utilization, and average network latency for different algorithms and different transmission speeds -- are also presented.

  11. Ingredients of Adaptability: A Survey of Reconfigurable Processors

    Directory of Open Access Journals (Sweden)

    Anupam Chattopadhyay

    2013-01-01

    Full Text Available For a design to survive unforeseen physical effects like aging, temperature variation, and/or emergence of new application standards, adaptability needs to be supported. Adaptability, in its complete strength, is present in reconfigurable processors, which makes it an important IP in modern System-on-Chips (SoCs. Reconfigurable processors have risen to prominence as a dominant computing platform across embedded, general-purpose, and high-performance application domains during the last decade. Significant advances have been made in many areas such as, identifying the advantages of reconfigurable platforms, their modeling, implementation flow and finally towards early commercial acceptance. This paper reviews these progresses from various perspectives with particular emphasis on fundamental challenges and their solutions. Empowered with the analysis of past, the future research roadmap is proposed.

  12. JIST: Just-In-Time Scheduling Translation for Parallel Processors

    Directory of Open Access Journals (Sweden)

    Giovanni Agosta

    2005-01-01

    Full Text Available The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures. We have implemented JIST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JITcompiler. Further optimizations are discussed.

  13. Biological Water Processor and Forward Osmosis Secondary Treatment

    Science.gov (United States)

    Shull, Sarah; Meyer, Caitlin

    2014-01-01

    The goal of the Biological Water Processor (BWP) is to remove 90% organic carbon and 75% ammonium from an exploration-based wastewater stream for four crew members. The innovative design saves on space, power and consumables as compared to the ISS Urine Processor Assembly (UPA) by utilizing microbes in a biofilm. The attached-growth system utilizes simultaneous nitrification and denitrification to mineralize organic carbon and ammonium to carbon dioxide and nitrogen gas, which can be scrubbed in a cabin air revitalization system. The BWP uses a four-crew wastewater comprised of urine and humidity condensate, as on the ISS, but also includes hygiene (shower, shave, hand washing and oral hygiene) and laundry. The BWP team donates 58L per day of this wastewater processed in Building 7.

  14. Investigating the Performance of an Adiabatic Quantum Optimization Processor

    CERN Document Server

    Rose, Geordie; Dickson, Neil G; Hamze, Firas; Amin, M H S; Drew-Brook, Marshall; Chudak, Fabian A; Bunyk, Paul I; Macready, William G

    2010-01-01

    We calculate median adiabatic times (in seconds) of a specific superconducting adiabatic quantum processor for an NP-hard Ising spin glass instance class with up to N=128 binary variables. To do so, we ran high performance Quantum Monte Carlo simulations on a large-scale Internet-based computing platform. We compare the median adiabatic times with the median running times of two classical solvers and find that, for problems with up to 128 variables, the adiabatic times for the simulated processor architecture are about 4 and 6 orders of magnitude shorter than the two classical solvers' times. This performance difference shows that, even in the potential absence of a scaling advantage, adiabatic quantum optimization may outperform classical solvers.

  15. Parallel information transfer in a multinode quantum information processor.

    Science.gov (United States)

    Borneman, T W; Granade, C E; Cory, D G

    2012-04-06

    We describe a method for coupling disjoint quantum bits (qubits) in different local processing nodes of a distributed node quantum information processor. An effective channel for information transfer between nodes is obtained by moving the system into an interaction frame where all pairs of cross-node qubits are effectively coupled via an exchange interaction between actuator elements of each node. All control is achieved via actuator-only modulation, leading to fast implementations of a universal set of internode quantum gates. The method is expected to be nearly independent of actuator decoherence and may be made insensitive to experimental variations of system parameters by appropriate design of control sequences. We show, in particular, how the induced cross-node coupling channel may be used to swap the complete quantum states of the local processors in parallel.

  16. A test vector generator for a radar signal processor

    Science.gov (United States)

    Robins, C. B.

    1991-02-01

    This report documents the test vector generator (TVG) system developed for the purpose of testing a radar signal processor. This system simulates an eight channel radar receiver by providing input data for testing the signal processor test bed. The TVG system outputs 128-bit wide data samples at variable rates up to and including 10 million samples per second. The VTG memory array is one million samples deep. Variably sized output vectors can be addressed within the memory array and the vectors can be concatenated, repeated, and reshuffled in real time under the control of a single board computer. The TVG is seen having applications on a variety of programs. Discussions of adapting and scaling the system to these other applications are presented.

  17. NMRFx Processor: a cross-platform NMR data processing program.

    Science.gov (United States)

    Norris, Michael; Fetler, Bayard; Marchant, Jan; Johnson, Bruce A

    2016-08-01

    NMRFx Processor is a new program for the processing of NMR data. Written in the Java programming language, NMRFx Processor is a cross-platform application and runs on Linux, Mac OS X and Windows operating systems. The application can be run in both a graphical user interface (GUI) mode and from the command line. Processing scripts are written in the Python programming language and executed so that the low-level Java commands are automatically run in parallel on computers with multiple cores or CPUs. Processing scripts can be generated automatically from the parameters of NMR experiments or interactively constructed in the GUI. A wide variety of processing operations are provided, including methods for processing of non-uniformly sampled datasets using iterative soft thresholding. The interactive GUI also enables the use of the program as an educational tool for teaching basic and advanced techniques in NMR data analysis.

  18. Dense and Sparse Matrix Operations on the Cell Processor

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Samuel W.; Shalf, John; Oliker, Leonid; Husbands,Parry; Yelick, Katherine

    2005-05-01

    The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. Therefore, the high performance computing community is examining alternative architectures that address the limitations of modern superscalar designs. In this work, we examine STI's forthcoming Cell processor: a novel, low-power architecture that combines a PowerPC core with eight independent SIMD processing units coupled with a software-controlled memory to offer high FLOP/s/Watt. Since neither Cell hardware nor cycle-accurate simulators are currently publicly available, we develop an analytic framework to predict Cell performance on dense and sparse matrix operations, using a variety of algorithmic approaches. Results demonstrate Cell's potential to deliver more than an order of magnitude better GFLOP/s per watt performance, when compared with the Intel Itanium2 and Cray X1 processors.

  19. Image processing algorithm acceleration using reconfigurable macro processor model

    Institute of Scientific and Technical Information of China (English)

    孙广富; 陈华明; 卢焕章

    2004-01-01

    The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of reconfigurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented.Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of "hardware" function that can be called by the DSP in high-level algorithm.It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.

  20. The fast tracker processor for hadron collider triggers

    CERN Document Server

    Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, E; Pietri, M; Varotto, G

    2001-01-01

    Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times. (15 refs).

  1. Implementing a Vector Controller Using 68k Processors

    Directory of Open Access Journals (Sweden)

    Mohammad Bagher

    2009-01-01

    Full Text Available Problem statement: This study described the design of a 3-phase AC Induction Motor (ACIM vector control drive with position encoder coupled to the motor shaft. Approach: It was based on free scale's (Motorola's 68k micro processor devices. Although the free scale 56F80x (56800 core and 56F8300 (56800E core families were well-suited for digital motor control and offer all things was needed, but we decided to realize a complete vector controller with a powerful 68k processor. Results: Obviously all 680X0 and many 683XX can overcome this task very easily, but we decided 68332 for time consuming because it combines high-performance data manipulation capabilities with powerful peripheral subsystems. All software and hardware was based on Peter J. Pinewski's nice research from Motorola. Conclusion: In this study the overall software algorithm and in two fellow papers the hardware schematics and performance will be described respectively.

  2. Distributing and Scheduling Divisible Task on Parallel Communicating Processors

    Institute of Scientific and Technical Information of China (English)

    李国东; 张德富

    2002-01-01

    In this paper we propose a novel scheme for scheduling divisible task onparallel processors connected by system interconnection network with arbitrary topology. Thedivisible task is a computation that can be divided into arbitrary independent subtasks solvedin parallel. Our model takes into consideration communication initial time and communicationdelays between processors. Moreover, by constructing the corresponding Network SpanningTree (NST) for a network, our scheme can be applied to all kinds of network topologies. Wepresent the concept of Balanced Task Distribution Tree and use it to design the Equation SetCreation Algorithm in which the set of linear equations is created by traversing the NST inpost-order. After solving the created equations, we get the optimal task assignment scheme.Experiments confirm the applicability of our scheme in real-life situations.

  3. In-Network Adaptation of Video Streams Using Network Processors

    Directory of Open Access Journals (Sweden)

    Mohammad Shorfuzzaman

    2009-01-01

    problem can be addressed, near the network edge, by applying dynamic, in-network adaptation (e.g., transcoding of video streams to meet available connection bandwidth, machine characteristics, and client preferences. In this paper, we extrapolate from earlier work of Shorfuzzaman et al. 2006 in which we implemented and assessed an MPEG-1 transcoding system on the Intel IXP1200 network processor to consider the feasibility of in-network transcoding for other video formats and network processor architectures. The use of “on-the-fly” video adaptation near the edge of the network offers the promise of simpler support for a wide range of end devices with different display, and so forth, characteristics that can be used in different types of environments.

  4. The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units

    CERN Document Server

    Tavares Delgado, Ademar; The ATLAS collaboration

    2016-01-01

    The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units Type: Talk Abstract: We present the ATLAS Trigger algorithms developed to exploit General­ Purpose Graphics Processor Units. ATLAS is a particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system has two levels, hardware-­based Level 1 and the High Level Trigger implemented in software running on a farm of commodity CPU. Performing the trigger event selection within the available farm resources presents a significant challenge that will increase future LHC upgrades. are being evaluated as a potential solution for trigger algorithms acceleration. Key factors determining the potential benefit of this new technology are the relative execution speedup, the number of GPUs required and the relative financial cost of the selected GPU. We have developed a trigger demonstrator which includes algorithms for reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Cal...

  5. The Potential of Turboprops to Reduce Aviation Fuel Consumption

    OpenAIRE

    2009-01-01

    Aviation system planning, particularly fleet selection and adoption, is challenged by fuel price uncertainty. Fuel price uncertainty is due fuel and energy price fluctuations and a growing awareness of the environmental externalities related to transportation activities, particularly as they relate to climate change. To assist in aviation systems planning under such fuel price uncertainty and environmental regulation, this study takes a total logistic cost approach and evaluates three represe...

  6. Environmental external effects from wind power based on the EU ExternE methodology

    DEFF Research Database (Denmark)

    Ibsen, Liselotte Schleisner; Nielsen, Per Sieverts

    1998-01-01

    The European Commission has launched a major study project, ExternE, to develop a methodology to quantify externalities. A “National Implementation Phase”, was started under the Joule II programme with the purpose of implementing the ExternE methodology in all member states. The main objective...

  7. Preliminary low temperature tests of a digital signal processor

    Science.gov (United States)

    Zebulum, Ricardo S.; Ramesham, Rajeshuni; Stoica, Adrian; Keymeulen, Didier; Daud, Taher; Sekanina, Lukas

    2005-01-01

    This paper describes an initial experiment performed to assess the electrical behavior of the Innovative Integration board containing a Digital Signal Processor (DSP) with its JTAG (Blackhawk) connector at low temperatures. The objective of the experiment is to determine the lowest temperature at which the DSP can operate. The DSP was tested at various low-temperatures and a Genetic Algorithm was used as the DSP test program.

  8. Floating-point array processors evolve into tailorable systems

    Energy Technology Data Exchange (ETDEWEB)

    Kotelly, G.

    1983-05-12

    Recently introduced 32-bit floating point array processors (APs) combine configuration flexibility, integrated hardware/software system architecture and real-time computational power to meet a variety of application requirements. APS have now evolved into general-purpose boxes and PC boards which readily adapt to changing OEM needs. Contributing to this greater AP versatility are a variety of hardware and software features. These features are described and the range of available products is surveyed.

  9. Real-Time Signal Processor for Pulsar Studies

    Indian Academy of Sciences (India)

    P. S. Ramkumar; A. A. Deshpande

    2001-12-01

    This paper describes the design, tests and preliminary results of a real-time parallel signal processor built to aid a wide variety of pulsar observations. The signal processor reduces the distortions caused by the effects of dispersion, Faraday rotation, doppler acceleration and parallactic angle variations, at a sustained data rate of 32 Msamples/sec. It also folds the pulses coherently over the period and integrates adjacent samples in time and frequency to enhance the signal-to-noise ratio. The resulting data are recorded for further off-line analysis of the characteristics of pulsars and the intervening medium. The signal processing for analysis of pulsar signals is quite complex, imposing the need for a high computational throughput, typically of the order of a Giga operations per second (GOPS). Conventionally, the high computational demand restricts the flexibility to handle only a few types of pulsar observations. This instrument is designed to handle a wide variety of Pulsar observations with the Giant Metre Wave Radio Telescope (GMRT), and is flexible enough to be used in many other high-speed, signal processing applications. The technology used includes field-programmable-gate-array(FPGA) based data/code routing interfaces, PC-AT based control, diagnostics and data acquisition, digital signal processor (DSP) chip based parallel processing nodes and C language based control software and DSP-assembly programs for signal processing. The architecture and the software implementation of the parallel processor are fine-tuned to realize about 60 MOPS per DSP node and a multiple-instruction-multiple-data (MIMD) capability.

  10. Environmental data processor of the adaptive intrusion data system

    Energy Technology Data Exchange (ETDEWEB)

    Rogers, M.S.

    1977-06-01

    A data acquisition system oriented specifically toward collection and processing of various meteorological and environmental parameters has been designed around a National Semiconductor IMP-16 microprocessor, This system, called the Environmental Data Processor (EDP), was developed specifically for use with the Adaptive Intrusion Data System (AIDS) in a perimeter intrusion alarm evaluation, although its design is sufficiently general to permit use elsewhere. This report describes in general detail the design of the EDP and its interaction with other AIDS components.

  11. High speed optical object recognition processor with massive holographic memory

    Science.gov (United States)

    Chao, T.; Zhou, H.; Reyes, G.

    2002-01-01

    Real-time object recognition using a compact grayscale optical correlator will be introduced. A holographic memory module for storing a large bank of optimum correlation filters, to accommodate the large data throughput rate needed for many real-world applications, has also been developed. System architecture of the optical processor and the holographic memory will be presented. Application examples of this object recognition technology will also be demonstrated.

  12. Implementation Of A Prototype Digital Optical Cellular Image Processor (DOCIP)

    Science.gov (United States)

    Huang, K. S.; Sawchuk, A. A.; Jenkins, B. K.; Chavel, P.; Wang, J. M.; Weber, A. G.; Wang, C. H.; Glaser, I.

    1989-02-01

    A processing element of a prototype digital optical cellular image processor (DOCIP) is implemented to demonstrate a particular parallel computing and interconnection architecture. This experimental digital optical computing system consists of a 2-D array of 54 optical logic gates, a 2-D array of 53 subholograms to provide interconnections between gates, and electronic input/output interfaces. The multi-facet interconnection hologram used in this system is fabricated by a computer-controlled optical system to offer very flexible interconnections.

  13. Reversible machine code and its abstract processor architecture

    DEFF Research Database (Denmark)

    Axelsen, Holger Bock; Glück, Robert; Yokoyama, Tetsuo

    2007-01-01

    A reversible abstract machine architecture and its reversible machine code are presented and formalized. For machine code to be reversible, both the underlying control logic and each instruction must be reversible. A general class of machine instruction sets was proven to be reversible, building ...... on our concept of reversible updates. The presentation is abstract and can serve as a guideline for a family of reversible processor designs. By example, we illustrate programming principles for the abstract machine architecture formalized in this paper....

  14. Fast Fourier Transform Co-Processor (FFTC)- Towards Embedded GFLOPs

    Science.gov (United States)

    Kuehl, Christopher; Liebstueckel, Uwe; Tejerina, Isaac; Uemminghaus, Michael; Wite, Felix; Kolb, Michael; Suess, Martin; Weigand, Roland

    2012-08-01

    Many signal processing applications and algorithms perform their operations on the data in the transform domain to gain efficiency. The Fourier Transform Co- Processor has been developed with the aim to offload General Purpose Processors from performing these transformations and therefore to boast the overall performance of a processing module. The IP of the commercial PowerFFT processor has been selected and adapted to meet the constraints of the space environment.In frame of the ESA activity “Fast Fourier Transform DSP Co-processor (FFTC)” (ESTEC/Contract No. 15314/07/NL/LvH/ma) the objectives were the following:Production of prototypes of a space qualified version of the commercial PowerFFT chip called FFTC based on the PowerFFT IP.The development of a stand-alone FFTC Accelerator Board (FTAB) based on the FFTC including the Controller FPGA and SpaceWire Interfaces to verify the FFTC function and performance.The FFTC chip performs its calculations with floating point precision. Stand alone it is capable computing FFTs of up to 1K complex samples in length in only 10μsec. This corresponds to an equivalent processing performance of 4.7 GFlops. In this mode the maximum sustained data throughput reaches 6.4Gbit/s. When connected to up to 4 EDAC protected SDRAM memory banks the FFTC can perform long FFTs with up to 1M complex samples in length or multidimensional FFT- based processing tasks.A Controller FPGA on the FTAB takes care of the SDRAM addressing. The instructions commanded via the Controller FPGA are used to set up the data flow and generate the memory addresses.The presentation will give and overview on the project, including the results of the validation of the FFTC ASIC prototypes.

  15. Fast Fourier Transform Co-processor (FFTC), towards embedded GFLOPs

    Science.gov (United States)

    Kuehl, Christopher; Liebstueckel, Uwe; Tejerina, Isaac; Uemminghaus, Michael; Witte, Felix; Kolb, Michael; Suess, Martin; Weigand, Roland; Kopp, Nicholas

    2012-10-01

    Many signal processing applications and algorithms perform their operations on the data in the transform domain to gain efficiency. The Fourier Transform Co-Processor has been developed with the aim to offload General Purpose Processors from performing these transformations and therefore to boast the overall performance of a processing module. The IP of the commercial PowerFFT processor has been selected and adapted to meet the constraints of the space environment. In frame of the ESA activity "Fast Fourier Transform DSP Co-processor (FFTC)" (ESTEC/Contract No. 15314/07/NL/LvH/ma) the objectives were the following: • Production of prototypes of a space qualified version of the commercial PowerFFT chip called FFTC based on the PowerFFT IP. • The development of a stand-alone FFTC Accelerator Board (FTAB) based on the FFTC including the Controller FPGA and SpaceWire Interfaces to verify the FFTC function and performance. The FFTC chip performs its calculations with floating point precision. Stand alone it is capable computing FFTs of up to 1K complex samples in length in only 10μsec. This corresponds to an equivalent processing performance of 4.7 GFlops. In this mode the maximum sustained data throughput reaches 6.4Gbit/s. When connected to up to 4 EDAC protected SDRAM memory banks the FFTC can perform long FFTs with up to 1M complex samples in length or multidimensional FFT-based processing tasks. A Controller FPGA on the FTAB takes care of the SDRAM addressing. The instructions commanded via the Controller FPGA are used to set up the data flow and generate the memory addresses. The paper will give an overview on the project, including the results of the validation of the FFTC ASIC prototypes.

  16. COTS Multicore Processors in Avionics Systems: Challenges and Solutions

    Science.gov (United States)

    2015-01-06

    COTS Multicore Processors in Avionics Systems: Challenges and Solutions Dionisio de Niz Bjorn Andersson and Lutz Wrage dionisio@sei.cmu.edu... Avionics Systems: Challenges and Solutions 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) Wrage /Dionisio de Niz Bjorn...NVIDIA Tegra K1 platform • Avionics and defense: – Rugged Intel i7 single board computers – Freescale P4080 8-core CPU 4 Shared Hardware: Multicore Memory

  17. Dormancy and Recovery Testing for Biological Wastewater Processors

    Science.gov (United States)

    Hummerick, Mary F.; Coutts, Janelle L.; Lunn, Griffin M.; Spencer, LaShelle; Khodadad, Christina L.; Birmele, Michele N.; Frances, Someliz; Wheeler, Raymond

    2015-01-01

    Resource recovery and recycling waste streams to usable water via biological water processors is a plausible component of an integrated water purification system. Biological processing as a pretreatment can reduce the load of organic carbon and nitrogen compounds entering physiochemical systems downstream. Aerated hollow fiber membrane bioreactors, have been proposed and studied for a number of years as an approach for treating wastewater streams for space exploration.

  18. Method of Modeling and Simulation of Shaped External Occulters

    Science.gov (United States)

    Lyon, Richard G. (Inventor); Clampin, Mark (Inventor); Petrone, Peter, III (Inventor)

    2016-01-01

    The present invention relates to modeling an external occulter including: providing at least one processor executing program code to implement a simulation system, the program code including: providing an external occulter having a plurality of petals, the occulter being coupled to a telescope; and propagating light from the occulter to a telescope aperture of the telescope by scalar Fresnel propagation, by: obtaining an incident field strength at a predetermined wavelength at an occulter surface; obtaining a field propagation from the occulter to the telescope aperture using a Fresnel integral; modeling a celestial object at differing field angles by shifting a location of a shadow cast by the occulter on the telescope aperture; calculating an intensity of the occulter shadow on the telescope aperture; and applying a telescope aperture mask to a field of the occulter shadow, and propagating the light to a focal plane of the telescope via FFT techniques.

  19. Pipelining and bypassing in a RISC/DSP processor

    Science.gov (United States)

    Yu, Guojun; Yao, Qingdong; Liu, Peng; Jiang, Zhidi; Li, Fuping

    2005-03-01

    This paper proposes pipelining and bypassing unit (BPU) design method in our 32-bit RISC/DSP processor: MediaDsp3201 (briefly, MD32). MD32 is realized in 0.18μm technology, 1.8v, 200MHz working clock and can achieve 200 million/s Multiply-Accumulate (MAC) operations. It merges RISC architecture and DSP computation capability thoroughly, achieves fundamental RISC, extended DSP and single instruction multiple data (SIMD) instruction set with various addressing modes in a unified and customized DSP pipeline stage architecture. We will first describe the pipeline structure of MD32, comparing it to typical RISC-style pipeline structure. And then we will study the validity of two bypassing schemes in terms of their effectiveness in resolving pipeline data hazards: Centralized and Distributed BPU design strategy (CBPU and DBPU). A bypassing circuit chain model is given for DBPU, which register read is only placed at ID pipe stage. Considering the processor"s working clock which is decided by the pipeline time delay, the optimization of circuit that serial select with priority is also analyzed in detail since the BPU consists of a long serial path for combination logic. Finally, the performance improvement is analyzed.

  20. Single-Scale Retinex Using Digital Signal Processors

    Science.gov (United States)

    Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn

    2005-01-01

    The Retinex is an image enhancement algorithm that improves the brightness, contrast and sharpness of an image. It performs a non-linear spatial/spectral transform that provides simultaneous dynamic range compression and color constancy. It has been used for a wide variety of applications ranging from aviation safety to general purpose photography. Many potential applications require the use of Retinex processing at video frame rates. This is difficult to achieve with general purpose processors because the algorithm contains a large number of complex computations and data transfers. In addition, many of these applications also constrain the potential architectures to embedded processors to save power, weight and cost. Thus we have focused on digital signal processors (DSPs) and field programmable gate arrays (FPGAs) as potential solutions for real-time Retinex processing. In previous efforts we attained a 21 (full) frame per second (fps) processing rate for the single-scale monochromatic Retinex with a TMS320C6711 DSP operating at 150 MHz. This was achieved after several significant code improvements and optimizations. Since then we have migrated our design to the slightly more powerful TMS320C6713 DSP and the fixed point TMS320DM642 DSP. In this paper we briefly discuss the Retinex algorithm, the performance of the algorithm executing on the TMS320C6713 and the TMS320DM642, and compare the results with the TMS320C6711.

  1. New Developments in the SCIAMACHY L2 Ground Processor

    Science.gov (United States)

    Gretschany, S.; Lichtenberg, G.; Meringer, M.; Theys, N.; Lerot, C.; Eichmann, K.-U.; Liebing, P.; Noel, S.; Dehn, A.; Fehr, T.

    2016-08-01

    SCIAMACHY (SCanning Imaging Absorption spectroMeter for Atmospheric ChartographY) aboard ESA's environmental satellite ENVISAT observed the Earth's atmosphere in limb, nadir, and solar/lunar occultation geometries covering the UV-Visible to NIR spectral range. It is a joint project of Germany, the Netherlands and Belgium and was launched in February 2002. SCIAMACHY doubled its originally planned in-orbit lifetime of five years before the communication to ENVISAT was severed in April 2012, and the mission entered its post- operational phase F.The SCIAMACHY Quality Working Group (SQWG) was established in 2007. The group coordinates evolution of algorithms and processors, aiming at improving the quality of the operational data products. University of Bremen (IUP), BIRA, DLR-IMF, SRON (Netherlands Institute for Space Research) and KNMI (The Royal Netherlands Meteorological Institute) are the members providing expertise in this group.In order to preserve the best quality of the outstanding data obtained by SCIAMACHY, data processors are still being updated. This presentation will highlight new developments that are currently being incorporated into the forthcoming Version 7 of ESA's operational Level 2 processor.

  2. Design and implementation of a high performance network security processor

    Science.gov (United States)

    Wang, Haixin; Bai, Guoqiang; Chen, Hongyi

    2010-03-01

    The last few years have seen many significant progresses in the field of application-specific processors. One example is network security processors (NSPs) that perform various cryptographic operations specified by network security protocols and help to offload the computation intensive burdens from network processors (NPs). This article presents a high performance NSP system architecture implementation intended for both internet protocol security (IPSec) and secure socket layer (SSL) protocol acceleration, which are widely employed in virtual private network (VPN) and e-commerce applications. The efficient dual one-way pipelined data transfer skeleton and optimised integration scheme of the heterogenous parallel crypto engine arrays lead to a Gbps rate NSP, which is programmable with domain specific descriptor-based instructions. The descriptor-based control flow fragments large data packets and distributes them to the crypto engine arrays, which fully utilises the parallel computation resources and improves the overall system data throughput. A prototyping platform for this NSP design is implemented with a Xilinx XC3S5000 based FPGA chip set. Results show that the design gives a peak throughput for the IPSec ESP tunnel mode of 2.85 Gbps with over 2100 full SSL handshakes per second at a clock rate of 95 MHz.

  3. On-board neural processor design for intelligent multisensor microspacecraft

    Science.gov (United States)

    Fang, Wai-Chi; Sheu, Bing J.; Wall, James

    1996-03-01

    A compact VLSI neural processor based on the Optimization Cellular Neural Network (OCNN) has been under development to provide a wide range of support for an intelligent remote sensing microspacecraft which requires both high bandwidth communication and high- performance computing for on-board data analysis, thematic data reduction, synergy of multiple types of sensors, and other advanced smart-sensor functions. The OCNN is developed with emphasis on its capability to find global optimal solutions by using a hardware annealing method. The hardware annealing function is embedded in the network. It is a parallel version of fast mean-field annealing in analog networks, and is highly efficient in finding globally optimal solutions for cellular neural networks. The OCNN is designed to perform programmable functions for fine-grained processing with annealing control to enhance the output quality. The OCNN architecture is a programmable multi-dimensional array of neurons which are locally connected with their local neurons. Major design features of the OCNN neural processor includes massively parallel neural processing, hardware annealing capability, winner-take-all mechanism, digitally programmable synaptic weights, and multisensor parallel interface. A compact current-mode VLSI design feasibility of the OCNN neural processor is demonstrated by a prototype 5 X 5-neuroprocessor array chip in a 2-micrometers CMOS technology. The OCNN operation theory, architecture, design and implementation, prototype chip, and system applications have been investigated in detail and presented in this paper.

  4. Accelerate Climate Models with the IBM Cell Processor

    Science.gov (United States)

    Zhou, S.; Duffy, D.; Clune, T.; Williams, S.; Suarez, M.; Halem, M.

    2008-12-01

    Ever increasing model resolutions and physical processes in climate models demand continual computing power increases. The IBM Cell processor's order-of- magnitude peak performance increase over conventional processors makes it very attractive for fulfilling this requirement. However, the Cell's characteristics: 256KB local memory per SPE and the new low-level communication mechanism, make it very challenging to port an application. We selected the solar radiation component of the NASA GEOS-5 climate model, which: (1) is representative of column physics components (~50% total computation time), (2) has a high computational load relative to data traffic to/from main memory, and (3) performs independent calculations across multiple columns. We converted the baseline code (single-precision, Fortran code) to C and ported it to an IBM BladeCenter QS20, manually SIMDizing 4 independent columns, and found that a Cell with 8 SPEs can process more than 3000 columns per second. Compared with the baseline results, the Cell is ~6.76x, ~8.91x, ~9.85x faster than a core on Intel's Xeon Woodcrest, Dempsey, and Itanium2 respectively. Our analysis shows that the Cell could also speed up the dynamics component (~25% total computation time). We believe this dramatic performance improvement makes the Cell processor very competitive, at least as an accelerator. We will report our experience in porting both the C and Fortran codes and will discuss our work in porting other climate model components.

  5. A Geometric Algebra Co-Processor for Color Edge Detection

    Directory of Open Access Journals (Sweden)

    Biswajit Mishra

    2015-01-01

    Full Text Available This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA co-processor implemented on an Application Specific Integrated Circuit (ASIC. GA provides a rich set of geometric operations, giving the advantage that many signal and image processing operations become straightforward and the algorithms intuitive to design. The use of GA allows images to be represented with the three R, G, B color channels defined as a single entity, rather than separate quantities. A novel custom ASIC is proposed and fabricated that directly targets GA operations and results in significant performance improvement for color edge detection. Use of the hardware described in this paper also shows that the convolution operation with the rotor masks within GA belongs to a class of linear vector filters and can be applied to image or speech signals. The contribution of the proposed approach has been demonstrated by implementing three different types of edge detection schemes on the proposed hardware. The overall performance gains using the proposed GA Co-Processor over existing software approaches are more than 3.2× faster than GAIGEN and more than 2800× faster than GABLE. The performance of the fabricated GA co-processor is approximately an order of magnitude faster than previously published results for hardware implementations.

  6. DESIGN OF INSTRUCTION LIST (IL PROCESSOR FOR PROCESS CONTROL

    Directory of Open Access Journals (Sweden)

    Mrs. Shilpa Rudrawar

    2012-06-01

    Full Text Available Programmable Logic Controller (PLC is a device that allows an Electro-Mechanical engineer to automate his mechanical process in an efficient manner. Safety critical high speed application requires quick response. In order to improve the speed of executing PLC instructions, the IL processor is researched. Hierarchical approach has been used so that basic units can be modeled using behavioral programming. These basic units are combined using structural programming. Hardwired control approach is used to design the control unit. The proposed IL (Instruction List processor work upon our developed IL instructions which are compatible with the programming language IL according to the norm IEC 61131-3. This can accelerate the instructions execution, ultimately improve real-time performance comparing to the traditional sequential execution of PLC program by giving quick response at such safety critical high speed application. The design is to be implemented on FPGA for verification purpose. To validate the advance of the proposed design, two ladder programs are compiled to the instruction set of proposed IL processor as well as in IL programming language.

  7. Evaluation of the Intel Westmere-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2011-01-01

    One year after the arrival of the Intel Xeon 7500 systems (“Nehalem-EX”), CERN openlab is presenting a set of benchmark results obtained when running on the new Xeon E7-4870 Processors, representing the “Westmere-EX” family. A modern 4-socket, 40-core system is confronted with the previous generation of expandable (“EX”) platforms, represented by a 4-socket, 32-core Intel Xeon X7560 based system – both being “top of the line” systems. Benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Symmetric MultiThreading (SMT), the cache sizes available, the configured memory topology, as well as the power configuration if throughput per watt is to be measured. As in previous activities, we have tried to do a good job of comparing like with like. In a “top of the line” comparison based on the HEPSPEC06 benchmark, the “We...

  8. Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2010-12-01

    Full Text Available As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalability in Intel Core 2 Duo series processors. Even though AI benchmarks have similar execution time, they have dissimilar characteristics which are identified using principal component analysis and dendogram. As the processor frequency increased from 1.8 GHz to 3.167 GHz the execution time is decreased by ~370 sec for AI workloads. In the case of Physics/Quantum Computing programs it was ~940 sec.

  9. Externality or sustainability economics?

    Energy Technology Data Exchange (ETDEWEB)

    Bergh, Jeroen C.J.M. van den [ICREA, Barcelona (Spain); Department of Economics and Economic History and Institute for Environmental Science and Technology, Universitat Autonoma de Barcelona (Spain)

    2010-09-15

    In an effort to develop 'sustainability economics' Baumgaertner and Quaas (2010) neglect the central concept of environmental economics-'environmental externality'. This note proposes a possible connection between the concepts of environmental externality and sustainability. In addition, attention is asked for other aspects of 'sustainability economics', namely the distinction weak/strong sustainability, spatial sustainability and sustainable trade, distinctive sustainability policy, and the ideas of early 'sustainability economists'. I argue that both sustainability and externalities reflect a systems perspective and propose that effective sustainability solutions require that more attention is given to system feedbacks, notably other-regarding preferences and social interactions, and energy and environmental rebound. The case of climate change and policy is used to illustrate particular statements. As a conclusion, a list of 20 insights and suggestions for research is offered. (author)

  10. Metasurface external cavity laser

    Energy Technology Data Exchange (ETDEWEB)

    Xu, Luyao, E-mail: luyaoxu.ee@ucla.edu; Curwen, Christopher A.; Williams, Benjamin S. [Department of Electrical Engineering, University of California, Los Angeles, California 90095 (United States); California NanoSystems Institute, University of California, Los Angeles, California 90095 (United States); Hon, Philip W. C.; Itoh, Tatsuo [Department of Electrical Engineering, University of California, Los Angeles, California 90095 (United States); Chen, Qi-Sheng [Northrop Grumman Aerospace Systems, Redondo Beach, California 90278 (United States)

    2015-11-30

    A vertical-external-cavity surface-emitting-laser is demonstrated in the terahertz range, which is based upon an amplifying metasurface reflector composed of a sub-wavelength array of antenna-coupled quantum-cascade sub-cavities. Lasing is possible when the metasurface reflector is placed into a low-loss external cavity such that the external cavity—not the sub-cavities—determines the beam properties. A near-Gaussian beam of 4.3° × 5.1° divergence is observed and an output power level >5 mW is achieved. The polarized response of the metasurface allows the use of a wire-grid polarizer as an output coupler that is continuously tunable.

  11. Dose-rate conversion factors for external exposure to photon and electron radiation from radionuclides occurring in routine releases from nuclear fuel cycle facilities. [Conversion factors are given for dose rates to 21 organs from 240 different radionuclides for 3 different modes of exposure

    Energy Technology Data Exchange (ETDEWEB)

    Kocher, D.C.

    1979-02-01

    Dose-rate conversion factors for external exposure to photon and electron radiation have been calculated for 240 radionuclides of potential importance in routine releases from nuclear fuel cycle facilities. Dose-rate conversion factors for immersion in contaminated air, immersion in contaminated water, and exposure to a contaminated ground surface are estimated for tissue-equivalent material at the body surface of an exposed individual. For each exposure mode, photon dose-rate conversion factors are also estimated for 22 body organs. The calculations assume that the contaminated air, water, and ground surface are infinite in extent and that the radionuclide concentration is uniform. Dose-rate conversion factors for immersion in contaminated air and water are based on the requirement that all energy emitted in the decay of a radionuclide is absorbed in the infinite medium. Dose-rate conversion factors for ground-surface exposure are calculated for a height of 1 m using the point-kernel integration method and known specific absorbed fractions for photons and electrons in air. The computer code DOSFACTER written to perform the calculations is described and documented.

  12. External costs of electricity; Les couts externes de l'electricite

    Energy Technology Data Exchange (ETDEWEB)

    Rabl, A. [Ecole des Mines de Paris, 75 (France); Spadaro, J.V. [International Atomic Energy Agency (IAEA), Vienna (Austria)

    2005-07-01

    This article presents a synthesis of the ExternE project (External costs of Energy) of the European community about the external costs of power generation. Pollution impacts are calculated using an 'impact pathways' analysis, i.e. an analysis of the emission - dispersion - dose-response function - cost evaluation chain. Results are presented for different fuel cycles (with several technological variants) with their confidence intervals. The environmental impact costs are particularly high for coal: for instance, in France, for coal-fired power plants it is of the same order as the electricity retail price. For natural gas, this cost is about a third of the one for coal. On the contrary, the environmental impact costs for nuclear and renewable energies are low, typically of few per cent of the electricity price. The main part of these costs corresponds to the sanitary impacts, in particular the untimely mortality. In order to avoid any controversy about the cost evaluation of mortality, the reduction of the expectation of life due to the different fuel cycles is also indicated and the risks linked with nuclear energy are presented using several comparisons. (J.S.)

  13. An Overview of Stationary Fuel Cell Technology

    Energy Technology Data Exchange (ETDEWEB)

    DR Brown; R Jones

    1999-03-23

    Technology developments occurring in the past few years have resulted in the initial commercialization of phosphoric acid (PA) fuel cells. Ongoing research and development (R and D) promises further improvement in PA fuel cell technology, as well as the development of proton exchange membrane (PEM), molten carbonate (MC), and solid oxide (SO) fuel cell technologies. In the long run, this collection of fuel cell options will be able to serve a wide range of electric power and cogeneration applications. A fuel cell converts the chemical energy of a fuel into electrical energy without the use of a thermal cycle or rotating equipment. In contrast, most electrical generating devices (e.g., steam and gas turbine cycles, reciprocating engines) first convert chemical energy into thermal energy and then mechanical energy before finally generating electricity. Like a battery, a fuel cell is an electrochemical device, but there are important differences. Batteries store chemical energy and convert it into electrical energy on demand, until the chemical energy has been depleted. Depleted secondary batteries may be recharged by applying an external power source, while depleted primary batteries must be replaced. Fuel cells, on the other hand, will operate continuously, as long as they are externally supplied with a fuel and an oxidant.

  14. Research and development of proton-exchange membrane (PEM) fuel cell system for transportation applications. Phase I final report

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1996-01-01

    Objective during Phase I was to develop a methanol-fueled 10-kW fuel cell power source and evaluate its feasibility for transportation applications. This report documents research on component (fuel cell stack, fuel processor, power source ancillaries and system sensors) development and the 10-kW power source system integration and test. The conceptual design study for a PEM fuel cell powered vehicle was documented in an earlier report (DOE/CH/10435-01) and is summarized herein. Major achievements in the program include development of advanced membrane and thin-film low Pt-loaded electrode assemblies that in reference cell testing with reformate-air reactants yielded performance exceeding the program target (0.7 V at 1000 amps/ft{sup 2}); identification of oxidation catalysts and operating conditions that routinely result in very low CO levels ({le} 10 ppm) in the fuel processor reformate, thus avoiding degradation of the fuel cell stack performance; and successful integrated operation of a 10-kW fuel cell stack on reformate from the fuel processor.

  15. Reforming of Liquid Hydrocarbons in a Novel Hydrogen-Selective Membrane-Based Fuel Processor

    Energy Technology Data Exchange (ETDEWEB)

    Shamsuddin Ilias

    2006-03-10

    In this work, asymmetric dense Pd/porous stainless steel composite membranes were fabricated by depositing palladium on the outer surface of the tubular support. The electroless plating method combined with an osmotic pressure field was used to deposit the palladium film. Surface morphology and microstructure of the composite membranes were characterized by SEM and EDX. The SEM and EDX analyses revealed strong adhesion of the plated pure palladium film on the substrate and dense coalescence of the Pd film. Membranes were further characterized by conducting permeability experiments with pure hydrogen, nitrogen, and helium gases at temperatures from 325 to 450 C and transmembrane pressure differences from 5 to 45 psi. The permeation results showed that the fabricated membranes have both high hydrogen permeability and selectivity. For example, the hydrogen permeability for a composite membrane with a 20 {micro}m Pd film was 3.02 x 10{sup -5} moles/m{sup 2}.s.Pa{sup 0.765} at 450 C. Hydrogen/nitrogen selectivity for this composite membrane was 1000 at 450 C with a transmembrane pressure difference of 14.7 psi. Steam reforming of methane is one of the most important chemical processes in hydrogen and syngas production. To investigate the usefulness of palladium-based composite membranes in membrane-reactor configuration for simultaneous production and separation of hydrogen, steam reforming of methane by equilibrium shift was studied. The steam reforming of methane using a packed-bed inert membrane tubular reactor (PBIMTR) was simulated. A two-dimensional pseudo-homogeneous reactor model with parallel flow configuration was developed for steam reforming of methane. The shell volume was taken as the feed and sweep gas was fed to the inside of the membrane tube. Radial diffusion was taken into account for concentration gradient in the radial direction due to hydrogen permeation through the membrane. With appropriate reaction rate expressions, a set of partial differential equations was derived using the continuity equation for the reaction system and then solved by finite difference method with appropriate boundary and initial conditions. An iterative scheme was used to obtain a converged solution. Membrane reactor performance was compared to that in a traditional non-membrane packed-bed reactor (PBR). Their performances were also compared with thermodynamic equilibrium values achievable in a conventional non-membrane reactor. Numerical results of the models show that the methane conversions in the PBIMTR are always higher than that in the PBR, as well as thermodynamic equilibrium conversions. For instance, at a reaction pressure of 6 atm, a temperature of 650 C, a space velocity of 900/16.0 SCCM/gm{sub cat}, a steam to methane molar feed ratio of 3.0, a sweep ratio of 0.15, the conversion in the membrane reactor is about 86.5%, while the conversion in the non-membrane reactor is about 50.8%. The corresponding equilibrium conversion is about 56.4%. The effects on the degree of conversion and hydrogen yield were analyzed for different parameters such as temperature, reactor pressure, feed and sweep flow rate, feed molar ratio, and space time. From the analysis of the model results, it is obvious that the membrane reactor operation can be optimized for conversion or yield through the choice of proper operating and design parameters. Comparisons with available literature data for both membrane and non-membrane reactors showed a good agreement.

  16. 3-D model of a radial flow sub-watt methanol fuel processor

    Energy Technology Data Exchange (ETDEWEB)

    Holladay, J. D.; Wang, Y.

    2015-10-01

    A 3-D model is presented for a novel sub-watt packed bed reactor. The reactor uses an annular inlet flow combined with a radial flow packed bed reactor. The baseline reactor is compared to a reactor with multiple outlets and a reactor with 3 internal fins. Increasing the outlets from 1 to 4 did improve the flow distribution, but did not increase the performance in the simulation. However, inserting fins allowed a decrease in temperature with same inlet flow of approximately 35K. Or the inlet flow rate could be increased by a factor of 2.8x while maintaining >99% conversion.

  17. External combustion wankel engine for solar applications

    Energy Technology Data Exchange (ETDEWEB)

    Kovarsky, N.; Kaftori, D.; Gamzon, E.; Dgani, E. [Silver Arrow (Israel)

    1999-03-01

    An External Combustion Wankel Engine (ECWE), intended for use in a dish-engine solar power plant is discussed. The engine operates in a Brayton cycle using a gaseous working fluid, which is heated outside of the engine by concentrated solar radiation or fossil fuel. A computer simulation code that models the ECWE's operation and performance has been developed The program takes into account all of the engine's characteristics, subsystems and operating conditions. In the present work, the advantages and features of ECWE are considered in detail, together with simulation results of its performance. (authors)

  18. Fuel cells:

    DEFF Research Database (Denmark)

    Sørensen, Bent

    2013-01-01

    A brief overview of the progress in fuel cell applications and basic technology development is presented, as a backdrop for discussing readiness for penetration into the marketplace as a solution to problems of depletion, safety, climate or environmental impact from currently used fossil and nucl......A brief overview of the progress in fuel cell applications and basic technology development is presented, as a backdrop for discussing readiness for penetration into the marketplace as a solution to problems of depletion, safety, climate or environmental impact from currently used fossil...... and nuclear fuel-based energy technologies....

  19. Environmental Externalities Related to Power Production Technologies in Denmark

    DEFF Research Database (Denmark)

    Ibsen, Liselotte Schleisner; Nielsen, Per Sieverts

    1997-01-01

    of the Danish part of the project is to implement the framework for externality evaluation, for three different power plants located in Denmark. The paper will focus on the assessment of the impacts of the whole fuel cycles for wind, natural gas and biogas. Priority areas for environmental impact assessment...

  20. Low input voltage converter/regulator minimizes external disturbances

    Science.gov (United States)

    1966-01-01

    Low-input voltage converter/regulator constructed in a coaxial configuration minimizes external magnetic field disturbance, suppresses radio noise interference, and provides excellent heat transfer from power transistors. It converts the output of fuel and solar cells, thermionic diodes, thermoelectric generators, and electrochemical batteries to a 28 V dc output.

  1. Stochastic Control - External Models

    DEFF Research Database (Denmark)

    Poulsen, Niels Kjølstad

    2005-01-01

    This note is devoted to control of stochastic systems described in discrete time. We are concerned with external descriptions or transfer function model, where we have a dynamic model for the input output relation only (i.e.. no direct internal information). The methods are based on LTI systems...

  2. Productivity Change and Externalities

    DEFF Research Database (Denmark)

    Kravtsova, Victoria

    2014-01-01

    firms and the economy as a whole. The approach used in the current research accounts for different internal as well as external factors that individual firms face and evaluates the effect on changes in productivity, technology as well as the efficiency of domestic firms. The empirical analysis focuses...... change in different types of firms and sectors of the economy...

  3. Multiple external root resorption.

    Science.gov (United States)

    Yusof, W Z; Ghazali, M N

    1989-04-01

    Presented is an unusual case of multiple external root resorption. Although the cause of this resorption was not determined, several possibilities are presented. Trauma from occlusion, periodontal and pulpal inflammation, and resorption of idiopathic origin are all discussed as possible causes.

  4. External meeting: Geneva University

    CERN Multimedia

    2006-01-01

    Ecole de physique 24 quai Ernest Ansermet 1211 GENEVA 4 Tel: (022) 379 62 73 Fax: (022) 379 69 92 Monday 19 June 2006 17:00-Stückelberg Auditorium Quantum Optics and Quantum Information Processing with Superconducting Circuits Prof. A. Wallraff /ETH Zürich I will describe recent experiments with superconducting circuits in which we have demonstrated the coherent interaction of a two-level system and a single mode of a cavityfield. Such a feat was previously only realizable in atomic cavity quantum electrodynamics experiments. In our circuit we have generated coherent superpositions between asingle photon and a single superconducting qubit and have used photons to perform a quantum non-demolition measurement of the state of the qubit. This new regime ofmatter-light interaction in a circuit, allows us to both perform state of the art quantum optics experiments and to realize new elements for a quantum information processor. For additional information and publications please visit: http://www.solid.phys....

  5. EFFECTS OF COOLED EXTERNAL EXHAUST GAS RECIRCULATION ON DIESEL HOMOGENEOUS CHARGE COMPRESSION IGNITION ENGINE

    Institute of Scientific and Technical Information of China (English)

    SHI Lei; CUI Yi; DENG Kangyao

    2007-01-01

    The effects of cooled external exhaust gas recirculation (EGR) on the combustion and emission performance of diesel fuel homogeneous charge compression ignition (HCCI) are studied. Homogeneous mixture is formed by injecting fuel in-cylinder in the negative valve overlap (NVO) period. So, the HCCI combustion which has low NOx and smoke emission is achieved. Cooled external EGR can delay the start of combustion effectively, which is very useful for high cetane fuel (diesel) HCCI, because these fuels can easily self-ignition, which makes the start of combustion more early. External EGR can avoid the knock combustion of HCCI at high load which means that the EGR can expand the high load limit. HCCI maintains low smoke emission at various EGR rate and various load compared with conventional diesel engine because there is no fuel-rich area in cylinder.

  6. Fuel cells

    Directory of Open Access Journals (Sweden)

    D. N. Srivastava

    1962-05-01

    Full Text Available The current state of development of fuel cells as potential power sources is reviewed. Applications in special fields with particular reference to military requirements are pointed out.

  7. Fuel cells - Fundamentals and types: Unique features

    Science.gov (United States)

    Selman, J. R.

    An overview of the working principles, thermodynamic efficiencies, types, and engineering aspects of fuel cells is presented. It is noted that fuel cells are distinguished from other direct energy conversion devices by the existence of charge separation at the electrodes involving ions in an electrolyte. The electrical energy produced by a fuel cell is shown to be equal to the change in the free energy of the reactants, and thermodynamic balances of reactions in different fuel cells are provided. The production of electricity in the discharge mode involves a spontaneous reaction of overproduction of electrons at the anode and consumption of the electrons at the cathode, with the total ionic current being equal to the electronic current in the external circuit. Attention is given to the operations and problems of acid, alkaline, molten carbonate, and solid oxide fuel cells, in addition to applications of electro-organic fuel cells.

  8. Messiah College Biodiesel Fuel Generation Project Final Technical Report

    Energy Technology Data Exchange (ETDEWEB)

    Zummo, Michael M; Munson, J; Derr, A; Zemple, T; Bray, S; Studer, B; Miller, J; Beckler, J; Hahn, A; Martinez, P; Herndon, B; Lee, T; Newswanger, T; Wassall, M

    2012-03-30

    Many obvious and significant concerns arise when considering the concept of small-scale biodiesel production. Does the fuel produced meet the stringent requirements set by the commercial biodiesel industry? Is the process safe? How are small-scale producers collecting and transporting waste vegetable oil? How is waste from the biodiesel production process handled by small-scale producers? These concerns and many others were the focus of the research preformed in the Messiah College Biodiesel Fuel Generation project over the last three years. This project was a unique research program in which undergraduate engineering students at Messiah College set out to research the feasibility of small-biodiesel production for application on a campus of approximately 3000 students. This Department of Energy (DOE) funded research program developed out of almost a decade of small-scale biodiesel research and development work performed by students at Messiah College. Over the course of the last three years the research team focused on four key areas related to small-scale biodiesel production: Quality Testing and Assurance, Process and Processor Research, Process and Processor Development, and Community Education. The objectives for the Messiah College Biodiesel Fuel Generation Project included the following: 1. Preparing a laboratory facility for the development and optimization of processors and processes, ASTM quality assurance, and performance testing of biodiesel fuels. 2. Developing scalable processor and process designs suitable for ASTM certifiable small-scale biodiesel production, with the goals of cost reduction and increased quality. 3. Conduct research into biodiesel process improvement and cost optimization using various biodiesel feedstocks and production ingredients.

  9. Future Fuels

    Science.gov (United States)

    2006-04-01

    Storage Devices, Fuel Management, Gasification, Fischer-Tropsch, Syngas , Hubberts’s Peak UNCLAS UNCLAS UNCLAS UU 80 Dr. Sujata Millick (703) 696...prices ever higher, and perhaps lead to intermittent fuel shortages as production fluctuates. Clearly, this competition for resources also provides oil...producers multiple options for selling their products, and raises the possibility that the US could face shortages resulting from shifts in

  10. National Aviation Fuel Scenario Analysis Program (NAFSAP). Volume I. Model Description. Volume II. User Manual.

    Science.gov (United States)

    1980-03-01

    TESI CHART NATIONAI RUREAt (F ANDA[)Rt 1V4 A NATIONAL. AVIATION ~ FUEL SCENARIO.. ANALYSIS PROGRAM 49!! VOLUM I: MODEL DESCRIA~v 4<C VOLUME II: tr)ER...executes post processor which translates results of the graphics program to machine readable code used by the pen plotter) cr (depressing the carriage

  11. ExternE transport methodology for external cost evaluation of air pollution

    DEFF Research Database (Denmark)

    Jensen, S. S.; Berkowicz, R.; Brandt, J.

    The report describes how the human exposure estimates based on NERI's human exposure modelling system (AirGIS) can improve the Danish data used for exposure factors in the ExternE Transport methodology. Initially, a brief description of the ExternE Tranport methodology is given and it is summaris...

  12. An Alternative Water Processor for Long Duration Space Missions

    Science.gov (United States)

    Barta, Daniel J.; Wheeler, Raymond; Jackson, William; Pickering, Karen; Meyer, Caitlin; Pensinger, Stuart; Vega, Leticia; Flynn, Michael

    A new wastewater recovery system has been developed that combines novel biological and physicochemical components for recycling wastewater on long duration space missions. Functionally, this Alternative Water Processor (AWP) would replace the Urine Processing Assembly on the International Space Station and reduce or eliminate the need for the multi-filtration beds of the Water Processing Assembly (WPA). At its center are two unique game changing technologies: 1) a biological water processor (BWP) to mineralize organic forms of carbon and nitrogen and 2) an advanced membrane processor (Forward Osmosis Secondary Treatment) for removal of solids and inorganic ions. The AWP is designed for recycling larger quantities of wastewater from multiple sources expected during future exploration missions, including urine, hygiene (hand wash, shower, oral and shave) and laundry. The BWP utilizes a single-stage membrane-aerated biological reactor for simultaneous nitrification and denitrification. The Forward Osmosis Secondary Treatment (FOST) system uses a combination of forward osmosis (FO) and reverse osmosis (RO), is resistant to biofouling and can easily tolerate wastewaters high in non-volatile organics and solids associated with shower and/or hand washing. The BWP has been operated continuously for over 300 days. After startup, the mature biological system averaged 85% organic carbon removal and 44% nitrogen removal, close to maximum based on available carbon. To date, the FOST has averaged 93% water recovery, with a maximum of 98%. If the wastewater is slighty acidified, ammonia rejection is optimal. This paper will provide a description of the technology and summarize results from ground-based testing using real wastewater.

  13. An Alternative Water Processor for Long Duration Space Missions

    Science.gov (United States)

    Barta, Daniel J.; Pickering, Karen D.; Meyer, Caitlin; Pennsinger, Stuart; Vega, Leticia; Flynn, Michael; Jackson, Andrew; Wheeler, Raymond

    2014-01-01

    A new wastewater recovery system has been developed that combines novel biological and physicochemical components for recycling wastewater on long duration human space missions. Functionally, this Alternative Water Processor (AWP) would replace the Urine Processing Assembly on the International Space Station and reduce or eliminate the need for the multi-filtration beds of the Water Processing Assembly (WPA). At its center are two unique game changing technologies: 1) a biological water processor (BWP) to mineralize organic forms of carbon and nitrogen and 2) an advanced membrane processor (Forward Osmosis Secondary Treatment) for removal of solids and inorganic ions. The AWP is designed for recycling larger quantities of wastewater from multiple sources expected during future exploration missions, including urine, hygiene (hand wash, shower, oral and shave) and laundry. The BWP utilizes a single-stage membrane-aerated biological reactor for simultaneous nitrification and denitrification. The Forward Osmosis Secondary Treatment (FOST) system uses a combination of forward osmosis (FO) and reverse osmosis (RO), is resistant to biofouling and can easily tolerate wastewaters high in non-volatile organics and solids associated with shower and/or hand washing. The BWP has been operated continuously for over 300 days. After startup, the mature biological system averaged 85% organic carbon removal and 44% nitrogen removal, close to stoichiometric maximum based on available carbon. To date, the FOST has averaged 93% water recovery, with a maximum of 98%. If the wastewater is slighty acidified, ammonia rejection is optimal. This paper will provide a description of the technology and summarize results from ground-based testing using real wastewater

  14. The External Mind

    DEFF Research Database (Denmark)

    The External Mind: an Introduction by Riccardo Fusaroli, Claudio Paolucci pp. 3-31 The sign of the Hand: Symbolic Practices and the Extended Mind by Massimiliano Cappuccio, Michael Wheeler pp. 33-55 The Overextended Mind by Shaun Gallagher pp. 57-68 The "External Mind": Semiotics, Pragmatism......, Extended Mind and Distributed Cognition by Claudio Paolucci pp. 69-96 The Social Horizon of Embodied Language and Material Symbols by Riccardo Fusaroli pp. 97-123 Semiotics and Theories of Situated/Distributed Action and Cognition: a Dialogue and Many Intersections by Tommaso Granelli pp. 125-167 Building...... Action in Public Environments with Diverse Semiotic Resources by Charles Goodwin pp. 169-182 How Marking in Dance Constitutes Thinking with the Body by David Kirsh pp. 183-214 Ambiguous Coordination: Collaboration in Informal Science Education Research by Ivan Rosero, Robert Lecusay, Michael Cole pp. 215-240...

  15. External-Memory Multimaps

    CERN Document Server

    Angelino, Elaine; Mitzenmacher, Michael; Thaler, Justin

    2011-01-01

    Many data structures support dictionaries, also known as maps or associative arrays, which store and manage a set of key-value pairs. A \\emph{multimap} is generalization that allows multiple values to be associated with the same key. For example, the inverted file data structure that is used prevalently in the infrastructure supporting search engines is a type of multimap, where words are used as keys and document pointers are used as values. We study the multimap abstract data type and how it can be implemented efficiently online in external memory frameworks, with constant expected I/O performance. The key technique used to achieve our results is a combination of cuckoo hashing using buckets that hold multiple items with a multiqueue implementation to cope with varying numbers of values per key. Our external-memory results are for the standard two-level memory model.

  16. Power estimation on functional level for programmable processors

    Directory of Open Access Journals (Sweden)

    M. Schneider

    2004-01-01

    Full Text Available In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA. Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA. This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated

  17. Distributed digital signal processors for multi-body structures

    Science.gov (United States)

    Lee, Gordon K.

    1990-01-01

    Several digital filter designs were investigated which may be used to process sensor data from large space structures and to design digital hardware to implement the distributed signal processing architecture. Several experimental tests articles are available at NASA Langley Research Center to evaluate these designs. A summary of some of the digital filter designs is presented, an evaluation of their characteristics relative to control design is discussed, and candidate hardware microcontroller/microcomputer components are given. Future activities include software evaluation of the digital filter designs and actual hardware inplementation of some of the signal processor algorithms on an experimental testbed at NASA Langley.

  18. Highly scalable linear solvers on thousands of processors.

    Energy Technology Data Exchange (ETDEWEB)

    Domino, Stefan Paul (Sandia National Laboratories, Albuquerque, NM); Karlin, Ian (University of Colorado at Boulder, Boulder, CO); Siefert, Christopher (Sandia National Laboratories, Albuquerque, NM); Hu, Jonathan Joseph; Robinson, Allen Conrad (Sandia National Laboratories, Albuquerque, NM); Tuminaro, Raymond Stephen

    2009-09-01

    In this report we summarize research into new parallel algebraic multigrid (AMG) methods. We first provide a introduction to parallel AMG. We then discuss our research in parallel AMG algorithms for very large scale platforms. We detail significant improvements in the AMG setup phase to a matrix-matrix multiplication kernel. We present a smoothed aggregation AMG algorithm with fewer communication synchronization points, and discuss its links to domain decomposition methods. Finally, we discuss a multigrid smoothing technique that utilizes two message passing layers for use on multicore processors.

  19. The Level 0 Trigger Processor for the NA62 experiment

    Energy Technology Data Exchange (ETDEWEB)

    Chiozzi, S. [INFN, Ferrara (Italy); Gamberini, E. [University of Ferrara and INFN, Ferrara (Italy); Gianoli, A. [INFN, Ferrara (Italy); Mila, G. [University of Turin and INFN, Turin (Italy); Neri, I., E-mail: neri@fe.infn.it [University of Ferrara and INFN, Ferrara (Italy); Petrucci, F. [University of Ferrara and INFN, Ferrara (Italy); Soldi, D. [University of Turin and INFN, Turin (Italy)

    2016-07-11

    In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1 MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.

  20. FPGA Implementation of Decimal Processors for Hardware Acceleration

    DEFF Research Database (Denmark)

    Borup, Nicolas; Dindorp, Jonas; Nannarelli, Alberto

    2011-01-01

    Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial...... transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its...