WorldWideScience

Sample records for exploiting commercial cmos

  1. Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

    International Nuclear Information System (INIS)

    Gabrielli, A.; Matteucci, G.; Civera, P.; Demarchi, D.; Villani, G.; Weber, M.

    2009-01-01

    The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

  2. Planar pixel sensors in commercial CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

    2015-07-01

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  3. The exploitation argument against commercial surrogacy.

    Science.gov (United States)

    Wilkinson, Stephen

    2003-04-01

    This paper discusses the exploitation argument against commercial surrogacy: the claim that commercial surrogacy is morally objectionable because it is exploitative. The following questions are addressed. First, what exactly does the exploitation argument amount to? Second, is commercial surrogacy in fact exploitative? Third, if it were exploitative, would this provide a sufficient reason to prohibit (or otherwise legislatively discourage) it? The focus throughout is on the exploitation of paid surrogates, although it is noted that other parties (e.g. 'commissioning parents') may also be the victims of exploitation. It is argued that there are good reasons for believing that commercial surrogacy is often exploitative. However, even if we accept this, the exploitation argument for prohibiting (or otherwise legislatively discouraging) commercial surrogacy remains quite weak. One reason for this is that prohibition may well 'backfire' and lead to potential surrogates having to do other things that are more exploitative and/or more harmful than paid surrogacy. It is concluded therefore that those who oppose exploitation should (rather than attempting to stop particular practices like commercial surrogacy) concentrate on: (a) improving the conditions under which paid surrogates 'work'; and (b) changing the background conditions (in particular, the unequal distribution of power and wealth) which generate exploitative relationships.

  4. Uncovering Indicators of Commercial Sexual Exploitation.

    Science.gov (United States)

    Bounds, Dawn; Delaney, Kathleen R; Julion, Wrenetha; Breitenstein, Susan

    2017-07-01

    It is estimated that annually 100,000 to 300,000 youth are at risk for sex trafficking; a commercial sex act induced by force, fraud, or coercion, or any such act where the person induced to perform such an act is younger than 18 years of age. Increasingly, such transactions are occurring online via Internet-based sites that serve the commercial sex industry. Commercial sex transactions involving trafficking are illegal; thus, Internet discussions between those involved must be veiled. Even so, transactions around sex trafficking do occur. Within these transactions are innuendos that provide one avenue for detecting potential activity. The purpose of this study is to identify linguistic indicators of potential commercial sexual exploitation within the online comments of men posted on an Internet site. Six hundred sixty-six posts from five Midwest cities and 363 unique members were analyzed via content analysis. Three main indicators were found: the presence of youth or desire for youthfulness, presence of pimps, and awareness of vulnerability. These findings begin a much-needed dialogue on uncovering online risks of commercial sexual exploitation and support the need for further research on Internet indicators of sex trafficking.

  5. Dandruff: The most commercially exploited skin disease

    Directory of Open Access Journals (Sweden)

    Ranganathan S

    2010-01-01

    Full Text Available The article discuss in detail about the prevalence, pathophysiology, clinical manifestations of dandruff including the etio-pathology. The article also discusses in detail about various treatment methods available for dandruff. The status of dandruff being amphibious - a disease/disorder, and relatively less medical intervention is sought after for the treatment, dandruff is the most commercially exploited skin and scalp disorder/disease by personal care industries.

  6. Exploiting The New Commercial Space Race

    Science.gov (United States)

    2016-02-10

    provided launches for the EELV on a sole-source basis. Recently the landscape of the commercial space launch industry is being changed by a new group of...commercial space launch industry is being changed by a new group of entrepreneurs motivated by broader interests other than only launching satellites...James Cameron-backed Planetary Resources which seeks to mine asteroids for precious metals  Richard Branson’s Virgin Galactic which started selling

  7. Simulated population responses of common carp to commercial exploitation

    Energy Technology Data Exchange (ETDEWEB)

    Weber, Michael J.; Hennen, Matthew J.; Brown, Michael L.

    2011-12-01

    Common carp Cyprinus carpio is a widespread invasive species that can become highly abundant and impose deleterious ecosystem effects. Thus, aquatic resource managers are interested in controlling common carp populations. Control of invasive common carp populations is difficult, due in part to the inherent uncertainty of how populations respond to exploitation. To understand how common carp populations respond to exploitation, we evaluated common carp population dynamics (recruitment, growth, and mortality) in three natural lakes in eastern South Dakota. Common carp exhibited similar population dynamics across these three systems that were characterized by consistent recruitment (ages 3 to 15 years present), fast growth (K = 0.37 to 0.59), and low mortality (A = 1 to 7%). We then modeled the effects of commercial exploitation on size structure, abundance, and egg production to determine its utility as a management tool to control populations. All three populations responded similarly to exploitation simulations with a 575-mm length restriction, representing commercial gear selectivity. Simulated common carp size structure modestly declined (9 to 37%) in all simulations. Abundance of common carp declined dramatically (28 to 56%) at low levels of exploitation (0 to 20%) but exploitation >40% had little additive effect and populations were only reduced by 49 to 79% despite high exploitation (>90%). Maximum lifetime egg production was reduced from 77 to 89% at a moderate level of exploitation (40%), indicating the potential for recruitment overfishing. Exploitation further reduced common carp size structure, abundance, and egg production when simulations were not size selective. Our results provide insights to how common carp populations may respond to exploitation. Although commercial exploitation may be able to partially control populations, an integrated removal approach that removes all sizes of common carp has a greater chance of controlling population abundance

  8. Total dose hardness of a commercial SiGe BiCMOS technology

    International Nuclear Information System (INIS)

    Van Vonno, N.; Lucas, R.; Thornberry, D.

    1999-01-01

    Over the past decade SiGe HBT technology has progress from the laboratory to actual commercial applications. When integrated into a BiMOS process, this technology has applications in low-cost space systems. In this paper, we report results of total dose testing of a SiGe/CMOS process accessible through a commercial foundry. (authors)

  9. Commercial CMOS image sensors as X-ray imagers and particle beam monitors

    International Nuclear Information System (INIS)

    Castoldi, A.; Guazzoni, C.; Maffessanti, S.; Montemurro, G.V.; Carraresi, L.

    2015-01-01

    CMOS image sensors are widely used in several applications such as mobile handsets webcams and digital cameras among others. Furthermore they are available across a wide range of resolutions with excellent spectral and chromatic responses. In order to fulfill the need of cheap systems as beam monitors and high resolution image sensors for scientific applications we exploited the possibility of using commercial CMOS image sensors as X-rays and proton detectors. Two different sensors have been mounted and tested. An Aptina MT9v034, featuring 752 × 480 pixels, 6μm × 6μm pixel size has been mounted and successfully tested as bi-dimensional beam profile monitor, able to take pictures of the incoming proton bunches at the DeFEL beamline (1–6 MeV pulsed proton beam) of the LaBeC of INFN in Florence. The naked sensor is able to successfully detect the interactions of the single protons. The sensor point-spread-function (PSF) has been qualified with 1MeV protons and is equal to one pixel (6 mm) r.m.s. in both directions. A second sensor MT9M032, featuring 1472 × 1096 pixels, 2.2 × 2.2 μm pixel size has been mounted on a dedicated board as high-resolution imager to be used in X-ray imaging experiments with table-top generators. In order to ease and simplify the data transfer and the image acquisition the system is controlled by a dedicated micro-processor board (DM3730 1GHz SoC ARM Cortex-A8) on which a modified LINUX kernel has been implemented. The paper presents the architecture of the sensor systems and the results of the experimental measurements

  10. Exploitation of commercial remote sensing images: reality ignored?

    Science.gov (United States)

    Allen, Paul C.

    1999-12-01

    The remote sensing market is on the verge of being awash in commercial high-resolution images. Market estimates are based on the growing numbers of planned commercial remote sensing electro-optical, radar, and hyperspectral satellites and aircraft. EarthWatch, Space Imaging, SPOT, and RDL among others are all working towards launch and service of one to five meter panchromatic or radar-imaging satellites. Additionally, new advances in digital air surveillance and reconnaissance systems, both manned and unmanned, are also expected to expand the geospatial customer base. Regardless of platform, image type, or location, each system promises images with some combination of increased resolution, greater spectral coverage, reduced turn-around time (request-to- delivery), and/or reduced image cost. For the most part, however, market estimates for these new sources focus on the raw digital images (from collection to the ground station) while ignoring the requirements for a processing and exploitation infrastructure comprised of exploitation tools, exploitation training, library systems, and image management systems. From this it would appear the commercial imaging community has failed to learn the hard lessons of national government experience choosing instead to ignore reality and replicate the bias of collection over processing and exploitation. While this trend may be not impact the small quantity users that exist today it will certainly adversely affect the mid- to large-sized users of the future.

  11. Commercial sexual exploitation and sex trafficking of adolescents.

    Science.gov (United States)

    Chung, Richard J; English, Abigail

    2015-08-01

    This review describes the current state of commercial sexual exploitation and sex trafficking of adolescents in the United States and globally, the legal and health implications of this severe form of abuse, and the roles that pediatric and adolescent healthcare providers can play in addressing this issue. Although this form of exploitation and abuse is shrouded in secrecy, pediatric and adolescent healthcare providers are well positioned to respond when it arises. However, awareness and understanding of the issue are generally lacking among healthcare professionals, currently limiting their effectiveness in combating this problem. Although the empirical evidence base available to guide clinical care of victims of trafficking remains limited given the secretive nature of the abuse, important contributions to the multidisciplinary literature on this issue have been made in recent years, including the Institute of Medicine's landmark report in the United States. Commercial sexual exploitation and sex trafficking of adolescents represent a human rights tragedy that remains inadequately addressed. As preeminent advocates for the health and well-being of adolescents, pediatric and adolescent healthcare providers can play a crucial role in advancing efforts not only to intervene but also to prevent further victimization of vulnerable youth.

  12. Counting neutrons with a commercial S-CMOS camera

    Directory of Open Access Journals (Sweden)

    Patrick Van Esch

    2018-01-01

    Full Text Available It is possible to detect individual flashes from thermal neutron impacts in a ZnS scintillator using a CMOS camera looking at the scintillator screen, and off line image processing. Some preliminary results indicated that the efficiency of recognition could be improved by optimizing the light collection and the image processing. We will report on this ongoing work which is a result from the collaboration between ESS Bilbao and the ILL. The main progress to be reported is situated on the level of the on-line treatment of the imaging data. If this technology is to work on a genuine scientific instrument, it is necessary that all the processing happens on line, to avoid the accumulation of large amounts of image data to be analyzed off line. An FPGA-based real-time full-deca mode VME-compatible CameraLink board has been developed at the SCI of the ILL, which is able to manage the data flow from the camera and convert it in a reasonable “neutron impact” data flow like from a usual neutron counting detector. The main challenge of the endeavor is the optical light collection from the scintillator. While the light yield of a ZnS scintillator is a priori rather important, the amount of light collected with a photographic objective is small. Different scintillators and different light collection techniques have been experimented with and results will be shown for different setups improving upon the light recuperation on the camera sensor. Improvements on the algorithm side will also be presented. The algorithms have to be at the same time efficient in their recognition of neutron signals, in their rejection of noise signals (internal and external to the camera but also have to be simple enough to be easily implemented in the FPGA. The path from the idea of detecting individual neutron impacts with a CMOS camera to a practical working instrument detector is challenging, and in this paper we will give an overview of the part of the road that has

  13. Counting neutrons with a commercial S-CMOS camera

    Science.gov (United States)

    Patrick, Van Esch; Paolo, Mutti; Emilio, Ruiz-Martinez; Estefania, Abad Garcia; Marita, Mosconi; Jon, Ortega

    2018-01-01

    It is possible to detect individual flashes from thermal neutron impacts in a ZnS scintillator using a CMOS camera looking at the scintillator screen, and off line image processing. Some preliminary results indicated that the efficiency of recognition could be improved by optimizing the light collection and the image processing. We will report on this ongoing work which is a result from the collaboration between ESS Bilbao and the ILL. The main progress to be reported is situated on the level of the on-line treatment of the imaging data. If this technology is to work on a genuine scientific instrument, it is necessary that all the processing happens on line, to avoid the accumulation of large amounts of image data to be analyzed off line. An FPGA-based real-time full-deca mode VME-compatible CameraLink board has been developed at the SCI of the ILL, which is able to manage the data flow from the camera and convert it in a reasonable "neutron impact" data flow like from a usual neutron counting detector. The main challenge of the endeavor is the optical light collection from the scintillator. While the light yield of a ZnS scintillator is a priori rather important, the amount of light collected with a photographic objective is small. Different scintillators and different light collection techniques have been experimented with and results will be shown for different setups improving upon the light recuperation on the camera sensor. Improvements on the algorithm side will also be presented. The algorithms have to be at the same time efficient in their recognition of neutron signals, in their rejection of noise signals (internal and external to the camera) but also have to be simple enough to be easily implemented in the FPGA. The path from the idea of detecting individual neutron impacts with a CMOS camera to a practical working instrument detector is challenging, and in this paper we will give an overview of the part of the road that has already been walked.

  14. Commercial Sexual Exploitation of Children and State Child Welfare Systems.

    Science.gov (United States)

    Bounds, Dawn; Julion, Wrenetha A; Delaney, Kathleen R

    2015-01-01

    In several states, commercial sexual exploitation of children (CSEC) is now a reportable child abuse offense. Illinois has taken the lead in tackling the issue and the Illinois experience illuminates valuable lessons. This article delineates the protection, practice, and policy implications that evolve when CSEC falls under a state child welfare system. The specific aims are to (a) discuss CSEC, its victims, risks, harms, and challenges inherent in providing effective care; (b) use Illinois as an exemplar to explicate the consequences and implementation challenges of establishing a state reporting system that frames CSEC as a child welfare issue; (c) recommend strategies for developing effective state reporting models, and (d) demonstrate how nurses are well poised to advocate for victims of human trafficking on both state and national levels. Recommendations for improving the identification of CSEC victims and overcoming challenges to state implementation are offered. © The Author(s) 2015.

  15. Particle detection and classification using commercial off the shelf CMOS image sensors

    Energy Technology Data Exchange (ETDEWEB)

    Pérez, Martín [Instituto Balseiro, Av. Bustillo 9500, Bariloche, 8400 (Argentina); Comisión Nacional de Energía Atómica (CNEA), Centro Atómico Bariloche, Av. Bustillo 9500, Bariloche 8400 (Argentina); Consejo Nacional de Investigaciones Científicas y Técnicas, Centro Atómico Bariloche, Av. Bustillo 9500, 8400 Bariloche (Argentina); Lipovetzky, Jose, E-mail: lipo@cab.cnea.gov.ar [Instituto Balseiro, Av. Bustillo 9500, Bariloche, 8400 (Argentina); Comisión Nacional de Energía Atómica (CNEA), Centro Atómico Bariloche, Av. Bustillo 9500, Bariloche 8400 (Argentina); Consejo Nacional de Investigaciones Científicas y Técnicas, Centro Atómico Bariloche, Av. Bustillo 9500, 8400 Bariloche (Argentina); Sofo Haro, Miguel; Sidelnik, Iván; Blostein, Juan Jerónimo; Alcalde Bessia, Fabricio; Berisso, Mariano Gómez [Instituto Balseiro, Av. Bustillo 9500, Bariloche, 8400 (Argentina); Consejo Nacional de Investigaciones Científicas y Técnicas, Centro Atómico Bariloche, Av. Bustillo 9500, 8400 Bariloche (Argentina)

    2016-08-11

    In this paper we analyse the response of two different Commercial Off The shelf CMOS image sensors as particle detectors. Sensors were irradiated using X-ray photons, gamma photons, beta particles and alpha particles from diverse sources. The amount of charge produced by different particles, and the size of the spot registered on the sensor are compared, and analysed by an algorithm to classify them. For a known incident energy spectrum, the employed sensors provide a dose resolution lower than microGray, showing their potentials in radioprotection, area monitoring, or medical applications.

  16. Radiation hardness evaluation of the commercial 150 nm CMOS process using 60Co source

    International Nuclear Information System (INIS)

    Carna, M; Havranek, M; Hejtmanek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Vrba, V

    2014-01-01

    We present a study of radiation effects on MOSFET transistors irradiated with a 60 Co source to a total absorbed dose of 1.5 Mrad. The transistor test structures were manufactured using a commercial 150 nm CMOS process and are composed of transistors of different types (NMOS and PMOS), dimensions and insulation from the bulk material by means of deep n-wells. We have observed a degradation of electrical characteristics of both PMOS and NMOS transistors, namely a large increase of the leakage current of the NMOS transistors after irradiation

  17. Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits

    Science.gov (United States)

    Sahay, Shubham; Suri, Manan

    2017-12-01

    This paper provides a comprehensive review and insight of recent trends in the field of random number generator (RNG) and physically unclonable function (PUF) circuits implemented using different types of emerging resistive non-volatile (NVM) memory devices. We present a detailed review of hybrid RNG/PUF implementations based on the use of (i) Spin-Transfer Torque (STT-MRAM), and (ii) metal-oxide based (OxRAM), NVM devices. Various approaches on Hybrid CMOS-NVM RNG/PUF circuits are considered, followed by a discussion on different nanoscale device phenomena. Certain nanoscale device phenomena (variability/stochasticity etc), which are otherwise undesirable for reliable memory and storage applications, form the basis for low power and highly scalable RNG/PUF circuits. Detailed qualitative comparison and benchmarking of all implementations is performed.

  18. Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

    Science.gov (United States)

    Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

    2008-08-01

    The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

  19. Total Ionizing Dose effects in 130-nm commercial CMOS technologies for HEP experiments

    CERN Document Server

    Gonella, L; Silvestri, M; Gerardin, S; Pantano, D; Re, V; Manghisoni, M; Ratti, L; Ranieri, A

    2007-01-01

    The impact of foundry-to-foundry variability and bias conditions during irradiation on the Total Ionizing Dose (TID) response of commercial 130-nm CMOS technologies have been investigated for applications in High Energy Physics (HEP) experiments. n- and p-channel MOSFETs from three different manufacturers have been irradiated with X-rays up to more than 100 Mrad (SiO2). Even though the effects of TID are qualitatively similar, the amount of degradation is shown to vary considerably from foundry to foundry, probably depending on the processing of the STI oxide and/or doping profile in the substrate. The bias during irradiation showed to have a strong impact as well on the TID response, proving that exposure at worst case bias conditions largely overestimates the degradation a device may experience during its lifetime. Overall, our results increase the confidence that 130-nm CMOS technologies can be used in future HEP experiments even without Hardness-By-Design solutions, provided that constant monitoring of th...

  20. Radiation tolerance study of a commercial 65 nm CMOS technology for high energy physics applications

    Energy Technology Data Exchange (ETDEWEB)

    Ding, Lili, E-mail: lili03.ding@gmail.com [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy); State Key Laboratory of Pulsed Radiation Simulation and Effect, Northwest Institute of Nuclear Technology, Xi' an (China); Gerardin, Simone [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy); Bagatin, Marta [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); Bisello, Dario [Department of Physics and Astronomy, Padova University, Via Marzolo 8, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy); Mattiazzo, Serena [Department of Physics and Astronomy, Padova University, Via Marzolo 8, 35131 Padova (Italy); Paccagnella, Alessandro [Department of Information Engineering, Padova University, Via Gradenigo 6/B, 35131 Padova (Italy); INFN, Padova, Via Marzolo 8, 35131 Padova (Italy)

    2016-09-21

    This paper reports the radiation tolerance study of a commercial 65 nm technology, which is a strong candidate for the Large Hadron Collider applications. After exposure to 3 MeV protons till 1 Grad dose, the 65 nm CMOS transistors, especially the pMOSFETs, showed severe long-term degradation mainly in the saturation drain currents. There were some differences between the degradation levels in the nMOSFETs and the pMOSFETs, which were likely attributed to the positive charges trapped in the gate spacers. After exposure to heavy ions till multiple strikes, the pMOSFETs did not show any sudden loss of drain currents, the degradations in the characteristics were negligible.

  1. April 1977 The Cape gurnard is a commercially exploited species of ...

    African Journals Online (AJOL)

    The Cape gurnard is a commercially exploited species of which the annual landings between ... fishing operations took place along the eastern Cape coast of South Africa ..... Handbook of computation for biological statistics offish populations.

  2. Efforts to Overcome Child Commercial Sexual Exploitation Victims in City Tourism Area, Manado

    Directory of Open Access Journals (Sweden)

    Rahmat Hidayat

    2017-09-01

    Full Text Available The tourism sector has a significant contribution to the economy of Manado City, North Sulawesi Province. However, on the other hand, it has a negative effect on the increase in the number of child commercial sexual exploitation victims and makes children into commercial sex workers. Despite not effective, the Local Government of Manado City, North Sulawesi Province, has made efforts to cope with the child commercial sexual exploitation victims. In connection with the case, this study is designed to analyze the causes of ineffectiveness of Local Government efforts in tackling child commercial sexual exploitation victims. The study was conducted in tourism area of Manado City, North Sulawesi Province. The informants involved in this study were divided into two types: experts and non-experts. The informants were determined by using Opportunistic Sampling, and the sampling is using Snowball Sampling. The results of the study showed that the development of tourism sector has negative effect on children in the communities. Efforts made to cope with child commercial sexual exploitation victims by the local government and relevant parties have not been effective due to limited allocation of budgets and skilled, quality human resources, the lack of harmonious understanding between police with judges and public prosecutors as law apparatus, supervision, and protection of victims in solving the cases of child commercial sexual exploitation victims, the implementation of action committee’s duties and responsibility have been not effect, the number of obstacles facing them.

  3. Understanding and Responding to the Needs of Commercially Sexually Exploited Youth: Recommendations for the Mental Health Provider.

    Science.gov (United States)

    Ijadi-Maghsoodi, Roya; Cook, Mekeila; Barnert, Elizabeth S; Gaboian, Shushanik; Bath, Eraka

    2016-01-01

    Mental health providers are frequently at the forefront of addressing the multifaceted needs of commercially sexually exploited youth. This article provides an overview of the definition of commercial sexual exploitation of children and relevant legislation including the shift toward decriminalization of commercially sexually exploited youth. To provide clinicians with tools needed to deliver competent care to this population, a review of risk factors for commercial sexual exploitation of children and the role of the clinician in identification, assessment, and treatment of commercially sexually exploited youth are discussed. Published by Elsevier Inc.

  4. For your first born child: an ethical defense of the exploitation argument against commercial surrogacy.

    Science.gov (United States)

    Osberg, Brendan

    2006-01-01

    In this essay I explore two arguments against commercial surrogacy, based on commodification and exploitation respectively. I adopt a consequentialist framework and argue that commodification arguments must be grounded in a resultant harm to either child or surrogate, and that a priori arguments which condemn the practice for puritanical reasons cannot form a basis for public law. Furthermore there is no overwhelming evidence of harm caused to either party involved in commercial surrogacy, and hence Canadian law (which forbids the practice) must (and can) be justified on exploitative grounds. Objections raised by Wilkinson based on an 'isolated case' approach are addressed when one takes into account the political implications of public policy. I argue that is precisely these implications that justify laws forbidding commercial surrogacy on the grounds of preventing systematic exploitation.

  5. Stable isotopes reveal the effect of trawl fisheries on the diet of commercially exploited species

    DEFF Research Database (Denmark)

    Hinz, Hilmar; Moranta, Joan; Balestrini, Stephen

    2017-01-01

    both negatively and positively influence the quantity and quality of food available. Using δ 13C and δ 15N we investigated potential diet changes of three commercially exploited species across trawling gradients in the Kattegat (plaice, dab and Norway lobster (Nephrops)) and the Irish Sea (Nephrops...

  6. Little Adults: Child and Teenage Commercial Sexual Exploitation in Contemporary Brazilian Cinema

    Science.gov (United States)

    da Silvia, Antonio Marcio

    2016-01-01

    This current study explores three contemporary Brazilian films' depiction of commercial sexual exploitation of young girls and teenagers. It points out how the young female characters cope with the abuses they suffer and proposes that these filmic representations of the characters' experiences expose a significant social problem of contemporary…

  7. Sexual slavery without borders: trafficking for commercial sexual exploitation in India.

    Science.gov (United States)

    Joffres, Christine; Mills, Edward; Joffres, Michel; Khanna, Tinku; Walia, Harleen; Grund, Darrin

    2008-09-25

    Trafficking in women and children is a gross violation of human rights. However, this does not prevent an estimated 800 000 women and children to be trafficked each year across international borders. Eighty per cent of trafficked persons end in forced sex work. India has been identified as one of the Asian countries where trafficking for commercial sexual exploitation has reached alarming levels. While there is a considerable amount of internal trafficking from one state to another or within states, India has also emerged as a international supplier of trafficked women and children to the Gulf States and South East Asia, as well as a destination country for women and girls trafficked for commercial sexual exploitation from Nepal and Bangladesh. Trafficking for commercial sexual exploitation is a highly profitable and low risk business that preys on particularly vulnerable populations. This paper presents an overview of the trafficking of women and girls for sexual exploitation (CSE) in India; identifies the health impacts of CSE; and suggest strategies to respond to trafficking and related issues.

  8. Sexual slavery without borders: trafficking for commercial sexual exploitation in India

    Science.gov (United States)

    Joffres, Christine; Mills, Edward; Joffres, Michel; Khanna, Tinku; Walia, Harleen; Grund, Darrin

    2008-01-01

    Trafficking in women and children is a gross violation of human rights. However, this does not prevent an estimated 800 000 women and children to be trafficked each year across international borders. Eighty per cent of trafficked persons end in forced sex work. India has been identified as one of the Asian countries where trafficking for commercial sexual exploitation has reached alarming levels. While there is a considerable amount of internal trafficking from one state to another or within states, India has also emerged as a international supplier of trafficked women and children to the Gulf States and South East Asia, as well as a destination country for women and girls trafficked for commercial sexual exploitation from Nepal and Bangladesh. Trafficking for commercial sexual exploitation is a highly profitable and low risk business that preys on particularly vulnerable populations. This paper presents an overview of the trafficking of women and girls for sexual exploitation (CSE) in India; identifies the health impacts of CSE; and suggest strategies to respond to trafficking and related issues. PMID:18817576

  9. Instruments to Identify Commercially Sexually Exploited Children: Feasibility of Use in an Emergency Department Setting.

    Science.gov (United States)

    Armstrong, Stephanie

    2017-12-01

    This review examines the screening instruments that are in existence today to identify commercially sexually exploited children. The instruments are compared and evaluated for their feasibility of use in an emergency department setting. Four electronic databases were searched to identify screening instruments that assessed solely for commercial sexual exploitation. Search terms included "commercially sexually exploited children," "CSEC," "domestic minor sex trafficking," "DMST," "juvenile sex trafficking," and "JST." Those terms were then searched in combination with each of the following: "tools," "instruments," "screening," "policies," "procedures," "data collection," "evidence," and "validity." Six screening instruments were found to meet the inclusion criteria. Variation among instruments included number of questions, ease of administration, information sources, scoring methods, and training information provided. Two instruments were determined to be highly feasible for use in the emergency department setting, those being the Asian Health Services and Banteay Srei's CSEC Screening Protocol and Greenbaum et al's CSEC/child sex trafficking 6-item screening tool. A current dearth of screening instruments was confirmed. It is recommended that additional screening instruments be created to include developmentally appropriate instruments for preadolescent children. Numerous positive features were identified within the instruments in this review and are suggested for use in future screening instruments, including succinctness, a simple format, easy administration, training materials, sample questions, multiple information sources, designation of questions requiring mandatory reporting, a straightforward scoring system, and an algorithm format.

  10. Helix Nebula and CERN: A Symbiotic approach to exploiting commercial clouds

    CERN Document Server

    Barreiro Megino, Fernando Harald; Kucharczyk, Katarzyna; Medrano Llamas, Ramón; van der Ster, Daniel

    2014-01-01

    The recent paradigm shift toward cloud computing in IT, and general interest in "Big Data" in particular, have demonstrated that the computing requirements of HEP are no longer globally unique. Indeed, the CERN IT department and LHC experiments have already made significant R&D investments in delivering and exploiting cloud computing resources. While a number of technical evaluations of interesting commercial offerings from global IT enterprises have been performed by various physics labs, further technical, security, sociological, and legal issues need to be address before their large-scale adoption by the research community can be envisaged. Helix Nebula - the Science Cloud is an initiative that explores these questions by joining the forces of three European research institutes (CERN, ESA and EMBL) with leading European commercial IT enterprises. The goals of Helix Nebula are to establish a cloud platform federating multiple commercial cloud providers, along with new business models, which can sustain ...

  11. Helix Nebula and CERN: A Symbiotic approach to exploiting commercial clouds

    CERN Multimedia

    Barreiro Megino, Fernando Harald; Kucharczyk, Katarzyna; Medrano Llamas, Ramón; van der Ster, Daniel

    2013-01-01

    The recent paradigm shift toward cloud computing in IT, and general interest in "Big Data" in particular, have demonstrated that the computing requirements of HEP are no longer globally unique. Indeed, the CERN IT department and LHC experiments have already made significant R&D; investments in delivering and exploiting cloud computing resources. While a number of technical evaluations of interesting commercial offerings from global IT enterprises have been performed by various physics labs, further technical, security, sociological, and legal issues need to be address before their large-scale adoption by the research community can be envisaged. Helix Nebula - the Science Cloud is an initiative that explores these questions by joining the forces of three European research institutes (CERN, ESA and EMBL) with leading European commercial IT enterprises. The goals of Helix Nebula are to establish a cloud platform federating multiple commercial cloud providers, along with new business models, which can sustain...

  12. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric,I et al.

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 1015 neq=cm2 , nearly 100% detection efficiency and a spatial resolution of about 3 μm were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

  13. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric, Ivan; Backhaus, Malte; Barbero, Marlon; Benoit, Mathieu; Berger, Niklaus; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Dannheim, Dominik; Dierlamm, Alexander; Feigl, Simon; Fischer, Peter; Fougeron, Denis; Garcia-Sciveres, Maurice; Heim, Timon; Hügging, Fabian; Kiehn, Moritz; Kreidl, Christian; Krüger, Hans; La Rosa, Alessandro; Liu, Jian; Lütticke, Florian; Mariñas, Carlos; Meng, Lingxin; Miucci, Antonio; Münstermann, Daniel; Nguyen, Hong Hanh; Obermann, Theresa; Pangaud, Patrick; Perrevoort, Ann-Kathrin; Rozanov, Alexandre; Schöning, André; Schwenker, Benjamin; Wiedner, Dirk

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 10 15 n eq = cm 2 , nearly 100% detection ef fi ciency and a spatial resolution of about 3 μ m were demonstrated. Since 2011 the HV detectors have fi rst applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process

  14. An acetone microsensor with a ring oscillator circuit fabricated using the commercial 0.18 μm CMOS process.

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

    2014-07-17

    This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm.

  15. Child trafficking and commercial sexual exploitation: a review of promising prevention policies and programs.

    Science.gov (United States)

    Rafferty, Yvonne

    2013-10-01

    Child trafficking, including commercial sexual exploitation (CSE), is one of the fastest growing and most lucrative criminal activities in the world. The global enslavement of children affects countless numbers of victims who are trafficked within their home countries or transported away from their homes and treated as commodities to be bought, sold, and resold for labor or sexual exploitation. All over the world, girls are particularly likely to be trafficked into the sex trade: Girls and women constitute 98% of those who are trafficked for CSE. Health and safety standards in exploitative settings are generally extremely low, and the degree of experienced violence has been linked with adverse physical, psychological, and social-emotional development. The human-rights-based approach to child trafficking provides a comprehensive conceptual framework whereby victim-focused and law enforcement responses can be developed, implemented, and evaluated. This article highlights promising policies and programs designed to prevent child trafficking and CSE by combating demand for sex with children, reducing supply, and strengthening communities. The literature reviewed includes academic publications as well as international and governmental and nongovernmental reports. Implications for social policy and future research are presented. © 2013 American Orthopsychiatric Association.

  16. An exploratory model of girls' vulnerability to commercial sexual exploitation in prostitution.

    Science.gov (United States)

    Reid, Joan A

    2011-05-01

    Due to inaccessibility of child victims of commercial sexual exploitation, the majority of emergent research on the problem lacks theoretical framing or sufficient data for quantitative analysis. Drawing from Agnew's general strain theory, this study utilized structural equation modeling to explore: whether caregiver strain is linked to child maltreatment, if experiencing maltreatment is associated with risk-inflating behaviors or sexual denigration of self/others, and if these behavioral and psychosocial dysfunctions are related to vulnerability to commercial sexual exploitation. The proposed model was tested with data from 174 predominately African American women, 12% of whom indicated involvement in prostitution while a minor. Findings revealed child maltreatment worsened with increased caregiver strain. Experiencing child maltreatment was linked to running away, initiating substance use at earlier ages, and higher levels of sexual denigration of self/others. Sexual denigration of self/others was significantly related to the likelihood of prostitution as a minor. The network of variables in the model accounted for 34% of the variance in prostitution as a minor.

  17. An ethnomethodological approach to examine exploitation in the context of capacity, trust and experience of commercial surrogacy in India

    OpenAIRE

    Saravanan, Sheela

    2013-01-01

    The socio-ethical concerns regarding exploitation in commercial surrogacy are premised on asymmetric vulnerability and the commercialization of women’s reproductive capacity to suit individualistic motives. In examining the exploitation argument, this article reviews the social contract theory that describes an individual as an ‘economic man’ with moral and/or political motivations to satisfy individual desires. This study considers the critique by feminists, who argue that ...

  18. The Peace and Power Conceptual Model: An Assessment Guide for School Nurses Regarding Commercial Sexual Exploitation of Children.

    Science.gov (United States)

    Fraley, Hannah E; Aronowitz, Teri

    2017-10-01

    Human trafficking is a global problem; more than half of all victims are children. In the United States (US), at-risk youth continue to attend school. School nurses are on the frontlines, presenting a window of opportunity to identify and prevent exploitation. Available papers targeting school nurses report that school nurses may lack awareness of commercial sexual exploitation and may have attitudes and misperceptions about behaviors of school children at risk. This is a theoretical paper applying the Peace and Power Conceptual Model to understand the role of school nurses in commercial sexual exploitation of children.

  19. Stable isotopes reveal the effect of trawl fisheries on the diet of commercially exploited species.

    Science.gov (United States)

    Hinz, Hilmar; Moranta, Joan; Balestrini, Stephen; Sciberras, Marija; Pantin, Julia R; Monnington, James; Zalewski, Alex; Kaiser, Michel J; Sköld, Mattias; Jonsson, Patrik; Bastardie, Francois; Hiddink, Jan Geert

    2017-07-24

    Bottom trawling can change food availability for benthivorous demersal species by (i) changing benthic prey composition through physical seabed impacts and (ii) by removing overall benthic consumer biomass increasing the net availability of benthic prey for remaining individuals. Thus trawling may both negatively and positively influence the quantity and quality of food available. Using δ 13 C and δ 15 N we investigated potential diet changes of three commercially exploited species across trawling gradients in the Kattegat (plaice, dab and Norway lobster (Nephrops)) and the Irish Sea (Nephrops). In the Kattegat, trawling affected primarily the biomass of benthic consumers, lowering competition. Nephrops showed significant positive relationships for δ 13 C and a domed relationship for δ 15 N with trawling. In the Irish Sea, intense trawling had a negative effect on benthic prey. δ 13 C and δ 15 N thus showed the inverse relationships to those observed in the Kattegat. Plaice from the Kattegat, showed a significant relationship with trawling intensity for δ 13 C, but not for δ 15 N. No relationship was found for dab. Changes of δ 13 C and δ 15 N correlated with changes in condition of species. The results show that the removal of demersal competitors and benthos by trawling can change the diets of commercial species, ultimately affecting their body condition.

  20. Helix Nebula and CERN: A Symbiotic approach to exploiting commercial clouds

    International Nuclear Information System (INIS)

    Megino, Fernando H Barreiro; Jones, Robert; Llamas, Ramón Medrano; Ster, Daniel van der; Kucharczyk, Katarzyna

    2014-01-01

    The recent paradigm shift toward cloud computing in IT, and general interest in 'Big Data' in particular, have demonstrated that the computing requirements of HEP are no longer globally unique. Indeed, the CERN IT department and LHC experiments have already made significant R and D investments in delivering and exploiting cloud computing resources. While a number of technical evaluations of interesting commercial offerings from global IT enterprises have been performed by various physics labs, further technical, security, sociological, and legal issues need to be address before their large-scale adoption by the research community can be envisaged. Helix Nebula – the Science Cloud is an initiative that explores these questions by joining the forces of three European research institutes (CERN, ESA and EMBL) with leading European commercial IT enterprises. The goals of Helix Nebula are to establish a cloud platform federating multiple commercial cloud providers, along with new business models, which can sustain the cloud marketplace for years to come. This contribution will summarize the participation of CERN in Helix Nebula. We will explain CERN's flagship use-case and the model used to integrate several cloud providers with an LHC experiment's workload management system. During the first proof of concept, this project contributed over 40.000 CPU-days of Monte Carlo production throughput to the ATLAS experiment with marginal manpower required. CERN's experience, together with that of ESA and EMBL, is providing a great insight into the cloud computing industry and highlighted several challenges that are being tackled in order to ease the export of the scientific workloads to the cloud environments.

  1. Helix Nebula and CERN: A Symbiotic approach to exploiting commercial clouds

    Science.gov (United States)

    Barreiro Megino, Fernando H.; Jones, Robert; Kucharczyk, Katarzyna; Medrano Llamas, Ramón; van der Ster, Daniel

    2014-06-01

    The recent paradigm shift toward cloud computing in IT, and general interest in "Big Data" in particular, have demonstrated that the computing requirements of HEP are no longer globally unique. Indeed, the CERN IT department and LHC experiments have already made significant R&D investments in delivering and exploiting cloud computing resources. While a number of technical evaluations of interesting commercial offerings from global IT enterprises have been performed by various physics labs, further technical, security, sociological, and legal issues need to be address before their large-scale adoption by the research community can be envisaged. Helix Nebula - the Science Cloud is an initiative that explores these questions by joining the forces of three European research institutes (CERN, ESA and EMBL) with leading European commercial IT enterprises. The goals of Helix Nebula are to establish a cloud platform federating multiple commercial cloud providers, along with new business models, which can sustain the cloud marketplace for years to come. This contribution will summarize the participation of CERN in Helix Nebula. We will explain CERN's flagship use-case and the model used to integrate several cloud providers with an LHC experiment's workload management system. During the first proof of concept, this project contributed over 40.000 CPU-days of Monte Carlo production throughput to the ATLAS experiment with marginal manpower required. CERN's experience, together with that of ESA and EMBL, is providing a great insight into the cloud computing industry and highlighted several challenges that are being tackled in order to ease the export of the scientific workloads to the cloud environments.

  2. On the relationships between commercial sexual exploitation/prostitution, substance dependency, and delinquency in youthful offenders.

    Science.gov (United States)

    Reid, Joan A; Piquero, Alex R

    2014-01-01

    Researchers have consistently linked commercial sexual exploitation (CSE) of youth and involvement in prostitution with substance dependency and delinquency. Yet, important questions remain regarding the directionality and mechanisms driving this association. Utilizing a sample of 114 CSE/prostituted youth participating in the Pathways to Desistance study-a longitudinal investigation of the transition from adolescence to adulthood among serious adolescent offenders-the current study examined key criminal career parameters of CSE/prostitution including age of onset and rate of recurrence. Additionally, structural equation modeling (SEM) was used to explore concurrent associations and causal links between CSE/prostitution and drug involvement. Findings show a general sequential pattern of the ages of onset with substance use and selling drugs occurring prior to CSE/prostitution, evidence that a small group with chronic CSE/prostitution account for the majority of CSE/prostitution occurrences, and high rates of repeated CSE/prostitution. SEM results suggest CSE/prostituted youth persist in drug involvement from year to year but infrequently experience perpetuation of CSE/prostitution from year to year. Concurrent associations between CSE/prostitution and drug involvement were found across the length of the study. Additionally, drug involvement at one year was linked to CSE/prostitution during the subsequent year during early years of the study. © The Author(s) 2014.

  3. Child sex trafficking and commercial sexual exploitation: health care needs of victims.

    Science.gov (United States)

    Greenbaum, Jordan; Crawford-Jakubiak, James E

    2015-03-01

    Child sex trafficking and commercial sexual exploitation of children (CSEC) are major public health problems in the United States and throughout the world. Despite large numbers of American and foreign youth affected and a plethora of serious physical and mental health problems associated with CSEC, there is limited information available to pediatricians regarding the nature and scope of human trafficking and how pediatricians and other health care providers may help protect children. Knowledge of risk factors, recruitment practices, possible indicators of CSEC, and common medical and behavioral health problems experienced by victims will help pediatricians recognize potential victims and respond appropriately. As health care providers, educators, and leaders in child advocacy, pediatricians play an essential role in addressing the public health issues faced by child victims of CSEC. Their roles can include working to increase recognition of CSEC, providing direct care and anticipatory guidance related to CSEC, engaging in collaborative efforts with medical and nonmedical colleagues to provide for the complex needs of youth, and educating child-serving professionals and the public. Copyright © 2015 by the American Academy of Pediatrics.

  4. Commercially sexually exploited youths' health care experiences, barriers, and recommendations: A qualitative analysis.

    Science.gov (United States)

    Ijadi-Maghsoodi, Roya; Bath, Eraka; Cook, Mekeila; Textor, Lauren; Barnert, Elizabeth

    2018-02-01

    The current study sought to understand commercially sexually exploited (CSE) youths' health care experiences, barriers to care, and recommendations for improving health care services. We conducted focus groups (N=5) with 18 CSE youth from February 2015 through May 2016 at two group homes serving CSE youth in Southern California. We performed thematic content analysis to identify emergent themes about CSE youths' perspectives on health care. Youth described facilitators to care, including availability of services such as screening for sexually transmitted infections, knowledge about sexual health, and a strong motivation to stay healthy. Barriers included feeling judged, concerns about confidentiality, fear, perceived low quality of services, and self-reliance. Overall, youth emphasized self-reliance and "street smarts" for survival and de-emphasized "victimhood," which shaped their interactions with health care, and recommended that health providers develop increased understanding of CSE youth. Our findings suggest that providers and community agencies can play an essential role in raising awareness of the needs of CSE youth and meet their health needs through creating a non-judgmental environment in health care settings that validates the experiences of these youth. Published by Elsevier Ltd.

  5. Age-graded risks for commercial sexual exploitation of male and female youth.

    Science.gov (United States)

    Reid, Joan A; Piquero, Alex R

    2014-06-01

    Emerging evidence indicates male youth are affected by commercial sexual exploitation (CSE). However, most studies investigating risk markers influencing age of onset of CSE have focused on vulnerabilities of girls and women. Using a sample of 1,354 serious youthful offenders (of whom approximately 8% of males and females reported being paid for sex), the current study assessed whether risks associated with age of onset of CSE for girls and young women operated similarly in boys and young men. Findings showed that African American male youth were at heightened risk for CSE, while female youth of all races/ethnicities were at similar risk. For all youth, maternal substance use and earlier age of first sex were associated with early age of onset of CSE. For male youth, experiencing rape and substance use dependency were associated with early age of onset. Psychotic symptoms, likely experienced as social alienation, were associated with both early and late age of onset. For all youth, lower educational attainment was associated with CSE beginning in later adolescence or young adulthood. In addition, substance use dependency was linked to late age of onset for female youth. Implications of the study findings for theory development and application to CSE are noted.

  6. An ethnomethodological approach to examine exploitation in the context of capacity, trust and experience of commercial surrogacy in India

    Science.gov (United States)

    2013-01-01

    The socio-ethical concerns regarding exploitation in commercial surrogacy are premised on asymmetric vulnerability and the commercialization of women’s reproductive capacity to suit individualistic motives. In examining the exploitation argument, this article reviews the social contract theory that describes an individual as an ‘economic man’ with moral and/or political motivations to satisfy individual desires. This study considers the critique by feminists, who argue that patriarchal and medical control prevails in the surrogacy contracts. It also explores the exploitative dynamics amongst actors in the light of Baier’s conceptualization of trust and human relationship, within which both justice and exploitation thrive, and Foucault’s concept of bio-power. Drawing on these concepts, this paper aims to investigate the manifestations of exploitation in commercial surrogacy in the context of trust, power and experiences of actors, using a case study of one clinic in India. The actors’ experiences are evaluated at different stages of the surrogacy process: recruitment, medical procedures, living in the surrogate home, bonding with the child and amongst actors, financial dealings, relinquishment and post-relinquishment. This study applies ethnomethodology to identify phenomena as perceived by the actors in a situation, giving importance to their interpretations of the rules that make collective activity possible. The methods include semi-structured interviews, discussions, participant observation and explanation of the phenomena from the actors’ perspectives. Between August 2009 and April 2010, 13 surrogate mothers (SMs), 4 intended parents (IPs) and 2 medical practitioners (MPs) from one clinic in Western India were interviewed. This study reveals that asymmetries of capacity amongst the MPs, SMs, IPs and surrogate agents (SAs) lead to a network of trust and designation of powers through rules, bringing out the relevance of Baier’s conceptualization

  7. An ethnomethodological approach to examine exploitation in the context of capacity, trust and experience of commercial surrogacy in India.

    Science.gov (United States)

    Saravanan, Sheela

    2013-08-20

    The socio-ethical concerns regarding exploitation in commercial surrogacy are premised on asymmetric vulnerability and the commercialization of women's reproductive capacity to suit individualistic motives. In examining the exploitation argument, this article reviews the social contract theory that describes an individual as an 'economic man' with moral and/or political motivations to satisfy individual desires. This study considers the critique by feminists, who argue that patriarchal and medical control prevails in the surrogacy contracts. It also explores the exploitative dynamics amongst actors in the light of Baier's conceptualization of trust and human relationship, within which both justice and exploitation thrive, and Foucault's concept of bio-power. Drawing on these concepts, this paper aims to investigate the manifestations of exploitation in commercial surrogacy in the context of trust, power and experiences of actors, using a case study of one clinic in India. The actors' experiences are evaluated at different stages of the surrogacy process: recruitment, medical procedures, living in the surrogate home, bonding with the child and amongst actors, financial dealings, relinquishment and post-relinquishment.This study applies ethnomethodology to identify phenomena as perceived by the actors in a situation, giving importance to their interpretations of the rules that make collective activity possible. The methods include semi-structured interviews, discussions, participant observation and explanation of the phenomena from the actors' perspectives. Between August 2009 and April 2010, 13 surrogate mothers (SMs), 4 intended parents (IPs) and 2 medical practitioners (MPs) from one clinic in Western India were interviewed.This study reveals that asymmetries of capacity amongst the MPs, SMs, IPs and surrogate agents (SAs) lead to a network of trust and designation of powers through rules, bringing out the relevance of Baier's conceptualization of asymmetric

  8. Assessing the viability of the Species at Risk Act in managing commercial exploitation and recovery of threatened and endangered marine fish in Canada

    OpenAIRE

    Druce, Courtney Danielle

    2012-01-01

    Commercially exploited threatened or endangered marine fish are consistently declined for listing under Canada’s Species at Risk Act (SARA), largely due to predicted socio-economic impacts associated with SARA’s prohibitions. However, commercial exploitation can be exempted from SARA’s general prohibitions. If exemptions were utilized, commercially exploited species could benefit from other aspects of SARA listing, and support continued economic opportunities for fishers. I conducted a litera...

  9. Predicting running away in girls who are victims of commercial sexual exploitation.

    Science.gov (United States)

    Hershberger, Alexandra R; Sanders, Jasmyn; Chick, Crisanna; Jessup, Megan; Hanlin, Hugh; Cyders, Melissa A

    2018-05-01

    Youth that are victims of commercial sexual exploitation of children (CSEC) have a host of clinical problems and often run away from home, residential care, and treatment, which complicates and limits treatment effectiveness. No research to date has attempted to predict running away in CSEC victims. The present study aimed to 1) characterize a clinically referred sample of girls who were victims of CSEC and compare them to other high-risk girls (i.e., girls who also have a history of trauma and running away, but deny CSEC); and 2) examine the utility of using the Youth Level of Service/Case Management Inventory (YLS/CMI) to predict future running away. Data were collected from de-identified charts of 80 girls (mean age = 15.38, SD = 1.3, 37.9% White, 52.5% CSEC victims) who were referred for psychological assessment by the Department of Child Services. Girls in the CSEC group were more likely to have experienced sexual abuse (χ 2  = 6.85, p = .009), an STI (χ 2  = 6.45, p = .01), a post-traumatic stress disorder diagnosis (χ 2  = 11.84, p = .001), and a substance use disorder diagnosis (χ 2  = 11.32, p = .001) than high-risk girls. Moderated regression results indicated that YLS/CMI scores significantly predicted future running away among the CSEC group (β = 0.23, SE = .06, p = .02), but not the high-risk group (β = -.008, SE = .11, p =.90). The YLS/CMI shows initial promise for predicting future running away in girls who are CSEC victims. Predicting running away can help identify those at risk for and prevent running away and improve treatment outcomes. We hope current findings stimulate future work in this area. Copyright © 2018 Elsevier Ltd. All rights reserved.

  10. Diverting victims of commercial sexual exploitation from juvenile detention: development of the InterCSECt screening protocol.

    Science.gov (United States)

    Salisbury, Emily J; Dabney, Jonathan D; Russell, Kelli

    2015-04-01

    Identifying victims of commercial sexual exploitation in the juvenile justice system is a challenging complexity requiring concerted organizational commitment. Using a three-tiered, trauma-informed screening process, a 3½-month pilot intervention was implemented in Clark County Juvenile Court (Washington) to identify victims in an effort to connect them to community youth advocates and sexual assault resources. A total of 535 boys and girls ages 9 to 19 were screened during intake; 47 of these youth reported risk factors associated with commercial sexual exploitation of children (CSEC) and were subsequently referred to community advocates. Six youth (all girls) were confirmed CSEC victims and were successfully diverted from juvenile detention. Study results suggest that despite the lack of reliable data surrounding the prevalence of CSEC, juvenile justice agencies need to become educated on the risk factors to triage victims to services. © The Author(s) 2014.

  11. Commercial surrogacy in India: The presumption of adaptive preference formation, the possibility of autonomy and the persistence of exploitation

    OpenAIRE

    Fellowes, Melanie G.

    2017-01-01

    India’s proposed 2016 Bill on the regulation of surrogacy is its latest attempt to respond to criticism regarding the lack of protection given to those entering into a commercial surrogacy arrangement. Adaptive preference theorists presume that a decision made in an oppressive environment, which is inconsistent with the woman’s well-being, is not autonomous and that she is therefore exploited. This article challenges this presumption, arguing that some decisions may be suspected as adaptive p...

  12. The Trauma of Commercial Sexual Exploitation of Youth: A Comparison of CSE Victims to Sexual Abuse Victims in a Clinical Sample.

    Science.gov (United States)

    Cole, Jennifer; Sprang, Ginny; Lee, Robert; Cohen, Judith

    2016-01-01

    This study examined the demographic features, trauma profiles, clinical severity indicators, problem behaviors, and service utilization characteristics of youth victims of commercial sexual exploitation (CSE) compared with a matched sample of sexually abused/assaulted youth who were not exploited in commercial sex. Secondary data analysis and propensity score matching were used to select a sample of 215 help-seeking youth who were exploited in prostitution (n = 43) or who were sexually abused/assaulted but not exploited in prostitution (n = 172) from the National Child Traumatic Stress Network Core Data Set (NCTSN CDS). Propensity Score Matching was used to select a comparison sample based on age, race, ethnicity, and primary residence. Statistically significant differences were noted between the groups on standardized (e.g., UCLA Posttraumatic Stress Disorder Reaction Index [PTSD-RI], Child Behavior Checklist [CBCL]) and other measures of emotional and behavioral problems (e.g., avoidance and hyperarousal symptoms, dissociation, truancy, running away, conduct disorder, sexualized behaviors, and substance abuse). This study provides useful insight into the symptom and service utilization profiles of youth exploited in commercial sex as compared with youth with other types of sexually exploitive experiences. Targeted screening and event-sensitive measures are recommended to more accurately identify youth exploited in commercial sex. More research is needed to determine if and what modifications to trauma therapies may be required to address the more severe symptomatology and behavior problems associated with youth exploited in commercial sex. © The Author(s) 2014.

  13. Commercially sexually exploited girls and participant perceptions of blameworthiness: examining the effects of victimization history and race disclosure.

    Science.gov (United States)

    Menaker, Tasha A; Franklin, Cortney A

    2013-07-01

    Prostitution among female youth has been largely misunderstood, trivialized, or ignored. Increased attention has been directed toward juvenile female delinquency, particularly related to the overlap in their status as victims and offenders. Areas in this research continue to be underinvestigated, however, especially with regard to public perceptions of commercially sexually exploited girls. The current study used survey questionnaires to examine participant perceptions of the blameworthiness of a prostituted minor while considering her victimization history disclosure and race. Results indicate that victimization history disclosure significantly reduced perceptions of blameworthiness and reduced blameworthiness operated similarly for Caucasian and African American females forced into prostitution. Further research directions are discussed.

  14. Commercial surrogacy: how provisions of monetary remuneration and powers of international law can prevent exploitation of gestational surrogates.

    Science.gov (United States)

    Ramskold, Louise Anna Helena; Posner, Marcus Paul

    2013-06-01

    Increasing globalisation and advances in artificial reproductive techniques have opened up a whole new range of possibilities for infertile couples across the globe. Inter-country gestational surrogacy with monetary remuneration is one of the products of medical tourism meeting in vitro fertilisation embryo transfer. Filled with potential, it has also been a hot topic of discussion in legal and bioethics spheres. Fears of exploitation and breach of autonomy have sprung from the current situation, where there is no international regulation of surrogacy agreements--only a web of conflicting national laws that generates loopholes and removes safeguards for both the surrogate and commissioning couple. This article argues the need for evidence-based international laws and regulations as the only way to resolve both the ethical and legal issues around commercial surrogacy. In addition, a Hague Convention on inter-country surrogacy agreements is proposed to resolve the muddled state of affairs and enable commercial surrogacy to demonstrate its full potential.

  15. Exploring mental health and substance use treatment needs of commercially sexually exploited youth participating in a specialty juvenile court.

    Science.gov (United States)

    Cook, Mekeila C; Barnert, Elizabeth; Ijadi-Maghsoodi, Roya; Ports, Kayleen; Bath, Eraka

    2018-03-20

    The study sought to: 1) describe the mental health and substance use profiles among participants of a specialty trafficking court program (the Succeed Though Achievement and Resilience Court); 2) describe youths' mental health and substance use treatment prior to participating in the program; and 3) examine whether abuse influences report of mental health problems and/or substance use. Retrospective case review of court files was performed on commercially sexually exploited youth who volunteered to participate in the court from 2012 to 2014 (N = 184). All participants were female. Mental health problems and report of substance use was high among this population. Substance use differed at statistically significant levels between youth with a documented abuse history compared to those with no abuse history. Substance use also differed by report of mental health problems. Unexpected findings included the high rate of hospitalization for mental health problems and relatively low substance use treatment prior to STAR Court participation. Opportunities for improvement in critical points of contact to identify commercially sexually exploited youth and address their health needs are discussed.

  16. Human trafficking: Commercial sexual exploitation and forced domestic labour in African literature

    Directory of Open Access Journals (Sweden)

    Urama Evelyn Nwachukwu

    2017-05-01

    Full Text Available Just like social occurrences such as human sacrifice and slavery enhanced retardation of progress in Africa in the past, trafficking is another social occurrence addressed in contemporary African literature that impedes progress and tarnishes the image of the victims. Human trafficking is rampant in Africans and some part of the world in this 21st century. This paper examines how Akachi Adimora-Ezeigbo’s Trafficked (2008 and Chika Unigwe’s On Black Sisters′ Street (2009 highlight social occurrences and how they contribute to the spread of girl trafficking in Africa. It also explores how both men and women are partners in trafficking, forming trafficking networks that lure girls from Nigeria to Europe and make huge profits from their misery. These pimps use ‘juju magic’ and rituals as a threat to exert complete control over the girls and also to ensure their compliance. The trafficked girls share their life experiences by telling their tales of woes exposing the shame that accompanies the sex trade and the stigmatization they suffer in the society. Their experiences are presented by the authors to highlight the trafficked girls′ pains, misery and struggle for freedom in order to appeal to everybody in the society to fight against human trafficking. The paper also examines how these exploited and depressed trafficked girls that have lost their self-esteem can still live fulfilled lives if government agencies and nongovernmental organizations come to their rescue.

  17. DNA barcoding reveals cryptic diversity within commercially exploited Indo-Malay Carangidae (Teleosteii: Perciformes.

    Directory of Open Access Journals (Sweden)

    Tun Nurul Aimi Mat Jaafar

    Full Text Available BACKGROUND: DNA barcodes, typically focusing on the cytochrome oxidase I gene (COI in many animals, have been used widely as a species-identification tool. The ability of DNA barcoding to distinguish species from a range of taxa and to reveal cryptic species has been well documented. Despite the wealth of DNA barcode data for fish from many temperate regions, there are relatively few available from the Southeast Asian region. Here, we target the marine fish Family Carangidae, one of the most commercially-important families from the Indo-Malay Archipelago (IMA, to produce an initial reference DNA barcode library. METHODOLOGY/PRINCIPAL FINDINGS: Here, a 652 bp region of COI was sequenced for 723 individuals from 36 putative species of Family Carangidae distributed within IMA waters. Within the newly-generated dataset, three described species exhibited conspecific divergences up to ten times greater (4.32-4.82% than mean estimates (0.24-0.39%, indicating a discrepancy with assigned morphological taxonomic identification, and the existence of cryptic species. Variability of the mitochondrial DNA COI region was compared within and among species to evaluate the COI region's suitability for species identification. The trend in range of mean K2P distances observed was generally in accordance with expectations based on taxonomic hierarchy: 0% to 4.82% between individuals within species, 0% to 16.4% between species within genera, and 8.64% to 25.39% between genera within families. The average Kimura 2-parameter (K2P distance between individuals, between species within genera, and between genera within family were 0.37%, 10.53% and 16.56%, respectively. All described species formed monophyletic clusters in the Neighbour-joining phylogenetic tree, although three species representing complexes of six potential cryptic species were detected in Indo-Malay Carangidae; Atule mate, Selar crumenophthalmus and Seriolina nigrofasciata. CONCLUSION/SIGNIFICANCE: This

  18. Evidence from the past: exploitation as cause of commercial extinction of autumn-spawning herring in the Gulf of Riga, Baltic Sea

    DEFF Research Database (Denmark)

    MacKenzie, Brian R; Ojaveer, Henn

    2018-01-01

    Historical marine ecology has shown that many exploited animal populations declined before their abundance was quantified by scientists. This situation applies for autumn-spawning herring (Clupea harengus) in the Baltic Sea. This stock used to be the dominant spawning group of herring in the early...... and biological data and conduct population development simulations to evaluate the hypothesis that exploitation may have been sufficient to lead the stock towards commercial extinction. We found that the estimated exploitation pattern, including exploitation of juveniles, was unsustainable and led to stock...

  19. Taxonomic Identity, Geographic Distribution, and Commercial Exploitation of the Culinary-Medicinal Mushroom Pleurotus nebrodensis (Basidiomycetes).

    Science.gov (United States)

    Venturella, Giuseppe; Zervakis, Georgios I; Polemis, Elias; Gargano, Maria Letizia

    2016-01-01

    An updated overview of the outcome of studies conducted on the culinary-medicinal mushroom Pleurotus nebrodensis is presented by placing emphasis on the clarification of the taxonomic identity of P. nebrodensis and other related taxa possessing entirely white to cream basidiomes, which grow in association with different plants of the family Apiaceae. Cultivation techniques, quality of the product sold and sales price, as well as nutritional and medicinal aspects are discussed. Taking also into consideration the high economic importance of P. nebrodensis, it is essential to proceed with the verification of the commercial strains currently available in the international market under the name of "P. nebrodensis" since it is very probable that many (or most) of them do not represent the real P. nebrodensis. TO confirm this hypothesis, an in silico analysis was conducted on a large of number of ITS1-5.8S-ITS2 rRNA sequences deposited in the National Center for Biotechnology Information database under the name P. nebrodensis. Results demonstrated that all "P nebrodensis" material examined from China (plus several sequences of no reported origin) corresponded to P. eryngii subsp. tuoliensis, with only 2 exceptions, which were grouped within P. eryngii sensu stricto. The real P. nebrodensis biological material from Italy and Greece is certified and is available upon request by the authors at the University of Palermo and the Agricultural University of Athens.

  20. ICHTHYOFAUNA OF WATER BODIES OF THE NATIONAL NATURE PARK “TUZLA LAGOONS” AND ITS COMMERCIAL FISHERIES EXPLOITATION

    Directory of Open Access Journals (Sweden)

    P. Shekk

    2015-09-01

    Full Text Available Purpose. To study of the current species diversity of fish fauna in the water bodies included in the National Park “Tuzla lagoons”, to assess the perspectives of their commercial fisheries exploitation. Methodology. Collection of ichthyological material was performed in different seasons of 2011–2014 across the entire area of lagoons and coastal zone of the Black Sea included in the National Nature Park “Tuzla lagoons”. During commercial fish harvest, the material was collected from commercial fishing gear (gillnets, traps, hoop nets, beach seines. In fall, during the work of the fish catch-release channel, we analyzed the data describing the species composition, abundance and length-weight characteristics of fish migrating through the channel in the sea. We used the method of average representative sampling. During the closed period, ichthyologic material for the analysis was collected from the survey fishing gears. All catches were sorted by species composition. We recorded the total catch and the ratio of different species. Collection and processing of data were carried out using generally accepted methods. Findings. It 2011–2014, 72 fish species belonging to 30 families were detected in waters included in the National Nature Park “Tuzla lagoons”: 58 species in the coastal zone of the sea, 28 species in Dzhenshei and Maly Sasyk, 31 species in Tuzla lagoons. Among the fish detected in sea and freshwaters of the National Nature Park “Tuzla lagoons”, 6 species are listed in the Red Book of Ukraine, 7 are protected by Bern Convention, 4 are lusted in the Red List of the International Union for Conservation of Nature and Natural Resources, and 16 species are listed in the Red Book of the Black Sea. Before 2001, a mullet-rearing fish farm operated in Tuzla lagoons. Its fish productivity depended on the intensity and amounts of stocking which were determined by the regime of the work of lagoon–sea channels, state of natural

  1. Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

    Science.gov (United States)

    Kar-Roy, Arjun; Hurwitz, Paul; Mann, Richard; Qamar, Yasir; Chaudhry, Samir; Zwingman, Robert; Howard, David; Racanelli, Marco

    2012-06-01

    Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in the commercially available TowerJazz CA18 0.18μm mixed-signal CMOS technology platform for advanced read-out integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors (FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor having capacitance density of 8fF/μm2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process results in >50fC/μm2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile memory options in the CA18 technology platform are outlined.

  2. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  3. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  4. Characteristics of child commercial sexual exploitation and sex trafficking victims presenting for medical care in the United States.

    Science.gov (United States)

    Varma, Selina; Gillespie, Scott; McCracken, Courtney; Greenbaum, V Jordan

    2015-06-01

    The objective of the study is to describe distinguishing characteristics of commercial sexual exploitation of children/child sex trafficking victims (CSEC) who present for health care in the pediatric setting. This is a retrospective study of patients aged 12-18 years who presented to any of three pediatric emergency departments or one child protection clinic, and who were identified as suspected victims of CSEC. The sample was compared with gender and age-matched patients with allegations of child sexual abuse/sexual assault (CSA) without evidence of CSEC on variables related to demographics, medical and reproductive history, high-risk behavior, injury history and exam findings. There were 84 study participants, 27 in the CSEC group and 57 in the CSA group. Average age was 15.7 years for CSEC patients and 15.2 years for CSA patients; 100% of the CSEC and 94.6% of the CSA patients were female. The two groups significantly differed in 11 evaluated areas with the CSEC patients more likely to have had experiences with violence, substance use, running away from home, and involvement with child protective services and/or law enforcement. CSEC patients also had a longer history of sexual activity. Adolescent CSEC victims differ from sexual abuse victims without evidence of CSEC in their reproductive history, high risk behavior, involvement with authorities, and history of violence. Copyright © 2015 Elsevier Ltd. All rights reserved.

  5. Barriers to Accessing Detox Facilities, Substance Use Treatment, and Residential Services among Women Impacted by Commercial Sexual Exploitation & Trafficking.

    Science.gov (United States)

    Gerassi, Lara B

    2017-10-06

    More than 50% of women entering substance use treatment in the U.S. reported having traded sex for money or drugs. Women's participation in addiction treatment and related services is essential to their recovery and increased safety, stabilization, and quality of life. This paper's aim is to explore the barriers related to accessing detox facilities and essential services including substance use treatment and residential services for women impacted by commercial sexual exploitation (CSE). Data are drawn from a larger, community-based, grounded theory study. In-depth interview data were collected from 30 adult women who traded sex as adults (through maximum variation and snowball sampling), as well as 20 service providers who come into contact with adult women who trade sex (through nominations and purposive sampling). Finding suggest that women often encountered sobriety requirements, which created barriers to accessing addiction treatment or residential services. Some organizations' policies required evicting women if they were caught using, which created additional challenges for women who relapsed. Women wanted to avoid becoming "dopesick" on the streets or at home, which partially contributed to them needing to maintain their addiction. Consequently, some returned to sex trading, thus increasing their risk of trafficking. Some women engaged in creative strategies, such as claiming they were suicidal, in order to access the detox facilities in hospitals. Some women indicated they were only able to detox when they were forced to do so in jail or prison, often without medical assistance. Implications to improve health care delivery for this population are discussed.

  6. Childhood Maltreatment and Child Protective Services Involvement Among the Commercially Sexually Exploited: A Comparison of Women Who Enter as Juveniles or as Adults.

    Science.gov (United States)

    Cimino, Andrea N; Madden, Elissa E; Hohn, Kris; Cronley, Courtney M; Davis, Jaya B; Magruder, Karen; Kennedy, M Alexis

    2017-04-01

    A risk for commercial sexual exploitation is childhood maltreatment. It's unknown whether juveniles in commercial sexual exploitation experience more childhood maltreatment than adults or how involved child protective services is in investigating maltreatment, a focus of this study. Women (N = 96) who sold sex commercially completed a cross-sectional questionnaire. Descriptive statistics, t tests, chi-squares, and odds ratios were used to examine differences in background, childhood maltreatment, and child protective services involvement by juvenile or adult entry. Although 93% of participants experienced child maltreatment, juveniles had increased odds of parent/caregiver sexual abuse, being left alone, being kicked out, and running away from a parent/caregiver. There were no differences in cumulative childhood maltreatment resulting in an investigation or removal, indicating that juveniles not investigated or removed by child protective services had as much childhood maltreatment as juveniles who were investigated or removed by child protective services. Results highlight the need for child welfare staff to recognize childhood maltreatment as risks for commercial sexual exploitation.

  7. The genus Sida L. - A traditional medicine: Its ethnopharmacological, phytochemical and pharmacological data for commercial exploitation in herbal drugs industry.

    Science.gov (United States)

    Dinda, Biswanath; Das, Niranjan; Dinda, Subhajit; Dinda, Manikarna; SilSarma, Indrajit

    2015-12-24

    was reported. The detailed study on mechanism of action of isolates and extracts and their clinical study are needed for their use in modern medicine. More attention should be paid to Sida acuta, Sida cordifolia, Sida spinosa, Sida rhombifolia and Sida veronicaefolia in the domain of diarrhea, dysentery, gastrointestinal and urinary infections, skin ailments, asthma, bronchitis and other respiratory problems, malaria, childbirth and miscarriage problems, cardiac and neural problems, weight loss aid, and rheumatic and other inflammations, etc. Furthermore, detailed study on quality and safety assurance data on available ethnopharmacological preparations is needed for their commercial exploitation in local and global markets. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

  8. HIV risks and needs related to the Sustainable Development Goals among female sex workers who were commercially sexually exploited as children in Lesotho.

    Science.gov (United States)

    Grosso, Ashley; Busch, Shianne; Mothopeng, Tampose; Sweitzer, Stephanie; Nkonyana, John; Mpooa, Nkomile; Taruberekera, Noah; Baral, Stefan

    2018-02-01

    Sustainable Development Goals (SDGs) about gender equality; decent work; and peace, justice, and strong institutions include a focus on eradicating trafficking and sexual exploitation of and violence against women and children. In Lesotho, 86% of women have experienced gender-based violence. In addition, overall HIV prevalence is among the highest globally, and higher among adolescent girls than boys. Moreover, nearly three quarters of female sex workers (FSW) are estimated to be living with HIV in Lesotho. In this context, sexually exploited children may be particularly vulnerable to violence and HIV acquisition risks. This study's objective is to examine the prevalence and correlates of experiencing sexual exploitation as a child among FSW in Lesotho. FSW (≥18 years) recruited through respondent-driven sampling in Maseru and Maputsoe from February to September 2014 completed HIV and syphilis testing and an interviewer-administered survey, including a question about the age at which they started providing sex for money. This study examined correlates of experiencing sexual exploitation as a child (trouble with police (aOR: 3.18, 95% CI: 1.50 to 6.75, p = 0.003). Risk determinants for HIV and violence among sexually exploited children can be studied retrospectively through research with adult FSW. Further research working directly with sexually exploited children will improve understanding of their needs. Preventing commercial sexual exploitation of children and addressing the social and healthcare needs of those who are exploited are necessary to fully achieve SDGs 5, 8 and 16 and an AIDS-Free Generation. © 2018 The Authors. Journal of the International AIDS Society published by John Wiley & sons Ltd on behalf of the International AIDS Society.

  9. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  10. Internet-facilitated commercial sexual exploitation of children: findings from a nationally representative sample of law enforcement agencies in the United States.

    Science.gov (United States)

    Mitchell, Kimberly J; Jones, Lisa M; Finkelhor, David; Wolak, Janis

    2011-03-01

    This article explores the variety of ways in which the Internet is used to facilitate the commercial sexual exploitation of children (CSEC) and provides national incidence estimates for the number of arrests involving such technology-facilitated crimes in 2006. The National Juvenile Online Victimization Study is a nationally representative longitudinal study of more than 2,500 local, county, state, and federal law enforcement agencies across the United States. The current article utilizes Wave 2 data, which surveyed arrests in 2006 for Internet-related sex crimes against minors. Detailed data were collected via telephone interviews with investigators about 1,051 individual arrest cases. Findings show that an estimated 569 arrests for Internet-facilitated commercial sexual exploitation of children (IF-CSEC) occurred in the United States in 2006. Offenders in IF-CSEC cases fell into two main categories: (1) those who used the Internet to purchase or sell access to identified children for sexual purposes including child pornography (CP) production (36% of cases), and (2) those who used the Internet to purchase or sell CP images they possessed but did not produce (64% of cases). Offenders attempting to profit from child sexual exploitation were more likely than those who were purchasing to have (a) prior arrests for sexual and nonsexual offenses, (b) a history of violence, (c) produced CP, (d) joined forces with other offenders, and (e) involved female offenders. Although the number of arrests for IF-CSEC crimes is relatively small, the victims of these crimes are a high-risk subgroup of youth, and the offenders who try to profit from these crimes are particularly concerning from a child welfare perspective.

  11. Long-term Trends in Coral Reef Fish Yields and Exploitation Rates of Commercial Species from Coastal Kenya

    OpenAIRE

    Kaunda-Arara, B.; Rose, G.A.; Muchiri, M.S.; Kaka, R.

    2003-01-01

    Analysis of long-term (1978–2001) marine fisheries data showed that Kenyan coralreefs produced an estimated 2–4 metric t/km2/year of demersal fish. A rapid overall decline in landings occurred during the 1990s. Yields (t/km2/year) showed bimodal peaks in 1982 (2.98) and 1991 (2.90). The average total landings dropped by 55% during the last decade following peak landings in 1982. Landings of the commercially important families (e.g., Siganidae, Lethrinidae, Lutjanidae and Serran...

  12. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  13. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

  14. Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

    NARCIS (Netherlands)

    Dutta, Satadal

    2017-01-01

    Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

  15. High-voltage CMOS detectors

    International Nuclear Information System (INIS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-01-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

  16. High-voltage CMOS detectors

    Energy Technology Data Exchange (ETDEWEB)

    Ehrler, F., E-mail: felix.ehrler@student.kit.edu; Blanco, R.; Leys, R.; Perić, I.

    2016-07-11

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

  17. A 0.18μm CMOS low-power radiation sensor for UWB wireless transmission

    International Nuclear Information System (INIS)

    Crepaldi, M; Demarchi, D; Gabrielli, A; Khan, A; Pikhay, E; Roizin, Y; Villani, G; Zhang, Z

    2012-01-01

    The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype of the circuit has recently been simulated, fabricated and tested exploiting a commercial 180 nm, 4 metal CMOS technology. Some simulation results are presented along with a measurement of the readout circuit response to an input voltage swing. Given the small estimated area of the complete chip prototype, that is less than 1 mm 2 , the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements or radiation level in High-Energy Physics experiments.

  18. Radiation-hardened bulk CMOS technology

    International Nuclear Information System (INIS)

    Dawes, W.R. Jr.; Habing, D.H.

    1979-01-01

    The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

  19. Disclosing Sex Trading Histories to Providers: Barriers and Facilitators to Navigation of Social Services Among Women Impacted by Commercial Sexual Exploitation.

    Science.gov (United States)

    Gerassi, Lara; Edmond, Tonya E; Fabbre, Vanessa; Howard, Abby; Nichols, Andrea J

    2017-12-01

    Sex trafficking and commercial sexual exploitation (CSE) can lead to devastating health and mental health consequences for women, such as elevated rates of substance use, trauma, posttraumatic stress disorder, depression, sexually transmitted infections (STIs), and HIV. Consequently, engagement with services that address addiction, mental health, and housing, and provide general advocacy is critically important to women's increased safety, stabilization, and quality of life. The purpose of this study is to identify perceived barriers and facilitators to service access and engagement with social services among women involved in CSE. Drawing from a larger grounded theory study that partnered with an anti-trafficking coalition and a substance use treatment center for women, in-depth, semistructured interviews were conducted with 30 adult women who traded sex as adults and 20 service providers who come into contact with this population. Women engaging in services were sampled through maximum variation sampling ( n = 24) and women not engaged with services ( n = 6) were recruited through snowball sampling. Providers were recruited through purposive sampling through the coalition ( n = 10) and nominations sampling ( n = 10). Open and focused coding were conducted. Multiple enhancements to methodological and analytic rigor were taken, including collaboration with multiple key stakeholders, use of nonstigmatizing language, self-reflexivity processes, analytic memo-writing, and member checking. Findings suggest that women experienced judgment when disclosing sex trading in social service intakes, and individual and group sessions from providers and other women in the groups. Although some women saw disclosure as helpful in addressing the complex feelings stemming from sex trading, as well as the desire to help or relate to other women in similar situations, they also identified risk of harm and multiple barriers to disclosing during intake meetings and individual sessions

  20. Ion traps fabricated in a CMOS foundry

    Energy Technology Data Exchange (ETDEWEB)

    Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  1. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  2. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  3. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  4. Toward CMOS image sensor based glucose monitoring.

    Science.gov (United States)

    Devadhasan, Jasmine Pramila; Kim, Sanghyo

    2012-09-07

    Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

  5. Depleted CMOS pixels for LHC proton–proton experiments

    International Nuclear Information System (INIS)

    Wermes, N.

    2016-01-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  6. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  7. The CMOS Integration of a Power Inverter

    OpenAIRE

    Mannarino, Eric Francis

    2016-01-01

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this proce...

  8. All-CMOS night vision viewer with integrated microdisplay

    Science.gov (United States)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  9. CMOS dot matrix microdisplay

    Science.gov (United States)

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  10. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  11. CMOS sensors for atmospheric imaging

    Science.gov (United States)

    Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

    2017-09-01

    Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

  12. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  13. CMOS/SOS processing

    Science.gov (United States)

    Ramondetta, P.

    1980-01-01

    Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

  14. CMOS MEMS capacitive absolute pressure sensor

    International Nuclear Information System (INIS)

    Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

    2013-01-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

  15. Redefining Exploitation

    DEFF Research Database (Denmark)

    Agarwala, Rina

    2016-01-01

    This article examines how self-employed workers are organizing in the garments and waste collection industries in India. Although the question of who is profiting from self-employed workers’ labor is complex, the cases outlined in this paper highlight telling instances of how some self......-employed workers are organizing as workers. They are fighting labor exploitation by redefining the concept to include additional exploitation axes (from the state and middle class) and forms (including sexual). In doing so, they are redefining potential solutions, including identities and material benefits, to fit...... their unique needs. By expanding the category of “workers” beyond those defined by a narrow focus on a standard employer-employee relationship, these movements are also fighting exclusion from earlier labor protections by increasing the number of entitled beneficiaries. These struggles provide an important...

  16. Results of cost estimates for the exploitation of the Natuna gas field in Indonesia using the HTR: A new momentum for commercialization

    International Nuclear Information System (INIS)

    Barnert, H.

    1997-01-01

    The results of a simplified method for cost estimations are presented. The main result is: There exists a potential of economical competitiveness for the exploitation of the gas of the Natuna Gas Field in Indonesia. The potential consists in the production of Energy Alcohol from the gas of the Natuna Gas Field, making use of nuclear energy in the form of high temperature heat and electricity from the High Temperature reactor, HTR. The reason is that Energy Alcohol is a readily marketable product as a substitute for gasoline and diesel, with their relatively high market values. This is not so for methane, because of its lower market value, being used mainly in the heat market only. In the conversion process some - or a little more - of the carbondioxide CO 2 , the main constituent of the gas of the Natuna Gas Field, is used; the competitiveness of the product decreases with the increasing consumption of CO 2

  17. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  18. A wideband Noise-Canceling CMOS LNA exploiting a transformer

    NARCIS (Netherlands)

    Blaakmeer, S.C.; Klumperink, Eric A.M.; Leenaerts, Domine M.W.; Nauta, Bram

    2006-01-01

    Abstract — A broadband LNA incorporating single-ended to differential conversion, has been successfully implemented using a noise-canceling technique and a single on-chip transformer. The LNA achieves a high voltage gain of 19dB, a wideband input match (2.5–4.0 GHz), and a Noise Figure of 4–5.4 dB,

  19. A wideband Noise-Canceling CMOS LNA exploiting a transformer

    NARCIS (Netherlands)

    Blaakmeer, S.C.; Klumperink, Eric A.M.; Leenaerts, Domine M.W.; Nauta, Bram

    2006-01-01

    A broadband LNA incorporating single-ended to differential conversion, has been successfully implemented using a noise-canceling technique and a single on-chip transformer. The LNA achieves a high voltage gain of 19dB, a wideband input match (2.5–4.0 GHz), and a Noise Figure of 4–5.4 dB, while

  20. Amplifiers Exploiting Thermal Noise Canceling: A Review

    OpenAIRE

    Klumperink, Eric A.M.; Bruccoleri, Federico; Stroet, Peter; Nauta, Bram

    2004-01-01

    Wide-band LNAs suffer from a fundamental trade-off between noise figure NF and source impedance matching, which limits NF to values typically above 3dB. Recently, a feed-forward noise canceling technique has been proposed to break this trade-off. This paper reviews the principle of the technique and its key properties. Although the technique has been applied to wideband CMOS LNAs, it can just as well be implemented exploiting transconductance elements realized with oth...

  1. Study of CMOS Image Sensors for the Alignment System of the CMS Experiment

    Energy Technology Data Exchange (ETDEWEB)

    Virto, A. L.; Vila, I.; Rodrigo, T.; Matorras, F.; Figueroa, C. F.; Calvo, E.; Calderon, A.; Arce, P.; Oller, J. C.; Molinero, A.; Josa, M. I.; Fuentes, J.; Ferrando, A.; Fernandez, M. G.; Barcala, J. M.

    2002-07-01

    We report on an in-depth study made on commercial CMOS image sensors in order to determine their feasibility for beam light position detection in the CMS multipoint alignment scheme. (Author) 21 refs.

  2. Morphological and genetic evidence for multiple evolutionary distinct lineages in the endangered and commercially exploited red lined torpedo barbs endemic to the Western Ghats of India.

    Science.gov (United States)

    John, Lijo; Philip, Siby; Dahanukar, Neelesh; Anvar Ali, Palakkaparambil Hamsa; Tharian, Josin; Raghavan, Rajeev; Antunes, Agostinho

    2013-01-01

    Red lined torpedo barbs (RLTBS) (Cyprinidae: Puntius) endemic to the Western Ghats Hotspot of India, are popular and highly priced freshwater aquarium fishes. Two decades of indiscriminate exploitation for the pet trade, restricted range, fragmented populations and continuing decline in quality of habitats has resulted in their 'Endangered' listing. Here, we tested whether the isolated RLTB populations demonstrated considerable variation qualifying to be considered as distinct conservation targets. Multivariate morphometric analysis using 24 size-adjusted characters delineated all allopatric populations. Similarly, the species-tree highlighted a phylogeny with 12 distinct RLTB lineages corresponding to each of the different riverine populations. However, coalescence-based methods using mitochondrial DNA markers identified only eight evolutionarily distinct lineages. Divergence time analysis points to recent separation of the populations, owing to the geographical isolation, more than 5 million years ago, after the lineages were split into two ancestral stocks in the Paleocene, on north and south of a major geographical gap in the Western Ghats. Our results revealing the existence of eight evolutionarily distinct RLTB lineages calls for the re-determination of conservation targets for these cryptic and endangered taxa.

  3. Morphological and genetic evidence for multiple evolutionary distinct lineages in the endangered and commercially exploited red lined torpedo barbs endemic to the Western Ghats of India.

    Directory of Open Access Journals (Sweden)

    Lijo John

    Full Text Available Red lined torpedo barbs (RLTBS (Cyprinidae: Puntius endemic to the Western Ghats Hotspot of India, are popular and highly priced freshwater aquarium fishes. Two decades of indiscriminate exploitation for the pet trade, restricted range, fragmented populations and continuing decline in quality of habitats has resulted in their 'Endangered' listing. Here, we tested whether the isolated RLTB populations demonstrated considerable variation qualifying to be considered as distinct conservation targets. Multivariate morphometric analysis using 24 size-adjusted characters delineated all allopatric populations. Similarly, the species-tree highlighted a phylogeny with 12 distinct RLTB lineages corresponding to each of the different riverine populations. However, coalescence-based methods using mitochondrial DNA markers identified only eight evolutionarily distinct lineages. Divergence time analysis points to recent separation of the populations, owing to the geographical isolation, more than 5 million years ago, after the lineages were split into two ancestral stocks in the Paleocene, on north and south of a major geographical gap in the Western Ghats. Our results revealing the existence of eight evolutionarily distinct RLTB lineages calls for the re-determination of conservation targets for these cryptic and endangered taxa.

  4. The review of radiation effects of γ total dose in CMOS circuits

    International Nuclear Information System (INIS)

    Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

    1992-01-01

    Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

  5. Os agentes sociais da rede de proteção e atendimento no enfrentamento da exploração sexual comercial Social agents from protection networks in fighting commercial sexual exploitation

    Directory of Open Access Journals (Sweden)

    Maria de Fátima Pereira Alberto

    2012-01-01

    Full Text Available Neste artigo, apresentam-se dados de pesquisa sobre a percepção dos Agentes Sociais que atuam no enfrentamento da exploração sexual comercial de crianças e adolescentes. As entidades caracterizam-se por Organizações Governamentais, Organizações Não-Governamentais, Sistema de Justiça e Instâncias de Direitos. Compõem uma Rede de 15 instituições e foram entrevistados 31 Agentes Sociais de 12 delas. Utilizou-se um questionário composto de questões abertas e fechadas sobre: Conhecimento do Sistema de Proteção; Percepção da ESCCA; Formas de Enfrentamento da ESCCA; Procedimentos e Medidas em casos de suspeitas, identificações, denúncias e notificações. A maioria dos Agentes Sociais tem conhecimento do papel da instituição, embora alguns desconheçam parte da Legislação e as formas de se efetivar na prática o papel daquelas e a articulação interinstitucional.This article shows the data collected in a research regarding the perception of Social Agents who act in fighting children and adolescents' commercial sexual exploitation. The networking is composed by Governmental Organizations, Non-governmental Organizations, Justice System and Human Rights entities. They compose a network of 15 institutions, and 31 Social Agents who belonged to 12 of them were interviewed. It was used a questionnaire composed by open and closed questions about protection systems knowledge; perception of children and adolescents' commercial sexual exploitation; forms of fighting children and adolescents' commercial sexual exploitation; procedures and actions in case of suspicion, identification, denunciation and notification. Most of the Social Agents who make part of the network know the role of the institution where they work, although some of them do not know part of the Legislation which deals with this problematic and they also do not know the forms to effectuate in practice the purpose of the Legislation and its inter

  6. Genetic Variation in the ND1 Gene and D-loop in Protected and Commercially Exploited European Cisco (Coregonus albula L.) Populations.

    Science.gov (United States)

    Kirczuk, Lucyna; Rymaszewska, Anna; Pilecka-Rapacz, Malgorzata; Domagala, Jozef

    The European cisco (Coregonus albula L.) is a species with high environmental requirements. The deterioration of environmental conditions in recent decades has decreased its distribution. Currently the species is conserved by stocking, and the few existing natural populations are at risk of extinction. Therefore, contemporary studies involve not only reporting phenotypic parameters, but also determining the genetic structure of the population. This is an important aspect monitored in the C. albula population, which provides information valuable for proper fishing economy. This study included valuable populations from lakes located in Drawa National Park (DNP) and Wigry National Park (WNP), as well as lakes used for commercial fishing. In order to molecularly characterize the European cisco, the control region and NDl gene were sequenced from 48 individuals from 9 populations from lakes throughout northern Poland. Analysis revealed that populations from two park lakes (Marta, Ostrowieckie) are unique. This was also the case for some sequences originating from Lake Wigry. The mean value of genetic diversity was 0.2% within each region and 0.1-0.3% between the investigated regions. The obtained results demonstrated the necessity to strengthen and protect natural populations of the European cisco, which constitute a valuable element of the European ichthyofauna.

  7. Application of CMOS Technology to Silicon Photomultiplier Sensors

    Science.gov (United States)

    D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

    2017-01-01

    We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

  8. Structured Analog CMOS Design

    CERN Document Server

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  9. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  10. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  11. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  12. A CMOS Morlet Wavelet Generator

    Directory of Open Access Journals (Sweden)

    A. I. Bautista-Castillo

    2017-04-01

    Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

  13. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  14. Development of radiation hard CMOS active pixel sensors for HL-LHC

    International Nuclear Information System (INIS)

    Pernegger, Heinz

    2016-01-01

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  15. Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

    Science.gov (United States)

    Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

    2017-12-01

    With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

  16. An improved standard total dose test for CMOS space electronics

    International Nuclear Information System (INIS)

    Fleetwood, D.M.; Winokur, P.S.; Riewe, L.C.; Pease, R.L.

    1989-01-01

    The postirradiation response of hardened and commercial CMOS devices is investigated as a function of total dose, dose rate, and annealing time and temperature. Cobalt-60 irradiation at ≅ 200 rad(SiO 2 )/s followed by a 1-week 100 degrees C biased anneal and testing is shown to be an effective screen of hardened devices for space use. However, a similar screen and single-point test performed after Co-60 irradiation and elevated temperature anneal cannot be generally defined for commercial devices. In the absence of detailed knowledge about device and circuit radiation response, a two-point standard test is proposed to ensure space surviability of CMOS circuits: a Co-60 irradiation and test to screen against oxide-trapped charge related failures, and an additional rebound test to screen against interface-trap related failures. Testing implications for bipolar technologies are also discussed

  17. Large area CMOS image sensors

    International Nuclear Information System (INIS)

    Turchetta, R; Guerrini, N; Sedgwick, I

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  18. Large Format CMOS-based Detectors for Diffraction Studies

    Science.gov (United States)

    Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

    2013-03-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  19. Large Format CMOS-based Detectors for Diffraction Studies

    International Nuclear Information System (INIS)

    Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

    2013-01-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  20. Absorbed dose by a CMOS in radiotherapy

    International Nuclear Information System (INIS)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

    2011-10-01

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  1. The CMOS integration of a power inverter

    Science.gov (United States)

    Mannarino, Eric Francis

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this process using two topologies. The first is a cell-based switched-capacitor topology first presented by Ke Zou. The second is a novel topology that explores the advantage of using a bused input-output system, as in digital electronics. Simulations run on both topologies confirm the high-efficiency demonstrated in Zou’s process as well as the advantage the bus-based system has in output voltage levels.

  2. Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

    Science.gov (United States)

    Seco, Joao; Depauw, Nicolas

    2011-02-01

    Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The

  3. CMOS Integrated Carbon Nanotube Sensor

    International Nuclear Information System (INIS)

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-01-01

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  4. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  5. A Multipurpose CMOS Platform for Nanosensing.

    Science.gov (United States)

    Bonanno, Alberto; Sanginario, Alessandro; Marasso, Simone L; Miccoli, Beatrice; Bejtka, Katarzyna; Benetto, Simone; Demarchi, Danilo

    2016-11-30

    This paper presents a customizable sensing system based on functionalized nanowires (NWs) assembled onto complementary metal oxide semiconductor (CMOS) technology. The Micro-for-Nano (M4N) chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP) generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC) that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW-229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  6. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  7. Gamma and Proton-Induced Dark Current Degradation of 5T CMOS Pinned Photodiode 0.18 mu{m} CMOS Image Sensors

    Science.gov (United States)

    Martin, E.; Nuns, T.; David, J.-P.; Gilard, O.; Vaillant, J.; Fereyre, P.; Prevost, V.; Boutillier, M.

    2014-02-01

    The radiation tolerance of a 0.18 μm technology CMOS commercial image sensor has been evaluated with Co60 and proton irradiations. The effects of protons on the hot pixels and dynamic bias and duty cycle conditions during gamma irradiations are studied.

  8. A passive CMOS pixel sensor for the high luminosity LHC

    Energy Technology Data Exchange (ETDEWEB)

    Daas, Michael; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Muenchen (Germany)

    2016-07-01

    The high luminosity upgrade for the Large Hadron Collider at CERN requires a new inner tracking detector for the ATLAS experiment. About 200 m{sup 2} of silicon detectors are needed demanding new, low cost hybridization- and sensor technologies. One promising approach is to use commercial CMOS technologies to produce the passive sensor for a hybrid pixel detector design. In this talk a fully functional prototype of a 300 μm thick, backside biased CMOS pixel sensor in 150 nm LFoundry technology is presented. The sensor is bump bonded to the ATLAS FE-I4 with AC and DC coupled pixels. Results like leakage current, noise performance, and charge collection efficiency are presented and compared to the actual ATLAS pixel sensor design.

  9. A back-illuminated megapixel CMOS image sensor

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

    2005-01-01

    In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

  10. The Ethics of Exploitation

    Directory of Open Access Journals (Sweden)

    Paul McLaughlin

    2008-11-01

    Full Text Available Philosophical inquiry into exploitation has two major deficiencies to date: it assumes that exploitation is wrong by definition; and it pays too much attention to the Marxian account of exploitation. Two senses of exploitation should be distinguished: the ‘moral’ or pejorative sense and the ‘non-moral’ or ‘non-prejudicial’ sense. By demonstrating the conceptual inadequacy of exploitation as defined in the first sense, and by defining exploitation adequately in the latter sense, we seek to demonstrate the moral complexity of exploitation. We contend, moreover, that moral evaluation of exploitation is only possible once we abandon a strictly Marxian framework and attempt, in the long run, to develop an integral ethic along Godwinian lines.

  11. Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

    Science.gov (United States)

    Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

    2017-11-26

    Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

  12. Neutron absorbed dose in a pacemaker CMOS

    International Nuclear Information System (INIS)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

    2012-01-01

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

  13. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  14. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  15. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  16. Recent progress in the development of 3D deep n-well CMOS MAPS

    International Nuclear Information System (INIS)

    Traversi, G; Manghisoni, M; Re, V; Gaioni, L; Manazza, A; Ratti, L; Zucca, S

    2012-01-01

    In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

  17. CMOS Analog IC Design: Fundamentals

    OpenAIRE

    Bruun, Erik

    2018-01-01

    This book is intended for use as the main textbook for an introductory course in CMOS analog integrated circuit design. It is aimed at electronics engineering students who have followed basic courses in mathematics, physics, circuit theory, electronics and signal processing. It takes the students directly from a basic level to a level where they can start working on simple analog IC design projects or continue their studies using more advanced textbooks in the field. A distinct feature of thi...

  18. Electrothermal frequency references in standard CMOS

    CERN Document Server

    Kashmiri, S Mahdi

    2013-01-01

    This book describes an alternative method of accurate on-chip frequency generation in standard CMOS IC processes. This method exploits the thermal-diffusivity of silicon, the rate at which heat diffuses through a silicon substrate.  This is the first book describing thermal-diffusivity-based frequency references, including the complete theoretical methodology supported by practical realizations that prove the feasibility of the method.  Coverage also includes several circuit and system-level solutions for the analog electronic circuit design challenges faced.   ·         Surveys the state-of-the-art in all-silicon frequency references; ·         Examines the thermal properties of silicon as a solution for the challenge of on-chip accurate frequency generation; ·         Uses simplified modeling approaches that allow an electronics engineer easily to simulate the electrothermal elements; ·         Follows a top-down methodology in circuit design, in which system-level des...

  19. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    Science.gov (United States)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  20. CMOS optimization for radiation hardness

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Fossum, J.G.

    1975-01-01

    Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

  1. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  2. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  3. Radiation evaluation of commercial ferroelectric nonvolatile memories

    International Nuclear Information System (INIS)

    Benedetto, J.M.; DeLancey, W.M.; Oldham, T.R.; McGarrity, J.M.; Tipton, C.W.; Brassington, M.; Fisch, D.E.

    1991-01-01

    This paper reports on ferroelectric (FE) on complementary metal-oxide semiconductor (CMOS) 4-kbit nonvolatile memories, 8-bit octal latches (with and without FE), and process control test chips that were used to establish a baseline characterization of the radiation response of CMOS/FE integrated devices and to determine whether the additional FE processing caused significant degradation to the baseline CMOS process. Functional failure of all 4-kbit memories and octal latches occurred at total doses of between 2 and 4 krad(Si), most likely due to field- oxide effects in the underlying CMOS. No significant difference was observed between the radiation responses of devices with and without the FE film in this commercial process

  4. Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

    NARCIS (Netherlands)

    Tilmans, H.A.C.; Ziad, H.; Jansen, Henricus V.; Di Monaco, O.; Jourdain, A.; De Raedt, W.; Rottenberg, X.; De Backer, E.; Decoussernaeker, A.; Baert, K.

    2001-01-01

    Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as

  5. Radiation response of two Harris semiconductor radiation hardened 1k CMOS RAMs

    International Nuclear Information System (INIS)

    Abare, W.E.; Huffman, D.D.; Moffett, G.E.

    1982-01-01

    This paper describes the testing of two types 1K CMOS static RAMs in various transient and steady state ionizing radiation environments. Type HM 6551R (256x4 bits) and type HM 6508R (1024x1 bit) RAMs were evaluated. The RAMs are radiation hardened versions of Harris' commercial RAMs. A brief description of the radiation hardened process is presented

  6. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    International Nuclear Information System (INIS)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

    2012-01-01

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

  7. JPL CMOS Active Pixel Sensor Technology

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

  8. Exploit Kit traffic analysis

    OpenAIRE

    Καπίρης, Σταμάτης; Kapiris, Stamatis

    2017-01-01

    Exploit kits have become one of the most widespread and destructive threat that Internet users face on a daily basis. Since the first actor, which has been categorized as exploit kit, namely MPack, appeared in 2006, we have seen a new era on exploit kit variants compromising popular websites, infecting hosts and delivering destructive malware, following an exponentially evolvement to date. With the growing threat landscape, large enterprises to domestic networks, have starte...

  9. Exploitability Assessment with TEASER

    Science.gov (United States)

    2017-05-01

    for architectural neutral taint analysis on top of LLVM and QEMU. POC Proof of Concept : Demonstration of an exploit on a program . vii RCE Remote Code...bug with a Proof of Concept (POC), or input to a program demonstrating the ability to use a bug to exploit the application, to demonstrate the...often leads to either computationally difficult constraint solving problems or taint explosion. Given the computational difficulty of exploit

  10. Anthropology of sexual exploitation

    Directory of Open Access Journals (Sweden)

    Lalić Velibor

    2009-01-01

    Full Text Available In this paper, the authors observe sexual exploitation from an anthropological perspective. They analyze the rational, ethical, emotional and mythological dimensions of human sexuality. Consequently, after setting the phenomenon in a social and historical context, sexual exploitation is closely observed in the contemporary age. Based on thoughts of relevant thinkers, they make the conclusion that the elimination of sexual exploitation is not an utterly legal issue, but political and economical issues as well. Namely, legal norms are not sufficient to overcome sexual exploitation, but, political and economical relationships in contemporary societies, which will be based on sincere equal opportunities must be established.

  11. Hybrid CMOS/Molecular Integrated Circuits

    Science.gov (United States)

    Stan, M. R.; Rose, G. S.; Ziegler, M. M.

    CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

  12. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  13. CMOS foveal image sensor chip

    Science.gov (United States)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  14. Exploitation and disadvantage

    NARCIS (Netherlands)

    Ferguson, B.

    2016-01-01

    According to some accounts of exploitation, most notably Ruth Sample's (2003) degradation-based account and Robert Goodin's (1987) vulnerability-based account, exploitation occurs when an advantaged party fails to constrain their advantage in light of another's disadvantage, regardless of the cause

  15. EXPLOITATION OF GRANITE BOULDER

    Directory of Open Access Journals (Sweden)

    Ivan Cotman

    1994-12-01

    Full Text Available The processes of forming, petrography, features, properties and exploitation of granite boulders are described. The directional drilling and black powder blasting is the succesful method in exploitation of granite boulders (boulder technology (the paper is published in Croatian.

  16. TCAD simulations of High-Voltage-CMOS Pixel structures for the CLIC vertex detector

    CERN Document Server

    Buckland, Matthew Daniel

    2016-01-01

    The requirements for precision physics and the experimental conditions at CLIC result in stringent constraints for the vertex detector. Capacitively coupled active pixel sensors with 25 μm pitch implemented in a commercial 180 nm High-Voltage CMOS (HV-CMOS) process are currently under study as a candidate technology for the CLIC vertex detector. Laboratory calibration measurements and beam tests with prototypes are complemented by detailed TCAD and electronic circuit simulations, aiming for a comprehensive understanding of the signal formation in the HV-CMOS sensors and subsequent readout stages. In this note 2D and 3D TCAD simulation results of the prototype sensor, the Capacitively Coupled Pixel Detector version three (CCPDv3), will be presented. These include the electric field distribution, leakage current, well capacitance, transient response to minimum ionising particles and charge-collection.

  17. Competing Discourses about Youth Sexual Exploitation in Canadian News Media.

    Science.gov (United States)

    Saewyc, Elizabeth M; Miller, Bonnie B; Rivers, Robert; Matthews, Jennifer; Hilario, Carla; Hirakata, Pam

    2013-10-01

    Media holds the power to create, maintain, or break down stigmatizing attitudes, which affect policies, funding, and services. To understand how Canadian news media depicts the commercial sexual exploitation of children and youth, we examined 835 Canadian newspaper articles from 1989-2008 using a mixed methods critical discourse analysis approach, comparing representations to existing research about sexually exploited youth. Despite research evidence that equal rates of boys and girls experience exploitation, Canadian news media depicted exploited youth predominantly as heterosexual girls, and described them alternately as victims or workers in a trade, often both in the same story. News media mentioned exploiters far less often than victims, and portrayed them almost exclusively as male, most often called 'customers' or 'consumers,' and occasionally 'predators'; in contrast, research has documented the majority of sexually exploited boys report female exploiters. Few news stories over the past two decades portrayed the diversity of victims, perpetrators, and venues of exploitation reported in research. The focus on victims but not exploiters helps perpetuate stereotypes of sexual exploitation as business or a 'victimless crime,' maintains the status quo, and blurs responsibility for protecting youth under the UN Convention on the Rights of the Child. Health care providers and researchers can be advocates for accuracy in media coverage about sexual exploitation; news reporters and editors should focus on exploiters more than victims, draw on existing research evidence to avoid perpetuating stereotypes, and use accurate terms, such as commercial sexual exploitation, rather than terms related to business or trade.

  18. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  19. Poverty-Exploitation-Alienation.

    Science.gov (United States)

    Bronfenbrenner, Martin

    1980-01-01

    Illustrates how knowledge derived from the discipline of economics can be used to help shed light on social problems such as poverty, exploitation, and alienation, and can help decision makers form policy to minimize these and similar problems. (DB)

  20. Exploiting VM/XA

    International Nuclear Information System (INIS)

    Boeheim, C.

    1990-03-01

    The Stanford Linear Accelerator Center has recently completed a conversion to IBM's VM/XA SP Release 2 operating system. The primary physics application had been constrained by the previous 16 megabyte memory limit. Work is underway to enable this application to exploit the new features of VM/XA. This paper presents a brief tutorial on how to convert an application to exploit VM/XA and discusses some of the SLAC experiences in doing so. 13 figs

  1. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  2. Latch-up in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Estreich, D.B.; Dutton, R.W.

    1978-04-01

    An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

  3. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  4. A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.

    Science.gov (United States)

    Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

    2012-07-01

    As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.

  5. Variationen und ihre Kompensation in CMOS Digitalschaltungen

    OpenAIRE

    Baumann, Thomas

    2010-01-01

    Variationen bei der Herstellung und während des Betriebs von CMOS Schaltungen beeinflussen deren Geschwindigkeit und erschweren die Verifikation der in der Spezifikation zugesicherten Eigenschaften. In dieser Arbeit wird eine abstraktionsebenenübergreifende Vorgehensweise zur Abschätzung des Einflusses von Prozess- und betriebsbedingten Umgebungsvariationen auf die Geschwindigkeit einer Schaltung vorgestellt. Neben Untersuchungen der Laufzeitsensitivität in low-power CMOS Technologien von...

  6. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    . The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...... of 2.5 pF. (C) 2003 Elsevier Science B.V. All rights reserved....

  7. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

  8. Modeling methodology for a CMOS-MEMS electrostatic comb

    Science.gov (United States)

    Iyer, Sitaraman V.; Lakdawala, Hasnain; Mukherjee, Tamal; Fedder, Gary K.

    2002-04-01

    A methodology for combined modeling of capacitance and force 9in a multi-layer electrostatic comb is demonstrated in this paper. Conformal mapping-based analytical methods are limited to 2D symmetric cross-sections and cannot account for charge concentration effects at corners. Vertex capacitance can be more than 30% of the total capacitance in a single-layer 2 micrometers thick comb with 10 micrometers overlap. Furthermore, analytical equations are strictly valid only for perfectly symmetrical finger positions. Fringing and corner effects are likely to be more significant in a multi- layered CMOS-MEMS comb because of the presence of more edges and vertices. Vertical curling of CMOS-MEMS comb fingers may also lead to reduced capacitance and vertical forces. Gyroscopes are particularly sensitive to such undesirable forces, which therefore, need to be well-quantified. In order to address the above issues, a hybrid approach of superposing linear regression models over a set of core analytical models is implemented. Design of experiments is used to obtain data for capacitance and force using a commercial 3D boundary-element solver. Since accurate force values require significantly higher mesh refinement than accurate capacitance, we use numerical derivatives of capacitance values to compute the forces. The model is formulated such that the capacitance and force models use the same regression coefficients. The comb model thus obtained, fits the numerical capacitance data to within +/- 3% and force to within +/- 10%. The model is experimentally verified by measuring capacitance change in a specially designed test structure. The capacitance model matches measurements to within 10%. The comb model is implemented in an Analog Hardware Description Language (ADHL) for use in behavioral simulation of manufacturing variations in a CMOS-MEMS gyroscope.

  9. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal; Elshurafa, Amro M.; Mohammad, Mohammad Ali; Nelson-Fitzpatrick, Nathan E.; Evoy, S.

    2012-01-01

    . The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly

  10. Status and perspectives of deep N-well 130 nm CMOS MAPS

    International Nuclear Information System (INIS)

    Re, Valerio

    2009-01-01

    Deep N-Well (DNW) MAPS were developed in two different flavors to approach the specifications of vertex detectors in dissimilar experimental environments such as the Super B-Factory and the ILC. The first generation of MAPS with on-pixel data sparsification and time stamping capabilities is now available and was tested in a beam for the first time in September 2008. These devices are fabricated in a commercial 130 nm CMOS process, and the triple well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. Because of the high integration density of such a technology, complex digital functions can be included in each pixel, implementing a sparsified readout architecture of the pixel matrix with time stamping. This paper reviews the features of the ''ILC class'' and ''SuperB class'' MAPS devices, discussing their different design in terms of pixel pitch, analog signal processing, and digital readout architecture. For SuperB, a data-driven, continuously operating readout scheme was adopted along with a macropixel matrix arrangement, whereas for the ILC the matrix is read out in the long intertrain period. In both versions, the address of hit pixels is transmitted off-chip along with the time stamp. The experimental performance of the chips provides an assessment of the Deep N-Well MAPS potential in view of future applications. The paper also discusses the way forward in the development of these devices, outlining the issues that have to be tackled to design full size Deep N-Well MAPS for actual experiments. These sensors could take advantage from technological advances in microelectronic industry, such as vertical integration. The impact of these new technologies on the design and performance of DNW pixel sensors could be large, with potential benefit for various device features, from the charge collection properties to the digital readout architecture.

  11. Exploitation in International Paid Surrogacy Arrangements

    Science.gov (United States)

    Wilkinson, Stephen

    2015-01-01

    Abstract Many critics have suggested that international paid surrogacy is exploitative. Taking such concerns as its starting point, this article asks: (1) how defensible is the claim that international paid surrogacy is exploitative and what could be done to make it less exploitative? (2) In the light of the answer to (1), how strong is the case for prohibiting it? Exploitation could in principle be dealt with by improving surrogates' pay and conditions. However, doing so may exacerbate problems with consent. Foremost amongst these is the argument that surrogates from economically disadvantaged countries cannot validly consent because their background circumstances are coercive. Several versions of this argument are examined and I conclude that at least one has some merit. The article's overall conclusion is that while ethically there is something to be concerned about, paid surrogacy is in no worse a position than many other exploitative commercial transactions which take place against a backdrop of global inequality and constrained options, such as poorly‐paid and dangerous construction work. Hence, there is little reason to single surrogacy out for special condemnation. On a policy level, the case for prohibiting international commercial surrogacy is weak, despite legitimate concerns about consent and background poverty. PMID:27471338

  12. Exploitation in International Paid Surrogacy Arrangements.

    Science.gov (United States)

    Wilkinson, Stephen

    2016-05-01

    Many critics have suggested that international paid surrogacy is exploitative. Taking such concerns as its starting point, this article asks: (1) how defensible is the claim that international paid surrogacy is exploitative and what could be done to make it less exploitative? (2) In the light of the answer to (1), how strong is the case for prohibiting it? Exploitation could in principle be dealt with by improving surrogates' pay and conditions. However, doing so may exacerbate problems with consent. Foremost amongst these is the argument that surrogates from economically disadvantaged countries cannot validly consent because their background circumstances are coercive. Several versions of this argument are examined and I conclude that at least one has some merit. The article's overall conclusion is that while ethically there is something to be concerned about, paid surrogacy is in no worse a position than many other exploitative commercial transactions which take place against a backdrop of global inequality and constrained options, such as poorly-paid and dangerous construction work. Hence, there is little reason to single surrogacy out for special condemnation. On a policy level, the case for prohibiting international commercial surrogacy is weak, despite legitimate concerns about consent and background poverty.

  13. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-11-15

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

  14. Dissemination and Exploitation Strategy

    DEFF Research Database (Denmark)

    Badger, Merete; Monaco, Lucio; Fransson, Torsten

    of Technology in Sweden, Politecnico di Torino in Italy, and Eindhoven University of Technology in the Netherlands. The project is partially funded by the European Commission under the 7th Framework Programme (project no. RI-283746). This report describes the final dissemination and exploitation strategy...... for project Virtual Campus Hub. A preliminary dissemination and exploitation plan was setup early in the project as described in the deliverable D6.1 Dissemination strategy paper - preliminary version. The plan has been revised on a monthly basis during the project’s lifecycle in connection with the virtual...

  15. Prospects of geothermal resource exploitation

    International Nuclear Information System (INIS)

    Bourrelier, P.H.; Cornet, F.; Fouillac, C.

    1994-01-01

    The use of geothermal energy to generate electricity has only occurred during the past 50 years by drilling wells in aquifers close to magmas and producing either dry steam or hot water. The world's production of electricity from geothermal energy is over 6000 MWe and is still growing. The direct use of geothermal energy for major urban communities has been developed recently by exploitation of aquifers in sedimentary basins under large towns. Scaling up the extraction of heat implies the exploitation of larger and better located fields requiring an appropriate method of extraction; the objective of present attempts in USA, Japan and Europe is to create heat exchangers by the circulation of water between several deep wells. Two field categories are considered: the extension of classical geothermal fields beyond the aquifer areas, and areas favoured by both a high geothermal gradient, fractures inducing a natural permeability at large scale, and good commercial prospects (such as in the Rhenan Graben). Hot dry rocks concept has gained a large interest. 1 fig., 5 tabs., 11 refs

  16. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  17. Exploiting the energy potential of waste activated sludge with MicroSludge[Manure, biosolids, and organic industrial/commercial residuals in land applications programs : improving beneficial reuse and protection of water quality

    Energy Technology Data Exchange (ETDEWEB)

    Stephenson, R.; Laliberte, S. [Paradigm Environmental Technologies, Vancouver, BC (Canada); Nemeth, L. [Earth Tech Canada Inc., Burnaby, BC (Canada)

    2007-07-01

    When waste activated sludge (WAS) is efficiently converted to biogas through anaerobic digestion, the energy potential and economic value of WAS can be exploited. This paper discussed the chemical and pressure pre-treatment process using MicroSludge. MicroSludge uses alkaline pre-treatment to weaken cell membranes and a high-pressure homogenizer to liquefy the cells, enabling the anaerobic digester to work at a higher rate and more efficiently, destroying pathogens and generating less biosolids for disposal, with corresponding higher volumes of methane from which to generate added electrical power and/or produce added heat. MicroSludge was demonstrated at the Chilliwack waste water treatment plant (WWTP), located 115 km east of Vancouver. The paper provided a description of the Chilliwack WWTP and discussed the application of MicroSludge at a full-scale prototype plant. The MicroSludge plant was capable of pre-treating all of the waste secondary sludge generated at the Chilliwack WWTP prior to anaerobic digestion. The paper also discussed digester hydraulic retention time; scanning electron microscope images; temperature; pH; mass loading of primary sludge and waste activated sludge; total volatile solids concentrations; and digester gas composition. Operating and maintenance costs were also outlined along with electrical power costs, maintenance costs and chemical costs. Last, the paper presented the energy benefits for WWTPs when using MicroSludge. It was concluded that the economic benefits of MicroSludge are greater for plants with higher biosolids disposal costs and higher electrical utility costs. 6 refs., 8 tabs., 10 figs.

  18. Process controls for radiation hardened aluminum gate bulk silicon CMOS

    International Nuclear Information System (INIS)

    Gregory, B.L.

    1975-01-01

    Optimized dry oxides have recently yielded notable improvements in CMOS radiation-hardness. By following the proper procedures and recipes, it is now possible to produce devices which will function satisfactorily after exposure to a total ionizing dose in excess of 10 6 RADS (Si). This paper is concerned with the controls required on processing parameters once the optimized process is defined. In this process, the pre-irradiation electrical parameters must be closely controlled to insure that devices will function after irradiation. In particular, the specifications on n- and p-channel threshold voltages require tight control of fixed oxide charge, surface-state density, oxide thickness, and substrate and p-well surface concentrations. In order to achieve the above level of radiation hardness, certain processing procedures and parameters must also be closely controlled. Higher levels of cleanliness are required in the hardened process than are commonly required for commercial CMOS since, for hardened dry oxides, no impurity gettering can be employed during or after oxidation. Without such gettering, an unclean oxide is unacceptable due to bias-temperature instability. Correct pre-oxidation cleaning, residual surface damage removal, proper oxidation and annealing temperatures and times, and the correct metal sintering cycle are all important in determining device hardness. In a reproducible, hardened process, each of these processing steps must be closely controlled. (U.S.)

  19. Prospects for charge sensitive amplifiers in scaled CMOS

    Science.gov (United States)

    O'Connor, Paul; De Geronimo, Gianluigi

    2002-03-01

    Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

  20. Prospects for charge sensitive amplifiers in scaled CMOS

    International Nuclear Information System (INIS)

    O'Connor, Paul; De Geronimo, Gianluigi

    2002-01-01

    Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006

  1. A CMOS smart temperature and humidity sensor with combined readout.

    Science.gov (United States)

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-09-16

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

  2. Radiation hardening of CMOS-based circuitry in SMART transmitters

    International Nuclear Information System (INIS)

    Loescher, D.H.

    1993-02-01

    Process control transmitters that incorporate digital signal processing could be used advantageously in nuclear power plants; however, because such transmitters are too sensitive to radiation, they are not used. The Electric Power Research Institute sponsored work at Sandia National Laboratories under EPRI contract RP2614-58 to determine why SMART transmitters fail when exposed to radiation and to design and demonstrate SMART transmitter circuits that could tolerate radiation. The term ''SMART'' denotes transmitters that contain digital logic. Tests showed that transmitter failure was caused by failure of the complementary metal oxide semiconductors (CMOS)-integrated circuits which are used extensively in commercial transmitters. Radiation-hardened replacements were not available for the radiation-sensitive CMOS circuits. A conceptual design showed that a radiation-tolerant transmitter could be constructed. A prototype for an analog-to-digital converter subsection worked satisfactorily after a total dose of 30 megarads(Si). Encouraging results were obtained from preliminary bench-top tests on a dc-to-dc converter for the power supply subsection

  3. Optical readout of a triple-GEM detector by means of a CMOS sensor

    Energy Technology Data Exchange (ETDEWEB)

    Marafini, M. [INFN Sezione di Roma (Italy); Museo Storico della Fisica e Centro Studi e Ricerche “E. Fermi”, Roma (Italy); Patera, V. [INFN Sezione di Roma (Italy); Museo Storico della Fisica e Centro Studi e Ricerche “E. Fermi”, Roma (Italy); Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Pinci, D., E-mail: davide.pinci@roma1.infn.it [INFN Sezione di Roma (Italy); Sarti, A. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Dipartimento di Scienze di Base e Applicate per Ingegneria, Sapienza Università di Roma (Italy); Sciubba, A. [INFN Sezione di Roma (Italy); Museo Storico della Fisica e Centro Studi e Ricerche “E. Fermi”, Roma (Italy); Dipartimento di Scienze di Base e Applicate per Ingegneria, Sapienza Università di Roma (Italy); Spiriti, E. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy)

    2016-07-11

    In last years, the development of optical sensors has produced objects able to provide very interesting performance. Large granularity is offered along with a very high sensitivity. CMOS sensors with millions of pixels able to detect as few as two or three photons per pixel are commercially available and can be used to read-out the optical signals provided by tracking particle detectors. In this work the results obtained by optically reading-out a triple-GEM detector by a commercial CMOS sensor will be presented. A standard detector was assembled with a transparent window below the third GEM allowing the light to get out. The detector is supplied with an Ar/CF{sub 4} based gas mixture producing 650 nm wavelength photons matching the maximum quantum efficiency of the sensor.

  4. Real-time biochemical sensor based on Raman scattering with CMOS contact imaging.

    Science.gov (United States)

    Muyun Cao; Yuhua Li; Yadid-Pecht, Orly

    2015-08-01

    This work presents a biochemical sensor based on Raman scattering with Complementary metal-oxide-semiconductor (CMOS) contact imaging. This biochemical optical sensor is designed for detecting the concentration of solutions. The system is built with a laser diode, an optical filter, a sample holder and a commercial CMOS sensor. The output of the system is analyzed by an image processing program. The system provides instant measurements with a resolution of 0.2 to 0.4 Mol. This low cost and easy-operated small scale system is useful in chemical, biomedical and environmental labs for quantitative bio-chemical concentration detection with results reported comparable to a highly cost commercial spectrometer.

  5. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa; Sevilla, Galo Torres; Cordero, Marlon Diaz; Kutbee, Arwa T.

    2017-01-01

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications

  6. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  7. Visualization of heavy ion-induced charge production in a CMOS image sensor

    CERN Document Server

    Végh, J; Klamra, W; Molnár, J; Norlin, LO; Novák, D; Sánchez-Crespo, A; Van der Marel, J; Fenyvesi, A; Valastyan, I; Sipos, A

    2004-01-01

    A commercial CMOS image sensor was irradiated with heavy ion beams in the several MeV energy range. The image sensor is equipped with a standard video output. The data were collected on-line through frame grabbing and analysed off-line after digitisation. It was shown that the response of the image sensor to the heavy ion bombardment varied with the type and energy of the projectiles. The sensor will be used for the CMS Barrel Muon Alignment system.

  8. A simple and low-cost biofilm quantification method using LED and CMOS image sensor.

    Science.gov (United States)

    Kwak, Yeon Hwa; Lee, Junhee; Lee, Junghoon; Kwak, Soo Hwan; Oh, Sangwoo; Paek, Se-Hwan; Ha, Un-Hwan; Seo, Sungkyu

    2014-12-01

    A novel biofilm detection platform, which consists of a cost-effective red, green, and blue light-emitting diode (RGB LED) as a light source and a lens-free CMOS image sensor as a detector, is designed. This system can measure the diffraction patterns of cells from their shadow images, and gather light absorbance information according to the concentration of biofilms through a simple image processing procedure. Compared to a bulky and expensive commercial spectrophotometer, this platform can provide accurate and reproducible biofilm concentration detection and is simple, compact, and inexpensive. Biofilms originating from various bacterial strains, including Pseudomonas aeruginosa (P. aeruginosa), were tested to demonstrate the efficacy of this new biofilm detection approach. The results were compared with the results obtained from a commercial spectrophotometer. To utilize a cost-effective light source (i.e., an LED) for biofilm detection, the illumination conditions were optimized. For accurate and reproducible biofilm detection, a simple, custom-coded image processing algorithm was developed and applied to a five-megapixel CMOS image sensor, which is a cost-effective detector. The concentration of biofilms formed by P. aeruginosa was detected and quantified by varying the indole concentration, and the results were compared with the results obtained from a commercial spectrophotometer. The correlation value of the results from those two systems was 0.981 (N = 9, P CMOS image-sensor platform. Copyright © 2014 Elsevier B.V. All rights reserved.

  9. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Science.gov (United States)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  10. A Standard CMOS Humidity Sensor without Post-Processing

    OpenAIRE

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023?10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  11. Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

    CERN Document Server

    Nguyen, Cam

    2017-01-01

    This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

  12. High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

    Science.gov (United States)

    Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

    2017-02-01

    Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

  13. Development of a lens-coupled CMOS detector for an X-ray inspection system

    International Nuclear Information System (INIS)

    Kim, Ho Kyung; Ahn, Jung Keun; Cho, Gyuseong

    2005-01-01

    A digital X-ray imaging detector based on a complementary metal-oxide-semiconductor (CMOS) image sensor has been developed for X-ray non-destructive inspection applications. This is a cost-effective solution because of the availability of cheap commercial standard CMOS image sensors. The detector configuration adopts an indirect X-ray detection method by using scintillation material and lens assembly. As a feasibility test of the developed lens-coupled CMOS detector as an X-ray inspection system, we have acquired X-ray projection images under a variety of imaging conditions. The results show that the projected image is reasonably acceptable in typical non-destructive testing (NDT). However, the developed detector may not be appropriate for laminography due to a low light-collection efficiency of lens assembly. In this paper, construction of the lens-coupled CMOS detector and its specifications are described, and the experimental results are presented. Using the analysis of quantum accounting diagram, inefficiency of the lens-coupling method is discussed

  14. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  15. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  16. Negative Offset Operation of Four-Transistor CMOS Image Pixels for Increased Well Capacity and Suppressed Dark Current

    OpenAIRE

    Mheen, B.; Song, Y.J.; Theuwissen, J.P.

    2008-01-01

    This letter presents an electrical method to reduce dark current as well as increase well capacity of four-transistor pixels in a CMOS image sensor, utilizing a small negative offset voltage to the gate of the transfer (TX) transistor particularly only when the TX transistor is off. As a result, using a commercial pixel in a 0.18 ?m CMOS process, the voltage drop due to dark current of the pinned photodiode (PPD) is reduced by 6.1 dB and the well capacity is enhanced by 4.4 dB, which is attri...

  17. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  18. CMOS Compressed Imaging by Random Convolution

    OpenAIRE

    Jacques, Laurent; Vandergheynst, Pierre; Bibet, Alexandre; Majidzadeh, Vahid; Schmid, Alexandre; Leblebici, Yusuf

    2009-01-01

    We present a CMOS imager with built-in capability to perform Compressed Sensing. The adopted sensing strategy is the random Convolution due to J. Romberg. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to comp...

  19. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  20. Challenges & Roadmap for Beyond CMOS Computing Simulation.

    Energy Technology Data Exchange (ETDEWEB)

    Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-12-01

    Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

  1. Design and application of a metal wet-etching post-process for the improvement of CMOS-MEMS capacitive sensors

    International Nuclear Information System (INIS)

    Tsai, Ming-Han; Sun, Chih-Ming; Liu, Yu-Chia; Fang, Weileun; Wang, Chuanwei

    2009-01-01

    This study presents a process design methodology to improve the performance of a CMOS-MEMS gap-closing capacitive sensor. In addition to the standard CMOS process, the metal wet-etching approach is employed as the post-CMOS process to realize the present design. The dielectric layers of the CMOS process are exploited to form the main micro mechanical structures of the sensor. The metal layers of the CMOS process are used as the sensing electrodes and sacrificial layers. The advantages of the sensor design are as follows: (1) the parasitic capacitance is significantly reduced by the dielectric structure, (2) in-plane and out-of-plane sensing gaps can be reduced to increase the sensitivity, and (3) plate-type instead of comb-type out-of-plane sensing electrodes are available to increase the sensing electrode area. To demonstrate the feasibility of the present design, a three-axis capacitive CMOS-MEMS accelerometers chip is implemented and characterized. Measurements show that the sensitivities of accelerometers reach 11.5 mV G −1 (in the X-, Y-axes) and 7.8 mV G −1 (in the Z-axis), respectively, which are nearly one order larger than existing designs. Moreover, the detection of 10 mG excitation using the three-axis accelerometer is demonstrated for both in-plane and out-of-plane directions

  2. Energy for lunar resource exploitation

    Science.gov (United States)

    Glaser, Peter E.

    1992-02-01

    Humanity stands at the threshold of exploiting the known lunar resources that have opened up with the access to space. America's role in the future exploitation of space, and specifically of lunar resources, may well determine the level of achievement in technology development and global economic competition. Space activities during the coming decades will significantly influence the events on Earth. The 'shifting of history's tectonic plates' is a process that will be hastened by the increasingly insistent demands for higher living standards of the exponentially growing global population. Key to the achievement of a peaceful world in the 21st century, will be the development of a mix of energy resources at a societally acceptable and affordable cost within a realistic planning horizon. This must be the theme for the globally applicable energy sources that are compatible with the Earth's ecology. It is in this context that lunar resources development should be a primary goal for science missions to the Moon, and for establishing an expanding human presence. The economic viability and commercial business potential of mining, extracting, manufacturing, and transporting lunar resource based materials to Earth, Earth orbits, and to undertake macroengineering projects on the Moon remains to be demonstrated. These extensive activities will be supportive of the realization of the potential of space energy sources for use on Earth. These may include generating electricity for use on Earth based on beaming power from Earth orbits and from the Moon to the Earth, and for the production of helium 3 as a fuel for advanced fusion reactors.

  3. Hacking the art of exploitation

    CERN Document Server

    Erickson, Jon

    2003-01-01

    A comprehensive introduction to the techniques of exploitation and creative problem-solving methods commonly referred to as "hacking," Hacking: The Art of Exploitation is for both technical and non-technical people who are interested in computer security. It shows how hackers exploit programs and write exploits, instead of just how to run other people's exploits. Unlike many so-called hacking books, this book explains the technical aspects of hacking, including stack based overflows, heap based overflows, string exploits, return-into-libc, shellcode, and cryptographic attacks on 802.11b.

  4. On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

    Directory of Open Access Journals (Sweden)

    Hongyi Mi

    2017-03-01

    Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

  5. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Directory of Open Access Journals (Sweden)

    Chris R. Bowen

    2011-05-01

    Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  6. Low noise monolithic CMOS front end electronics

    International Nuclear Information System (INIS)

    Lutz, G.; Bergmann, H.; Holl, P.; Manfredi, P.F.

    1987-01-01

    Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

  7. CMOS VHF transconductance-C lowpass filter

    NARCIS (Netherlands)

    Nauta, Bram

    1990-01-01

    Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response

  8. CMOS switched current phase-locked loop

    NARCIS (Netherlands)

    Leenaerts, D.M.W.; Persoon, G.G.; Putter, B.M.

    1997-01-01

    The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes

  9. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  10. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  11. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  12. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  13. CMOS cassette for digital upgrade of film-based mammography systems

    Science.gov (United States)

    Baysal, Mehmet A.; Toker, Emre

    2006-03-01

    While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

  14. Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

    Science.gov (United States)

    Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

    2014-03-01

    We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

  15. Nanostructured Basaltfiberconcrete Exploitational Characteristics

    Science.gov (United States)

    Saraykina, K. A.; Shamanov, V. A.

    2017-11-01

    The article demonstrates that the mass use of basalt fiber concrete (BFC) is constrained by insufficient study of their durability and serviceability in a variety of environments. This research is aimed at the study of the basalt fiber corrosion processes in the cement stone of BFC, the control of the new products structure formation in order to protect the reinforcing fiber from alkaline destruction and thereby improve the exploitational characteristics of the composite. The research result revealed that the modification of basaltfiber concrete by the dispersion of MWNTs contributes to the directional formation of new products in the cement matrix. The HAM additive in basaltfiberconcrete provides for the binding of portlandite to low-basic calcium hydroaluminosilicates, thus reducing the aggressive effect of the cement environment on the reinforcing fibers properties. The complex modification of BFC with nanostructured additives provides for an increase in its durability and exploitational properties (strength, frost resistance and water resistance) due to basalt fiber protection from alkali corrosion on account of the compacting of the contact zone “basalt fiber - cement stone” and designing of the new products structure and morphology of cement matrix over the fiber surface.

  16. CMOS circuits for piezoelectric energy harvesters efficient power extraction, interface modeling and loss analysis

    CERN Document Server

    Hehn, Thorsten

    2014-01-01

    This book deals with the challenge of exploiting ambient vibrational energy which can be used to power small and low-power electronic devices, e.g. wireless sensor nodes. Generally, particularly for low voltage amplitudes, low-loss rectification is required to achieve high conversion efficiency. In the special case of piezoelectric energy harvesting, pulsed charge extraction has the potential to extract more power compared to a single rectifier. For this purpose, a fully autonomous CMOS integrated interface circuit for piezoelectric generators which fulfills these requirements is presented.Due

  17. Single Photon Counting Performance and Noise Analysis of CMOS SPAD-Based Image Sensors

    Science.gov (United States)

    Dutton, Neale A. W.; Gyongy, Istvan; Parmesan, Luca; Henderson, Robert K.

    2016-01-01

    SPAD-based solid state CMOS image sensors utilising analogue integrators have attained deep sub-electron read noise (DSERN) permitting single photon counting (SPC) imaging. A new method is proposed to determine the read noise in DSERN image sensors by evaluating the peak separation and width (PSW) of single photon peaks in a photon counting histogram (PCH). The technique is used to identify and analyse cumulative noise in analogue integrating SPC SPAD-based pixels. The DSERN of our SPAD image sensor is exploited to confirm recent multi-photon threshold quanta image sensor (QIS) theory. Finally, various single and multiple photon spatio-temporal oversampling techniques are reviewed. PMID:27447643

  18. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  19. Analysis of 3D stacked fully functional CMOS Active Pixel Sensor detectors

    International Nuclear Information System (INIS)

    Passeri, D; Servoli, L; Meroli, S

    2009-01-01

    The IC technology trend is to move from 3D flexible configurations (package on package, stacked dies) to real 3D ICs. This is mainly due to i) the increased electrical performances and ii) the cost of 3D integration which may be cheaper than to keep shrinking 2D circuits. Perspective advantages for particle tracking and vertex detectors applications in High Energy Physics can be envisaged: in this work, we will focus on the capabilities of the state-of-the-art vertical scale integration technologies, allowing for the fabrication of very compact, fully functional, multiple layers CMOS Active Pixel Sensor (APS) detectors. The main idea is to exploit the features of the 3D technologies for the fabrication of a ''stack'' of very thin and precisely aligned CMOS APS layers, leading to a single, integrated, multi-layers pixel sensor. The adoption of multiple-layers single detectors can dramatically reduce the mass of conventional, separated detectors (thus reducing multiple scattering issues), at the same time allowing for very precise measurements of particle trajectory and momentum. As a proof of concept, an extensive device and circuit simulation activity has been carried out, aiming at evaluate the suitability of such a kind of CMOS active pixel layers for particle tracking purposes.

  20. Gun muzzle flash detection using a CMOS single photon avalanche diode

    Science.gov (United States)

    Merhav, Tomer; Savuskan, Vitali; Nemirovsky, Yael

    2013-10-01

    Si based sensors, in particular CMOS Image sensors, have revolutionized low cost imaging systems but to date have hardly been considered as possible candidates for gun muzzle flash detection, due to performance limitations, and low SNR in the visible spectrum. In this study, a CMOS Single Photon Avalanche Diode (SPAD) module is used to record and sample muzzle flash events in the visible spectrum, from representative weapons, common on the modern battlefield. SPADs possess two crucial properties for muzzle flash imaging - Namely, very high photon detection sensitivity, coupled with a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. This enables high sampling frequencies in the kilohertz range without SNR degradation, in contrast to regular CMOS image sensors. To date, the SPAD has not been utilized for flash detection in an uncontrolled environment, such as gun muzzle flash detection. Gun propellant manufacturers use alkali salts to suppress secondary flashes ignited during the muzzle flash event. Common alkali salts are compounds based on Potassium or Sodium, with spectral emission lines around 769nm and 589nm, respectively. A narrow band filter around the Potassium emission doublet is used in this study to favor the muzzle flash signal over solar radiation. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength under the specified imaging conditions. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics.

  1. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

    Directory of Open Access Journals (Sweden)

    Preethi Padmanabhan

    2018-02-01

    Full Text Available Gallium nitride (GaN and its alloys are becoming preferred materials for ultraviolet (UV detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs, implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

  2. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

    Science.gov (United States)

    Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

    2018-01-01

    Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

  3. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

    Science.gov (United States)

    Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

    2018-02-03

    Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

  4. Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

    NARCIS (Netherlands)

    Bruccoleri, F.; Klumperink, Eric A.M.; Nauta, Bram

    Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In

  5. Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

    OpenAIRE

    Bruccoleri, F.; Klumperink, Eric A.M.; Nauta, Bram

    2004-01-01

    Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching d...

  6. Wideband CMOS receivers exploiting simultaneous output balancing and noise/distortion canceling

    NARCIS (Netherlands)

    Blaakmeer, S.C.; Klumperink, Eric A.M.; Leenaerts, D.M.W.; Nauta, Bram

    2008-01-01

    Abstract— This paper deals with the problem of realizing wideband receiver front-ends in downscaled CMOSTechnologies, which are highly wanted for multi-standard radio receivers and cognitive radio applications. Instead of using many narrowband inductor based receivers, we prefer the use of one

  7. Exploitation by Economic Necessity

    Directory of Open Access Journals (Sweden)

    Kristian F. Braekkan

    2015-10-01

    Full Text Available This study develops and tests a model that proposes economic necessity moderates the relationship between psychological contract violations (PCVs and organizational commitment and trust in the employing organization among non-unionized manufacturing workers (N = 226. Moderated regression analyses revealed that there was a significant interaction between PCV and economic necessity in predicting both outcomes. Specifically, the findings indicated that individuals experiencing high PCV and high economic necessity did not decrease their organizational commitment like their counterparts who endorsed lower economic necessity. They did, however, experience significantly decreased trust in their employer. The findings suggest that individuals who are forced to sell their labor power and obtain what they need through the market are more likely to continue to be exploited by their employer, as they have no other options than to continue the relationship. The importance of the findings is discussed, and recommendations for future research are provided.

  8. Exploitative Learning by Exporting

    DEFF Research Database (Denmark)

    Golovko, Elena; Lopes Bento, Cindy; Sofka, Wolfgang

    Decisions on entering foreign markets are among the most challenging but also potentially rewarding strategy choices managers can make. In this study, we examine the effect of export entry on the firm investment decisions in two activities associated with learning about new technologies...... and learning about new markets ? R&D investments and marketing investments, in search of novel insights into the content and process underlying learning by exporting. We draw from organizational learning theory for predicting changes in both R&D and marketing investment patterns that accompany firm entry......, it is predominantly the marketing-related investment decisions associated with starting to export that lead to increases in firm productivity. We conclude that learning-by-exporting might be more properly characterized as ?learning about and exploiting new markets? rather than ?learning about new technologies...

  9. Characterization and radiation studies of diode test structures in LFoundry CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Daas, Michael; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Muenchen (Germany)

    2016-07-01

    In order to prepare for the High Luminosity upgrade of the LHC, all subdetector systems of the ATLAS experiment will be upgraded. In preparation for this process, different possibilities for new radiation-hard and cost-efficient silicon sensor technologies to be used as part of hybrid pixel detectors in the ATLAS inner tracker are being investigated. One promising way to optimize the cost-efficiency of silicon-based pixel detectors is to use commercially available CMOS technologies such as the 150 nm process by LFoundry. In this talk, several CMOS pixel test structures, such as simple diodes and small pixel arrays, that were manufactured in this technology are characterized regarding general performance and radiation hardness and compared to each other as well as to the current ATLAS pixel detector.

  10. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

    Energy Technology Data Exchange (ETDEWEB)

    Bonacini, S

    2007-11-15

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

  11. Learning Metasploit exploitation and development

    CERN Document Server

    Balapure, Aditya

    2013-01-01

    A practical, hands-on tutorial with step-by-step instructions. The book will follow a smooth and easy-to-follow tutorial approach, covering the essentials and then showing the readers how to write more sophisticated exploits.This book targets exploit developers, vulnerability analysts and researchers, network administrators, and ethical hackers looking to gain advanced knowledge in exploitation development and identifying vulnerabilities. The primary goal is to take readers wishing to get into more advanced exploitation discovery and reaching the next level.Prior experience exploiting basic st

  12. There are two commercially exploited species of hake off Namibia ...

    African Journals Online (AJOL)

    denise

    on average 93% of the total landings of hake between. 1991 and ..... virtual population analysis (VPA) to formulate man- agement ... the same species below optimum levels, allowing the stock to .... 2001 — Depth-stratified density estimates.

  13. Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor

    Science.gov (United States)

    Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

    2013-09-01

    This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

  14. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    International Nuclear Information System (INIS)

    Liu, Yu-Chia; Tsai, Ming-Han; Fang, Weileun; Tang, Tsung-Lin

    2011-01-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  15. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  16. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  17. Recent developments with CMOS SSPM photodetectors

    Energy Technology Data Exchange (ETDEWEB)

    Stapels, Christopher J. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)], E-mail: CStapels@RMDInc.com; Barton, Paul [University of Michigan, Ann Arbor, MI (United States); Johnson, Erik B. [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Wehe, David K. [University of Michigan, Ann Arbor, MI (United States); Dokhale, Purushottam; Shah, Kanai [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Augustine, Frank L. [Augustine Engineering, Encinitas, CA (United States); Christian, James F. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)

    2009-10-21

    Experiments and simulations using various solid-state photomultiplier (SSPM) designs have been performed to evaluate pixel layouts and explore design choices. SPICE simulations of a design for position-sensing SSPMs showed charge division in the resistor network, and anticipated timing performance of the device. The simulation results predict good position information for resistances in the range of 1-5 k{omega} and 150-{omega} preamplifier input impedance. Back-thinning of CMOS devices can possibly increase the fill factor to 100%, improve spectral sensitivity, and allow for the deposition of anti-reflective coatings after fabrication. We report initial results from back illuminating a CMOS SSPM, and single Geiger-mode avalanche photodiode (GPD) pixels, thinned to 50 {mu}m.

  18. Desenvolvimento de uma matriz de portas CMOS

    OpenAIRE

    Jose Geraldo Mendes Taveira

    1991-01-01

    Resumo: É apresentado o projeto de uma matriz deportas CMOS. O capítulo 11 descreve as etapas de projeto, incluindo desde a escolha da topologia das células internas e de interface, o projeto e a simulação elétrica, até a geração do lay-out. Ocaprtulo III apresenta o projeto dos circuitos de aplicação, incluídos para permitir a validação da matriz. Os circuitos de apl icação são : Oscilador em anel e comparador de códigos. A matriz foi difundida no Primeiro Projeto Multi-Usuário CMOS Brasile...

  19. CMOS SPDT switch for WLAN applications

    International Nuclear Information System (INIS)

    Bhuiyan, M A S; Reaz, M B I; Rahman, L F; Minhad, K N

    2015-01-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal. (paper)

  20. Cmos spdt switch for wlan applications

    Science.gov (United States)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  1. Registration of Large Motion Blurred CMOS Images

    Science.gov (United States)

    2017-08-28

    raju@ee.iitm.ac.in - Institution : Indian Institute of Technology (IIT) Madras, India - Mailing Address : Room ESB 307c, Dept. of Electrical ...AFRL-AFOSR-JP-TR-2017-0066 Registration of Large Motion Blurred CMOS Images Ambasamudram Rajagopalan INDIAN INSTITUTE OF TECHNOLOGY MADRAS Final...NUMBER 5f.  WORK UNIT NUMBER 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) INDIAN INSTITUTE OF TECHNOLOGY MADRAS SARDAR PATEL ROAD Chennai, 600036

  2. Advanced CMOS Radiation Effects Testing and Analysis

    Science.gov (United States)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; hide

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  3. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation i...... for integration with existing insulator-metal-insu lator plasmonic waveguides as well as novel photonic/electronic hybrid circuits...

  4. Ultra-low Voltage CMOS Cascode Amplifier

    OpenAIRE

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique.

  5. Aging sensor for CMOS memory cells

    OpenAIRE

    Santos, Hugo Fernandes da Silva

    2016-01-01

    Dissertação de Mestrado, Engenharia e Tecnologia, Instituto Superior de Engenharia, Universidade do Algarve, 2016 As memórias Complementary Metal Oxide Semiconductor (CMOS) ocupam uma percentagem de área significativa nos circuitos integrados e, com o desenvolvimento de tecnologias de fabrico a uma escala cada vez mais reduzida, surgem problemas de performance e de fiabilidade. Efeitos como o BTI (Bias Thermal Instability), TDDB (Time Dependent Dielectric Breakdown), HCI (Hot Carrier Injec...

  6. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique......, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique....

  7. Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination

    Directory of Open Access Journals (Sweden)

    Michele Grassi

    2009-06-01

    Full Text Available This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively.

  8. Integrated CMOS dew point sensors for relative humidity measurement

    Science.gov (United States)

    Savalli, Nicolo; Baglio, Salvatore; Castorina, Salvatore; Sacco, Vincenzo; Tringali, Cristina

    2004-07-01

    This work deals with the development of integrated relative humidity dew point sensors realized by adopting standard CMOS technology for applications in various fields. The proposed system is composed by a suspended plate that is cooled by exploiting integrated Peltier cells. The cold junctions of the cells have been spread over the plate surface to improve the homogeneity of the temperature distribution over its surface, where cooling will cause the water condensation. The temperature at which water drops occur, named dew point temperature, is a function of the air humidity. Measurement of such dew point temperature and the ambient temperature allows to know the relative humidity. The detection of water drops is achieved by adopting a capacitive sensing strategy realized by interdigited fixed combs, composed by the upper layer of the adopted process. Such a capacitive sensor, together with its conditioning circuit, drives a trigger that stops the cooling of the plate and enables the reading of the dew point temperature. Temperature measurements are achieved by means of suitably integrated thermocouples. The analytical model of the proposed system has been developed and has been used to design a prototype device and to estimate its performances. In such a prototype, the thermoelectric cooler is composed by 56 Peltier cells, made by metal 1/poly 1 junctions. The plate has a square shape with 200 μm side, and it is realized by exploiting the oxide layers. Starting from the ambient temperature a temperature variation of ΔT = 15 K can be reached in 10 ms thus allowing to measure a relative humidity greater than 40%.

  9. CMOS image sensors: State-of-the-art

    Science.gov (United States)

    Theuwissen, Albert J. P.

    2008-09-01

    This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

  10. A receiver with in-band IIP3>20dBm, exploiting cancelling of OpAmp finite-gain-induced distortion via negative conductance

    NARCIS (Netherlands)

    Mahrof, D.H.; Klumperink, Eric A.M.; Oude Alink, M.S.; Nauta, Bram

    2013-01-01

    Highly linear CMOS radio receivers increasingly exploit linear RF V-I conversion and passive down-mixing, followed by an OpAmp based Transimpedance Amplifier at baseband. Due to the finite OpAmp gain in wideband receivers operating with large signals, virtual ground is imperfect, inducing distortion

  11. Profits and Exploitation: A Reappraisal

    OpenAIRE

    Yoshihara, Naoki; Veneziani, Roberto

    2011-01-01

    This paper provides a mathematical analysis of the Marxian theory of the exploitation of labour in general equilibrium models. The two main definitions of Marxian exploitation in the literature, proposed by Morishima (1974) and Roemer (1982), respectively, are analysed in the context of general convex economies. It is shown that, contrary to the received view, in general these definitions do not preserve the so-called Fundamental Marxian Theorem (FMT), which states that the exploitation of la...

  12. Commercial lumber

    Science.gov (United States)

    Kent A. McDonald; David E. Kretschmann

    1999-01-01

    In a broad sense, commercial lumber is any lumber that is bought or sold in the normal channels of commerce. Commercial lumber may be found in a variety of forms, species, and types, and in various commercial establishments, both wholesale and retail. Most commercial lumber is graded by standardized rules that make purchasing more or less uniform throughout the country...

  13. Dissemination and Exploitation: Project Goals beyond Science

    Science.gov (United States)

    Hamann, Kristin; Reitz, Anja

    2017-04-01

    Dissemination and Exploitation are essential parts of public funded projects. In Horizon 2020 a plan for the exploitation and dissemination of results (PEDR) is a requirement. The plan should contain a clear vision on the objectives of the project in relation to actions for dissemination and potential exploitation of the project results. The actions follow the basic idea to spread the knowledge and results gathered within the project and face the challenge of how to bring the results into potentially relevant policy circle and how they impact the market. The plan follows the purpose to assess the impact of the project and to address various target groups who are interested in the project results. Simply put, dissemination concentrates on the transfer of knowledge and exploitation on the commercialization of the project. Beyond the question of the measurability of project`s impact, strategies within science marketing can serve purposes beyond internal and external communication. Accordingly, project managers are facing the challenge to implement a dissemination and exploitation strategy that ideally supports the identification of all partners with the project and matches the current discourse of the project`s content within the society, politics and economy. A consolidated plan might unite all projects partners under a central idea and supports the identification with the project beyond the individual research questions. Which applications, strategies and methods can be used to bring forward a PEDR that accompanies a project successfully and allows a comprehensive assessment of the project afterwards? Which hurdles might project managers experience in the dissemination process and which tasks should be fulfilled by the project manager?

  14. Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

    Science.gov (United States)

    Kremastiotis, I.

    2017-12-01

    The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (~20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ~20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (~20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

  15. Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

    CERN Document Server

    AUTHOR|(SzGeCERN)756402

    2017-01-01

    The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128 × 128 square pixels with 25 μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼ 20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼ 20 ns for a power consumption of 5 μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼ 20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using...

  16. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications

    KAUST Repository

    Hussain, Aftab M.

    2015-11-26

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today\\'s digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  17. 270GHz SiGe BiCMOS manufacturing process platform for mmWave applications

    Science.gov (United States)

    Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

    2011-11-01

    TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

  18. SiGe BiCMOS manufacturing platform for mmWave applications

    Science.gov (United States)

    Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

    2010-10-01

    TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18μm and 0.13μm node CMOS processes along with high density 5.6fF/μm2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

  19. Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier

    International Nuclear Information System (INIS)

    Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

    2010-01-01

    The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

  20. Trajectories and cycles of sexual exploitation and trafficking for sexual exploitation of women in the Peruvian Amazon

    OpenAIRE

    Mujica, Jaris

    2015-01-01

    The commercial sexual exploitation is a constant activity in the Peruvian Amazon. Around the river port of Pucallpa in ucayali region, the practice appears systematically: teenage attend taverns around the port, and those dedicated to the work of cooking camps logging, are victims of constant exploitation and many also of trafficking. this article aims to reconstruct the path of life and reproductive cycle of the forms of exploitation in a sample of 20 women, and focuses on: (i) evidence of s...

  1. Consensual exploitation : the moral wrong in exploitation and legal restrictions on consensual exploitative transactions

    OpenAIRE

    van der Neut, Wendy

    2014-01-01

    This thesis is about so-­‐called consensual exploitative transactions: transactions to which all parties agree voluntarily, and which are beneficial for all parties, but which are still widely considered exploitative, and for that reason legally restricted in many countries. The thesis asks two main questions: 1. What is wrong with consensual exploitation? 2.What implications does the answer to this question have for the legal restriction of consensual transactions ...

  2. Development of ultra-light pixelated systems based on CMOS sensors for future high precision vertex detectors

    Energy Technology Data Exchange (ETDEWEB)

    Winter, Marc [Institut Pluridisciplinaire Hubert Curien - IPHC, 23 rue du loess - BP28, 67037 Strasbourg cedex 2 (France)

    2010-07-01

    CMOS pixel sensors have demonstrated attractive performances in terms of spatial resolution and material budget. The recent emergence of high resistivity substrates in mass production CMOS processes has originated particularly high signal-to-noise ratios and improved the non-ionising radiation tolerance to fluences close to 10{sup 14} Neq/cm{sup 2}. These achievements, obtained with MIMOSA sensors developed at IPHC (Strasbourg) and IRFU (Saclay) will be overviewed and put in perspective of the numerous applications of the sensors. These include collider experiments at RHIC, LHC, ILC and CLIC. The development of ultra-light ladders composed of these sensors and featuring 0.1% to 0.3% of radiation length, will be summarised. The contribution to the conference will also address the evolution of these pixelated systems, including on-going R on multi-tier sensors exploiting vertical integration technologies. (author)

  3. Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

    International Nuclear Information System (INIS)

    Bonacini, S.

    2007-11-01

    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

  4. A novel compact model for on-chip stacked transformers in RF-CMOS technology

    Science.gov (United States)

    Jun, Liu; Jincai, Wen; Qian, Zhao; Lingling, Sun

    2013-08-01

    A novel compact model for on-chip stacked transformers is presented. The proposed model topology gives a clear distinction to the eddy current, resistive and capacitive losses of the primary and secondary coils in the substrate. A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided. The model is further verified by the excellent match between the measured and simulated S -parameters on the extracted parameters for a 1 : 1 stacked transformer manufactured in a commercial RF-CMOS technology.

  5. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  6. Cryo-CMOS Circuits and Systems for Quantum Computing Applications

    NARCIS (Netherlands)

    Patra, B; Incandela, R.M.; van Dijk, J.P.G.; Homulle, H.A.R.; Song, Lin; Shahmohammadi, M.; Staszewski, R.B.; Vladimirescu, A.; Babaie, M.; Sebastiano, F.; Charbon, E.E.E.

    2018-01-01

    A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising

  7. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

  8. First principle leakage current reduction technique for CMOS devices

    CSIR Research Space (South Africa)

    Tsague, HD

    2015-12-01

    Full Text Available This paper presents a comprehensive study of leakage reduction techniques applicable to CMOS based devices. In the process, mathematical equations that model the power-performance trade-offs in CMOS logic circuits are presented. From those equations...

  9. Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

    International Nuclear Information System (INIS)

    Miucci, A; Gonzalez-Sevilla, S; Ferrere, D; Iacobucci, G; Rosa, A La; Muenstermann, D; Gonella, L; Hemperek, T; Hügging, F; Krüger, H; Obermann, T; Wermes, N; Garcia-Sciveres, M; Backhaus, M; Capeans, M; Feigl, S; Nessi, M; Pernegger, H; Ristic, B; George, M

    2014-01-01

    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

  10. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  11. Simulations of depleted CMOS sensors for high-radiation environments

    CERN Document Server

    Liu, J.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Degerli, Y.; Godiot-Basolo, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Moustakas, K.; Pangaud, P.; Rozanov, A.; Rymaszewski, P.; Schwemling, P.; Wang, M.; Wang, T.; Wermes, N.; Zhang, L.

    2017-01-01

    After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

  12. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa

    2017-11-23

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

  13. Broadband image sensor array based on graphene-CMOS integration

    Science.gov (United States)

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  14. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  15. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2003-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved....... A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0...

  16. CMOS current controlled fully balanced current conveyor

    International Nuclear Information System (INIS)

    Wang Chunhua; Zhang Qiujing; Liu Haiguang

    2009-01-01

    This paper presents a current controlled fully balanced second-generation current conveyor circuit (CF-BCCII). The proposed circuit has the traits of fully balanced architecture, and its X-Y terminals are current controllable. Based on the CFBCCII, two biquadratic universal filters are also proposed as its applications. The CFBCCII circuits and the two filters were fabricated with chartered 0.35-μm CMOS technology; with ±1.65 V power supply voltage, the total power consumption of the CFBCCII circuit is 3.6 mW. Comparisons between measured and HSpice simulation results are also given.

  17. CMOS Current-mode Operational Amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1992-01-01

    current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain bandwidth product of 8 MHz, an offset current of 0.8 ¿A (signal-range ±700¿A) and a (theoretically) unlimited slew-rate. The amplifier is realized in a standard CMOS 2......A fully differential-input differential-output current-mode operational amplifier (COA) is described. The amplifier utilizes three second generation current-conveyors (CCII) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced...

  18. A CMOS current-mode operational amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1993-01-01

    current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2......A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced...

  19. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Pikor, A.; Reiss, E.M.

    1980-01-01

    Substantial effort has been directed at radiation-hardening CMOS integrated circuits using various oxide processes. While most of these integrated circuits have been successful in demonstrating megarad hardness, further investigations have shown that the 'wet-oxide process' is most compatible with the RCA CD4000 Series process. This article describes advances in the wet-oxide process that have resulted in multimegarad hardness and yield to MIL-M-38510 screening requirements. The implementation of these advances into volume manufacturing is geared towards supplying devices for aerospace requirements such as the Defense Meterological Satellite program (DMSP) and the Global Positioning Satellite (GPS). (author)

  20. Monolithic CMOS imaging x-ray spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  1. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  2. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  3. A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

    Science.gov (United States)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-01-01

    This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

  4. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  5. Neutron-induced soft errors in CMOS circuits

    International Nuclear Information System (INIS)

    Hazucha, P.

    1999-01-01

    The subject of this thesis is a systematic study of soft errors occurring in CMOS integrated circuits when being exposed to radiation. The vast majority of commercial circuits operate in the natural environment ranging from the sea level to aircraft flight altitudes (less than 20 km), where the errors are caused mainly by interaction of atmospheric neutrons with silicon. Initially, the soft error rate (SER) of a static memory was measured for supply voltages from 2V to 5V when irradiated by 14 MeV and 100 MeV neutrons. Increased error rate due to the decreased supply voltage has been identified as a potential hazard for operation of future low-voltage circuits. A novel methodology was proposed for accurate SER characterization of a manufacturing process and it was validated by measurements on a 0.6 μm process and 100 MeV neutrons. The methodology can be applied to the prediction of SER in the natural environment

  6. Radiation Tolerant Design with 0.18-micron CMOS Technology

    CERN Document Server

    Chen, Li; Durdle , Nelson G.

    This thesis discusse s th e issues r elated to the us e of enclosed-gate layou t trans isto rs and guard rings in a 0.18 μ m CMOS technology in order to im prove the radiation tolerance of ASICs. The thin gate oxides of subm icron technologies ar e inherently m ore radiation tole rant tha n the thick er oxides present in less advanced technologies. Using a commercial deep subm icron technology to bu ild up radiation-ha rdened circuits introduces several advantages com pared to a dedicated radiation-ha rd technology, such as speed, power, area, stability, and expense. Som e novel aspects related to the use of encl osed-gate layout transist ors are presented in this th esis. A m odel to calculate the aspect ratio is introduced and verified. Some im portant electrica l par ameters of the tran sistors such as threshold voltage, leakage current, subthreshold slope, and transconducta nce are studied before and afte...

  7. A Biologically Inspired CMOS Image Sensor

    CERN Document Server

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  8. A new CMOS Hall angular position sensor

    Energy Technology Data Exchange (ETDEWEB)

    Popovic, R.S.; Drljaca, P. [Swiss Federal Inst. of Tech., Lausanne (Switzerland); Schott, C.; Racz, R. [SENTRON AG, Zug (Switzerland)

    2001-06-01

    The new angular position sensor consists of a combination of a permanent magnet attached to a shaft and of a two-axis magnetic sensor. The permanent magnet produces a magnetic field parallel with the magnetic sensor plane. As the shaft rotates, the magnetic field also rotates. The magnetic sensor is an integrated combination of a CMOS Hall integrated circuit and a thin ferromagnetic disk. The CMOS part of the system contains two or more conventional Hall devices positioned under the periphery of the disk. The ferromagnetic disk converts locally a magnetic field parallel with the chip surface into a field perpendicular to the chip surface. Therefore, a conventional Hall element can detect an external magnetic field parallel with the chip surface. As the direction of the external magnetic field rotates in the chip plane, the output voltage of the Hall element varies as the cosine of the rotation angle. By placing the Hall elements at the appropriate places under the disk periphery, we may obtain the cosine signals shifted by 90 , 120 , or by any other angle. (orig.)

  9. CMOS latch-up analysis and prevention

    International Nuclear Information System (INIS)

    Shafer, B.D.

    1975-06-01

    An analytical model is presented which develops relationships between ionization rates, minority carrier lifetimes, and latch-up in bulk CMOS integrated circuits. The basic mechanism for latch-up is the SCR action reported by Gregory and Shafer. The SCR is composed of a vertical NPN transistor formed by the N-channel source diffusion, the P-Well, and the N-substrate. The second part of the SCR is the lateral PNP transistor made up of the P-channel source diffusion, the N-substrate, and P-Well. It is shown that the NPN transistor turns on due to photocurrent-induced lateral voltage drops in the base of the transistor. The gain of this double diffused transistor has been shown to be as high as 100. Therefore, the transistor action of this device produces a much larger current flow in the substrate. This transistor current adds to that produced by the P-Well diode photocurrent in the substrate. It is found that the combined flow of current in the substrate forward biases the base emitter junction of the PNP device long before this could occur due to the P-Well photocurrent alone. The analysis indicated that a CD4007A CMOS device biased in the normal mode of operation should latch at about 2 . 10 8 rads/sec. Experimental results produced latch-up at 1 to 3 . 10 8 rads/sec. (U.S.)

  10. Investigation of Toshiba 130nm CMOS process as a possible candidate for active silicon sensors in HEP and X-ray experiments

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Yunan; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany); Peric, Ivan [Karlsruhe Institute of Technology, Karlsruhe (Germany)

    2015-07-01

    Following the advances of commercial semiconductor manufacturing technologies there has recently been an increased interest within experimental physics community in applying CMOS manufacturing processes to developing active silicon sensors. Possibility of applying high voltage bias combined with high resistivity substrate allows for better depletion of sensor and therefore quicker and more efficient charge collection. One of processes that accommodates those features is Toshiba 130 nm CMOS technology (CMOS3E). Within our group a test chip was designed to examine the suitability of this technology for physics experiment (both for HEP and X-ray imaging). Design consisted of 4 pixel matrices with total of 12 different pixel flavors allowing for evaluation of various pixel geometries and architectures in terms of depletion depth, noise performance, charge collection efficiency, etc. During this talk initial outcome of this evaluation is presented, starting with brief introduction to technology itself, followed by results of TCAD simulations, description of final design and first measurements results.

  11. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L. [INFN, Pavia; Braga, D. [Fermilab; Christian, D. [Fermilab; Deptuch, G. [Fermilab; Fahim. F., Fahim. F. [Fermilab; Nodari, B. [Lyon, IPN; Ratti, L. [INFN, Pavia; Re, V. [INFN, Pavia; Zimmerman, T. [Fermilab

    2017-09-01

    This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

  12. Development of a CMOS process using high energy ion implantation

    International Nuclear Information System (INIS)

    Stolmeijer, A.

    1986-01-01

    The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

  13. Prevention of CMOS latch-up by gold doping

    International Nuclear Information System (INIS)

    Dawes, W.R.; Derbenwick, G.F.

    1976-01-01

    CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

  14. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  15. Advances in CMOS solid-state photomultipliers for scintillation detector applications

    Energy Technology Data Exchange (ETDEWEB)

    Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric [Radiation Monitoring Devices, 44 Hunt Street, Watertownm, MA 02472 (United States); Augustine, Frank L., E-mail: JChristian@RMDInc.co [Augustine Engineering, 2115 Park Dale Ln, Encinitas, CA 92024 (United States)

    2010-12-11

    Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance.

  16. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  17. Using polynomials to simplify fixed pattern noise and photometric correction of logarithmic CMOS image sensors.

    Science.gov (United States)

    Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

    2015-10-16

    An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient.

  18. Development of Fast and High Precision CMOS Pixel Sensors for an ILC Vertex Detector

    CERN Document Server

    Hu-Guo, Christine

    2010-01-01

    The development of CMOS pixel sensors with column parallel read-out and integrated zero-suppression has resulted in a full size, nearly 1 Megapixel, prototype with ~100 \\mu s read-out time. Its performances are quite close to the ILD vertex detector specifications, showing that the sensor architecture can presumably be evolved to meet these specifications exactly. Starting from the existing architecture and achieved performances, the paper will expose the details of how the sensor will be evolved in the coming 2-3 years in perspective of the ILD Detector Baseline Document, to be delivered in 2012. Two different devices are foreseen for this objective, one being optimized for the inner layers and their fast read-out requirement, while the other exploits the dimmed background in the outer layers to reduce the power consumption. The sensor evolution relies on a high resistivity epitaxial layer, on the use of an advanced CMOS process and on the combination of column-level ADCs with a pixel array. The paper will p...

  19. Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

    Science.gov (United States)

    Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

    2018-03-01

    Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

  20. Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

    Science.gov (United States)

    Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

    2017-09-01

    The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

  1. Floating Gate CMOS Dosimeter With Frequency Output

    Science.gov (United States)

    Garcia-Moreno, E.; Isern, E.; Roca, M.; Picos, R.; Font, J.; Cesari, J.; Pineda, A.

    2012-04-01

    This paper presents a gamma radiation dosimeter based on a floating gate sensor. The sensor is coupled with a signal processing circuitry, which furnishes a square wave output signal, the frequency of which depends on the total dose. Like any other floating gate dosimeter, it exhibits zero bias operation and reprogramming capabilities. The dosimeter has been designed in a standard 0.6 m CMOS technology. The whole dosimeter occupies a silicon area of 450 m250 m. The initial sensitivity to a radiation dose is Hz/rad, and to temperature and supply voltage is kHz/°C and 0.067 kHz/mV, respectively. The lowest detectable dose is less than 1 rad.

  2. CMOS image sensor with contour enhancement

    Science.gov (United States)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

  3. CHARACTERISTICS OF HYDROCARBON EXPLOITATION IN ARCTIC CIRCLE

    Directory of Open Access Journals (Sweden)

    Vanja Lež

    2013-12-01

    Full Text Available The existence of large quantities of hydrocarbons is supposed within the Arctic Circle. Assumed quantities are 25% of the total undiscovered hydrocarbon reserves on Earth, mostly natural gas. Over 500 major and minor gas accumulations within the Arctic Circle were discovered so far, but apart from Snøhvit gas field, there is no commercial exploitation of natural gas from these fields. Arctic gas projects are complicated, technically hard to accomplish, and pose a great threat to the return of investment, safety of people and equipment and for the ecosystem. Russia is a country that is closest to the realization of the Arctic gas projects that are based on the giant gas fields. The most extreme weather conditions in the seas around Greenland are the reason why this Arctic region is the least explored and furthest from the realization of any gas project (the paper is published in Croatian .

  4. Device Innovation and Material Challenges at the Limits of CMOS Technology

    Science.gov (United States)

    Solomon, P. M.

    2000-08-01

    Scaling of the predominant silicon complementary metal-oxide semiconductor (CMOS) technology is finally approaching an end after decades of exponential growth. This review explores the reasons for this limit and some of the strategies available to the semiconductor industry to continue the technology extension. Evolutionary change to the silicon transistor will be pursued as long as possible, with increasing demands being placed on materials. Eventually new materials such a silicon-germanium may be used, and new device topologies such as the double-gated transistor may be employed. These strategies are being pursued in research organizations today. It is likely that planar technology will reach its limit with devices on the 10-nm scale, and then the third dimension will have to be exploited more efficiently to achieve further performance and density improvements.

  5. A 3D deep n-well CMOS MAPS for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L., E-mail: luigi.gaioni@unipv.i [Universita di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Manghisoni, M. [Universita di Bergamo, I-24044 Dalmine (Bulgaria) (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Ratti, L. [Universita di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Re, V.; Traversi, G. [Universita di Bergamo, I-24044 Dalmine (Bulgaria) (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy)

    2010-05-21

    This work presents the features of a new kind of deep n-well monolithic active pixel sensor (DNW-MAPS), called SDR1 (Sparsified Data Readout), which exploits the capabilities of vertical integration (3D) processing in view of the design of a high granularity detector for vertexing applications at the International Linear Collider (ILC). SDR1 inherits and extends the functional capabilities of DNW-MAPS fabricated in planar (2D) CMOS technology and is expected to show better collection efficiency with respect to 2D versions. The aim of the paper is to outline the features of analog and digital architecture of the SDR1 chip, together with circuit simulations data. Also some device simulation results concerning detection efficiency will be discussed.

  6. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  7. CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

    Science.gov (United States)

    Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

    2018-04-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  8. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    Science.gov (United States)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  9. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  10. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

    2018-01-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  11. CMOS serial link for fully duplexed data communication

    Science.gov (United States)

    Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

    1995-04-01

    This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

  12. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  13. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    International Nuclear Information System (INIS)

    Zhang Guo-An; He Jin; Zhang Dong-Wei; Su Yan-Mei; Wang Cheng; Chen Qin; Liang Hai-Lang; Ye Yun

    2012-01-01

    A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology

  14. A novel CMOS SRAM feedback element for SEU environments

    International Nuclear Information System (INIS)

    Verghese, S.; Wortman, J.J.; Kerns, S.E.

    1987-01-01

    A hardened CMOS SRAM has been proposed which utilizes a leaky polysilicon Schottky diode placed in the feedback path to attain the SEU immunity of resistor-coupled SRAMs while improving the access speed of the cell. Novel polysilicon hybrid Schottky-resistor structures which emulate the leaky diodes have been designed and fabricated. The elements' design criteria and methods of fulfilling them are presented along with a practical implementation scheme for CMOS SRAM cells

  15. Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier

    OpenAIRE

    Hassan Jassim Motlak

    2015-01-01

    A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to...

  16. CMOS Image Sensors: Electronic Camera On A Chip

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  17. The law and economics of international sex slavery: prostitution laws and trafficking for sexual exploitation

    OpenAIRE

    Jakobsson, Niklas; Kotsadam, Andreas

    2013-01-01

    International trafficking in humans for sexual exploitation is an eco- nomic activity driven by profit motives. Laws regarding commercial sex influence the profitability of trafficking and may thus affect the inflow of trafficking to a country. Using two recent sources of European cross country data we show that trafficking of persons for commercial sexual exploitation (as proxied by the data sets we are using) is least prevalent in coun...

  18. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  19. Advancement of CMOS Doping Technology in an External Development Framework

    Science.gov (United States)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  20. Design optimization of radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    1975-01-01

    Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

  1. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  2. Commercial Toilets

    Science.gov (United States)

    Whether you are looking to reduce water use in a new facility or replace old, inefficient toilets in commercial restrooms, a WaterSense labeled flushometer-valve toilet is a high-performance, water-efficient option worth considering.

  3. Cloud Based Earth Observation Data Exploitation Platforms

    Science.gov (United States)

    Romeo, A.; Pinto, S.; Loekken, S.; Marin, A.

    2017-12-01

    In the last few years data produced daily by several private and public Earth Observation (EO) satellites reached the order of tens of Terabytes, representing for scientists and commercial application developers both a big opportunity for their exploitation and a challenge for their management. New IT technologies, such as Big Data and cloud computing, enable the creation of web-accessible data exploitation platforms, which offer to scientists and application developers the means to access and use EO data in a quick and cost effective way. RHEA Group is particularly active in this sector, supporting the European Space Agency (ESA) in the Exploitation Platforms (EP) initiative, developing technology to build multi cloud platforms for the processing and analysis of Earth Observation data, and collaborating with larger European initiatives such as the European Plate Observing System (EPOS) and the European Open Science Cloud (EOSC). An EP is a virtual workspace, providing a user community with access to (i) large volume of data, (ii) algorithm development and integration environment, (iii) processing software and services (e.g. toolboxes, visualization routines), (iv) computing resources, (v) collaboration tools (e.g. forums, wiki, etc.). When an EP is dedicated to a specific Theme, it becomes a Thematic Exploitation Platform (TEP). Currently, ESA has seven TEPs in a pre-operational phase dedicated to geo-hazards monitoring and prevention, costal zones, forestry areas, hydrology, polar regions, urban areas and food security. On the technology development side, solutions like the multi cloud EO data processing platform provides the technology to integrate ICT resources and EO data from different vendors in a single platform. In particular it offers (i) Multi-cloud data discovery, (ii) Multi-cloud data management and access and (iii) Multi-cloud application deployment. This platform has been demonstrated with the EGI Federated Cloud, Innovation Platform Testbed Poland

  4. Hardness variability in commercial technologies

    International Nuclear Information System (INIS)

    Shaneyfelt, M.R.; Winokur, P.S.; Meisenheimer, T.L.; Sexton, F.W.; Roeske, S.B.; Knoll, M.G.

    1994-01-01

    The radiation hardness of commercial Floating Gate 256K E 2 PROMs from a single diffusion lot was observed to vary between 5 to 25 krad(Si) when irradiated at a low dose rate of 64 mrad(Si)/s. Additional variations in E 2 PROM hardness were found to depend on bias condition and failure mode (i.e., inability to read or write the memory), as well as the foundry at which the part was manufactured. This variability is related to system requirements, and it is shown that hardness level and variability affect the allowable mode of operation for E 2 PROMs in space applications. The radiation hardness of commercial 1-Mbit CMOS SRAMs from Micron, Hitachi, and Sony irradiated at 147 rad(Si)/s was approximately 12, 13, and 19 krad(Si), respectively. These failure levels appear to be related to increases in leakage current during irradiation. Hardness of SRAMs from each manufacturer varied by less than 20%, but differences between manufacturers are significant. The Qualified Manufacturer's List approach to radiation hardness assurance is suggested as a way to reduce variability and to improve the hardness level of commercial technologies

  5. A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

    International Nuclear Information System (INIS)

    Traversi, G; Manghisoni, M; Re, V; Gaioni, L; Ratti, L

    2011-01-01

    Deep N-Well (DNW) Monolithic Active Pixel Sensors (MAPS) have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. In these devices the triple well option, available in deep submicron processes, is exploited to implement analog and digital signal processing at the pixel level. Many prototypes have been fabricated in a planar (2D) 130nm CMOS technology. A new kind of DNW-MAPS, namely Apsel5 3 D, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. The impact of 3D processes on the design and performance of DNW pixel sensors could be large, with significant advantages in terms of detection efficiency, pixel cell size and immunity to cross-talk, therefore complying with the severe constraints set by future HEP experiments.

  6. A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

    Energy Technology Data Exchange (ETDEWEB)

    Traversi, G; Manghisoni, M; Re, V [University of Bergamo, Via Marconi 5, 24044 Dalmine (Italy); Gaioni, L; Ratti, L, E-mail: gianluca.traversi@unibg.it [INFN Pavia, Via Bassi 6, 27100 Pavia (Italy)

    2011-01-15

    Deep N-Well (DNW) Monolithic Active Pixel Sensors (MAPS) have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. In these devices the triple well option, available in deep submicron processes, is exploited to implement analog and digital signal processing at the pixel level. Many prototypes have been fabricated in a planar (2D) 130nm CMOS technology. A new kind of DNW-MAPS, namely Apsel5{sub 3}D, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. The impact of 3D processes on the design and performance of DNW pixel sensors could be large, with significant advantages in terms of detection efficiency, pixel cell size and immunity to cross-talk, therefore complying with the severe constraints set by future HEP experiments.

  7. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-11-04

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  8. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-01-01

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

  9. Space Commercialization

    Science.gov (United States)

    Martin, Gary L.

    2011-01-01

    A robust and competitive commercial space sector is vital to continued progress in space. The United States is committed to encouraging and facilitating the growth of a U.S. commercial space sector that supports U.S. needs, is globally competitive, and advances U.S. leadership in the generation of new markets and innovation-driven entrepreneurship. Energize competitive domestic industries to participate in global markets and advance the development of: satellite manufacturing; satellite-based services; space launch; terrestrial applications; and increased entrepreneurship. Purchase and use commercial space capabilities and services to the maximum practical extent Actively explore the use of inventive, nontraditional arrangements for acquiring commercial space goods and services to meet United States Government requirements, including measures such as public-private partnerships, . Refrain from conducting United States Government space activities that preclude, discourage, or compete with U.S. commercial space activities. Pursue potential opportunities for transferring routine, operational space functions to the commercial space sector where beneficial and cost-effective.

  10. Sexual exploitation and labor during adolescence: A case study

    Directory of Open Access Journals (Sweden)

    Luciana Dutra-Thomé

    2011-09-01

    Full Text Available The present article focused on the perception of sexual exploitation as a job, using a single case study design. The aim of the study was to investigate the case of a 14 year-old girl, involved in commercial sexual exploitation, who considered this situation as her labor activity. A content analysis showed protective and risk factors as categories, especially related to her labor activities. The girl perceived the sexual exploitation activity as a job that provided autonomy, subsistence, and survival. The study revealed that the negative effects of working during adolescence may bring consequences to health and development. Youth work may be defined as a risk factor, especially when the labour conditions are not adequate and protected.

  11. Teotihuacan, tepeapulco, and obsidian exploitation.

    Science.gov (United States)

    Charlton, T H

    1978-06-16

    Current cultural ecological models of the development of civilization in central Mexico emphasize the role of subsistence production techniques and organization. The recent use of established and productive archeological surface survey techniques along natural corridors of communication between favorable niches for cultural development within the Central Mexican symbiotic region resulted in the location of sites that indicate an early development of a decentralized resource exploitation, manufacturing, and exchange network. The association of the development of this system with Teotihuacán indicates the importance such nonsubsistence production and exchange had in the evolution of this first central Mexican civilization. The later expansion of Teotihuacán into more distant areas of Mesoamerica was based on this resource exploitation model. Later civilizations centered at Tula and Tenochtitlán also used such a model in their expansion.

  12. Network exploitation using WAMI tracks

    Science.gov (United States)

    Rimey, Ray; Record, Jim; Keefe, Dan; Kennedy, Levi; Cramer, Chris

    2011-06-01

    Creating and exploiting network models from wide area motion imagery (WAMI) is an important task for intelligence analysis. Tracks of entities observed moving in the WAMI sensor data are extracted, then large numbers of tracks are studied over long time intervals to determine specific locations that are visited (e.g., buildings in an urban environment), what locations are related to other locations, and the function of each location. This paper describes several parts of the network detection/exploitation problem, and summarizes a solution technique for each: (a) Detecting nodes; (b) Detecting links between known nodes; (c) Node attributes to characterize a node; (d) Link attributes to characterize each link; (e) Link structure inferred from node attributes and vice versa; and (f) Decomposing a detected network into smaller networks. Experimental results are presented for each solution technique, and those are used to discuss issues for each problem part and its solution technique.

  13. A Class-F CMOS Oscillator

    NARCIS (Netherlands)

    Babaie, M.; Staszewski, R.B.

    2013-01-01

    An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC

  14. Development of a CMOS MEMS pressure sensor with a mechanical force-displacement transduction structure

    International Nuclear Information System (INIS)

    Cheng, Chao-Lin; Chang, Heng-Chung; Fang, Weileun; Chang, Chun-I

    2015-01-01

    This study presents a capacitive pressure sensor with a mechanical force-displacement transduction structure based on the commercially available standard CMOS process (the TSMC 0.18 μm 1P6M CMOS process). The pressure sensor has a deformable diaphragm to support a movable plate with an embedded sensing electrode. As the diaphragm is deformed by the ambient pressure, the movable plate and its embedded sensing electrode are displaced. Thus, the pressure is detected from the capacitance change between the movable and fixed electrodes. The undeformed movable electrode will increase the effective sensing area between the sensing electrodes, thereby improving the sensitivity. Experimental results show that the proposed pressure sensor with a force-displacement transducer will increase the sensitivity by 126% within the 20 kPa–300 kPa absolute pressure range. Moreover, this study extends the design to add pillars inside the pressure sensor to further increase its sensing area as well as sensitivity. A sensitivity improvement of 117% is also demonstrated for a pressure sensor with an enlarged sensing electrode (the overlap area is increased two fold). (paper)

  15. Design and Characterization of a Built-In CMOS TID Smart Sensor

    Science.gov (United States)

    Agustin, Javier; Gil, Carlos; Lopez-Vallejo, Marisa; Ituero, Pablo

    2015-04-01

    This paper describes a total ionization dose (TID) sensor that presents the following advantages: it is a digital sensor able to be integrated in CMOS circuits; it has a configurable sensitivity that allows radiation doses ranging from very low to high levels; its interface helps to integrate this design in a multidisciplinary sensor network; and it is self-timed, hence it does not need a clock signal. We designed, implemented and manufactured the sensor in a 0.35 μm CMOS commercial technology. It was irradiated with a 60Co source. This test was used to characterize the sensor in terms of the radiation response up to 575 krad. After irradiation, we monitored the sensor to control charge redistribution and annealing effects for 80 hours. We also exposed our design to meticulous temperature analysis from 0 to 50°C and we studied the acceleration on the annealing phenomena due to high temperatures. Sensor calibration takes into account the results of all tests. Finally we propose to use this sensor in a self-recovery system. The sensor manufactured in this work has an area of 0.047 mm 2, of which 22% is dedicated to measuring radiation. Its energy per conversion is 463 pJ.

  16. A large dynamic range radiation-tolerant analog memory in a quarter- micron CMOS technology

    CERN Document Server

    Anelli, G; Rivetti, A

    2001-01-01

    An analog memory prototype containing 8*128 cells has been designed in a commercial quarter-micron CMOS process. The aim of this work is to investigate the possibility of designing large dynamic range mixed-mode switched capacitor circuits for high-energy physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant. The memory cells employ gate-oxide capacitors for storage, permitting a very high density. A voltage write-voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (the power supply voltage V/sub DD/ is equal to 2.5 V), with a linearity of almost 8 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is +or-0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after 1...

  17. A large dynamic range radiation tolerant analog memory in a quarter micron CMOS technology

    CERN Document Server

    Anelli, G; Rivetti, A

    2000-01-01

    A 8*128 cell analog memory prototype has been designed in a commercial 0.25 jam CMOS process. The aim of this work was to investigate the possibility of designing large dynamic range mixed- mode switched capacitor circuits for High-Energy Physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant left bracket 1 right bracket . The memory cells employ gate-oxide capacitors for storage, allowing for a very high density. A voltage write - voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (V//D//D = 2.5 V), with a linearity of at least 7.5 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is plus or minus 0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after lOMrd (...

  18. Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

    Science.gov (United States)

    Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

    2008-02-01

    Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

  19. A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    Energy Technology Data Exchange (ETDEWEB)

    Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua, E-mail: gaoleisheng@ime.ac.c [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2010-08-15

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 {mu}m CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 {mu}m{sup 2}. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

  20. A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    International Nuclear Information System (INIS)

    Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua

    2010-01-01

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 μm CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 μm 2 . Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

  1. Simulation of SEU transients in CMOS ICs

    International Nuclear Information System (INIS)

    Kaul, N.; Bhuva, B.L.; Kerns, S.E.

    1991-01-01

    This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE

  2. Fast Hopping Frequency Generation in Digital CMOS

    CERN Document Server

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  3. A New CMOS Posicast Pre-shaper for Vibration Reduction of CMOS Op-Amps

    Science.gov (United States)

    Rasoulzadeh, M.; Ghaznavi-Ghoushchi, M. B.

    2010-06-01

    Posicast-based control is a widely used method in vibration reduction of lightly damped oscillatory systems especially in mechanical fields. The target systems to apply Posicast method are the systems which are excited by pulse inputs. Using the Posicast idea, the input pulse is reshaped into a new pulse, which is called Posicast pulse. Applying the generated Posicast pulse reduces the undesired oscillatory manner of under-test systems. In this paper, a fully CMOS Pulse pre-shaper circuit for realization of Posicast command is proposed. Our design is based on delay-and-add approach for the incoming pulses. The delay is done via a modified Schmitt Trigger-like circuit. The adder circuit is implemented by a simple non-binary analog adder terminated by a passive element. Our proposed design has a reasonable flexibility in configuration of time delay and amplitude of the desired pulse-like shapes. The delay is controlled via the delay unit and the pre-shaped pulse's amplitudes are controlled by an analog adder unit. The overall system has 18 MOS transistors, one small capacitor, and one resistor. To verify the effectiveness of the recommended method, it is experienced on a real CMOS Op-Amp. HSPICE simulation results, on 0.25u technology, show a significant reduction on overshoot and settling time of the under-test Op-Amp. The mentioned reduction is more than 95% in overshoot and more than 60% in settling time of the system.

  4. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  5. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  6. CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

    National Research Council Canada - National Science Library

    An, S

    2001-01-01

    .... Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step...

  7. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    Science.gov (United States)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  8. Characterization of active CMOS pixel sensors on high resistive substrate

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Bonn (Germany)

    2016-07-01

    Active CMOS pixel sensors are very attractive as radiation imaging pixel detector because they do not need cost-intensive fine pitch bump bonding. High radiation tolerance and time resolution are required to apply those sensors to upcoming particle physics experiments. To achieve these requirements, the active CMOS pixel sensors were developed on high resistive substrates. Signal charges are collected faster by drift in high resistive substrates than in standard low resistive substrates yielding also a higher radiation tolerance. A prototype of the active CMOS pixel sensor has been fabricated in the LFoundry 150 nm CMOS process on 2 kΩcm substrate. This prototype chip was thinned down to 300 μm and the backside has been processed and can contacted by an aluminum contact. The breakdown voltage is around -115 V, and the depletion width has been measured to be as large as 180 μm at a bias voltage of -110 V. Gain and noise of the readout circuitry agree with the designed values. Performance tests in the lab and test beam have been done before and after irradiation with X-rays and neutrons. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  9. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  10. CMOS Cell Sensors for Point-of-Care Diagnostics

    Science.gov (United States)

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  11. The ESA Geohazard Exploitation Platform

    Science.gov (United States)

    Bally, Philippe; Laur, Henri; Mathieu, Pierre-Philippe; Pinto, Salvatore

    2015-04-01

    Earthquakes represent one of the world's most significant hazards in terms both of loss of life and damages. In the first decade of the 21st century, earthquakes accounted for 60 percent of fatalities from natural disasters, according to the United Nations International Strategy for Disaster Reduction (UNISDR). To support mitigation activities designed to assess and reduce risks and improve response in emergency situations, satellite EO can be used to provide a broad range of geo-information services. This includes for instance crustal block boundary mapping to better characterize active faults, strain rate mapping to assess how rapidly faults are deforming, soil vulnerability mapping to help estimate how the soil is behaving in reaction to seismic phenomena, geo-information to assess the extent and intensity of the earthquake impact on man-made structures and formulate assumptions on the evolution of the seismic sequence, i.e. where local aftershocks or future main shocks (on nearby faults) are most likely to occur. In May 2012, the European Space Agency and the GEO Secretariat convened the International Forum on Satellite EO for Geohazards now known as the Santorini Conference. The event was the continuation of a series of international workshops such as those organized by the Geohazards Theme of the Integrated Global Observing Strategy Partnership. In Santorini the seismic community has set out a vision of the EO contribution to an operational global seismic risk program, which lead to the Geohazard Supersites and Natural Laboratories (GSNL) initiative. The initial contribution of ESA to suuport the GSNL was the first Supersites Exploitation Platform (SSEP) system in the framework of Grid Processing On Demand (GPOD), now followed by the Geohazard Exploitation Platform (GEP). In this presentation, we will describe the contribution of the GEP for exploiting satellite EO for geohazard risk assessment. It is supporting the GEO Supersites and has been further

  12. Total exploitation of an ornamental granite quarry

    Directory of Open Access Journals (Sweden)

    Taboada, J.

    2005-09-01

    Full Text Available In this paper we propose a methodology to estimate the recovery percentage for each of the products which can be obtained from the exploitation of an ornamental granite quarry: block, semiblock, masonry-transverse stone, and the smaller materials that can be used to obtain construction aggregates. This methodology ensures that quarry exploitation is exhaustive, thereby minimising the production of spoils and the consequent negative impact on the environment. The analysis is based on a detailed and exhaustive compilation of discontinuity data from the research fronts, which are then interpreted statistically and projected over the three weakness planes that are a particular feature of ornamental granite deposits. Using this information, and bearing in mind the minimum commercially viable sizes for each kind of granite, the corresponding recovery rates are calculated for each material in each plane. The results are then integrated using spatial techniques, and the result is an evaluation of quarry contents with a view to total exploitation. This methodology was applied to a quarry in the opening phase in order to carry out an a priori assessment of the economic feasibility of the quarry.

    En este trabajo se propone una metodología para estimar el porcentaje de recuperación de cada uno de los productos que se pueden obtener en la explotación de una cantera de granito ornamental: bloque, semibloque, manpostería y per piaños, y material restante destinado a la obtención de áridos. De esta manera se logra un aprovechamiento integral de la cantera, evitándose la generación de estériles y el subsiguiente impacto ambiental producido por éstos. La metodología de análisis se basa en la recopilación detallada y exhaustiva de datos de discontinuidades en los frentes de investigación, que se interpretan estadísticamente y se proyectan sobre los tres planos de debilidad propios del granito ornamental. Con esta información, y las

  13. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Science.gov (United States)

    2012-05-07

    ... INTERNATIONAL TRADE COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products.... International Trade Commission has received a complaint entitled Certain CMOS Image Sensors and Products... importation, and the sale within the United States after importation of certain CMOS image sensors and...

  14. Electromagnetic Investigation of a CMOS MEMS Inductive Microphone

    Directory of Open Access Journals (Sweden)

    Farès TOUNSI

    2009-09-01

    Full Text Available This paper presents a detailed electromagnetic modeling for a new structure of a monolithic CMOS micromachined inductive microphone. We have shown, that the use of an alternative current (AC in the primary fixed inductor results in a substantially higher induced voltage in the secondary inductor comparing to the case when a direct current (DC is used. The expected increase of the induced voltage can be expressed by a voltage ratio of AC and DC solutions that is in the range of 3 to 6. A prototype fabrication of this microphone has been realized using a combination of standard CMOS 0.6 µm process with a CMOS-compatible post-process consisting in a bulk micromachining technology. The output voltage of the electrodynamic microphone that achieves the µV range can be increased by the use of the symmetric dual-layer spiral inductor structure.

  15. Small Pixel Hybrid CMOS X-ray Detectors

    Science.gov (United States)

    Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

    2018-01-01

    Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

  16. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  17. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  18. High-speed nonvolatile CMOS/MNOS RAM

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

    1979-01-01

    A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

  19. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2014-05-01

    Full Text Available This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  20. A CMOS humidity sensor for passive RFID sensing applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-05-16

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  1. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    Science.gov (United States)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  2. Analysis and simulation of HV-CMOS assemblies for the CLIC vertex detector

    CERN Document Server

    Buckland, Matthew Daniel

    2017-01-01

    One of the design concepts currently under study for the vertex detector at the proposed Compact Linear Collider is a High-Voltage CMOS sensor, fabricated in a commercial 180 nm technology, capacitively coupled to a hybrid readout chip. Tests of the assemblies were carried out at the CERN SPS using 120 GeV/c pions, covering incident angles ranging from 0$^\\circ$ to 80$^\\circ$. The measurements have shown an excellent tracking performance with an efficiency above 99.7% and a spatial resolution of 5–7 $\\mu$m over the tested angular range. These results were then compared to TCAD simulations carried out using simulations, showing a good agreement for the current-voltage, breakdown and charge collection properties. The simulations have also been used to optimise future sensor design.

  3. E-Beam Effects on CMOS Active Pixel Sensors

    International Nuclear Information System (INIS)

    Kang, Dong Ook; Jo, Gyu Seong; Kim, Hyeon Daek; Kim, Hyunk Taek; Kim, Jong Yeol; Kim, Chan Kyu

    2011-01-01

    Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co 60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

  4. Commercial Banks

    Directory of Open Access Journals (Sweden)

    Abbas Asosheh

    2009-09-01

    Full Text Available Information systems outsourcing issues has been attracted in recent years because many information systems projects in organizations are done in this case. On the other hand, failure rate of this kind of projects is also high. The aim of this article is to find success factors in risk management of information systems outsourcing in commercial banks using these factors leads to increase the success rate of risk management of information systems outsourcing projects. Research methods in the present article based on purpose are applied and descriptive- survey. In addition, research tool is questionnaire which was used among commercial bank experts. For this purpose, First information systems outsourcing risks were identified and then ranked. In the next step, the information systems outsourcing reasons were surveyed and the most important reasons were identified. Then the risks which have not any relationship with the most important reasons were removed and success factors in managing residual risks were extracted.

  5. An introduction to deep submicron CMOS for vertex applications

    CERN Document Server

    Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

    2001-01-01

    Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

  6. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  7. A 205GHz Amplifier in 90nm CMOS Technology

    Science.gov (United States)

    2017-03-01

    10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...other advantages, such as low- cost , reliability, and mixed-mode analog/digital chips, intensifying its usage in the mm-wave band [5]. CMOS has several... disadvantages at the higher frequency range with the worst case scenario happening when the device operates near its fmax. This is chiefly due to

  8. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  9. Two CMOS BGR using CM and DTMOST techniques

    International Nuclear Information System (INIS)

    Mohd-Yasin, F.; Teh, Y.K.; Choong, F.; Reaz, M.B.I.

    2009-06-01

    Two CMOS BGR using current mode (0.044mm 2 ) and Dynamic Threshold MOST (0.017mm 2 ) techniques are designed on CMOS 0.18μm process. On-wafer measurement shows both circuits have minimum operating V DD 1.28V at 25 o C; taking 2.1μA and 0.5μA (maximum current 3.1μA and 1.1μA) and output voltage of 514mV and 457mV. Both circuits could support V DD range up to 4V required by passive UHF RFID. (author)

  10. Linear CMOS RF power amplifiers a complete design workflow

    CERN Document Server

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  11. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  12. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  13. A new measure of interpersonal exploitativeness

    Directory of Open Access Journals (Sweden)

    Amy B. Brunell

    2013-05-01

    Full Text Available Measures of exploitativeness evidence problems with validity and reliability. The present set of studies assessed a new measure (the Interpersonal Exploitativeness Scale that defines exploitativeness in terms of reciprocity. In Studies 1 and 2, 33 items were administered to participants. Exploratory and Confirmatory Factor Analysis demonstrated that a single factor consisting of six items adequately assess interpersonal exploitativeness. Study 3 results revealed that the Interpersonal Exploitativeness Scale was positively associated with normal narcissism, pathological narcissism, psychological entitlement, and negative reciprocity and negatively correlated with positive reciprocity. In Study 4, participants competed in a commons dilemma. Those who scored higher on the Interpersonal Exploitativeness Scale were more likely to harvest a greater share of resources over time, even while controlling for other relevant variables, such as entitlement. Together, these studies show the Interpersonal Exploitativeness Scale to be a valid and reliable measure of interpersonal exploitativeness. The authors discuss the implications of these studies.

  14. Exploitation in International Paid Surrogacy Arrangements

    OpenAIRE

    Wilkinson, Stephen

    2015-01-01

    Abstract Many critics have suggested that international paid surrogacy is exploitative. Taking such concerns as its starting point, this article asks: (1) how defensible is the claim that international paid surrogacy is exploitative and what could be done to make it less exploitative? (2) In the light of the answer to (1), how strong is the case for prohibiting it? Exploitation could in principle be dealt with by improving surrogates' pay and conditions. However, doing so may exacerbate probl...

  15. Fostering the Exploitation of Open Educational Resources

    Directory of Open Access Journals (Sweden)

    Thomas Richter

    2014-07-01

    Full Text Available The central concept behind Open Educational Resources (OER is opening up the access to educational resources for stakeholders who are not the usual target user group. This concept must be perceived as innovative because it describes a general economic and social paradigm shift: Education, which formerly was limited to a specific group of learners, now, is promoted as a public good. However, despite very good intentions, internationally agreed quality standards, and the availability of the required technological infrastructure, the critical threshold is not yet met. Due to several reasons, the usefulness of OER is often limited to the originally targeted context. Questions arise if the existing quality standards for Technology Enhanced Learning (TEL actually meet the specific requirements within the OER value chain, if the existing quality standards are applicable to OER in a meaningful way, and under which conditions related standards generally could support the exploitation of OER.We analyze quality standards for TEL and contrast the life cycle model of commercial learning resources against the life cycle model of OER. We investigate special demands on quality from the context of OER and, taking the former results into account, derive emergent quality criteria for OER. The paper concludes with recommendations for the design of OER and a future standard development.

  16. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  17. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  18. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    Science.gov (United States)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  19. The Exploitation of Evolving Resources

    CERN Document Server

    McGlade, Jacqueline; Law, Richard

    1993-01-01

    The impact of man on the biosphere is profound. Quite apart from our capacity to destroy natural ecosystems and to drive species to extinction, we mould the evolution of the survivors by the selection pressures we apply to them. This has implications for the continued health of our natural biological resources and for the way in which we seek to optimise yield from those resources. Of these biological resources, fish stocks are particularly important to mankind as a source of protein. On a global basis, fish stocks provide the major source of protein for human consumption from natural ecosystems, amounting to some seventy million tonnes in 1970. Although fisheries management has been extensively developed over the last century, it has not hitherto considered the evolutionary consequences of fishing activity. While this omission may not have been serious in the past, the ever increasing intensity of exploitation and the deteriorating health of fish stocks has generated an urgent need for a better understanding...

  20. Swedish mines. Underground exploitation methods

    International Nuclear Information System (INIS)

    Paucard, A.

    1960-01-01

    Between 1949 and 1957, 10 engineers of the Mining research and exploitation department of the CEA visited 17 Swedish mines during 5 field trips. This paper presents a compilation of the information gathered during these field trips concerning the different underground mining techniques used in Swedish iron mines: mining with backfilling (Central Sweden and Boliden mines); mining without backfilling (mines of the polar circle area). The following techniques are described successively: pillar drawing and backfilled slices (Ammeberg, Falun, Garpenberg, Boliden group), sub-level pillar drawing (Grangesberg, Bloettberget, Haeksberg), empty room and sub-level pillar drawing (Bodas, Haksberg, Stripa, Bastkarn), storage chamber pillar drawing (Bodas, Haeksberg, Bastkarn), and pillar drawing by block caving (ldkerberget). Reprint of a paper published in Revue de l'Industrie Minerale, vol. 41, no. 12, 1959 [fr

  1. Exploiting social evolution in biofilms

    DEFF Research Database (Denmark)

    Boyle, Kerry E; Heilmann, Silja; van Ditmarsch, Dave

    2013-01-01

    Bacteria are highly social organisms that communicate via signaling molecules, move collectively over surfaces and make biofilm communities. Nonetheless, our main line of defense against pathogenic bacteria consists of antibiotics-drugs that target individual-level traits of bacterial cells...... and thus, regrettably, select for resistance against their own action. A possible solution lies in targeting the mechanisms by which bacteria interact with each other within biofilms. The emerging field of microbial social evolution combines molecular microbiology with evolutionary theory to dissect...... the molecular mechanisms and the evolutionary pressures underpinning bacterial sociality. This exciting new research can ultimately lead to new therapies against biofilm infections that exploit evolutionary cheating or the trade-off between biofilm formation and dispersal....

  2. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  3. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  4. Photon imaging using post-processed CMOS chips

    NARCIS (Netherlands)

    Melai, J.

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic

  5. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...

  6. Integrated imaging sensor systems with CMOS active pixel sensor technology

    Science.gov (United States)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  7. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2017-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  8. A CMOS rail-to-rail linear VI-converter

    NARCIS (Netherlands)

    Vervoort, P.P.; Vervoort, P.P.; Wassenaar, R.F.

    1995-01-01

    A linear CMOS VI-converter operating in strong inversion with a common-mode input range from the negative to the positive supply rail is presented. The circuit consists of three linear VI-converters based on the difference of squares principle. Two of these perform the actual V to I conversion,

  9. An efficient CMOS bridging fault simulator with SPICE accuracy

    NARCIS (Netherlands)

    Di, C.; Jess, J.A.G.

    1996-01-01

    This paper presents an alternative modeling and simulation method for CMOS bridging faults. The significance of the method is the introduction of a set of generic-bridge tables which characterize the bridged outputs for each bridge and a set of generic-cell tables which characterize how each cell

  10. Characterisation of a CMOS charge transfer device for TDI imaging

    International Nuclear Information System (INIS)

    Rushton, J.; Holland, A.; Stefanov, K.; Mayer, F.

    2015-01-01

    The performance of a prototype true charge transfer imaging sensor in CMOS is investigated. The finished device is destined for use in TDI applications, especially Earth-observation, and to this end radiation tolerance must be investigated. Before this, complete characterisation is required. This work starts by looking at charge transfer inefficiency and then investigates responsivity using mean-variance techniques

  11. Radiation response of high speed CMOS integrated circuits

    International Nuclear Information System (INIS)

    Yue, H.; Davison, D.; Jennings, R.F.; Lothongkam, P.; Rinerson, D.; Wyland, D.

    1987-01-01

    This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis

  12. A toroidal inductor integrated in a standard CMOS process

    DEFF Research Database (Denmark)

    Vandi, Luca; Andreani, Pietro; Temporiti, Enrico

    2007-01-01

    This paper presents a toroidal inductor integrated in a standard 0.13 um CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches...

  13. Design for manufacturability and yield for nano-scale CMOS

    CERN Document Server

    Chiang, Charles C

    2007-01-01

    Talks about the various aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells. This book is suitable for practicing IC designer and for graduate students intent on having a career in IC design or in EDA tool development.

  14. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    CERN Document Server

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  15. First experimental results on CMOS Integrated Nickel Electroplated Resonators

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Hansen, Ole

    2004-01-01

    This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation of the electri...

  16. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  17. CMOS-based avalanche photodiodes for direct particle detection

    International Nuclear Information System (INIS)

    Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

    2007-01-01

    Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

  18. Temperature Sensors Integrated into a CMOS Image Sensor

    NARCIS (Netherlands)

    Abarca Prouza, A.N.; Xie, S.; Markenhof, Jules; Theuwissen, A.J.P.

    2017-01-01

    In this work, a novel approach is presented for measuring relative temperature variations inside the pixel array of a CMOS image sensor itself. This approach can give important information when compensation for dark (current) fixed pattern noise (FPN) is needed. The test image sensor consists of

  19. High-temperature complementary metal oxide semiconductors (CMOS)

    International Nuclear Information System (INIS)

    McBrayer, J.D.

    1979-10-01

    Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300 0 C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed

  20. A CMOS image sensor with row and column profiling means

    NARCIS (Netherlands)

    Xie, N.; Theuwissen, A.J.P.; Wang, X.; Leijtens, J.A.P.; Hakkesteegt, H.; Jansen, H.

    2008-01-01

    This paper describes the implementation and firstmeasurement results of a new way that obtains row and column profile data from a CMOS Image Sensor, which is developed for a micro-Digital Sun Sensor (μDSS).The basic profiling action is achieved by the pixels with p-type MOS transistors which realize

  1. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    Science.gov (United States)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  2. Design of a CMOS temperature sensor with current output

    NARCIS (Netherlands)

    Kolling, A.; Kölling, Arjan; Bak, Frans; Bergveld, Piet; Seevinck, E.; Seevinck, Evert

    1990-01-01

    In this paper a CMOS temperature-to-current converter is presented of which the output current is the difference between a PTC current and an NTC current. The PTC current is derived from a PTAT cell, while the NTC current is derived from a threshold voltage reference source. It is shown that this

  3. A CMOS four-quadrant analog current multiplier

    NARCIS (Netherlands)

    Wiegerink, Remco J.

    1991-01-01

    A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual

  4. HYBRID SILICON-ON-SAPPHIRE/SCALED CMOS INTERFERENCE MITIGATION FRONT END BASED ON SIMULTANEOUS NOISE CANCELLATION, ACTIVE-INTERFERENCE CANCELLATION AND N-PATH-MIXER FILTERING

    Science.gov (United States)

    2017-04-01

    supported under the RF focal plane gate array (FPGA) program, SOS CMOS in conjunction with series stacking of devices is exploited to enable...OOB IIP3 of +7 and +17.5dBm respectively. The clock path direct current (DC) power consumption at 700MHz is 90mW from a 1.2V supply. The proposed...the circulator architecture to enhance the TX-RX isolation and track ANT variations. These innovations (i) lower the overall power consumption due

  5. Industry's Commercial Initiatives on ISS

    Science.gov (United States)

    Shields, C. E.; Kessler, C.; Lavitola, M. S.

    2002-01-01

    For more than ten years, private industry has worked to develop a commercial human space market and to create a sustainable ISS commercial utilization customer base. Before ISS assembly was underway - and long before NASA and the international space agencies began to craft ISS commercial business terms and conditions - industry planted and nurtured the seeds of interest in exploiting human space utilization for commerce. These early initiatives have yielded the impetus and framework for industry approaches to ISS commercial utilization today and for NASA's and the International Partners' planned accommodation of private sector interests and desires on the ISS. This paper chronicles major industry initiatives for commercial ISS utilization, emphasizing successful marketing and business approaches and why these approaches have a higher likelihood of success than others. It provides an overview of individual companies' initiatives, as well as collaborative efforts that cross company lines and country borders; and it assesses the relative success of each. Rather than emphasize negative issues and barriers, this paper characterizes and prioritizes actionable success factors for industry and government to make ISS commercial utilization a sustainable reality.

  6. A novel multi-actuation CMOS RF MEMS switch

    Science.gov (United States)

    Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

    2008-12-01

    This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

  7. Photon detection with CMOS sensors for fast imaging

    International Nuclear Information System (INIS)

    Baudot, J.; Dulinski, W.; Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N.

    2009-01-01

    Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e - , and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100μs have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

  8. Contact CMOS imaging of gaseous oxygen sensor array.

    Science.gov (United States)

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  9. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    Directory of Open Access Journals (Sweden)

    Mohammad Reza Shokrani

    2014-01-01

    Full Text Available This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  10. An economic comparison of the commercial and recreational ...

    African Journals Online (AJOL)

    The most important Namibian linefish species, the silver kob Argyrosomus inodorus, is currently heavily exploited, and in order to ensure its survival catch restrictions are being introduced. However, kob are exploited both by recreational anglers and by commercial vessels, and it is important to examine the economics of ...

  11. Exploiting Symmetry on Parallel Architectures.

    Science.gov (United States)

    Stiller, Lewis Benjamin

    1995-01-01

    This thesis describes techniques for the design of parallel programs that solve well-structured problems with inherent symmetry. Part I demonstrates the reduction of such problems to generalized matrix multiplication by a group-equivariant matrix. Fast techniques for this multiplication are described, including factorization, orbit decomposition, and Fourier transforms over finite groups. Our algorithms entail interaction between two symmetry groups: one arising at the software level from the problem's symmetry and the other arising at the hardware level from the processors' communication network. Part II illustrates the applicability of our symmetry -exploitation techniques by presenting a series of case studies of the design and implementation of parallel programs. First, a parallel program that solves chess endgames by factorization of an associated dihedral group-equivariant matrix is described. This code runs faster than previous serial programs, and discovered it a number of results. Second, parallel algorithms for Fourier transforms for finite groups are developed, and preliminary parallel implementations for group transforms of dihedral and of symmetric groups are described. Applications in learning, vision, pattern recognition, and statistics are proposed. Third, parallel implementations solving several computational science problems are described, including the direct n-body problem, convolutions arising from molecular biology, and some communication primitives such as broadcast and reduce. Some of our implementations ran orders of magnitude faster than previous techniques, and were used in the investigation of various physical phenomena.

  12. Gun muzzle flash detection using a single photon avalanche diode array in 0.18µm CMOS technology

    Science.gov (United States)

    Savuskan, Vitali; Jakobson, Claudio; Merhav, Tomer; Shoham, Avi; Brouk, Igor; Nemirovsky, Yael

    2015-05-01

    In this study, a CMOS Single Photon Avalanche Diode (SPAD) 2D array is used to record and sample muzzle flash events in the visible spectrum, from representative weapons. SPADs detect the emission peaks of alkali salts, potassium or sodium, with spectral emission lines around 769nm and 589nm, respectively. The alkali salts are included in the gunpowder to suppress secondary flashes ignited during the muzzle flash event. The SPADs possess two crucial properties for muzzle flash imaging: (i) very high photon detection sensitivity, (ii) a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. The sole noise sources are the ones prior to the readout circuitry (optical signal distribution, avalanche initiation distribution and nonphotonic generation). This enables high sampling frequencies in the kilohertz range without significant SNR degradation, in contrast to regular CMOS image sensors. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength, in the presence of sunlight. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics and signal processing, which will be reported. The frame rate of ~16 KHz was chosen as an optimum between SNR degradation and temporal profile recognition accuracy. In contrast to a single SPAD, the 2D array allows for multiple events to be processed simultaneously. Moreover, a significant field of view is covered, enabling comprehensive surveillance and imaging.

  13. Two questions about surrogacy and exploitation.

    Science.gov (United States)

    Wertheimer, Alan

    1992-01-01

    In this article I will consider two related questions about surrogacy and exploitation: (1) Is surrogacy exploitative? (2) If surrogacy is exploitative, what is the moral force of this exploitation? Briefly stated, I shall argue that whether surrogacy is exploitative depends on whether exploitation must be harmful to the exploited party or whether (as I think) there can be mutually advantageous exploitation. It also depends on some facts about surrogacy about which we have little reliable evidence and on our philosophical view on what counts as a harm to the surrogate. Our answer to the second question will turn in part on the account of exploitation we invoke in answering the first question and in part on the way in which we resolve some other questions about the justification of state interference. I shall suggest, however, that if surrogacy is a form of voluntary and mutually advantageous exploitation, then there is a strong presumption that surrogacy contracts should be permitted and even enforceable, although that presumption may be overridden on other grounds.

  14. Charged particle detection performances of CMOS pixel sensors produced in a 0.18 um process with a high resistivity epitaxial layer

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Gilles; Cousin, Loic; Dorokhov, Andrei; Dulinski, Wojciech; Goffe, Mathieu; Hu-Guo, Christine; Winter, Marc

    2013-01-01

    The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 um thin CMOS Pixel Sensors (CPS) covering either the 3 innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 um CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJa...

  15. Fishery Development and Exploitation in South East Australia

    Directory of Open Access Journals (Sweden)

    Camilla Novaglio

    2018-04-01

    Full Text Available Understanding the full extent of past ecological changes in human-influenced marine systems is needed to inform present management policies, but is often hampered by the scarcity of information about exploitation practices and population status over the entire history of fishing. The history of commercial fishing in South East Australia is relatively recent and thus easier to document. Our aim is to reconstruct such history and to use this information to understand general patterns and consequences of fishing exploitation. Intense exploitation of marine resources arrived in South East Australia with European colonization in the early 1800s, and unregulated sealing, whaling and oyster dredging resulted in the first documented significant impact on local marine populations. Exploitation extended to demersal resources in 1915 when the trawl fishery developed. Between the early 1800s and the 1980s, some of the exploited stocks collapsed, but fishing moved further offshore and in deeper waters as technology improved and new resources became available or were discovered. This phase of fisheries expansion masked the unsustainable nature of some fishing industries, such as trawling and whaling, and postponed the need for management regulations. From the 1990s onward, an increasing awareness of the depleted nature of some fisheries led to the establishment of management strategies aiming at a more sustainable exploitation of target stocks and, from the mid-2000s onwards, management strategies were revised and improved to better address the effect of fishing on multiple components of marine ecosystems. This led to the recovery of some depleted populations and to increased habitat protection. The relatively short history of fishing exploitation and the small scale of the fishing industry in South East Australia played a significant role in limiting the magnitude of fishing impacts on local populations and helped to achieve recoveries when fisheries

  16. A 32-channels, 025 mu m CMOS ASIC for the readout of the Silicon Drift Detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anelli, G; Anghinolfi, F; Martínez, M I; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the Silicon Drift Detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same chip 32 transimpedance amplifiers, a 32*256 cells analogue memory and 16 successive approximation 10 bit A /D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way; when an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial. 0.25 mu m CMOS technology. It has been extensively tested both on a bench and connected with the detector in several beam tests. In this paper both design issues and test results are presented. The commercial technology used for the design has been yield radiation tolerant with special layout techniques. Total dose irradiation tests are also presented. (13 refs).

  17. The strv 1 microsatellite semes: Exploiting the geosynchronous transfer orbit

    Science.gov (United States)

    Blott, R. J.; Wells, N. S.; Eves, J.

    Following 3 successful years in orbit, the UK Defence Evaluation and Research Agency's two Space Technology Research Vehicle microsatellites (STRV) 1 a&b will be followed by a second mission. STRV 1 c&d are now in construction for a planned launch in 1999. The new mission, which includes 22 experimental payloads and developmental spacecraft bus technologies from European, US and Canadian military, civil and commercial sponsors, exploits the Geosynchronous Transfer Orbit (GTO) to offer an affordable, working space research tool for both government and industry. The STRV 1 programme objective is to promote the enhancement of military and civil space communications, remote sensing and navigation capabilities at reduced cost and risk. Additional aims are to help industry to achieve commercial benefit from investment in emerging technologies and to develop the synergy between government, commercial and civilian space applications. The paper explains how STRV 1 exploits the variable altitude and high radiation environment of GTO to investigate the performance of emerging technologies and techniques. This includes the accelerated life testing of components and materials, such as infra-red detectors, advanced microprocessors and solar cell technologies, and the prototyping of new techniques to improve communications and spacecraft autonomy. Experiments include implementing a secure version of the Consultative Committee for Space Data Systems (CCSDS) packet telecommand and telemetry standards, further development of the Internet-based Space Communication Protocol Standards (SCPS) and evaluating the exploitation of the Global Positioning System (GPS) in geosynchronous orbit. The new mission also builds on and extends the comprehensive environmental monitoring achieved by STRV 1 a&b.

  18. A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

    International Nuclear Information System (INIS)

    Han Kefeng; Cao Shengguo; Tan Xi; Yan Na; Wang Junyu; Tang Zhangwen; Min Hao

    2010-01-01

    A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 x 0.55 mm 2 . System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader. (semiconductor integrated circuits)

  19. Studies of the LBL CMOS integrated amplifier/discriminator for randomly timed inputs from fixed target experiments

    International Nuclear Information System (INIS)

    Russ, J.S.; Yarema, R.J.; Zimmerman, T.

    1988-12-01

    A group at Lawrence Berkeley Laboratory has reported an elegant CMOS VLSI circuit for amplifying, discriminating, and encoding the signals from highly-segmented charge output devices, e.g., silicon strip detectors or pad readout structures in gaseous detectors. The design exploits switched capacitor circuits and the well-known time structure of data acquisition in colliding beam accelerators to cancel leakage effects and switching noise. For random inputs, these methods are not directly applicable. However, the high speed of the reset switches makes possible a mode of operation for fixed target experiments that uses fast resets to erase unwanted data from random triggers. Data acquisition in this mode has been performed. Details of operation and measurements of noise and rate capability will be presented. 8 refs., 6 figs

  20. A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

    Energy Technology Data Exchange (ETDEWEB)

    Han Kefeng; Cao Shengguo; Tan Xi; Yan Na; Wang Junyu; Tang Zhangwen; Min Hao, E-mail: tanxi@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-12-15

    A two-stage differential linear power amplifier (PA) fabricated by 0.18 {mu}m CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 x 0.55 mm{sup 2}. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader. (semiconductor integrated circuits)

  1. Radiation environmental impact assessment of copper exploitation

    International Nuclear Information System (INIS)

    Fan Guang; Wen Zhijian

    2010-01-01

    The radiation environmental impact of mineral exploitation on the surrounding environment has become a public concern. This paper presents the radiation environmental impact assessment of copper exploitation. Based on the project description and detailed investigations of surrounding environment, systematic radiation environmental impacts have been identified. The environmental impacts are assessed during both construction and operation phase. The environmental protection measures have also been proposed. The related conclusion and measures can play an active role in copper exploitation and environmental protection. (authors)

  2. Exploitation and exploration dynamics in recessionary times

    OpenAIRE

    Walrave, B.

    2012-01-01

    Firm performance largely depends on the ability to adapt to, and exploit, changes in the business environment. That is, firms should maintain ecological fitness by reconfiguring their resource base to cope with emerging threats and explore new opportunities, while at the same time exploiting existing resources. As such, firms possessing the ability to simultaneously perform exploitative and explorative initiatives are more resilient. In this respect, the performance implications of balancing ...

  3. Commercial applications

    International Nuclear Information System (INIS)

    Anon.

    1982-01-01

    The objective of this paper is to assess the near term (one-to-five-year) needs of domestic and foreign commercial suppliers of radiochemicals and radiopharmaceuticals for electromagnetically separated stable isotopes. Only isotopes purchased to make products for sale and profit are considered in this assessment. Radiopharmaceuticals produced from enriched stable isotopes supplied by the Calutron facility at ORNL are used in about 600,000 medical procedures each year in the United States. A temporary or permanent disruption of the supply of stable isotopes to the domestic radiopharmaceutical industry could curtail, if not eliminate, the use of such diagnostic procedures as the thallium heart scan, the gallium cancer scan, the gallium abscess scan, and the low-radiation-dose thyroid scan. The word could in the preceding sentence is underlined because an alternative source of enriched stable isotopes does exist in the USSR. Alternative starting materials could, in theory, eventually be developed for both the thallium and gallium scans. The development of a new technology for these purposes, however, would take at least five years and would be expensive. Hence, any disruption of the supply of enriched isotopes from ORNL and the resulting unavailability of critical nuclear medicine procedures would have a dramatic negative effect on the level of health care in the United States

  4. Commercial applications

    Science.gov (United States)

    The near term (one to five year) needs of domestic and foreign commercial suppliers of radiochemicals and radiopharmaceuticals for electromagnetically separated stable isotopes are assessed. Only isotopes purchased to make products for sale and profit are considered. Radiopharmaceuticals produced from enriched stable isotopes supplied by the Calutron facility at ORNL are used in about 600,000 medical procedures each year in the United States. A temporary or permanent disruption of the supply of stable isotopes to the domestic radiopharmaceutical industry could curtail, if not eliminate, the use of such diagnostic procedures as the thallium heart scan, the gallium cancer scan, the gallium abscess scan, and the low radiation dose thyroid scan. An alternative source of enriched stable isotopes exist in the USSR. Alternative starting materials could, in theory, eventually be developed for both the thallium and gallium scans. The development of a new technology for these purposes, however, would take at least five years and would be expensive. Hence, any disruption of the supply of enriched isotopes from ORNL and the resulting unavailability of critical nuclear medicine procedures would have a dramatic negative effect on the level of health care in the United States.

  5. Characterisation results of the CMOS VISNIR spectral band detector for the METimage instrument

    Science.gov (United States)

    Pratlong, Jérôme; Schmuelling, Frank; Benitez, Victor; Breart De Boisanger, Michel; Skegg, Michael; Simpson, Robert; Bowring, Steve; Krzizok, Natalie

    2017-09-01

    The METimage instrument is part of the EPS-SG (EUMETSAT Polar System Second Generation) program. It will be situated on the MetOp-SG platform which in operation has an objective of collecting data for meteorology and climate monitoring as well as their forecasting. Teledyne e2v has developed and characterised the CMOS VISNIR detector flight module part of the METimage instrument. This paper will focus on the silicon results obtained from the CMOS VISNIR detector flight model. The detector is a large multi-linear device composed of 7 spectral bands covering a wavelength range from 428 nm to 923 nm (some bands are placed twice and added together to enhance the signal-to-noise performance). This detector uses a 4T pixel, with a size of 250μm square, presenting challenges to achieve good charge transfer efficiency with high conversion factor and good linearity for signal levels up to 2M electrons and with high line rates. Low noise has been achieved using correlated double sampling to suppress the read-out noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. The photodiode occupies a significant fraction of the large pixel area. This makes it possible to meet the detection efficiency when front illuminated. A thicker than standard epitaxial silicon is used to improve NIR response. However, the dielectric stack on top of the sensor produces Fabry-Perot étalon effects, which are problematic for narrow band illumination as this causes the detection efficiency to vary significantly over a small wavelength range. In order to reduce this effect and to meet the specification, the silicon manufacturing process has been modified. The flight model will have black coating deposited between each spectral channel, onto the active silicon regions.

  6. A theoretical investigation of spectra utilization for a CMOS based indirect detector for dual energy applications

    International Nuclear Information System (INIS)

    Kalyvas, N; Michail, C; Valais, I; Kandarakis, I; Fountos, G; Martini, N; Koukou, V; Sotiropoulou, P

    2015-01-01

    Dual Energy imaging is a promising method for visualizing masses and microcalcifications in digital mammography. Currently commercially available detectors may be suitable for dual energy mammographic applications. The scope of this work was to theoretically examine the performance of the Radeye CMOS digital indirect detector under three low- and high-energy spectral pairs. The detector was modeled through the linear system theory. The pixel size was equal to 22.5μm and the phosphor material of the detector was a 33.9 mg/cm 2 Gd 2 O 2 S:Tb phosphor screen. The examined spectral pairs were (i) a 40kV W/Ag (0.01cm) and a 70kV W/Cu (0.1cm) target/filter combinations, (ii) a 40kV W/Cd (0.013cm) and a 70kV W/Cu (0.1cm) target/filter combinations and (iii) a 40kV W/Pd (0.008cm) and a 70kV W/Cu (0.1cm) target/filter combinations. For each combination the Detective Quantum Efficiency (DQE), showing the signal to noise ratio transfer, the detector optical gain (DOG), showing the sensitivity of the detector and the coefficient of variation (CV) of the detector output signal were calculated. The second combination exhibited slightly higher DOG (326 photons per X-ray) and lower CV (0.755%) values. In terms of electron output from the RadEye CMOS, the first two combinations demonstrated comparable DQE values; however the second combination provided an increase of 6.5% in the electron output. (paper)

  7. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  8. High-Voltage-Input Level Translator Using Standard CMOS

    Science.gov (United States)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  9. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  10. Applications of Si/SiGe heterostructures to CMOS devices

    International Nuclear Information System (INIS)

    Sidek, R.M.

    1999-03-01

    For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometer regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performance or to relax the technological challenge. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics. The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally, demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations. The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapor deposition oxide and plasma anodic oxide. Low field mobilities, μ 0 are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge

  11. Freeform Compliant CMOS Electronic Systems for Internet of Everything Applications

    KAUST Repository

    Shaikh, Sohail F.

    2017-01-17

    The state-of-the-art electronics technology has been an integral part of modern advances. The prevalent rise of the mobile device and computational technology in the age of information technology offers exciting applications that are attributed to sophisticated, enormously reliable, and most mature CMOS-based electronics. We are accustomed to high performance, cost-effective, multifunctional, and energy-efficient scaled electronics. However, they are rigid, bulky, and brittle. The convolution of flexibility and stretchability in electronics for emerging Internet of Everything application can unleash smart application horizon in unexplored areas, such as robotics, healthcare, smart cities, transport, and entertainment systems. While flexible and stretchable device themes are being remarkably chased, the realization of the fully compliant electronic system is unaddressed. Integration of data processing, storage, communication, and energy management devices complements a compliant system. Here, a comprehensive review is presented on necessity and design criteria for freeform (physically flexible and stretchable) compliant high-performance CMOS electronic systems.

  12. Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

    CERN Document Server

    Morgado, Alonso; Rosa, José M

    2012-01-01

    This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.   This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview...

  13. Micromachined high-performance RF passives in CMOS substrate

    International Nuclear Information System (INIS)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-01-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

  14. Future challenges in single event effects for advanced CMOS technologies

    International Nuclear Information System (INIS)

    Guo Hongxia; Wang Wei; Luo Yinhong; Zhao Wen; Guo Xiaoqiang; Zhang Keying

    2010-01-01

    SEE have became a substantial Achilles heel for the reliability of space-based advanced CMOS technologies with features size downscaling. Future space and defense systems require identification and understanding of single event effects to develop hardening approaches for advanced technologies, including changes in device geometry and materials affect energy deposition, charge collection,circuit upset, parametric degradation devices. Topics covered include the impact of technology scaling on radiation response, including single event transients in high speed digital circuits, evidence for single event effects caused by proton direct ionization, and the impact for SEU induced by particle energy effects and indirect ionization. The single event effects in CMOS replacement technologies are introduced briefly. (authors)

  15. A CMOS integrated timing discriminator circuit for fast scintillation counters

    International Nuclear Information System (INIS)

    Jochmann, M.W.

    1998-01-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t r ≥ 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal's amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range

  16. PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    T. Tharaneeswaran

    2012-06-01

    Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

  17. Pixel front-end development in 65 nm CMOS technology

    International Nuclear Information System (INIS)

    Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

    2014-01-01

    Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

  18. Latch-up control in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Ochoa, A. Jr.; Estreich, D.B.; Dawes, W.R. Jr.

    1979-01-01

    The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed

  19. SEU-hardened design for shift register in CMOS APS

    International Nuclear Information System (INIS)

    Meng Liya; Liu Zedong; Hu Dajiang; Wang Qingxiang

    2012-01-01

    The inverter-based quasi-static shift register in CMOS APS, which is used in ionizing radiation environment, is susceptible to single event upset (SEU), thus affecting the CMOS active pixel sensor (APS) working. The analysis of the SEU for inverter-based quasi-static shift register concludes that the most sensitive node to single event transient (SET) exists in the input of inverter, and the threshold voltage and capacitance of input node of inverter determine the capability of anti-SEU. A new method was proposed, which replaced the inverter with Schmitt trigger in shift register. Because there is a hysteresis on voltage transfer characteristic of Schmitt trigger, there is high flip threshold, thus better capability of anti-SEU can be achieved. Simulation results show that the anti-SEU capability of Schmitt trigger is 10 times more than that of inverter. (authors)

  20. Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

    Science.gov (United States)

    Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

    2016-11-01

    Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

  1. Smart CMOS image sensor for lightning detection and imaging.

    Science.gov (United States)

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

  2. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... of the mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The design of the readout circuitry used for the first electrical characterization of an integrated cantilever...... with CMOS circuitry is demonstrated. The electrical characterization of the device shows that the resonant behavior of the cantilever depends on the applied voltages, which corresponds to theory....

  3. Experimental research on transient ionizing radiation effects of CMOS microcontroller

    International Nuclear Information System (INIS)

    Jin Xiaoming; Fan Ruyu; Chen Wei; Wang Guizhen; Lin Dongsheng; Yang Shanchao; Bai Xiaoyan

    2010-01-01

    This paper presents an experimental test system of CMOS microcontroller EE80C196KC20. Based on this system, the transient ionizing radiation effects on microcontroller were investigated using 'Qiangguang-I' accelerator. The gamma pulse width was 20 ns and the dose rate (for the Si atom) was in the range of 6.7 x 10 6 to 2.0 x 10 8 Gy/s in the experimental study. The disturbance and latchup effects were observed at different dose rate levels. Latchup threshold of the microcontroller was obtained. Disturbance interval and the system power supply current have a relationship with the dose rate level. The transient ionizing radiation induces photocurrent in the PN junctions that are inherent in CMOS circuits. The photocurrent is responsible for the electrical and functional degradation. (authors)

  4. The economics of exploiting gas hydrates

    International Nuclear Information System (INIS)

    Döpke, Lena-Katharina; Requate, Till

    2014-01-01

    We investigate the optimal exploitation of methane hydrates, a recent discovery of methane resources under the sea floor, mainly located along the continental margins. Combustion of methane (releasing CO2) and leakage through blow-outs (releasing CH4) contribute to the accumulation of greenhouse gases. A second externality arises since removing solid gas hydrates from the sea bottom destabilizes continental margins and thus increases the risk of marine earthquakes. We show that in such a model three regimes can occur: i) resource exploitation will be stopped in finite time, and some of the resource will stay in situ, ii) the resource will be used up completely in finite time, and iii) the resource will be exhausted in infinite time. We also show how to internalize the externalities by policy instruments. - Highlights: • We set up a model of optimal has hydrate exploitation • We incorporate to types of damages: contribution to global warming and geo-hazards • We characterize optimal exploitation paths and study decentralization with an exploitation tax. • Three regimes can occur: • i) exploitation in finite time and some of the stock remaining in situ, • ii) exploitation in finite time and the resource will be exhausted, • iii) exploitation and exhaustion in infinite time

  5. Exploitation and exploration dynamics in recessionary times

    NARCIS (Netherlands)

    Walrave, B.

    2012-01-01

    Firm performance largely depends on the ability to adapt to, and exploit, changes in the business environment. That is, firms should maintain ecological fitness by reconfiguring their resource base to cope with emerging threats and explore new opportunities, while at the same time exploiting

  6. Packaging of Sin Goods - Commitment or Exploitation?

    DEFF Research Database (Denmark)

    Nafziger, Julia

    to such self-control problems, and possibly exploit them, by offering different package sizes. In a competitive market, either one or three (small, medium and large) packages are offered. In contrast to common intuition, the large, and not the small package is a commitment device. The latter serves to exploit...

  7. SEXUAL EXPLOITATION AND ABUSE BY UN PEACEKEEPERS ...

    African Journals Online (AJOL)

    Allaiac

    sexual exploitation of children by peacekeepers is particularly insidious. ... sexual exploitation and abuse should involve an understanding of the social .... The charges of sexual misconduct, and the consequent media exposure, have ..... awareness programmes such as video tapes, lectures and training manuals, designed.

  8. A BiCMOS Binary Hysteresis Chaos Generator

    Science.gov (United States)

    Ahmadi, S.; Newcomb, R. W.

    A previous op-amp RC circuit which was proven to give chaotic signals is converted to a BiCMOS design more suitable to integrated circuit realization. The structure results from a degree two differential equation which includes binary hysteresis as its nonlinearity. The circuit is realized by differential (voltage to current) pairs feeding two capacitors, which carry the dynamics, with the key component being a (voltage to current) binary hysteresis circuit due to Linares.

  9. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

    2013-01-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  10. Simulation of design dependent failure exposure levels for CMOS ICs

    International Nuclear Information System (INIS)

    Kaul, N.; Bhuva, B.L.; Rangavajjhala, V.; van der Molen, H.; Kerns, S.E.

    1990-01-01

    The total dose exposure of CMOS ICs introduces bias-dependent parameter shifts in individual devices. The bias dependency of individual parameter shifts of devices cause different designs to behave differently under identical testing conditions. This paper studies the effect of design and bias on the radiation tolerance of ICs and presents an automated design tool that produces different designs for a logic function, and presents important parameters of each design to circuit designer for trade off analysis

  11. Integrated CMOS sensor technologies for the CLIC tracker

    CERN Document Server

    AUTHOR|(SzGeCERN)754303

    2017-01-01

    Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear e+e- collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

  12. Accelerated life testing effects on CMOS microcircuit characteristics, phase 1

    Science.gov (United States)

    Maximow, B.

    1976-01-01

    An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

  13. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  14. Design and Characterization of Vertical Mesh Capacitors in Standard CMOS

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF/μ2, 2.2 μm wide shielded unit capacitors, 6...

  15. Scaling limits and reliability of SOI CMOS technology

    International Nuclear Information System (INIS)

    Ioannou, D E

    2005-01-01

    As bulk and PD-SOI CMOS approach their scaling limit (at gate length of around 50 nm), there is a renewed interest on FD-SOI because of its potential for continued scalability beyond this limit. In this review the performance and reliability of extremely scaled FD transistors are discussed and an attempt is made to identify critical areas for further research. (invited paper)

  16. Deep n-well MAPS in a 130 nm CMOS technology: Beam test results

    International Nuclear Information System (INIS)

    Neri, N.; Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Ceccanti, M.; Cenci, R.; Cervelli, A.; Crescioli, F.; Dell'Orso, M.; Forti, F.; Giannetti, P.; Giorgi, M.A.; Gregucci, S.; Mammini, P.; Marchiori, G.; Massa, M.; Morsani, F.; Paoloni, E.; Piendibene, M.

    2010-01-01

    We report on recent beam test results for the APSEL4D chip, a new deep n-well MAPS prototype with a full in-pixel signal processing chain obtained by exploiting the triple well option of the CMOS 0.13μm process. The APSEL4D chip consists of a 4096 pixel matrix (32 rows and 128 columns) with 50x50μm 2 pixel cell area, with custom readout architecture capable of performing data sparsification at pixel level. APSEL4D has been characterized in terms of charge collection efficiency and intrinsic spatial resolution under different conditions of discriminator threshold settings using a 12 GeV/c proton beam in the T9 area of the CERN PS. We observe a maximum hit efficiency of 92% and we estimate an intrinsic resolution of about 14μm. The data driven approach of the tracking detector readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on associative memories. The analysis of the beam test data is critically reviewed along with the characterization of the device under test.

  17. A 65 nm CMOS analog processor with zero dead time for future pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L., E-mail: luigi.gaioni@unibg.it [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Braga, D.; Christian, D.C.; Deptuch, G.; Fahim, F. [Fermi National Accelerator Laboratory, Batavia IL (United States); Nodari, B. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Centre National de Recherche Scientifique, APC/IN2P3, Paris (France); Ratti, L. [Università di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Re, V. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Zimmerman, T. [Fermi National Accelerator Laboratory, Batavia IL (United States)

    2017-02-11

    Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10{sup 34} cm{sup −2} s{sup −1} in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

  18. Development of CMOS pixel sensors for the upgrade of the ALICE Inner Tracking System

    International Nuclear Information System (INIS)

    Molnar, L.

    2014-01-01

    The ALICE Collaboration is preparing a major upgrade of the current detector, planned for installation during the second long LHC shutdown in the years 2018-19, in order to enhance its low-momentum vertexing and tracking capability, and exploit the planned increase of the LHC luminosity with Pb beams. One of the cornerstones of the ALICE upgrade strategy is to replace the current Inner Tracking System in its entirety with a new, high resolution, low-material ITS detector. The new ITS will consist of seven concentric layers equipped with Monolithic Active Pixel Sensors (MAPS) implemented using the 0.18 μm CMOS technology of TowerJazz. In this contribution, the main key features of the ITS upgrade will be illustrated with emphasis on the functionality of the pixel chip. The ongoing developments on the readout architectures, which have been implemented in several fabricated prototypes, will be discussed. The operational features of these prototypes as well as the results of the characterisation tests before and after irradiation will also be presented

  19. Development of CMOS pixel sensors for the upgrade of the ALICE Inner Tracking System

    Science.gov (United States)

    Molnar, L.

    2014-12-01

    The ALICE Collaboration is preparing a major upgrade of the current detector, planned for installation during the second long LHC shutdown in the years 2018-19, in order to enhance its low-momentum vertexing and tracking capability, and exploit the planned increase of the LHC luminosity with Pb beams. One of the cornerstones of the ALICE upgrade strategy is to replace the current Inner Tracking System in its entirety with a new, high resolution, low-material ITS detector. The new ITS will consist of seven concentric layers equipped with Monolithic Active Pixel Sensors (MAPS) implemented using the 0.18 μm CMOS technology of TowerJazz. In this contribution, the main key features of the ITS upgrade will be illustrated with emphasis on the functionality of the pixel chip. The ongoing developments on the readout architectures, which have been implemented in several fabricated prototypes, will be discussed. The operational features of these prototypes as well as the results of the characterisation tests before and after irradiation will also be presented.

  20. A 5 Gb/s CMOS adaptive equalizer for serial link

    Science.gov (United States)

    Wu, Hongbing; Wang, Jingyu; Liu, Hongxia

    2018-04-01

    A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13 μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter. Project supported by the National Natural Science Foundation of China (No. 61376099), the Foundation for Fundamental Research of China (No. JSZL2016110B003), and the Major Fundamental Research Program of Shaanxi (No. 2017ZDJC-26).

  1. High-ratio voltage conversion in CMOS for efficient mains-connected standby

    CERN Document Server

    Meyvaert, Hans

    2016-01-01

    This book describes synergetic innovation opportunities offered by combining the field of power conversion with the field of integrated circuit (IC) design. The authors demonstrate how integrating circuits enables increased operation frequency, which can be exploited in power converters to reduce drastically the size of the discrete passive components. The authors introduce multiple power converter circuits, which are very compact as result of their high level of integration. First, the limits of high-power-density low-voltage monolithic switched-capacitor DC-DC conversion are investigated to enable on-chip power granularization. AC-DC conversion from the mains to a low voltage DC is discussed, enabling an efficient and compact, lower-power auxiliary power supply to take over the power delivery during the standby mode of mains-connected appliances, allowing the main power converter of these devices to be shut down fully. Discusses high-power-density monolithic switched-capacitor DC-DC conversion in bulk CMOS,...

  2. 1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

    International Nuclear Information System (INIS)

    Huang Beiju; Zhang Xu; Chen Hongda

    2009-01-01

    A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS technology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capacitance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resistance is 50 Ω, and the average input noise current spectral density is 9.7 pA/√Hz. Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

  3. 1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

    Energy Technology Data Exchange (ETDEWEB)

    Huang Beiju; Zhang Xu; Chen Hongda, E-mail: bjhuang@semi.ac.c [State Key Laboratory of Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-10-15

    A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 {mu}m RF CMOS technology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB{center_dot}{Omega} for 1.5 pF photodiode capacitance, with a gain-bandwidth product of 3.4 THz{center_dot}{Omega}. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resistance is 50 {Omega}, and the average input noise current spectral density is 9.7 pA/{radical}Hz. Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

  4. Low resistive edge contacts to CVD-grown graphene using a CMOS compatible metal

    Energy Technology Data Exchange (ETDEWEB)

    Shaygan, Mehrdad; Otto, Martin; Sagade, Abhay A.; Neumaier, Daniel [Advanced Microelectronic Center Aachen, AMO GmbH, Aachen (Germany); Chavarin, Carlos A. [Lehrstuhl Werkstoffe der Elektrotechnik, Duisburg-Essen Univ., Duisburg (Germany); Innovations for High Performance Microelectronics, IHP GmbH, Frankfurt (Oder) (Germany); Bacher, Gerd; Mertin, Wolfgang [Lehrstuhl Werkstoffe der Elektrotechnik, Duisburg-Essen Univ., Duisburg (Germany)

    2017-11-15

    The exploitation of the excellent intrinsic electronic properties of graphene for device applications is hampered by a large contact resistance between the metal and graphene. The formation of edge contacts rather than top contacts is one of the most promising solutions for realizing low ohmic contacts. In this paper the fabrication and characterization of edge contacts to large area CVD-grown monolayer graphene by means of optical lithography using CMOS compatible metals, i.e. Nickel and Aluminum is reported. Extraction of the contact resistance by Transfer Line Method (TLM) as well as the direct measurement using Kelvin Probe Force Microscopy demonstrates a very low width specific contact resistance down to 130 Ωμm. The contact resistance is found to be stable for annealing temperatures up to 150 C enabling further device processing. Using this contact scheme for edge contacts, a field effect transistor based on CVD graphene with a high transconductance of 0.63 mS/μm at 1 V bias voltage is fabricated. (copyright 2017 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  5. From hybrid to CMOS pixels ... a possibility for LHC's pixel future?

    International Nuclear Information System (INIS)

    Wermes, N.

    2015-01-01

    Hybrid pixel detectors have been invented for the LHC to make tracking and vertexing possible at all in LHC's radiation intense environment. The LHC pixel detectors have meanwhile very successfully fulfilled their promises and R and D for the planned HL-LHC upgrade is in full swing, targeting even higher ionising doses and non-ionising fluences. In terms of rate and radiation tolerance hybrid pixels are unrivaled. But they have disadvantages as well, most notably material thickness, production complexity, and cost. Meanwhile also active pixel sensors (DEPFET, MAPS) have become real pixel detectors but they would by far not stand the rates and radiation faced from HL-LHC. New MAPS developments, so-called DMAPS (depleted MAPS) which are full CMOS-pixel structures with charge collection in a depleted region have come in the R and D focus for pixels at high rate/radiation levels. This goal can perhaps be realised exploiting HV technologies, high ohmic substrates and/or SOI based technologies. The paper covers the main ideas and some encouraging results from prototyping R and D, not hiding the difficulties

  6. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    OpenAIRE

    Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao

    2011-01-01

    Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...

  7. Self-calibrated humidity sensor in CMOS without post-processing.

    Science.gov (United States)

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2012-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  8. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    OpenAIRE

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  9. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  10. Exploration, Exploitation, and Organizational Coordination Mechanisms

    Directory of Open Access Journals (Sweden)

    Silvio Popadiuk

    2016-03-01

    Full Text Available This paper presents an empirical relationship among exploration, exploitation, and organizational coordination mechanisms, classified as the centralization of decision-making, formalization, and connectedness. In order to analyze the findings of this survey, we used two techniques: Principal Component Analysis (PCA and Partial Least Squares Path Modeling (PLS-PM. Our analysis was supported by 249 answers from managers of companies located in Brazil (convenience sampling. Contrary to expectations, centralization and exploitation were negatively associated. Our data supports the research hypothesis that formalization is positively associated with exploitation. Although the relationship between formalization and exploration were significant, the result is contrary to the research hypothesis that we made. The relationships among connectedness and exploitation, and connectedness and exploration were both positive and significant. This relationship means that the more connectedness increases, the higher the likelihood of exploitation and exploration.

  11. A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

    Science.gov (United States)

    Wallace, Robert M.

    2001-03-01

    Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

  12. Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Chen Qu

    2017-09-01

    Full Text Available The CMOS (Complementary Metal-Oxide-Semiconductor is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze, causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

  13. Advanced CMOS device technologies for 45 nm node and below

    Directory of Open Access Journals (Sweden)

    A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

    2007-01-01

    Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

  14. CMOS-compatible high-voltage integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Parpia, Z

    1988-01-01

    Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

  15. 32 x 16 CMOS smart pixel array for optical interconnects

    Science.gov (United States)

    Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

    2000-05-01

    Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

  16. From vertex detectors to inner trackers with CMOS pixel sensors

    CERN Document Server

    Besson, A.

    2017-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  17. Transient-induced latchup in CMOS integrated circuits

    CERN Document Server

    Ker, Ming-Dou

    2009-01-01

    "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

  18. Multi-target electrochemical biosensing enabled by integrated CMOS electronics

    International Nuclear Information System (INIS)

    Rothe, J; Lewandowska, M K; Heer, F; Frey, O; Hierlemann, A

    2011-01-01

    An integrated electrochemical measurement system, based on CMOS technology, is presented, which allows the detection of several analytes in parallel (multi-analyte) and enables simultaneous monitoring at different locations (multi-site). The system comprises a 576-electrode CMOS sensor chip, an FPGA module for chip control and data processing, and the measurement laptop. The advantages of the highly versatile system are demonstrated by two applications. First, a label-free, hybridization-based DNA sensor is enabled by the possibility of large-scale integration in CMOS technology. Second, the detection of the neurotransmitter choline is presented by assembling the chip with biosensor microprobe arrays. The low noise level enables a limit of detection of, e.g., 0.3 µM choline. The fully integrated system is self-contained: it features cleaning, functionalization and measurement functions without the need for additional electrical equipment. With the power supplied by the laptop, the system is very suitable for on-site measurements

  19. Nanosecond-laser induced crosstalk of CMOS image sensor

    Science.gov (United States)

    Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

    2018-02-01

    The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

  20. First result on biased CMOS MAPs-on-diamond devices

    Energy Technology Data Exchange (ETDEWEB)

    Kanxheri, K., E-mail: keida.kanxheri@pg.infn.it [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Citroni, M.; Fanetti, S. [LENS Firenze, Florence (Italy); Lagomarsino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Morozzi, A. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Parrini, G. [Università degli Studi di Firenze, Florence (Italy); Passeri, D. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Sciortino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Servoli, L. [INFN Perugia, Perugia (Italy)

    2015-10-01

    Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

  1. Development of CMOS Imager Block for Capsule Endoscope

    International Nuclear Information System (INIS)

    Shafie, S; Fodzi, F A M; Tung, L Q; Lioe, D X; Halin, I A; Hasan, W Z W; Jaafar, H

    2014-01-01

    This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5 V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5 V to 3.3 V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5 V to 3.3 V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

  2. Radiation hardness of CMOS monolithic active pixel sensors manufactured in a 0.18 μm CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Linnik, Benjamin [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2015-07-01

    CMOS Monolithic Active Pixels Sensors (MAPS) are considered as the technology of choice for various vertex detectors in particle and heavy-ion physics including the STAR HFT, the upgrade of the ALICE ITS, the future ILC detectors and the CBM experiment at FAIR. To match the requirements of those detectors, their hardness to radiation is being improved, among others in a joined research activity of the Goethe University Frankfurt and the IPHC Strasbourg. It was assumed that combining an improved high resistivity (1-8 kΩcm) sensitive medium with the features of a 0.18 μm CMOS process, is suited to reach substantial improvements in terms of radiation hardness as compared to earlier sensor designs. This strategy was tested with a novel generation of sensor prototypes named MIMOSA-32 and MIMOSA-34. We show results on the radiation hardness of those sensors and discuss its impact on the design of future vertex detectors.

  3. Herbivory eliminates fitness costs of mutualism exploiters.

    Science.gov (United States)

    Simonsen, Anna K; Stinchcombe, John R

    2014-04-01

    A common empirical observation in mutualistic interactions is the persistence of variation in partner quality and, in particular, the persistence of exploitative phenotypes. For mutualisms between hosts and symbionts, most mutualism theory assumes that exploiters always impose fitness costs on their host. We exposed legume hosts to mutualistic (nitrogen-fixing) and exploitative (non-nitrogen-fixing) symbiotic rhizobia in field conditions, and manipulated the presence or absence of insect herbivory to determine if the costly fitness effects of exploitative rhizobia are context-dependent. Exploitative rhizobia predictably reduced host fitness when herbivores were excluded. However, insects caused greater damage on hosts associating with mutualistic rhizobia, as a consequence of feeding preferences related to leaf nitrogen content, resulting in the elimination of fitness costs imposed on hosts by exploitative rhizobia. Our experiment shows that herbivory is potentially an important factor in influencing the evolutionary dynamic between legumes and rhizobia. Partner choice and host sanctioning are theoretically predicted to stabilize mutualisms by reducing the frequency of exploitative symbionts. We argue that herbivore pressure may actually weaken selection on choice and sanction mechanisms, thus providing one explanation of why host-based discrimination mechanisms may not be completely effective in eliminating nonbeneficial partners. © 2014 The Authors. New Phytologist © 2014 New Phytologist Trust.

  4. Optimization of CMOS active pixels for high resolution digital radiography

    International Nuclear Information System (INIS)

    Kim, Young Soo

    2007-02-01

    CMOS image sensors have poorer performance compared to conventional charge coupled devices (CCDs). Since CMOS Active Pixel Sensors (APSs) in general have higher temporal noise, higher dark current, smaller full well charge capacitance, and lower spectral response, they cannot provide the same wide dynamic range and superior signal-to-noise ratio as CCDs. In view of electronic noise, the main source for the CMOS APS is the pixel, along with other signal processing blocks such as row and column decoder, analog signal processor (ASP), analog-to-digital converter (ADC), and timing and control logic circuitry. Therefore, it is important and necessary to characterize noise of the active pixels in CMOS APSs. We developed our theoretical noise model to account for the temporal noise in active pixels, and then found out the optimum design parameters such as fill actor, each size of the three transistors (source follower, row selection transistor, bias transistor) comprising active pixels, bias current, and load capacitance that can have the maximum signal-to-noise ratio. To develop the theoretical noise model in active pixels, we considered the integration noise of the photodiode and the readout noise of the transistors related to readout. During integration, the shot noise due to the dark current and photocurrent, during readout, the thermal and flicker noise were considered. The developed model can take the input variables such as photocurrent, capacitance of the photodiode, integration time, transconductance of the transistors, channel resistance of the transistors, gate-to-source capacitance of the follower, and load capacitance etc. To validate our noise model, two types of test structures have been realized. Firstly, four types of photodiodes (n_d_i_f_f_u_s_i_o_n/p_s_u_b_s_t_r_a_t_e, n_w_e_l_l/p_s_u_b_s_t_r_a_t_e, n_d_i_f_f_u_s_i_o_n/p_e_p_i_t_a_x_i_a_l/p_s_u_b_s_t_r_a_t_e, n_w_e_l_l/p_e_p_i_t_a_x_i_a_l/p_s_u_b_s_t_r_a_t_e) used in CMOS active pixels were fabricated

  5. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    Science.gov (United States)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

  6. Design and characterization of radiation resistant integrated circuits for the LHC particle detectors using deep sub-micron CMOS technologies

    International Nuclear Information System (INIS)

    Anelli, Giovanni Maria

    2000-01-01

    The electronic circuits associated with the particle detectors of the CERN Large Hadron Collider (LHC) have to work in a highly radioactive environment. This work proposes a methodology allowing the design of radiation resistant integrated circuits using the commercial sub-micron CMOS technology. This method uses the intrinsic radiation resistance of ultra-thin grid oxides, the technology of enclosed layout transistors (ELT), and the protection rings to avoid the radio-induced creation of leakage currents. In order to check the radiation tolerance level, several test structures have been designed and tested with different radiation sources. These tests have permitted to study the physical phenomena responsible for the damages induced by the radiations and the possible remedies. Then, the particular characteristics of ELT transistors and their influence on the design of complex integrated circuits has been explored. The modeling of the W/L ratio, the asymmetries (for instance in the output conductance) and the performance of ELT couplings have never been studied yet. The noise performance of the 0.25 μ CMOS technology, used in the design of several integrated circuits of the LHC detectors, has been characterized before and after irradiation. Finally, two integrated circuits designed using the proposed method are presented. The first one is an analogic memory and the other is a circuit used for the reading of the signals of one of the LHC detectors. Both circuits were irradiated and have endured very high doses practically without any sign of performance degradation. (J.S.)

  7. Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

    CERN Document Server

    Miucci, A; Hemperek, T.; Hügging, F.; Krüger, H.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Backhaus, M.; Capeans, M.; Feigl, S.; Nessi, M.; Pernegger, H.; Ristic, B.; Gonzalez-Sevilla, S.; Ferrere, D.; Iacobucci, G.; Rosa, A.La; Muenstermann, D.; George, M.; Grosse-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.; Kreidl, C.; Peric, I.; Breugnon, P.; Pangaud, P.; Godiot-Basolo, S.; Fougeron, D.; Bompard, F.; Clemens, J.C.; Liu, J; Barbero, M.; Rozanov, A

    2014-01-01

    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. 1Corresponding author. c CERN 2014, published under the terms of the Creative Commons Attribution 3.0 License by IOP Publishing Ltd and Sissa Medialab srl. Any further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation and DOI. doi:10.1088/1748-0221/9/05/C050642014 JINST 9 C05064 A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation a...

  8. Development of CMOS MEMS inductive type tactile sensor with the integration of chrome steel ball force interface

    Science.gov (United States)

    Yeh, Sheng-Kai; Chang, Heng-Chung; Fang, Weileun

    2018-04-01

    This study presents an inductive tactile sensor with a chrome steel ball sensing interface based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC 0.18 µm 1P6M CMOS process). The tactile senor has a deformable polymer layer as the spring of the device and no fragile suspended thin film structures are required. As a tactile force is applied on the chrome steel ball, the polymer would deform. The distance between the chrome steel ball and the sensing coil would changed. Thus, the tactile force can be detected by the inductance change of the sensing coil. In short, the chrome steel ball acts as a tactile bump as well as the sensing interface. Experimental results show that the proposed inductive tactile sensor has a sensing range of 0-1.4 N with a sensitivity of 9.22(%/N) and nonlinearity of 2%. Preliminary wireless sensing test is also demonstrated. Moreover, the influence of the process and material issues on the sensor performances have also been investigated.

  9. Scaled CMOS Technology Reliability Users Guide

    Science.gov (United States)

    White, Mark

    2010-01-01

    The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is

  10. Peat exploitation - Environment. Effects and measures

    International Nuclear Information System (INIS)

    Stenbeck, G.

    1996-01-01

    This report gives a detailed description of the influence of peat exploitation on the land-, water- and atmospheric environments. Proposals for mitigatory measures to minimize damage to the environment are also given

  11. SEXUAL EXPLOITATION AND ABUSE BY UN PEACEKEEPERS ...

    African Journals Online (AJOL)

    Allaiac

    from sexual exploitation and sexual abuse (ST/SGB/2003/13) (UN, Secretary .... In addition, in most situations, UN personnel have enjoyed immunity from local .... 9 Official UN statistics show a higher incidence of allegations reported against.

  12. Exploitation of linkage learning in evolutionary algorithms

    CERN Document Server

    Chen, Ying-ping

    2010-01-01

    The exploitation of linkage learning is enhancing the performance of evolutionary algorithms. This monograph examines recent progress in linkage learning, with a series of focused technical chapters that cover developments and trends in the field.

  13. Exploitative and Deceptive Resource Acquisition Strategies

    Directory of Open Access Journals (Sweden)

    Joshua J. Reynolds

    2015-07-01

    Full Text Available Life history strategy (LHS and life history contingencies (LHCs should theoretically influence the use of exploitative and deceptive resource acquisition strategies. However, little research has been done in this area. The purpose of the present work was to create measures of exploitative strategies and test the predictions of life history theory. Pilot studies developed and validated a behavioral measure of cheating called the Dot Game. The role of individual LHS and LHCs (manipulated via validated story primes on cheating was investigated in Study 1. Studies 2a through 2c were conducted to develop and validate a self-report measure called the Exploitative and Deceptive Resource Acquisition Strategy Scale (EDRASS. Finally, Study 3 investigated life history and EDRASS. Results indicated that while LHS influences exploitative strategies, life history contingences had little effect. Implications of these findings are discussed.

  14. Organ sales: exploitative at any price?

    Science.gov (United States)

    Lawlor, Rob

    2014-05-01

    In many cases, claims that a transaction is exploitative will focus on the details of the transaction, such as the price paid or conditions. For example, in a claim that a worker is exploited, the grounds for the claim are usually that the pay is not sufficient or the working conditions too dangerous. In some cases, however, the claim that a transaction is exploitative is not seen to rely on these finer details. Many, for example, claim that organ sales would be exploitative, in a way that doesn't seem to depend on the details. This article considers, but ultimately rejects, a number of arguments which could be used to defend this sort of claim. © 2012 John Wiley & Sons Ltd.

  15. A Theory of Exploitative Child Labor

    OpenAIRE

    Carol Ann Rogers; Kenneth A. Swinnerton

    2003-01-01

    Child labor laws should aim to protect children who work, instead of trying to remove children from work. In this paper, we identify an instance when the risk of exploitation lowers the expected bene…t of child labor to the child,and therefore suppresses child labor force participation. Targeted legal intervention that lowers or removes the risk of exploitation raises child participation in the labor market, child welfare, and overall societal welfare. Targeting on child labor more broadly ma...

  16. Managing the Innovators for Exploration and Exploitation

    Directory of Open Access Journals (Sweden)

    C. Annique UN

    2007-09-01

    Full Text Available I analyze how to manage employees to achieve a balance between exploration and exploitation in large established firms. Previous studies suggest that, although firms need to undertake both exploration and exploitation simultaneously, this is difficult either because of the scarcity of resources or because of the incompatibility of these two processes. Proposed solutions have been ambidexterity, punctuated equilibrium or specialization. I suggest another method: managing employees. Specifically, I argue that using the so-called “innovative” system of human resource management practices, consisting of team-based incentive system, team-based job design, and job rotation, enables the firm to undertake exploration and exploitation simultaneously because it provides the psychological safety for people to explore new knowledge to make novel products and develops employees to have the perspective-taking capability that enables the integration of knowledge cross-functionally for efficiency. Using the so-called “traditional” system of human resource management practices, consisting of individual-based incentive system, individual-based job design, and no job rotation, has limited impact on either exploration or exploitation because it does not create the psychological safety for people to explore new knowledge and does not develop the perspective-taking capability needed for exploitation. Moreover, mixing practices from both systems is better than only using the traditional system in achieving exploration or exploitation, but less effective than only using the innovative system as the mix of practices can create inconsistent expectations on employees.

  17. Charged particle detection performances of CMOS pixel sensors produced in a 0.18 μm process with a high resistivity epitaxial layer

    Science.gov (United States)

    Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

    2013-12-01

    The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013neq /cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz 0.18 μm CMOS process for the ALICE ITS upgrade.

  18. Charged particle detection performances of CMOS pixel sensors produced in a 0.18μm process with a high resistivity epitaxial layer

    Energy Technology Data Exchange (ETDEWEB)

    Senyukov, S., E-mail: serhiy.senyukov@cern.ch; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

    2013-12-01

    The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz0.18μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 10{sup 13}n{sub eq}/cm{sup 2} was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz0.18μm CMOS process for the ALICE ITS upgrade.

  19. CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

    KAUST Repository

    Ghoneim, Mohamed T.; Hanna, Amir; Hussain, Muhammad Mustafa

    2014-01-01

    Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with prefabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.

  20. CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

    KAUST Repository

    Ghoneim, Mohamed T.

    2014-08-01

    Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with prefabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.