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Sample records for efficient vlsi architecture

  1. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  2. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  3. VLSI Architectures For Syntactic Image Analysis

    Science.gov (United States)

    Chiang, Y. P.; Fu, K. S.

    1984-01-01

    Earley's algorithm has been commonly used for the parsing of general context-free languages and error-correcting parsing in syntactic pattern recognition. The time complexity for parsing is 0(n3). In this paper we present a parallel Earley's recognition algorithm in terms of "x*" operation. By restricting the input context-free grammar to be X-free, we are able to implement this parallel algorithm on a triangular shape VLSI array. This system has an efficient way of moving data to the right place at the right time. Simulation results show that this system can recognize a string with length n in 2n+1 system time. We also present an error-correcting recognition algorithm. The parallel error-correcting recognition algorithm has also been im-plemented on a triangular VLSI array. This array recognizes an erroneous string length n in time 2n+1 and gives the correct error count. Applications of the proposed VLSI architectures to image analysis are illus-trated by examples.

  4. VLSI-distributed architectures for smart cameras

    Science.gov (United States)

    Wolf, Wayne H.

    2001-03-01

    Smart cameras use video/image processing algorithms to capture images as objects, not as pixels. This paper describes architectures for smart cameras that take advantage of VLSI to improve the capabilities and performance of smart camera systems. Advances in VLSI technology aid in the development of smart cameras in two ways. First, VLSI allows us to integrate large amounts of processing power and memory along with image sensors. CMOS sensors are rapidly improving in performance, allowing us to integrate sensors, logic, and memory on the same chip. As we become able to build chips with hundreds of millions of transistors, we will be able to include powerful multiprocessors on the same chip as the image sensors. We call these image sensor/multiprocessor systems image processors. Second, VLSI allows us to put a large number of these powerful sensor/processor systems on a single scene. VLSI factories will produce large quantities of these image processors, making it cost-effective to use a large number of them in a single location. Image processors will be networked into distributed cameras that use many sensors as well as the full computational resources of all the available multiprocessors. Multiple cameras make a number of image recognition tasks easier: we can select the best view of an object, eliminate occlusions, and use 3D information to improve the accuracy of object recognition. This paper outlines approaches to distributed camera design: architectures for image processors and distributed cameras; algorithms to run on distributed smart cameras, and applications of which VLSI distributed camera systems.

  5. VLSI architectures for the new (T,L) algorithm

    Science.gov (United States)

    Bengough, P. A.; Simmons, S. J.

    Trellis coding techniques have seen much use in error correction codes for space and satellite applications. When long sequences of data are encoded, the number of possible paths through the trellis becomes great and a trellis search algorithm must be used to determine the path that best matches the received data sequence. The (T,L) algorithm is a new reduced complexity trellis search algorithm, applicable to data sequence estimation in digital communications, that adapts to changing channel conditions. Its simplicity and inherent parallelism suits it well for very large scale integration (VLSI) implementation. A number of alternative VLSI architectures are presented which can be used to realize this algorithm. While one uses a simple nonsorting structure, two other sorting designs based on parallel insertion and weavesorting algorithms are proposed. The area-time performance of the various architectures is compared.

  6. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  7. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  8. A parallel VLSI architecture for a digital filter using a number theoretic transform

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1983-01-01

    The advantages of a very large scalee integration (VLSI) architecture for implementing a digital filter using fermat number transforms (FNT) are the following: It requires no multiplication. Only additions and bit rotations are needed. It alleviates the usual dynamic range limitation for long sequence FNT's. It utilizes the FNT and inverse FNT circuits 100% of the time. The lengths of the input data and filter sequences can be arbitraty and different. It is regular, simple, and expandable, and as a consequence suitable for VLSI implementation.

  9. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  10. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  11. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  12. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  13. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  14. A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1982-01-01

    A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

  15. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  16. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  17. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  18. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  19. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  20. Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

    Science.gov (United States)

    Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

    1989-01-01

    The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

  1. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  2. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  3. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  4. An Efficient Reconfigurable Architecture for Fingerprint Recognition

    Directory of Open Access Journals (Sweden)

    Satish S. Bhairannawar

    2016-01-01

    Full Text Available The fingerprint identification is an efficient biometric technique to authenticate human beings in real-time Big Data Analytics. In this paper, we propose an efficient Finite State Machine (FSM based reconfigurable architecture for fingerprint recognition. The fingerprint image is resized, and Compound Linear Binary Pattern (CLBP is applied on fingerprint, followed by histogram to obtain histogram CLBP features. Discrete Wavelet Transform (DWT Level 2 features are obtained by the same methodology. The novel matching score of CLBP is computed using histogram CLBP features of test image and fingerprint images in the database. Similarly, the DWT matching score is computed using DWT features of test image and fingerprint images in the database. Further, the matching scores of CLBP and DWT are fused with arithmetic equation using improvement factor. The performance parameters such as TSR (Total Success Rate, FAR (False Acceptance Rate, and FRR (False Rejection Rate are computed using fusion scores with correlation matching technique for FVC2004 DB3 Database. The proposed fusion based VLSI architecture is synthesized on Virtex xc5vlx30T-3 FPGA board using Finite State Machine resulting in optimized parameters.

  5. How to build VLSI-efficient neural chips

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-02-01

    This paper presents several upper and lower bounds for the number-of-bits required for solving a classification problem, as well as ways in which these bounds can be used to efficiently build neural network chips. The focus will be on complexity aspects pertaining to neural networks: (1) size complexity and depth (size) tradeoffs, and (2) precision of weights and thresholds as well as limited interconnectivity. They show difficult problems-exponential growth in either space (precision and size) and/or time (learning and depth)-when using neural networks for solving general classes of problems (particular cases may enjoy better performances). The bounds for the number-of-bits required for solving a classification problem represent the first step of a general class of constructive algorithms, by showing how the quantization of the input space could be done in O (m{sup 2}n) steps. Here m is the number of examples, while n is the number of dimensions. The second step of the algorithm finds its roots in the implementation of a class of Boolean functions using threshold gates. It is substantiated by mathematical proofs for the size O (mn/{Delta}), and the depth O [log(mn)/log{Delta}] of the resulting network (here {Delta} is the maximum fan in). Using the fan in as a parameter, a full class of solutions can be designed. The third step of the algorithm represents a reduction of the size and an increase of its generalization capabilities. Extensions by using analogue COMPARISONs, allows for real inputs, and increase the generalization capabilities at the expense of longer training times. Finally, several solutions which can lower the size of the resulting neural network are detailed. The interesting aspect is that they are obtained for limited, or even constant, fan-ins. In support of these claims many simulations have been performed and are called upon.

  6. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  7. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  8. Phase-Based Binocular Perception of Motion in Depth: Cortical-Like Operators and Analog VLSI Architectures

    Directory of Open Access Journals (Sweden)

    Silvio P. Sabatini

    2003-06-01

    Full Text Available We present a cortical-like strategy to obtain reliable estimates of the motions of objects in a scene toward/away from the observer (motion in depth, from local measurements of binocular parameters derived from direct comparison of the results of monocular spatiotemporal filtering operations performed on stereo image pairs. This approach is suitable for a hardware implementation, in which such parameters can be gained via a feedforward computation (i.e., collection, comparison, and punctual operations on the outputs of the nodes of recurrent VLSI lattice networks, performing local computations. These networks act as efficient computational structures for embedded analog filtering operations in smart vision sensors. Extensive simulations on both synthetic and real-world image sequences prove the validity of the approach that allows to gain high-level information about the 3D structure of the scene, directly from sensorial data, without resorting to explicit scene reconstruction.

  9. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    OpenAIRE

    T. Kalavathi Devi; Sakthivel Palaniappan

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the powe...

  10. Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

    CERN Document Server

    Shen, Ruijing; Yu, Hao

    2012-01-01

    Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have  become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits.  Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and ...

  11. Novel structure-recognition-based OCR system and its parallel VLSI architecture

    Science.gov (United States)

    Shan, Tie-Jun

    1993-04-01

    We propose a structure pattern recognition based OCR system for printed text recognition. The segmentation algorithm is a raster-scan based one that reduces memory access time a great deal. The feature extract algorithm is a chain-code encoding based graph traversal algorithm. It has an advantage of single memory access for each pixel while most graph traversal algorithms require multiple scans of the entire image. While traversing a thinned character, structural feature is automatically extracted. The classification is a process of tree search in the structure feature space that is created during the training process. The segmentation, thinning, and feature extraction algorithms are all raster-scan based algorithms that can be implemented by a parallel systolic array architecture.

  12. An efficient VLSI implementation of on-line recursive ICA processor for real-time multi-channel EEG signal separation.

    Science.gov (United States)

    Shih, Wei-Yeh; Liao, Jui-Chieh; Huang, Kuan-Ju; Fang, Wai-Chi; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2013-01-01

    This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of the ORICA processor is 128 Hz, the ORICA processor should produce independent components before the next sample is input in 1/128 s. Under the timing constraints of commutating multi-channel ORICA in real time, the design of the ORICA processor is a mixed architecture, which is designed as different hardware parallelism according to the complexity of processing units. The shared arithmetic processing unit and shared register can reduce hardware complexity and power consumption. The proposed design is implemented used TSMC 90 nm CMOS technology with 8-channel EEG processing in 128 Hz sample rate of raw data and consumes 2.827 mW at 50 MHz clock rate. The performance of the proposed design is also shown to reach 0.0078125 s latency after each EEG sample time, and the average correlation coefficient between the original source signals and extracted ORICA signals for each 1 s frame is 0.9763.

  13. Power-efficient computer architectures recent advances

    CERN Document Server

    Själander, Magnus; Kaxiras, Stefanos

    2014-01-01

    As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture.Table of Contents: Introduction / Voltage and Frequency Management / Heterogeneity and Sp

  14. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  15. Efficient Algorithm and Architecture of Critical-Band Transform for Low-Power Speech Applications

    Directory of Open Access Journals (Sweden)

    Gan Woon-Seng

    2007-01-01

    Full Text Available An efficient algorithm and its corresponding VLSI architecture for the critical-band transform (CBT are developed to approximate the critical-band filtering of the human ear. The CBT consists of a constant-bandwidth transform in the lower frequency range and a Brown constant- transform (CQT in the higher frequency range. The corresponding VLSI architecture is proposed to achieve significant power efficiency by reducing the computational complexity, using pipeline and parallel processing, and applying the supply voltage scaling technique. A 21-band Bark scale CBT processor with a sampling rate of 16 kHz is designed and simulated. Simulation results verify its suitability for performing short-time spectral analysis on speech. It has a better fitting on the human ear critical-band analysis, significantly fewer computations, and therefore is more energy-efficient than other methods. With a 0.35 m CMOS technology, it calculates a 160-point speech in 4.99 milliseconds at 234 kHz. The power dissipation is 15.6 W at 1.1 V. It achieves 82.1 power reduction as compared to a benchmark 256-point FFT processor.

  16. DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency

    Directory of Open Access Journals (Sweden)

    David Raphaël

    2008-01-01

    Full Text Available Abstract Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13  m CMOS SoC implementing a specialized DART cluster is presented.

  17. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  18. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    Directory of Open Access Journals (Sweden)

    T. Kalavathi Devi

    2015-01-01

    Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  19. Motion estimation for video coding efficient algorithms and architectures

    CERN Document Server

    Chakrabarti, Indrajit; Chatterjee, Sumit Kumar

    2015-01-01

    The need of video compression in the modern age of visual communication cannot be over-emphasized. This monograph will provide useful information to the postgraduate students and researchers who wish to work in the domain of VLSI design for video processing applications. In this book, one can find an in-depth discussion of several motion estimation algorithms and their VLSI implementation as conceived and developed by the authors. It records an account of research done involving fast three step search, successive elimination, one-bit transformation and its effective combination with diamond search and dynamic pixel truncation techniques. Two appendices provide a number of instances of proof of concept through Matlab and Verilog program segments. In this aspect, the book can be considered as first of its kind. The architectures have been developed with an eye to their applicability in everyday low-power handheld appliances including video camcorders and smartphones.

  20. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  1. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  2. Efficient architectures for streaming applications

    NARCIS (Netherlands)

    Smit, Gerardus Johannes Maria; Kokkeler, Andre B.J.; Wolkotte, P.T.; van de Burgwal, M.D.; Heysters, P.M.; Athanas, P.; Becker, J.; Brebner, G.; Teich, J.

    2006-01-01

    This presentation will focus on algorithms and reconfigurable tiled architectures for streaming DSP applications. The tile concept will not only be applied on chip level but also on board-level and system-level. The tile concept has a number of advantages: (1) depending on the requirements more or

  3. Evaluating architecture impact on system energy efficiency

    National Research Council Canada - National Science Library

    Shijie Yu; Hailong Yang; Rui Wang; Zhongzhi Luan; Depei Qian

    2017-01-01

    As the energy consumption has been surging in an unsustainable way, it is important to understand the impact of existing architecture designs from energy efficiency perspective, which is especially...

  4. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  5. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  6. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  7. EFFICIENT ASIC ARCHITECTURE OF RSA CRYPTOSYSTEM

    OpenAIRE

    Varun Nehru; H.S. Jattana

    2014-01-01

    This paper presents a unified architecture design of the RSA cryptosystem i.e. RSA cryptoaccelerator along with key-pair generation. A structural design methodology for the same is proposed and implemented. The purpose is to design a complete cryptosystem efficiently with reduced hardware redundancy. Individual modular architectures of RSA, Miller-Rabin Test and Extended Binary GCD algorithm are presented and then they are integrated. Standard algorithm for RSA has been used. T...

  8. Area-Power Efficient VLSI Implementation of Multichannel DWT for Data Compression in Implantable Neuroprosthetics.

    Science.gov (United States)

    Kamboh, A M; Raetz, M; Oweiss, K G; Mason, A

    2007-06-01

    Time-frequency domain signal processing of neural recordings, from high-density microelectrode arrays implanted in the cortex, is highly desired to ease the bandwidth bottleneck associated with data transfer to extra-cranial processing units. Because of its energy compactness features, discrete wavelet transform (DWT) has been shown to provide efficient data compression for neural records without compromising the information content. This paper describes an area-power minimized hardware implementation of the lifting scheme for multilevel, multichannel DWT with quantized filter coefficients and integer computation. Performance tradeoffs and key design decisions for implantable neuroprosthetics are presented. A 32-channel 4-level version of the circuit has been custom designed in 0.18-mum CMOS and occupies only 0.22 mm(2) area and consumes 76 muW of power, making it highly suitable for implantable neural interface applications requiring wireless data transfer.

  9. A subthreshold aVLSI implementation of the Izhikevich simple neuron model.

    Science.gov (United States)

    Rangan, Venkat; Ghosh, Abhishek; Aparin, Vladimir; Cauwenberghs, Gert

    2010-01-01

    We present a circuit architecture for compact analog VLSI implementation of the Izhikevich neuron model, which efficiently describes a wide variety of neuron spiking and bursting dynamics using two state variables and four adjustable parameters. Log-domain circuit design utilizing MOS transistors in subthreshold results in high energy efficiency, with less than 1pJ of energy consumed per spike. We also discuss the effects of parameter variations on the dynamics of the equations, and present simulation results that replicate several types of neural dynamics. The low power operation and compact analog VLSI realization make the architecture suitable for human-machine interface applications in neural prostheses and implantable bioelectronics, as well as large-scale neural emulation tools for computational neuroscience.

  10. Multiple-Clock-Cycle Architecture for the VLSI Design of a System for Time-Frequency Analysis

    Directory of Open Access Journals (Sweden)

    Ivanović Veselin N

    2006-01-01

    Full Text Available Multiple-clock-cycle implementation (MCI of a flexible system for time-frequency (TF signal analysis is presented. Some very important and frequently used time-frequency distributions (TFDs can be realized by using the proposed architecture: (i the spectrogram (SPEC and the pseudo-Wigner distribution (WD, as the oldest and the most important tools used in TF signal analysis; (ii the S-method (SM with various convolution window widths, as intensively used reduced interference TFD. This architecture is based on the short-time Fourier transformation (STFT realization in the first clock cycle. It allows the mentioned TFDs to take different numbers of clock cycles and to share functional units within their execution. These abilities represent the major advantages of multicycle design and they help reduce both hardware complexity and cost. The designed hardware is suitable for a wide range of applications, because it allows sharing in simultaneous realizations of the higher-order TFDs. Also, it can be accommodated for the implementation of the SM with signal-dependent convolution window width. In order to verify the results on real devices, proposed architecture has been implemented with a field programmable gate array (FPGA chips. Also, at the implementation (silicon level, it has been compared with the single-cycle implementation (SCI architecture.

  11. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  12. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  13. Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder

    Directory of Open Access Journals (Sweden)

    Guilherme Corrêa

    2012-01-01

    Full Text Available In H.264/AVC, the encoding process can occur according to one of the 13 intraframe coding modes or according to one of the 8 available interframes block sizes, besides the SKIP mode. In the Joint Model reference software, the choice of the best mode is performed through exhaustive executions of the entire encoding process, which significantly increases the encoder's computational complexity and sometimes even forbids its use in real-time applications. Considering this context, this work proposes a set of heuristic algorithms targeting hardware architectures that lead to earlier selection of one encoding mode. The amount of repetitions of the encoding process is reduced by 47 times, at the cost of a relatively small cost in compression performance. When compared to other works, the fast hierarchical mode decision results are expressively more satisfactory in terms of computational complexity reduction, quality, and bit rate. The low-complexity mode decision architecture proposed is thus a very good option for real-time coding of high-resolution videos. The solution is especially interesting for embedded and mobile applications with support to multimedia systems, since it yields good compression rates and image quality with a very high reduction in the encoder complexity.

  14. Evaluating architecture impact on system energy efficiency.

    Science.gov (United States)

    Yu, Shijie; Yang, Hailong; Wang, Rui; Luan, Zhongzhi; Qian, Depei

    2017-01-01

    As the energy consumption has been surging in an unsustainable way, it is important to understand the impact of existing architecture designs from energy efficiency perspective, which is especially valuable for High Performance Computing (HPC) and datacenter environment hosting tens of thousands of servers. One obstacle hindering the advance of comprehensive evaluation on energy efficiency is the deficient power measuring approach. Most of the energy study relies on either external power meters or power models, both of these two methods contain intrinsic drawbacks in their practical adoption and measuring accuracy. Fortunately, the advent of Intel Running Average Power Limit (RAPL) interfaces has promoted the power measurement ability into next level, with higher accuracy and finer time resolution. Therefore, we argue it is the exact time to conduct an in-depth evaluation of the existing architecture designs to understand their impact on system energy efficiency. In this paper, we leverage representative benchmark suites including serial and parallel workloads from diverse domains to evaluate the architecture features such as Non Uniform Memory Access (NUMA), Simultaneous Multithreading (SMT) and Turbo Boost. The energy is tracked at subcomponent level such as Central Processing Unit (CPU) cores, uncore components and Dynamic Random-Access Memory (DRAM) through exploiting the power measurement ability exposed by RAPL. The experiments reveal non-intuitive results: 1) the mismatch between local compute and remote memory node caused by NUMA effect not only generates dramatic power and energy surge but also deteriorates the energy efficiency significantly; 2) for multithreaded application such as the Princeton Application Repository for Shared-Memory Computers (PARSEC), most of the workloads benefit a notable increase of energy efficiency using SMT, with more than 40% decline in average power consumption; 3) Turbo Boost is effective to accelerate the workload execution

  15. Evaluating architecture impact on system energy efficiency

    Science.gov (United States)

    Yu, Shijie; Wang, Rui; Luan, Zhongzhi; Qian, Depei

    2017-01-01

    As the energy consumption has been surging in an unsustainable way, it is important to understand the impact of existing architecture designs from energy efficiency perspective, which is especially valuable for High Performance Computing (HPC) and datacenter environment hosting tens of thousands of servers. One obstacle hindering the advance of comprehensive evaluation on energy efficiency is the deficient power measuring approach. Most of the energy study relies on either external power meters or power models, both of these two methods contain intrinsic drawbacks in their practical adoption and measuring accuracy. Fortunately, the advent of Intel Running Average Power Limit (RAPL) interfaces has promoted the power measurement ability into next level, with higher accuracy and finer time resolution. Therefore, we argue it is the exact time to conduct an in-depth evaluation of the existing architecture designs to understand their impact on system energy efficiency. In this paper, we leverage representative benchmark suites including serial and parallel workloads from diverse domains to evaluate the architecture features such as Non Uniform Memory Access (NUMA), Simultaneous Multithreading (SMT) and Turbo Boost. The energy is tracked at subcomponent level such as Central Processing Unit (CPU) cores, uncore components and Dynamic Random-Access Memory (DRAM) through exploiting the power measurement ability exposed by RAPL. The experiments reveal non-intuitive results: 1) the mismatch between local compute and remote memory node caused by NUMA effect not only generates dramatic power and energy surge but also deteriorates the energy efficiency significantly; 2) for multithreaded application such as the Princeton Application Repository for Shared-Memory Computers (PARSEC), most of the workloads benefit a notable increase of energy efficiency using SMT, with more than 40% decline in average power consumption; 3) Turbo Boost is effective to accelerate the workload execution

  16. DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency

    Directory of Open Access Journals (Sweden)

    Sébastien Pillement

    2007-12-01

    Full Text Available Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13 μm CMOS SoC implementing a specialized DART cluster is presented.

  17. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  18. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  19. Learning and optimization with cascaded VLSI neural network building-block chips

    Science.gov (United States)

    Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

    1992-01-01

    To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

  20. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  1. All passive architecture for high efficiency cascaded Raman conversion

    Science.gov (United States)

    Balaswamy, V.; Arun, S.; Chayran, G.; Supradeepa, V. R.

    2018-02-01

    Cascaded Raman fiber lasers have offered a convenient method to obtain scalable, high-power sources at various wavelength regions inaccessible with rare-earth doped fiber lasers. A limitation previously was the reduced efficiency of these lasers. Recently, new architectures have been proposed to enhance efficiency, but this came at the cost of enhanced complexity, requiring an additional low-power, cascaded Raman laser. In this work, we overcome this with a new, all-passive architecture for high-efficiency cascaded Raman conversion. We demonstrate our architecture with a fifth-order cascaded Raman converter from 1117nm to 1480nm with output power of ~64W and efficiency of 60%.

  2. An Area Efficient Composed CORDIC Architecture

    Directory of Open Access Journals (Sweden)

    AGUIRRE-RAMOS, F.

    2014-05-01

    Full Text Available This article presents a composed architecture for the CORDIC algorithm. CORDIC is a widely used technique to calculate basic trigonometric functions using only additions and shifts. This composed architecture combines an initial coarse stage to approximate sine and cosine functions, and a second stage to finely tune those values while CORDIC operates on rotation mode. Both stages contribute to shorten the algorithmic steps required to fully execute the CORDIC algorithm. For comparison purposes, the Xilinx CORDIC logiCORE IP and previously reported research are used. The proposed architecture aims at reducing hardware resources usage as its key objective.

  3. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...

  4. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  5. VLSI Technology for Cognitive Radio

    Science.gov (United States)

    VIJAYALAKSHMI, B.; SIDDAIAH, P.

    2017-08-01

    One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

  6. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  7. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  8. "ENERGY-EFFICIENT ARCHITECTURE" PARADIGMA DAN MANIFESTASI ARSITEKTUR HIJAU

    Directory of Open Access Journals (Sweden)

    Jimmy Priatman

    2002-01-01

    Full Text Available Energy adds a new standpoint from which to better understand building design. But the subject of study, architecture and its environmental and social context, is not new. The objective of design is to improve the quality of buildings and the environment. On broader perspective, the mentioned environment means global environment encompasses earth, air, water and energy that are needed to be conserved. Energy-efficient architecture is one of that architectural typology focuses on conservation of global environment. The paper discusses the existence of energy-efficient architecture and its contextual to green architecture. Abstract in Bahasa Indonesia : Faktor energi menambah suatu pijakan baru untuk memahami perencanaan arsitektur secara lebih baik. Tetapi sebenarnya, subyek arsitektur dan konteks lingkungannya bukanlah suatu hal yang baru., karena tujuan dari suatu disain adalah untuk meningkatkan kwalitas dari hasil arsitektur dan lingkungannya. Dalam perspektif lebih luas, lingkungan yang dimaksud adalah lingkungan global alami yang meliputi unsur bumi, udara, air, dan energi yang perlu dilestarikan. Arsitektur Hemat Energi merupakan salah satu tipologi arsitektur yang ber-orientasi pada konservasi lingkungan global alami. Makalah ini membahas eksistensi arsitektur hemat energi ini dalam konteks wawasan arsitektur hijau (green architecture. Kata kunci: Arsitektur Hemat Energi, Arsitektur Hijau.

  9. Area-Efficient VLSI Computation.

    Science.gov (United States)

    1981-10-01

    1.2 A Simple Systolic Priority Queue Before we begin a formal treatment of systolic systems, it is worthwhile to consider an example. Many...be omput on the right, much as corn gocs through ith: 11N malid. \\ Vih , 1,,1 pir flF’lLk IlCks. 111C pri, ri. (1 ’lcuc ik, r1,cR l’d 1) cC I1.Ic U

  10. Computer Architecture Techniques for Power-Efficiency

    CERN Document Server

    Kaxiras, Stefanos

    2008-01-01

    In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these

  11. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  12. Achieving Energy Efficiency in Accordance with Bioclimatic Architecture Principles

    Directory of Open Access Journals (Sweden)

    Bajcinovci Bujar

    2016-12-01

    Full Text Available By using our natural resources, and through inefficient use of energy, we produce much waste that can be recycled as a useful resource, which further contributes to climate change. This study aims to address energy effective bioclimatic architecture principles, by which we can achieve a potential energy savings, estimated at thirty-three per cent, mainly through environmentally affordable reconstruction, resulting in low negative impact on the environment. The study presented in this paper investigated the Ulpiana neighbourhood of Prishtina City, focusing on urban design challenges, energy efficiency and air pollution issues. The research methods consist of empirical observations through the urban spatial area using a comparative method, in order to receive clearer data and information research is conducted within Ulpiana’s urban blocks, shapes of architectural structures, with the objective focusing on bioclimatic features in terms of the morphology and microclimate of Ulpiana. Energy supply plays a key role in the economic development of any country, hence, bioclimatic design principles for sustainable architecture and energy efficiency, present an evolutive integrated strategy for achieving efficiency and healthier conditions for Kosovar communities. Conceptual findings indicate that with the integrated design strategy: energy efficiency, and passive bioclimatic principles will result in a bond of complex interrelation between nature, architecture, and community. The aim of this study is to promote structured organized actions to be taken in Prishtina, and Kosovo, which will result in improved energy efficiency in all sectors, and particularly in the residential housing sector.

  13. Achieving Energy Efficiency in Accordance with Bioclimatic Architecture Principles

    Science.gov (United States)

    Bajcinovci, Bujar; Jerliu, Florina

    2016-12-01

    By using our natural resources, and through inefficient use of energy, we produce much waste that can be recycled as a useful resource, which further contributes to climate change. This study aims to address energy effective bioclimatic architecture principles, by which we can achieve a potential energy savings, estimated at thirty-three per cent, mainly through environmentally affordable reconstruction, resulting in low negative impact on the environment. The study presented in this paper investigated the Ulpiana neighbourhood of Prishtina City, focusing on urban design challenges, energy efficiency and air pollution issues. The research methods consist of empirical observations through the urban spatial area using a comparative method, in order to receive clearer data and information research is conducted within Ulpiana's urban blocks, shapes of architectural structures, with the objective focusing on bioclimatic features in terms of the morphology and microclimate of Ulpiana. Energy supply plays a key role in the economic development of any country, hence, bioclimatic design principles for sustainable architecture and energy efficiency, present an evolutive integrated strategy for achieving efficiency and healthier conditions for Kosovar communities. Conceptual findings indicate that with the integrated design strategy: energy efficiency, and passive bioclimatic principles will result in a bond of complex interrelation between nature, architecture, and community. The aim of this study is to promote structured organized actions to be taken in Prishtina, and Kosovo, which will result in improved energy efficiency in all sectors, and particularly in the residential housing sector.

  14. Efficient architecture for global elimination algorithm for H. 264 ...

    Indian Academy of Sciences (India)

    Home; Journals; Sadhana; Volume 41; Issue 1. Efficient ... Fast block matching motion estimation; global elimination; matching complexity reduction; power reduction. ... The proposed architecture is based on Global Elimination (GE) Algorithm, which uses pixel averaging to reduce complexity of motion search while keeping ...

  15. Passive solar energy-efficient architectural building Design ...

    African Journals Online (AJOL)

    In this paper analyses have been done on the climate data for various climatic regions in North Cyprus to obtain physical architectural building design specification with a view to develop passive solar energy-efficient building. It utilizes a computer program, ARCHIPAK, together with climate data (for 25 year period) to get ...

  16. Efficient architecture for spike sorting in reconfigurable hardware.

    Science.gov (United States)

    Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

    2013-11-01

    This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

  17. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  18. Summary of workshop on the application of VLSI for robotic sensing

    Science.gov (United States)

    Brooks, T.; Wilcox, B.

    1984-01-01

    It was one of the objectives of the considered workshop to identify near, mid, and far-term applications of VLSI for robotic sensing and sensor data preprocessing. The workshop was also to indicate areas in which VLSI technology can provide immediate and future payoffs. A third objective is related to the promotion of dialog and collaborative efforts between research communities, industry, and government. The workshop was held on March 24-25, 1983. Conclusions and recommendations are discussed. Attention is given to the need for a pixel correction chip, an image sensor with 10,000 dynamic range, VLSI enhanced architectures, the need for a high-density serpentine memory, an LSI-tactile sensing program, an analog-signal preprocessor chip, a smart strain gage, a protective proximity envelope, a VLSI-proximity sensor program, a robot-net chip, and aspects of silicon micromechanics.

  19. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  20. Modular, Parallel Pulse-Shaping Filter Architectures

    Science.gov (United States)

    Gray, Andrew A.

    2003-01-01

    Novel architectures based on parallel subconvolution frequency-domain filtering methods have been developed for modular processing rate reduction of discrete-time pulse-shaping filters. Such pulse-shaping is desirable and often necessary to obtain bandwidth efficiency in very-high-rate wireless communications systems. In principle, this processing could be implemented in very-large-scale integrated (VLSI) circuits. Whereas other approaches to digital pulse-shaping are based primarily on time-domain processing concepts, the theory and design rules of the architectures presented here are founded on frequency-domain processing that has advantages in certain systems.

  1. High-Efficient Parallel CAVLC Encoders on Heterogeneous Multicore Architectures

    Directory of Open Access Journals (Sweden)

    H. Y. Su

    2012-04-01

    Full Text Available This article presents two high-efficient parallel realizations of the context-based adaptive variable length coding (CAVLC based on heterogeneous multicore processors. By optimizing the architecture of the CAVLC encoder, three kinds of dependences are eliminated or weaken, including the context-based data dependence, the memory accessing dependence and the control dependence. The CAVLC pipeline is divided into three stages: two scans, coding, and lag packing, and be implemented on two typical heterogeneous multicore architectures. One is a block-based SIMD parallel CAVLC encoder on multicore stream processor STORM. The other is a component-oriented SIMT parallel encoder on massively parallel architecture GPU. Both of them exploited rich data-level parallelism. Experiments results show that compared with the CPU version, more than 70 times of speedup can be obtained for STORM and over 50 times for GPU. The implementation of encoder on STORM can make a real-time processing for 1080p @30fps and GPU-based version can satisfy the requirements for 720p real-time encoding. The throughput of the presented CAVLC encoders is more than 10 times higher than that of published software encoders on DSP and multicore platforms.

  2. Declarative Descriptions for VLSI Generators

    Science.gov (United States)

    1986-06-01

    will review languages in each category. Sheeran [ Sheeran 83] proposes a structured hierarchical design language, IL, FP (a variation of the...IEEE, 1982. [ Sheeran 83] Mary Sheeran . p& FP -An Algebraic VLSI Design Language. PhD thesis, Oxford University Computing Laboratory, November, 1983

  3. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  4. Enabling High Efficiency Nanoplasmonics with Novel Nanoantenna Architectures

    Science.gov (United States)

    Cohen, Moshik; Shavit, Reuven; Zalevsky, Zeev

    2015-12-01

    Surface plasmon polaritons (SPPs) are propagating excitations that arise from coupling of light with collective electron oscillations. Characterized by high field intensity and nanometric dimensions, SPPs fashion rapid expansion of interest from fundamental and applicative perspectives. However, high metallic losses at optical frequencies still make nanoplasmonics impractical when high absolute efficiency is paramount, with major challenge is efficient plasmon generation in deep nanoscale. Here we introduce the Plantenna, the first reported nanodevice with the potential of addressing these limitations utilizing novel plasmonic architecture. The Plantenna has simple 2D structure, ultracompact dimensions and is fabricated on Silicon chip for future CMOS integration. We design the Plantenna to feed channel (20 nm × 20 nm) nanoplasmonic waveguides, achieving 52% coupling efficiency with Plantenna dimensions of λ3/17,000. We theoretically and experimentally show that the Plantenna enormously outperforms dipole couplers, achieving 28 dB higher efficiency with broad polarization diversity and huge local field enhancement. Our findings confirm the Plantenna as enabling device for high efficiency plasmonic technologies such as quantum nanoplasmonics, molecular strong coupling and plasmon nanolasers.

  5. A Coherent VLSI Design Environment.

    Science.gov (United States)

    1985-03-31

    We would like to acknowledge the contributions by Flavio Rose of MIT when we first studied this problem. The three of us originally produced a O(1V13...Rinehart and Winston, New York, 1976. 18] Charles E. Leiserson, Flavio M. Rose, and James B. Saxe, "Optimizing synchronous circuitry by retiming... Flavio M. Rose, Models for VLSI CircuiLs, Masters Thesis, Department of Electrical En- gineering and Computer Science, Massachusetts Institute of

  6. An energy-efficient architecture for internet of things systems

    Science.gov (United States)

    De Rango, Floriano; Barletta, Domenico; Imbrogno, Alessandro

    2016-05-01

    In this paper some of the motivations for energy-efficient communications in wireless systems are described by highlighting emerging trends and identifying some challenges that need to be addressed to enable novel, scalable and energy-efficient communications. So an architecture for Internet of Things systems is presented, the purpose of which is to minimize energy consumption by communication devices, protocols, networks, end-user systems and data centers. Some electrical devices have been designed with multiple communication interfaces, such as RF or WiFi, using open source technology; they have been analyzed under different working conditions. Some devices are programmed to communicate directly with a web server, others to communicate only with a special device that acts as a bridge between some devices and the web server. Communication parameters and device status have been changed dynamically according to different scenarios in order to have the most benefits in terms of energy cost and battery lifetime. So the way devices communicate with the web server or between each other and the way they try to obtain the information they need to be always up to date change dynamically in order to guarantee always the lowest energy consumption, a long lasting battery lifetime, the fastest responses and feedbacks and the best quality of service and communication for end users and inner devices of the system.

  7. Learning Methods for Efficient Adoption of Contemporary Technologies in Architectural Design

    Science.gov (United States)

    Mahdavinejad, Mohammadjavad; Dehghani, Sohaib; Shahsavari, Fatemeh

    2013-01-01

    The interaction between technology and history is one of the most significant issues in achieving an efficient and progressive architecture in any era. This is a concept which stems from lesson of traditional architecture of Iran. Architecture as a part of art, has permanently been transforming just like a living organism. In fact, it has been…

  8. Efficiency of High Order Spectral Element Methods on Petascale Architectures

    KAUST Repository

    Hutchinson, Maxwell

    2016-06-14

    High order methods for the solution of PDEs expose a tradeoff between computational cost and accuracy on a per degree of freedom basis. In many cases, the cost increases due to higher arithmetic intensity while affecting data movement minimally. As architectures tend towards wider vector instructions and expect higher arithmetic intensities, the best order for a particular simulation may change. This study highlights preferred orders by identifying the high order efficiency frontier of the spectral element method implemented in Nek5000 and NekBox: the set of orders and meshes that minimize computational cost at fixed accuracy. First, we extract Nek’s order-dependent computational kernels and demonstrate exceptional hardware utilization by hardware-aware implementations. Then, we perform productionscale calculations of the nonlinear single mode Rayleigh-Taylor instability on BlueGene/Q and Cray XC40-based supercomputers to highlight the influence of the architecture. Accuracy is defined with respect to physical observables, and computational costs are measured by the corehour charge of the entire application. The total number of grid points needed to achieve a given accuracy is reduced by increasing the polynomial order. On the XC40 and BlueGene/Q, polynomial orders as high as 31 and 15 come at no marginal cost per timestep, respectively. Taken together, these observations lead to a strong preference for high order discretizations that use fewer degrees of freedom. From a performance point of view, we demonstrate up to 60% full application bandwidth utilization at scale and achieve ≈1PFlop/s of compute performance in Nek’s most flop-intense methods.

  9. Marginal Space Deep Learning: Efficient Architecture for Volumetric Image Parsing.

    Science.gov (United States)

    Ghesu, Florin C; Krubasik, Edward; Georgescu, Bogdan; Singh, Vivek; Yefeng Zheng; Hornegger, Joachim; Comaniciu, Dorin

    2016-05-01

    Robust and fast solutions for anatomical object detection and segmentation support the entire clinical workflow from diagnosis, patient stratification, therapy planning, intervention and follow-up. Current state-of-the-art techniques for parsing volumetric medical image data are typically based on machine learning methods that exploit large annotated image databases. Two main challenges need to be addressed, these are the efficiency in scanning high-dimensional parametric spaces and the need for representative image features which require significant efforts of manual engineering. We propose a pipeline for object detection and segmentation in the context of volumetric image parsing, solving a two-step learning problem: anatomical pose estimation and boundary delineation. For this task we introduce Marginal Space Deep Learning (MSDL), a novel framework exploiting both the strengths of efficient object parametrization in hierarchical marginal spaces and the automated feature design of Deep Learning (DL) network architectures. In the 3D context, the application of deep learning systems is limited by the very high complexity of the parametrization. More specifically 9 parameters are necessary to describe a restricted affine transformation in 3D, resulting in a prohibitive amount of billions of scanning hypotheses. The mechanism of marginal space learning provides excellent run-time performance by learning classifiers in clustered, high-probability regions in spaces of gradually increasing dimensionality. To further increase computational efficiency and robustness, in our system we learn sparse adaptive data sampling patterns that automatically capture the structure of the input. Given the object localization, we propose a DL-based active shape model to estimate the non-rigid object boundary. Experimental results are presented on the aortic valve in ultrasound using an extensive dataset of 2891 volumes from 869 patients, showing significant improvements of up to 45

  10. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  11. Security Policy Scheme for an Efficient Security Architecture in Software-Defined Networking

    Directory of Open Access Journals (Sweden)

    Woosik Lee

    2017-06-01

    Full Text Available In order to build an efficient security architecture, previous studies have attempted to understand complex system architectures and message flows to detect various attack packets. However, the existing hardware-based single security architecture cannot efficiently handle a complex system structure. To solve this problem, we propose a software-defined networking (SDN policy-based scheme for an efficient security architecture. The proposed scheme considers four policy functions: separating, chaining, merging, and reordering. If SDN network functions virtualization (NFV system managers use these policy functions to deploy a security architecture, they only submit some of the requirement documents to the SDN policy-based architecture. After that, the entire security network can be easily built. This paper presents information about the design of a new policy functions model, and it discusses the performance of this model using theoretical analysis.

  12. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  13. Energy Efficiency in Architecture – a Technical Obstacle or a Chance to Find new Forms?

    Directory of Open Access Journals (Sweden)

    Shchepetkov Nikolai

    2016-01-01

    Full Text Available The article exposes innovative materials and structures for improving the energy efficiency of lightning in architecture. The problem of architectural energy efficiency and its part – energy saving illumination of rooms and urban environment is very actual in developing countries. This problem can be successfully solved only by a complex of architectural, constructional, electrical and technological measures which will lead to new forms in architecture and lightning design. This article briefly reviews the benefits of light pipes technologies to enhance natural illumination of deep plan buildings.

  14. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  15. Efficient phase unwrapping architecture for digital holographic microscopy.

    Science.gov (United States)

    Hwang, Wen-Jyi; Cheng, Shih-Chang; Cheng, Chau-Jern

    2011-01-01

    This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize throughput of the computation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system.

  16. Information architecture and exchange mechanisms for efficient transport concepts

    NARCIS (Netherlands)

    Johan Blok; Jacob Mulder

    2015-01-01

    Best practice guide on creating an IT architecture that supports smart mobility services. Joint work of Karlstad University and Hanze University of Applied Sciences within the Interrg IVb project ITRACT.

  17. Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2011-09-01

    Full Text Available This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM. A fast Fourier transform (FFT based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize through put of thecomputation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system.

  18. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  19. An architecture for efficient reuse in flexible production scenarios

    DEFF Research Database (Denmark)

    Andersen, Rasmus Hasle; Dalgaard, Lars; Beck, Anders Billesø

    2015-01-01

    Traditionally, small batch production has not been automated - it has been too resource demanding compared to the expected benefit. However, this is set to change with the new developments in easily trainable robotic co-worker systems, capable of being adapted to new tasks through intuitive user...... interaction. The main concern addressed in this paper is the creation of an architecture, which facilitates flexible robotic systems, and enables hardware-independent system configuration, while providing users of the system with the possibility to instruct and modify process descriptions for industrial tasks....... We present the DTI Robot CoWorker architecture, which is a generic robotic architecture, which provides a system-independent execution framework for adaptive and interactive robotic applications. Our approach has proven viable as we have successfully automated a complicated integration task (among...

  20. Efficient Aho-Corasick String Matching on Emerging Multicore Architectures

    Energy Technology Data Exchange (ETDEWEB)

    Tumeo, Antonino; Villa, Oreste; Secchi, Simone; Chavarría-Miranda, Daniel

    2013-12-12

    String matching algorithms are critical to several scientific fields. Beside text processing and databases, emerging applications such as DNA protein sequence analysis, data mining, information security software, antivirus, ma- chine learning, all exploit string matching algorithms [3]. All these applica- tions usually process large quantity of textual data, require high performance and/or predictable execution times. Among all the string matching algorithms, one of the most studied, especially for text processing and security applica- tions, is the Aho-Corasick algorithm. 1 2 Book title goes here Aho-Corasick is an exact, multi-pattern string matching algorithm which performs the search in a time linearly proportional to the length of the input text independently from pattern set size. However, depending on the imple- mentation, when the number of patterns increase, the memory occupation may raise drastically. In turn, this can lead to significant variability in the performance, due to the memory access times and the caching effects. This is a significant concern for many mission critical applications and modern high performance architectures. For example, security applications such as Network Intrusion Detection Systems (NIDS), must be able to scan network traffic against very large dictionaries in real time. Modern Ethernet links reach up to 10 Gbps, and malicious threats are already well over 1 million, and expo- nentially growing [28]. When performing the search, a NIDS should not slow down the network, or let network packets pass unchecked. Nevertheless, on the current state-of-the-art cache based processors, there may be a large per- formance variability when dealing with big dictionaries and inputs that have different frequencies of matching patterns. In particular, when few patterns are matched and they are all in the cache, the procedure is fast. Instead, when they are not in the cache, often because many patterns are matched and the caches are

  1. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  2. Full custom VLSI - A technology for high performance computing

    Science.gov (United States)

    Maki, Gary K.; Whitaker, Sterling R.

    1990-01-01

    Full custom VLSI is presented as a viable technology for addressing the need for the computing capabilities required for the real-time health monitoring of spacecraft systems. This technology presents solutions that cannot be realized with stored program computers or semicustom VLSI; also, it is not dependent on current IC processes. It is argued that, while design time is longer, full custom VLSI produces the fastest and densest VLSI solution and that high density normally also yields low manufacturing costs.

  3. A secure and efficiently searchable health information architecture.

    Science.gov (United States)

    Yasnoff, William A

    2016-06-01

    Patient-centric repositories of health records are an important component of health information infrastructure. However, patient information in a single repository is potentially vulnerable to loss of the entire dataset from a single unauthorized intrusion. A new health record storage architecture, the personal grid, eliminates this risk by separately storing and encrypting each person's record. The tradeoff for this improved security is that a personal grid repository must be sequentially searched since each record must be individually accessed and decrypted. To allow reasonable search times for large numbers of records, parallel processing with hundreds (or even thousands) of on-demand virtual servers (now available in cloud computing environments) is used. Estimated search times for a 10 million record personal grid using 500 servers vary from 7 to 33min depending on the complexity of the query. Since extremely rapid searching is not a critical requirement of health information infrastructure, the personal grid may provide a practical and useful alternative architecture that eliminates the large-scale security vulnerabilities of traditional databases by sacrificing unnecessary searching speed. Copyright © 2016 Elsevier Inc. All rights reserved.

  4. Transforming the existing building stock to high performed energy efficient and experienced architecture

    DEFF Research Database (Denmark)

    Vestergaard, Inge

    The project Sustainable Renovation examines the challenge of the current and future architectural renovation of Danish suburbs which were designed in the period from 1945 to 1973. The research project takes its starting point in the perspectives of energy optimization and the fact that the building...... architectural heritage to energy efficiency and from architectural quality to sustainability. The first, second and third renovations are discussed from financial and sustainable view points. The role of housing related to the public energy supply system and the relation between the levels of renovation...... process over the period changed from craftsmanship to industrialized production of housing. The aim is to present the context in which energy transformation has to be seen as an architectural question. The research field focuses on social housing blocks and expands the discussion of architecture from...

  5. DNA Fountain enables a robust and efficient storage architecture.

    Science.gov (United States)

    Erlich, Yaniv; Zielinski, Dina

    2017-03-03

    DNA is an attractive medium to store digital information. Here we report a storage strategy, called DNA Fountain, that is highly robust and approaches the information capacity per nucleotide. Using our approach, we stored a full computer operating system, movie, and other files with a total of 2.14 × 106 bytes in DNA oligonucleotides and perfectly retrieved the information from a sequencing coverage equivalent to a single tile of Illumina sequencing. We also tested a process that can allow 2.18 × 1015 retrievals using the original DNA sample and were able to perfectly decode the data. Finally, we explored the limit of our architecture in terms of bytes per molecule and obtained a perfect retrieval from a density of 215 petabytes per gram of DNA, orders of magnitude higher than previous reports. Copyright © 2017, American Association for the Advancement of Science.

  6. Centralized and Modular Architectures for Photovoltaic Panels with Improved Efficiency: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Dhakal, B.; Mancilla-David, F.; Muljadi, E.

    2012-07-01

    The most common type of photovoltaic installation in residential applications is the centralized architecture, but the performance of a centralized architecture is adversely affected when it is subject to partial shading effects due to clouds or surrounding obstacles, such as trees. An alternative modular approach can be implemented using several power converters with partial throughput power processing capability. This paper presents a detailed study of these two architectures for the same throughput power level and compares the overall efficiencies using a set of rapidly changing real solar irradiance data collected by the Solar Radiation Research Laboratory at the National Renewable Energy Laboratory.

  7. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  8. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  9. Use of polyimides in VLSI fabrication

    Science.gov (United States)

    Wilson, A. M.

    The functional requirements of overcoats and multilevel insulators for very large scale integrated circuits (VLSI) are outlined. The moisture barrier properties of polyimide films are reviewed. Polyimide performance vs plasma enhanced chemically vapor deposited (CVD) silicon nitride overcoats are compared. The topological and via forming advantages of polyimides vs plasma enhanced CVD silicon oxide as a multilevel insulator are cited. The temperature and voltage field induced electronic charge transport and trapping at oxide interfaces is cited as the most serious limitation to the use of polyimides as multilevel insulators on VLSI chips.

  10. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

    Science.gov (United States)

    Sharma, Anuj; Manolakos, Elias S

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

  11. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures

    Science.gov (United States)

    Manolakos, Elias S.

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

  12. An Efficient Connected Component Labeling Architecture for Embedded Systems

    Directory of Open Access Journals (Sweden)

    Fanny Spagnolo

    2018-03-01

    Full Text Available Connected component analysis is one of the most fundamental steps used in several image processing systems. This technique allows for distinguishing and detecting different objects in images by assigning a unique label to all pixels that refer to the same object. Most of the previous published algorithms have been designed for implementation by software. However, due to the large number of memory accesses and compare, lookup, and control operations when executed on a general-purpose processor, they do not satisfy the speed performance required by the next generation high performance computer vision systems. In this paper, we present the design of a new Connected Component Labeling hardware architecture suitable for high performance heterogeneous image processing of embedded designs. When implemented on a Zynq All Programmable-System on Chip (AP-SOC 7045 chip, the proposed design allows a throughput rate higher of 220 Mpixels/s to be reached using less than 18,000 LUTs and 5000 FFs, dissipating about 620 μJ.

  13. Efficient Ada multitasking on a RISC register window architecture

    Science.gov (United States)

    Kearns, J. P.; Quammen, D.

    1987-01-01

    This work addresses the problem of reducing context switch overhead on a processor which supports a large register file - a register file much like that which is part of the Berkeley RISC processors and several other emerging architectures (which are not necessarily reduced instruction set machines in the purest sense). Such a reduction in overhead is particularly desirable in a real-time embedded application, in which task-to-task context switch overhead may result in failure to meet crucial deadlines. A storage management technique by which a context switch may be implemented as cheaply as a procedure call is presented. The essence of this technique is the avoidance of the save/restore of registers on the context switch. This is achieved through analysis of the static source text of an Ada tasking program. Information gained during that analysis directs the optimized storage management strategy for that program at run time. A formal verification of the technique in terms of an operational control model and an evaluation of the technique's performance via simulations driven by synthetic Ada program traces are presented.

  14. Efficient BinDCT hardware architecture exploration and implementation on FPGA.

    Science.gov (United States)

    Ben Abdelali, Abdessalem; Chatti, Ichraf; Hannachi, Marwa; Mtibaa, Abdellatif

    2016-11-01

    This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

  15. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  16. A systolic architecture for the correlation and accumulation of digital sequences

    Science.gov (United States)

    Deutsch, L. J.; Lahmeyer, C. R.

    1986-01-01

    A fully systolic architecture for the implementation of digital sequence correlator/accumulators is described. These devices consist of a two-dimensional array of processing elements that are conceived for efficient fabrication in Very Large Scale Integrated (VLSI) circuits. A custom VLSI chip that was implemented using these concepts is described. The chip, which contains a four-lag three-level sequence correlator and four bits of accumulation with overflow detection, was designed using the Integrated UNIX-Based Computer Aided Design (CAD) System. Applications of such devices include the synchronization of coded telemetry data, alignment of both real time and non-real time Very Large Baseline Interferometry (VLBI) signals, and the implementation of digital filters and processes of many types.

  17. An efficient FPGA architecture for integer ƞth root computation

    Science.gov (United States)

    Rangel-Valdez, Nelson; Barron-Zambrano, Jose Hugo; Torres-Huitzil, Cesar; Torres-Jimenez, Jose

    2015-10-01

    In embedded computing, it is common to find applications such as signal processing, image processing, computer graphics or data compression that might benefit from hardware implementation for the computation of integer roots of order ?. However, the scientific literature lacks architectural designs that implement such operations for different values of N, using a low amount of resources. This article presents a parameterisable field programmable gate array (FPGA) architecture for an efficient Nth root calculator that uses only adders/subtractors and ? location memory elements. The architecture was tested for different values of ?, using 64-bit number representation. The results show a consumption up to 10% of the logical resources of a Xilinx XC6SLX45-CSG324C device, depending on the value of N. The hardware implementation improved the performance of its corresponding software implementations in one order of magnitude. The architecture performance varies from several thousands to seven millions of root operations per second.

  18. Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

    Science.gov (United States)

    Ou, Chien-Min; Li, Hui-Ya; Hwang, Wen-Jyi

    2012-01-01

    A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

  19. An Energy Efficient Instruction Window for Scalable Processor Architecture

    Science.gov (United States)

    Choi, Min; Maeng, Seungryoul

    Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the small reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption. Second, we replace a conventional issue queue by a direct lookup table (DLT) with an efficient tag translation technique. The translation scheme resolves the instruction dependency, especially for the case of one producer to multiple consumers. The efficiency of the translation scheme stems from the fact that the vast majority of instruction dependency exists within a basic block. Experimental results show that our proposed design reduces the power consumption significantly for SPEC2000 benchmarks.

  20. Techniques for Enabling Highly Efficient Message Passing on Many-Core Architectures

    Energy Technology Data Exchange (ETDEWEB)

    Si, Min; Balaji, Pavan; Ishikawa, Yutaka

    2015-01-01

    Many-core architecture provides a massively parallel environment with dozens of cores and hundreds of hardware threads. Scientific application programmers are increasingly looking at ways to utilize such large numbers of lightweight cores for various programming models. Efficiently executing these models on massively parallel many-core environments is not easy, however and performance may be degraded in various ways. The first author's doctoral research focuses on exploiting the capabilities of many-core architectures on widely used MPI implementations. While application programmers have studied several approaches to achieve better parallelism and resource sharing, many of those approaches still face communication problems that degrade performance. In the thesis, we investigate the characteristics of MPI on such massively threaded architectures and propose two efficient strategies -- a multi-threaded MPI approach and a process-based asynchronous model -- to optimize MPI communication for modern scientific applications.

  1. High efficiency video coding (HEVC) algorithms and architectures

    CERN Document Server

    Budagavi, Madhukar; Sullivan, Gary

    2014-01-01

    This book provides developers, engineers, researchers and students with detailed knowledge about the High Efficiency Video Coding (HEVC) standard. HEVC is the successor to the widely successful H.264/AVC video compression standard, and it provides around twice as much compression as H.264/AVC for the same level of quality. The applications for HEVC will not only cover the space of the well-known current uses and capabilities of digital video – they will also include the deployment of new services and the delivery of enhanced video quality, such as ultra-high-definition television (UHDTV) and video with higher dynamic range, wider range of representable color, and greater representation precision than what is typically found today. HEVC is the next major generation of video coding design – a flexible, reliable and robust solution that will support the next decade of video applications and ease the burden of video on world-wide network traffic. This book provides a detailed explanation of the various parts ...

  2. Area and power efficient DCT architecture for image compression

    Science.gov (United States)

    Dhandapani, Vaithiyanathan; Ramachandran, Seshasayanan

    2014-12-01

    The discrete cosine transform (DCT) is one of the major components in image and video compression systems. The final output of these systems is interpreted by the human visual system (HVS), which is not perfect. The limited perception of human visualization allows the algorithm to be numerically approximate rather than exact. In this paper, we propose a new matrix for discrete cosine transform. The proposed 8 × 8 transformation matrix contains only zeros and ones which requires only adders, thus avoiding the need for multiplication and shift operations. The new class of transform requires only 12 additions, which highly reduces the computational complexity and achieves a performance in image compression that is comparable to that of the existing approximated DCT. Another important aspect of the proposed transform is that it provides an efficient area and power optimization while implementing in hardware. To ensure the versatility of the proposal and to further evaluate the performance and correctness of the structure in terms of speed, area, and power consumption, the model is implemented on Xilinx Virtex 7 field programmable gate array (FPGA) device and synthesized with Cadence® RTL Compiler® using UMC 90 nm standard cell library. The analysis obtained from the implementation indicates that the proposed structure is superior to the existing approximation techniques with a 30% reduction in power and 12% reduction in area.

  3. Genetic architecture of feed efficiency in mid-lactation Holstein dairy cows

    Science.gov (United States)

    The objective of this study was to explore the genetic architecture and biological basis of feed efficiency in lactating Holstein cows. In total, 4,918 cows with actual or imputed genotypes for 60,671 SNP had individual feed intake, milk yield, milk composition, and body weight records. Cows were ...

  4. An Efficient, Highly Flexible Multi-Channel Digital Downconverter Architecture

    Science.gov (United States)

    Goodhart, Charles E.; Soriano, Melissa A.; Navarro, Robert; Trinh, Joseph T.; Sigman, Elliott H.

    2013-01-01

    In this innovation, a digital downconverter has been created that produces a large (16 or greater) number of output channels of smaller bandwidths. Additionally, this design has the flexibility to tune each channel independently to anywhere in the input bandwidth to cover a wide range of output bandwidths (from 32 MHz down to 1 kHz). Both the flexibility in channel frequency selection and the more than four orders of magnitude range in output bandwidths (decimation rates from 32 to 640,000) presented significant challenges to be solved. The solution involved breaking the digital downconversion process into a two-stage process. The first stage is a 2 oversampled filter bank that divides the whole input bandwidth as a real input signal into seven overlapping, contiguous channels represented with complex samples. Using the symmetry of the sine and cosine functions in a similar way to that of an FFT (fast Fourier transform), this downconversion is very efficient and gives seven channels fixed in frequency. An arbitrary number of smaller bandwidth channels can be formed from second-stage downconverters placed after the first stage of downconversion. Because of the overlapping of the first stage, there is no gap in coverage of the entire input bandwidth. The input to any of the second-stage downconverting channels has a multiplexer that chooses one of the seven wideband channels from the first stage. These second-stage downconverters take up fewer resources because they operate at lower bandwidths than doing the entire downconversion process from the input bandwidth for each independent channel. These second-stage downconverters are each independent with fine frequency control tuning, providing extreme flexibility in positioning the center frequency of a downconverted channel. Finally, these second-stage downconverters have flexible decimation factors over four orders of magnitude The algorithm was developed to run in an FPGA (field programmable gate array) at input data

  5. NUMERICAL SIMULATION OF DIGITAL VLSI TOTAL DOSE FUNCTIONAL FAILURES

    Directory of Open Access Journals (Sweden)

    O. A. Kalashnikov

    2016-10-01

    Full Text Available The technique for numerical simulation of digital VLSI total dose failures is presented, based on fuzzy logic sets theory. It assumes transfer from boolean logic model of a VLSI with values {0,1} to fuzzy model with continuous interval [0,1], and from boolean logic functions to continuous minimax functions. The technique is realized as a calculation system and allows effective estimating of digital VLSI radiation behavior without experimental investigation.

  6. SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications

    Directory of Open Access Journals (Sweden)

    Liang Cao

    2009-01-01

    Full Text Available This paper presents SmartCell, a novel coarse-grained reconfigurable architecture, which tiles a large number of processor elements with reconfigurable interconnection fabrics on a single chip. SmartCell is able to provide high performance and energy efficient processing for stream-based applications. It can be configured to operate in various modes, such as SIMD, MIMD, and systolic array. This paper describes the SmartCell architecture design, including processing element, reconfigurable interconnection fabrics, instruction and control process, and configuration scheme. The SmartCell prototype with 64 PEs is implemented using 0.13  m CMOS standard cell technology. The core area is about 8.5  , and the power consumption is about 1.6 mW/MHz. The performance is evaluated through a set of benchmark applications, and then compared with FPGA, ASIC, and two well-known reconfigurable architectures including RaPiD and Montium. The results show that the SmartCell can bridge the performance and flexibility gap between ASIC and FPGA. It is also about 8% and 69% more energy efficient than Montium and RaPiD systems for evaluated benchmarks. Meanwhile, SmartCell can achieve 4 and 2 times more throughput gains when comparing with Montium and RaPiD, respectively. It is concluded that SmartCell system is a promising reconfigurable and energy efficient architecture for stream processing.

  7. 3D video coding for embedded devices energy efficient algorithms and architectures

    CERN Document Server

    Zatt, Bruno; Bampi, Sergio; Henkel, Jörg

    2013-01-01

    This book shows readers how to develop energy-efficient algorithms and hardware architectures to enable high-definition 3D video coding on resource-constrained embedded devices.  Users of the Multiview Video Coding (MVC) standard face the challenge of exploiting its 3D video-specific coding tools for increasing compression efficiency at the cost of increasing computational complexity and, consequently, the energy consumption.  This book enables readers to reduce the multiview video coding energy consumption through jointly considering the algorithmic and architectural levels.  Coverage includes an introduction to 3D videos and an extensive discussion of the current state-of-the-art of 3D video coding, as well as energy-efficient algorithms for 3D video coding and energy-efficient hardware architecture for 3D video coding.     ·         Discusses challenges related to performance and power in 3D video coding for embedded devices; ·         Describes energy-efficient algorithms for reduci...

  8. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  9. TECHNOLOGY MAPPING TOOL FOR VLSI CAD

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2017-01-01

    Full Text Available Technology mapping program implements a sequential circuit using the gates of a particular technology library. It is an integral component of any automated VLSI circuit design flow. The structure of the program for solving the technology mapping problem and formats of the source and result data are presented. Models of intermediate representations of the sequential circuit and their conversions are described. Technology mapping is a stage of logic synthesis and it is viewed as the transformation of a functional (i.e., algebraic circuit specification into a gate (i.e., netlist specification. The program is included as project operations in the VLSI CAD system for energy-saving logical synthesis developed in the United Institute of Informatics Problems of NAS of Belarus.

  10. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  11. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  12. Linear discriminant analysis reveals differences in root architecture in wheat seedlings related to nitrogen uptake efficiency.

    Science.gov (United States)

    Kenobi, Kim; Atkinson, Jonathan A; Wells, Darren M; Gaju, Oorbessy; De Silva, Jayalath G; Foulkes, M John; Dryden, Ian L; Wood, Andrew T A; Bennett, Malcolm J

    2017-10-13

    Root architecture impacts water and nutrient uptake efficiency. Identifying exactly which root architectural properties influence these agronomic traits can prove challenging. In this paper, approximately 300 wheat (Triticum aestivum) plants were divided into four groups using two binary classifications, high versus low nitrogen uptake efficiency (NUpE), and high versus low nitrate in the growth medium. The root system architecture for each wheat plant was captured using 16 quantitative variables. The multivariate analysis tool, linear discriminant analysis, was used to construct composite variables, each a linear combination of the original variables, such that the score of the plants on the new variables showed the maximum between-group variability. The results show that the distribution of root-system architecture traits differs between low- and high-NUpE plants and, less strongly, between low-NUpE plants grown on low versus high nitrate media. © The Author 2017. Published by Oxford University Press on behalf of the Society for Experimental Biology.

  13. A VLSI design for universal noiseless coding. [for spacecraft imaging equipment

    Science.gov (United States)

    Lee, Jun-Ji; Fang, Wai-Chi; Rice, Robert F.

    1988-01-01

    The practical, noiseless and efficient data-compression technique presented involves a conceptual VLSI design which is capable of meeting real-time processing rates and meets low-power, low-weight, and small-volume requirements. This form of data compression is applicable to image data compression aboard future low-budget spaceflight missions, for such instruments as visual-IR mapping spectrometers and high-resolution imaging spectrometers.

  14. Comments on `Area and power efficient DCT architecture for image compression' by Dhandapani and Ramachandran

    Science.gov (United States)

    Cintra, Renato J.; Bayer, Fábio M.

    2017-12-01

    In [Dhandapani and Ramachandran, "Area and power efficient DCT architecture for image compression", EURASIP Journal on Advances in Signal Processing 2014, 2014:180] the authors claim to have introduced an approximation for the discrete cosine transform capable of outperforming several well-known approximations in literature in terms of additive complexity. We could not verify the above results and we offer corrections for their work.

  15. A Notation for Describing Multiple Views of VLSI Circuits

    Science.gov (United States)

    1988-06-01

    leaf In the functional programming language pFP cells or abstract objects) and a set of relations among [ Sheeran 83] the behavior specification implies a...A raduate VLSI design class has employed the notation in the design of modules com- [ Sheeran 83] M. Sheeran , "jvFP - An Algebraic VLSI prising a

  16. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  17. Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Schoeberl, Martin; Sørensen, Rasmus Bo

    2016-01-01

    In this paper, we present an area-efficient, globally asynchronous, locally synchronous network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC implements message-passing communication between processor cores. It uses statically scheduled time-division multiplexing...... (TDM) to control the communication over a structure of routers, links, and network interfaces (NIs) to offer real-time guarantees. The area-efficient design is a result of two contributions: 1) asynchronous routers combined with TDM scheduling and 2) a novel NI microarchitecture. Together they result...

  18. Efficient high-precision matrix algebra on parallel architectures for nonlinear combinatorial optimization

    KAUST Repository

    Gunnels, John

    2010-06-01

    We provide a first demonstration of the idea that matrix-based algorithms for nonlinear combinatorial optimization problems can be efficiently implemented. Such algorithms were mainly conceived by theoretical computer scientists for proving efficiency. We are able to demonstrate the practicality of our approach by developing an implementation on a massively parallel architecture, and exploiting scalable and efficient parallel implementations of algorithms for ultra high-precision linear algebra. Additionally, we have delineated and implemented the necessary algorithmic and coding changes required in order to address problems several orders of magnitude larger, dealing with the limits of scalability from memory footprint, computational efficiency, reliability, and interconnect perspectives. © Springer and Mathematical Programming Society 2010.

  19. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  20. Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

    Directory of Open Access Journals (Sweden)

    S. Jayanthy

    2012-01-01

    Full Text Available As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG method based on a modified Fanout Oriented (FAN to detect crosstalk-induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage, less number of backtracks, and hence reduced test generation time for most of the benchmark circuits when compared to modified Path-Oriented Decision Making (PODEM based ATPG. The number of transitions is also reduced thus reducing the power dissipation of the circuit.

  1. Survey on Efficient Linear Solvers for Porous Media Flow Models on Recent Hardware Architectures

    Directory of Open Access Journals (Sweden)

    Anciaux-Sedrakian Ani

    2014-07-01

    Full Text Available In the past few years, High Performance Computing (HPC technologies led to General Purpose Processing on Graphics Processing Units (GPGPU and many-core architectures. These emerging technologies offer massive processing units and are interesting for porous media flow simulators may used for CO2 geological sequestration or Enhanced Oil Recovery (EOR simulation. However the crucial point is “are current algorithms and software able to use these new technologies efficiently?” The resolution of large sparse linear systems, almost ill-conditioned, constitutes the most CPU-consuming part of such simulators. This paper proposes a survey on various solver and preconditioner algorithms, analyzes their efficiency and performance regarding these distinct architectures. Furthermore it proposes a novel approach based on a hybrid programming model for both GPU and many-core clusters. The proposed optimization techniques are validated through a Krylov subspace solver; BiCGStab and some preconditioners like ILU0 on GPU, multi-core and many-core architectures, on various large real study cases in EOR simulation.

  2. EH-GC: An Efficient and Secure Architecture of Energy Harvesting Green Cloud Infrastructure

    Directory of Open Access Journals (Sweden)

    Saurabh Singh

    2017-04-01

    Full Text Available Nowadays, the high power consumption of data centers is the biggest challenge to making cloud computing greener. Many researchers are still seeking effective solutions to reduce or harvest the energy produced at data centers. To address this challenge, we propose a green cloud infrastructure which provides security and efficiency based on energy harvesting (EH-GC. The EH-GC is basically focused on harvesting the heat energy produced by data centers in the Infrastructure-as-a-Service (IaaS infrastructure. A pyroelectric material is used to generate the electric current from heat using the Olsen cycle. In order to achieve efficient green cloud computing, the architecture utilizes a genetic algorithm for proper virtual machine allocation, taking into consideration less Service Level Agreement (SLA violations. The architecture utilizes Multivariate Correlation Analysis (MCA correlation analysis based on a triangular map area generation to detect Denial of Service (DoS attacks in the data center layer of the IaaS. Finally, the experimental analysis is explained based on the energy parameter, which proves that our model is efficient and secure, and that it efficiently reuses the energy emitted from the data center.

  3. AREA EFFICIENT FRACTIONAL SAMPLE RATE CONVERSION ARCHITECTURE FOR SOFTWARE DEFINED RADIOS

    Directory of Open Access Journals (Sweden)

    Latha Sahukar

    2014-09-01

    Full Text Available The modern software defined radios (SDRs use complex signal processing algorithms to realize efficient wireless communication schemes. Several such algorithms require a specific symbol to sample ratio to be maintained. In this context the fractional rate converter (FRC becomes a crucial block in the receiver part of SDR. The paper presents an area optimized dynamic FRC block, for low power SDR applications. The limitations of conventional cascaded interpolator and decimator architecture for FRC are also presented. Extending the SINC function interpolation based architecture; towards high area optimization and providing run time configuration with time register are presented. The area and speed analysis are carried with Xilinx FPGA synthesis tools. Only 15% area occupancy with maximum clock speed of 133 MHz are reported on Spartan-6 Lx45 Field Programmable Gate Array (FPGA.

  4. Gene Transfer Efficiency in Gonococcal Biofilms: Role of Biofilm Age, Architecture, and Pilin Antigenic Variation.

    Science.gov (United States)

    Kouzel, Nadzeya; Oldewurtel, Enno R; Maier, Berenike

    2015-07-01

    Extracellular DNA is an important structural component of many bacterial biofilms. It is unknown, however, to which extent external DNA is used to transfer genes by means of transformation. Here, we quantified the acquisition of multidrug resistance and visualized its spread under selective and nonselective conditions in biofilms formed by Neisseria gonorrhoeae. The density and architecture of the biofilms were controlled by microstructuring the substratum for bacterial adhesion. Horizontal transfer of antibiotic resistance genes between cocultured strains, each carrying a single resistance, occurred efficiently in early biofilms. The efficiency of gene transfer was higher in early biofilms than between planktonic cells. It was strongly reduced after 24 h and independent of biofilm density. Pilin antigenic variation caused a high fraction of nonpiliated bacteria but was not responsible for the reduced gene transfer at later stages. When selective pressure was applied to dense biofilms using antibiotics at their MIC, the double-resistant bacteria did not show a significant growth advantage. In loosely connected biofilms, the spreading of double-resistant clones was prominent. We conclude that multidrug resistance readily develops in early gonococcal biofilms through horizontal gene transfer. However, selection and spreading of the multiresistant clones are heavily suppressed in dense biofilms. Biofilms are considered ideal reaction chambers for horizontal gene transfer and development of multidrug resistances. The rate at which genes are exchanged within biofilms is unknown. Here, we quantified the acquisition of double-drug resistance by gene transfer between gonococci with single resistances. At early biofilm stages, the transfer efficiency was higher than for planktonic cells but then decreased with biofilm age. The surface topography affected the architecture of the biofilm. While the efficiency of gene transfer was independent of the architecture, spreading of

  5. Artwork Analysis Tools for VLSI Circuits.

    Science.gov (United States)

    1980-06-01

    derived frcm the art- work.i~nFo :.- Is zr Code DI t pecal Sculnfv CLA a uPICAT OP T0416 PA*6WM Dine Bftee AMA& -’M Artwork Analysis Tools for VLSI Circuits... code of the program and in pre-generated bit tables. The design rules thcmselves are not input directly into the checker. The rules were interpreted...circuit simulation is swich -level sintulation. In this type, transistors are modeled as switches that are either on or off. Fixed delays are a%.ociated

  6. Wavy channel thin film transistor architecture for area efficient, high performance and low power displays

    KAUST Repository

    Hanna, Amir

    2013-12-23

    We demonstrate a new thin film transistor (TFT) architecture that allows expansion of the device width using continuous fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.5× increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, ~100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers an interesting opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  8. Efficient Machine Learning Approach for Optimizing Scientific Computing Applications on Emerging HPC Architectures

    Energy Technology Data Exchange (ETDEWEB)

    Arumugam, Kamesh [Old Dominion Univ., Norfolk, VA (United States)

    2017-05-01

    Efficient parallel implementations of scientific applications on multi-core CPUs with accelerators such as GPUs and Xeon Phis is challenging. This requires - exploiting the data parallel architecture of the accelerator along with the vector pipelines of modern x86 CPU architectures, load balancing, and efficient memory transfer between different devices. It is relatively easy to meet these requirements for highly structured scientific applications. In contrast, a number of scientific and engineering applications are unstructured. Getting performance on accelerators for these applications is extremely challenging because many of these applications employ irregular algorithms which exhibit data-dependent control-ow and irregular memory accesses. Furthermore, these applications are often iterative with dependency between steps, and thus making it hard to parallelize across steps. As a result, parallelism in these applications is often limited to a single step. Numerical simulation of charged particles beam dynamics is one such application where the distribution of work and memory access pattern at each time step is irregular. Applications with these properties tend to present significant branch and memory divergence, load imbalance between different processor cores, and poor compute and memory utilization. Prior research on parallelizing such irregular applications have been focused around optimizing the irregular, data-dependent memory accesses and control-ow during a single step of the application independent of the other steps, with the assumption that these patterns are completely unpredictable. We observed that the structure of computation leading to control-ow divergence and irregular memory accesses in one step is similar to that in the next step. It is possible to predict this structure in the current step by observing the computation structure of previous steps. In this dissertation, we present novel machine learning based optimization techniques to address

  9. An efficient architecture for the integration of sensor and actuator networks into the future internet

    Science.gov (United States)

    Schneider, J.; Klein, A.; Mannweiler, C.; Schotten, H. D.

    2011-08-01

    In the future, sensors will enable a large variety of new services in different domains. Important application areas are service adaptations in fixed and mobile environments, ambient assisted living, home automation, traffic management, as well as management of smart grids. All these applications will share a common property, the usage of networked sensors and actuators. To ensure an efficient deployment of such sensor-actuator networks, concepts and frameworks for managing and distributing sensor data as well as for triggering actuators need to be developed. In this paper, we present an architecture for integrating sensors and actuators into the future Internet. In our concept, all sensors and actuators are connected via gateways to the Internet, that will be used as comprehensive transport medium. Additionally, an entity is needed for registering all sensors and actuators, and managing sensor data requests. We decided to use a hierarchical structure, comparable to the Domain Name Service. This approach realizes a cost-efficient architecture disposing of "plug and play" capabilities and accounting for privacy issues.

  10. ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

    Directory of Open Access Journals (Sweden)

    V. I. Romanov

    2016-01-01

    Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

  11. Strategies for increasing the efficiency of heterojunction organic solar cells: material selection and device architecture.

    Science.gov (United States)

    Heremans, Paul; Cheyns, David; Rand, Barry P

    2009-11-17

    Thin-film blends or bilayers of donor- and acceptor-type organic semiconductors form the core of heterojunction organic photovoltaic cells. Researchers measure the quality of photovoltaic cells based on their power conversion efficiency, the ratio of the electrical power that can be generated versus the power of incident solar radiation. The efficiency of organic solar cells has increased steadily in the last decade, currently reaching up to 6%. Understanding and combating the various loss mechanisms that occur in processes from optical excitation to charge collection should lead to efficiencies on the order of 10% in the near future. In organic heterojunction solar cells, the generation of photocurrent is a cascade of four steps: generation of excitons (electrically neutral bound electron-hole pairs) by photon absorption, diffusion of excitons to the heterojunction, dissociation of the excitons into free charge carriers, and transport of these carriers to the contacts. In this Account, we review our recent contributions to the understanding of the mechanisms that govern these steps. Starting from archetype donor-acceptor systems of planar small-molecule heterojunctions and solution-processed bulk heterojunctions, we outline our search for alternative materials and device architectures. We show that non-planar phthalocynanines have appealing absorption characteristics but also have reduced charge carrier transport. As a result, the donor layer needs to be ultrathin, and all layers of the device have to be tuned to account for optical interference effects. Using these optimization techniques, we illustrate cells with 3.1% efficiency for the non-planar chloroboron subphthalocyanine donor. Molecules offering a better compromise between absorption and carrier mobility should allow for further improvements. We also propose a method for increasing the exciton diffusion length by converting singlet excitons into long-lived triplets. By doping a polymer with a

  12. Efficient Graph Based Assembly of Short-Read Sequences on Hybrid Core Architecture

    Energy Technology Data Exchange (ETDEWEB)

    Sczyrba, Alex; Pratap, Abhishek; Canon, Shane; Han, James; Copeland, Alex; Wang, Zhong; Brewer, Tony; Soper, David; D' Jamoos, Mike; Collins, Kirby; Vacek, George

    2011-03-22

    Advanced architectures can deliver dramatically increased throughput for genomics and proteomics applications, reducing time-to-completion in some cases from days to minutes. One such architecture, hybrid-core computing, marries a traditional x86 environment with a reconfigurable coprocessor, based on field programmable gate array (FPGA) technology. In addition to higher throughput, increased performance can fundamentally improve research quality by allowing more accurate, previously impractical approaches. We will discuss the approach used by Convey?s de Bruijn graph constructor for short-read, de-novo assembly. Bioinformatics applications that have random access patterns to large memory spaces, such as graph-based algorithms, experience memory performance limitations on cache-based x86 servers. Convey?s highly parallel memory subsystem allows application-specific logic to simultaneously access 8192 individual words in memory, significantly increasing effective memory bandwidth over cache-based memory systems. Many algorithms, such as Velvet and other de Bruijn graph based, short-read, de-novo assemblers, can greatly benefit from this type of memory architecture. Furthermore, small data type operations (four nucleotides can be represented in two bits) make more efficient use of logic gates than the data types dictated by conventional programming models.JGI is comparing the performance of Convey?s graph constructor and Velvet on both synthetic and real data. We will present preliminary results on memory usage and run time metrics for various data sets with different sizes, from small microbial and fungal genomes to very large cow rumen metagenome. For genomes with references we will also present assembly quality comparisons between the two assemblers.

  13. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  14. An Energy-Efficient Multi-Tier Architecture for Fall Detection on Smartphones

    Science.gov (United States)

    Guvensan, M. Amac; Kansiz, A. Oguz; Camgoz, N. Cihan; Turkmen, H. Irem; Yavuz, A. Gokhan; Karsligil, M. Elif

    2017-01-01

    Automatic detection of fall events is vital to providing fast medical assistance to the causality, particularly when the injury causes loss of consciousness. Optimization of the energy consumption of mobile applications, especially those which run 24/7 in the background, is essential for longer use of smartphones. In order to improve energy-efficiency without compromising on the fall detection performance, we propose a novel 3-tier architecture that combines simple thresholding methods with machine learning algorithms. The proposed method is implemented on a mobile application, called uSurvive, for Android smartphones. It runs as a background service and monitors the activities of a person in daily life and automatically sends a notification to the appropriate authorities and/or user defined contacts when it detects a fall. The performance of the proposed method was evaluated in terms of fall detection performance and energy consumption. Real life performance tests conducted on two different models of smartphone demonstrate that our 3-tier architecture with feature reduction could save up to 62% of energy compared to machine learning only solutions. In addition to this energy saving, the hybrid method has a 93% of accuracy, which is superior to thresholding methods and better than machine learning only solutions. PMID:28644378

  15. An Energy-Efficient Multi-Tier Architecture for Fall Detection Using Smartphones.

    Science.gov (United States)

    Guvensan, M Amac; Kansiz, A Oguz; Camgoz, N Cihan; Turkmen, H Irem; Yavuz, A Gokhan; Karsligil, M Elif

    2017-06-23

    Automatic detection of fall events is vital to providing fast medical assistance to the causality, particularly when the injury causes loss of consciousness. Optimization of the energy consumption of mobile applications, especially those which run 24/7 in the background, is essential for longer use of smartphones. In order to improve energy-efficiency without compromising on the fall detection performance, we propose a novel 3-tier architecture that combines simple thresholding methods with machine learning algorithms. The proposed method is implemented on a mobile application, called uSurvive, for Android smartphones. It runs as a background service and monitors the activities of a person in daily life and automatically sends a notification to the appropriate authorities and/or user defined contacts when it detects a fall. The performance of the proposed method was evaluated in terms of fall detection performance and energy consumption. Real life performance tests conducted on two different models of smartphone demonstrate that our 3-tier architecture with feature reduction could save up to 62% of energy compared to machine learning only solutions. In addition to this energy saving, the hybrid method has a 93% of accuracy, which is superior to thresholding methods and better than machine learning only solutions.

  16. Reliable and Efficient Parallel Processing Algorithms and Architectures for Modern Signal Processing. Ph.D. Thesis

    Science.gov (United States)

    Liu, Kuojuey Ray

    1990-01-01

    Least-squares (LS) estimations and spectral decomposition algorithms constitute the heart of modern signal processing and communication problems. Implementations of recursive LS and spectral decomposition algorithms onto parallel processing architectures such as systolic arrays with efficient fault-tolerant schemes are the major concerns of this dissertation. There are four major results in this dissertation. First, we propose the systolic block Householder transformation with application to the recursive least-squares minimization. It is successfully implemented on a systolic array with a two-level pipelined implementation at the vector level as well as at the word level. Second, a real-time algorithm-based concurrent error detection scheme based on the residual method is proposed for the QRD RLS systolic array. The fault diagnosis, order degraded reconfiguration, and performance analysis are also considered. Third, the dynamic range, stability, error detection capability under finite-precision implementation, order degraded performance, and residual estimation under faulty situations for the QRD RLS systolic array are studied in details. Finally, we propose the use of multi-phase systolic algorithms for spectral decomposition based on the QR algorithm. Two systolic architectures, one based on triangular array and another based on rectangular array, are presented for the multiphase operations with fault-tolerant considerations. Eigenvectors and singular vectors can be easily obtained by using the multi-pase operations. Performance issues are also considered.

  17. A new hardware-efficient algorithm and reconfigurable architecture for image contrast enhancement.

    Science.gov (United States)

    Huang, Shih-Chia; Chen, Wen-Chieh

    2014-10-01

    Contrast enhancement is crucial when generating high quality images for image processing applications, such as digital image or video photography, liquid crystal display processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a novel hardware-oriented contrast enhancement algorithm which can be implemented effectively for hardware design. In order to be considered for hardware implementation, approximation techniques are proposed to reduce these complex computations during performance of the contrast enhancement algorithm. The proposed hardware-oriented contrast enhancement algorithm achieves good image quality by measuring the results of qualitative and quantitative analyzes. To decrease hardware cost and improve hardware utilization for real-time performance, a reduction in circuit area is proposed through use of parameter-controlled reconfigurable architecture. The experiment results show that the proposed hardware-oriented contrast enhancement algorithm can provide an average frame rate of 48.23 frames/s at high definition resolution 1920 × 1080.

  18. VLSI Design of Trusted Virtual Sensors

    Directory of Open Access Journals (Sweden)

    Macarena C. Martínez-Rodríguez

    2018-01-01

    Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

  19. An efficient three-dimensional Poisson solver for SIMD high-performance-computing architectures

    Science.gov (United States)

    Cohl, H.

    1994-01-01

    We present an algorithm that solves the three-dimensional Poisson equation on a cylindrical grid. The technique uses a finite-difference scheme with operator splitting. This splitting maps the banded structure of the operator matrix into a two-dimensional set of tridiagonal matrices, which are then solved in parallel. Our algorithm couples FFT techniques with the well-known ADI (Alternating Direction Implicit) method for solving Elliptic PDE's, and the implementation is extremely well suited for a massively parallel environment like the SIMD architecture of the MasPar MP-1. Due to the highly recursive nature of our problem, we believe that our method is highly efficient, as it avoids excessive interprocessor communication.

  20. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    KAUST Repository

    Bahabry, Rabab R.

    2018-01-02

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  1. Through-Wafer Optical Interconnects For Multi-Wafer Wafer-Scale Integrated Architectures

    Science.gov (United States)

    Hornak, L. A.; Tewksbury, S. K.; Hatamian, M.; Ligtenberg, A.; Sugla, B.; Franzon, P.

    1986-12-01

    Hybrid mounting of optical components, combined perhaps with integrated optical waveguides and lenses on a large area silicon, wafer-scale integrated (WSI) electronic circuit provides one potential approach to combine advanced electronic and photonic functions. The desire to achieve a high degree of parallelism in multi-wafer WSI-based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and. providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While presently it is difficult for optical interconnects to compete with electrical interconnects in the wafer plane, it is appropriate to look at vertical optical interconnections between wafer planes since the corresponding conductive structures would be large in area and may impede system repairability. The ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages for multi-wafer WSI or other dense three-dimensional architectures. However, while optical waveguides are readily fabricated in the plane of the wafer, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one straightforward method of meeting this criterion. Using optical device technology operating at wavelengths beyond the ≍1.1μm Si absorption cutoff, low loss, through-wafer propagation between WSI circuit boards can be achieved over the distances of interest (≍1mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that the transmittance can be raised to ≍77% for n-type and to ≍97% for p-type silicon. Optical interconnect source

  2. An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures

    Directory of Open Access Journals (Sweden)

    Maurizio Palesi

    2015-03-01

    Full Text Available Modern systems-on-chip (SoCs today contain hundreds of cores, and this number is predicted to reach the thousands by the year 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The network-on-chip (NoC design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues, such as the performance limitations of long interconnects and integration of large number of cores on a chip. Recently, new communication technologies based on the NoC concept have emerged with the aim of improving the scalability limitations of conventional NoC-based architectures. Among them, wireless NoCs (WiNoCs use the radio medium for reducing the performance and energy penalties of long-range and multi-hop communications. As the radio medium can be accessed by a single transmitter at a time, a radio access control mechanism (RACM is needed. In this paper, we present a novel RACM, which allows one to improve both the performance and energy figures of the WiNoC. Experiments, carried out on both synthetic and real traffic scenarios, have shown the effectiveness of the proposed RACM. On average, a 30% reduction in communication delay and a 25% energy savings have been observed when the proposed RACM is applied to a known WiNoC architecture.

  3. Algorithms, architectures and information systems security

    CERN Document Server

    Sur-Kolay, Susmita; Nandy, Subhas C; Bagchi, Aditya

    2008-01-01

    This volume contains articles written by leading researchers in the fields of algorithms, architectures, and information systems security. The first five chapters address several challenging geometric problems and related algorithms. These topics have major applications in pattern recognition, image analysis, digital geometry, surface reconstruction, computer vision and in robotics. The next five chapters focus on various optimization issues in VLSI design and test architectures, and in wireless networks. The last six chapters comprise scholarly articles on information systems security coverin

  4. High-efficiency receiver architecture for resonance-fluorescence and Doppler lidars.

    Science.gov (United States)

    Smith, John A; Chu, Xinzhao

    2015-04-10

    A high-efficiency lidar receiver architecture that emphasizes boosting the receiver collection efficiency of resonance-fluorescence and Doppler lidars has opened up new avenues of study for the mesosphere and lower thermosphere-extended (MLT-X) at sites in Boulder, Colorado, USA, and Cerro Pachón, Chile. Described in this work are in-depth considerations in the design, construction, and alignment of Na Doppler lidar receivers that have yielded signal levels typically 5-10 times higher per power-aperture product than any demonstrated in the literature, to these authors' knowledge, making studies of fine-scale MLT turbulence and tenuous thermospheric layers in Na possible with temperature and vertical wind capability for the first time. A lowering of the detection threshold by higher receiver collection efficiency at Cerro Pachón has enabled this Na Doppler lidar to extend its measurement range far higher into the thermosphere, to regions with Na density less than 3  cm(-3). With renewed interest in the MLT-X region prompted by recent lidar discoveries of Fe in the thermosphere reaching 170 km at McMurdo, Antarctica, the receiver optimizations we have made now enable addressing an important need in the community. In addition, the higher spatial and temporal resolutions afforded by high signal-to-noise ratio, down to resolutions of ∼20  s and ∼20  m, promise to make the first direct measurements of eddy flux in the mesopause region possible. Results from deployment of optimized receivers at the Table Mountain Lidar Observatory in Boulder, the Andes Lidar Observatory at Cerro Pachón, and the Arecibo Observatory in Puerto Rico are presented to demonstrate the power and portability of our methods that are readily applicable to other lidar varieties, including, but not limited to, the newly developed Fe Doppler lidar and recently upgraded K Doppler lidar.

  5. Multilevel VLSI interconnection—an optimum approach?

    Science.gov (United States)

    Srikrishnan, K. V.; Totta, P. A.

    1986-04-01

    The wirability of circuit elements is a key ingredient in the success of the very large scale integration technology. Multilevel wiring eliminates the need to use extensive areas of the silicon surface simply for wiring channels. Increasing the number of wiring planes significantly improves the possibility of achieving the goals of the VLSI, i.e. the interconnection of the maximum number of devices in the smallest possible area. Extensive modeling has shown the need to optimize the wiring pitch, number of wiring planes and electrical properties of the materials used (e.g-low resistivity for conductors and low dielectric constant for insulators). The choice of the interconnection technology is also influenced by other factors. Some of these areas: cost and reliability objectives; in house expertise and practice; new process/equipment availability and a desire to maintain process commonality. The selected strategy is sometimes an optimum approach for an individual situation which is not universally optimum. In IBM, for example, two different but successful multilevel wiring technologies are being used extensively. The first is used for bipolar circuits; it is a three-level metallization design, with sputtered SiO2 as the insulator. The second, for FET devices, has two-levels of metal and polyimide as the insulator. Both technologies use area array input/output terminal connections and lift off line definition. The process/material set of each is reviewed to emphasize the mechanics of reaching an ``optimum'' solution for the individual applications.

  6. Use of genetic algorithms for encoding efficient neural network architectures: neurocomputer implementation

    Science.gov (United States)

    James, Jason; Dagli, Cihan H.

    1995-04-01

    In this study an attempt is being made to encode the architecture of a neural network in a chromosome string for evolving robust, fast-learning, minimal neural network architectures through genetic algorithms. Various attributes affecting the learning of the network are represented as genes. The performance of the networks is used as the fitness value. Neural network architecture design concepts are initially demonstrated using a backpropagation architecture with the standard data set of Rosenberg and Sejnowski for text to speech conversion on Adaptive Solutions Inc.'s CNAPS Neuro-Computer. The architectures obtained are compared with the one reported in the literature for the standard data set used. The study concludes by providing some insights regarding the architecture encoding for other artificial neural network paradigms.

  7. An efficient architecture to support digital pathology in standard medical imaging repositories.

    Science.gov (United States)

    Marques Godinho, Tiago; Lebre, Rui; Silva, Luís Bastião; Costa, Carlos

    2017-07-01

    In the past decade, digital pathology and whole-slide imaging (WSI) have been gaining momentum with the proliferation of digital scanners from different manufacturers. The literature reports significant advantages associated with the adoption of digital images in pathology, namely, improvements in diagnostic accuracy and better support for telepathology. Moreover, it also offers new clinical and research applications. However, numerous barriers have been slowing the adoption of WSI, among which the most important are performance issues associated with storage and distribution of huge volumes of data, and lack of interoperability with other hospital information systems, most notably Picture Archive and Communications Systems (PACS) based on the DICOM standard. This article proposes an architecture of a Web Pathology PACS fully compliant with DICOM standard communications and data formats. The solution includes a PACS Archive responsible for storing whole-slide imaging data in DICOM WSI format and offers a communication interface based on the most recent DICOM Web services. The second component is a zero-footprint viewer that runs in any web-browser. It consumes data using the PACS archive standard web services. Moreover, it features a tiling engine especially suited to deal with the WSI image pyramids. These components were designed with special focus on efficiency and usability. The performance of our system was assessed through a comparative analysis of the state-of-the-art solutions. The results demonstrate that it is possible to have a very competitive solution based on standard workflows. Copyright © 2017 Elsevier Inc. All rights reserved.

  8. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  9. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  10. Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacks

    DEFF Research Database (Denmark)

    Bogdanov, Andrey; Kavun, Elif Bilge; Tischhauser, Elmar

    2012-01-01

    in a vast range of parameters. The new hardware architecture allows us to verify the existing theoretical models for the complexity estimation in linear cryptanalysis. The designed hardware architecture is realized on two Xilinx Virtex-6 XC6VLX240T FPGAs for smaller block lengths, and on RIVYERA platform...... with 128 Xilinx Spartan-3 XC3S5000 FPGAs for larger block lengths....

  11. A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level

    Directory of Open Access Journals (Sweden)

    Anthony Barreteau

    2012-01-01

    Full Text Available Abstract models are necessary to assist system architects in the evaluation process of hardware/software architectures and to cope with the still increasing complexity of embedded systems. Efficient methods are required to create reliable models of system architectures and to allow early performance evaluation and fast exploration of the design space. In this paper, we present a specific transaction level modeling approach for performance evaluation of hardware/software architectures. This approach relies on a generic execution model that exhibits light modeling effort. Created models are used to evaluate by simulation expected processing and memory resources according to various architectures. The proposed execution model relies on a specific computation method defined to improve the simulation speed of transaction level models. The benefits of the proposed approach are highlighted through two case studies. The first case study is a didactic example illustrating the modeling approach. In this example, a simulation speed-up by a factor of 7,62 is achieved by using the proposed computation method. The second case study concerns the analysis of a communication receiver supporting part of the physical layer of the LTE protocol. In this case study, architecture exploration is led in order to improve the allocation of processing functions.

  12. An Energy-Efficient and High-Quality Video Transmission Architecture in Wireless Video-Based Sensor Networks

    Science.gov (United States)

    Aghdasi, Hadi S.; Abbaspour, Maghsoud; Moghadam, Mohsen Ebrahimi; Samei, Yasaman

    2008-01-01

    Technological progress in the fields of Micro Electro-Mechanical Systems (MEMS) and wireless communications and also the availability of CMOS cameras, microphones and small-scale array sensors, which may ubiquitously capture multimedia content from the field, have fostered the development of low-cost limited resources Wireless Video-based Sensor Networks (WVSN). With regards to the constraints of video-based sensor nodes and wireless sensor networks, a supporting video stream is not easy to implement with the present sensor network protocols. In this paper, a thorough architecture is presented for video transmission over WVSN called Energy-efficient and high-Quality Video transmission Architecture (EQV-Architecture). This architecture influences three layers of communication protocol stack and considers wireless video sensor nodes constraints like limited process and energy resources while video quality is preserved in the receiver side. Application, transport, and network layers are the layers in which the compression protocol, transport protocol, and routing protocol are proposed respectively, also a dropping scheme is presented in network layer. Simulation results over various environments with dissimilar conditions revealed the effectiveness of the architecture in improving the lifetime of the network as well as preserving the video quality. PMID:27873772

  13. An Energy-Efficient and High-Quality Video Transmission Architecture in Wireless Video-Based Sensor Networks

    Directory of Open Access Journals (Sweden)

    Yasaman Samei

    2008-08-01

    Full Text Available Technological progress in the fields of Micro Electro-Mechanical Systems (MEMS and wireless communications and also the availability of CMOS cameras, microphones and small-scale array sensors, which may ubiquitously capture multimedia content from the field, have fostered the development of low-cost limited resources Wireless Video-based Sensor Networks (WVSN. With regards to the constraints of videobased sensor nodes and wireless sensor networks, a supporting video stream is not easy to implement with the present sensor network protocols. In this paper, a thorough architecture is presented for video transmission over WVSN called Energy-efficient and high-Quality Video transmission Architecture (EQV-Architecture. This architecture influences three layers of communication protocol stack and considers wireless video sensor nodes constraints like limited process and energy resources while video quality is preserved in the receiver side. Application, transport, and network layers are the layers in which the compression protocol, transport protocol, and routing protocol are proposed respectively, also a dropping scheme is presented in network layer. Simulation results over various environments with dissimilar conditions revealed the effectiveness of the architecture in improving the lifetime of the network as well as preserving the video quality.

  14. An Energy-Efficient and High-Quality Video Transmission Architecture in Wireless Video-Based Sensor Networks.

    Science.gov (United States)

    Aghdasi, Hadi S; Abbaspour, Maghsoud; Moghadam, Mohsen Ebrahimi; Samei, Yasaman

    2008-08-04

    Technological progress in the fields of Micro Electro-Mechanical Systems (MEMS) and wireless communications and also the availability of CMOS cameras, microphones and small-scale array sensors, which may ubiquitously capture multimedia content from the field, have fostered the development of low-cost limited resources Wireless Video-based Sensor Networks (WVSN). With regards to the constraints of videobased sensor nodes and wireless sensor networks, a supporting video stream is not easy to implement with the present sensor network protocols. In this paper, a thorough architecture is presented for video transmission over WVSN called Energy-efficient and high-Quality Video transmission Architecture (EQV-Architecture). This architecture influences three layers of communication protocol stack and considers wireless video sensor nodes constraints like limited process and energy resources while video quality is preserved in the receiver side. Application, transport, and network layers are the layers in which the compression protocol, transport protocol, and routing protocol are proposed respectively, also a dropping scheme is presented in network layer. Simulation results over various environments with dissimilar conditions revealed the effectiveness of the architecture in improving the lifetime of the network as well as preserving the video quality.

  15. Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

    Science.gov (United States)

    Yang, Chen; Liu, LeiBo; Yin, ShouYi; Wei, ShaoJun

    2014-12-01

    The computational capability of a coarse-grained reconfigurable array (CGRA) can be significantly restrained due to data and context memory bandwidth bottlenecks. Traditionally, two methods have been used to resolve this problem. One method loads the context into the CGRA at run time. This method occupies very small on-chip memory but induces very large latency, which leads to low computational efficiency. The other method adopts a multi-context structure. This method loads the context into the on-chip context memory at the boot phase. Broadcasting the pointer of a set of contexts changes the hardware configuration on a cycle-by-cycle basis. The size of the context memory induces a large area overhead in multi-context structures, which results in major restrictions on application complexity. This paper proposes a Predictable Context Cache (PCC) architecture to address the above context issues by buffering the context inside a CGRA. In this architecture, context is dynamically transferred into the CGRA. Utilizing a PCC significantly reduces the on-chip context memory and the complexity of the applications running on the CGRA is no longer restricted by the size of the on-chip context memory. Data preloading is the most frequently used approach to hide input data latency and speed up the data transmission process for the data bandwidth issue. Rather than fundamentally reducing the amount of input data, the transferred data and computations are processed in parallel. However, the data preloading method cannot work efficiently because data transmission becomes the critical path as the reconfigurable array scale increases. This paper also presents a Hierarchical Data Memory (HDM) architecture as a solution to the efficiency problem. In this architecture, high internal bandwidth is provided to buffer both reused input data and intermediate data. The HDM architecture relieves the external memory from the data transfer burden so that the performance is significantly

  16. Formal Hierarchical Multilevel Verification of Synchronous MOS VLSI Designs,

    Science.gov (United States)

    1987-11-01

    description of digital systems appear in Johnson [Johnson] (though in a much less accessible form). Other researchers, [ Sheeran , Johnson], use the same...Snepscheut, "Hot-Clock nMOS," Proc of the 1985 Chapel Hil Conference on VLSI. Henry Fuchs, Editor. Computer Science Press 1985 [ Sheeran ] Mary Sheeran

  17. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  18. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...

  19. An evaluation of the software architecture efficiency using the Clichés and behavioral diagrams pertaining to the unified modeling language

    Directory of Open Access Journals (Sweden)

    Siamak Khaksar Haghani

    2014-06-01

    Full Text Available The software architecture plays essential role for the development of the complicated software systems and it is important to evaluate the software architecture efficiency. One way to evaluate the software architecture is to create an executable model from the architecture. Unified Modeling Language (UML diagrams are used to describe the software architecture. UML has made it easy to use and to evaluate the necessary requirements at the software architecture level. It creates an executable model from these diagrams; yet, since the UML is a standard semi-formal language for describing the software architecture, evaluating the software architecture is not directly possible through it. Furthermore, in order to evaluate the software architecture, one needs to turn the actual model into the formal model. In this study, first we describe the architecture using the UML. Then, some properties of the software architecture are mentioned using the UML sequence diagram, deployment diagram, use case diagram, and component diagram. The necessary information associated with the qualitative characteristic of efficiency will be margined as clichés and labels to these diagrams. The independent and dependent components will be extracted from the component diagram. Finally, the resulted semi-formal model will be mapped into a formal model based on the colored Petri net and finally the evaluation will take place.

  20. High Efficiency Three Phase Resonant Conversion for Standardized Architecture Power System Applications Project

    Data.gov (United States)

    National Aeronautics and Space Administration — A low-cost, standardized-architecture power system is proposed for NASA electric propulsion (EP) applications. Three approaches are combined to develop a system that...

  1. Engineering interfacial photo-induced charge transfer based on nanobamboo array architecture for efficient solar-to-chemical energy conversion.

    Science.gov (United States)

    Wang, Xiaotian; Liow, Chihao; Bisht, Ankit; Liu, Xinfeng; Sum, Tze Chien; Chen, Xiaodong; Li, Shuzhou

    2015-04-01

    Engineering interfacial photo-induced charge transfer for highly synergistic photocatalysis is successfully realized based on nanobamboo array architecture. Programmable assemblies of various components and heterogeneous interfaces, and, in turn, engineering of the energy band structure along the charge transport pathways, play a critical role in generating excellent synergistic effects of multiple components for promoting photocatalytic efficiency. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  2. Using Runtime Systems Tools to Implement Efficient Preconditioners for Heterogeneous Architectures

    Directory of Open Access Journals (Sweden)

    Roussel Adrien

    2016-11-01

    Full Text Available Solving large sparse linear systems is a time-consuming step in basin modeling or reservoir simulation. The choice of a robust preconditioner strongly impact the performance of the overall simulation. Heterogeneous architectures based on General Purpose computing on Graphic Processing Units (GPGPU or many-core architectures introduce programming challenges which can be managed in a transparent way for developer with the use of runtime systems. Nevertheless, algorithms need to be well suited for these massively parallel architectures. In this paper, we present preconditioning techniques which enable to take advantage of emerging architectures. We also present our task-based implementations through the use of the HARTS (Heterogeneous Abstract RunTime System runtime system, which aims to manage the recent architectures. We focus on two preconditoners. The first is ILU(0 preconditioner implemented on distributing memory systems. The second one is a multi-level domain decomposition method implemented on a shared-memory system. Obtained results are then presented on corresponding architectures, which open the way to discuss on the scalability of such methods according to numerical performances while keeping in mind that the next step is to propose a massively parallel implementations of these techniques.

  3. Drought Response in Wheat: Key Genes and Regulatory Mechanisms Controlling Root System Architecture and Transpiration Efficiency

    Directory of Open Access Journals (Sweden)

    Manoj Kulkarni

    2017-12-01

    Full Text Available Abiotic stresses such as, drought, heat, salinity, and flooding threaten global food security. Crop genetic improvement with increased resilience to abiotic stresses is a critical component of crop breeding strategies. Wheat is an important cereal crop and a staple food source globally. Enhanced drought tolerance in wheat is critical for sustainable food production and global food security. Recent advances in drought tolerance research have uncovered many key genes and transcription regulators governing morpho-physiological traits. Genes controlling root architecture and stomatal development play an important role in soil moisture extraction and its retention, and therefore have been targets of molecular breeding strategies for improving drought tolerance. In this systematic review, we have summarized evidence of beneficial contributions of root and stomatal traits to plant adaptation to drought stress. Specifically, we discuss a few key genes such as, DRO1 in rice and ERECTA in Arabidopsis and rice that were identified to be the enhancers of drought tolerance via regulation of root traits and transpiration efficiency. Additionally, we highlight several transcription factor families, such as, ERF (ethylene response factors, DREB (dehydration responsive element binding, ZFP (zinc finger proteins, WRKY, and MYB that were identified to be both positive and negative regulators of drought responses in wheat, rice, maize, and/or Arabidopsis. The overall aim of this review is to provide an overview of candidate genes that have been identified as regulators of drought response in plants. The lack of a reference genome sequence for wheat and non-transgenic approaches for manipulation of gene functions in wheat in the past had impeded high-resolution interrogation of functional elements, including genes and QTLs, and their application in cultivar improvement. The recent developments in wheat genomics and reverse genetics, including the availability of a

  4. Path to Zero: Ultra-Efficient Architecture on the NREL Campus: S&TF and Master Planning (Presentation)

    Energy Technology Data Exchange (ETDEWEB)

    Carlisle, N.

    2012-05-01

    Describe the aspects of NREL's S and TF and Campus Master Planning in terms of how they have influenced ultra-efficient architecture on NREL's campus. Energy goals for the NREL campus are: (1) Understand how buildings uses energy, implement the cost-effective energy and water efficiency retrofits; (2) Use principals of energy efficiency and low energy design to reduce energy demand in all new construction; (3) Operate central plants efficiently; (4) Alternative transportation; (5) Use combined heat and power systems; (6) Use on-site renewables for demonstration and where it is cost-effective; and (7) Buy green power (over the next 25 years) so that 100% of our power will be from renewable sources.

  5. Computer architecture for efficient algorithmic executions in real-time systems: New technology for avionics systems and advanced space vehicles

    Science.gov (United States)

    Carroll, Chester C.; Youngblood, John N.; Saha, Aindam

    1987-01-01

    Improvements and advances in the development of computer architecture now provide innovative technology for the recasting of traditional sequential solutions into high-performance, low-cost, parallel system to increase system performance. Research conducted in development of specialized computer architecture for the algorithmic execution of an avionics system, guidance and control problem in real time is described. A comprehensive treatment of both the hardware and software structures of a customized computer which performs real-time computation of guidance commands with updated estimates of target motion and time-to-go is presented. An optimal, real-time allocation algorithm was developed which maps the algorithmic tasks onto the processing elements. This allocation is based on the critical path analysis. The final stage is the design and development of the hardware structures suitable for the efficient execution of the allocated task graph. The processing element is designed for rapid execution of the allocated tasks. Fault tolerance is a key feature of the overall architecture. Parallel numerical integration techniques, tasks definitions, and allocation algorithms are discussed. The parallel implementation is analytically verified and the experimental results are presented. The design of the data-driven computer architecture, customized for the execution of the particular algorithm, is discussed.

  6. Mixed-Signal Architectures for High-Efficiency and Low-Distortion Digital Audio Processing and Power Amplification

    Directory of Open Access Journals (Sweden)

    Pierangelo Terreni

    2010-01-01

    Full Text Available The paper addresses the algorithmic and architectural design of digital input power audio amplifiers. A modelling platform, based on a meet-in-the-middle approach between top-down and bottom-up design strategies, allows a fast but still accurate exploration of the mixed-signal design space. Different amplifier architectures are configured and compared to find optimal trade-offs among different cost-functions: low distortion, high efficiency, low circuit complexity and low sensitivity to parameter changes. A novel amplifier architecture is derived; its prototype implements digital processing IP macrocells (oversampler, interpolating filter, PWM cross-point deriver, noise shaper, multilevel PWM modulator, dead time compensator on a single low-complexity FPGA while off-chip components are used only for the power output stage (LC filter and power MOS bridge; no heatsink is required. The resulting digital input amplifier features a power efficiency higher than 90% and a total harmonic distortion down to 0.13% at power levels of tens of Watts. Discussions towards the full-silicon integration of the mixed-signal amplifier in embedded devices, using BCD technology and targeting power levels of few Watts, are also reported.

  7. A highly efficient 3D level-set grain growth algorithm tailored for ccNUMA architecture

    Science.gov (United States)

    Mießen, C.; Velinov, N.; Gottstein, G.; Barrales-Mora, L. A.

    2017-12-01

    A highly efficient simulation model for 2D and 3D grain growth was developed based on the level-set method. The model introduces modern computational concepts to achieve excellent performance on parallel computer architectures. Strong scalability was measured on cache-coherent non-uniform memory access (ccNUMA) architectures. To achieve this, the proposed approach considers the application of local level-set functions at the grain level. Ideal and non-ideal grain growth was simulated in 3D with the objective to study the evolution of statistical representative volume elements in polycrystals. In addition, microstructure evolution in an anisotropic magnetic material affected by an external magnetic field was simulated.

  8. Two-dimensional high efficiency thin-film silicon solar cells with a lateral light trapping architecture

    Science.gov (United States)

    Fang, Jia; Liu, Bofei; Zhao, Ying; Zhang, Xiaodan

    2014-01-01

    Introducing light trapping structures into thin-film solar cells has the potential to enhance their solar energy harvesting as well as the performance of the cells; however, current strategies have been focused mainly on harvesting photons without considering the light re-escaping from cells in two-dimensional scales. The lateral out-coupled solar energy loss from the marginal areas of cells has reduced the electrical yield indeed. We therefore herein propose a lateral light trapping structure (LLTS) as a means of improving the light-harvesting capacity and performance of cells, achieving a 13.07% initial efficiency and greatly improved current output of a-Si:H single-junction solar cell based on this architecture. Given the unique transparency characteristics of thin-film solar cells, this proposed architecture has great potential for integration into the windows of buildings, microelectronics and other applications requiring transparent components. PMID:25145774

  9. Two-dimensional high efficiency thin-film silicon solar cells with a lateral light trapping architecture.

    Science.gov (United States)

    Fang, Jia; Liu, Bofei; Zhao, Ying; Zhang, Xiaodan

    2014-08-22

    Introducing light trapping structures into thin-film solar cells has the potential to enhance their solar energy harvesting as well as the performance of the cells; however, current strategies have been focused mainly on harvesting photons without considering the light re-escaping from cells in two-dimensional scales. The lateral out-coupled solar energy loss from the marginal areas of cells has reduced the electrical yield indeed. We therefore herein propose a lateral light trapping structure (LLTS) as a means of improving the light-harvesting capacity and performance of cells, achieving a 13.07% initial efficiency and greatly improved current output of a-Si:H single-junction solar cell based on this architecture. Given the unique transparency characteristics of thin-film solar cells, this proposed architecture has great potential for integration into the windows of buildings, microelectronics and other applications requiring transparent components.

  10. Softwarization of Mobile Network Functions towards Agile and Energy Efficient 5G Architectures: A Survey

    Directory of Open Access Journals (Sweden)

    Dlamini Thembelihle

    2017-01-01

    Full Text Available Future mobile networks (MNs are required to be flexible with minimal infrastructure complexity, unlike current ones that rely on proprietary network elements to offer their services. Moreover, they are expected to make use of renewable energy to decrease their carbon footprint and of virtualization technologies for improved adaptability and flexibility, thus resulting in green and self-organized systems. In this article, we discuss the application of software defined networking (SDN and network function virtualization (NFV technologies towards softwarization of the mobile network functions, taking into account different architectural proposals. In addition, we elaborate on whether mobile edge computing (MEC, a new architectural concept that uses NFV techniques, can enhance communication in 5G cellular networks, reducing latency due to its proximity deployment. Besides discussing existing techniques, expounding their pros and cons and comparing state-of-the-art architectural proposals, we examine the role of machine learning and data mining tools, analyzing their use within fully SDN- and NFV-enabled mobile systems. Finally, we outline the challenges and the open issues related to evolved packet core (EPC and MEC architectures.

  11. Noise-margin limitations on gallium-arsenide VLSI

    Science.gov (United States)

    Long, Stephen I.; Sundaram, Mani

    1988-01-01

    Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

  12. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  13. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  14. Energy-Efficient Transmissions for Remote Wireless Sensor Networks: An Integrated HAP/Satellite Architecture for Emergency Scenarios.

    Science.gov (United States)

    Dong, Feihong; Li, Hongjun; Gong, Xiangwu; Liu, Quan; Wang, Jingchao

    2015-09-03

    A typical application scenario of remote wireless sensor networks (WSNs) is identified as an emergency scenario. One of the greatest design challenges for communications in emergency scenarios is energy-efficient transmission, due to scarce electrical energy in large-scale natural and man-made disasters. Integrated high altitude platform (HAP)/satellite networks are expected to optimally meet emergency communication requirements. In this paper, a novel integrated HAP/satellite (IHS) architecture is proposed, and three segments of the architecture are investigated in detail. The concept of link-state advertisement (LSA) is designed in a slow flat Rician fading channel. The LSA is received and processed by the terminal to estimate the link state information, which can significantly reduce the energy consumption at the terminal end. Furthermore, the transmission power requirements of the HAPs and terminals are derived using the gradient descent and differential equation methods. The energy consumption is modeled at both the source and system level. An innovative and adaptive algorithm is given for the energy-efficient path selection. The simulation results validate the effectiveness of the proposed adaptive algorithm. It is shown that the proposed adaptive algorithm can significantly improve energy efficiency when combined with the LSA and the energy consumption estimation.

  15. Energy-Efficient Transmissions for Remote Wireless Sensor Networks: An Integrated HAP/Satellite Architecture for Emergency Scenarios

    Directory of Open Access Journals (Sweden)

    Feihong Dong

    2015-09-01

    Full Text Available A typical application scenario of remote wireless sensor networks (WSNs is identified as an emergency scenario. One of the greatest design challenges for communications in emergency scenarios is energy-efficient transmission, due to scarce electrical energy in large-scale natural and man-made disasters. Integrated high altitude platform (HAP/satellite networks are expected to optimally meet emergency communication requirements. In this paper, a novel integrated HAP/satellite (IHS architecture is proposed, and three segments of the architecture are investigated in detail. The concept of link-state advertisement (LSA is designed in a slow flat Rician fading channel. The LSA is received and processed by the terminal to estimate the link state information, which can significantly reduce the energy consumption at the terminal end. Furthermore, the transmission power requirements of the HAPs and terminals are derived using the gradient descent and differential equation methods. The energy consumption is modeled at both the source and system level. An innovative and adaptive algorithm is given for the energy-efficient path selection. The simulation results validate the effectiveness of the proposed adaptive algorithm. It is shown that the proposed adaptive algorithm can significantly improve energy efficiency when combined with the LSA and the energy consumption estimation.

  16. Dynamic brain architectures in local brain activity and functional network efficiency associate with efficient reading in bilinguals.

    Science.gov (United States)

    Feng, Gangyi; Chen, Hsuan-Chih; Zhu, Zude; He, Yong; Wang, Suiping

    2015-10-01

    The human brain is organized as a dynamic network, in which both regional brain activity and inter-regional connectivity support high-level cognitive processes, such as reading. However, it is still largely unknown how the functional brain network organizes to enable fast and effortless reading processing in the native language (L1) but not in a non-proficient second language (L2), and whether the mechanisms underlying local activity are associated with connectivity dynamics in large-scale brain networks. In the present study, we combined activation-based and multivariate graph-theory analysis with functional magnetic resonance imaging data to address these questions. Chinese-English unbalanced bilinguals read narratives for comprehension in Chinese (L1) and in English (L2). Compared with L2, reading in L1 evoked greater brain activation and recruited a more globally efficient but less clustered network organization. Regions with both increased network efficiency and enhanced brain activation in L1 reading were mostly located in the fronto-temporal reading-related network (RN), whereas regions with decreased global network efficiency, increased clustering, and more deactivation in L2 reading were identified in the default mode network (DMN). Moreover, functional network efficiency was closely associated with local brain activation, and such associations were also modulated by reading efficiency in the two languages. Our results demonstrate that an economical and integrative brain network topology is associated with efficient reading, and further reveal a dynamic association between network efficiency and local activation for both RN and DMN. These findings underscore the importance of considering interregional connectivity when interpreting local BOLD signal changes in bilingual reading. Copyright © 2015 Elsevier Inc. All rights reserved.

  17. Lightweight Filter Architecture for Energy Efficient Mobile Vehicle Localization Based on a Distributed Acoustic Sensor Network

    OpenAIRE

    Kim, Keonwook

    2013-01-01

    The generic properties of an acoustic signal provide numerous benefits for localization by applying energy-based methods over a deployed wireless sensor network (WSN). However, the signal generated by a stationary target utilizes a significant amount of bandwidth and power in the system without providing further position information. For vehicle localization, this paper proposes a novel proximity velocity vector estimator (PVVE) node architecture in order to capture the energy from a moving v...

  18. UW/NW (University of Washington/Northwest) VLSI Consortium

    Science.gov (United States)

    1986-12-10

    structure of the described circuits. One such language is ^ FP (a variation of the Functional Programming language FP) [ Sheeran 83] that describes...86] [Lipton 82] [ Sheeran 83] [Suzuki 85] [UW/NW 84] Bamji, C, Hauck, C. and Allen, J. A Design by Example Regular Structure Generator. In 22nd...Automation Conference, pages 467-474. IEEE, 1982. Mary Sheeran . \\i.FP - An Algebraic VLSI Design Language. PhD thesis, Oxford University Computing La

  19. Using Software Technology to Specify Abstract Interfaces in VLSI Design.

    Science.gov (United States)

    1985-01-01

    and Smoliar [Fran7g], Rowson [Rows80, Gordon [Gord8lJ, Cardelli and Plotkin [Card8l1, Hafer and Parker (Hafe83I, and Sheeran [Shee84] have all suggested...Software 1, 4 (October 1984), pp. 10-26. •.’ Y .. , ;,, ..- , .. r ,- ’..-.... -. -.. ,.:.%.. -. 149 ISbeeS4I. Sheeran , M., "mFP, a Language for VLSI

  20. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  1. Model for EOS caused EF screening in CMOS VLSI

    Energy Technology Data Exchange (ETDEWEB)

    Lisenker, B. [Tower Semiconductor Ltd., Migdal Haemek (Israel); Nevo, Y. [National Semiconductor Ltd., Herzlia B` (Israel)

    1995-12-31

    This paper introduced a Fault Model, capable to elucidate the sensitivity to Electrical Overstress (EOS) and Early Fault (EF) rising nature in CMOS VLSI circuit. The Model based on the general Percolation Theory applied to the CMOS technology. Early Failures screening technique employing this Model, shows strong correlation between rejected devices, EOS faults and EF rate. This technique is recommenced both as an EF screening test and a process reliability monitor.

  2. A System Architecture for Efficient Transmission of Massive DNA Sequencing Data.

    Science.gov (United States)

    Sağiroğlu, Mahmut Şamİl; Külekcİ, M Oğuzhan

    2017-04-17

    The DNA sequencing data analysis pipelines require significant computational resources. In that sense, cloud computing infrastructures appear as a natural choice for this processing. However, the first practical difficulty in reaching the cloud computing services is the transmission of the massive DNA sequencing data from where they are produced to where they will be processed. The daily practice here begins with compressing the data in FASTQ file format, and then sending these data via fast data transmission protocols. In this study, we address the weaknesses in that daily practice and present a new system architecture that incorporates the computational resources available on the client side while dynamically adapting itself to the available bandwidth. Our proposal considers the real-life scenarios, where the bandwidth of the connection between the parties may fluctuate, and also the computing power on the client side may be of any size ranging from moderate personal computers to powerful workstations. The proposed architecture aims at utilizing both the communication bandwidth and the computing resources for satisfying the ultimate goal of reaching the results as early as possible. We present a prototype implementation of the proposed architecture, and analyze several real-life cases, which provide useful insights for the sequencing centers, especially on deciding when to use a cloud service and in what conditions.

  3. Interplay between efficiency and device architecture for small molecule organic solar cells.

    Science.gov (United States)

    Williams, Graeme; Sutty, Sibi; Aziz, Hany

    2014-06-21

    Small molecule organic solar cells (OSCs) have experienced a resurgence of interest over their polymer solar cell counterparts, owing to their improved batch-to-batch (thus, cell-to-cell) reliability. In this systematic study on OSC device architecture, we investigate five different small molecule OSC structures, including the simple planar heterojunction (PHJ) and bulk heterojunction (BHJ), as well as several planar-mixed structures. The different OSC structures are studied over a wide range of donor:acceptor mixing concentrations to gain a comprehensive understanding of their charge transport behavior. Transient photocurrent decay measurements provide crucial information regarding the interplay between charge sweep-out and charge recombination, and ultimately hint toward space charge effects in planar-mixed structures. Results show that the BHJ/acceptor architecture, comprising a BHJ layer with high C60 acceptor content, generates OSCs with the highest performance by balancing charge generation with charge collection. The performance of other device architectures is largely limited by hole transport, with associated hole accumulation and space charge effects.

  4. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  5. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  6. A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3 Discrete Wavelet Transform used in JPEG2000

    Directory of Open Access Journals (Sweden)

    Mohammad Rafi Lone

    2017-03-01

    Full Text Available For real-time applications, efficient VLSI implementation of DWT is desired. In this paper, DWT architecture based on retiming for pipelining and unfolding is presented. The architecture is based on lifting one-dimensional Cohen-Daubechies-Feauveau (CDF (5,3 wavelet filter, which is easily extended to 2-D implementation. It consists of low complexity and easily repeatable components. This paper is focused on the critical path minimization and throughput optimization at the same time. The architecture has been implemented on Virtex 6 Xilinx FPGA platform. The implementation results show that the critical path is minimized four to five times, while throughput is doubled, making the overall architecture approximately ten times faster when compared with the conventional lifting-based DWT architecture. Further with parallel implementation, the throughput has doubled without any increase in number of row buffers, implying that the architecture is memory efficient as well. The even and odd rows of the image are scanned in parallel fashion. To perform the 2-D DWT transform of an image of size 15 Megapixels, it takes 16.86 ms, which implies 59 images of that size can be processed in one second. This can be utilized for real-time video processing applications even for high resolution videos.

  7. A series connection architecture for large-area organic photovoltaic modules with a 7.5% module efficiency

    Science.gov (United States)

    Hong, Soonil; Kang, Hongkyu; Kim, Geunjin; Lee, Seongyu; Kim, Seok; Lee, Jong-Hoon; Lee, Jinho; Yi, Minjin; Kim, Junghwan; Back, Hyungcheol; Kim, Jae-Ryoung; Lee, Kwanghee

    2016-01-01

    The fabrication of organic photovoltaic modules via printing techniques has been the greatest challenge for their commercial manufacture. Current module architecture, which is based on a monolithic geometry consisting of serially interconnecting stripe-patterned subcells with finite widths, requires highly sophisticated patterning processes that significantly increase the complexity of printing production lines and cause serious reductions in module efficiency due to so-called aperture loss in series connection regions. Herein we demonstrate an innovative module structure that can simultaneously reduce both patterning processes and aperture loss. By using a charge recombination feature that occurs at contacts between electron- and hole-transport layers, we devise a series connection method that facilitates module fabrication without patterning the charge transport layers. With the successive deposition of component layers using slot-die and doctor-blade printing techniques, we achieve a high module efficiency reaching 7.5% with area of 4.15 cm2.

  8. A series connection architecture for large-area organic photovoltaic modules with a 7.5% module efficiency.

    Science.gov (United States)

    Hong, Soonil; Kang, Hongkyu; Kim, Geunjin; Lee, Seongyu; Kim, Seok; Lee, Jong-Hoon; Lee, Jinho; Yi, Minjin; Kim, Junghwan; Back, Hyungcheol; Kim, Jae-Ryoung; Lee, Kwanghee

    2016-01-05

    The fabrication of organic photovoltaic modules via printing techniques has been the greatest challenge for their commercial manufacture. Current module architecture, which is based on a monolithic geometry consisting of serially interconnecting stripe-patterned subcells with finite widths, requires highly sophisticated patterning processes that significantly increase the complexity of printing production lines and cause serious reductions in module efficiency due to so-called aperture loss in series connection regions. Herein we demonstrate an innovative module structure that can simultaneously reduce both patterning processes and aperture loss. By using a charge recombination feature that occurs at contacts between electron- and hole-transport layers, we devise a series connection method that facilitates module fabrication without patterning the charge transport layers. With the successive deposition of component layers using slot-die and doctor-blade printing techniques, we achieve a high module efficiency reaching 7.5% with area of 4.15 cm(2).

  9. High efficiency and low roll-off blue phosphorescent organic light-emitting devices using mixed host architecture

    Energy Technology Data Exchange (ETDEWEB)

    Chopra, Neetu; Swensen, James S.; Polikarpov, Evgueni; Cosimbescu, Lelia; So, Franky; Padmaperuma, Asanga B.

    2010-07-20

    We report high efficiency and low roll-off for blue electrophosphorescent organic light emitting devices (OLEDs) based on a mixed host layer architecture. The devices were fabricated using a mixed layer of di-[4-(N,N-ditolyl-amino)-phenyl]cyclohexane (TAPC), a hole transport material, and 2,8-bis(diphenylphosphoryl)dibenzothiophene (PO15), an electron transport material, as the host layer doped with the blue phosphor iridium (III) bis[(4,6-difluorophenyl)-pyridinato-N,C2’]picolinate (FIrpic). Using a mixed layer as the host allowed us to achieve high power efficiency (59 lm/W at 100 cd/m2), low turn-on voltage (2.7 V for >10 cd/m2), and low roll-off in these devices.

  10. Fe/amorphous ceramics core/shell structured nanoflakes-assembled rod-like architecture for efficient microwave absorber

    Science.gov (United States)

    Li, Xiaolong; Li, Zhenxing; Liu, Xianguo; Zhang, Shihong; Ran, Songlin

    2017-12-01

    A rod-like architecture self-assembled from Fe/amorphous ceramics core/shell structured nanoflakes has been prepared by arc discharging steelmaking slag in an Ar/H2 atmosphere, in which the amorphous ceramic shell is composed of MgO, Al2O3, MgSiO3 and CaSiO3. The electromagnetic absorbing performance of the rod-like architecture is evaluated over the range of 2–18 GHz. Multiple dielectric relaxation of the permittivity is attributed to the size distribution and novel morphology of the rod-like architecture. The experimental permeability is in good agreement with the calculated curves based on the Landau–Lifshitz–Gilbert equation. The magnetic loss ability is superior to the dielectric loss ability, due to the planar anisotropy of flake-shaped particles. At a thickness of 2.4 mm, the minimal reflection loss (RL) can reach  ‑35.04 dB at 10.96 GHz. In particular, the effective bandwidth with RL exceeding  ‑10 dB remains at least 2.56 GHz at a thickness of 1.6–4.1 mm, and exhibits a red shift phenomenon as layer thickness increases. Such efficient EM absorption performances originate from magnetic/dielectric loss ability accompanied by 1/4-wave elimination. The represented work not only provides a good reference for efficient microwave absorption, but also broadens the application of steelmaking slag.

  11. Neighborhood structure influences the convergence in light capture efficiency and carbon gain: an architectural approach for cloud forest shrubs.

    Science.gov (United States)

    Guzmán Q, J Antonio; Cordero S, Roberto A

    2016-06-01

    Although plant competition is recognized as a fundamental factor that limits survival and species coexistence, its relative importance on light capture efficiency and carbon gain is not well understood. Here, we propose a new framework to explain the effects of neighborhood structures and light availability on plant attributes and their effect on plant performance in two understory shade-tolerant species (Palicourea padifolia (Roem. & Schult.) C.M. Taylor & Lorence and Psychotria elata (Swartz)) within two successional stages of a cloud forest in Costa Rica. Features of plant neighborhood physical structure and light availability, estimated by hemispherical photographs, were used to characterize the plant competition. Plant architecture, leaf attributes and gas exchange parameters extracted from the light-response curve were used as functional plant attributes, while an index of light capture efficiency (silhouette to total area ratio, averaged over all viewing angles, STAR) and carbon gain were used as indicators of plant performance. This framework is based in a partial least square Path model, which suggests that changes in plant performance in both species were affected in two ways: (i) increasing size and decreasing distance of neighbors cause changes in plant architecture (higher crown density and greater leaf dispersion), which contribute to lower STAR and subsequently lower carbon gain; and (ii) reductions in light availability caused by the neighbors also decrease plant carbon gain. The effect of neighbors on STAR and carbon gain were similar for the two forests sites, which were at different stages of succession, suggesting that the architectural changes of the two understory species reflect functional convergence in response to plant competition. Because STAR and carbon gain are variables that depend on multiple plant attributes and environmental characteristics, we suggest that changes in these features can be used as a whole-plant response approach to

  12. Rationally designed graphene-nanotube 3D architectures with a seamless nodal junction for efficient energy conversion and storage.

    Science.gov (United States)

    Xue, Yuhua; Ding, Yong; Niu, Jianbing; Xia, Zhenhai; Roy, Ajit; Chen, Hao; Qu, Jia; Wang, Zhong Lin; Dai, Liming

    2015-09-01

    One-dimensional (1D) carbon nanotubes (CNTs) and 2D single-atomic layer graphene have superior thermal, electrical, and mechanical properties. However, these nanomaterials exhibit poor out-of-plane properties due to the weak van der Waals interaction in the transverse direction between graphitic layers. Recent theoretical studies indicate that rationally designed 3D architectures could have desirable out-of-plane properties while maintaining in-plane properties by growing CNTs and graphene into 3D architectures with a seamless nodal junction. However, the experimental realization of seamlessly-bonded architectures remains a challenge. We developed a strategy of creating 3D graphene-CNT hollow fibers with radially aligned CNTs (RACNTs) seamlessly sheathed by a cylindrical graphene layer through a one-step chemical vapor deposition using an anodized aluminum wire template. By controlling the aluminum wire diameter and anodization time, the length of the RACNTs and diameter of the graphene hollow fiber can be tuned, enabling efficient energy conversion and storage. These fibers, with a controllable surface area, meso-/micropores, and superior electrical properties, are excellent electrode materials for all-solid-state wire-shaped supercapacitors with poly(vinyl alcohol)/H2SO4 as the electrolyte and binder, exhibiting a surface-specific capacitance of 89.4 mF/cm(2) and length-specific capacitance up to 23.9 mF/cm, - one to four times the corresponding record-high capacities reported for other fiber-like supercapacitors. Dye-sensitized solar cells, fabricated using the fiber as a counter electrode, showed a power conversion efficiency of 6.8% and outperformed their counterparts with an expensive Pt wire counter electrode by a factor of 2.5. These novel fiber-shaped graphene-RACNT energy conversion and storage devices are so flexible they can be woven into fabrics as power sources.

  13. Novel insight into the genomic architecture of feed and nitrogen efficiency measured by residual energy intake and nitrogen excretion in growing pigs

    OpenAIRE

    Shirali, M.; Duthie, C.A.; Doeschl-Wilson, A.; Knap, P.W.; Kanis, E.; Arendonk, van, J.A.M.; Roehe, R.

    2013-01-01

    Background Improvement of feed efficiency in pigs is of great economical and environmental interest and contributes to use limited resources efficiently to feed the world population. Genome scans for feed efficiency traits are of importance to reveal the underlying biological causes and increase the rate of genetic gain. The aim of this study was to determine the genomic architecture of feed efficiency measured by residual energy intake (REI), in association with production, feed conversion r...

  14. Robust Bioinformatics Recognition with VLSI Biochip Microsystem

    Science.gov (United States)

    Lue, Jaw-Chyng L.; Fang, Wai-Chi

    2006-01-01

    A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

  15. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

  16. Highly Conductive 3D Segregated Graphene Architecture in Polypropylene Composite with Efficient EMI Shielding

    Directory of Open Access Journals (Sweden)

    Fakhr E. Alam

    2017-12-01

    Full Text Available The extensive use of electronic equipment in modern life causes potential electromagnetic pollution harmful to human health. Therefore, it is of great significance to enhance the electrical conductivity of polymers, which are widely used in electronic components, to screen out electromagnetic waves. The fabrication of graphene/polymer composites has attracted much attention in recent years due to the excellent electrical properties of graphene. However, the uniform distribution of graphene nanoplatelets (GNPs in a non-polar polymer matrix like polypropylene (PP still remains a challenge, resulting in the limited improvement of electrical conductivity of PP-based composites achieved to date. Here, we propose a single-step approach to prepare GNPs/PP composites embedded with a segregated architecture of GNPs by coating PP particles with GNPs, followed by hot-pressing. As a result, the electrical conductivity of 10 wt % GNPs-loaded composites reaches 10.86 S·cm−1, which is ≈7 times higher than that of the composites made by the melt-blending process. Accordingly, a high electromagnetic interference shielding effectiveness (EMI SE of 19.3 dB can be achieved. Our method is green, low-cost, and scalable to develop 3D GNPs architecture in a polymer matrix, providing a versatile composite material suitable for use in electronics, aerospace, and automotive industries.

  17. Historical building monitoring using an energy-efficient scalable wireless sensor network architecture.

    Science.gov (United States)

    Capella, Juan V; Perles, Angel; Bonastre, Alberto; Serrano, Juan J

    2011-01-01

    We present a set of novel low power wireless sensor nodes designed for monitoring wooden masterpieces and historical buildings, in order to perform an early detection of pests. Although our previous star-based system configuration has been in operation for more than 13 years, it does not scale well for sensorization of large buildings or when deploying hundreds of nodes. In this paper we demonstrate the feasibility of a cluster-based dynamic-tree hierarchical Wireless Sensor Network (WSN) architecture where realistic assumptions of radio frequency data transmission are applied to cluster construction, and a mix of heterogeneous nodes are used to minimize economic cost of the whole system and maximize power saving of the leaf nodes. Simulation results show that the specialization of a fraction of the nodes by providing better antennas and some energy harvesting techniques can dramatically extend the life of the entire WSN and reduce the cost of the whole system. A demonstration of the proposed architecture with a new routing protocol and applied to termite pest detection has been implemented on a set of new nodes and should last for about 10 years, but it provides better scalability, reliability and deployment properties.

  18. Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures

    NARCIS (Netherlands)

    Bierens, L.; Deprettere, E.

    1998-01-01

    We present an efficient approach for the partitioning of algorithms implementing long convolutions. The dependence graph (DG) of a convolution algorithm is locally sequential globally parallel (LSGP) partitioned into smaller, less complex convolution algorithms. The LSGP partitioned DG is mapped

  19. Data gathering and architecture aspects of a major EU wide energy efficiency project for SMEs

    OpenAIRE

    Brown, Neil; Fleming, P. D.; Favaretto, Nicoletta; Snadford, Niall

    2016-01-01

    “Support and Training for an Excellent Energy Efficiency Performance” is a 3-year European project helping over 600 European cross-sector small and medium sized enterprises (SMEs) to reduce their energy use and become more energy-efficient. Companies participating in STEEEP benefit from tailored training and guidance on effective energy management tools and best practices provided by an established network of energy advisors from Chambers of Commerce and Industry (CCIs) in 10 different count...

  20. Application and Integration of Quantum-Effect Devices for Cellular VLSI

    Science.gov (United States)

    Levy, Harold Joseph

    1995-01-01

    Cellular VLSI is that subclass of electronic systems for which small perturbations in a repeated cell design can dramatically influence the cost and performance of the entire system. This thesis presents examples of how the room-temperature quantum effects of tunneling and resonance may be used to condense the functionality of many conventional VLSI devices into a smaller and more efficient subunit, thus yielding tremendous benefits for the system as a whole. In particular, two and three-terminal applications of a complimentary pair of quantum-effect devices, the resonant-tunneling diode and the tunneling-switch diode, are presented. The first example is an image-segmentation network for machine vision, implemented by using resonant-tunneling diodes in one and two-dimensional networks to extract boundaries between regions of constant spatial texture. In this case a single quantum-effect device may replace up to thirty -three CMOS transistors per pixel. The second example is an artificial neural-network processor based on multistate resistors for synaptic conductances. These programmable resistors were produced by combining a vertically -integrated stack of resonant-tunneling diodes with a resistive load and a single MOSFET driven in its ohmic region. This macrostructure has the potential to provide synaptic changes on the picosecond time scale at length scales well below one micron. The third example is a current-mode transistorless memory array based on a two-dimensional network of cells containing only a single tunneling-switch diode and a resistive load. The resulting system has the potential for reaching more than an order-of-magnitude more cell density than state-of-the-art DRAM arrays, while operating at state -of-the-art SRAM speeds and reasonable power consumption.

  1. Performance Analysis of Multiradio Transmitter with Polar or Cartesian Architectures Associated with High Efficiency Switched-Mode Power Amplifiers (invited paper

    Directory of Open Access Journals (Sweden)

    F. Robert

    2010-12-01

    Full Text Available This paper deals with wireless multi-radio transmitter architectures operating in the frequency band of 800 MHz – 6 GHz. As a consequence of the constant evolution in the communication systems, mobile transmitters must be able to operate at different frequency bands and modes according to existing standards specifications. The concept of a unique multiradio architecture is an evolution of the multistandard transceiver characterized by a parallelization of circuits for each standard. Multi-radio concept optimizes surface and power consumption. Transmitter architectures using sampling techniques and baseband ΣΔ or PWM coding of signals before their amplification appear as good candidates for multiradio transmitters for several reasons. They allow using high efficiency power amplifiers such as switched-mode PAs. They are highly flexible and easy to integrate because of their digital nature. But when the transmitter efficiency is considered, many elements have to be taken into account: signal coding efficiency, PA efficiency, RF filter. This paper investigates the interest of these architectures for a multiradio transmitter able to support existing wireless communications standards between 800 MHz and 6 GHz. It evaluates and compares the different possible architectures for WiMAX and LTE standards in terms of signal quality and transmitter power efficiency.

  2. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    Science.gov (United States)

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  3. New Architecture towards Ultrathin CdTe Solar Cells for High Conversion Efficiency

    OpenAIRE

    Teyou Ngoupo, A.; Ouédraogo, S.; Zougmoré, F.; Ndjaka, J. M. B.

    2015-01-01

    Solar Cell Capacitance Simulator in 1 Dimension (SCAPS-1D) is used to investigate the possibility of realizing ultrathin CdTe based solar cells with high and stable conversion efficiency. In the first step, we modified the conventional cell structure by substituting the CdS window layer with a CdS:O film having a wide band gap ranging from 2.42 to 3.17 eV. Thereafter, we simulated the quantum efficiency, as well as the parameters of J-V characteristics, and showed how the thickness of CdS:O l...

  4. Architectural freedom and industrialised architecture

    DEFF Research Database (Denmark)

    Vestergaard, Inge

    2012-01-01

    strategies which architects can use - to give the individual project attitudes and designs with architectural quality. Through the customized component production it is possible to choose many different proportions, to organize the process at site choosing either one room components or several rooms......Architectural freedom and industrialized architecture. Inge Vestergaard, Associate Professor, Cand. Arch. Aarhus School of Architecture, Denmark Noerreport 20, 8000 Aarhus C Telephone +45 89 36 0000 E-mai l inge.vestergaard@aarch.dk Based on the repetitive architecture from the "building boom" 1960...... to 1973 it is discussed how architects can handle these Danish element and montage buildings through the transformation to upgraded aesthetical, functional and energy efficient architecture. The method used is analysis of cases, parallels to literature studies and producer interviews. This analysis...

  5. A Smart Gateway Architecture for Improving Efficiency of Home Network Applications

    Directory of Open Access Journals (Sweden)

    Fei Ding

    2016-01-01

    Full Text Available A smart home gateway plays an important role in the Internet of Things (IoT system that takes responsibility for the connection between the network layer and the ubiquitous sensor network (USN layer. Even though the home network application is developing rapidly, researches on the home gateway based open development architecture are less. This makes it difficult to extend the home network to support new applications, share service, and interoperate with other home network systems. An integrated access gateway (IAGW is proposed in this paper which upward connects with the operator machine-to-machine platform (M2M P/F. In this home network scheme, the gateway provides standard interfaces for supporting various applications in home environments, ranging from on-site configuration to node and service access. In addition, communication management ability is also provided by M2M P/F. A testbed of a simple home network application system that includes the IAGW prototype is created to test its user interaction capabilities. Experimental results show that the proposed gateway provides significant flexibility for users to configure and deploy a home automation network; it can be applied to other monitoring areas and simultaneously supports a multi-ubiquitous sensor network.

  6. Lightweight filter architecture for energy efficient mobile vehicle localization based on a distributed acoustic sensor network.

    Science.gov (United States)

    Kim, Keonwook

    2013-08-23

    The generic properties of an acoustic signal provide numerous benefits for localization by applying energy-based methods over a deployed wireless sensor network (WSN). However, the signal generated by a stationary target utilizes a significant amount of bandwidth and power in the system without providing further position information. For vehicle localization, this paper proposes a novel proximity velocity vector estimator (PVVE) node architecture in order to capture the energy from a moving vehicle and reject the signal from motionless automobiles around the WSN node. A cascade structure between analog envelope detector and digital exponential smoothing filter presents the velocity vector-sensitive output with low analog circuit and digital computation complexity. The optimal parameters in the exponential smoothing filter are obtained by analytical and mathematical methods for maximum variation over the vehicle speed. For stationary targets, the derived simulation based on the acoustic field parameters demonstrates that the system significantly reduces the communication requirements with low complexity and can be expected to extend the operation time considerably.

  7. New Architecture towards Ultrathin CdTe Solar Cells for High Conversion Efficiency

    Directory of Open Access Journals (Sweden)

    A. Teyou Ngoupo

    2015-01-01

    Full Text Available Solar Cell Capacitance Simulator in 1 Dimension (SCAPS-1D is used to investigate the possibility of realizing ultrathin CdTe based solar cells with high and stable conversion efficiency. In the first step, we modified the conventional cell structure by substituting the CdS window layer with a CdS:O film having a wide band gap ranging from 2.42 to 3.17 eV. Thereafter, we simulated the quantum efficiency, as well as the parameters of J-V characteristics, and showed how the thickness of CdS:O layer influences output parameters of Glass/SnO2/ZTO/CdS:O/CdTe1-xSx/CdTe/Ni reference cell. High conversion efficiency of 17.30% has been found using CdTe1-xSx (x=0.12 and CdTe layers of thickness 15 nm and 4 μm, respectively. Secondly, we introduced a BSR layer between the absorber layer and back metal contact, which led to Glass/SnO2/ZTO/CdS:O/CdTe1-xSx/CdTe/BSR/Ni configuration. We found that a few nanometers (about 5 nm of CdTe1-xSx layer is sufficient to obtain high conversion efficiency. For BSR layer, different materials with large band gap, such as ZnTe, Cu2Te, and p+-CdTe, have been used in order to reduce minority carrier recombination at the back contact. When ZnTe is used, high conversion efficiency of 21.65% and better stability are obtained, compared to other BSR.

  8. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  9. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  10. Profiling high performance dense linear algebra algorithms on multicore architectures for power and energy efficiency

    KAUST Repository

    Ltaief, Hatem

    2011-08-31

    This paper presents the power profile of two high performance dense linear algebra libraries i.e., LAPACK and PLASMA. The former is based on block algorithms that use the fork-join paradigm to achieve parallel performance. The latter uses fine-grained task parallelism that recasts the computation to operate on submatrices called tiles. In this way tile algorithms are formed. We show results from the power profiling of the most common routines, which permits us to clearly identify the different phases of the computations. This allows us to isolate the bottlenecks in terms of energy efficiency. Our results show that PLASMA surpasses LAPACK not only in terms of performance but also in terms of energy efficiency. © 2011 Springer-Verlag.

  11. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  12. Core-shell nanophosphor architecture: toward efficient energy transport in inorganic/organic hybrid solar cells.

    Science.gov (United States)

    Li, Qinghua; Yuan, Yongbiao; Chen, Zihan; Jin, Xiao; Wei, Tai-huei; Li, Yue; Qin, Yuancheng; Sun, Weifu

    2014-08-13

    In this work, a core-shell nanostructure of samarium phosphates encapsulated into a Eu(3+)-doped silica shell has been successfully fabricated, which has been confirmed by X-ray diffraction, transmission electron microscopy (TEM), and high-resolution TEM. Moreover, we report the energy transfer process from the Sm(3+) to emitters Eu(3+) that widens the light absorption range of the hybrid solar cells (HSCs) and the strong enhancement of the electron-transport of TiO2/poly(3-hexylthiophene) (P3HT) bulk heterojunction (BHJ) HSCs by introducing the unique core-shell nanoarchitecture. Furthermore, by applying femtosecond transient absorption spectroscopy, we successfully obtain the electron transport lifetimes of BHJ systems with or without incorporating the core-shell nanophosphors (NPs). Concrete evidence has been provided that the doping of core-shell NPs improves the efficiency of electron transfers from donor to acceptor, but the hole transport almost remains unchanged. In particular, the hot electron transfer lifetime was shortened from 30.2 to 16.7 ps, i.e., more than 44% faster than pure TiO2 acceptor. Consequently, a notable power conversion efficiency of 3.30% for SmPO4@Eu(3+):SiO2 blended TiO2/P3HT HSCs is achieved at 5 wt % as compared to 1.98% of pure TiO2/P3HT HSCs. This work indicates that the core-shell NPs can efficiently broaden the absorption region, facilitate electron-transport of BHJ, and enhance photovoltaic performance of inorganic/organic HSCs.

  13. Next generation internet architecture and cyber-assisted energy efficiency in smart grids of buildings

    Science.gov (United States)

    Peterson, Robb Alex

    Northern Minnesota's iron mines are the starting point for the majority of the steel that gets produced in the United States. Their taconite processing plants use heat in furnaces to oxidize and indurate iron in the final stage of making a taconite pellet. Facilities can increase efficiencies when refractory service life is maintained. Efficiencies gained include: less fuel used, better quality control, better furnace control, and less mechanical component maintenance. Furnace refractory linings fail when the cracks that develop in them are uncontrolled or too large. These failures allow heat and gases retained by the lining to reach structural or mechanical components. Furnace control and efficiencies are also compromised when heat and gases are allowed to short circuit or escape the system. These failures are primarily the result of thermal of shock and expansion. It is common place to add stainless steel needle reinforcement to a monolithic refractory in an effort to counteract these effects. This study used several standard ASTM testing procedures to test 65% alumina mullite based refractory samples with 304 and 406 grade stainless steel needles. Mechanical property data gathered was used to analyze performance. The study found that adding reinforcement does not increase initial Compression and Cold Modulus of Ruptures strengths, however, after prolonged heat and thermal shock exposure, needles help maintain integrity and mechanical properties of samples. The study also found that corrosion due to oxidation was a major contributing factor to the way needles performed; and concluded that a concentration of 3% 406 "Alfa 1" stainless steel reinforcing needles added to the working lining of a taconite furnace is recommended.

  14. Synergetic electrode architecture for efficient graphene-based flexible organic light-emitting diodes.

    Science.gov (United States)

    Lee, Jaeho; Han, Tae-Hee; Park, Min-Ho; Jung, Dae Yool; Seo, Jeongmin; Seo, Hong-Kyu; Cho, Hyunsu; Kim, Eunhye; Chung, Jin; Choi, Sung-Yool; Kim, Taek-Soo; Lee, Tae-Woo; Yoo, Seunghyup

    2016-06-02

    Graphene-based organic light-emitting diodes (OLEDs) have recently emerged as a key element essential in next-generation displays and lighting, mainly due to their promise for highly flexible light sources. However, their efficiency has been, at best, similar to that of conventional, indium tin oxide-based counterparts. We here propose an ideal electrode structure based on a synergetic interplay of high-index TiO2 layers and low-index hole-injection layers sandwiching graphene electrodes, which results in an ideal situation where enhancement by cavity resonance is maximized yet loss to surface plasmon polariton is mitigated. The proposed approach leads to OLEDs exhibiting ultrahigh external quantum efficiency of 40.8 and 62.1% (64.7 and 103% with a half-ball lens) for single- and multi-junction devices, respectively. The OLEDs made on plastics with those electrodes are repeatedly bendable at a radius of 2.3 mm, partly due to the TiO2 layers withstanding flexural strain up to 4% via crack-deflection toughening.

  15. A programmable analog VLSI neural network processor for communication receivers.

    Science.gov (United States)

    Choi, J; Bang, S H; Sheu, B J

    1993-01-01

    An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.

  16. VLSI design for reliability. Final report, September-November 1989

    Energy Technology Data Exchange (ETDEWEB)

    Hajj, I.N.; Najm, F.N.; Yang, P.

    1990-05-01

    This report contains the results of supplementary work done related to the reliability analysis of Application Specific Very Large Scale Integrated (ASIC VLSI) CMOS circuits. The major work is currently being carried out under Task N-9-5716. The main goal of both tasks is to determine the electromigration susceptibility of VLSI circuits. Electromigration is a major reliability problem caused by the transport of atoms in a metal line due to the electron flow. Under persistent current stress, electromigration can cause deformations of the metal lines which may result in shorts or open circuits. The failure rate due to electromigration depends on the current density in the metal lines and is usually expressed as a median-time-to-failure (MTF). This work focuses on the electromigration problem in the power and ground busses. To estimate the bust MTF, an estimate of the current waveform in each branch of the bus is required. In general, the MTF is dependent on the shape of the current waveform, and not simply on its time-average. However, a very large number of such waveform shapes are possible, depending on what inputs are applied to the circuit. This is especially true for complementary metal oxide semiconductors circuits, which draw current only during switching.

  17. Visibiome: an efficient microbiome search engine based on a scalable, distributed architecture.

    Science.gov (United States)

    Azman, Syafiq Kamarul; Anwar, Muhammad Zohaib; Henschel, Andreas

    2017-07-24

    Given the current influx of 16S rRNA profiles of microbiota samples, it is conceivable that large amounts of them eventually are available for search, comparison and contextualization with respect to novel samples. This process facilitates the identification of similar compositional features in microbiota elsewhere and therefore can help to understand driving factors for microbial community assembly. We present Visibiome, a microbiome search engine that can perform exhaustive, phylogeny based similarity search and contextualization of user-provided samples against a comprehensive dataset of 16S rRNA profiles environments, while tackling several computational challenges. In order to scale to high demands, we developed a distributed system that combines web framework technology, task queueing and scheduling, cloud computing and a dedicated database server. To further ensure speed and efficiency, we have deployed Nearest Neighbor search algorithms, capable of sublinear searches in high-dimensional metric spaces in combination with an optimized Earth Mover Distance based implementation of weighted UniFrac. The search also incorporates pairwise (adaptive) rarefaction and optionally, 16S rRNA copy number correction. The result of a query microbiome sample is the contextualization against a comprehensive database of microbiome samples from a diverse range of environments, visualized through a rich set of interactive figures and diagrams, including barchart-based compositional comparisons and ranking of the closest matches in the database. Visibiome is a convenient, scalable and efficient framework to search microbiomes against a comprehensive database of environmental samples. The search engine leverages a popular but computationally expensive, phylogeny based distance metric, while providing numerous advantages over the current state of the art tool.

  18. Efficient Lookup Table-Based Adaptive Baseband Predistortion Architecture for Memoryless Nonlinearity

    Directory of Open Access Journals (Sweden)

    Waheed Khurram

    2010-01-01

    Full Text Available Digital predistortion is an effective means to compensate for the nonlinear effects of a memoryless system. In case of a cellular transmitter, a digital baseband predistorter can mitigate the undesirable nonlinear effects along the signal chain, particularly the nonlinear impairments in the radiofrequency (RF amplifiers. To be practically feasible, the implementation complexity of the predistorter must be minimized so that it becomes a cost-effective solution for the resource-limited wireless handset. This paper proposes optimizations that facilitate the design of a low-cost high-performance adaptive digital baseband predistorter for memoryless systems. A comparative performance analysis of the amplitude and power lookup table (LUT indexing schemes is presented. An optimized low-complexity amplitude approximation and its hardware synthesis results are also studied. An efficient LUT predistorter training algorithm that combines the fast convergence speed of the normalized least mean squares (NLMSs with a small hardware footprint is proposed. Results of fixed-point simulations based on the measured nonlinear characteristics of an RF amplifier are presented.

  19. Metabolic Architecture of the Cereal Grain and Its Relevance to Maximize Carbon Use Efficiency1[OPEN

    Science.gov (United States)

    Rolletschek, Hardy; Grafahrend-Belau, Eva; Munz, Eberhard; Radchuk, Volodymyr; Kartäusch, Ralf; Tschiersch, Henning; Melkus, Gerd; Schreiber, Falk; Jakob, Peter M.; Borisjuk, Ljudmilla

    2015-01-01

    Here, we have characterized the spatial heterogeneity of the cereal grain’s metabolism and demonstrated how, by integrating a distinct set of metabolic strategies, the grain has evolved to become an almost perfect entity for carbon storage. In vivo imaging revealed light-induced cycles in assimilate supply toward the ear/grain of barley (Hordeum vulgare) and wheat (Triticum aestivum). In silico modeling predicted that, in the two grain storage organs (the endosperm and embryo), the light-induced shift in solute influx does cause adjustment in metabolic flux without changes in pathway utilization patterns. The enveloping, leaf-like pericarp, in contrast, shows major shifts in flux distribution (starch metabolism, photosynthesis, remobilization, and tricarboxylic acid cycle activity) allow to refix 79% of the CO2 released by the endosperm and embryo, allowing the grain to achieve an extraordinary high carbon conversion efficiency of 95%. Shading experiments demonstrated that ears are autonomously able to raise the influx of solutes in response to light, but with little effect on the steady-state levels of metabolites or transcripts or on the pattern of sugar distribution within the grain. The finding suggests the presence of a mechanism(s) able to ensure metabolic homeostasis in the face of short-term environmental fluctuation. The proposed multicomponent modeling approach is informative for predicting the metabolic effects of either an altered level of incident light or a momentary change in the supply of sucrose. It is therefore of potential value for assessing the impact of either breeding and/or biotechnological interventions aimed at increasing grain yield. PMID:26395842

  20. Metabolic Architecture of the Cereal Grain and Its Relevance to Maximize Carbon Use Efficiency.

    Science.gov (United States)

    Rolletschek, Hardy; Grafahrend-Belau, Eva; Munz, Eberhard; Radchuk, Volodymyr; Kartäusch, Ralf; Tschiersch, Henning; Melkus, Gerd; Schreiber, Falk; Jakob, Peter M; Borisjuk, Ljudmilla

    2015-11-01

    Here, we have characterized the spatial heterogeneity of the cereal grain's metabolism and demonstrated how, by integrating a distinct set of metabolic strategies, the grain has evolved to become an almost perfect entity for carbon storage. In vivo imaging revealed light-induced cycles in assimilate supply toward the ear/grain of barley (Hordeum vulgare) and wheat (Triticum aestivum). In silico modeling predicted that, in the two grain storage organs (the endosperm and embryo), the light-induced shift in solute influx does cause adjustment in metabolic flux without changes in pathway utilization patterns. The enveloping, leaf-like pericarp, in contrast, shows major shifts in flux distribution (starch metabolism, photosynthesis, remobilization, and tricarboxylic acid cycle activity) allow to refix 79% of the CO2 released by the endosperm and embryo, allowing the grain to achieve an extraordinary high carbon conversion efficiency of 95%. Shading experiments demonstrated that ears are autonomously able to raise the influx of solutes in response to light, but with little effect on the steady-state levels of metabolites or transcripts or on the pattern of sugar distribution within the grain. The finding suggests the presence of a mechanism(s) able to ensure metabolic homeostasis in the face of short-term environmental fluctuation. The proposed multicomponent modeling approach is informative for predicting the metabolic effects of either an altered level of incident light or a momentary change in the supply of sucrose. It is therefore of potential value for assessing the impact of either breeding and/or biotechnological interventions aimed at increasing grain yield. © 2015 American Society of Plant Biologists. All Rights Reserved.

  1. Nano-architecture based photoelectrochemical water oxidation efficiency enhancement by CdS photoanodes

    Science.gov (United States)

    Pareek, Alka; Kim, Hyun Gyu; Paik, Pradip; Joardar, Joydip; Borse, Pramod H.

    2017-02-01

    In the present work, 2D nanostructuring has been utilized to impart an efficiency improvement to the hexagonal phase CdS films for the photoelectrochemical (PEC) cells those were deposited by spray pyrolysis technique. By controlling the aerosol droplet- size, population and impingement time during the spray pyrolysis deposition, various nano-features viz. randomly aligned nanorods, nanotubes and nanowires of CdS has been demonstrated for the first time. A growth mechanism has been proposed to predict the temporal evolution of the nanostructures. The prominent nanoscale structures show improved optical properties in the visible range of solar spectrum. The structural studies validate the morphological differences of nanostructures in terms of the texture coefficient analysis as well as 2D micro x-ray diffraction imaging. Electrochemical characterization is carried out to understand the effect of nanostructuring on the PEC performance of the CdS photoanodes in the sulphide (0.1 M Na2S  +  0.02 M Na2SO3) electrolyte at applied bias of 0.2 V (versus SCE). The evolution of morphology from randomly aligned rods to nanowire is responsible for improved photocurrent (3.5 times). CdS film morphology can be tuned to nanotubes, nano- rose buds and nanorod bunches even by doping Zn2+ ions in CdS lattice. Nano-structuring of doped CdS has shown enhanced performance of the photoanodes. The nanotubes structures yielded highest photocurrent density of 1.6 mA cm-2. Whereas modifying the 2D-nanostructured CdS film by simple MoO3 spray coating yields the photocurrent enhancement to 2.1 mA cm-2.

  2. Forming Different Planetary Architectures. I. The Formation Efficiency of Hot Jupiters from High-eccentricity Mechanisms

    Science.gov (United States)

    Wang, Ying; Zhou, Ji-lin; hui-gen, Liu; Meng, Zeyang

    2017-10-01

    Exoplanets discovered over the past decades have provided a new sample of giant exoplanets: hot Jupiters. For lack of enough materials in the current locations of hot Jupiters, they are perceived to form outside the snowline. Then, they migrate to the locations observed through interactions with gas disks or high-eccentricity mechanisms. We examined the efficiencies of different high-eccentricity mechanisms for forming hot Jupiters in near-coplanar multi-planet systems. These mechanisms include planet-planet scattering, the Kozai-Lidov mechanism, coplanar high-eccentricity migration, and secular chaos, as well as other two new mechanisms that we present in this work, which can produce hot Jupiters with high inclinations even in retrograde. We find that the Kozai-Lidov mechanism plays the most important role in producing hot Jupiters among these mechanisms. Secular chaos is not the usual channel for the formation of hot Jupiters due to the lack of an angular momentum deficit within {10}7{T}{in} (periods of the inner orbit). According to comparisons between the observations and simulations, we speculate that there are at least two populations of hot Jupiters. One population migrates into the boundary of tidal effects due to interactions with the gas disk, such as ups And b, WASP-47 b, and HIP 14810 b. These systems usually have at least two planets with lower eccentricities, and remain dynamically stable in compact orbital configurations. Another population forms through high-eccentricity mechanisms after the excitation of eccentricity due to dynamical instability. These kinds of hot Jupiters usually have Jupiter-like companions in distant orbits with moderate or high eccentricities.

  3. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  4. Piecewise Linear Approach for Timing Simulation of VLSI (Very-Large-Scale-Integrated) Circuits on Serial and Parallel Computers.

    Science.gov (United States)

    1987-12-01

    328 S % 33880E ° PIECEWISE LINEAR APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS Ongky Tejayadi UNIVE,’RSITY OF ILL...APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS 12. PERSONAL AUTHOR(S) Tejayadi, Ongky 13a. TYPE OF REPO~Z J,..-13b...PIECE’WISE LINEAR APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS BY ONGKY TEJAYADI B.S., University of Illinois

  5. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  6. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  7. Spike-driven synaptic plasticity: theory, simulation, VLSI implementation.

    Science.gov (United States)

    Fusi, S; Annunziato, M; Badoni, D; Salamon, A; Amit, D J

    2000-10-01

    We present a model for spike-driven dynamics of a plastic synapse, suited for aVLSI implementation. The synaptic device behaves as a capacitor on short timescales and preserves the memory of two stable states (efficacies) on long timescales. The transitions (LTP/LTD) are stochastic because both the number and the distribution of neural spikes in any finite (stimulation) interval fluctuate, even at fixed pre- and postsynaptic spike rates. The dynamics of the single synapse is studied analytically by extending the solution to a classic problem in queuing theory (Takacs process). The model of the synapse is implemented in aVLSI and consists of only 18 transistors. It is also directly simulated. The simulations indicate that LTP/LTD probabilities versus rates are robust to fluctuations of the electronic parameters in a wide range of rates. The solutions for these probabilities are in very good agreement with both the simulations and measurements. Moreover, the probabilities are readily manipulable by variations of the chip's parameters, even in ranges where they are very small. The tests of the electronic device cover the range from spontaneous activity (3-4 Hz) to stimulus-driven rates (50 Hz). Low transition probabilities can be maintained in all ranges, even though the intrinsic time constants of the device are short (approximately 100 ms). Synaptic transitions are triggered by elevated presynaptic rates: for low presynaptic rates, there are essentially no transitions. The synaptic device can preserve its memory for years in the absence of stimulation. Stochasticity of learning is a result of the variability of interspike intervals; noise is a feature of the distributed dynamics of the network. The fact that the synapse is binary on long timescales solves the stability problem of synaptic efficacies in the absence of stimulation. Yet stochastic learning theory ensures that it does not affect the collective behavior of the network, if the transition probabilities are

  8. Efficient Processing of a Rainfall Simulation Watershed on an FPGA-Based Architecture with Fast Access to Neighbourhood Pixels

    Directory of Open Access Journals (Sweden)

    Yeong LeeSeng

    2009-01-01

    Full Text Available This paper describes a hardware architecture to implement the watershed algorithm using rainfall simulation. The speed of the architecture is increased by utilizing a multiple memory bank approach to allow parallel access to the neighbourhood pixel values. In a single read cycle, the architecture is able to obtain all five values of the centre and four neighbours for a 4-connectivity watershed transform. The storage requirement of the multiple bank implementation is the same as a single bank implementation by using a graph-based memory bank addressing scheme. The proposed rainfall watershed architecture consists of two parts. The first part performs the arrowing operation and the second part assigns each pixel to its associated catchment basin. The paper describes the architecture datapath and control logic in detail and concludes with an implementation on a Xilinx Spartan-3 FPGA.

  9. Architectural freedom and industrialized architecture

    DEFF Research Database (Denmark)

    Vestergaard, Inge

    2012-01-01

    proportions, to organize the process on site choosing either one room wall components or several rooms wall components – either horizontally or vertically. Combined with the seamless joint the playing with these possibilities the new industrialized architecture can deliver variations in choice of solutions......Based on the repetitive architecture from the “building boom” from 1960 to 1973, it is discussed how architects can handle these Danish element and montage buildings through the transformation to upgraded aesthetical, functional and energy efficient architecture. The method used is analysis...... of cases, parallels to literature studies and client and producer interviews. The analysis compares best practice in Denmark and best practice in Austria. Modern architects accepted the fact that industrialized architecture told the storey of repetition and monotony as basic condition. This article aims...

  10. DeF-GPU: Efficient and effective deletions finding in hepatitis B viral genomic DNA using a GPU architecture.

    Science.gov (United States)

    Cheng, Chun-Pei; Lan, Kuo-Lun; Liu, Wen-Chun; Chang, Ting-Tsung; Tseng, Vincent S

    2016-12-01

    Hepatitis B viral (HBV) infection is strongly associated with an increased risk of liver diseases like cirrhosis or hepatocellular carcinoma (HCC). Many lines of evidence suggest that deletions occurring in HBV genomic DNA are highly associated with the activity of HBV via the interplay between aberrant viral proteins release and human immune system. Deletions finding on the HBV whole genome sequences is thus a very important issue though there exist underlying the challenges in mining such big and complex biological data. Although some next generation sequencing (NGS) tools are recently designed for identifying structural variations such as insertions or deletions, their validity is generally committed to human sequences study. This design may not be suitable for viruses due to different species. We propose a graphics processing unit (GPU)-based data mining method called DeF-GPU to efficiently and precisely identify HBV deletions from large NGS data, which generally contain millions of reads. To fit the single instruction multiple data instructions, sequencing reads are referred to as multiple data and the deletion finding procedure is referred to as a single instruction. We use Compute Unified Device Architecture (CUDA) to parallelize the procedures, and further validate DeF-GPU on 5 synthetic and 1 real datasets. Our results suggest that DeF-GPU outperforms the existing commonly-used method Pindel and is able to exactly identify the deletions of our ground truth in few seconds. The source code and other related materials are available at https://sourceforge.net/projects/defgpu/. Copyright © 2016 Elsevier Inc. All rights reserved.

  11. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    Science.gov (United States)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  12. A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

    Science.gov (United States)

    Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

    2013-01-01

    This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

  13. Mapping of H.264 decoding on a multiprocessor architecture

    Science.gov (United States)

    van der Tol, Erik B.; Jaspers, Egbert G.; Gelderblom, Rob H.

    2003-05-01

    Due to the increasing significance of development costs in the competitive domain of high-volume consumer electronics, generic solutions are required to enable reuse of the design effort and to increase the potential market volume. As a result from this, Systems-on-Chip (SoCs) contain a growing amount of fully programmable media processing devices as opposed to application-specific systems, which offered the most attractive solutions due to a high performance density. The following motivates this trend. First, SoCs are increasingly dominated by their communication infrastructure and embedded memory, thereby making the cost of the functional units less significant. Moreover, the continuously growing design costs require generic solutions that can be applied over a broad product range. Hence, powerful programmable SoCs are becoming increasingly attractive. However, to enable power-efficient designs, that are also scalable over the advancing VLSI technology, parallelism should be fully exploited. Both task-level and instruction-level parallelism can be provided by means of e.g. a VLIW multiprocessor architecture. To provide the above-mentioned scalability, we propose to partition the data over the processors, instead of traditional functional partitioning. An advantage of this approach is the inherent locality of data, which is extremely important for communication-efficient software implementations. Consequently, a software implementation is discussed, enabling e.g. SD resolution H.264 decoding with a two-processor architecture, whereas High-Definition (HD) decoding can be achieved with an eight-processor system, executing the same software. Experimental results show that the data communication considerably reduces up to 65% directly improving the overall performance. Apart from considerable improvement in memory bandwidth, this novel concept of partitioning offers a natural approach for optimally balancing the load of all processors, thereby further improving the

  14. High-efficiency dynamic routing architecture for the readout of single photon avalanche diode arrays in time-correlated measurements

    Science.gov (United States)

    Cominelli, A.; Acconcia, G.; Peronio, P.; Rech, I.; Ghioni, M.

    2017-05-01

    transfer rate towards the elaboration unit. We developed a novel readout architecture, starting from a completely different perspective: considering the maximum data rate we can manage with a PC, a limited set of conversion data is selected and transferred to the elaboration unit during each excitation period, in order to take full advantage of the bus bandwidth toward the PC. In particular, we introduce a smart routing logic, able to dynamically connect a large number of SPAD detectors to a limited set of high-performance external acquisition chains, paving the way for a more efficient use of resources and allowing us to effectively break the tradeoff between integration and performance, which affects the solutions proposed so far. The routing electronic features a pixelated architecture, while 3D-stacking techniques are exploited to connect each SPAD to its dedicated electronic, leading to a minimization of the overall number of interconnections crossing the integrated system, which is one of the main issues in high-density arrays.

  15. Turbo decoder architecture for beyond-4G applications

    CERN Document Server

    Wong, Cheng-Chi

    2013-01-01

    This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respec

  16. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  17. Towards a sustainable architecture: Adequate to the environment and of maximum energy efficiency; Hacia una arquitectura sustentable: adecuada al ambiente y de maxima eficiencia energetica

    Energy Technology Data Exchange (ETDEWEB)

    Morillon Galvez, David [Comision Nacional para el Ahorro de Energia, Mexico, D. F. (Mexico)

    1999-07-01

    An analysis of the elements and factors that the architecture of buildings must have to be sustainable, such as: a design adequate to the environment, saving and efficient use of alternate energies, and the auto-supply is presented. In addition a methodology for the natural air conditioning (bioclimatic architecture) of buildings, as well as ideas for the saving and efficient use of energy, with the objective of contributing to the adequate use of components of the building (walls, ceilings, floors etc.), is presented, that when interacting with the environment it takes advantage of it, without deterioration of the same, obtaining energy efficient designs. [Spanish] Se presenta un analisis de los elementos y factores que debe tener la arquitectura de edificios para ser sustentable, como; un diseno adecuado al ambiente, ahorro y uso eficiente de la energia, el uso de energias alternas y el autoabastecimiento. Ademas se propone una metodologia para la climatizacion natural (arquitectura bioclimatica) de edificios, asi como ideas para el ahorro y uso eficiente de energia, con el objetivo de aportar al uso adecuado de componentes del edificio (muros, techos, pisos etc.) que al interactuar con el ambiente tome ventaja de el, sin deterioro del mismo, logrando disenos energeticamente eficientes.

  18. A novel triple-layer zinc oxide/carbon nanotube architecture for dye-sensitized solar cells with excellent power conversion efficiency

    Science.gov (United States)

    Hu, Jing; Xie, Yahong; Bai, Te; Zhang, Chunyang; Wang, Jide

    2015-07-01

    A novel triple-layer photoanode architecture, composed of ZnO and ZnO/CNT nanostructure semiconductor films for dye-sensitized solar cell with excellent power conversion efficiency is fabricated by a simple strategy. A convenient and effective method is applied to disperse the multiwalled carbon nanotube (MWCNT). The structure, morphology and light absorption of the novel hybrid photoanode are characterized by X-ray diffraction, scanning electron microscopy, and UV-vis absorption spectroscopy analyze. Results indicate that the ZnO has a typical wurtzite structure and the MWCNTs are homogeneously dispersed in ZnO. Current-voltage curves demonstrate CNT-0.5 with 0.05wt% of carbon nanotube (CNT) is the most suitable in improving the performance of DSSCs, and the power conversion efficiency of ZnO/CNT-0.5-0.05wt% is 6.25%, which is 35.57% higher than those without CNTs (4.61%). Finally, electrochemical impedance spectra confirms that the abundant dyes absorption by the ZnO layer and large numbers of direct pathway for electron transport provided by the MWCNTs are attributed to the high efficiency of this new DSSC. This result is remarkable and provides a novel triple-layer ZnO/CNT architecture in improving the performance of DSSCs.

  19. Real-time stereo matching architecture based on 2D MRF model: a memory-efficient systolic array

    Directory of Open Access Journals (Sweden)

    Park Sungchan

    2011-01-01

    Full Text Available Abstract There is a growing need in computer vision applications for stereopsis, requiring not only accurate distance but also fast and compact physical implementation. Global energy minimization techniques provide remarkably precise results. But they suffer from huge computational complexity. One of the main challenges is to parallelize the iterative computation, solving the memory access problem between the big external memory and the massive processors. Remarkable memory saving can be obtained with our memory reduction scheme, and our new architecture is a systolic array. If we expand it into N's multiple chips in a cascaded manner, we can cope with various ranges of image resolutions. We have realized it using the FPGA technology. Our architecture records 19 times smaller memory than the global minimization technique, which is a principal step toward real-time chip implementation of the various iterative image processing algorithms with tiny and distributed memory resources like optical flow, image restoration, etc.

  20. Exploration and Evaluation of Nanometer Low-power Multi-core VLSI Computer Architectures

    Science.gov (United States)

    2015-03-01

    Steven Helmer, Andrea Lapiana, Giuseppe Lapiana, Rich Linderman, Tom Renz, John Rooks, Ross Thompson, Lisa Weyna, and Qing Wu. iii 1...a script-based language that most EDA-vendors support called Tool Command Language (Tcl). John Ousterhout invented Tcl while he was a faculty...Integrated Circuit Technology, 2006. ICSICT 󈧊. 8th International Conference on, 2006, pp. 1610-1613. [11] R. Chau, J. Brask, S. Datta, G. Dewey , M

  1. VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

    National Research Council Canada - National Science Library

    Kuo, Huang-Chih; Lin, Youn-Long

    2013-01-01

    Intra-frame encoding is useful for many video applications such as security surveillance, digital cinema, and video conferencing because it supports random access to every video frame for easy editing...

  2. VLSI top-down design based on the separation of hierarchies

    NARCIS (Netherlands)

    Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

    1986-01-01

    Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

  3. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  4. Architecture on Architecture

    DEFF Research Database (Denmark)

    Olesen, Karen

    2016-01-01

    This paper will discuss the challenges faced by architectural education today. It takes as its starting point the double commitment of any school of architecture: on the one hand the task of preserving the particular knowledge that belongs to the discipline of architecture, and on the other hand...... the obligation to prepare students to perform in a profession that is largely defined by forces outside that discipline. It will be proposed that the autonomy of architecture can be understood as a unique kind of information: as architecture’s self-reliance or knowledge-about itself. A knowledge...... that is not scientific or academic but is more like a latent body of data that we find embedded in existing works of architecture. This information, it is argued, is not limited by the historical context of the work. It can be thought of as a virtual capacity – a reservoir of spatial configurations that can...

  5. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    Directory of Open Access Journals (Sweden)

    Jen-Chih Kuo

    2003-12-01

    Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

  6. SET: Session Layer-Assisted Efficient TCP Management Architecture for 6LoWPAN with Multiple Gateways

    Directory of Open Access Journals (Sweden)

    Akbar AliHammad

    2010-01-01

    Full Text Available 6LoWPAN (IPv6 based Low-Power Personal Area Network is a protocol specification that facilitates communication of IPv6 packets on top of IEEE 802.15.4 so that Internet and wireless sensor networks can be inter-connected. This interconnection is especially required in commercial and enterprise applications of sensor networks where reliable and timely data transfers such as multiple code updates are needed from Internet nodes to sensor nodes. For this type of inbound traffic which is mostly bulk, TCP as transport layer protocol is essential, resulting in end-to-end TCP session through a default gateway. In this scenario, a single gateway tends to become the bottleneck because of non-uniform connectivity to all the sensor nodes besides being vulnerable to buffer overflow. We propose SET; a management architecture for multiple split-TCP sessions across a number of serving gateways. SET implements striping and multiple TCP session management through a shim at session layer. Through analytical modeling and ns2 simulations, we show that our proposed architecture optimizes communication for ingress bulk data transfer while providing associated load balancing services. We conclude that multiple split-TCP sessions managed in parallel across a number of gateways result in reduced latency for bulk data transfer and provide robustness against gateway failures.

  7. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  8. Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off

    DEFF Research Database (Denmark)

    Gleerup, Thomas Møller; Holten-Lund, Hans Erik; Madsen, Jan

    2000-01-01

    This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance requirement of this application is a frame rate of 25 frames per second when rendering 3D models with 2 million triangles, i....... In software, forward differencing is usually better, but in this hardware implementation, the trade-off has made it possible to develop a very regular memory architecture with a buffering system, which can reach 95% bandwidth utilization using off-the-shelf SDRAM, This is achieved by changing the algorithm...... to use a memory access strategy with write-only and read-only phases, and a buffering system, which uses round-robin bank write-access combined with burst read-access....

  9. Architectural slicing

    DEFF Research Database (Denmark)

    Christensen, Henrik Bærbak; Hansen, Klaus Marius

    2013-01-01

    Architectural prototyping is a widely used practice, con- cerned with taking architectural decisions through experiments with light- weight implementations. However, many architectural decisions are only taken when systems are already (partially) implemented. This is prob- lematic in the context...... a system and a slicing criterion, architectural slicing produces an architectural prototype that contain the elements in the architecture that are dependent on the ele- ments in the slicing criterion. Furthermore, we present an initial design and implementation of an architectural slicer for Java....

  10. Achieving Extreme Utilization of Excitons by an Efficient Sandwich-Type Emissive Layer Architecture for Reduced Efficiency Roll-Off and Improved Operational Stability in Organic Light-Emitting Diodes.

    Science.gov (United States)

    Wu, Zhongbin; Sun, Ning; Zhu, Liping; Sun, Hengda; Wang, Jiaxiu; Yang, Dezhi; Qiao, Xianfeng; Chen, Jiangshan; Alshehri, Saad M; Ahamad, Tansir; Ma, Dongge

    2016-02-10

    It has been demonstrated that the efficiency roll-off is generally caused by the accumulation of excitons or charge carriers, which is intimately related to the emissive layer (EML) architecture in organic light-emitting diodes (OLEDs). In this article, an efficient sandwich-type EML structure with a mixed-host EML sandwiched between two single-host EMLs was designed to eliminate this accumulation, thus simultaneously achieving high efficiency, low efficiency roll-off and good operational stability in the resulting OLEDs. The devices show excellent electroluminescence performances, realizing a maximum external quantum efficiency (EQE) of 24.6% with a maximum power efficiency of 105.6 lm W(-1) and a maximum current efficiency of 93.5 cd A(-1). At the high brightness of 5,000 cd m(-2), they still remain as high as 23.3%, 71.1 lm W(-1), and 88.3 cd A(-1), respectively. And, the device lifetime is up to 2000 h at initial luminance of 1000 cd m(-2), which is significantly higher than that of compared devices with conventional EML structures. The improvement mechanism is systematically studied by the dependence of the exciton distribution in EML and the exciton quenching processes. It can be seen that the utilization of the efficient sandwich-type EML broadens the recombination zone width, thus greatly reducing the exciton quenching and increasing the probability of the exciton recombination. It is believed that the design concept provides a new avenue for us to achieve high-performance OLEDs.

  11. UW/NW (University of Washington/Northwest) VLSI Consortium

    Science.gov (United States)

    1985-10-30

    fabricated did not (by simulation evidence) meet the SOns PLA None durectly. The osi gatrateaon wor dot p"f ranc goatmor requirements but by then...was no interdependence among the architectural compo- * use design generators nents on clock characteristics, which promoted more indepeu- deuce among

  12. Design and Prototyping Flow of Flexible and Efficient NISC-Based Architectures for MIMO Turbo Equalization and Demapping

    Directory of Open Access Journals (Sweden)

    Mostafa Rizk

    2016-08-01

    Full Text Available In the domain of digital wireless communication, flexible design implementations are increasingly explored for different applications in order to cope with diverse system configurations imposed by the emerging wireless communication standards. In fact, shrinking the design time to meet market pressure, on the one hand, and adding the emerging flexibility requirement and, hence, increasing system complexity, on the other hand, require a productive design approach that also ensures final design quality. The no instruction set computer (NISC approach fulfills these design requirements by eliminating the instruction set overhead. The approach offers static scheduling of the datapath, automated register transfer language (RTLsynthesis and allows the designer to have direct control of hardware resources. This paper presents a complete NISC-based design and prototype flow, from architecture specification till FPGA implementation. The proposed design and prototype flow is illustrated through two case studies of flexible implementations, which are dedicated to low-complexity MIMO turbo-equalizer and a universal turbo-demapper. Moreover, the flexibility of the proposed prototypes allows supporting all communication modes defined in the emerging wireless communication standards, such LTE, LTE-Advanced, WiMAX, WiFi and DVB-RCS. For each prototype, its functionality is evaluated, and the resultant performance is verified for all system configurations.

  13. Co@Co3O4 nanoparticle embedded nitrogen-doped carbon architectures as efficient bicatalysts for oxygen reduction and evolution reactions

    Science.gov (United States)

    Qi, Chunling; Zhang, Li; Xu, Guancheng; Sun, Zhipeng; Zhao, Aihua; Jia, Dianzeng

    2018-01-01

    The oxygen reduction reaction (ORR) and oxygen evolution reaction (OER) play crucial roles in efficient energy conversion and storage solutions. Here, Co@Co3O4 nanoparticle embedded nitrogen-doped carbon architectures (denoted as Co@Co3O4/NCs) are prepared via a simple two-step and in situ approach by carbonization and subsequent oxidation of Co-MOF containing high contents of carbon and nitrogen. When evaluated as electrocatalyst towards both ORR and OER in a KOH electrolyte solution, the as-fabricated Co@Co3O4/NC-2 exhibits similar ORR catalytic activity to the commercial Pt/C catalyst, but superior stability and good methanol tolerance. Furthermore, the as-fabricated catalysts also show promising catalytic activity for OER. The effective catalytic activities originate from the synergistic effects between well wrapped Co@Co3O4 nanoparticles and nitrogen doped carbon structures.

  14. Hyperbranched-dendrimer architectural copolymer gene delivery using hyperbranched PEI conjugated to poly(propyleneimine) dendrimers: synthesis, characterization, and evaluation of transfection efficiency

    Science.gov (United States)

    Alavi, Seyyed Jamal; Gholami, Leila; Askarian, Saeedeh; Darroudi, Majid; Massoudi, Abdolhossein; Rezaee, Mehdi; Kazemi Oskuee, Reza

    2017-02-01

    The applications of dendrimer-based vectors seem to be promising in non-viral gene delivery because of their potential for addressing the problems with viral vectors. In this study, generation 3 poly(propyleneimine) (G3-PPI) dendrimers with 1, 4-diaminobutane as a core initiator was synthesized using a divergent growth approach. To increase the hydrophobicity and reduce toxicity, 10% of primary amines of G3-PPI dendrimers were replaced with bromoalkylcarboxylates with different chain lengths (6-bromohexanoic and 10-bromodecanoic). Then, to retain the overall buffering capacity and enhance transfection, the alkylcarboxylate-PPIs were conjugated to 10 kDa branched polyethylenimine (PEI). The results showed that the modified PPI was able to form complexes with the diameter of less than 60 nm with net-positive surface charge around 20 mV. No significant toxicity was observed in modified PPIs; however, the hexanoate conjugated PPI-PEI (PPI-HEX-10% PEI) and the decanoate conjugated PPI-PEI (PPI-DEC-10%-PEI) showed the best transfection efficiency in murine neuroblastoma (Neuro-2a) cell line, even PPI-HEX-10%-PEI showed transfection efficiency equal to standard PEI 25 kDa with reduced toxicity. This study suggested a new series of hyperbranched (PEI)-dendrimer (PPI) architectural copolymers as non-viral gene delivery vectors with high transfection efficiency and low toxicity.

  15. Hyperbranched–dendrimer architectural copolymer gene delivery using hyperbranched PEI conjugated to poly(propyleneimine) dendrimers: synthesis, characterization, and evaluation of transfection efficiency

    Energy Technology Data Exchange (ETDEWEB)

    Alavi, Seyyed Jamal [Ferdowsi University of Mashhad, Department of Chemistry, Faculty of Science (Iran, Islamic Republic of); Gholami, Leila [Mashhad University of Medical Sciences, Department of Modern Sciences and Technologies, School of Medicine (Iran, Islamic Republic of); Askarian, Saeedeh [Mashhad University of Medical Sciences, Department of Medical Biotechnology, School of Medicine (Iran, Islamic Republic of); Darroudi, Majid [Mashhad University of Medical Sciences, Nuclear Medicine Research Center (Iran, Islamic Republic of); Massoudi, Abdolhossein [University of Payam noor, Department of Chemistry (Iran, Islamic Republic of); Rezaee, Mehdi; Kazemi Oskuee, Reza, E-mail: Oskueekr@mums.ac.ir [Mashhad University of Medical Sciences, Department of Medical Biotechnology, School of Medicine (Iran, Islamic Republic of)

    2017-02-15

    The applications of dendrimer-based vectors seem to be promising in non-viral gene delivery because of their potential for addressing the problems with viral vectors. In this study, generation 3 poly(propyleneimine) (G3-PPI) dendrimers with 1, 4-diaminobutane as a core initiator was synthesized using a divergent growth approach. To increase the hydrophobicity and reduce toxicity, 10% of primary amines of G3-PPI dendrimers were replaced with bromoalkylcarboxylates with different chain lengths (6-bromohexanoic and 10-bromodecanoic). Then, to retain the overall buffering capacity and enhance transfection, the alkylcarboxylate–PPIs were conjugated to 10 kDa branched polyethylenimine (PEI). The results showed that the modified PPI was able to form complexes with the diameter of less than 60 nm with net-positive surface charge around 20 mV. No significant toxicity was observed in modified PPIs; however, the hexanoate conjugated PPI–PEI (PPI-HEX-10% PEI) and the decanoate conjugated PPI–PEI (PPI-DEC-10%-PEI) showed the best transfection efficiency in murine neuroblastoma (Neuro-2a) cell line, even PPI-HEX-10%-PEI showed transfection efficiency equal to standard PEI 25 kDa with reduced toxicity. This study suggested a new series of hyperbranched (PEI)–dendrimer (PPI) architectural copolymers as non-viral gene delivery vectors with high transfection efficiency and low toxicity.

  16. Single-unit-cell layer established Bi 2 WO 6 3D hierarchical architectures: Efficient adsorption, photocatalysis and dye-sensitized photoelectrochemical performance

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Hongwei; Cao, Ranran; Yu, Shixin; Xu, Kang; Hao, Weichang; Wang, Yonggang; Dong, Fan; Zhang, Tierui; Zhang, Yihe

    2017-12-01

    Single-layer catalysis sparks huge interests and gains widespread attention owing to its high activity. Simultaneously, three-dimensional (3D) hierarchical structure can afford large surface area and abundant reactive sites, contributing to high efficiency. Herein, we report an absorbing single-unit-cell layer established Bi2WO6 3D hierarchical architecture fabricated by a sodium dodecyl benzene sulfonate (SDBS)-assisted assembled strategy. The DBS- long chains can adsorb on the (Bi2O2)2+ layers and hence impede stacking of the layers, resulting in the single-unit-cell layer. We also uncovered that SDS with a shorter chain is less effective than SDBS. Due to the sufficient exposure of surface O atoms, single-unit-cell layer 3D Bi2WO6 shows strong selectivity for adsorption on multiform organic dyes with different charges. Remarkably, the single-unit-cell layer 3D Bi2WO6 casts profoundly enhanced photodegradation activity and especially a superior photocatalytic H2 evolution rate, which is 14-fold increase in contrast to the bulk Bi2WO6. Systematic photoelectrochemical characterizations disclose that the substantially elevated carrier density and charge separation efficiency take responsibility for the strengthened photocatalytic performance. Additionally, the possibility of single-unit-cell layer 3D Bi2WO6 as dye-sensitized solar cells (DSSC) has also been attempted and it was manifested to be a promising dye-sensitized photoanode for oxygen evolution reaction (ORR). Our work not only furnish an insight into designing single-layer assembled 3D hierarchical architecture, but also offer a multi-functional material for environmental and energy applications.

  17. An Energy-Efficient and Scalable Deep Learning/Inference Processor With Tetra-Parallel MIMD Architecture for Big Data Applications.

    Science.gov (United States)

    Park, Seong-Wook; Park, Junyoung; Bong, Kyeongryeol; Shin, Dongjoo; Lee, Jinmook; Choi, Sungpill; Yoo, Hoi-Jun

    2015-12-01

    Deep Learning algorithm is widely used for various pattern recognition applications such as text recognition, object recognition and action recognition because of its best-in-class recognition accuracy compared to hand-crafted algorithm and shallow learning based algorithms. Long learning time caused by its complex structure, however, limits its usage only in high-cost servers or many-core GPU platforms so far. On the other hand, the demand on customized pattern recognition within personal devices will grow gradually as more deep learning applications will be developed. This paper presents a SoC implementation to enable deep learning applications to run with low cost platforms such as mobile or portable devices. Different from conventional works which have adopted massively-parallel architecture, this work adopts task-flexible architecture and exploits multiple parallelism to cover complex functions of convolutional deep belief network which is one of popular deep learning/inference algorithms. In this paper, we implement the most energy-efficient deep learning and inference processor for wearable system. The implemented 2.5 mm × 4.0 mm deep learning/inference processor is fabricated using 65 nm 8-metal CMOS technology for a battery-powered platform with real-time deep inference and deep learning operation. It consumes 185 mW average power, and 213.1 mW peak power at 200 MHz operating frequency and 1.2 V supply voltage. It achieves 411.3 GOPS peak performance and 1.93 TOPS/W energy efficiency, which is 2.07× higher than the state-of-the-art.

  18. Dynamic Neural Fields as a Step Towards Cognitive Neuromorphic Architectures

    Directory of Open Access Journals (Sweden)

    Yulia eSandamirskaya

    2014-01-01

    Full Text Available Dynamic Field Theory (DFT is an established framework for modelling embodied cognition. In DFT, elementary cognitive functions such as memory formation, formation of grounded representations, attentional processes, decision making, adaptation, and learning emerge from neuronal dynamics. The basic computational element of this framework is a Dynamic Neural Field (DNF. Under constraints on the time-scale of the dynamics, the DNF is computationally equivalent to a soft winner-take-all (WTA network, which is considered one of the basic computational units in neuronal processing. Recently, it has been shown how a WTA network may be implemented in neuromorphic hardware, such as analogue Very Large Scale Integration (VLSI device. This paper leverages the relationship between DFT and soft WTA networks to systematically revise and integrate established DFT mechanisms that have previously been spread among different architectures. In addition, I also identify some novel computational and architectural mechanisms of DFT which may be implemented in neuromorphic VLSI devices using WTA networks as an intermediate computational layer. These specific mechanisms include the stabilization of working memory, the coupling of sensory systems to motor dynamics, intentionality, and autonomous learning. I further demonstrate how all these elements may be integrated into a unified architecture to generate behavior and autonomous learning.

  19. Enterprise architecture evaluation using architecture framework and UML stereotypes

    OpenAIRE

    Narges Shahi; Ali Haroun Abadi; Hadi abooei mehrizi

    2014-01-01

    There is an increasing need for enterprise architecture in numerous organizations with complicated systems with various processes. Support for information technology, organizational units whose elements maintain complex relationships increases. Enterprise architecture is so effective that its non-use in organizations is regarded as their institutional inability in efficient information technology management. The enterprise architecture process generally consists of three phases including stra...

  20. INTERNAL MEASUREMENTS FOR FAILURE ANALYSIS AND CHIP VERIFICATION OF VLSI CIRCUITS

    OpenAIRE

    KÖlzer, J.; Otto, J.

    1989-01-01

    Chip verification and failure analysis during the design evaluation of very large scale integrated (VLSI) devices call for highly accurate internal analysis methods. After having characterized the first silicon by automated functional testing, classification and statistical analysis can be carried out : In this way a rough electrical evaluation of the material under investigation can be made. Further clues to a faulty device behavior can only be obtained by internal measurements. Serious malf...

  1. Simulation-based analysis for NBTI degradation in combinational CMOS VLSI circuits

    OpenAIRE

    Georgiev, Zdravko

    2013-01-01

    The negative-bias temperature instability (NBTI) is one of the dominant aging degradation mechanisms in today Very Large Scale Integration (VLSI) Integrated Circuits (IC). With the further decreasing of the transistor dimensions and reduction of supply voltage, the NBTI degradation may become a critical reliability threat. Nevertheless, most of the EDA tools lack in the ability to predict and analyse the impact of the NBTI. Other tools able to analyse the NBTI, are often on very low design le...

  2. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  3. A parallel architecture for digital filtering using Fermat number transforms

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C.-S.; Shao, H. M.

    1983-01-01

    In this correspondence, a parallel architecture is developed to compute the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT). In particular, a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. The overlap-save method is generalized for the FNT to realize a digital filter of arbitrary length. The generalized overlap-save method alleviates the usual dynamic range limitation of FNT's of long transform lengths. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNT's of 128 points. Its architecture is regular, simple, and flexible, and therefore naturally suitable for VLSI implementation.

  4. An evaluation of the software architecture efficiency using the Clichés and behavioral diagrams pertaining to the unified modeling language

    National Research Council Canada - National Science Library

    Siamak Khaksar Haghani; Yousef Abbasnejad; Ali Harounabadi

    2014-01-01

    .... It creates an executable model from these diagrams; yet, since the UML is a standard semi-formal language for describing the software architecture, evaluating the software architecture is not directly possible...

  5. Generic Integrating Business Architecture

    Directory of Open Access Journals (Sweden)

    Mihaela MURESAN

    2006-01-01

    Full Text Available The generic business architecture offers an efficient solution for the business engineering and re-engineering processes. This approach strengthen the cooperation between the main actors involved in the business architecture design and implementation, aiming at including all the significant views in a integrated model. The main goal of the development of generic business architectures is to offer a standard model for the integration of the internal processes and for a better management of the technological and informational resources of the enterprise. Such standardization has as main benefits the increase of the management quality and the efficiency in the business engineering processes.

  6. ArcFVDSL, a DSEL Combined to HARTS, a Runtime System Layer to Implement Efficient Numerical Methods to Solve Diffusive Problems on New Heterogeneous Hardware Architecture

    Directory of Open Access Journals (Sweden)

    Gratien Jean-Marc

    2017-03-01

    Full Text Available Nowadays, some frameworks like Arcane and Dune offer a number of advanced tools to deal with the complexity related to parallelism, meshes and linear solvers. However, they do not handle the high level complexity related to discretization methods and physical models. Generative programming and Domain Specific Languages (DSL are key technologies allowing to write code with a high level expressive language and take advantage of the efficiency of generated code with low level services. DSL may be embedded in host languages like Python or C++. Such languages, named in that case Domain Specific Embedded Languages (DSEL, are applied for instance in frameworks like Fenics or Feel++ which are dedicated to the domain of Finite Element (FE methods and Galerkin methods. ArcFVDSL is a DSEL developed on top of the Arcane framework, aiming to implement various lowest order methods (Finite-Volume (FV, Mimetic Finite Difference (MFD, Mixed Hybrid Finite Volume (MHFV, etc. for diffusive problems on general meshes. In this paper, we present various implementations of different complex academic problems. We focus on the capability of the language to allow the description and the resolution of these problems with several lowest-order methods. We illustrate the benefits of such technology combined to runtime system tools like Heterogeneous Abstract RunTime System (HARTS and its ability to handle seamlessly new heterogeneous architectures with multi-core processors enhanced by General Purpose computing on Graphics Processing Units (GP-GPU. We present the performance results of each implementation on different kinds of heterogeneous hardware architecture.

  7. Improving Device Efficiencies in Organic Photovoltaics through the Manipulation of Device Architectures and the Development of Low-Bandgap Materials

    Science.gov (United States)

    Rice, Andrew Hideo

    Over the past two decades, vast amounts of research have been conducted in the pursuit of suitable organic semiconductors to replace inorganic materials in electronic applications due to their advantages of being lightweight, flexible, and solution-processible. However, before organic photovoltaics (OPVs) can be truly competitive and commercially viable, their efficiencies must be improved significantly. In this examination, we pursue higher efficiency OPVs in two different ways. Our attempts focus on 1) altering the microstructure of devices to improve charge dissociation, charge transport, and our understanding of how these devices function, and 2) tailoring materials to achieve optimal band gaps and energy levels for use in organic electronics. First, we demonstrate how the vertical morphology of bulk heterojunction (BHJ) solar cells, with an active layer consisting of self-assembled poly(3-hexylthiophene) (P3HT) nanowires and (6,6)-phenyl C61-butyric acid methyl ester (PCBM), can be beneficially influenced. Most device fabrication routes using similar materials employ an annealing step to influence active layer morphology, but this process can create an unfavorable phase migration where P3HT is driven toward the cathode. In contrast, we demonstrate devices that exhibit an increase in relative fullerene concentration at the top of the active layer by introducing the donor phase as a solid nanowire in the active layer solution and altering the pre-spin drying time. X-ray photoelectron spectroscopy (XPS) and conductive and photoconductive atomic force microscopy (cAFM and pcAFM) provide detailed information about how the surface of the active layer can be influenced; this is done by tracking the concentration and alignment of P3HT and PCBM domains. Using this new procedure, devices are made with power conversion efficiencies surpassing 2%. Additionally, we show that nanowires grown in the presence of the fullerene perform differently than those that are grown and

  8. Architectural prototyping

    DEFF Research Database (Denmark)

    Bardram, Jakob Eyvind; Christensen, Henrik Bærbak; Hansen, Klaus Marius

    2004-01-01

    A major part of software architecture design is learning how specific architectural designs balance the concerns of stakeholders. We explore the notion of "architectural prototypes", correspondingly architectural prototyping, as a means of using executable prototypes to investigate stakeholders......' concerns with respect to a system under development. An architectural prototype is primarily a learning and communication vehicle used to explore and experiment with alternative architectural styles, features, and patterns in order to balance different architectural qualities. The use of architectural...... prototypes in the development process is discussed, and we argue that such prototypes can play a role throughout the entire process. The use of architectural prototypes is illustrated by three distinct cases of creating software systems. We argue that architectural prototyping can provide key insights...

  9. Architectural Prototyping

    DEFF Research Database (Denmark)

    Bardram, Jakob; Christensen, Henrik Bærbak; Hansen, Klaus Marius

    2004-01-01

    A major part of software architecture design is learning how specific architectural designs balance the concerns of stakeholders. We explore the notion of "architectural prototypes", correspondingly architectural prototyping, as a means of using executable prototypes to investigate stakeholders......' concerns with respect to a system under development. An architectural prototype is primarily a learning and communication vehicle used to explore and experiment with alternative architectural styles, features, and patterns in order to balance different architectural qualities. The use of architectural...... prototypes in the development process is discussed, and we argue that such prototypes can play a role throughout the entire process. The use of architectural prototypes is illustrated by three distinct cases of creating software systems. We argue that architectural prototyping can provide key insights...

  10. A VLSI System-on-Chip for Particle Detectors

    CERN Document Server

    AUTHOR|(CDS)2078019

    In this thesis I present a System-on-Chip (SoC) I designed to oer a self- contained, compact data acquisition platform for micromegas detector mon- itoring. I carried on my work within the RD-51 collab oration of CERN. With a companion ADC, my architecture is capable to acquire the signal from a detector electro de, pro cess the data and p erform monitoring tests. The SoC is built around on a custom 8-bit micropro cessor with internal mem- ory resources and emb eds the p eripherals to b e interf...

  11. Novel insight into the genomic architecture of feed and nitrogen efficiency measured by residual energy intake and nitrogen excretion in growing pigs

    Science.gov (United States)

    2013-01-01

    Background Improvement of feed efficiency in pigs is of great economical and environmental interest and contributes to use limited resources efficiently to feed the world population. Genome scans for feed efficiency traits are of importance to reveal the underlying biological causes and increase the rate of genetic gain. The aim of this study was to determine the genomic architecture of feed efficiency measured by residual energy intake (REI), in association with production, feed conversion ratio (FCR) and nitrogen excretion traits through the identification of quantitative trait loci (QTL) at different stages of growth using a three generation full-sib design population which originated from a cross between Pietrain and a commercial dam line. Results Six novel QTL for REI were detected explaining 2.7-6.1% of the phenotypic variance in REI. At growth from 60–90 kg body weight (BW), a QTL with a significant dominance effect was identified for REI on SSC14, at a similar location to the QTL for feed intake and nitrogen excretion traits. At growth from 90–120 kg BW, three QTL for REI were detected on SSC2, SSC4 and SSC7 with significant additive, imprinting and additive effects, respectively. These QTL (except for the imprinted QTL) were positionally overlapping with QTL for FCR and nitrogen excretion traits. During final growth (120–140 kg BW), a further QTL for REI was identified on SSC8 with significant additive effect, which overlapped with QTL for nitrogen excretion. During entire analysed growth (60–140 kg BW), a novel additive QTL for REI on SSC4 was observed, with no overlapping with QTL for any other traits considered. Conclusions The occurrence of only one overlapping QTL of REI with feed intake suggests that only a small proportion of the variance in REI was explained by change in feed intake, whereas four overlapping QTL of REI with those of nitrogen excretion traits suggests that mostly underlying factors of feed utilisation such as metabolism

  12. Novel insight into the genomic architecture of feed and nitrogen efficiency measured by residual energy intake and nitrogen excretion in growing pigs.

    Science.gov (United States)

    Shirali, Mahmoud; Duthie, Carol-Anne; Doeschl-Wilson, Andrea; Knap, Pieter W; Kanis, Egbert; van Arendonk, Johan A M; Roehe, Rainer

    2013-12-20

    Improvement of feed efficiency in pigs is of great economical and environmental interest and contributes to use limited resources efficiently to feed the world population. Genome scans for feed efficiency traits are of importance to reveal the underlying biological causes and increase the rate of genetic gain. The aim of this study was to determine the genomic architecture of feed efficiency measured by residual energy intake (REI), in association with production, feed conversion ratio (FCR) and nitrogen excretion traits through the identification of quantitative trait loci (QTL) at different stages of growth using a three generation full-sib design population which originated from a cross between Pietrain and a commercial dam line. Six novel QTL for REI were detected explaining 2.7-6.1% of the phenotypic variance in REI. At growth from 60-90 kg body weight (BW), a QTL with a significant dominance effect was identified for REI on SSC14, at a similar location to the QTL for feed intake and nitrogen excretion traits. At growth from 90-120 kg BW, three QTL for REI were detected on SSC2, SSC4 and SSC7 with significant additive, imprinting and additive effects, respectively. These QTL (except for the imprinted QTL) were positionally overlapping with QTL for FCR and nitrogen excretion traits. During final growth (120-140 kg BW), a further QTL for REI was identified on SSC8 with significant additive effect, which overlapped with QTL for nitrogen excretion. During entire analysed growth (60-140 kg BW), a novel additive QTL for REI on SSC4 was observed, with no overlapping with QTL for any other traits considered. The occurrence of only one overlapping QTL of REI with feed intake suggests that only a small proportion of the variance in REI was explained by change in feed intake, whereas four overlapping QTL of REI with those of nitrogen excretion traits suggests that mostly underlying factors of feed utilisation such as metabolism and protein turnover were the reason for

  13. Large-Scale Tunable 3D Self-Supporting WO3 Micro-Nano Architectures as Direct Photoanodes for Efficient Photoelectrochemical Water Splitting.

    Science.gov (United States)

    Cai, Mingyong; Fan, Peixun; Long, Jiangyou; Han, Jinpeng; Lin, Yi; Zhang, Hongjun; Zhong, Minlin

    2017-05-31

    Hydrogen production from water based on photoelectrochemical (PEC) reactions is feasible to solve the urgent energy crisis. Herein, hierarchical 3D self-supporting WO3 micro-nano architectures in situ grown on W plates are successfully fabricated via ultrafast laser processing hybrid with thermal oxidation. Owing to the large surface area and efficient interface charge transfer, the W plate with hierarchical porous WO3 nanoparticle aggregates has been directly employed as the photoanode for excellent PEC performance, which exhibits a high photocurrent density of 1.2 mA cm-2 at 1.0 V vs Ag/AgCl (1.23 V vs RHE) under AM 1.5 G illumination and reveals excellent structural stability during long-term PEC water splitting reactions. The nanoscale and microscale features can be facilely tuned by controlling the laser processing parameters and the thermal oxidation conditions to achieve improved PEC activity. The presented hybrid method is simple, cost-effective, and controllable for large-scale fabrication, which should provide a new and general route that how the properties of conventional metal oxides can be improved via hierarchical 3D micro-nano configurations.

  14. Efficient synthesis of C2v-symmetrical pentakisadducts of C60 as versatile building blocks for fullerene architectures that involve a mixed octahedral addition pattern.

    Science.gov (United States)

    Hörmann, Frank; Donaubauer, Wolfgang; Hampel, Frank; Hirsch, Andreas

    2012-03-12

    We report here on the selective synthesis of fullerene pentakisadducts 3 with an incomplete octahedral addition pattern by means of mixed [5:1]hexakisadducts 1 that involve an isoxazoline moiety as a protection group. The isoxazoline addend can be cleanly cleaved by irradiation with light. By using this protection-deprotection strategy, a variety of fullerene pentakisadducts 3 were synthesized in 29-44% overall yield without the need of HPLC purification. This novel photolytic deprotection of 1 can be explained by an initial electron transfer that leads to a biradical, which can easily eliminate the isoxazoline added. The very efficient and straightforward syntheses of the bisfullerene 4 and the globular hexakisadduct 7, each of which involves mixed octahedral addition patterns, clearly demonstrate the advantage of fullerene pentakisadducts 3 as suitable precursors for the construction of highly functional and complex [5:1]hexakisadduct architectures. Complete structural characterization of all new compounds was carried out by MALDI mass spectrometry, UV/Vis, FTIR, (1)H NMR and (13)C NMR spectroscopy, as well as X-ray diffraction. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  15. Specification and Design Methodologies for High-Speed Fault-Tolerant Array Algorithms and Structures for VLSI.

    Science.gov (United States)

    1987-06-01

    Verlag Lecture Notes 201, 1985. [She84] M. Sheeran , "muFP, a language for VLSI design", Proc. 1984 ACM Conference on LISP and Functional Programming...fMeshkinpour8S5 and Sheeran (Sheeran84] extended Backus’ Fl? language with operators to handle sequential circuits. 2 Brief Introduction to vFP vFP...Spring 1913, pp. 274-277. (201 Sheeran , M., "muFP, a Language for VLSI Design." Proc 1984 ACM Conference on LU and Functional Programming. August [4

  16. Microscale Adaptive Optics: Wave-Front Control with a mu-Mirror Array and a VLSI Stochastic Gradient Descent Controller.

    Science.gov (United States)

    Weyrauch, T; Vorontsov, M A; Bifano, T G; Hammer, J A; Cohen, M; Cauwenberghs, G

    2001-08-20

    The performance of adaptive systems that consist of microscale on-chip elements [microelectromechanical mirror (mu-mirror) arrays and a VLSI stochastic gradient descent microelectronic control system] is analyzed. The mu-mirror arrays with 5 x 5 and 6 x 6 actuators were driven with a control system composed of two mixed-mode VLSI chips implementing model-free beam-quality metric optimization by the stochastic parallel perturbative gradient descent technique. The adaptation rate achieved was near 6000 iterations/s. A secondary (learning) feedback loop was used to control system parameters during the adaptation process, further increasing the adaptation rate.

  17. VLSI implementation of a new LMS-based algorithm for noise removal in ECG signal

    Science.gov (United States)

    Satheeskumaran, S.; Sabrigiriraj, M.

    2016-06-01

    Least mean square (LMS)-based adaptive filters are widely deployed for removing artefacts in electrocardiogram (ECG) due to less number of computations. But they posses high mean square error (MSE) under noisy environment. The transform domain variable step-size LMS algorithm reduces the MSE at the cost of computational complexity. In this paper, a variable step-size delayed LMS adaptive filter is used to remove the artefacts from the ECG signal for improved feature extraction. The dedicated digital Signal processors provide fast processing, but they are not flexible. By using field programmable gate arrays, the pipelined architectures can be used to enhance the system performance. The pipelined architecture can enhance the operation efficiency of the adaptive filter and save the power consumption. This technique provides high signal-to-noise ratio and low MSE with reduced computational complexity; hence, it is a useful method for monitoring patients with heart-related problem.

  18. Robotic architectures

    CSIR Research Space (South Africa)

    Mtshali, M

    2010-01-01

    Full Text Available In the development of mobile robotic systems, a robotic architecture plays a crucial role in interconnecting all the sub-systems and controlling the system. The design of robotic architectures for mobile autonomous robots is a challenging...

  19. Integrating genome annotation and QTL position to identify candidate genes for productivity, architecture and water-use efficiency in Populus spp

    Directory of Open Access Journals (Sweden)

    Monclus Romain

    2012-09-01

    Full Text Available Abstract Background Hybrid poplars species are candidates for biomass production but breeding efforts are needed to combine productivity and water use efficiency in improved cultivars. The understanding of the genetic architecture of growth in poplar by a Quantitative Trait Loci (QTL approach can help us to elucidate the molecular basis of such integrative traits but identifying candidate genes underlying these QTLs remains difficult. Nevertheless, the increase of genomic information together with the accessibility to a reference genome sequence (Populus trichocarpa Nisqually-1 allow to bridge QTL information on genetic maps and physical location of candidate genes on the genome. The objective of the study is to identify QTLs controlling productivity, architecture and leaf traits in a P. deltoides x P. trichocarpa F1 progeny and to identify candidate genes underlying QTLs based on the anchoring of genetic maps on the genome and the gene ontology information linked to genome annotation. The strategy to explore genome annotation was to use Gene Ontology enrichment tools to test if some functional categories are statistically over-represented in QTL regions. Results Four leaf traits and 7 growth traits were measured on 330 F1 P. deltoides x P. trichocarpa progeny. A total of 77 QTLs controlling 11 traits were identified explaining from 1.8 to 17.2% of the variation of traits. For 58 QTLs, confidence intervals could be projected on the genome. An extended functional annotation was built based on data retrieved from the plant genome database Phytozome and from an inference of function using homology between Populus and the model plant Arabidopsis. Genes located within QTL confidence intervals were retrieved and enrichments in gene ontology (GO terms were determined using different methods. Significant enrichments were found for all traits. Particularly relevant biological processes GO terms were identified for QTLs controlling number of sylleptic

  20. Architectural Theatricality

    DEFF Research Database (Denmark)

    Tvedebrink, Tenna Doktor Olsen; Fisker, Anna Marie; Kirkegaard, Poul Henning

    2013-01-01

    and recovery through the architecture framing eating experiences, this article examines, from a theoretical perspective, two less debated concepts relating to hospitality called food design and architectural theatricality. In architectural theory the nineteenth century German architect Gottfried Semper...... is known for his writings on theatricality, understood as a holistic design approach emphasizing the contextual, cultural, ritual and social meanings rooted in architecture. Relative hereto, the International Food Design Society recently argued, in a similar holistic manner, that the methodology used...

  1. Architecture & Environment

    Science.gov (United States)

    Erickson, Mary; Delahunt, Michael

    2010-01-01

    Most art teachers would agree that architecture is an important form of visual art, but they do not always include it in their curriculums. In this article, the authors share core ideas from "Architecture and Environment," a teaching resource that they developed out of a long-term interest in teaching architecture and their fascination with the…

  2. An effective timing characterization method for an accuracy-proved VLSI standard cell library

    Science.gov (United States)

    Jianhua, Jiang; Man, Liang; Lei, Wang; Yumei, Zhou

    2014-02-01

    This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.

  3. Towards an automated system for the verification and diagnosis of intelligent VLSI circuits

    Science.gov (United States)

    Velazco, Raoul; Ziade, Haissam

    The main features of a system designed to cope with both the verification and diagnosis of Very Large Scale Integration (VLSI) intelligent circuits are detailed. The system is composed of a validation program generator, the GAPT (French Acronym for automatic generation of test programs) software and a microprocessor dedicated verification system, the TEMAC functional tester. GAPT/TEMAC tools allow an easy implementation of a top down diagnosis procedure. Each diagnosis action is composed of symptom analysis, malfunction hypothesis statement, sequence generation, execution, and result evaluation. It was successfully used in various microprocessor qualification/validation experiments. The system capabilities and the diagnosis procedure are illustrated by an actual 68000 microprocessor diagnosis experiment.

  4. High-performance fault-tolerant VLSI systems using micro rollback

    Science.gov (United States)

    Tamir, Yuval; Tremblay, Marc

    1990-01-01

    A technique called micro rollback, which allows most of the performance penalty for concurrent error detection to be eliminated, is presented. Detection is performed in parallel with the transmission of information between modules, thus removing the delay for detection from the critical path. Erroneous information may thus reach its destination module several clock cycles before an error indication. Operations performed on this erroneous information are undone using a hardware mechanism for fast rollback of a few cycles. The implementation of a VLSI processor capable of micro rollback is discussed, as well as several critical issues related to its use in a complete system.

  5. Evolutionary and Disruptive Approaches for Designing Next-Generation Ultra Energy-Efficient Electronics

    Science.gov (United States)

    Dadgour, Hamed F.

    With growing concerns over the energy crisis, the semiconductor industry is motivated to reduce its energy consumption by deploying emerging nanotechnologies. This research contributes to such attempts by (1) introducing novel methods to evaluate energy consumption of nanoscale circuits and systems, (2) improving the energy efficiency of micro-architectures by employing innovative circuit design methods and (3) investigating the implications of employing Nano-Electro-Mechanical Switches (NEMS) to reduce the power consumption of VLSI circuits. In the first part of the dissertation, we propose an accurate method for full-chip estimation of energy consumption in VLSI circuits considering the impact of parameter fluctuations. Furthermore, a novel variation-tolerant wide fan-in dynamic OR gate (a key component used in memory designs) will be introduced, which enables circuit designers to simultaneously improve the energy-efficiency as well as reliability. I will also introduce a new source of threshold voltage variation, which results in higher energy consumption in nano-scaled designs. The new source of process variation is unique to high-k/metal gate transistors and is caused by the dependency of work function of metal grains on their orientations. The implications of this source of random variations on the energy consumption, reliability and performance of SRAM cells will be investigate. In the second part of the dissertation, the implications of employing NEMS devices for improving the energy efficiency of circuits and systems will be discussed. NEMS transistors, while disruptive, are attractive devices because they offer unbeatable subthreshold characteristics (energy efficiency) compared to all other emerging solid-state transistors. In this dissertation, the implications of employing various NEMS devices on digital circuit design are explored. Particularly, a new class of NEMS devices called Laterally-Actuated Double-Gate NEMS transistor is introduced and

  6. An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

    DEFF Research Database (Denmark)

    Paaske, Erik; Pedersen, Steen; Sparsø, Jens

    1991-01-01

    area savings compared to the REA and the TBA are achieved. Furthermore, the relative area savings increase for larger decoding depths, which might be desirable for punctured codes.Based on the new algorithm a test chip has been designed and fabricated in a 2 micron CMOS process using MOSIS like...

  7. Project Integration Architecture: Application Architecture

    Science.gov (United States)

    Jones, William Henry

    2005-01-01

    The Project Integration Architecture (PIA) implements a flexible, object-oriented, wrapping architecture which encapsulates all of the information associated with engineering applications. The architecture allows the progress of a project to be tracked and documented in its entirety. Additionally, by bringing all of the information sources and sinks of a project into a single architectural space, the ability to transport information between those applications is enabled.

  8. Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA

    DEFF Research Database (Denmark)

    Saini, Rishita; Bansal, Neha; Bansal, Meenakshi

    2015-01-01

    Thermal aware design is currently gaining importance in VLSI research domain. In this work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA. Ambient Temperature, airflow, and heat sink profile play a significant role in thermal aware hardware design life cycle. Ambient...

  9. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    Science.gov (United States)

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  10. Peer-to-Peer Simulation Architecture

    CSIR Research Space (South Africa)

    Duvenhage, B

    2007-06-01

    Full Text Available Distributed parallel and soft real-time simulation architecture is presented. It employs a publish-subscribe communication framework layered on a peer-to-peer Transport Control Protocol-based message passing architecture. Mechanisms for efficient...

  11. DSP Architecture Design Essentials

    CERN Document Server

    Marković, Dejan

    2012-01-01

    In DSP Architecture Design Essentials, authors Dejan Marković and Robert W. Brodersen cover a key subject for the successful realization of DSP algorithms for communications, multimedia, and healthcare applications. The book addresses the need for DSP architecture design that maps advanced DSP algorithms to hardware in the most power- and area-efficient way. The key feature of this text is a design methodology based on a high-level design model that leads to hardware implementation with minimum power and area. The methodology includes algorithm-level considerations such as automated word-length reduction and intrinsic data properties that can be leveraged to reduce hardware complexity. From a high-level data-flow graph model, an architecture exploration methodology based on linear programming is used to create an array of architectural solutions tailored to the underlying hardware technology. The book is supplemented with online material: bibliography, design examples, CAD tutorials and custom software.

  12. Architectural Anthropology

    DEFF Research Database (Denmark)

    Stender, Marie

    , while recent material and spatial turns in anthropology have also brought an increasing interest in design, architecture and the built environment. Understanding the relationship between the social and the physical is at the heart of both disciplines, and they can obviously benefit from further...... collaboration: How can qualitative anthropological approaches contribute to contemporary architecture? And just as importantly: What can anthropologists learn from architects’ understanding of spatial and material surroundings? Recent theoretical developments in anthropology stress the role of materials...... and maybe also contribute to architectural design and the shaping of built environments? Through various empirical examples this paper explores the challenges and potentials of architectural anthropology....

  13. Catalyst Architecture

    DEFF Research Database (Denmark)

    Kiib, Hans; Marling, Gitte; Hansen, Peter Mandal

    2014-01-01

    How can architecture promote the enriching experiences of the tolerant, the democratic, and the learning city - a city worth living in, worth supporting and worth investing in? Catalyst Architecture comprises architectural projects, which, by virtue of their location, context and their combination...... of programs, have a role in mediating positive social and/or cultural development. In this sense, we talk about architecture as a catalyst for: sustainable adaptation of the city’s infrastructure appropriate renovation of dilapidated urban districts strengthening of social cohesiveness in the city development...

  14. Architectural Narratives

    DEFF Research Database (Denmark)

    Kiib, Hans

    2010-01-01

    a functional framework for these concepts, but tries increasingly to endow the main idea of the cultural project with a spatially aesthetic expression - a shift towards “experience architecture.” A great number of these projects typically recycle and reinterpret narratives related to historical buildings...... and architectural heritage; another group tries to embed new performative technologies in expressive architectural representation. Finally, this essay provides a theoretical framework for the analysis of the political rationales of these projects and for the architectural representation bridges the gap between...

  15. Fama Architecture: Implementation Details

    Science.gov (United States)

    Alcolea, A.; Martinez, A.; Laguna, P.; Navarro, J.; Pollan, T.; Vicente, S. J.; Roy, A.

    1987-10-01

    The FAMA (Fine granularity Advanced Multiprocessor Architecture), currently being developed in the Department of Electrical Engineering and Computer Science of the University of Zaragoza, is an SIMD array architecture optimized for computer-vision applications. Because of its high cost-effectiveness, it is a very interesting alternative for industrial systems. Papers describing the processor element of FAMA have been submitted to several conferences; this paper focuses on the rest of components that complete the architecture: controller, I/O interface and software. The controller generates instructions at a 10MHz rate, allowing efficient access to bidimensional data structures. The I/O interface is capable of reordering information for efficient I/O operations. Development tools and modules for classical computer-vision tasks are being worked on in a first stage, the implementation of models based on existing theories on human vision will follow.

  16. Architectural geometry

    NARCIS (Netherlands)

    Pottmann, Helmut; Eigensatz, Michael; Vaxman, A.; Wallner, Johannes

    2015-01-01

    Around 2005 it became apparent in the geometry processing community that freeform architecture contains many problems of a geometric nature to be solved, and many opportunities for optimization which however require geometric understanding. This area of research, which has been called architectural

  17. Architectural Contestation

    NARCIS (Netherlands)

    Merle, J.

    2012-01-01

    This dissertation addresses the reductive reading of Georges Bataille's work done within the field of architectural criticism and theory which tends to set aside the fundamental ‘broken’ totality of Bataille's oeuvre and also to narrowly interpret it as a mere critique of architectural form,

  18. Architecture Sustainability

    NARCIS (Netherlands)

    Avgeriou, Paris; Stal, Michael; Hilliard, Rich

    2013-01-01

    Software architecture is the foundation of software system development, encompassing a system's architects' and stakeholders' strategic decisions. A special issue of IEEE Software is intended to raise awareness of architecture sustainability issues and increase interest and work in the area. The

  19. Systemic Architecture

    DEFF Research Database (Denmark)

    Poletto, Marco; Pasquero, Claudia

    This is a manual investigating the subject of urban ecology and systemic development from the perspective of architectural design. It sets out to explore two main goals: to discuss the contemporary relevance of a systemic practice to architectural design, and to share a toolbox of informational...... design protocols developed to describe the city as a territory of self-organization. Collecting together nearly a decade of design experiments by the authors and their practice, ecoLogicStudio, the book discusses key disciplinary definitions such as ecologic urbanism, algorithmic architecture, bottom......-up or tactical design, behavioural space and the boundary of the natural and the artificial realms within the city and architecture. A new kind of "real-time world-city" is illustrated in the form of an operational design manual for the assemblage of proto-architectures, the incubation of proto...

  20. Architectural Anthropology

    DEFF Research Database (Denmark)

    Stender, Marie

    anthropology. On the one hand, there are obviously good reasons for developing architecture based on anthropological insights in local contexts and anthropologically inspired techniques for ‘collaborative formation of issues’. Houses and built environments are huge investments, their life expectancy......-anthropology. Within the field of architecture, however, there has not yet been quite the same eagerness to include anthropological approaches in design processes. This paper discusses why this is so and how and whether architectural anthropology has different conditions and objectives than other types of design...... and other spaces that architects are preoccupied with. On the other hand, the distinction between architecture and design is not merely one of scale. Design and architecture represent – at least in Denmark – also quite different disciplinary traditions and methods. Where designers develop prototypes...

  1. An MPSoC-Based QAM Modulation Architecture with Run-Time Load-Balancing

    Directory of Open Access Journals (Sweden)

    Doumenis Demosthenes

    2011-01-01

    Full Text Available QAM is a widely used multilevel modulation technique, with a variety of applications in data radio communication systems. Most existing implementations of QAM-based systems use high levels of modulation in order to meet the high data rate constraints of emerging applications. This work presents the architecture of a highly parallel QAM modulator, using MPSoC-based design flow and design methodology, which offers multirate modulation. The proposed MPSoC architecture is modular and provides dynamic reconfiguration of the QAM utilizing on-chip interconnection networks, offering high data rates (more than 1 Gbps, even at low modulation levels (16-QAM. Furthermore, the proposed QAM implementation integrates a hardware-based resource allocation algorithm that can provide better throughput and fault tolerance, depending on the on-chip interconnection network congestion and run-time faults. Preliminary results from this work have been published in the Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010. The current version of the work includes a detailed description of the proposed system architecture, extends the results significantly using more test cases, and investigates the impact of various design parameters. Furthermore, this work investigates the use of the hardware resource allocation algorithm as a graceful degradation mechanism, providing simulation results about the performance of the QAM in the presence of faulty components.

  2. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  3. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  4. An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

    Science.gov (United States)

    Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2014-01-01

    This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

  5. Project Integration Architecture: Architectural Overview

    Science.gov (United States)

    Jones, William Henry

    2001-01-01

    The Project Integration Architecture (PIA) implements a flexible, object-oriented, wrapping architecture which encapsulates all of the information associated with engineering applications. The architecture allows the progress of a project to be tracked and documented in its entirety. By being a single, self-revealing architecture, the ability to develop single tools, for example a single graphical user interface, to span all applications is enabled. Additionally, by bringing all of the information sources and sinks of a project into a single architectural space, the ability to transport information between those applications becomes possible, Object-encapsulation further allows information to become in a sense self-aware, knowing things such as its own dimensionality and providing functionality appropriate to its kind.

  6. Parallel Simulation of Chip-Multiprocessor Architectures

    National Research Council Canada - National Science Library

    Chidester, Matthew C; George, Alan D

    2002-01-01

    Chip-multiprocessor (CMP) architectures present a challenge for efficient simulation, combining the requirements of a detailed microprocessor simulator with that of a tightly-coupled parallel system...

  7. Architectural technology

    DEFF Research Database (Denmark)

    2005-01-01

    The booklet offers an overall introduction to the Institute of Architectural Technology and its projects and activities, and an invitation to the reader to contact the institute or the individual researcher for further information. The research, which takes place at the Institute of Architectural...... Technology at the Roayl Danish Academy of Fine Arts, School of Architecture, reflects a spread between strategic, goal-oriented pilot projects, commissioned by a ministry, a fund or a private company, and on the other hand projects which originate from strong personal interests and enthusiasm of individual...

  8. Humanizing Architecture

    DEFF Research Database (Denmark)

    Toft, Tanya Søndergaard

    2015-01-01

    The article proposes the urban digital gallery as an opportunity to explore the relationship between ‘human’ and ‘technology,’ through the programming of media architecture. It takes a curatorial perspective when proposing an ontological shift from considering media facades as visual spectacles...... agency and a sense of being by way of dematerializing architecture. This is achieved by way of programming the symbolic to provide new emotional realizations and situations of enlightenment in the public audience. This reflects a greater potential to humanize the digital in media architecture....

  9. Healing Architecture

    DEFF Research Database (Denmark)

    Folmer, Mette Blicher; Mullins, Michael; Frandsen, Anne Kathrine

    2012-01-01

    The project examines how architecture and design of space in the intensive unit promotes or hinders interaction between relatives and patients. The primary starting point is the relatives. Relatives’ support and interaction with their loved ones is important in order to promote the patients healing...... process. Therefore knowledge on how space can support interaction is fundamental for the architect, in order to make the best design solutions. Several scientific studies document that the hospital's architecture and design are important for human healing processes, including how the physical environment...... architectural and design solutions in order to improve quality of interaction between relative and patient in the hospital's intensive unit....

  10. Fabrication of TiO{sub 2} hierarchical architecture assembled by nanowires with anatase/TiO{sub 2}(B) phase-junctions for efficient photocatalytic hydrogen production

    Energy Technology Data Exchange (ETDEWEB)

    Qiu, Yong; Ouyang, Feng, E-mail: ouyangfh@hit.edu.cn

    2017-05-01

    Highlights: • H-titanate nanowires hierarchical architectures (TNH) were prepared by a hydrothermal method. • Calcinations of TNH leads to the formation of anatase/TiO{sub 2}(B) phase-junctions. • The hierarchical architecture offered enhanced light harvesting and large specific surface area. • The 1D nanowires and anatase/TiO{sub 2}(B) phase-junctions both can enhance the separation of photoinduced electron-hole. • The products calcined at the optimum conditions (450 °C) exhibited a maximum hydrogenproduction rate of 7808 μmol g{sup −1} h{sup −1}. - Abstract: TiO{sub 2} hierarchical architecture assembled by nanowires with anatase/TiO{sub 2}(B) phase-junctions was prepared by a hydrothermal process followed by calcinations. The optimum calcination treatment (450 °C) not only led to the formation of anatase/TiO{sub 2}(B) phase-junctions, but also kept the morphology of 1D nanowire and hierarchical architecture well. The T-450 load 0.5 wt% Pt cocatalysts showed the best photocatalytic hydrogen production activity, with a maximum hydrogen production rate of 7808 μmol g{sup −1} h{sup −1}. The high photocatalytic activity is ascribed to the combined effects of the following three factors: (1) the hierarchical architecture exhibits better light harvesting; (2) the larger specific surface area provides more surface active sites for the photocatalytic reaction; (3) the 1D nanowires and anatase/TiO{sub 2}(B) phase-junctions both can enhance the separation of photoinduced electron-hole pairs and inhibit their recombination.

  11. Ontology-based Software Architecture Documentation

    NARCIS (Netherlands)

    de Graaf, K.A.; Tang, A.; Liang, P.; van Vliet, J.C.

    2012-01-01

    A common approach to software architecture documentation in industry projects is the use of file-based documents. This approach offers a single-dimensional perspective on the architectural knowledge contained. Knowledge retrieval from file-based architecture documentation is efficient if the

  12. The Chameleon Architecture for Streaming DSP Applications

    NARCIS (Netherlands)

    Bergmann, N.; Smit, Gerardus Johannes Maria; Kokkeler, Andre B.J.; Platzner, M.; Wolkotte, P.T.; Teich, J.; Holzenspies, P.K.F.; van de Burgwal, M.D.; Heysters, P.M.

    2007-01-01

    We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a

  13. A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation

    Science.gov (United States)

    Zhang, Xiangyu; An, Fengwei; Nakashima, Ikki; Luo, Aiwen; Chen, Lei; Ishii, Idaku; Jürgen Mattausch, Hans

    2017-04-01

    A challenging and important issue for object recognition is feature extraction on embedded systems. We report a hardware implementation of the histogram of oriented gradients (HOG) algorithm for real-time object recognition, which is known to provide high efficiency and accuracy. The developed hardware-oriented algorithm exploits the cell-based scan strategy which enables image-sensor synchronization and extraction-speed acceleration. Furthermore, buffers for image frames or integral images are avoided. An image-size scalable hardware architecture with an effective bin-decoder and a parallelized voting element (PVE) is developed and used to verify the hardware-oriented HOG implementation with the application of human detection. The fabricated test chip in 180 nm CMOS technology achieves fast processing speed and large flexibility for different image resolutions with substantially reduced hardware cost and energy consumption.

  14. Architecture of Environmental Engineering

    DEFF Research Database (Denmark)

    Wenzel, Henrik; Alting, Leo

    2006-01-01

    comprise the disciplines of: management, system description & inventory, analysis & assessment, prioritisation, synthesis, and communication, each existing at all levels of intervention. The developed architecture of Environmental Engineering, thus, consists of thirty individual disciplines, within each......An architecture of Environmental Engineering has been developed comprising the various disciplines and tools involved. It identifies industry as the major actor and target group, and it builds on the concept of Eco-efficiency. To improve Eco-efficiency, there is a limited number of intervention...... points: the emission, the individual process/unit operation, the production system, the product/product system, and to some extent the whole societal system. At each level, environmental performance measured as Eco-efficiency can be addressed and changed by choice of solution. Because improvement of Eco...

  15. Architecture of Environmental Engineering

    DEFF Research Database (Denmark)

    Wenzel, Henrik; Alting, Leo

    2004-01-01

    Engineering, thus, in essence comprise the disciplines of: management, system description & inventory, analysis & assessment, prioritisation, synthesis, and communication, each existing at all levels of intervention. The developed architecture of Environmental Engineering, thus, consists of thirty individual......An architecture of Environmental Engineering has been developed comprising the various disciplines and tools involved. It identifies industry as the major actor and target group, and it builds on the concept of Eco-efficiency. To improve Eco-efficiency, there is a limited number of intervention...... points: the emission, the individual process or unit operation, the production system, the product or product system, and to some extent the whole societal system. At each level, environmental performance measured as Eco-efficiency can be addressed and changed by choice of solution. Because improvement...

  16. Architectural Mealscapes

    DEFF Research Database (Denmark)

    Tvedebrink, Tenna Doktor Olsen; Fisker, Anna Marie; Kirkegaard, Poul Henning

    2012-01-01

    the German architect Gottfried Semper developed a theory on the “four elements of Architecture” tracing the origin of architecture back to the rise of the early human settlement and the creation of fire. With the notion ‘hearth’ as the first motive in architecture and the definition of three enclosing...... motives; mounding, enclosure and roof, Semper linked the cultural and social values of the primordial fireplace with the order and shape of architecture. He claimed that any building ever made was nothing but a variation of the first primitive shelters erected around the fireplace, and that the three...... enclosing motives existed only as defenders of the “sacred flame”. In that way Semper developed the idea that any architectural scenery can be described, analyzed and explained by understanding the contextual, symbolic and social values of how the four basic motives of hearth, mounding, enclosure, and roof...

  17. Architectured Nanomembranes

    Energy Technology Data Exchange (ETDEWEB)

    Sturgeon, Matthew R. [Former ORNL postdoc; Hu, Michael Z. [ORNL

    2017-07-01

    This paper has reviewed the frontier field of “architectured membranes” that contains anisotropic oriented porous nanostructures of inorganic materials. Three example types of architectured membranes were discussed with some relevant results from our own research: (1) anodized thin-layer titania membranes on porous anodized aluminum oxide (AAO) substrates of different pore sizes, (2) porous glass membranes on alumina substrate, and (3) guest-host membranes based on infiltration of yttrium-stabilized zirconia inside the pore channels of AAO matrices.

  18. Textile Architecture

    OpenAIRE

    Maurin, Bernard; Motro, René

    2013-01-01

    The basic idea for a textile architecture project originates during early meetings between the architect and the engineer. The morphologic richness of such projects is provided by the varying curvatures of shapes, in contradiction with a classical straight line and orthogonal architecture. However the rules of construction are quite different in terms of realisation and of mechanical behaviour: textile membranes are subjected to a pre-stress conferring them their rigidity, and a major objecti...

  19. VLSI Research

    Science.gov (United States)

    1983-10-31

    Caesar and Mextra and other old programs, as well as several previously-unreleased pro- grams, such as Lyra. Crystal. Peg, and Tpack . The 1983...release was sent to eight beta test sites in January, and began general distribution on April 1. EL1. Tpack : A System for Combining Graphics and Procedures

  20. VLSI Research

    Science.gov (United States)

    1984-04-01

    23,1984 / CONTINENTAL BALLROOMS 6-9 / 9:00 A.M. *T-ś! J SESSION XII: MICROPROCESSORS ANO MICROCONTROLLERS THAM 12.1: A 32b NMOS Microprocessor...roisideration, AlC is insensitive to the interface-wrapt..2 charge. The difference between AVr and Al£, therefore, will be the con- tribution from the...reduction of AVr . Since the degree of impact ionization increases with the substrate bias, the end result is the observed decrease in AVj- with

  1. Novel insight into the genomic architecture of feed and nitrogen efficiency measured by residual energy intake and nitrogen excretion in growing pigs

    NARCIS (Netherlands)

    Shirali, M.; Duthie, C.A.; Doeschl-Wilson, A.; Knap, P.W.; Kanis, E.; Arendonk, van J.A.M.; Roehe, R.

    2013-01-01

    Background Improvement of feed efficiency in pigs is of great economical and environmental interest and contributes to use limited resources efficiently to feed the world population. Genome scans for feed efficiency traits are of importance to reveal the underlying biological causes and increase the

  2. Energy efficiency and bioclimatic architecture - the case of the Center of Energy and Sustainable Technologies; Eficiencia energetica e arquitetura bioclimatica - o caso do Centro de Energia e Tecnologias Sustentaveis

    Energy Technology Data Exchange (ETDEWEB)

    Stilpen, Daniel Vasconcellos de Sousa

    2007-07-15

    This thesis analyzes the energy efficiency of a single-family dwelling, constructed in Ilha do Fundao, Rio de Janeiro. It first describes the Center of Energy and Sustainable Technologies and also evaluates the thermal behavior of the non-conventional materials used in its construction. After that, a thermal comfort experiment, in accordance with the thermal comfort theory proposed by Fanger, is presented. Then, the experimental data analysis, from more than 300 (three hundred) interviews, is shown. Finally, some bioclimatic suggestions for modifications in the architecture project of the dwelling are presented. All solutions represent significant increases in the human thermal comfort responses, with low implementation cost.

  3. Architecture of a complex arithmetic processor for communication signal processing

    Science.gov (United States)

    Gilfeather, Susan L.; Gehman, John B., Jr.; Harrison, Calvin

    1994-10-01

    The Complex Arithmetic Processor (CAP) is a high performance, single chip Digital Signal Processor optimized for communication signal processing operations. The CAP VLSI provides the communication system building block necessary to meet the increased signal processing requirements of complex modulation types, voice and image compression while maintaining the requirement for small, low power implementations. The chip is intended for high speed, low power digital communication system applications such as hand held spread spectrum communications systems. The CAP architecture has been developed specifically for the complex arithmetic functions required in communication signal processing. The CAP is a software programmable, highly integrated parallel array of processors containing the arithmetic resources, memories, address generation, bit manipulation and logic functions necessary to support the sophisticated processing required in advanced communication equipment. The CAP executes a 1024 point complex Fast Fourier Transform in 131 microseconds.

  4. The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

    Science.gov (United States)

    Xu, Peng; Pan, Zhongliang

    2017-09-01

    With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits. To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed. First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes. The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model. Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique and ABCD parameter matrix approach at local level, intermediate level and global level, respectively. Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits. It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system. Project supported by the Guangdong Provincial Natural Science Foundation of China (No. 2014A030313441), the Guangzhou Science and Technology Project (No. 201510010169), the Guangdong Province Science and Technology Project (No. 2016B090918071), and the National Natural Science Foundation of China (No. 61072028).

  5. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  6. Enterprise architecture evaluation using architecture framework and UML stereotypes

    Directory of Open Access Journals (Sweden)

    Narges Shahi

    2014-08-01

    Full Text Available There is an increasing need for enterprise architecture in numerous organizations with complicated systems with various processes. Support for information technology, organizational units whose elements maintain complex relationships increases. Enterprise architecture is so effective that its non-use in organizations is regarded as their institutional inability in efficient information technology management. The enterprise architecture process generally consists of three phases including strategic programing of information technology, enterprise architecture programing and enterprise architecture implementation. Each phase must be implemented sequentially and one single flaw in each phase may result in a flaw in the whole architecture and, consequently, in extra costs and time. If a model is mapped for the issue and then it is evaluated before enterprise architecture implementation in the second phase, the possible flaws in implementation process are prevented. In this study, the processes of enterprise architecture are illustrated through UML diagrams, and the architecture is evaluated in programming phase through transforming the UML diagrams to Petri nets. The results indicate that the high costs of the implementation phase will be reduced.

  7. PICNIC Architecture.

    Science.gov (United States)

    Saranummi, Niilo

    2005-01-01

    The PICNIC architecture aims at supporting inter-enterprise integration and the facilitation of collaboration between healthcare organisations. The concept of a Regional Health Economy (RHE) is introduced to illustrate the varying nature of inter-enterprise collaboration between healthcare organisations collaborating in providing health services to citizens and patients in a regional setting. The PICNIC architecture comprises a number of PICNIC IT Services, the interfaces between them and presents a way to assemble these into a functioning Regional Health Care Network meeting the needs and concerns of its stakeholders. The PICNIC architecture is presented through a number of views relevant to different stakeholder groups. The stakeholders of the first view are national and regional health authorities and policy makers. The view describes how the architecture enables the implementation of national and regional health policies, strategies and organisational structures. The stakeholders of the second view, the service viewpoint, are the care providers, health professionals, patients and citizens. The view describes how the architecture supports and enables regional care delivery and process management including continuity of care (shared care) and citizen-centred health services. The stakeholders of the third view, the engineering view, are those that design, build and implement the RHCN. The view comprises four sub views: software engineering, IT services engineering, security and data. The proposed architecture is founded into the main stream of how distributed computing environments are evolving. The architecture is realised using the web services approach. A number of well established technology platforms and generic standards exist that can be used to implement the software components. The software components that are specified in PICNIC are implemented in Open Source.

  8. Architectural geometry

    KAUST Repository

    Pottmann, Helmut

    2014-11-26

    Around 2005 it became apparent in the geometry processing community that freeform architecture contains many problems of a geometric nature to be solved, and many opportunities for optimization which however require geometric understanding. This area of research, which has been called architectural geometry, meanwhile contains a great wealth of individual contributions which are relevant in various fields. For mathematicians, the relation to discrete differential geometry is significant, in particular the integrable system viewpoint. Besides, new application contexts have become available for quite some old-established concepts. Regarding graphics and geometry processing, architectural geometry yields interesting new questions but also new objects, e.g. replacing meshes by other combinatorial arrangements. Numerical optimization plays a major role but in itself would be powerless without geometric understanding. Summing up, architectural geometry has become a rewarding field of study. We here survey the main directions which have been pursued, we show real projects where geometric considerations have played a role, and we outline open problems which we think are significant for the future development of both theory and practice of architectural geometry.

  9. Architectural Theatricality

    DEFF Research Database (Denmark)

    Tvedebrink, Tenna Doktor Olsen

    This PhD thesis is motived by a personal interest in the theoretical, practical and creative qualities of architecture. But also a wonder and curiosity about the cultural and social relations architecture represents through its occupation with both the sciences and the arts. Inspired by present...... and well-being, as well as outline a set of basic design principles ‘predicting’ the future interior architectural qualities of patient eating environments. Methodologically the thesis is based on an explorative study employing an abductive approach and hermeneutic-interpretative strategy utilizing tactics...... such as a literature review, timeline and historical outline to create a “knowledge map”, which in an eclectic manner merges the positive, normative and polemical knowledge rooted in research, objects and writings. The results of these investigations show that sparse researchbased knowledge exist directly taking...

  10. Architectural Engineers

    DEFF Research Database (Denmark)

    Petersen, Rikke Premer

    engineering is addresses from two perspectives – as an educational response and an occupational constellation. Architecture and engineering are two of the traditional design professions and they frequently meet in the occupational setting, but at educational institutions they remain largely estranged....... The paper builds on a multi-sited study of an architectural engineering program at the Technical University of Denmark and an architectural engineering team within an international engineering consultancy based on Denmark. They are both responding to new tendencies within the building industry where...... the role of engineers and architects increasingly overlap during the design process, but their approaches reflect different perceptions of the consequences. The paper discusses some of the challenges that design education, not only within engineering, is facing today: young designers must be equipped...

  11. Active Sites Intercalated Ultrathin Carbon Sheath on Nanowire Arrays as Integrated Core-Shell Architecture: Highly Efficient and Durable Electrocatalysts for Overall Water Splitting.

    Science.gov (United States)

    Hou, Jungang; Wu, Yunzhen; Cao, Shuyan; Sun, Yiqing; Sun, Licheng

    2017-12-01

    The development of active bifunctional electrocatalysts with low cost and earth-abundance toward oxygen evolution reaction (OER) and hydrogen evolution reaction (HER) remains a great challenge for overall water splitting. Herein, metallic Ni 4 Mo nanoalloys are firstly implanted on the surface of NiMoO x nanowires array (NiMo/NiMoO x ) as metal/metal oxides hybrid. Inspired by the superiority of carbon conductivity, an ultrathin nitrogen-doped carbon sheath intercalated NiMo/NiMoO x (NC/NiMo/NiMoO x ) nanowires as integrated core-shell architecture are constructed. The integrated NC/NiMo/NiMoO x array exhibits an overpotential of 29 mV at 10 mA cm -2 and a low Tafel slope of 46 mV dec -1 for HER due to the abundant active sites, fast electron transport, low charge-transfer resistance, unique architectural structure and synergistic effect of carbon sheath, nanoalloys, and oxides. Moreover, as OER catalysts, the NC/NiMo/NiMoO x hybrids require an overpotential of 284 mV at 10 mA cm -2 . More importantly, the NC/NiMo/NiMoO x array as a highly active and stable electrocatalyst approaches ≈10 mA cm -2 at a voltage of 1.57 V, opening an avenue to the rational design and fabrication of the promising electrode materials with architecture structures toward the electrochemical energy storage and conversion. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  12. Reframing Architecture

    DEFF Research Database (Denmark)

    Riis, Søren

    2013-01-01

    I would like to thank Prof. Stephen Read (2011) and Prof. Andrew Benjamin (2011) for both giving inspiring and elaborate comments on my article “Dwelling in-between walls: the architectural surround”. As I will try to demonstrate below, their two different responses not only supplement my article...... focuses on how the absence of an initial distinction might threaten the endeavour of my paper. In my reply to Read and Benjamin, I will discuss their suggestions and arguments, while at the same time hopefully clarifying the postphenomenological approach to architecture....

  13. Multithreading architecture

    CERN Document Server

    Nemirovsky, Mario

    2013-01-01

    Multithreaded architectures now appear across the entire range of computing devices, from the highest-performing general purpose devices to low-end embedded processors. Multithreading enables a processor core to more effectively utilize its computational resources, as a stall in one thread need not cause execution resources to be idle. This enables the computer architect to maximize performance within area constraints, power constraints, or energy constraints. However, the architectural options for the processor designer or architect looking to implement multithreading are quite extensive and

  14. Three-dimensional design methodologies for tree-based FPGA architecture

    CERN Document Server

    Pangracious, Vinod; Mehrez, Habib

    2015-01-01

    This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

  15. From green architecture to architectural green

    DEFF Research Database (Denmark)

    Earon, Ofri

    2011-01-01

    that describes the architectural exclusivity of this particular architecture genre. The adjective green expresses architectural qualities differentiating green architecture from none-green architecture. Currently, adding trees and vegetation to the building’s facade is the main architectural characteristics......The paper investigates the topic of green architecture from an architectural point of view and not an energy point of view. The purpose of the paper is to establish a debate about the architectural language and spatial characteristics of green architecture. In this light, green becomes an adjective...... of green architecture. The paper argues that this greenification of facades is insufficient. The green is only a skin cladding the exterior envelope without having a spatial significance. Through the paper it is proposed to flip the order of words from green architecture to architectural green...

  16. Textile Architecture

    DEFF Research Database (Denmark)

    Heimdal, Elisabeth Jacobsen

    2010-01-01

    Textiles can be used as building skins, adding new aesthetic and functional qualities to architecture. Just like we as humans can put on a coat, buildings can also get dressed. Depending on our mood, or on the weather, we can change coat, and so can the building. But the idea of using textiles...

  17. Software Architecture

    NARCIS (Netherlands)

    Tekinerdogan, B.; Zdun, Uwe; Babar, Ali

    2016-01-01

    This book constitutes the proceedings of the 10th European Conference on Software Architecture, ECSA 2016, held in Copenhagen, Denmark, in November/December 2016.

    The 13 full papers presented together with 12 short papers were carefully reviewed and selected from 84 submissions. They are

  18. Design and implementation of efficient low complexity biomedical artifact canceller for nano devices

    Directory of Open Access Journals (Sweden)

    Md Zia Ur RAHMAN

    2016-07-01

    Full Text Available In the current day scenario, with the rapid development of communication technology remote health care monitoring becomes as an intense research area. In remote health care monitoring, the primary aim is to facilitate the doctor with high resolution biomedical data. In order to cancel various artifacts in clinical environment in this paper we propose some efficient adaptive noise cancellation techniques. To obtain low computational complexity we combine clipping the data or error with Least Mean Square (LMS algorithm. This results sign regressor LMS (SRLMS, sign LMS (SLMS and sign LMS (SSLMS algorithms. Using these algorithms, we design Very-large-scale integration (VLSI architectures of various Biomedical Noise Cancellers (BNCs. In addition, the filtering capabilities of the proposed implementations are measured using real biomedical signals. Among the various BNCs tested, SRLMS based BNC is found to be better with reference to convergence speed, filtering capability and computational complexity. The main advantage of this technique is it needs only one multiplication to compute next weight. In this manner SRLMS based BNC is independent of filter length with reference to its computations. Whereas, the average signal to noise ratio achieved in the noise cancellation experiments are recorded as 7.1059dBs, 7.1776dBs, 6.2795dBs and 5.8847dBs for various BNCs based on LMS, SRLMS, SLMS and SSSLMS algorithms respectively. Based on the filtering characteristics, convergence and computational complexity, the proposed SRLMS based BNC architecture is well suited for nanotechnology applications.

  19. Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

    Directory of Open Access Journals (Sweden)

    Massimiliano eGiulioni

    2012-02-01

    Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  20. A novel VLSI processor for high-rate, high resolution spectroscopy

    CERN Document Server

    Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

    2000-01-01

    A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

  1. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  2. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  3. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  4. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    Science.gov (United States)

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces. Copyright © 2014 Elsevier B.V. All rights reserved.

  5. Verification of electricity savings through energy-efficient train management - Concept and system architecture - Annex 1; Verifizierung der Stromeinsparung durch energieeffizientes Zugsmanagement - Anhang 1: Konzept und Systemarchitektur

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, M.; Lerjen, M.; Menth, S. [emkamatik GmbH, Wettingen (Switzerland); Luethi, M. [Swiss Federal Insitute of Technology (ETHZ), Institute for Transport Planning and Systems (IVT), Zuerich (Switzerland); Tuchschmid, M. [SBB AG, BahnUmwelt-Center, 3000 Bern (Switzerland)

    2009-11-15

    This appendix to a final report for the Swiss Federal Office of Energy (SFOE) discusses a system concept that can be used to help save energy in the Swiss rail network. The concept proposes that the highest level of energy savings can be achieved by controlling the trains to provide a high level of smooth flow as far as speed is concerned. In particular, various situations are described where, for example, double and single track working exists and unnecessary breaking when trains have to pass each other can be avoided. Predictor algorithms are described and discussed and possible indicators for train drivers are proposed. The system architecture required is examined and recommendations are made concerning the implementation of the system. Restrictions caused by the running of non-equipped foreign trains on the Swiss rail network are also discussed.

  6. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  7. MUF architecture /art London

    DEFF Research Database (Denmark)

    Svenningsen Kajita, Heidi

    2009-01-01

    Om MUF architecture samt interview med Liza Fior og Katherine Clarke, partnere i muf architecture/art......Om MUF architecture samt interview med Liza Fior og Katherine Clarke, partnere i muf architecture/art...

  8. Architectural fragments

    DEFF Research Database (Denmark)

    Bang, Jacob Sebastian

    2018-01-01

    . I try to invent the ways of drawing the models - that decode and unfold them into architectural fragments- into future buildings or constructions in the landscape. [1] Luigi Moretti: Italian architect, 1907 - 1973 [2] Man Ray: American artist, 1890 - 1976. in 2015, I saw the wonderful exhibition......I have created a large collection of plaster models: a collection of Obstructions, errors and opportunities that may develop into architecture. The models are fragments of different complex shapes as well as more simple circular models with different profiling and diameters. In this contect I have...... been studying Luigi Moretti's [1] plastermodel - "the Model of the inner spaces of the Saint Maria of the Divine Providence" - in which context I see my own models. In 1934, Man Ray [2] photographed mathematical rmodels (in plaster) at the Henri Poincaré Institute in Paris and later used...

  9. A Benefit Analysis of Infusing Wireless into Aircraft and Fleet Operations - Report to Seedling Project Efficient Reconfigurable Cockpit Design and Fleet Operations Using Software Intensive, Network Enabled, Wireless Architecture (ECON)

    Science.gov (United States)

    Alexandrov, Natalia; Holmes, Bruce J.; Hahn, Andrew S.

    2016-01-01

    We report on an examination of potential benefits of infusing wireless technologies into various areas of aircraft and airspace operations. The analysis is done in support of a NASA seedling project Efficient Reconfigurable Cockpit Design and Fleet Operations Using Software Intensive, Network Enabled Wireless Architecture (ECON). The study has two objectives. First, we investigate one of the main benefit hypotheses of the ECON proposal: that the replacement of wired technologies with wireless would lead to significant weight reductions on an aircraft, among other benefits. Second, we advance a list of wireless technology applications and discuss their system benefits. With regard to the primary hypothesis, we conclude that the promise of weight reduction is premature. Specificity of the system domain and aircraft, criticality of components, reliability of wireless technologies, the weight of replacement or augmentation equipment, and the cost of infusion must all be taken into account among other considerations, to produce a reliable estimate of weight savings or increase.

  10. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  11. Introduction to parallel algorithms and architectures arrays, trees, hypercubes

    CERN Document Server

    Leighton, F Thomson

    1991-01-01

    Introduction to Parallel Algorithms and Architectures: Arrays Trees Hypercubes provides an introduction to the expanding field of parallel algorithms and architectures. This book focuses on parallel computation involving the most popular network architectures, namely, arrays, trees, hypercubes, and some closely related networks.Organized into three chapters, this book begins with an overview of the simplest architectures of arrays and trees. This text then presents the structures and relationships between the dominant network architectures, as well as the most efficient parallel algorithms for

  12. Interleaved Convolutional Code and Its Viterbi Decoder Architecture

    National Research Council Canada - National Science Library

    Kong, Jun Jin; Parhi, Keshab K

    2003-01-01

    We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code...

  13. High efficiency 2 micrometer laser utilizing wing-pumped Tm{sup 3+} and a laser diode array end-pumping architecture

    Science.gov (United States)

    Beach, R.J.

    1997-11-18

    Wing pumping a Tm{sup 3+} doped, end pumped solid state laser generates 2 {micro}m laser radiation at high average powers with high efficiency. Using laser diode arrays to end-pump the laser rod or slab in the wing of the Tm{sup 3+} absorption band near 785 nm results in 2-for-1 quantum efficiency in Tm{sup 3+} because high Tm{sup 3+} concentrations can be used. Wing pumping allows the thermal power generated in the rod or slab to be distributed over a large enough volume to make thermal management practical in the laser gain medium even at high average power operation. The approach is applicable to CW, Q-switched, and rep-pulsed free-laser operation. 7 figs.

  14. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  15. Architectural Drawing

    DEFF Research Database (Denmark)

    Steinø, Nicolai

    2018-01-01

    is that computers can represent graphic ideas both faster and better than most medium-skilled draftsmen, drawing in design is not only about representing final designs. In fact, several steps involving the capacity to draw lie before the representation of a final design. Not only is drawing skills an important...... it is developed from empirical and partly introspective observations of the design process – from analysis over design development to the presentation of final designs – it seeks to corroborate these observations through literature on architectural drawing....

  16. Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers

    OpenAIRE

    Misra, Supratik Kumar

    2012-01-01

    Continuous advances in VLSI technology have led to more complex digital designs and shrinking transistor sizes. Due to these developments, design verification and manufacturing test have gained more importance and 70 % of the design expenditure in on validation processes. Electronic Design Automation (EDA) tools play a huge role in the validation process with various verification and test tools. Their efficiency have a high impact in saving time and money in this competitive market. Direct Ac...

  17. HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

    DEFF Research Database (Denmark)

    Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

    2015-01-01

    standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

  18. Preindustrial versus postindustrial Architecture and Building Techniques

    DEFF Research Database (Denmark)

    Vestergaard, Inge

    2014-01-01

    How can preindustrial architecture inspire sustainable thinking in postindustrial architectural design? How can we learn from experience and how can social, economic and environmental conditions give perspectives and guide a knowledge based evolution of basic experience towards modern...... fisherman’s house built around year 1700; and second a frontrunner suburban family house built year 2008. The analysis involves architectural, technical and comfort matters and will state the levels of design, social conditions, sustainable and energy efficient parameters. Results will show lessons learned...

  19. The urban lighting in the rehabilitation of the minor historical centre. The design scenarios for the architectural valorisation and the energy efficiency improvement of the urban environment

    Directory of Open Access Journals (Sweden)

    Pierluigi De Berardinis

    2015-12-01

    as to value the architectural and environmental heritage giving importance to energy and economic saving.

  20. Analog very large-scale integrated (VLSI) implementation of a model of amplitude-modulation sensitivity in the auditory brainstem.

    Science.gov (United States)

    van Schaik, A; Meddis, R

    1999-02-01

    An analog very large-scale integrated (VLSI) implementation of a model of signal processing in the auditory brainstem is presented and evaluated. The implementation is based on a model of amplitude-modulation sensitivity in the central nucleus of the inferior colliculus (CNIC) previously described by Hewitt and Meddis [J. Acoust. Soc. Am. 95, 2145-2159 (1994)]. A single chip is used to implement the three processing stages of the model; the inner-hair cell (IHC), cochlear nucleus sustained-chopper, and CNIC coincidence-detection stages. The chip incorporates two new circuits: an IHC circuit and a neuron circuit. The input to the chip is taken from a "silicon cochlea" consisting of a cascade of filters that simulate basilar membrane mechanical frequency selectivity. The chip which contains 142 neurons was evaluated using amplitude-modulated pure tones. Individual cells in the CNIC stage demonstrate bandpass rate-modulation responses using these stimuli. The frequency of modulation is represented spatially in an array of these cells as the location of the cell generating the highest rate of action potentials. The chip processes acoustic signals in real time and demonstrates the feasibility of using analog VLSI to build and test auditory models that use large numbers of component neurons.

  1. 1993 architectural design awards.

    Science.gov (United States)

    1993-06-01

    The 10th annual architectural design awards sponsored by Contemporary Long Term Care salute nursing homes and retirement communities that combine a flair for innovative living environments with a sensitivity to the needs of aging residents. These facilities represent the very best in elderly housing that prolongs independence while enhancing efficient operation. The 1993 winners are: King Health Center, U.S. Soldiers' and Airmen's Home, Washington, DC; The Terrace of Los Gatos, Los Gatos, CA; Walker Elder Suites, Edina, MN; The Jefferson, Ballston, VA; The Forum at Rancho San Antonio, Cupertino, CA.

  2. Efficient rejection of scattered light enables deep optical sectioning in turbid media with low-numerical-aperture optics in a dual-axis confocal architecture.

    Science.gov (United States)

    Liu, Jonathan T C; Mandella, Michael J; Crawford, James M; Contag, Christopher H; Wang, Thomas D; Kino, Gordon S

    2008-01-01

    Miniature endoscopic microscopes, with subcellular imaging capabilities, will enable in vivo detection of molecularly-targeted fluorescent probes for early disease detection. To optimize a dual-axis confocal microscope (DACM) design for this purpose, we use a tabletop instrument to determine the ability of this technology to perform optical sectioning deep within tissue. First, we determine how tissue scattering deteriorates the diffraction-limited transverse and vertical responses in reflectance imaging. Specifically, the vertical response of a DACM to a plane reflector is measured at various depths in a scattering phantom and compared with diffraction theory and Monte Carlo scattering simulations. Similarly, transverse line scans across a knife-edge target are performed at various depths in a scattering phantom. Second, as a practical demonstration of deep-tissue fluorescence microscopy that corroborates the findings from our scattering experiments, 3-D fluorescence images are obtained in thick human gastrointestinal mucosal specimens. Our results demonstrate efficient rejection of scattered light in a DACM, which enables deep optical sectioning in tissue with subcellular resolution that can distinguish between normal and premalignant pathologies.

  3. 3D architecture constructed via the confined growth of MoS2 nanosheets in nanoporous carbon derived from metal-organic frameworks for efficient hydrogen production.

    Science.gov (United States)

    Liu, Yun; Zhou, Xiaoli; Ding, Tao; Wang, Chunde; Yang, Qing

    2015-11-21

    The design and synthesis of robust, high-performance and low-cost three-dimensional (3D) hierarchical structured materials for the electrochemical reduction of water to generate hydrogen is of great significance for practical water splitting applications. In this study, we develop an in situ space-confined method to synthesize an MoS2-based 3D hierarchical structure, in which the MoS2 nanosheets grow in the confined nanopores of metal-organic frameworks (MOFs)-derived 3D carbons as electrocatalysts for efficient hydrogen production. Benefiting from its unique structure, which has more exposed active sites and enhanced conductivity, the as-prepared MoS2/3D nanoporous carbon (3D-NPC) composite exhibits remarkable electrocatalytic activity for the hydrogen evolution reaction (HER) with a small onset overpotential of ∼0.16 V, large cathodic currents, small Tafel slope of 51 mV per decade and good durability. We anticipate that this in situ confined growth provides new insights into the construction of high performance catalysts for energy storage and conversion.

  4. Software Architecture Simulation

    OpenAIRE

    Mårtensson, Frans; Jönsson, Per

    2002-01-01

    A software architecture is one of the first steps towards a software system. A software architecture can be designed in different ways. During the design phase, it is important to select the most suitable design of the architecture, in order to create a good foundation for the system. The selection process is performed by evaluating architecture alternatives against each other. We investigate the use of continuous simulation of a software architecture as a support tool for architecture evalua...

  5. SUSTAINABLE ARCHITECTURE : WHAT ARCHITECTURE STUDENTS THINK

    OpenAIRE

    Satwiko, Prasasto

    2013-01-01

    Sustainable architecture has become a hot issue lately as the impacts of climate change become more intense. Architecture educations have responded by integrating knowledge of sustainable design in their curriculum. However, in the real life, new buildings keep coming with designs that completely ignore sustainable principles. This paper discusses the results of two national competitions on sustainable architecture targeted for architecture students (conducted in 2012 and 2013). The results a...

  6. Mechanical Stimulation Modifies Canopy Architecture and Improves Volume Utilization Efficiency in Bell Pepper: Implications for Bioregenerative Life-support and Vertical Farming

    Directory of Open Access Journals (Sweden)

    Graham Thomas

    2017-02-01

    Full Text Available Mechanical stimuli or stress has been shown to induce characteristic morphogenic responses (thigmomorphogenesis in a range of crop species. The typical mechanically stimulated phenotype is shorter and more compact than non-mechanically stimulated plants. This dwarfing effect can be employed to help conform crop plants to the constraints of spaceflight and vertical agriculture crop production systems. Capsicum annum (cv. California Wonder plants were grown in controlled environment chambers and subjected to mechanical stimulation in the form of firm but gentle daily rubbing of internode tissue with a tightly wrapped cotton swab. Two studies were conducted, the first being a vegetative growth phase study in which plants were mechanically stimulated until anthesis. The second study carried the mechanical stimulation through to fruit set. The response during the vegetative growth experiment was consistent with other results in the literature, with a general reduction in all plant growth metrics and an increase in relative chlorophyll (SPAD content under mechanical stimulation. In the fruiting phase study, only height and stem thickness differed from the control plants. Using the data from the fruiting study, a rudimentary calculation of volume use efficiency (VUE improvements was conducted. Results suggest that VUE can be improved, particularly in terrestrial vertical agriculture systems that can take advantage of moderate height reductions by exploiting much greater vertical capacity in the production system. Mechanical stimulation can also improve VUE in spaceflight applications by reducing vertical system requirements or by expanding the species range that can be grown in a fixed production volume. Mechanical stimulation is also discussed as a microgravity countermeasure for crop plants.

  7. Lightweight enterprise architectures

    CERN Document Server

    Theuerkorn, Fenix

    2004-01-01

    STATE OF ARCHITECTUREArchitectural ChaosRelation of Technology and Architecture The Many Faces of Architecture The Scope of Enterprise Architecture The Need for Enterprise ArchitectureThe History of Architecture The Current Environment Standardization Barriers The Need for Lightweight Architecture in the EnterpriseThe Cost of TechnologyThe Benefits of Enterprise Architecture The Domains of Architecture The Gap between Business and ITWhere Does LEA Fit? LEA's FrameworkFrameworks, Methodologies, and Approaches The Framework of LEATypes of Methodologies Types of ApproachesActual System Environmen

  8. Software architecture 1

    CERN Document Server

    Oussalah , Mourad Chabane

    2014-01-01

    Over the past 20 years, software architectures have significantly contributed to the development of complex and distributed systems. Nowadays, it is recognized that one of the critical problems in the design and development of any complex software system is its architecture, i.e. the organization of its architectural elements. Software Architecture presents the software architecture paradigms based on objects, components, services and models, as well as the various architectural techniques and methods, the analysis of architectural qualities, models of representation of architectural template

  9. Software architecture 2

    CERN Document Server

    Oussalah, Mourad Chabanne

    2014-01-01

    Over the past 20 years, software architectures have significantly contributed to the development of complex and distributed systems. Nowadays, it is recognized that one of the critical problems in the design and development of any complex software system is its architecture, i.e. the organization of its architectural elements. Software Architecture presents the software architecture paradigms based on objects, components, services and models, as well as the various architectural techniques and methods, the analysis of architectural qualities, models of representation of architectural templa

  10. An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

    1991-01-01

    A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required......- mu m CMOS process using MOSIS-like simplified design rules. The chip operates at speeds up to 19 MHz under worst-case conditions (V/sub DD/=4.75 V and T/sub A/=70 degrees C). The core of the chip (excluding pad cells) is 7.8*5.1 mm/sup 2/ and contains approximately 50000 transistors...

  11. Computer organization, design, and architecture

    CERN Document Server

    Shiva, Sajjan G

    2007-01-01

    Suitable for a one- or two-semester undergraduate or beginning graduate course in computer science and computer engineering, Computer Organization, Design, and Architecture, Fourth Edition presents the operating principles, capabilities, and limitations of digital computers to enable development of complex yet efficient systems. With 40% updated material and four new chapters, this edition takes students through a solid, up-to-date exploration of single- and multiple-processor systems, embedded architectures, and performance evaluation. New to the Fourth Edition Additional material that cove

  12. Architecture Synthesis and Reduced-Cost Architectures for Human Exploration Missions

    Science.gov (United States)

    Woodcock, Gordon

    2004-01-01

    Development of architectures for human exploration missions has been pursued in the international aerospace community for a long time. This paper attempts a different approach and way of looking at architectures. Most of the emphasis is on lunar architectures with a brief look at Mars. The first step is to set forth overarching gods in order to understand origins of requirements. Then, principles and guidelines are developed for architecture formulation. It is argued that safety and cost are the primary factors. Alternative mission profiles are examined for adherence to the principles, and specific architectures formulated according to the guidelines. The guidelines themselves indicate preferred evolution paths from lunar to Mars architectures. Results of example calculations are given to illustrate the process, and an evolution path is recommended. Safety and cost criteria tend to conflict, but it is shown that cost-efficient architectures can be enhanced for good safety ratings at modest cost.

  13. Transcription co-activator Arabidopsis ANGUSTIFOLIA3 (AN3) regulates water-use efficiency and drought tolerance by modulating stomatal density and improving root architecture by the transrepression of YODA (YDA).

    Science.gov (United States)

    Meng, Lai-Sheng; Yao, Shun-Qiao

    2015-09-01

    One goal of modern agriculture is the improvement of plant drought tolerance and water-use efficiency (WUE). Although stomatal density has been linked to WUE, the causal molecular mechanisms and engineered alternations of this relationship are not yet fully understood. Moreover, YODA (YDA), which is a MAPKK kinase gene, negatively regulates stomatal development. BR-INSENSITIVE 2 interacts with phosphorylates and inhibits YDA. However, whether YDA is modulated in the transcriptional level is still unclear. Plants lacking ANGUSTIFOLIA3 (AN3) activity have high drought stress tolerance because of low stomatal densities and improved root architecture. Such plants also exhibit enhanced WUE through declining transpiration without a demonstrable reduction in biomass accumulation. AN3 negatively regulated YDA expression at the transcriptional level by target-gene analysis. Chromatin immunoprecipitation analysis indicated that AN3 was associated with a region of the YDA promoter in vivo. YDA mutation significantly decreased the stomatal density and root length of an3 mutant, thus proving the participation of YDA in an3 drought tolerance and WUE enhancement. These components form an AN3-YDA complex, which allows the integration of water deficit stress signalling into the production or spacing of stomata and cell proliferation, thus leading to drought tolerance and enhanced WUE. © 2015 Society for Experimental Biology, Association of Applied Biologists and John Wiley & Sons Ltd.

  14. Architecture as Design Study.

    Science.gov (United States)

    Kauppinen, Heta

    1989-01-01

    Explores the use of analogies in architectural design, the importance of Gestalt theory and aesthetic cannons in understanding and being sensitive to architecture. Emphasizes the variation between public and professional appreciation of architecture. Notes that an understanding of architectural process enables students to improve the aesthetic…

  15. Fragments of Architecture

    DEFF Research Database (Denmark)

    Bang, Jacob Sebastian

    2016-01-01

    Topic 3: “Case studies dealing with the artistic and architectural work of architects worldwide, and the ties between specific artistic and architectural projects, methodologies and products”......Topic 3: “Case studies dealing with the artistic and architectural work of architects worldwide, and the ties between specific artistic and architectural projects, methodologies and products”...

  16. Emulated Muscle Spindle and Spiking Afferents Validates VLSI Neuromorphic Hardware as a Testbed for Sensorimotor Function and Disease

    Directory of Open Access Journals (Sweden)

    Chuanxin M. Niu

    2014-12-01

    Full Text Available The lack of multi-scale empirical measurements (e.g. recording simultaneously from neurons, muscles, whole body, etc. complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI technology to provide considerable scalability and high-speed, as much as 365x faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006 and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Matthews, 1964; 1972; Crowe and Matthews, 1964b. Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365x real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  17. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    Science.gov (United States)

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  18. Self assembly of interlocked architectures

    CERN Document Server

    Schergna, S

    2002-01-01

    An area of great interest is the synthesis and characterisation of molecules possessing moving parts, with the goal that they can act as 'molecular machine' carrying out tasks that molecules with fixed conventional architectures cannot do. Rotaxanes and catenanes (mechanically interlocked architectures) represent one approach toward achieving these aims as their component wheels and / or threads are connected together but can still move, in certain, controlled directions. This thesis focused on the study of structural rigidity and the preorganisation of thread binding sites as factors of major influence on template efficiency in the synthesis of hydrogen bond assembled supramolecular structures (rotaxanes and catenanes). Chapter One gives a brief outline of the common synthetic approaches to interlocked architectures (catenanes and rotaxanes) that are now being developed to address the problems outlined above. Chapter Two and Chapter Three concerns the synthesis of novel amide-based rotaxanes containing vario...

  19. Creating product line architectures

    OpenAIRE

    Bayer, J.; Flege, O.; Gacek, C.

    2000-01-01

    The creation and validation of product line software architectures are inherently more complex than those of software architectures for single systems. This paper compares a process for creating and evaluating a traditional, one-of-a- kind software architecture with one for a reference software architecture. The comparison is done in the context of PuLSE-DSSA, a customizable process that integrates both product line architecture creation and evaluation.

  20. Readout Architecture for Hybrid Pixel Readout Chips

    CERN Document Server

    AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

    The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

  1. Octopus - an energy-efficient architecture

    NARCIS (Netherlands)

    Havinga, Paul J.M.; Smit, Gerardus Johannes Maria

    1999-01-01

    Multimedia computing and mobile computing are two trends that will lead to a new application domain in the near future. However, the technological challenges to establishing this paradigm of computing are non-trivial. Personal mobile computing offers a vision of the future with a much richer and

  2. Computer Architecture for Energy Efficient SFQ

    Science.gov (United States)

    2014-08-27

    pulse propagation. In order to form viable TSVs, they will need to be shielded and reduced in inductance. One means of accomplishing this is to...2009) 10 “Identifying and Quantifying Printed Circuit Board Performance”, Hubing, et al, IEEE International Symp on EMC p205 (1994) 24

  3. Aceleración de un algoritmo de enfriamiento simulado mediante particionamiento de redes. Aplicación a "placement" de circuitos VLSI

    OpenAIRE

    Aguirre Echanove, Miguel Ángel; Torralba Silgado, Antonio Jesús; García Franquelo, Leopoldo

    1995-01-01

    Se propone un nuevo método de mejora de los resultados del "placement" de un circuito VLSI. El método propuesto utiliza un particionamiento recursivo para obtener una solución de partida para el posterior proceso de enfriamiento simulado. Para preservar los beneficios de esta solución de partida, la temperatura inicial del algoritmo de enfriamiento es seleccionada del espacio intermedio de las temperaturas. Se presentan resultados experimentales sobre diversos circuitos de prueba, demostrando...

  4. Low-Power and Optimized VLSI Implementation of Compact Recursive Discrete Fourier Transform (RDFT Processor for the Computations of DFT and Inverse Modified Cosine Transform (IMDCT in a Digital Radio Mondiale (DRM and DRM+ Receiver

    Directory of Open Access Journals (Sweden)

    Sheau-Fang Lei

    2013-05-01

    Full Text Available This paper presents a compact structure of recursive discrete Fourier transform (RDFT with prime factor (PF and common factor (CF algorithms to calculate variable-length DFT coefficients. Low-power optimizations in VLSI implementation are applied to the proposed RDFT design. In the algorithm, for 256-point DFT computation, the results show that the proposed method greatly reduces the number of multiplications/additions/computational cycles by 97.40/94.31/46.50% compared to a recent approach. In chip realization, the core size and chip size are, respectively, 0.84 × 0.84 and 1.38 × 1.38 mm2. The power consumption for the 288- and 256-point DFT computations are, respectively, 10.2 (or 0.1051 and 11.5 (or 0.1176 mW at 25 (or 0.273 MHz simulated by NanoSim. It would be more efficient and more suitable than previous works for DRM and DRM+ applications.

  5. Modeling Architectural Patterns' Behavior Using Architectural Primitives

    NARCIS (Netherlands)

    Kamal, Ahmad Waqas; Avgeriou, Paris; Morrison, R; Balasubramaniam, D; Falkner, K

    2008-01-01

    Architectural patterns have an impact on both the structure and the behavior of a system at the architecture design level. However, it is challenging to model patterns' behavior in a systematic way because modeling languages do not provide the appropriate abstractions and because each pattern

  6. Religious architecture: anthropological perspectives

    NARCIS (Netherlands)

    Verkaaik, O.

    2013-01-01

    Religious Architecture: Anthropological Perspectives develops an anthropological perspective on modern religious architecture, including mosques, churches and synagogues. Borrowing from a range of theoretical perspectives on space-making and material religion, this volume looks at how religious

  7. Software architecture evolution

    DEFF Research Database (Denmark)

    Barais, Olivier; Le Meur, Anne-Francoise; Duchien, Laurence

    2008-01-01

    architecture. Following the early aspect paradigm, Tran SAT allows the software architect to design a software architecture stepwise in terms of aspects at the design stage. It realises the evolution as the weaving of new architectural aspects into an existing software architecture.......Software architectures must frequently evolve to cope with changing requirements, and this evolution often implies integrating new concerns. Unfortunately, when the new concerns are crosscutting, existing architecture description languages provide little or no support for this kind of evolution....... The software architect must modify multiple elements of the architecture manually, which risks introducing inconsistencies. This chapter provides an overview, comparison and detailed treatment of the various state-of-the-art approaches to describing and evolving software architectures. Furthermore, we discuss...

  8. Rhein-Ruhr architecture

    DEFF Research Database (Denmark)

    2002-01-01

    katalog til udstillingen 'Rhein - Ruhr architecture' Meldahls smedie, 15. marts - 28. april 2002. 99 sider......katalog til udstillingen 'Rhein - Ruhr architecture' Meldahls smedie, 15. marts - 28. april 2002. 99 sider...

  9. Data accuracy assessment using enterprise architecture

    Science.gov (United States)

    Närman, Per; Holm, Hannes; Johnson, Pontus; König, Johan; Chenine, Moustafa; Ekstedt, Mathias

    2011-02-01

    Errors in business processes result in poor data accuracy. This article proposes an architecture analysis method which utilises ArchiMate and the Probabilistic Relational Model formalism to model and analyse data accuracy. Since the resources available for architecture analysis are usually quite scarce, the method advocates interviews as the primary data collection technique. A case study demonstrates that the method yields correct data accuracy estimates and is more resource-efficient than a competing sampling-based data accuracy estimation method.

  10. Information architecture for a planetary 'exploration web'

    Science.gov (United States)

    Lamarra, N.; McVittie, T.

    2002-01-01

    'Web services' is a common way of deploying distributed applications whose software components and data sources may be in different locations, formats, languages, etc. Although such collaboration is not utilized significantly in planetary exploration, we believe there is significant benefit in developing an architecture in which missions could leverage each others capabilities. We believe that an incremental deployment of such an architecture could significantly contribute to the evolution of increasingly capable, efficient, and even autonomous remote exploration.

  11. Bioclimatism in vernacular architecture

    OpenAIRE

    Coch Roura, Helena

    1998-01-01

    Any analysis of the role played by energy in architecture is faced with serious limitations due to the lack of studies in the architectural bibliography, especially studies of popular architecture. An awareness of these limitations will allow us to understand better why architects have paid little attention to the interaction of form and energy, and to the bioclimatic approach in contemporary architecture in general. The first limitation stems from the very essence of bioclimatic analysis; en...

  12. Controller Architectures for Switching

    DEFF Research Database (Denmark)

    Niemann, Hans Henrik; Poulsen, Niels Kjølstad

    2009-01-01

    This paper investigate different controller architectures in connection with controller switching. The controller switching is derived by using the Youla-Jabr-Bongiorno-Kucera (YJBK) parameterization. A number of different architectures for the implementation of the YJBK parameterization...... are described and applied in connection with controller switching. An architecture that does not include inversion of the coprime factors is introduced. This architecture will make controller switching particular simple....

  13. Can You Hear Architecture

    DEFF Research Database (Denmark)

    Ryhl, Camilla

    2016-01-01

    design and architectural quality for people with a hearing disability and a newly conducted qualitative evaluation research in Denmark as well as architectural theories on multisensory aspects of architectural experiences, the paper uses examples of existing Nordic building cases to discuss the role...

  14. OS Friendly Microprocessor Architecture

    Science.gov (United States)

    2017-04-01

    Architecture Version 2 Permission Bit Cache Bank Architecture 28 5.7 Microkernel, OS, and Application Cache Banks Organization 29 5.8 Process Level Cache... architecture cache bank organization 5.8 Process Level Cache Bank Operations Figure 26 presents a simplified example of microkernel cache banks and cache...

  15. Secure Storage Architectures

    Energy Technology Data Exchange (ETDEWEB)

    Aderholdt, Ferrol [Tennessee Technological University; Caldwell, Blake A [ORNL; Hicks, Susan Elaine [ORNL; Koch, Scott M [ORNL; Naughton, III, Thomas J [ORNL; Pogge, James R [Tennessee Technological University; Scott, Stephen L [Tennessee Technological University; Shipman, Galen M [ORNL; Sorrillo, Lawrence [ORNL

    2015-01-01

    The purpose of this report is to clarify the challenges associated with storage for secure enclaves. The major focus areas for the report are: - review of relevant parallel filesystem technologies to identify assets and gaps; - review of filesystem isolation/protection mechanisms, to include native filesystem capabilities and auxiliary/layered techniques; - definition of storage architectures that can be used for customizable compute enclaves (i.e., clarification of use-cases that must be supported for shared storage scenarios); - investigate vendor products related to secure storage. This study provides technical details on the storage and filesystem used for HPC with particular attention on elements that contribute to creating secure storage. We outline the pieces for a a shared storage architecture that balances protection and performance by leveraging the isolation capabilities available in filesystems and virtualization technologies to maintain the integrity of the data. Key Points: There are a few existing and in-progress protection features in Lustre related to secure storage, which are discussed in (Chapter 3.1). These include authentication capabilities like GSSAPI/Kerberos and the in-progress work for GSSAPI/Host-keys. The GPFS filesystem provides native support for encryption, which is not directly available in Lustre. Additionally, GPFS includes authentication/authorization mechanisms for inter-cluster sharing of filesystems (Chapter 3.2). The limitations of key importance for secure storage/filesystems are: (i) restricting sub-tree mounts for parallel filesystem (which is not directly supported in Lustre or GPFS), and (ii) segregation of hosts on the storage network and practical complications with dynamic additions to the storage network, e.g., LNET. A challenge for VM based use cases will be to provide efficient IO forwarding of the parallel filessytem from the host to the guest (VM). There are promising options like para-virtualized filesystems to

  16. Architecture-Driven Requirements Engineering

    NARCIS (Netherlands)

    Engelsman, W.; Jonkers, Henk; Franken, H.M.; Franken, Henry M.; Iacob, Maria Eugenia; Proper, Erik; Harmsen, Frank; Dietz, Jan L.G.

    2009-01-01

    This paper presents an architecture driven requirements engineering method. We will demonstrate how to integrate requirements engineering in architecture design and we will demonstrate how to use enterprise architectures during solution realization projects. We will demonstrate how architecture can

  17. Exporting Humanist Architecture

    DEFF Research Database (Denmark)

    Nielsen, Tom

    2016-01-01

    The article is a chapter in the catalogue for the Danish exhibition at the 2016 Architecture Biennale in Venice. The catalogue is conceived at an independent book exploring the theme Art of Many - The Right to Space. The chapter is an essay in this anthology tracing and discussing the different...... values and ethical stands involved in the export of Danish Architecture. Abstract: Danish architecture has, in a sense, been driven by an unwritten contract between the architects and the democratic state and its institutions. This contract may be viewed as an ethos – an architectural tradition...... with inherent aesthetic and moral values. Today, however, Danish architecture is also an export commodity. That raises questions, which should be debated as openly as possible. What does it mean for architecture and architects to practice in cultures and under political systems that do not use architecture...

  18. The Chameleon Architecture for Streaming DSP Applications

    Directory of Open Access Journals (Sweden)

    André B. J. Kokkeler

    2007-02-01

    Full Text Available We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2 in a 130 nm process, is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC via a network interface (NI. Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT and best effort (BE. For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

  19. The Chameleon Architecture for Streaming DSP Applications

    Directory of Open Access Journals (Sweden)

    Heysters PaulM

    2007-01-01

    Full Text Available We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2 in a 130 nm process, is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC via a network interface (NI. Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT and best effort (BE. For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

  20. Knowledge and Architectural Practice

    DEFF Research Database (Denmark)

    Verbeke, Johan

    2017-01-01

    This paper focuses on the specific knowledge residing in architectural practice. It is based on the research of 35 PhD fellows in the ADAPT-r (Architecture, Design and Art Practice Training-research) project. The ADAPT-r project innovates architectural research in combining expertise from academia...... and from practice in order to highlight and extract the specific kind of knowledge which resides and is developed in architectural practice (creative practice research). The paper will discuss three ongoing and completed PhD projects and focusses on the outcomes and their contribution to the field....... Specific to these research projects is that the researcher is within academia but stays emerged in architectural practice. The projects contribute to a better understanding of architectural practice, how it develops and what kind of knowledge is crucial. Furthermore, the paper will develop a reflection...

  1. Enterprise architecture management

    DEFF Research Database (Denmark)

    Rahimi, Fatemeh; Gøtze, John; Møller, Charles

    2017-01-01

    Despite the growing interest in enterprise architecture management, researchers and practitioners lack a shared understanding of its applications in organizations. Building on findings from a literature review and eight case studies, we develop a taxonomy that categorizes applications of enterprise...... architecture management based on three classes of enterprise architecture scope. Organizations may adopt enterprise architecture management to help form, plan, and implement IT strategies; help plan and implement business strategies; or to further complement the business strategy-formation process....... The findings challenge the traditional IT-centric view of enterprise architecture management application and suggest enterprise architecture management as an approach that could support the consistent design and evolution of an organization as a whole....

  2. Architecture and Stages

    DEFF Research Database (Denmark)

    Kiib, Hans

    2009-01-01

    Architecture and Art as Fuel New development zones for shopping and entertainment and space for festivals inside the city CAN be coupled with art and architecture and become ‘open minded' public domains based on cultural exchange and mutual learning. This type of space could be labelled...... as "experiencescape" - a space between tourism, culture, learning and economy. Strategies related to these challenges involve new architectural concepts and art as ‘engines' for a change. New expressive architecture and old industrial buildings are often combined into hybrid narratives, linking the past...... with the future. But this is not enough. The agenda is to develop architectural spaces, where social interaction and learning are enhanced by art and fun. How can we develop new architectural designs in our inner cities and waterfronts where eventscapes, learning labs and temporal use are merged with everyday...

  3. Service entity network virtualization architecture and model

    Science.gov (United States)

    Jin, Xue-Guang; Shou, Guo-Chu; Hu, Yi-Hong; Guo, Zhi-Gang

    2017-07-01

    Communication network can be treated as a complex network carrying a variety of services and service can be treated as a network composed of functional entities. There are growing interests in multiplex service entities where individual entity and link can be used for different services simultaneously. Entities and their relationships constitute a service entity network. In this paper, we introduced a service entity network virtualization architecture including service entity network hierarchical model, service entity network model, service implementation and deployment of service entity networks. Service entity network oriented multiplex planning model were also studied and many of these multiplex models were characterized by a significant multiplex of the links or entities in different service entity network. Service entity networks were mapped onto shared physical resources by dynamic resource allocation controller. The efficiency of the proposed architecture was illustrated in a simulation environment that allows for comparative performance evaluation. The results show that, compared to traditional networking architecture, this architecture has a better performance.

  4. DIALOG and SYNC a VLSI chip set for timing of the LHCb Muon detector

    CERN Document Server

    Cadeddu, S; Deplano, C; Lai, A

    2004-01-01

    The Muon detector of the LHCb experiment at CERN plays a fundamental role in the first trigger level. It is mainly realized by means of a MWPC technology and consists of about 126,000 front-end channels. High efficiency is necessary both at detector and front-end level to satisfy the trigger requirement of 5 hits per 5 Muon stations with an overall efficiency of 95%. This corresponds to having a single front- end channel detection efficiency of 99% within a time window of 20 ns and also poses the problem of an accurate time alignment of the whole detector. The problem is addressed by designing two custom integrated circuits, named DIALOG and SYNC, realized in the IBM 0.25 mu m radiation hard technology. (3 refs).

  5. Software Architecture Evolution

    Science.gov (United States)

    2013-12-01

    Software Architecture Evolution Jeffrey M. Barnes December 2013 CMU-ISR-13-118 Institute for Software Research School of Computer Science Carnegie...DEC 2013 2. REPORT TYPE 3. DATES COVERED 00-00-2013 to 00-00-2013 4. TITLE AND SUBTITLE Software Architecture Evolution 5a. CONTRACT NUMBER 5b...systems eventually undergo changes to their basic architectural structure. Such changes may be prompted by new feature requests, new quality attribute

  6. Architecture for the senses

    DEFF Research Database (Denmark)

    Ryhl, Camilla

    2009-01-01

    Accommodating sensory disabilities in architectural design requires specific design considerations. These are different from the ones included by the existing design concept 'accessibility', which primarily accommodates physical disabilites. Hence a new design concept 'sensory accessbility......' is presented as a parallel and complementary concept to the existing one. Sensory accessiblity accommodates sensory disabilities and describes architectural design requirements needed to ensure access to to the sensory experiences and architectural quality of a given space. The article is based on research...

  7. Essential Layers, Artifacts, and Dependencies of Enterprise Architecture

    OpenAIRE

    Winter, Robert; Fischer, Ronny

    2007-01-01

    After a period where implementation speed was more important than integration, consistency and reduction of complexity, architectural considerations have become a key issue of information management in recent years again. Enterprise architecture is widely accepted as an essential mechanism for ensuring agility and consistency, compliance and efficiency. Although standards like TOGAF and FEAF have developed, however, there is no common agreement on which architecture layers, which artifact typ...

  8. Architecture and Programming Models for High Performance Intensive Computation

    Science.gov (United States)

    2016-06-29

    AFRL-AFOSR-VA-TR-2016-0230 Architecture and Programming Models for High Performance Intensive Computation XiaoMing Li UNIVERSITY OF DELAWARE Final...TITLE AND SUBTITLE Architecture and Programming Models for High Performance Intensive Computation 5a. CONTRACT NUMBER 5b. GRANT NUMBER FA9550-13-1-0213...developing an efficient system architecture and software tools for building and running Dynamic Data Driven Application Systems (DDDAS). The foremost

  9. A hardware implementation of neural network with modified HANNIBAL architecture

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Bum youb; Chung, Duck Jin [Inha University, Inchon (Korea, Republic of)

    1996-03-01

    A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). 14 refs., 10 figs., 3 tabs.

  10. Grid Architecture 2

    Energy Technology Data Exchange (ETDEWEB)

    Taft, Jeffrey D. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2016-01-01

    The report describes work done on Grid Architecture under the auspices of the Department of Electricity Office of Electricity Delivery and Reliability in 2015. As described in the first Grid Architecture report, the primary purpose of this work is to provide stakeholder insight about grid issues so as to enable superior decision making on their part. Doing this requires the creation of various work products, including oft-times complex diagrams, analyses, and explanations. This report provides architectural insights into several important grid topics and also describes work done to advance the science of Grid Architecture as well.

  11. Elements of Architecture

    DEFF Research Database (Denmark)

    Elements of Architecture explores new ways of engaging architecture in archaeology. It conceives of architecture both as the physical evidence of past societies and as existing beyond the physical environment, considering how people in the past have not just dwelled in buildings but have existed...... and affective impacts, of these material remains. The contributions in this volume investigate the way time, performance and movement, both physically and emotionally, are central aspects of understanding architectural assemblages. It is a book about the constellations of people, places and things that emerge...

  12. Towards a Media Architecture

    DEFF Research Database (Denmark)

    Ebsen, Tobias

    2010-01-01

    This text explores the concept of media architecture as a phenomenon of visual culture that describes the use of screen-technology in new spatial configurations in practices of architecture and art. I shall argue that this phenomenon is not necessarily a revolutionary new approach, but rather...... a result of conceptual changes in both modes visual representation and in expressions of architecture. These are changes the may be described as an evolution of ideas and consequent experiments that can be traced back to changes in the history of art and the various styles and ideologies of architecture....

  13. VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

    Science.gov (United States)

    Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

    2017-08-01

    Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

  14. Implementation of a 4-tier Cloud-Based Architecture for ...

    African Journals Online (AJOL)

    Akorede

    mining procedures as well as Cloud Service Provider (CSP) and Health Care Providers (HCPs). The architecture which has been implemented on CloudSim has proved to be efficient and reliable base on the results obtained when compared with previous work. KEYWORDS: Architecture, collaborative, cloud computing, ...

  15. Quantitative Application Data Flow Characterization for Heterogeneous Multicore Architectures

    NARCIS (Netherlands)

    Ostadzadeh, S.A.

    2012-01-01

    Recent trends show a steady increase in the utilization of heterogeneous multicore architectures in order to address the ever-growing need for computing performance. These emerging architectures pose specific challenges with regard to their programmability. In addition, they require efficient

  16. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

  17. Enterprise architecture intelligence

    NARCIS (Netherlands)

    Veneberg, R.K.M.; Iacob, Maria Eugenia; van Sinderen, Marten J.; Bodenstaff, L.; Reichert, M.U.; Rinderle-Ma, S.; Grossmann, G.

    2014-01-01

    Combining enterprise architecture and operational data is complex (especially when considering the actual ‘matching’ of data with enterprise architecture objects), and little has been written on how to do this. Therefore, in this paper we aim to fill this gap and propose a method to combine

  18. Towards Adaptive Evolutionary Architecture

    DEFF Research Database (Denmark)

    Bak, Sebastian HOlt; Rask, Nina; Risi, Sebastian

    2016-01-01

    This paper presents first results from an interdisciplinary project, in which the fields of architecture, philosophy and artificial life are combined to explore possible futures of architecture. Through an interactive evolutionary installation, called EvoCurtain, we investigate aspects of how...

  19. Architecture and energy

    DEFF Research Database (Denmark)

    Marsh, Rob; Lauring, Michael

    2011-01-01

    Traditional low-energy architecture has not necessarily led to reduced energy consumption. A paradigm shift is proposed promoting pluralistic energy-saving strategies.......Traditional low-energy architecture has not necessarily led to reduced energy consumption. A paradigm shift is proposed promoting pluralistic energy-saving strategies....

  20. Digitally-Driven Architecture

    Directory of Open Access Journals (Sweden)

    Henriette Bier

    2010-06-01

    Full Text Available The shift from mechanical to digital forces architects to reposition themselves: Architects generate digital information, which can be used not only in designing and fabricating building components but also in embedding behaviours into buildings. This implies that, similar to the way that industrial design and fabrication with its concepts of standardisation and serial production influenced modernist architecture, digital design and fabrication influences contemporary architecture. While standardisa­tion focused on processes of rationalisation of form, mass-customisation as a new paradigm that replaces mass-production, addresses non-standard, complex, and flexible designs. Furthermore, knowledge about the designed object can be encoded in digital data pertaining not just to the geometry of a design but also to its physical or other behaviours within an environment. Digitally-driven architecture implies, therefore, not only digitally-designed and fabricated architecture, it also implies architecture – built form – that can be controlled, actuated, and animated by digital means. In this context, this sixth Footprint issue examines the influence of digital means as prag­matic and conceptual instruments for actuating architecture. The focus is not so much on computer-based systems for the development of architectural designs, but on architecture incorporating digital control, sens­ing, actuating, or other mechanisms that enable buildings to inter­act with their users and surroundings in real time in the real world through physical or sensory change and variation.

  1. Architecture and Intelligentsia

    Directory of Open Access Journals (Sweden)

    Alexander Rappaport

    2015-08-01

    Full Text Available The article observes intellectual and cultural level of architecture and its important functions in social process. Historical analysis shows constant decline of intellectual level of profession, as a reaction on radical changes in its social functions and mass scale, leading to degrading of individual critical reflection and growing dependence of architecture to political and economical bureaucracy.

  2. Architectural Physics: Lighting.

    Science.gov (United States)

    Hopkinson, R. G.

    The author coordinates the many diverse branches of knowledge which have dealt with the field of lighting--physiology, psychology, engineering, physics, and architectural design. Part I, "The Elements of Architectural Physics", discusses the physiological aspects of lighting, visual performance, lighting design, calculations and measurements of…

  3. Information Architecture: Looking Ahead.

    Science.gov (United States)

    Rosenfeld, Louis

    2002-01-01

    Considers the future of the field of information architecture. Highlights include a comparison with the growth of the field of professional management; the design of information systems since the Web; more demanding users; the need for an interdisciplinary approach; and how to define information architecture. (LRW)

  4. Aesthetics of sustainable architecture

    NARCIS (Netherlands)

    Lee, S.; Hill, G.; Sauerbruch, M.; Hutton, L.; Knowles, R.; Bothwell, K.; Brennan, J.; Jauslin, D.; Holzheu, H.; AlSayyad, N.; Arboleda, G.; Bharne, V.; Røstvik, H.; Kuma, K.; Sunikka-Blank, M.; Glaser, M.; Pero, E.; Sjkonsberg, M.; Teuffel, P.; Mangone, G.; Finocchiaro, L.; Hestnes, A.; Briggs, D.; Frampton, K.; Lee, S.

    2011-01-01

    The purpose of this book is to reveal, explore and further the debate on the aesthetic potentials of sustainable architecture and its practice. This book opens a new area of scholarship and discourse in the design and production of sustainable architecture, one that is based in aesthetics. The

  5. Workflow automation architecture standard

    Energy Technology Data Exchange (ETDEWEB)

    Moshofsky, R.P.; Rohen, W.T. [Boeing Computer Services Co., Richland, WA (United States)

    1994-11-14

    This document presents an architectural standard for application of workflow automation technology. The standard includes a functional architecture, process for developing an automated workflow system for a work group, functional and collateral specifications for workflow automation, and results of a proof of concept prototype.

  6. Digitally-Driven Architecture

    Directory of Open Access Journals (Sweden)

    Henriette Bier

    2014-07-01

    Full Text Available The shift from mechanical to digital forces architects to reposition themselves: Architects generate digital information, which can be used not only in designing and fabricating building components but also in embedding behaviours into buildings. This implies that, similar to the way that industrial design and fabrication with its concepts of standardisation and serial production influenced modernist architecture, digital design and fabrication influences contemporary architecture. While standardisation focused on processes of rationalisation of form, mass-customisation as a new paradigm that replaces mass-production, addresses non-standard, complex, and flexible designs. Furthermore, knowledge about the designed object can be encoded in digital data pertaining not just to the geometry of a design but also to its physical or other behaviours within an environment. Digitally-driven architecture implies, therefore, not only digitally-designed and fabricated architecture, it also implies architecture – built form – that can be controlled, actuated, and animated by digital means.In this context, this sixth Footprint issue examines the influence of digital means as pragmatic and conceptual instruments for actuating architecture. The focus is not so much on computer-based systems for the development of architectural designs, but on architecture incorporating digital control, sens­ing, actuating, or other mechanisms that enable buildings to inter­act with their users and surroundings in real time in the real world through physical or sensory change and variation.

  7. Software Architecture Evolution

    Science.gov (United States)

    Barnes, Jeffrey M.

    2013-01-01

    Many software systems eventually undergo changes to their basic architectural structure. Such changes may be prompted by new feature requests, new quality attribute requirements, changing technology, or other reasons. Whatever the causes, architecture evolution is commonplace in real-world software projects. Today's software architects, however,…

  8. Architecture or Sculpture?

    DEFF Research Database (Denmark)

    Baumeister, Ruth

    2014-01-01

    Jørn Utzon´s museum design for Asger Jorn´s collection in Silkeborg contextualized in the postwar context of an organic architecture.......Jørn Utzon´s museum design for Asger Jorn´s collection in Silkeborg contextualized in the postwar context of an organic architecture....

  9. Symbiosis of aesthetics and efficiency. Klimahaus {sup registered} Bremerhaven 8 Ost sets new standards for architecture and technology; Symbiose aus Inhalt und Verpackung. Klimahaus {sup registered} Bremerhaven 8 Ost setzt neue Massstaebe fuer Architektur und Technik

    Energy Technology Data Exchange (ETDEWEB)

    Heumer, Wolfgang [Klimahaus Betriebsgesellschaft mbH (Germany); Kessling, Wolfgang; Oberdorf, Christian [Transsolar Energietechnik GmbH (Germany); Matzel, Martin [ACD Communication GmbH (Germany)

    2009-07-01

    From outside, the Klimahaus {sup registered} Bremerhaven 8 Ost looks like a cloud or a ship. The building houses an information centre with a floor space of nearly 12,000 square meters in the new Bremerhaven district of ''Havenwelten'', between the old harbour and the dyke of the outer Weser river. Facts and phenomena on climate and climate protection are presented inside the building. With its unique concept, the Klimahaus {sup registered} sets new architectural standards. (orig.)

  10. Rapid phenotyping of alfalfa root system architecture

    Science.gov (United States)

    Root system architecture (RSA) influences the capacity of an alfalfa plant for symbiotic nitrogen fixation, nutrient uptake and water use efficiency, resistance to frost heaving, winterhardiness, and some pest and pathogen resistance. However, we currently lack a basic understanding of root system d...

  11. Product Architecture Modularity Strategies

    DEFF Research Database (Denmark)

    Mikkola, Juliana Hsuan

    2003-01-01

    The focus of this paper is to integrate various perspectives on product architecture modularity into a general framework, and also to propose a way to measure the degree of modularization embedded in product architectures. Various trade-offs between modular and integral product architectures...... and how components and interfaces influence the degree of modularization are considered. In order to gain a better understanding of product architecture modularity as a strategy, a theoretical framework and propositions are drawn from various academic literature sources. Based on the literature review......, the following key elements of product architecture are identified: components (standard and new-to-the-firm), interfaces (standardization and specification), degree of coupling, and substitutability. A mathematical function, termed modularization function, is introduced to measure the degree of modularization...

  12. Architecture as liminal Space

    Directory of Open Access Journals (Sweden)

    Nilly Harag

    2015-11-01

    Full Text Available The point of departure of the architectural project has to stem from the combination of inner and outer journeys in between the real or imagined limits. The pressing challenge is to destabilize the neat division of architecture into separate bodies of knowledge and pose the architect’s mode of action on the threshold between the concrete and the universal. Architecture is a lens, an instrument one looks through to bring new perspectives into focus, enabling the transformation of experience from a magnified self-concentrated space to a wide horizon. Architecture narrates relations between spaces and examines its validity through signifying practices of design. Design for itself becomes the language of the current, of the immediate fashion. Architecture can fulfill peoples’ dreams and miraculously can provide them tools to invent new ones: Curiosity is the first motive to act.

  13. Can architecture be barbaric?

    Science.gov (United States)

    Hürol, Yonca

    2009-06-01

    The title of this article is adapted from Theodor W. Adorno's famous dictum: 'To write poetry after Auschwitz is barbaric.' After the catastrophic earthquake in Kocaeli, Turkey on the 17th of August 1999, in which more than 40,000 people died or were lost, Necdet Teymur, who was then the dean of the Faculty of Architecture of the Middle East Technical University, referred to Adorno in one of his 'earthquake poems' and asked: 'Is architecture possible after 17th of August?' The main objective of this article is to interpret Teymur's question in respect of its connection to Adorno's philosophy with a view to make a contribution to the politics and ethics of architecture in Turkey. Teymur's question helps in providing a new interpretation of a critical approach to architecture and architectural technology through Adorno's philosophy. The paper also presents a discussion of Adorno's dictum, which serves for a better understanding of its universality/particularity.

  14. Architecture of a Morphological Malware Detector

    OpenAIRE

    Bonfante, Guillaume; Kaczmarek, Matthieu; Marion, Jean-Yves

    2009-01-01

    International audience; Most of malware detectors are based on syntactic signatures that identify known malicious programs. Up to now this architecture has been sufficiently efficient to overcome most of malware attacks. Nevertheless, the complexity of malicious codes still increase. As a result the time required to reverse engineer malicious programs and to forge new signatures is increasingly longer. This study proposes an efficient construction of a morphological malware detector, that is ...

  15. Minimalism in architecture: Abstract conceptualization of architecture

    Directory of Open Access Journals (Sweden)

    Vasilski Dragana

    2015-01-01

    Full Text Available Minimalism in architecture contains the idea of the minimum as a leading creative tend to be considered and interpreted in working through phenomena of empathy and abstraction. In the Western culture, the root of this idea is found in empathy of Wilhelm Worringer and abstraction of Kasimir Malevich. In his dissertation, 'Abstraction and Empathy' Worringer presented his thesis on the psychology of style through which he explained the two opposing basic forms: abstraction and empathy. His conclusion on empathy as a psychological basis of observation expression is significant due to the verbal congruence with contemporary minimalist expression. His intuition was enhenced furthermore by figure of Malevich. Abstraction, as an expression of inner unfettered inspiration, has played a crucial role in the development of modern art and architecture of the twentieth century. Abstraction, which is one of the basic methods of learning in psychology (separating relevant from irrelevant features, Carl Jung is used to discover ideas. Minimalism in architecture emphasizes the level of abstraction to which the individual functions are reduced. Different types of abstraction are present: in the form as well as function of the basic elements: walls and windows. The case study is an example of Sou Fujimoto who is unequivocal in its commitment to the autonomy of abstract conceptualization of architecture.

  16. Architecture Diagrams: A Graphical Language for Architecture Style Specification

    Directory of Open Access Journals (Sweden)

    Anastasia Mavridou

    2016-08-01

    Full Text Available Architecture styles characterise families of architectures sharing common characteristics. We have recently proposed configuration logics for architecture style specification. In this paper, we study a graphical notation to enhance readability and easiness of expression. We study simple architecture diagrams and a more expressive extension, interval architecture diagrams. For each type of diagrams, we present its semantics, a set of necessary and sufficient consistency conditions and a method that allows to characterise compositionally the specified architectures. We provide several examples illustrating the application of the results. We also present a polynomial-time algorithm for checking that a given architecture conforms to the architecture style specified by a diagram.

  17. Preserving urban objects of historicaland architectural heritage

    Directory of Open Access Journals (Sweden)

    Bal'zannikova Ekaterina Mikhailovna

    2014-01-01

    Full Text Available Large cities of central Russia were built under the influence of the factors that played an important role in protecting their population; natural resources and opportunities for trading were also essential. The industrial development and construction of large industrial facilities were significant for the formation of urban environment. As a result architectural monuments of great historical value that have a significant influence on the formation of the modern city image were preserved.Nowadays, a great number of buildings of historical and architectural heritage turned out to be in poor condition. Funding and its efficient use are rational means of saving the most valuable objects of historical and cultural heritage. In order to do this it is necessary to solve the problems of developing complex and effective measures for preserving these objectsThe existing method of preserving urban objects does not focus on urban architectural objects of historical and architectural value. It does not cover the study of urban development features in architectural and town-planning environment surrounding this object, it does not determine the historical and architectural value of the object and it does not identify the relationship of the object and the surrounding objects as well as architectural frame of the total area. That is why the existing method cannot be considered an appropriate system for preserving the objects of historical and architectural heritage.In order to avoid the disadvantages mentioned above and to increase tourist interest to the architecturally valuable buildings in urban areas, the author has proposed a complex approach to improve the method of reconstructing urban objects of great historical and architectural significance.The existing method of preserving historical objects includes the preparatory period of studying the degree of historical and architectural heritage wear and decay, developing the techniques for strengthening

  18. Travels in Architectural History

    Directory of Open Access Journals (Sweden)

    Davide Deriu

    2016-11-01

    Full Text Available Travel is a powerful force in shaping the perception of the modern world and plays an ever-growing role within architectural and urban cultures. Inextricably linked to political and ideological issues, travel redefines places and landscapes through new transport infrastructures and buildings. Architecture, in turn, is reconstructed through visual and textual narratives produced by scores of modern travellers — including writers and artists along with architects themselves. In the age of the camera, travel is bound up with new kinds of imaginaries; private records and recollections often mingle with official, stereotyped views, as the value of architectural heritage increasingly rests on the mechanical reproduction of its images. Whilst students often learn about architectural history through image collections, the place of the journey in the formation of the architect itself shifts. No longer a lone and passionate antiquarian or an itinerant designer, the modern architect eagerly hops on buses, trains, and planes in pursuit of personal as well as professional interests. Increasingly built on a presumption of mobility, architectural culture integrates travel into cultural debates and design experiments. By addressing such issues from a variety of perspectives, this collection, a special 'Architectural Histories' issue on travel, prompts us to rethink the mobile conditions in which architecture has historically been produced and received.

  19. Avionics Architecture for Exploration Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The Avionics Architectures for Exploration Project team will develop a system level environment and architecture that will accommodate equipment from multiple...

  20. Integrated Data Assimilation Architecture Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The Integrated Data Assimilation Architecture (IDAA) is a middleware architecture that facilitates the incorporation of heterogeneous sensing and control devices...

  1. On Detailing in Contemporary Architecture

    DEFF Research Database (Denmark)

    Kristensen, Claus; Kirkegaard, Poul Henning

    2010-01-01

    Details in architecture have a significant influence on how architecture is experienced. One can touch the materials and analyse the detailing - thus details give valuable information about the architectural scheme as a whole. The absence of perceptual stimulation like details and materiality...... / tactility can blur the meaning of the architecture and turn it into an empty statement. The present paper will outline detailing in contemporary architecture and discuss the issue with respect to architectural quality. Architectural cases considered as sublime piece of architecture will be presented...

  2. Computer architecture technology trends

    CERN Document Server

    1991-01-01

    Please note this is a Short Discount publication. This year's edition of Computer Architecture Technology Trends analyses the trends which are taking place in the architecture of computing systems today. Due to the sheer number of different applications to which computers are being applied, there seems no end to the different adoptions which proliferate. There are, however, some underlying trends which appear. Decision makers should be aware of these trends when specifying architectures, particularly for future applications. This report is fully revised and updated and provides insight in

  3. Architectural Knitted Surfaces

    DEFF Research Database (Denmark)

    Mossé, Aurélie

    2010-01-01

    WGSN reports from the Architectural Knitted Surfaces workshop recently held at ShenkarCollege of Engineering and Design, Tel Aviv, which offered a cutting-edge insight into interactive knitted surfaces. With the increasing role of smart textiles in architecture, the Architectural Knitted Surfaces...... workshop brought together architects and interior and textile designers to highlight recent developments in intelligent knitting. The five-day workshop was led by architects Ayelet Karmon and Mette Ramsgaard Thomsen, together with Amir Cang and Eyal Sheffer from the Knitting Laboratory, in collaboration...

  4. An Integrated Hybrid Transportation Architecture for Human Mars Expeditions

    Science.gov (United States)

    Merrill, Raymond G.; Chai, Patrick R.; Qu, Min

    2015-01-01

    NASA's Human Spaceflight Architecture Team is developing a reusable hybrid transportation architecture that uses both chemical and electric propulsion systems on the same vehicle to send crew and cargo to Mars destinations such as Phobos, Deimos, the surface of Mars, and other orbits around Mars. By applying chemical and electrical propulsion where each is most effective, the hybrid architecture enables a series of Mars trajectories that are more fuel-efficient than an all chemical architecture without significant increases in flight times. This paper presents an integrated Hybrid in-space transportation architecture for piloted missions and delivery of cargo. A concept for a Mars campaign including orbital and Mars surface missions is described in detail including a system concept of operations and conceptual design. Specific constraints, margin, and pinch points are identified for the architecture and opportunities for critical path commercial and international collaboration are discussed.

  5. 4th Conference on Advances in architectural geometry 2014

    CERN Document Server

    Knippers, Jan; Mitra, Niloy; Wang, Wenping

    2015-01-01

    This book contains 24 technical papers presented at the fourth edition of the Advances in Architectural Geometry conference, AAG 2014, held in London, England, September 2014. It offers engineers, mathematicians, designers, and contractors insight into the efficient design, analysis, and manufacture of complex shapes, which will help open up new horizons for architecture. The book examines geometric aspects involved in architectural design, ranging from initial conception to final fabrication. It focuses on four key topics: applied geometry, architecture, computational design, and also practice in the form of case studies. In addition, the book also features algorithms, proposed implementation, experimental results, and illustrations. Overall, the book presents both theoretical and practical work linked to new geometrical developments in architecture. It gathers the diverse components of the contemporary architectural tendencies that push the building envelope towards free form in order to respond to multiple...

  6. Implantable VLSI systems for compression and communication in wireless biosensor recording arrays

    Science.gov (United States)

    Kamboh, Awais Mehmood

    Successful use of microelectrode arrays to record neural activity in the cortex has opened new opportunities for scientists to decode the intricate functionality of the human brain and the behavior of neurons that enable its complex operation. The resulting brain-machine interface devices play a critical role in enabling patients with neural disorders to achieve a better lifestyle. Such interfaces provide a direct interface to the brain and show great promise in many biomedical applications. This thesis explores some of the major obstacles impeding the advance of wireless neural implants and addresses them through development of highly efficient algorithms and implantable hardware. An overwhelming amount of data is generated by the microelectrode arrays, resulting in a data bandwidth bottleneck. To overcome this problem, an implantable system has been devised to enable control over the amount of data that must be transmitted without compromising the information contained in the array of neural signals. Furthermore, the nature of the wireless communication channel across the skin tissue is not well characterized. In this thesis, solutions have been developed to maximize that data throughput and enable unfailing yet low-power communication of bidirectional data between the implanted device and the external world. Finally, a unified energy-efficient, implantable CMOS integrated circuit was developed to address these two critical problems. The resulting integrated solution ensures seamless multi-modal operation, and thus establishes a pathway to the design of next-generation neuroprosthetics devices. Although the motivation for this thesis comes from the field of neuroprosthetics, the solutions devised are pertinent to a wide range of implantable applications.

  7. Evaluation of software architecture using fuzzy color Petri net

    Directory of Open Access Journals (Sweden)

    Zohreh Shiriyan Dehkordi

    2013-02-01

    Full Text Available Unified modeling language is a semi-formal and standard language for describing software architecture easily used to meet requirement functionality and to describe behavioral and structural specifications in software engineering. However, since UML is not a formal model, direct evaluation of software architecture is not possible, directly. On the other hand, evaluating software architecture in initial phases helps us consider more requirements and it reduces designing expenditures. Therefore, converting pragmatic model to formal model is necessary for software architecture evaluation. For evaluating software architecture and making an executive model, using color Petri net are useful because of simplicity, high capability and enhancing theoretical mathematics. Using language variables and fuzzy logic causes a higher accuracy in computations associated with efficiency evaluation. In this paper, we present fuzzy logic and reaction analysis before implementation, which can improve efficiency of design problems.

  8. Constructing three-dimensional quasi-vertical nanosheet architectures from self-assemble two-dimensional WO3·2H2O for efficient electrochromic devices

    DEFF Research Database (Denmark)

    Li, Haizeng; Wang, Jinmin; Shi, Qiuwei

    2016-01-01

    Three-dimensional (3D) quasi-vertical nanosheet (QVNS) architectures are of great importance in the application of electrochromic devices due to its 3D porous structures, large surface area and lamellar permeable space of nanosheets. In this study, we demonstrate successful preparing of WO3·2H2O...... nanosheets via a novel and facile solution route and repurposing the typical electrodeposition technique to obtain 3D QVNS electrodes. The electrode was successfully assembled into an electrochromic device which exhibits good electrochromic performance....

  9. Perceptual-components architecture for digital video

    Science.gov (United States)

    Watson, Andrew B.

    1990-01-01

    A perceptual-components architecture for digital video partitions the image stream into signal components in a manner analogous to that used in the human visual system. These components consist of achromatic and opponent color channels, divided into static and motion channels, further divided into bands of particular spatial frequency and orientation. Bits are allocated to an individual band in accord with visual sensitivity to that band and in accord with the properties of visual masking. This architecture is argued to have desirable features such as efficiency, error tolerance, scalability, device independence, and extensibility.

  10. Kalman filter tracking on parallel architectures

    Science.gov (United States)

    Cerati, G.; Elmer, P.; Krutelyov, S.; Lantz, S.; Lefebvre, M.; McDermott, K.; Riley, D.; Tadel, M.; Wittich, P.; Wurthwein, F.; Yagil, A.

    2017-10-01

    We report on the progress of our studies towards a Kalman filter track reconstruction algorithm with optimal performance on manycore architectures. The combinatorial structure of these algorithms is not immediately compatible with an efficient SIMD (or SIMT) implementation; the challenge for us is to recast the existing software so it can readily generate hundreds of shared-memory threads that exploit the underlying instruction set of modern processors. We show how the data and associated tasks can be organized in a way that is conducive to both multithreading and vectorization. We demonstrate very good performance on Intel Xeon and Xeon Phi architectures, as well as promising first results on Nvidia GPUs.

  11. Architectures of prototypes and architectural prototyping

    DEFF Research Database (Denmark)

    Hansen, Klaus Marius; Christensen, Michael; Sandvad, Elmer

    1998-01-01

    This paper reports from experience obtained through development of a prototype of a global customer service system in a project involving a large shipping company and a university research group. The research group had no previous knowledge of the complex business of shipping and had never worked...... together as a team, but developed a prototype that more than fulfilled the expectations of the shipping company. The prototype should: - complete the first major phase within 10 weeks, - be highly vertical illustrating future work practice, - continuously live up to new requirements from prototyping...... sessions with users, - evolve over a long period of time to contain more functionality - allow for 6-7 developers working intensively in parallel. Explicit focus on the software architecture and letting the architecture evolve with the prototype played a major role in resolving these conflicting...

  12. ESPC Common Model Architecture Earth System Modeling Framework (ESMF) Software and Application Development

    Science.gov (United States)

    2015-09-30

    1 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. ESPC Common Model Architecture Earth System Modeling...Capability (NUOPC) was established between NOAA and Navy to develop a common software architecture for easy and efficient interoperability. The...model architecture and other software-related standards in this project. OBJECTIVES NUOPC proposes to accelerate improvement of our national

  13. Communication-Oriented Design Space Exploration for Reconfigurable Architectures

    Directory of Open Access Journals (Sweden)

    Gogniat Guy

    2007-01-01

    Full Text Available Many academic works in computer engineering focus on reconfigurable architectures and associated tools. Fine-grain architectures, field programmable gate arrays (FPGAs, are the most well-known structures of reconfigurable hardware. Dedicated tools (generic or specific allow for the exploration of their design space to choose the best architecture characteristics and/or to explore the application characteristics. The aim is to increase the synergy between the application and the architecture in order to get the best performance. However, there is no generic tool to perform such an exploration for coarse-grain or heterogeneous-grain architectures, just a small number of very specific tools are able to explore a limited set of architectures. To address this major lack, in this paper we propose a new design space exploration approach adapted to fine- and coarse-grain granularities. Our approach combines algorithmic and architecture explorations. It relies on an automatic estimation tool which computes the communication hierarchical distribution and the architectural processing resources use rate for the architecture under exploration. Such an approach forwards the rapid definition of efficient reconfigurable architectures dedicated to one or several applications.

  14. Communication-Oriented Design Space Exploration for Reconfigurable Architectures

    Directory of Open Access Journals (Sweden)

    Lilian Bossuet

    2007-03-01

    Full Text Available Many academic works in computer engineering focus on reconfigurable architectures and associated tools. Fine-grain architectures, field programmable gate arrays (FPGAs, are the most well-known structures of reconfigurable hardware. Dedicated tools (generic or specific allow for the exploration of their design space to choose the best architecture characteristics and/or to explore the application characteristics. The aim is to increase the synergy between the application and the architecture in order to get the best performance. However, there is no generic tool to perform such an exploration for coarse-grain or heterogeneous-grain architectures, just a small number of very specific tools are able to explore a limited set of architectures. To address this major lack, in this paper we propose a new design space exploration approach adapted to fine- and coarse-grain granularities. Our approach combines algorithmic and architecture explorations. It relies on an automatic estimation tool which computes the communication hierarchical distribution and the architectural processing resources use rate for the architecture under exploration. Such an approach forwards the rapid definition of efficient reconfigurable architectures dedicated to one or several applications.

  15. Minimalism in architecture: Abstract conceptualization of architecture

    OpenAIRE

    Vasilski Dragana

    2015-01-01

    Minimalism in architecture contains the idea of the minimum as a leading creative tend to be considered and interpreted in working through phenomena of empathy and abstraction. In the Western culture, the root of this idea is found in empathy of Wilhelm Worringer and abstraction of Kasimir Malevich. In his dissertation, 'Abstraction and Empathy' Worringer presented his thesis on the psychology of style through which he explained the two opposing basic forms: abstraction and empathy. His concl...

  16. Analysis of Architecture Pattern Usage in Legacy System Architecture Documentation

    NARCIS (Netherlands)

    Harrison, Neil B.; Avgeriou, Paris

    2008-01-01

    Architecture patterns are an important tool in architectural design. However, while many architecture patterns have been identified, there is little in-depth understanding of their actual use in software architectures. For instance, there is no overview of how many patterns are used per system or

  17. Ultra-efficient 10 Gb/s hybrid integrated silicon photonic transmitter and receiver.

    Science.gov (United States)

    Zheng, Xuezhe; Patil, Dinesh; Lexau, Jon; Liu, Frankie; Li, Guoliang; Thacker, Hiren; Luo, Ying; Shubin, Ivan; Li, Jieda; Yao, Jin; Dong, Po; Feng, Dazeng; Asghari, Mehdi; Pinguet, Thierry; Mekis, Attila; Amberg, Philip; Dayringer, Michael; Gainsley, Jon; Moghadam, Hesam Fathi; Alon, Elad; Raj, Kannan; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2011-03-14

    Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.

  18. Agility: Agent - Ility Architecture

    National Research Council Canada - National Science Library

    Thompson, Craig

    2002-01-01

    ...., object and web technologies). The objective of the Agility project is to develop an open agent grid architecture populated with scalable, deployable, industrial strength agent grid components, targeting the theme 'agents for the masses...

  19. SERVICE ORIENTED ARCHITECTURE

    Directory of Open Access Journals (Sweden)

    Stanculea Liana

    2009-05-01

    Full Text Available Service-oriented architecture (SOA supply methods for systems development and integration where work interoperable services. A SOA suppose application functionality distribution in distinct units called services that communicate with each other. This ser

  20. Service Modularity and Architecture

    DEFF Research Database (Denmark)

    Brax, Saara A.; Bask, Anu; Hsuan, Juliana

    2017-01-01

    , platform-based and mass-customized service business models, comparative research designs, customer perspectives and service experience, performance in context of modular services, empirical evidence of benefits and challenges, architectural innovation in services, modularization in multi-provider contexts...

  1. Border information flow architecture

    Science.gov (United States)

    2006-04-01

    This brochure describes the Border Information Flow Architecture (BIFA). The Transportation Border Working Group, a bi-national group that works to enhance coordination and planning between the United States and Canada, identified collaboration on th...

  2. Bionics in architecture

    Directory of Open Access Journals (Sweden)

    Sugár Viktória

    2017-04-01

    Full Text Available The adaptation of the forms and phenomena of nature is not a recent concept. Observation of natural mechanisms has been a primary source of innovation since prehistoric ages, which can be perceived through the history of architecture. Currently, this idea is coming to the front again through sustainable architecture and adaptive design. Investigating natural innovations and the clear-outness of evolution during the 20th century led to the creation of a separate scientific discipline, Bionics. Architecture and Bionics are strongly related to each other, since the act of building is as old as the human civilization - moreover its first formal and structural source was obviously the surrounding environment. Present paper discusses the definition of Bionics and its connection with the architecture.

  3. Architecture and Energy

    DEFF Research Database (Denmark)

    Lauring, Michael; Marsh, Rob

    2009-01-01

    Architecture and Energy. Strategies for a Changing Climate. By Michael Lauring and Rob Marsh INTENT AND PURPOSE. The paper aims to further integrated design of low energy buildings with high architectural quality. A precondition for qualified integrated design is a holistic approach...... and on the related architectural aspects: Building depths, spatial organization, daylight, natural ventilation and solar cells [1]. In order to get a truer, well-focused perception of how to design sustainable buildings, one needs to know basically what is more and what is less important among all the energy......, and where the transition from an industrial to an information- or knowledge-based society is well-developed. The last three decades of the 20th century show many conscientious - both governmental and architectural - Danish attempts at creating buildings with lower heat consumption. The lower U...

  4. Thermal Space in Architecture

    DEFF Research Database (Denmark)

    Petersen, Mads Dines

    Present research is revolving around the design process and the use of digital applications to support the design process among architects. This work is made in relation to the current discussions about sustainable architecture and the increased focus on energy consumption and the comfort in our...... and understanding of spaces in buildings can change significantly and instead of the creation of frozen geometrical spaces, thermal spaces can be created as it is suggested in meteorological architecture where functions are distributed in relation to temperature gradients. This creates an interesting contrast......-introducing an increased adaptability in the architecture can be a part of re-defining the environmental agenda and re-establish a link between the environment of the site and the environment of the architecture and through that an increased appreciation of the sensuous space here framed in discussions about thermal...

  5. Performative Urban Architecture

    DEFF Research Database (Denmark)

    Thomsen, Bo Stjerne; Jensen, Ole B.

    The paper explores how performative urban architecture can enhance community-making and public domain using socio-technical systems and digital technologies to constitute an urban reality. Digital medias developed for the web are now increasingly occupying the urban realm as a tool for navigating...... using sensor technologies opening up for new access considerations in architecture as well as the ability for a local environment to act as real-time sources of information and facilities. Starting from the NoRA pavilion for the 10th International Architecture Biennale in Venice the paper discusses...... couple relationships between architecture, humans and society. These performative relationships between digital and physical environments are seen as illustrative of the social production of space by performance and the creative production of identity. The paper reflects on the perspectives...

  6. Layered Fault Management Architecture

    National Research Council Canada - National Science Library

    Sztipanovits, Janos

    2004-01-01

    ... UAVs or Organic Air Vehicles. The approach of this effort was to analyze fault management requirements of formation flight for fleets of UAVs, and develop a layered fault management architecture which demonstrates significant...

  7. Adaptive Architectural Envelope

    DEFF Research Database (Denmark)

    Foged, Isak Worre; Kirkegaard, Poul Henning

    2010-01-01

    . The general scopes of this paper are to develop a new adaptive kinetic architectural structure, particularly a reconfigurable architectural structure which can transform body shape from planar geometries to hyper-surfaces using different control strategies, i.e. a transformation into more than one or two......Recent years have seen an increasing variety of applications of adaptive architectural structures for improvement of structural performance by recognizing changes in their environments and loads, adapting to meet goals, and using past events to improve future performance or maintain serviceability...... different shape alternatives. The adaptive structure is a proposal for a responsive building envelope which is an idea of a first level operational framework for present and future investigations towards performance based responsive architectures through a set of responsive typologies. A mock- up concept...

  8. The toolbus coordination architecture

    NARCIS (Netherlands)

    Bergstra, J.A.; Klint, P.

    1996-01-01

    Building large, heterogeneous, distributed software systems poses serious problems for the software engineer; achieving interoperability of software systems is still a major challenge. We describe an experiment in designing a generic software architecture for solving these problems. To get

  9. Architecture, Drawing, Topology

    DEFF Research Database (Denmark)

    Meldgaard, Morten

    This book presents contributions of drawing and text along with their many relationalities from ontology to history and vice versa in a range of reflections on architecture, drawing and topology. We hope to thereby indicate the potential of the theme in understanding not only the architecture...... the intricate issues of the imagination and the moving ratio in the topological culture, over urban topology, diagrammatisation, mediality and dynamics of transduction in the contemporary artificial environment....

  10. Architecture humanitarian emergencies

    DEFF Research Database (Denmark)

    Gomez-Guillamon, Maria; Eskemose Andersen, Jørgen; Contreras, Jorge Lobos

    2013-01-01

    of architecture. Followed by articles focusing on interdisciplinary research and design of emergency shelters as well as educational environments. Finally concretized in 35 studies from international workshops arranged globally on and by different architect schools: Royal Danish Academy of Fine Arts in Denmark......, Architettura di Alghero in Italy, Architecture and Design of Kocaeli University in Turkey, University of Aguascalientes in Mexico, Architectura y Urbanismo of University of Chile and Escuela de Architectura of Universidad Austral in Chile....

  11. Artificial cognition architectures

    CERN Document Server

    Crowder, James A; Friess, Shelli A

    2013-01-01

    The goal of this book is to establish the foundation, principles, theory, and concepts that are the backbone of real, autonomous Artificial Intelligence. Presented here are some basic human intelligence concepts framed for Artificial Intelligence systems. These include concepts like Metacognition and Metamemory, along with architectural constructs for Artificial Intelligence versions of human brain functions like the prefrontal cortex. Also presented are possible hardware and software architectures that lend themselves to learning, reasoning, and self-evolution

  12. Greek architecture now

    DEFF Research Database (Denmark)

    Skousbøll, Karin Merete

    2006-01-01

    With the author's Scandinavian viewpoint the aim of this book has been an investigation into contemporary Greek architecture and at the same time providing an understanding for its essential characteristics based on the historic, cultural heritage of Hellas.......With the author's Scandinavian viewpoint the aim of this book has been an investigation into contemporary Greek architecture and at the same time providing an understanding for its essential characteristics based on the historic, cultural heritage of Hellas....

  13. Future Details of Architecture

    OpenAIRE

    Garcia, Mark

    2014-01-01

    Despite the exaggerated news of the untimely ′death of the detail′ by Greg Lynn, the architectural detail is now more lifelike and active than ever before. In this era of digital design and production technologies, new materials, parametrics, building information modeling (BIM), augmented realities and the nano–bio–information–computation consilience, the detail is now an increasingly vital force in architecture. Though such digitally designed and produced details are diminishing in size to t...

  14. Climate and architecture

    DEFF Research Database (Denmark)

    Tind Kristensen, Eva; Friis Møller, Winnie; Rotne, Georg

    Climate and Architecture analyserer klimaets rolle i arkitekturen. Intentionen med bogen er at pege på nogle af de mange muligheder for bygningers klimaregulering, som et mere detaljeret studie af de lokale klimatiske forhold og den stedlige byggeskik tilbyder.......Climate and Architecture analyserer klimaets rolle i arkitekturen. Intentionen med bogen er at pege på nogle af de mange muligheder for bygningers klimaregulering, som et mere detaljeret studie af de lokale klimatiske forhold og den stedlige byggeskik tilbyder....

  15. Essential software architecture

    CERN Document Server

    Gorton, Ian

    2011-01-01

    Job titles like ""Technical Architect"" and ""Chief Architect"" nowadays abound in software industry, yet many people suspect that ""architecture"" is one of the most overused and least understood terms in professional software development. Gorton's book tries to resolve this dilemma. It concisely describes the essential elements of knowledge and key skills required to be a software architect. The explanations encompass the essentials of architecture thinking, practices, and supporting technologies. They range from a general understanding of structure and quality attributes through technical i

  16. ARCHITECTURE IN THE ISLAMIC CIVILIZATION: MUSLIM BUILDING OR ISLAMIC ARCHITECTURE

    Directory of Open Access Journals (Sweden)

    Ayat Ali Yassin

    2012-12-01

    Full Text Available The main problem of the theory in the arena of islamic architecture is affected by some of its Westernthoughts, and stereotyping the islamic architecture according to Western thoughts; this leads to the breakdownof the foundations in the islamic architecture. It is a myth that islamic architecture is subjected to theinfluence from foreign architectures. This paper will highlight the dialectical concept of islamic architecture ormuslim buildings and the areas of recognition in islamic architecture. It will also widen the knowledge in thecharacteristics of each point in time according to the stages of islamic architecture from the prophetic agemoving through the architecture outside the city of Medina, the Caliphs, the Umayyad, Abbasid, andarchitectural models by spatial and time periods, taking Iraq as the example to explain how the Islam influentson architecture and vice versa.

  17. Autonomous, Decentralized Grid Architecture: Prosumer-Based Distributed Autonomous Cyber-Physical Architecture for Ultra-Reliable Green Electricity Networks

    Energy Technology Data Exchange (ETDEWEB)

    None

    2012-01-11

    GENI Project: Georgia Tech is developing a decentralized, autonomous, internet-like control architecture and control software system for the electric power grid. Georgia Tech’s new architecture is based on the emerging concept of electricity prosumers—economically motivated actors that can produce, consume, or store electricity. Under Georgia Tech’s architecture, all of the actors in an energy system are empowered to offer associated energy services based on their capabilities. The actors achieve their sustainability, efficiency, reliability, and economic objectives, while contributing to system-wide reliability and efficiency goals. This is in marked contrast to the current one-way, centralized control paradigm.

  18. Hardware architecture design of a fast global motion estimation method

    Science.gov (United States)

    Liang, Chaobing; Sang, Hongshi; Shen, Xubang

    2015-12-01

    VLSI implementation of gradient-based global motion estimation (GME) faces two main challenges: irregular data access and high off-chip memory bandwidth requirement. We previously proposed a fast GME method that reduces computational complexity by choosing certain number of small patches containing corners and using them in a gradient-based framework. A hardware architecture is designed to implement this method and further reduce off-chip memory bandwidth requirement. On-chip memories are used to store coordinates of the corners and template patches, while the Gaussian pyramids of both the template and reference frame are stored in off-chip SDRAMs. By performing geometric transform only on the coordinates of the center pixel of a 3-by-3 patch in the template image, a 5-by-5 area containing the warped 3-by-3 patch in the reference image is extracted from the SDRAMs by burst read. Patched-based and burst mode data access helps to keep the off-chip memory bandwidth requirement at the minimum. Although patch size varies at different pyramid level, all patches are processed in term of 3x3 patches, so the utilization of the patch-processing circuit reaches 100%. FPGA implementation results show that the design utilizes 24,080 bits on-chip memory and for a sequence with resolution of 352x288 and frequency of 60Hz, the off-chip bandwidth requirement is only 3.96Mbyte/s, compared with 243.84Mbyte/s of the original gradient-based GME method. This design can be used in applications like video codec, video stabilization, and super-resolution, where real-time GME is a necessity and minimum memory bandwidth requirement is appreciated.

  19. The NASA Integrated Information Technology Architecture

    Science.gov (United States)

    Baldridge, Tim

    1997-01-01

    This document defines an Information Technology Architecture for the National Aeronautics and Space Administration (NASA), where Information Technology (IT) refers to the hardware, software, standards, protocols and processes that enable the creation, manipulation, storage, organization and sharing of information. An architecture provides an itemization and definition of these IT structures, a view of the relationship of the structures to each other and, most importantly, an accessible view of the whole. It is a fundamental assumption of this document that a useful, interoperable and affordable IT environment is key to the execution of the core NASA scientific and project competencies and business practices. This Architecture represents the highest level system design and guideline for NASA IT related activities and has been created on the authority of the NASA Chief Information Officer (CIO) and will be maintained under the auspices of that office. It addresses all aspects of general purpose, research, administrative and scientific computing and networking throughout the NASA Agency and is applicable to all NASA administrative offices, projects, field centers and remote sites. Through the establishment of five Objectives and six Principles this Architecture provides a blueprint for all NASA IT service providers: civil service, contractor and outsourcer. The most significant of the Objectives and Principles are the commitment to customer-driven IT implementations and the commitment to a simpler, cost-efficient, standards-based, modular IT infrastructure. In order to ensure that the Architecture is presented and defined in the context of the mission, project and business goals of NASA, this Architecture consists of four layers in which each subsequent layer builds on the previous layer. They are: 1) the Business Architecture: the operational functions of the business, or Enterprise, 2) the Systems Architecture: the specific Enterprise activities within the context

  20. An architectural decision modeling framework for service oriented architecture design

    OpenAIRE

    Zimmermann, Olaf

    2009-01-01

    In this thesis, we investigate whether reusable architectural decision models can support Service-Oriented Architecture (SOA) design. In the current state of the art, architectural decisions are captured ad hoc and retrospectively on projects; this is a labor-intensive undertaking without immediate benefits. On the contrary, we investigate the role reusable architectural decision models can play during SOA design: We treat recurring architectural decisions as first-class method elements and p...