'De digitale elever' som genstand for ledelse af læring i folkeskolen

DEFF Research Database (Denmark)

Stenbøg, Sofie

2016-01-01

Mange børn er i dag allerede fra en tidlig alder erfarne teknologibrugere. Denne omstændighed har fået flere folkeskoler til at medtænke elevernes digitale erfaringer og kompetencer fra fritidslivet som centrale ressourcer i undervisningen. Kapitlet undersøger, hvordan ’de digitale elever’ på...... forskellige måder gøres til genstand for ledelse på en skole, der arbejder med at inddrage elevernes digitale erfaringer og kompetencer gennem digitalt projektarbejde. Kapitlet viser, at der knytter sig en lang række kausale antagelser og forhåbninger til de digitale elever, og at disse virker bestemmende...... for både lærerens ledelsesopgave og rollefordelingen mellem lærer og elever i det digitale projektarbejde. Disse antagelser og forhåbninger diskuteres kritisk i lyset af nyere studier af folkeskoleelevers digitale kompetencer....

FPGA design

CERN Document Server

Simpson, Philip

2010-01-01

This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

Transferencia de datos por puerto USB de una tarjeta FPGA Nexys 2 empleando LabWindows CVI v9.0

Directory of Open Access Journals (Sweden)

Juan Raúl Rodríguez Suárez

2011-05-01

Full Text Available Normal 0 21 false false false MicrosoftInternetExplorer4 st1:*{behavior:url(#ieooui } /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} En el trabajo se presenta la implementación de la comunicación por puerto USB entre una computadora con sistema operativo Windows y una tarjeta FPGA Nexys2.  Dicha tarjeta posee un microcontrolador Cypress CY7C68013A que maneja un puerto  USB2 de alta velocidad que ha sido programado para emular un puerto paralelo EPP. Se expone el diseño y evaluación  de una interfaz gráfica de usuario con programación LabWindows que maneja la biblioteca DPCUTIL y que posibilita la transferencia y visualización de datos desde la Nexys2. La aplicación permite  la transferencia en tiempo real de un procesador digital de 12bits, de dos canales implementado con frecuencia de muestreo de 1MHz en la FPGA. En el trabajo se evalúa los resultados alcanzados en cuanto a la velocidad de transferencia de datos efectiva.

Las tecnologías digitales en contextos interculturales.

Directory of Open Access Journals (Sweden)

Pedro Hepp K

2009-07-01

Full Text Available El presente trabajo ofrece un panorama general sobre la educación chilena con énfasis en los sectores de población más vulnerable. En seguida, aborda el uso de las tecnologías digitales en contextos interculturales en general y en el ámbito mapuche en particular. A continuación describe el estado de las tecnologías digitales en Chile y las oportunidades que esta situación ofrece para el trabajo educativo intercultural. Finalmente, presenta la línea de tecnologías digitales en contextos indígenas e interculturales del Núcleo Iniciativa Científica Milenio Centro de Investigación en Educación en Contexto Indígena e Intercultural (CIECII de la Universidad Católica de Temuco

Materiales y recursos digitales

OpenAIRE

Silva i Galán, Josep M.

2011-01-01

La oferta de herramientas, materiales y contenidos educativos digitales es ilimitada y obliga al profesorado a buscarlos, seleccionarlos y almacenarlos de una forma muy distinta a cómo estaba acostumbrado. ¿De qué recursos dispone? ¿Cómo puede organizarlos? ¿Y compartirlos?

Generación de contenidos educativos digitales

OpenAIRE

Russo, Claudia Cecilia; Durán, Laura; Calderone, Marina; Saenz, Mariana; Sarobe, Mónica; Alonso, Nicolás; Esnaola, Leonardo; Pérez, Daniela; De Vito, María Cecilia; Piergallini, Maria Rosana; Segura, Natalia; Picco, Trinidad; Osella Massa, Germán Leandro; Ramón, Hugo Dionisio

2014-01-01

La presente línea de investigación propone desde una mirada interdisciplinaria determinar y sistematizar aspectos determinantes en el desarrollo de materiales didácticos digitales a fin de generar un manual de buenas prácticas para la producción, administración y almacenamiento. Se consideran materiales digitales aquellos desarrollados para su utilización en los EVEA (Entornos Virtuales de Enseñanza y Aprendizaje), PLE (Entornos Personales de Aprendizaje), televisión digital, etc. A la hor...

Medios digitales en Ecuador: perspectivas de futuro

Directory of Open Access Journals (Sweden)

María Isabel Punín Larrea

2014-01-01

Full Text Available El avance de la tecnología, en especial, en el ámbito de la comunicación, obliga a los medios a evolucionar constantemente para no morir en un escenario marcado por una serie de transformaciones y cambios mediáticos que han afectado al periodismo como profesión y a los medios de comunicación, proceso que ha generado estudios de todo orden. Este trabajo analiza el panorama mediático digital en Ecuador, las características de cultura periodística y el consumo de contenidos en la Red. Describe las tendencias de los principales medios digitales en el país, seleccionados para realizar un estudio de caso. El artículo toma como referencia central el estudio de las diez tendencias digitales en medios de comunicación de Cerezo-Gilarranz, especialista en estrategias digitales. Posteriormente se identifican las deficiencias que tienen los medios en Ecuador; principalmente por la falta de domino de los entornos tecnológicos y la escasa vinculación del proyecto empresarial y periodístico con soportes tecnológicos e innovadores, como el uso de redes sociales... El resultado final es una guía detallada de las debilidades y las fortalezas de cada medio digital en estudio. Asimismo, este trabajo propone tendencias fiables para que los medios estudiados puedan encaminarse firmes en entornos digitales, asumiendo a las herramientas tecnológicas como oportunidad de negocio y de servicio.

FPGA programming using FX3

CERN Document Server

Calleja, Stefano

2014-01-01

An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

Digitale Indfødte - Findes De?

DEFF Research Database (Denmark)

Ivang, Reimer

2011-01-01

De digitale indfødte er i flere år blevet omtalt som samfundets redning. De har fået de grundlæggende IT kompetencer med modermælken og de anvender sociale medier, smartphones osv. i stort omfang. Når denne tsunami af progressive IT-individer rammer vores arbejdsmarked skal meget ændres. Spørgsmå......De digitale indfødte er i flere år blevet omtalt som samfundets redning. De har fået de grundlæggende IT kompetencer med modermælken og de anvender sociale medier, smartphones osv. i stort omfang. Når denne tsunami af progressive IT-individer rammer vores arbejdsmarked skal meget ændres...

Categorizando a los usuarios de sistemas digitales

OpenAIRE

Hernández y Hernández, Denise; Ramírez Martinell, Alberto; Cassany, Daniel

2014-01-01

Repasamos las categorías más utilizadas para aludir a las características de las personas que utilizan algún tipo de sistema digital, ya sea por su grado de participación en la comunicación global y en los sistemas web -1.0 o 2.0-; por la actitud que toman ante el contenido digital -consumidores o productores-; por su intermitencia en el mundo digital -residentes o visitantes-; o por el momento histórico en el que nacieron -nativos digitales o inmigrantes digitales-, con el propósito de refle...

CATEGORIZANDO A LOS USUARIOS DE SISTEMAS DIGITALES.

OpenAIRE

Denise Hernández y Hernández; Alberto Ramírez-Martinell; Daniel Cassany

2014-01-01

Repasamos las categorías más utilizadas para aludir a las características de las personas que utilizan algún tipo de sistema digital, ya sea por su grado de participación en la comu- nicación global y en los sistemas web -1.0 o 2.0-; por la actitud que toman ante el contenido digital -consumidores o productores-; por su intermitencia en el mundo digital -residentes o visitantes-; o por el momento histórico en el que nacieron -nativos digitales o inmigrantes digitales-, con el propósito de ref...

The FPGA Pixel Array Detector

International Nuclear Information System (INIS)

Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

2013-01-01

A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

Tras las competencias de los nativos digitales: avances de una metasíntesis

Directory of Open Access Journals (Sweden)

David Arturo Acosta\\u2013Silva

2017-01-01

Full Text Available En el presente documento reporto los avances de una metasíntesis realizada sobre investigaciones que en los últimos 15 años han buscado evaluar las competencias digitales de los jóvenes; ello con el fin de establecer si sus resultados soportan las posturas que afirman que los jóvenes y las jóvenes tienen unas competencias digitales generalizadas y de alto nivel. Para tal fin realicé una selección en la literatura de reportes de investigaciones cuyos objetivos se dirigieran al análisis de las competencias digitales, posteriores al planteamiento original de los nativos digitales y que presentaran resultados empíricos. De los artículos obtenidos analicé sus concepciones, métodos y resultados. El producto de este proceso indica que la mayoría de tales estudios concluyen que las aseveraciones sobre las superiores competencias digitales de los sujetos jóvenes no están soportadas empíricamente.

Jóvenes, migraciones digitales y brecha tecnológica

Directory of Open Access Journals (Sweden)

Delia María Crovi Druetta

2010-01-01

Full Text Available Este trabajo tiene como propósito reflexionar en torno a los procesos y condiciones en que actualmente se realiza la articulación juventud-digitalización. Para ello, y a partir de una caracterización de los jóvenes como nativos digitales, se definen estos dos factores identificando la existencia de brechas (digitales y cognitivas que configuran una nueva causa de exclusión para el sector juvenil.

Happing: Nativos digitales al servicio de la imagen corporativa de Coca-Cola

Directory of Open Access Journals (Sweden)

Carmen Llorente Barroso

2012-04-01

Full Text Available Happing, la comunidad de la gente que se atreve a ser feliz, es la nueva propuesta de la compañía Coca-Cola para su promoción web en España; su éxito entre los nativos digitales pone de manifiesto el acierto de esta gran marca internacional, que ha sabido aprovechar la creatividad de los nativos digitales que participan en la comunidad, para dar brillo a una Imagen Corporativa Intencional de sobra solvente. Los nativos digitales que contribuyen a la creación del mágico mundo Coca-Cola, participan gustosos de la oportunidad expresiva que les brida la compañía, fascinados por la filosofía de vida que siempre ha sido bandera de la Imagen de marca de Coca-Cola, ahora alimentada y, en parte, creada por esos nativos digitales.

Digitalisierung und Energie 4.0 - Wie schaffen wir die digitale Energiewende?

Science.gov (United States)

Irlbeck, Maximilian

Die digitale Energiewende verändert nachhaltig die Systeme der "alten" Energiewelt. Ein Zusammenwachsen verschiedener Domänen im Energiesystem, die durch digitale Technologie möglich wird, birgt enorme Herausforderungen, ist aber notwendig, um die Energiewende und ihre Ziele zu meistern. Dieser Beitrag beschreibt die Wirkung der Digitalisierung auf das Energiesystem, listet Charakteristika der digitalen Energiewende auf und schildert für verschiedene Domänen mögliche Zielvorstellungen, die durch digitale Technologie umsetzbar sind. Am Ende erläutert der Beitrag Handlungsschritte, die auf dem Weg zu einem erneuerbaren Energiesystem gegangen werden sollten und zeigt Probleme und Risiken einer Fehlentwicklung auf.

Dos generaciones de nativos digitales

Directory of Open Access Journals (Sweden)

Joaquín Linne

Full Text Available A partir de encuestas, entrevistas y observaciones en la Ciudad Autónoma de Buenos Aires, afirmamos que existen dos generaciones de nativos digitales (ND: los jóvenes 1.0 y los adolescentes 2.0. Si bien ambas comparten características comunes, los 2.0 poseen rasgos propios: son una generación post-mail, suelen haberse criado alrededor de entornos digitales y manifiestan de modo online sus aspectos íntimos. Estos contenidos personales, que comparten con su grupo de pares a través de sitios de redes sociales, expresan una nueva concepción de la intimidad que podemos denominar "multimidad". A su vez, dividimos a los ND 2.0 según su nivel de alfabetización digital, condicionado por su entorno tecnológico, su capital cultural y su uso de las TIC, con el objetivo de brindar herramientas analíticas que contribuyan a mejorar las políticas públicas de inclusión digital.

Case Study: Derechos Digitales

Directory of Open Access Journals (Sweden)

Cameron Neylon

2017-10-01

Full Text Available Derechos Digitales is a Latin American advocacy and research network focussed on freedom on the internet, privacy and copyright reform. For the pilot project a specific IDRC funded project was the notional focus of study. However in practice the effort for considering data sharing was aimed at being organisation wide. The organisation already shares reports and other resources (particularly images and infographics by default. While open data was described as being “in the DNA of the organisation” there was little practice across the network of sharing preliminary and in-process materials. Some aspects of data collection on research projects, particularly to do with copyright and legal issues, have significant privacy issues and as the organisation focuses on privacy as one of its advocacy areas this is taken very seriously. Many materials from research projects are not placed online at all. Derechos Digitales run distributed projects and this creates challenges for consistent management. Alongside this the main contact at DD changed during the course of the pilot. This exchange exemplified the challenges of maintaining organisational systems and awareness through a personnel change.

Barrierefreiheit zur Routine machen – Praxisfall: Digitale Bibliothek

Directory of Open Access Journals (Sweden)

Susanne Baudisch

2015-04-01

Full Text Available Sechs Jahre sind vergangen seit Deutschland am 24. Februar 2009 die Behindertenrechtskonvention der Vereinten Nationen (BRK, die die volle Teilhabe aller Menschen an der Gesellschaft als Menschenrecht festschreibt, ratifizierte. Bereits seit 2002 gibt es in Deutschland ein Behindertengleichstellungsgesetz (BGG, den barrierefreien Zugang zu Informations- und Kommunikationstechnologien regelt die Barrierefreie Informationstechnik-Verordnung (BITV. Aus Sicht des Gesetzgebers sind die Rahmenbedingungen gegeben, Barrierefreiheit gehört inzwischen zum gängigen Vokabular im öffentlichen und teils auch privatwirtschaftlichen Bereich. Längst möchte man meinen, es sei ein alter Hut, Barrierefreiheit als Kernanliegen zu thematisieren oder gar einzufordern. Dies betrifft auch den rasant wachsenden Bereich digitaler Medien, der Wissen und Bildung für jedermann verfügbar macht - oder machen sollte. Vor diesem Hintergrund stellen sich die Autoren der Frage, inwieweit Barrierefreiheit in den digitalen Angeboten wissenschaftlicher und öffentlicher Bibliotheken in Deutschland angekommen ist; ob diese Angebote tatsächlich von allen genutzt werden können. Ausgehend von rechtlichen Grundlagen und Normen werden Formate und Standards für barrierefreie Netzpublikationen an Beispielen diskutiert. Im Fokus stehen einerseits Werkzeuge zum Suchen und Finden digitaler Information (Kataloge und Rechercheoberflächen, andererseits Ausgabeformate digitaler Dokumente (wie XML, PDF, EPUB oder TEI. Den Abschluss bilden Empfehlungen für (Digitale Bibliotheken und deren Verbände, um Barrierefreiheit künftig zur Routine zu machen. Das Fazit: Barrierefreiheit muss gewollt, geplant und sinnvoll umgesetzt werden. Technische Komponenten sind ein wichtiger, doch meist erst der zweite Schritt.

Quickscan QTI addendum #1 - Usability study of QTI for De Digitale Universiteit

NARCIS (Netherlands)

dr. Pierre Gorissen

2003-01-01

De Digitale Universiteit (DU) performed a quickscan to determine the usability of the IMS Question and TestInteroperability (QTI) specification as a format to store questions and tests developed for and by the consortium. The original report is available in Dutch from the website of De Digitale

Strategie di spazializzazione dei contenuti nel GeniusLoci Digitale

Directory of Open Access Journals (Sweden)

Davide Gasperi

2013-07-01

Full Text Available GeniusLoci Digitale is a software architecture of virtual tour that integrates various multimedia technologies (3D computer graphics, panoramas, dynamic maps, movies, pictures to represent the identity of places. The designer is interested in reproducing virtually complex aspects that define a context, which means the effect of meaning that distinguishes one place. GeniusLoci Digitale is in fact an architecture that evolves in search of a reproductive and communicative function which is recognizable to extend its development to the Open Source community.

Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

Energy Technology Data Exchange (ETDEWEB)

Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

2017-05-23

The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

Medios digitales en Ecuador, cuántos son y qué hacen

Directory of Open Access Journals (Sweden)

Jose Rivera Costales

2013-06-01

Full Text Available El mapa de medios digitales es un estudio realizado por CIESPAL para conocer los medios que publican, investigan y difunden información noticiosa en Internet. Los formatos digitales de radio, prensa y televisión así como los nativos en Internet fueron parte de este estudio que integra 254 medios ecuatorianos. En el estudio se logró determinar: distribución geográfica, origen del medio, inmediatez, tipo de información, formatos, niveles de actualización, secciones, hipertextualidad, multimedialidad, interactividad, redes sociales y herramientas multimedia, para comprender los procesos y lógicas de los medios de comunicación digitales.

Digital techniques. Special issue; Digitale techniek. Themanummer

Energy Technology Data Exchange (ETDEWEB)

Rigter, L.J.M. [Siemens Nederland, Building Technologies, Den Haag (Netherlands); Meiring, O.; Hut, W. [Getronics Industrial Automation, Amsterdam (Netherlands); Van Dijk, K.W. [Van Dijk Woon-ICT Adviseur Domotica, Dordrecht (Netherlands); Aartman, M.J. [Siemens Nederland, Fire Safety, Den Haag (Netherlands); Spies, R.J. [Deerns raadgevende ingenieurs, Rijswijk (Netherlands); Burgers, H. [Honeywell, Amsterdam (Netherlands); Stouthart, F.J. [Merlijn Media, Waddinxveen (Netherlands); Van Gurp, J.P. [GTI Electroproject, Zaanstad (Netherlands); Draijer, G.W.

2003-06-01

In 11 articles several aspects of the principles and uses of digital techniques in buildings are highlighted: Building Automation and Control network (BACnet); trends in building automation and building management; technology and uses of domotics; developments and trends in fire alarm systems; control of thermal comfort (LonWorks); process control technology; use of internet in building management systems; and frequency control of indoor climate systems. [Dutch] In 11 artikelen wordt aandacht besteed aan de principes en het gebruik van digitale technieken in gebouwen: Building Automation and Control network (BACnet); gebouwautomatisering en gebouwbeheer nu en in de nabije toekomst; techniek, toepassing en uitvoering van domotica; ontwikkelingen en trends in brandmelders; het gebruik van LonWorks voor flexibele ruimtecomfortregelingen; digitale technieken in de meet- en regeltechniek; gebouwbeheerssytemen met geintegreerde internettechnologie; en frequentiegeregelde aandrijvingen voor de klimaattechniek.

Tethered Forth system for FPGA applications

Science.gov (United States)

Goździkowski, Paweł; Zabołotny, Wojciech M.

2013-10-01

This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

Qualification of FPGA-Based Safety-Related PRM System

International Nuclear Information System (INIS)

Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

2011-01-01

Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

Flexible experimental FPGA based platform

DEFF Research Database (Denmark)

Andersen, Karsten Holm; Nymand, Morten

2016-01-01

This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

Activismo y Prácticas Digitales en la Construcción de una Esfera LGTB en España

Directory of Open Access Journals (Sweden)

Begonya Enguix Grau

Full Text Available RESUMEN A partir de una interrogación antropológica sobre las “comunidades” y la construcción de una “esfera pública”, este artículo aborda las estrategias digitales que sirven para dar forma a lo que podría denominarse como la esfera LGTB española. Consideramos el activismo LGTB como el principal productor de discurso social legitimado y por ello hemos analizado las páginas web de siete colectivos LGTB y otros recursos digitales para examinar la articulación de prácticas digitales y no digitales, que se basan en un conocimiento compartido que evoca las identidades colectivas y retroalimenta el activismo. Tras combinar trabajo de campo antropológico sobre el activismo y etnografías digitales de entornos virtuales, consideramos que a pesar del uso intensivo de los recursos digitales, la esfera LGTB sigue dependiendo en gran medida de las redes sociales tradicionales. Como consecuencia, ponemos en duda la utilidad de la conceptualización de las relaciones digitales y no digitales como separadas y distintas y discutimos esa imbricación como una característica del activismo contemporáneo.

Vertrouwen in vrije digitale X.509 certificaten

NARCIS (Netherlands)

Koot, M.

2008-01-01

Public Key Infrastructuren (PKIs) worden vanwege hun gecentraliseerde karakter waarschijnlijk eerder geassocieerd met inbreuk op privacy dan met privacy bescherming. Dit artikel laat PKIs van een andere kant zien door een beschouwing van CAcert, een non-profit vereniging die kosteloos digitale X.509

Allemaal digitaal : Een overzicht van digitale spelvormen voor mensen met een licht verstandelijke beperking

NARCIS (Netherlands)

Alyssa de Kruif; Carly Kuijper; Josje Louisse

Voor u ligt een overzicht van vrij toegankelijke digitale spelvormen ter bevordering van de zelfredzaamheid van mensen met een licht verstandelijke beperking. In dit overzicht vindt u digitale spelvormen die beschikbaar zijn als website en/of als applicatie voor op de smartphone of tablet. Voor de

Nativos digitales y aprendizaje

Directory of Open Access Journals (Sweden)

Ramón Ovelar Beltrán

2012-04-01

Full Text Available En el presente artículo se realiza una descripción y comentario de las aportaciones más relevan-tes que se han realizado en sobre el fenómeno de los "nativos digitales" o "Net Generation". Se recogen distintas posiciones sobre el desarrollo de nuevas habilidades cognitivas y nuevas tareas y necesidades de estas nuevas generaciones afectadas por el cambio tecnológico, así como sus implicaciones para las políticas educativas y prácticas docentes.

Protection and Control with FPGA technology

Energy Technology Data Exchange (ETDEWEB)

Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2012-03-15

To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

Protection and Control with FPGA technology

International Nuclear Information System (INIS)

Sohn, K. Y.; Yi, W. J.; Koo, I. S.

2012-01-01

To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper

Competencias digitales en maestros de escuelas de educación media superior privadas

Directory of Open Access Journals (Sweden)

Ramona Imelda García López

2012-10-01

Full Text Available El propósito de este estudio fue identificar los niveles de adquisición de las competencias digitales de los docentes de las preparatorias incorporadas al Instituto Tecnológico de Sonora (ITSON, a fin de obtener un diagnóstico que permita planear un programa de estrategias de formación en el área de tecnología aplicadas en la educación; lo anterior, debido a que no hay estudios que ayuden a precisar en qué aspectos se necesita capacitar a los maestros de dichas escuelas. La investigación fue descriptiva con enfoque cuantitativo y un diseño no experimental transeccional. Participaron 170 maestros, a quienes se les administró una encuesta compuesta por 47 reactivos que medían cinco dimensiones: conocimientos y habilidades en la Web, organización en formato digital, uso de herramientas o dispositivos digitales para la comunicación, búsqueda electrónica y diseño de recursos educativos digitales. Los resultados revelan que gran parte de los maestros poseen mayor dominio en la dimensión de organización en formato digital y la que menos dominan y en la requieren un curso de capacitación es en la de diseño de recursos educativos digitales. Asimismo, a mayor edad y a más años de servicio, los maestros tienden a hacer un menor uso de la tecnología, por lo que manifiestan un menor dominio de las competencias digitales.

Irradiation test of FPGA for BES III

International Nuclear Information System (INIS)

Chen Yixin; Liang Hao; Xue Jundong; Liu Baoying; Liu Qiang; Yu Xiaoqi; Zhou Yongzhao; Hou Long

2005-01-01

The irradiation effect of FPGA, applied in Front-end Electronics for experiments of High-Energy Physics, is a serious problem. The performance of FPGA, used in the front-end card of Muon Counters of BES III project, needs to be evaluated under irradiation. SEUs on Altera ACEX 1K FPGA, observed in the experiment under the irradiation of γ ray, 14 and 2.5 MeV neutrons, was investigated. The authors calculated involved cross-section and provided reasonable analysis and evaluation for the result of the experiment. The conclusion about feasibility of applying ACEX 1K FPGA in the front-end card of the readout system of Muon Counters for BES III was given. (authors)

Exploration of Heterogeneous FPGA Architectures

Directory of Open Access Journals (Sweden)

Umer Farooq

2011-01-01

mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

Mesa redonda sobre nuevos modelos organizativos en la gestión de proyectos digitales

OpenAIRE

Taladriz Mas, Margarita; Magriñá Contreras, Marta; Martín Marichal, Carmen; Cabo Rigol, Mercé; X Workshop Rebiun sobre proyectos digitales. Valencia, 7-8 Octubre de 2010

2010-01-01

Mesa redonda dentro del X Workshop Rebiun sobre proyectos digitales, celebrado en Valencia, 7-8 Ocubre de 2010, sobre: Nuevos modelos organizativos en la gestión de proyectos digitales. Moderador: José Manuel Barrueco (UV). Intervienen: Margarita Taladriz Mas(UC3M), Marta Magriñá Contreras (UNIRIOJA), Carmen Martín Marichal (ULPGC) y Mercé Cabo Rigol (UPF).

The MCD circuit based on FPGA

International Nuclear Information System (INIS)

Vu Quoc Trong

2003-01-01

Two MCD circuits based on different FPGA are presented as results of the study of the MAX+PLUS II software and FPGA devices. An external memory like 62256 and programmed EPM7064S will be able to form a MCD with 8 kilo channels. (NHA)

Exploración de nuevos soportes digitales. Tadvertising como oportunidad para la creatividad publicitaria.

Directory of Open Access Journals (Sweden)

Patricia Comesaña Comesaña

2015-02-01

Full Text Available Las tabletas digitales han revolucionado el mercado de los dispositivos móviles y han cambiado la forma en la que el usuario interactúa con la publicidad. Se han definido nuevas estrategias, nuevas tipologías de apps, nuevos formatos interactivos y no interactivos; y se han encontrado grandes posibilidades para los anunciantes. Este libro pretende mostrar algunas de las estrategias publicitarias más comunes entre el anunciante, así casos de éxito en el mundo de las tabletas digitales que los ejemplifiquen. El storytelling, el advergaming, el advertainment, la publicidad para revistas,la prensa diaria o las aplicaciones de anunciantes más descargadas configuran el Tabvertising, la denominada por el Interactive Advertising Bureau como publicidad creada para tabletas digitales.

FPGA Design Methodologies Applicable to Nuclear Power Plants

International Nuclear Information System (INIS)

Kwong, Yongil; Jeong, Choongheui

2013-01-01

In order to solve the above problem, NPPs in some countries such as the US, Canada and Japan have already applied FPGA-based equipment which has advantages as follows: It is easier to verify the performance because it needs only HDL code to configure logic circuits without other software, compared to microprocessor-based equipment, It is much cheaper than ASIC in a small quantity, Its logic circuits are re configurable, It has enough resources like logic blocks and memory blocks to implement I and C functions, Multiple functions can be implemented in a FPGA chip, It is stronger with respect to carboy security than microprocessor-based equipment because its configuration cannot be changed by external access, It is simple to replace it with new one when it is obsolete, Its power consumption is lower. However, FPGA-based equipment does not have only the merits. There are some issues on its application to NPPs. First of all, the experiences in applying it to NPPs are much less than to other industries, and international standards or guidelines are also very few. And there is the small number of FPGA platforms for I and C systems. Finally, the specific guidelines on FPGA design are required because the design has both hardware and software characteristics. In order to handle the above issues, KINS(Korea Institute of Nuclear Safety) built a test platform last year and have developed regulatory guidelines for FPGA-application in NPPs. I and C systems of NPPs have been increasingly using FPGA-based equipment as an alternative of microprocessor-based equipment which is not simple to be evaluated for safety due to its complexity. This paper explained the FPGA design flow and design guidelines. Those methodologies can be used as the guidelines on FPGA verification for safety of I and C systems

Aspectos tributarios de las plataformas digitales en Colombia: actualidad y retos

OpenAIRE

Cabrera Cabrera, Omar Sebastián

2017-01-01

Los agigantados avances en las tecnologías de la comunicación y la información han labrado el terreno para el arribo de la economía digital. Esta situación lleva a señalar que es una realidad ineludible que la mayoría de las operaciones de negocios se canalizan hoy a través del comercio electrónico, donde las últimas décadas atestiguan el auge y revolución de todas las formas de las plataformas digitales. No obstante, estos nuevos modelos digitales de negocios conllevan importantes intrincaci...

Real-time FPGA architectures for computer vision

Science.gov (United States)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar

2000-03-01

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

Dimensiones e indicadores de la calidad informativa en los medios digitales

Directory of Open Access Journals (Sweden)

2016-10-01

Full Text Available El actual ecosistema informativo, atravesado por una lógica de mediamorfosis, está generando con avidez el surgimiento de medios digitales y portales informativos que no siguen los procedimientos editoriales formales de los medios convencionales. La crisis de los medios de comunicación tradicionales ha cambiado también nuestra forma de informarnos. Sin embargo, la calidad informativa sigue siendo un factor de discusión al no existir unidad de criterios para su análisis. En este sentido surge la pregunta ¿Cómo evaluar y valorar la calidad informativa de los medios digitales? Este trabajo contribuye a buscar convergencias entre académicos y profesionales de la comunicación sobre las áreas y dimensiones de la calidad informativa de los medios digitales en función de valores objetivos o cuantificables. Para ello se ha realizado una taxonomía de dimensiones de la calidad informativa a partir de la revisión de la literatura científica, para posteriormente someterlo a la evaluación y validación por juicio de 40 expertos, académicos y profesionales de la comunicación, para verificar su fiabilidad. Como resultado, quedaron validadas tres macroáreas de la calidad informativa, contentivas en 21 ámbitos que consideran intrínsecamente un total de 75 dimensiones. Esta investigación propone finalmente un modelo estructurado que permitirá analizar la calidad informativa de los medios digitales, tanto en su fase pre-informativa, catalogadas en el medio-empresa, las características sociolaborales de los trabajadores del medio, así como el producto final y el contenido informativo.

From OO to FPGA :

Energy Technology Data Exchange (ETDEWEB)

Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

2012-09-01

Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

Development of FPGA-based safety-related I and C systems

Energy Technology Data Exchange (ETDEWEB)

Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S. [08, Shinsugita-cho, Isogo-ku, Yokohama 235-8523 (Japan); 1, Toshiba-cho, Fuchu, Tokyo 183-8511 (Japan)

2006-07-01

Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

Realise of PWM-generating based on FPGA

International Nuclear Information System (INIS)

Su Rongfeng; Xu Ruinian; Huang Maomao

2012-01-01

The power supply digital controllers of Shanghai Synchrotron Radiation Facility(SSRF) make use of the PWM (pulse width modulation) wave as the feedback to the power-electrical devices, so as to obtain constant current of high accuracy and stability. The design of PWM wave generation structure in FPGA is good for a compact controller,and the reduction of the usage of Integrated Circuits (ICs) decreases the interference from the noise among the ICs, hence better performance of the controller. In addition, FPGA can be programmed circularly at any time,so as to optimize the structure design and make a maximum use of the advantage of FPGA. As a part of transplanting the complete function of the DSP (digital signal processor/processing), realizing the generation of PWM wave in FPGA is feasible. In this paper, we report progress in this regard at SSRF. (authors)

Modelo de Producción de Contenidos Digitales para la Educación Online

Directory of Open Access Journals (Sweden)

Evelio Granizo

2016-11-01

Full Text Available A partir de un análisis del estado actual de la industria de contenidos digitales y del entorno normativo y legal del Ecuador, referido principalmente a temas de seguridad en Internet y derechos de propiedad intelectual; y a través de una investigación de mercado, para identificar las necesidades de los usuarios y aprovechar las oportunidades y retos que presenta la educación en línea; se recomienda un modelo de producción de contenidos digitales para la educación en línea, basado en un esquema colaborativo y de ecosistema inteligente, y en un conjunto de políticas públicas para el fomento de la industria de contenidos digitales en el Ecuador.

Kommunen er død - længe leve den digitale disruption

DEFF Research Database (Denmark)

Andersen, Kim Normann

2017-01-01

"New Public Management is Dead. Long Live the Digital Era." Sådan proklamerede Patrick Donleavy digitaliseringens muligheder i en banebrydende artikel fra 2005. Med en omskrivning af dette citat til "Kommunen er død, længe leve den digitale disruption", er ballet åbnet for denne artikel......."New Public Management is Dead. Long Live the Digital Era." Sådan proklamerede Patrick Donleavy digitaliseringens muligheder i en banebrydende artikel fra 2005. Med en omskrivning af dette citat til "Kommunen er død, længe leve den digitale disruption", er ballet åbnet for denne artikel....

FPGA Design and Verification Procedure for Nuclear Power Plant MMIS

Energy Technology Data Exchange (ETDEWEB)

Lee, Dongil; Yoo, Kawnwoo; Ryoo, Kwangki [Hanbat National Univ., Daejeon (Korea, Republic of)

2013-05-15

In this paper, it is shown that it is possible to ensure reliability by performing the steps of the verification based on the FPGA development methodology, to ensure the safety of application to the NPP MMIS of the FPGA run along the step. Currently, the PLC (Programmable Logic Controller) which is being developed is composed of the FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit). As the importance of the FPGA in the NPP (Nuclear Power Plant) MMIS (Man-Machine Interface System) has been increasing than before, the research on the verification of the FPGA has being more and more concentrated recently.

FPGA Acceleration by Dynamically-Loaded Hardware Libraries

DEFF Research Database (Denmark)

Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

-the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

Development of FPGA-based safety-related instrumentation and control systems

Energy Technology Data Exchange (ETDEWEB)

Oda, N.; Tanaka, A.; Izumi, M.; Tarumi, T.; Sato, T. [Toshiba Corporation, Isogo Nuclear Engineering Center, Yokohama (Japan)

2004-07-01

Toshiba has developed systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related instrumentation and control systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

Fault tolerance based on serial communication of FPGA

International Nuclear Information System (INIS)

Peng Jing; Fang Zongliang; Xu Quanzhou; Hu Jiewei; Ma Guizhen

2012-01-01

There maybe appear mistake in serial communication. This paper was described the intellectual detector of γ dose ratemeter communication with FPGA. The software of FPGA designed the code about fault tolerance, prevented mistake effectively. (authors)

Random number generators for large-scale parallel Monte Carlo simulations on FPGA

Science.gov (United States)

Lin, Y.; Wang, F.; Liu, B.

2018-05-01

Through parallelization, field programmable gate array (FPGA) can achieve unprecedented speeds in large-scale parallel Monte Carlo (LPMC) simulations. FPGA presents both new constraints and new opportunities for the implementations of random number generators (RNGs), which are key elements of any Monte Carlo (MC) simulation system. Using empirical and application based tests, this study evaluates all of the four RNGs used in previous FPGA based MC studies and newly proposed FPGA implementations for two well-known high-quality RNGs that are suitable for LPMC studies on FPGA. One of the newly proposed FPGA implementations: a parallel version of additive lagged Fibonacci generator (Parallel ALFG) is found to be the best among the evaluated RNGs in fulfilling the needs of LPMC simulations on FPGA.

Computer vision camera with embedded FPGA processing

Science.gov (United States)

Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

2000-03-01

Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

Algorithmic strategies for FPGA-based vision

OpenAIRE

Lim, Yoong Kang

2016-01-01

As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

A Hardware Framework for on-Chip FPGA Acceleration

DEFF Research Database (Denmark)

Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

2016-01-01

In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

Studerende og underviseres brug af digitale medier - En kvantitativ undersøgelse af Aarhus Universitets studerende og underviseres brug af digitale medier og internettet anno 2008

Directory of Open Access Journals (Sweden)

Maria Hvid Stenalt

2009-06-01

• Hvilke medier anvender universitetsstuderende generelt? • Ligner undervisernes medievalg/forbrug de studerendes? • Hvilke medier inddrager underviserne i undervisningen? Nærværende artikel vil forsøge at besvare disse spørgsmål på baggrund af en kvantitativ spørgeskemaundersøgelse af Aarhus Universitets studerende og underviseres brug af digitale medier og internettet. Undersøgelsen blev gennemført i efteråret 2008 af E-læringsenheden ved Aarhus Universitet som led i en almen kvalitetssikring på media- og e-læringsområdet, samt som led i en behovsafklaring vedrørende etablering af et medie- og podcastarkiv. E-læringsenheden er en administrativ enhed, der teknisk og pædagogisk understøtter underviseres inddragelse af digitale medier i undervisningen.

Exploración de nuevos soportes digitales. Tadvertising como oportunidad para la creatividad publicitaria.

OpenAIRE

Patricia Comesaña Comesaña

2015-01-01

Las tabletas digitales han revolucionado el mercado de los dispositivos móviles y han cambiado la forma en la que el usuario interactúa con la publicidad. Se han definido nuevas estrategias, nuevas tipologías de apps, nuevos formatos interactivos y no interactivos; y se han encontrado grandes posibilidades para los anunciantes. Este libro pretende mostrar algunas de las estrategias publicitarias más comunes entre el anunciante, así casos de éxito en el mundo de las tabletas digitales que los ...

OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

Biosorción de metales pesados empleando lodos activados

OpenAIRE

Santos Bonilla, Karín Ángela; Santos Bonilla, Karín Ángela

2010-01-01

Aunque las tecnologías existentes, tales como: precipitación química, osmosis inversa, intercambio iónico y separación por membranas representan una alternativa potencial para el tratamiento de drenajes ácidos de mina, presentan significativas desventajas como requerimientos altos de reactivos y energía; además de la generación de lodos tóxicos y otros subproductos a disponer. En este contexto, la biosorción empleando lodos activados procedentes de una planta de tratamiento de aguas residuale...

Prototyping Advanced Control Systems on FPGA

Directory of Open Access Journals (Sweden)

Simard Stéphane

2009-01-01

Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

Desarrollo de competencias digitales docentes en la educación básica

Directory of Open Access Journals (Sweden)

Víctor Gerardo Morales Arce

2013-04-01

Full Text Available Este documento tiene como objetivo presentar un breve análisis de cómo se está favoreciendo la formación de competencias digitales en docentes de educación básica con el programa Habilidades Digitales para Todos (HDT; se destaca la importancia y trascendencia de la formación digital para hacer frente a las expectativas y retos que plantea el nuevo paradigma educativo, al introducir las nuevas tecnologías de la información y la comunicación (TIC a las prácticas educativas propias del siglo XXI.

FPGA Implementation of the stepwise shutdown system

International Nuclear Information System (INIS)

Lotjonen, L.

2012-01-01

This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and standards can be used to some extent but the hardware aspects bring new challenges that cannot be tackled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation process from the requirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

FPGA Implementation of the stepwise shutdown system

Energy Technology Data Exchange (ETDEWEB)

Lotjonen, L.

2012-07-01

This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

Percepción de estudiantes con discapacidad visual sobre sus competencias digitales en una universidad pública del sureste de México

Directory of Open Access Journals (Sweden)

Silvia Patricia Aquino Zúñiga

2016-04-01

Full Text Available En este artículo nuestro objetivo fue indagar la percepción de estudiantes universitarios con discapacidad visual (ECDV acerca del desarrollo de sus competencias digitales. Participaron en el estudio los diez ECDV inscritos en programas de licenciatura en el ciclo 2014-02. Evaluamos el avance que perciben los estudiantes en competencias digitales relacionadas con el aprendizaje social y colaborativo, la búsqueda y tratamiento de la información, el desarrollo de relaciones interpersonales en el contexto universitario, y el uso de herramientas virtuales y de comunicación social de la universidad. Los resultados sugieren que, a excepción de aquellas referentes a las relaciones interpersonales, los ECDV perciben poco adelanto en sus competencias digitales. Con una prueba Anova de medidas repetidas, determinamos que la percepción de los ECDV sobre las competencias digitales concernientes a las relaciones interpersonales es significativamente mayor que la que reportan en las otras competencias. Concluimos que los ECDV no perciben una mejora en sus competencias digitales, en particular las de aprendizaje social y colaborativo, así como el uso de herramientas digitales.

Digitale Medien in der Grundschule

Directory of Open Access Journals (Sweden)

Birgit Eickelmann

2013-06-01

Full Text Available Mit der internationalen Grundschulleistungsstudie Trends in International Mathematics and Science Study (TIMSS 2011; vgl. Bos/Wendt/Köller/Selter 2012; Suchań/Wallner-Paschon/Bergmüller/Schreiner 2012 liegen aktuelle Daten zur schulischen und außerschulischen Nutzung digitaler Medien durch GrundschülerInnen sowie Lehrerdaten über den Einsatz von digitalen Medien in der Schule sowie im Fachunterricht in den Fächern Mathematik und Naturwissenschaften vor. Mit diesem Beitrag sollen die für die beteiligten Länder repräsentativen Daten genutzt werden, um Einblicke in die schulische und außerschulische Nutzung digitaler Medien durch Grundschulkinder am Ende der vierten Klasse zu geben. Dabei werden die Länder Deutschland und Österreich fokussiert und verglichen. Die Befunde werden theoretisch im Gesamtkontext der Medienpädagogik und vor dem Hintergrund der Qualitätsentwicklung von Schulsystemen im internationalen Vergleich diskutiert.With the international large-scale assessment study TIMSS 2011 (Trends in International Mathematics and Science Study; cf. Bos/Wendt/Köller/Selter 2012; Suchań/Wallner-Paschon/Bergmüller/Schreiner 2012 rich data concerning primary students’ and teachers’ use of computers is available. This data gives insights into the use of digital media both at school and in subject specific courses such as mathematics and science. With this contribution representative TIMSS-data is used to examine the role of new technologies at the end of Grade 4. In this process, a description and a comparison of the educational systems in Germany and in Austria will be focused. Findings will be discussed in the light of media education and the quality of school systems in the context of international developments.

A software radio platform based on ARM and FPGA

Directory of Open Access Journals (Sweden)

Yang Xin.

2016-01-01

Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

A FPGA-based architecture for real-time image matching

Science.gov (United States)

Wang, Jianhui; Zhong, Sheng; Xu, Wenhui; Zhang, Weijun; Cao, Zhiguo

2013-10-01

Image matching is a fundamental task in computer vision. It is used to establish correspondence between two images taken at different viewpoint or different time from the same scene. However, its large computational complexity has been a challenge to most embedded systems. This paper proposes a single FPGA-based image matching system, which consists of SIFT feature detection, BRIEF descriptor extraction and BRIEF matching. It optimizes the FPGA architecture for the SIFT feature detection to reduce the FPGA resources utilization. Moreover, we implement BRIEF description and matching on FPGA also. The proposed system can implement image matching at 30fps (frame per second) for 1280x720 images. Its processing speed can meet the demand of most real-life computer vision applications.

Interpretación de las competencias digitales profesorales presentes en el contexto universitario

Directory of Open Access Journals (Sweden)

Mariel Evelyn Castellanos Adarme

2018-01-01

Full Text Available La investigación tuvo como objetivo interpretar realidades en competencias digitales de docentes y estudiantes en Norte de Santander, buscó contribuir con la educación de calidad en la consolidación de competencias digitales, al innovar y transformar la realidad universitaria a través del pensamiento reflexivo hacia un aprendizaje significativo y colaborativo con horizonte pedagógico socio critico apoyado en las teorías de la complejidad y el constructivismo para lograr que concurran los tres elementos básicos: Estado-Profesores-Estudiantes. Siguió la metodología cualitativa, mediante la etnografía y con un método de análisis hermenéutico, a partir de cuatro fases sistemáticas para la correcta gestión de la investigación, se seleccionaron como informantes clave a profesores, estudiantes a quienes se les aplicó la entrevista a profundidad así como la observación participante, el análisis de la información se llevó mediante la categorización, emergiendo resultados cruciales en los espacios académicos para la consolidación de competencias digitales. Resultados muestran el escaso dominio de competencias digitales por parte de profesores y estudiantes en logro de un aprendizaje significativo; se concluye que existe un distanciamiento entre la realidad y el deber ser; es decir, entre la planeación y ejecución de acciones que conduzcan al uso, familiarización e integración de las tecnologías como se demanda y prácticas en el ámbito educativo y laboral actual.

Logic qualification of FPGA-based safety-related I and C systems

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

2009-01-01

We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

FPGA design best practices for team-based reuse

CERN Document Server

Simpson, Philip Andrew

2015-01-01

This book describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book’s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expand...

Technologies for faults diagnosis of FPGA logic blocks

Directory of Open Access Journals (Sweden)

C. U. Ngene

2012-08-01

Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

FPGA-Based Sonar Processing

National Research Council Canada - National Science Library

Graham, Paul; Nelson, Brent

1998-01-01

This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays...

FPGA based Control of a Production Cell System

NARCIS (Netherlands)

Groothuis, M.A.; van Zuijlen, Jasper J.P.; Broenink, Johannes F.

Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control

Commercial FPGA based multipurpose controller: implementation perspective

International Nuclear Information System (INIS)

Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

2012-01-01

This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

FPGA remote update for nuclear environments

Energy Technology Data Exchange (ETDEWEB)

Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

2015-07-01

The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

El laberinto teatral de espejos digitales : la presentación de mexicano-americanos en Facebook

OpenAIRE

Arao Galhardi, Renato de Almeida

2010-01-01

Este trabajo explora las formas en las cuales mexicano-americanos universitarios actualmente viviendo en Estados Unidos, se presentan en un sitio de redes sociales, Facebook. Partiendo de los enfoques del interaccionismo simbólico, la fenomenología y la psicología social, investigando cómo éstos incorporan la mexicanidad dentro de sus presentaciones digitales. 1. Definición del marco analítico. -- 2. Internet: la red de redes. -- 3. Una introducción a Facebook. -- 4. Analogías digitales: s...

‹Digitale Bildung› und die Genealogie digitaler Kultur: historiographische Skizzen

Directory of Open Access Journals (Sweden)

Benjamin Jörissen

2016-10-01

Full Text Available Wenn Aspekte ‹Digitaler Kultur› und Effekte der ‹Digitalisierung› der Selbst- und Weltverhältnisse thematisiert werden – vom Selfie über das quantified Self zur Big Data – so geschieht dies meist unter der Perspektive emergenter medientechnologischer Brüche und Umbrüche von Kultur. Man findet entsprechend dort, wo überhaupt historische Perpektiven bemüht werden, vor allem technik-, medien- und kommunikationszentrierte Emergenznarrationen. Es stellt sich angesichts der enormen Entwicklungsgeschwindigkeit der Digitalisierung jedoch die Frage nach ihren kulturellen Möglichkeitsbedingungen. Die offenkundig hohe Anschlussfähigkeit des Digitalen setzt auf – prinzipiell bekannten – kulturhistorischen Strukturbildungen auf, die ihm überhaupt erst ‹Bedeutung› geben können. Eine solche ‹Digitalisierung avant la technique› skizziert der Beitrag anhand dreier historischer Prozesslinien seit der Neuzeit – der Quantifizierung von Zahlverständnissen, der Organisation von ‹Wissen› im proto-datenbankförmigen Tableau und der Verknüpfung von Subjektivität und Sichtbarkeit.

Digitale inhoud en consumentenkooprecht : Een groot bezwaar en een kleine wijziging

NARCIS (Netherlands)

Neppelenbroek, E.D.C.

2014-01-01

Met de voorgestelde wijze van implementatie van de Europese Richtlijn consumentenrechten worden de bepalingen over consumentenkoop grotendeels vant toepassing op digitale inhoud die niet op dragers wordt geleverd. Hiermee lijkt het consumentenkooprecht van toepassing te worden op alle overeengekomen

Embedded system in FPGA-based LLRF controller for FLASH

Science.gov (United States)

Szewinski, Jaroslaw; Pucyk, Piotr; Jalmuzna, Wojciech; Fafara, Przemyslaw; Pieciukiewicz, Marcin; Romaniuk, Ryszard; Pozniak, Krzysztof T.

2006-10-01

FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

Fpga As A Part Of Ms Windows Control Environment

Directory of Open Access Journals (Sweden)

Krzysztof Kołek

2007-01-01

Full Text Available The attention is focused on the Windows operating system (OS used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS.Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

Long-distance configuration of FPGA based on serial communication

International Nuclear Information System (INIS)

Liu Xiang; Song Kezhu; Zhang Sifeng

2010-01-01

To solve FPGA configuration in some nuclear electronics, which works in radioactivity environment, the article introduces a way of long-distance configuration with PC and CPLD, based on serial communication. Taking CYCLONE series FPGA and EPCS configuration chip from ALTERA for example, and using the AS configuration mode, we described our design from the aspects of basic theory, hardware connection, software function and communication protocol. With this design, we could configure several FPGAs in the distance of 100 meters, or we could configure on FPGA in the distance of 150 meters. (authors)

Automatic generation of application specific FPGA multicore accelerators

DEFF Research Database (Denmark)

Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

2014-01-01

High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

Proyecto de mejora de la durabilidad de los pavimentos usados en aeropuertos empleando materiales alternativos y geo-sintéticos

OpenAIRE

Cabezuelo Moreno, Juan José

2015-01-01

Contribuir a la mejora de la durabilidad de los pavimentos usados en las pistas de aeropuertos, en particular pavimentos de tipo flexible, empleando combinaciones de capas de diferentes materiales y geo-sintéticos. En particular, plantear el uso de materiales novedosos como alternativa a las típicas capas de pavimento a base de hormigón y mejora de la durabilidad de las mismas empleando combinaciones de sendos materiales y geo-sintéticos. El mundo de la aviación y en concreto el del diseño...

Flexible, fpga-based electronics for modular robots

DEFF Research Database (Denmark)

Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

2008-01-01

In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

FPGA based Smart Wireless MIMO Control System

International Nuclear Information System (INIS)

Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

2013-01-01

In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

Interconnectedness und digitale Texte

Directory of Open Access Journals (Sweden)

Detlev Doherr

2013-04-01

Full Text Available Zusammenfassung Die multimedialen Informationsdienste im Internet werden immer umfangreicher und umfassender, wobei auch die nur in gedruckter Form vorliegenden Dokumente von den Bibliotheken digitalisiert und ins Netz gestellt werden. Über Online-Dokumentenverwaltungen oder Suchmaschinen können diese Dokumente gefunden und dann in gängigen Formaten wie z.B. PDF bereitgestellt werden. Dieser Artikel beleuchtet die Funktionsweise der Humboldt Digital Library, die seit mehr als zehn Jahren Dokumente von Alexander von Humboldt in englischer Übersetzung im Web als HDL (Humboldt Digital Library kostenfrei zur Verfügung stellt. Anders als eine digitale Bibliothek werden dabei allerdings nicht nur digitalisierte Dokumente als Scan oder PDF bereitgestellt, sondern der Text als solcher und in vernetzter Form verfügbar gemacht. Das System gleicht damit eher einem Informationssystem als einer digitalen Bibliothek, was sich auch in den verfügbaren Funktionen zur Auffindung von Texten in unterschiedlichen Versionen und Übersetzungen, Vergleichen von Absätzen verschiedener Dokumente oder der Darstellung von Bilden in ihrem Kontext widerspiegelt. Die Entwicklung von dynamischen Hyperlinks auf der Basis der einzelnen Textabsätze der Humboldt‘schen Werke in Form von Media Assets ermöglicht eine Nutzung der Programmierschnittstelle von Google Maps zur geographischen wie auch textinhaltlichen Navigation. Über den Service einer digitalen Bibliothek hinausgehend, bietet die HDL den Prototypen eines mehrdimensionalen Informationssystems, das mit dynamischen Strukturen arbeitet und umfangreiche thematische Auswertungen und Vergleiche ermöglicht. Summary The multimedia information services on Internet are becoming more and more comprehensive, even the printed documents are digitized and republished as digital Web documents by the libraries. Those digital files can be found by search engines or management tools and provided as files in usual formats as

IMPLEMENTACIÓN EN HARDWARE DEL ESTÁNDAR DE ENCRIPTACIÓN AVANZADO (AES, EN UNA PLATAFORMA FPGA, EMPLEANDO EL MICROCONTROLADOR PICOBLAZETM

Directory of Open Access Journals (Sweden)

J. Fernando Piñal M.

2009-01-01

Full Text Available En este trabajo analizamos las características del estándar de encriptación avanzado AES y suimplementación en una tarjeta de desarrollo FPGA Spartan-3E , utilizando una de las herramientas de procesamiento embebido del fabricante Xilinx®, el microcontrolador PicoBlaze¿. Además se diseñó un bloque en VHDL, el cual es el encargado de realizar la interfaz entre el microcontrolador y los periféricos de entrada- salida de la tarjeta. El ingreso de los datos a cifrar puede realizarse de dos maneras: mediante un teclado conectado al puerto PS/2 de la tarjeta o transmitiéndolos por el puerto serie de una computadora personal; para esto se diseñó una interfaz programada en Matlab¿. Los datos cifrados pueden observarse en el exhibidor LCD de la tarjeta de desarrollo, o bien se pueden transmitir en modo serial hacia una computadora personal. Estas opciones de funcionamiento del sistema se seleccionan mediante los interruptores deslizables de la tarjeta de desarrollo. La verificación del funcionamiento del sistema se realiza haciendo uso del documento oficial que describe a AES: FIPS-PUB 197. Aun cuando se implementó el algoritmo en un sistema basado en un procesador, se obtuvo un buen rendimiento. Se incluye la comparación del desempeño de nuestro diseño con otras arquitecturas que implementan también el mismo algoritmo.

Verification of FPGA-based NPP I and C systems. General approach and techniques

International Nuclear Information System (INIS)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Reva, Lubov; Siora, Alexander

2011-01-01

This paper presents a general approach and techniques for design and verification of Field Programmable Gates Arrays (FPGA)-based Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP). Appropriate regulatory documents used for I and C systems design, development, verification and validation (V and V) are discussed considering the latest international standards and guidelines. Typical development and V and V processes of FPGA electronic design for FPGA-based NPP I and C systems are presented. Some safety-related features of implementation process are discussed. Corresponding development artifacts, related to design and implementation activities are outlined. An approach to test-based verification of FPGA electronic design algorithms, used in FPGA-based reactor trip systems is proposed. The results of application of test-based techniques for assessment of FPGA electronic design algorithms for reactor trip system (RTS) produced by Research and Production Corporation (RPC) 'Radiy' are presented. Some principles of invariant-oriented verification for FPGA-based safety-critical systems are outlined. (author)

Modelo de Producción de Contenidos Digitales para la Educación Online

OpenAIRE

Evelio Granizo; Silvia Haro

2016-01-01

A partir de un análisis del estado actual de la industria de contenidos digitales y del entorno normativo y legal del Ecuador, referido principalmente a temas de seguridad en Internet y derechos de propiedad intelectual; y a través de una investigación de mercado, para identificar las necesidades de los usuarios y aprovechar las oportunidades y retos que presenta la educación en línea; se recomienda un modelo de producción de contenidos digitales para la educación en línea, basado en un esque...

La relevancia de los medios digitales en la Iniciativa Ciudadana Europea

Directory of Open Access Journals (Sweden)

Carlos Espaliú Berdud

2016-02-01

Full Text Available

La corriente política y social que en todo el mundo tiende a una mayor participación ciudadana en la gobernanza de las instituciones se materializó en el Derecho comunitario, entre otras cosas, en la inclusión de la figura de la iniciativa ciudadana, en virtud del Tratado de Lisboa, como un derecho más dentro del abanico del estatuto de la ciudadanía europea.  Los textos normativos comunitarios han previsto un importante papel para los medios digitales, tanto para facilitar la información como la participación de los ciudadanos. Habiendo transcurrido ya unos tres años desde el comienzo de la posibilidad de presentar iniciativas ciudadanas y habiéndose promovido ya en la práctica unas cincuenta, se posee ya perspectiva suficiente para valorar si aquellas expectativas eran fundadas o no. Tras el estudio pertinente, hemos podido corroborar cómo los medios digitales han resultado esenciales para alcanzar los fines para los que se pensó la iniciativa ciudadana, tanto en el sentido de servir de altavoz de las iniciativas promovidas, como en el de facilitar las recogidas de apoyos mediante páginas web. Incluso, parece que la práctica demuestra que hoy en día ya sería imposible, por falta de tiempo y medios de todo tipo, alcanzar las cifras de apoyo requeridas por las normas pertinentes sobre la iniciativa ciudadana, en los plazos previstos, si no es con ayuda de los medios digitales.

FPGA communications based on Gigabit Ethernet

International Nuclear Information System (INIS)

Doolittle, L.R.; Serrano, C.

2012-01-01

The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

Edición Especial: Las redes sociales digitales en la educación del siglo XXI

OpenAIRE

Pedagógicos, Ensayos

2017-01-01

Vivimos en una constante y acelerada innovación tecnológica, especialmente en el campo de las tecnologías de información y comunicación (TIC). Los recursos, servicios y espacios digitales se han ido transformando e incorporando en los últimos años a los estilos de vida de las personas, tanto para trabajar, comunicarse y producir conocimiento como consumir medios y contenido de entretenimiento, colaborar y socializar. En este sentido es innegable distinguir que las redes sociales digitales son...

Effektregnskab for projektet Digitales ll – Det svære valg

DEFF Research Database (Denmark)

Mark, Stine

Effektregnskabet for projektet Digitales ll – Det svære valg er udarbejdet af forskningscenteret INCEVIDA, Aalborg Universitet 2012. Rapporten er gennemført i et samarbejde mellem INCEVIDA, KulturarvNord og Bangsbo Museum. Effektregnskabet tager udgangspunkt i en model for oplevelsesøkonomisk...

Síntesis de copolímeros de PS-b-PMMA empleando polimerización radicalaria controlada

Directory of Open Access Journals (Sweden)

Vivina Hanazumi

2016-01-01

Full Text Available Se estudió la síntesis de copolímeros bloque de poli (estireno y poli (metil metacrilato (PS-b-PMMA empleando polimerización radicalaria por transferencia atómica (ATRP. Se realizaron distintos experimentos variando las relaciones molares de monómero, ligando e iniciador para determinar su influencia en la síntesis de copolímeros PS-b-PMMA con masas molares determinadas y estructura homogénea. Los polímeros sintetizados se caracterizaron químicamente por espectroscopia infrarroja con Transformada de Fourier (FTIR y cromatografía por exclusión de tamaños (SEC, empleando un detector de índice de refracción. Se obtuvieron los copolímeros bloque propuestos, con un buen control de su estructura macromolecular (Mw/Mn < 1,90.

Een Digitale bibliotheek van dateringen: de internationale doorwerking van een Nederlands initiatief

NARCIS (Netherlands)

Jansma, E.; Lanen, R.J. van

De Rijksdienst voor het Cultureel Erfgoed en Data Archiving and Networked Services (DANS) hebben met NWO-gelden een internationale digitale bibliotheek ontwikkeld voor ouderdomsbepalingen met behulp van houtonderzoek. Alle in Nederland ontwikkelde jaarringarchieven over het cultureel erfgoed

SEU mitigation exploratory tests in a ITER related FPGA

International Nuclear Information System (INIS)

Batista, Antonio J.N.; Leong, Carlos; Santos, Bruno; Fernandes, Ana; Ramos, Ana Rita; Santos, Joana P.; Marques, José G.; Teixeira, Isabel C.; Teixeira, João P.; Sousa, Jorge; Gonçalves, Bruno

2017-01-01

Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

SEU mitigation exploratory tests in a ITER related FPGA

Energy Technology Data Exchange (ETDEWEB)

Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

2017-05-15

Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

Competencias docentes digitales: propuesta de un perfil

OpenAIRE

Adriana Rangel Baca

2015-01-01

En este artículo se presenta la propuesta de un perfil de competencias docentes digitales y se describen las dimensiones, competencias e indicadores que lo componen. Se analizan distintas fuentes para determinar el conjunto de recursos a movilizar por los docentes en materia digital y se elabora una versión preliminar del perfil, la cual es puesta a consideración de un grupo de expertos en el uso de las Tecnologías de la Información y la Comunicación (TIC) para su validación. Los resultados m...

Burst-Mode Asynchronous Controllers on FPGA

Directory of Open Access Journals (Sweden)

Duarte L. Oliveira

2008-01-01

Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

Det digitale interaktive fjernsyn i hverdagslivet

DEFF Research Database (Denmark)

Bjørner, Thomas

2007-01-01

, at den digitale teknologi indpasses i eksisterende mønstre for tv-sening. Med baggrund i forsøgskanalen TV2/Nord-Digital, som var den første kanal der udsendte digitalt interaktivt tv i Danmark, vil denne artikel give nogle svar på, hvad der sker når digitalt tv (med de øgede interaktive muligheder......Digitaliseringen af tv-mediet er allerede i fuld gang, og der er i Danmark fastlagt en analog slukdato for public servicekanalerne i 2009. I forlængelse heraf leverer denne artikel en række indsigter i, hvordan den nye teknologi potentielt forandrer hverdagen, men samtidig er det også en pointe...

La evaluación de los recursos digitales para las humanidades

OpenAIRE

Galina Russell, Isabel

2016-01-01

Aunque ha habido un aumento en el reconocimiento de los proyectos de Humanidades Digitales (HD) como formas legítimas de investigación en Humanidades, su evaluación y valoración continúan siendo problemáticas. Una querella común para los humanistas

Competencias digitales y aprendizaje de ofimática en los estudiantes de una universidad privada - 2015

OpenAIRE

Neyra Herrera, Miguel Ángel

2015-01-01

El presente trabajo de investigación tuvo como problema general: ¿Qué relación que existe entre las competencias digitales y el aprendizaje de ofimática, en los estudiantes del I ciclo de ingeniería de sistemas e informática de la Universidad Alas Peruanas, 2015? y el objetivo general fue: Determinar si existe relación entre las competencias digitales y el aprendizaje de ofimática, en los estudiantes del I ciclo de ingeniería de sistemas e informática de la Universidad Alas ...

Conductas sociocomunicativas de los nativos digitales y los jóvenes en la web 2.0

OpenAIRE

García-García, F. (Francisco); Rosado-Millán, M.J. (María Jesús)

2012-01-01

La investigación se centra en el estudio de la percepción que los nativos digitales y los jóvenes tienen acerca de sus conductas y relaciones sociales en la Web 2.0. Se parte de la hipótesis de que la forma en que los adolescentes y jóvenes utilizan la red a través de los servicios y contenidos digitales abiertos, está transformando sus relacionales sociales en la medida en que son abiertas, activas, globales, inmediatas, y poco controlables por otros agentes sociales (familiares, educativos ...

Sistem national de management al resurselor digitale în stiinta si tehnologie, bazat pe structuri GRID - SINRED

CERN Document Server

Banciu, D

2007-01-01

Proiectului CEEX, SINRED ?i-a propus s? defineasc? ?i s? realizeze un sistem na?ional unitar de management al resurselor digitale în ?tiin?? ?i tehnologie bazat pe structuri GRID. Partenerii din consor?iu sunt: Universitatea din Bucure?ti; Universitatea Politehnica Bucure?ti; Universitatea Tehnic? din Cluj-Napoca; Institutul National de Informare ?i Documentar; Universitatea de Vest din Timi?oara. Problematica propus? spre rezolvare se circumscrie urm?toarelor obiective specifice: definirea ?i fundamentarea solu?iilor privind constituirea unei biblioteci digitale bazate pe re?eaua bibliotecilor universitare, publice ?i academic;definirea metodelor ?i metodologiilor de creare a unui sistem unitar la nivel na?ional în domeniul info-documentar bazat pe documente digital; analiza ?i testarea modalit??ilor de valorificare a tehnologiilor GRID în domeniul info-documentar;definirea unor proceduri de construire a bazelor de date digitale în acord cu normele ?i reglement?rile na?ionale ?i interna?ionale în domeni...

Digitale Editionen in den Altertumswissenschaften?

Directory of Open Access Journals (Sweden)

Friedrich Meins

2016-02-01

Full Text Available In his extensive study „Digitale Editionsformen“, Patrick Sahle gives a broad survey of the history of text-editions in general and the new possibilities as provided by digital technology. In the course of this, he passes harsh criticism on the „Critical edition“. In his eyes the „Critical edition“ is an outdated means, whose ontological and hence scientifical limitations are mainly a result of the technological limitations and ideological preconditions of the times when it came into being. This short paper argues that at least in the case of the „Critical edition“ as it is still the basis of Classical Studies both historical and linguistical, its own significance as an outcome of research cannot simply be depreciated against a general claim for „editions“ in a mere documentary meaning.

Generación de objetos de aprendizaje empleando un enfoque asistido

OpenAIRE

Menéndez Domínguez, Victor Hugo; Castellanos Bolaños, María Enriqueta; Zapata González, Alfredo; Prieto Méndez, Manuel Emilio:

2011-01-01

El etiquetado de un Objeto de Aprendizaje generalmente es una actividad extenuante y propensa a errores, lo cual afecta directamente la reutilización e interoperabilidad del recurso. En este trabajo se describe un modelo que genera Objetos de Aprendizaje a partir de recursos digitales existentes. El modelo emplea la similitud entre objetos, así como reglas inferidas del conocimiento existente, para proponer metadatos y de esta manera facilitar la descripción del recurso. El modelo ha sido imp...

FPGA Mezzanine Cards for CERN’s Accelerator Control System

CERN Document Server

Alvarez, P R; Lewis, J; Serrano, J; Wlostowski, T

2009-01-01

Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, PCI and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed...

A low-power wave union TDC implemented in FPGA

International Nuclear Information System (INIS)

Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

2011-01-01

A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

Digitale modeller af danske arkitekturværker

DEFF Research Database (Denmark)

Villaume, René; Rude Ørstrup, Finn

2001-01-01

Digitale modeller af dansk arkitektur åbner op for helt nye muligheder og faciliteter, fordi den enkelte bruger får et nyt redskab til at tilegne sig viden om dansk arkitektur med modeller, der kan anvendes til at iagtage og analysere både opførte og skitserede danske bygningsværker. Internettet ...... arbejder fra analyseopgaver i studiet. Der er store ressourcer og muligheder for opbygning af en samling, der systematisk kan udbygges og udvikles år for år. En helt ny dimension når man ønsker at indhente viden om dansk arkitektur og arkitekter....

FAS: Using FPGA to Accelerate and Secure SDN Software Switches

Directory of Open Access Journals (Sweden)

Wenwen Fu

2018-01-01

Full Text Available Software-Defined Networking (SDN promises the vision of more flexible and manageable networks but requires certain level of programmability in the data plane to accommodate different forwarding abstractions. SDN software switches running on commodity multicore platforms are programmable and are with low deployment cost. However, the performance of SDN software switches is not satisfactory due to the complex forwarding operations on packets. Moreover, this may hinder the performance of real-time security on software switch. In this paper, we analyze the forwarding procedure and identify the performance bottleneck of SDN software switches. An FPGA-based mechanism for accelerating and securing SDN switches, named FAS (FPGA-Accelerated SDN software switch, is proposed to take advantage of the reconfigurability and high-performance advantages of FPGA. FAS improves the performance as well as the capacity against malicious traffic attacks of SDN software switches by offloading some functional modules. We validate FAS on an FPGA-based network processing platform. Experiment results demonstrate that the forwarding rate of FAS can be 44% higher than the original SDN software switch. In addition, FAS provides new opportunity to enhance the security of SDN software switches by allowing the deployment of bump-in-the-wire security modules (such as packet detectors and filters in FPGA.

Rendimiento académico de los alumnos de secundaria que participan en el programa de aulas digitales

Directory of Open Access Journals (Sweden)

Jeckson Enrique Loza Arenas

2017-07-01

Full Text Available Este estudio analiza el impacto de las aulas digitales en el rendimiento académico en alumnos de educación secundaria de una institución educativa del sector público de Colombia. La metodología, de tipo cuantitativo, empleó un enfoque cuasi-experimental con dos tratamientos: un grupo experimental y uno de control, para establecer la diferencia del rendimiento académico de los alumnos participantes en el programa de aulas digitales con respecto a alumnos que no participan en el mismo. Los instrumentos empleados en este estudio fueron la aplicación de un pre-test y un post-test, una encuesta a los alumnos que integraron las aulas digitales y una encuesta al docente participante. Los resultados muestran que los alumnos participantes en el programa observan una mejora en el rendimiento académico en aspectos como la motivación, atención y participación con respecto a los alumnos que siguen un método de enseñanza tradicional; no ocurre igual en las calificaciones obtenidas ya que no se observa una mejora significativa en comparación con los alumnos no participantes. El uso de las aulas digitales mejora la disposición de los alumnos en el desarrollo de las clases, favoreciendo el trabajo colaborativo; facilitando la comprensión de los temas y dinamizando el desarrollo de las actividades de clase.

CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

CERN Document Server

Zhu, Yu

2010-01-01

Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

FPGA cluster for high-performance AO real-time control system

Science.gov (United States)

Geng, Deli; Goodsell, Stephen J.; Basden, Alastair G.; Dipper, Nigel A.; Myers, Richard M.; Saunter, Chris D.

2006-06-01

Whilst the high throughput and low latency requirements for the next generation AO real-time control systems have posed a significant challenge to von Neumann architecture processor systems, the Field Programmable Gate Array (FPGA) has emerged as a long term solution with high performance on throughput and excellent predictability on latency. Moreover, FPGA devices have highly capable programmable interfacing, which lead to more highly integrated system. Nevertheless, a single FPGA is still not enough: multiple FPGA devices need to be clustered to perform the required subaperture processing and the reconstruction computation. In an AO real-time control system, the memory bandwidth is often the bottleneck of the system, simply because a vast amount of supporting data, e.g. pixel calibration maps and the reconstruction matrix, need to be accessed within a short period. The cluster, as a general computing architecture, has excellent scalability in processing throughput, memory bandwidth, memory capacity, and communication bandwidth. Problems, such as task distribution, node communication, system verification, are discussed.

FPGA-based trigger system for the Fermilab SeaQuest experimentz

Energy Technology Data Exchange (ETDEWEB)

Shiu, Shiuan-Hal, E-mail: shshiu@phys.sinica.edu.tw [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Department of Physics, National Central University, No. 300, Jhongda Rd., Jhongli District, Taoyuan City 32001, Taiwan (China); Wu, Jinyuan [Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); McClellan, Randall Evan [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Gilman, Ron [Rutgers, The State University of New Jersey, 136 Frelinghuysen Rd., Piscataway, NJ 08854 (United States); Nakano, Kenichi [Department of Physics, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550 (Japan); Peng, Jen-Chieh [Department of Physics, University of Illinois at Urbana-Champaign, 1110 W. Green St., Urbana, IL 61801-3080 (United States); Wang, Su-Yin [Institute of Physics, Academia Sinica,128 Sec. 2, Academia Rd., Nankang, Taipei 11529, Taiwan (China); Fermi National Accelerator Laboratory, Kirk and Pine Streets, Batavia, IL 60510-5011 (United States); Department of Physics, National Kaohsiung Normal University, No. 62, Shenjhong Rd.,Yanchao Township, Kaohsiung County 824, Taiwan (China)

2015-12-01

The SeaQuest experiment (Fermilab E906) detects pairs of energetic μ{sup +} and μ{sup −} produced in 120 GeV/c proton–nucleon interactions in a high rate environment. The trigger system consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined against pre-determined trigger matrices to identify candidate muon tracks. Information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.

Development of an FPGA-based controller for safety critical application

International Nuclear Information System (INIS)

Xing, A.; De Grosbois, J.; Sklyar, V.; Archer, P.; Awwal, A.

2011-01-01

In implementing safety functions, Field Programmable Gate Arrays (FPGA) technology offers a distinct combination of benefits and advantages over microprocessor-based systems. FPGAs can be designed such that the final product is purely hardware, without any overhead runtime software, bringing the design closer to a conventional hardware-based solution. On the other hand, FPGAs can implement more complex safety logic that would generally require microprocessor-based safety systems. There are now qualified FPGA-based platforms available on the market with a credible use history in safety applications in nuclear power plants. Atomic Energy of Canada (AECL), in collaboration with RPC Radiy, has initiated a development program to define a vigorous FPGA engineering process suitable for implementing safety critical functions at the application development level. This paper provides an update on the FPGA development program along with the proposed design model using function block diagrams for the development of safety controllers in CANDU applications. (author)

Energy efficiency analysis and implementation of AES on an FPGA

Science.gov (United States)

Kenney, David

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

Spatial and color clustering on an FPGA-based computer system

Science.gov (United States)

Leeser, Miriam E.; Kitaryeva, Natalya V.; Crisman, Jill D.

1998-10-01

We are mapping an image clustering algorithm onto an FPGA- based computer system. Our approach processes raw pixel data in the red, green, blue color space and generates an output image where all pixels are assigned to classes. A class is a group of pixels with similar color and location. These classes are then used as the basis of further processing to generate tags. The tags, in turn, are used to generate queries for searching libraries of digital images. We run our image tagging approach on an FPGA-based computing machine. The image clustering algorithm is run on an FPGA board, and only the classified image is communicated to the host PC. Further processing is run on the host. Our experimental system consists of an Annapolis Wildforce board with four Xilinx XC4000 chips and a PCI connection to a host PC. Our implementation allows the raw image data to stay local to the FPGAs, and only the class image is communicated to the host PC. The classified pixels are then used to generate tags which can be used for searching a digital library. This approach allows us to parallelize the image processing on the FPGA board, and to minimize the data handled by the PC. FPGA platforms are ideally suited for this sort of initial processing of images. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures, keeping unnecessary data off the host processor. The result of our algorithm is a reduction by up to a factor of six in the number of bits required to represent each pixel. The output data is passed to the host PC, thus reducing the processing and memory resources needed compared to handling the raw data on the PC. The process of generating tags of images is simplified by first classifying pixels on an FPGA-based system, and digital library search is accelerated.

FPGA development board for applications in cosmic rays physics

International Nuclear Information System (INIS)

Angelov, Ivo; Damov, Krasimir; Dimitrova, Svetla

2013-01-01

The modern experiments in cosmic rays and particle physics are usually performed with large number of detectors and signal processing have to be done by complex electronics. The analog signals from the detectors are converted to digital (by discriminators or fast ADC) and connected to different type of logic implemented in FPGA (Field Programmable Gate Arrays). A FPGA development board based on Xilinx XC3S50AN was designed, assembled and tested. The board will be used for developing a modern registering controller (to replace the existing now) for the muon telescope in the University and can be used for other experiments in cosmic rays physics when fast digital pulses have to be processed. Keywords: FPGA, Spartan3A, muon telescope, cosmic rays variations

Het verbonden winkelgebied : hoe collectieve digitale marketing kan bijdragen aan een aantrekkelijke binnenstad

NARCIS (Netherlands)

Risselada, A.H.; Hagen, D.; Weltevreden, J.W.J.; Atzema, O.A.L.C.; Spierings, B.; Janssen, J.W.H.; Ghaus, F.

2018-01-01

Met het handboek ‘Het verbonden winkelgebied’ willen we inzichtelijk maken hoe collectieve digitale marketing kan bijdragen aan een aantrekkelijke binnenstad. Het handboek bevat naast onderzoeksresultaten ook een toolkit met een plan van aanpak voor collectieve marketing. Collectieven,

Digitale teknologier på det specialpædagogiske område

DEFF Research Database (Denmark)

Dupret, Katia

2015-01-01

Denne artikel handler om, hvordan forsøgsvis indførelse af digitale teknologier (tablets til kommunikation og kognitiv træning, virtuelle tavler og virtuel dagbog) på det specialpædagogiske område ændrer på grundlaget for brugernes livskvalitet, herunder autonomi og vilkår for social nærhed...

Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

Energy Technology Data Exchange (ETDEWEB)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir [Centre for Safety Infrastructure-Oriented Research and Analysis, Kharkov (Ukraine); SIORA Alexander [Research and Production Corporation Radiy, Kirovograd (Ukraine)

2011-08-15

Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper.

Innovative approach to implementation of FPGA-based NPP instrumentation and control systems

International Nuclear Information System (INIS)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Siora, Alexander

2011-01-01

Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper. (author)

Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

International Nuclear Information System (INIS)

Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; SIORA Alexander

2011-01-01

Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper

Il MUDE Piemonte - modello unico digitale per l’edilizia: un progetto organizzativo

Directory of Open Access Journals (Sweden)

Livio Mandrile

2012-12-01

Full Text Available Le tecnologie dell’informazione e della comunicazione consentono di affrontare la reingegnerizzazione dei processi amministrativi attraverso servizi informatici definiti “di cooperazione applicativa”, aprendo nuove prospettive per semplificare il rapporto fra cittadino e Pubbliche Amministrazioni e agevolare lo scambio di documenti e informazioni. Il MUDE Piemonte – modello unico digitale per l’edilizia - è un sistema informativo realizzato attraverso la collaborazione di tutti i livelli di governo del territorio regionale, che crea un archivio digitale delle pratiche edilizie presentate allo Sportello per l’Edilizia, utilizzando il mezzo telematico per l’interazione fra professionista e Pubblica Amministrazione e l’interscambio informativo fra le banche dati amministrative. Il MUDE Piemonte è un sistema che realizza un ambiente operativo di fruizione / aggiornamento della base di dati territoriali ed amministrativi ad uso di più soggetti ed enti e in costante evoluzione in ragione dell’apporto progettuale offerto da tutti gli attori coinvolti nei procedimenti autorizzativi edilizi.

FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

Directory of Open Access Journals (Sweden)

B. Lakshmi

2010-09-01

Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

Der ATLAS LVL2-Trigger mit FPGA-Prozessoren : Entwicklung, Aufbau und Funktionsnachweis des hybriden FPGA/CPU-basierten Prozessorsystems ATLANTIS

CERN Document Server

Singpiel, Holger

2000-01-01

This thesis describes the conception and implementation of the hybrid FPGA/CPU based processing system ATLANTIS as trigger processor for the proposed ATLAS experiment at CERN. CompactPCI provides the close coupling of a multi FPGA system and a standard CPU. The system is scalable in computing power and flexible in use due to its partitioning into dedicated FPGA boards for computation, I/O tasks and a private communication. Main focus of the research activities based on the usage of the ATLANTIS system are two areas in the second level trigger (LVL2). First, the acceleration of time critical B physics trigger algorithms is the major aim. The execution of the full scan TRT algorithm on ATLANTIS, which has been used as a demonstrator, results in a speedup of 5.6 compared to a standard CPU. Next, the ATLANTIS system is used as a hardware platform for research work in conjunction with the ATLAS readout systems. For further studies a permanent installation of the ATLANTIS system in the LVL2 application testbed is f...

Digital radiography - from principles to practical testing; Digitale Radiografie - von den Grundlagen zur Pruefpraxis

Energy Technology Data Exchange (ETDEWEB)

Mattis, A. [Siemens KWU, Erlangen (Germany)

1994-12-31

Digital radiography is broken down into two branches: storage luminescence technology and digitalization of existing films. The principles of both methods are presented in a short outline. The main advantages of this technology include decay-proof archiving that dispenses with film storage, computerized analysis of images using quantitative assessment standards, and improved display readability as compared to visual analysis. As a neutral authority, the Federal Institute for Materials Research and Testing (BAM) was charged with making an assessment of digital radiography by means of the approved ROC method. Based on an extensive collection of test pieces, the respective final result of the analysis was compared with the transmission images, i.e. digital data were compared with original films. (orig./MM) [Deutsch] Die Digitale Radiografie teilt sich in zwei Zweige - die Speicherleuchtstofftechnik sowie die Digitalisierung vorhandener Filme. Die Prinzipien beider Verfahren werden in einem kurzen Abriss dargestellt. Hauptvorteile dieser Technik sind die verfallsgesicherte Archivierung, die die Aufbewahrung der Filme ueberfluessig macht, die rechnergestuetzte Analyse der Aufnahmen unter Einsatz quantitativer Beurteilungsmassstaebe sowie die verbesserte Anzeigenerkennbarkeit gegenueber der visuellen Auswertung. Als neutrale Instanz wurde die Bundesanstalt fuer Materialforschung (BAM) beauftragt, mithilfe des anerkannten ROC-Verfahrens die Digitale Radiografie zu beurteilen. Basierend auf einer umfangreichen Sammlung von Teststuecken wurde das jeweilige Endergebnis der Auswertung der Durchstrahlungsaufnahmen verglichen d.h. digitale Daten mit Original-Filmen. (orig./MM)

UNE 71362: calidad de los materiales educativos digitales

OpenAIRE

Fernández-Pampillón Cesteros, Ana María

2017-01-01

La norma UNE 71362:2017 proporciona un modelo de base para definir y evaluar cuantitativa y cualitativamente la calidad de los materiales educativos digitales. En la elaboración de la norma han participado especialistas en enseñanza y aprendizaje, tecnologías, accesibilidad y gestión educativa pertenecientes a los tres sectores implicados en la creación y uso de estos materiales: académico, empresarial y de las administraciones públicas. El propósito de la norma es responder al reto y a la ne...

B-DCGAN:Evaluation of Binarized DCGAN for FPGA

OpenAIRE

Terada, Hideo; Shouno, Hayaru

2018-01-01

We are trying to implement deep neural networks in the edge computing environment for real-world applications such as the IoT(Internet of Things), the FinTech etc., for the purpose of utilizing the significant achievement of Deep Learning in recent years. Especially, we now focus algorithm implementation on FPGA, because FPGA is one of the promising devices for low-cost and low-power implementation of the edge computer. In this work, we introduce Binary-DCGAN(B-DCGAN) - Deep Convolutional GAN...

Photoelectric radar servo control system based on ARM+FPGA

Science.gov (United States)

Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

2016-01-01

In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

Directory of Open Access Journals (Sweden)

Tomyslav Sledevič

2013-05-01

Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

La industria musical colombiana en el mercado de los nuevos usos digitales

Directory of Open Access Journals (Sweden)

Juan Carlos Monroy Rodríguez

2006-01-01

Full Text Available Este artículo pone de presente una realidad que está transformando el mercado de la industria fonográfica, discográfica y cinematográfica. En efecto, hoy en día esta industria ha perdido competitividad en un mercado donde es más económico descargar archivos de música de Internet y fijarlos a través de quemadores en soportes físicos o fijarlos en formatos de comprensión digital (MP3, que comprar los soportes físicos que pagan derechos de autor. Con este panorama actual, el artículo propone alternativas para hacer viable un mercado legal de la música y el cine a través de usos digitales, con soluciones como el uso de ringtones y master tones como una de las posibilidades para poner obras musicales a disposición del público a través de usos digitales y así mismo buscar que los titulares de estos derechos puedan obtener un lucro. De otro lado, también se propone la opción de eliminar los soportes o medios físicos y hacer accesibles al público las obras a través de medios digitales, como un downloading oneroso, que requerirá la adopción de medidas tecnológicas que disuadan el downloading gratuito. Finalmente, el artículo rescata la labor que han realizado las sociedades de gestión colectiva en Colombia buscando poner acorde con el mercado a los autores y a los titulares de derechos conexos.

Asesinatos empleando relajantes musculares, opioides y otras drogas anestésicas

OpenAIRE

Martínez Hurtado, Eugenio; Gómez García, Ana María

2012-01-01

Los anestésicos, los opiáceos y los relajantes musculares pueden deprimir la respiración y otros procesos vitales hasta el extremo de producir la muerte si no se mantiene la ventilación. De modo que estos fármacos se han empleado para la eutanasia, el suicidio y las ejecuciones. Los criminales también han reparado en las posibilidades letales de los anestésicos, y durante los años recientes se han cometido homicidios empleando hipnóticos, anestésicos generales inhalados, opiáceos y relajantes...

Estimation of channel impulse response and FPGA simulation

Directory of Open Access Journals (Sweden)

YU Longjie

2015-02-01

Full Text Available Wideband code division multiple access (WCDMA is a 3G wireless communication network.The common pilot channel in downlink of WCDMA provides an effective method to estimate the channel impulse response.In this paper,universal software radio peripheral (USRP is utilized to sample and process WCDMA signal which is emitted by China Unicom base station.Firstly,the received signal is pre-processed with filtering and down-sampling.Secondly,fast algorithm of WCDMA cell search is fulfilled.Thirdly,frequency shift caused by USRP′s crystal oscillator is checked and compensated.Eventually,channel impulse response is estimated.In this paper,MATLAB is used to describe the above algorithm and field programmable gate array (FPGA is used to simulate algorithm.In the process of simulation,pipeline and IP core multiplexing are introduced.In the case of 32 MHz clock frequency,FPGA simulation time is 80.861 ms.Simulation results show that FPGA is able to estimate the channel impulse response quickly and accurately with less hardware resources.

An FPGA-based torus communication network

Energy Technology Data Exchange (ETDEWEB)

Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

2011-02-15

We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

An FPGA-based torus communication network

International Nuclear Information System (INIS)

Pivanti, Marcello; Schifano, Sebastiano Fabio; Simma, Hubert

2011-02-01

We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

FPGA based VME boards for Indus-2 timing control system

International Nuclear Information System (INIS)

Lulani, Nitin; Barpande, K.; Fatnani, P.; Sheth, Y.

2009-01-01

FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards. (author)

EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER

International Nuclear Information System (INIS)

HOFF, L.T.

2005-01-01

The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control

Uranus: a rapid prototyping tool for FPGA embedded computer vision

Science.gov (United States)

Rosales-Hernández, Victor; Castillo-Jimenez, Liz; Viveros-Velez, Gilberto; Zuñiga-Grajeda, Virgilio; Treviño Torres, Abel; Arias-Estrada, M.

2007-01-01

The starting point for all successful system development is the simulation. Performing high level simulation of a system can help to identify, insolate and fix design problems. This work presents Uranus, a software tool for simulation and evaluation of image processing algorithms with support to migrate them to an FPGA environment for algorithm acceleration and embedded processes purposes. The tool includes an integrated library of previous coded operators in software and provides the necessary support to read and display image sequences as well as video files. The user can use the previous compiled soft-operators in a high level process chain, and code his own operators. Additional to the prototyping tool, Uranus offers FPGA-based hardware architecture with the same organization as the software prototyping part. The hardware architecture contains a library of FPGA IP cores for image processing that are connected with a PowerPC based system. The Uranus environment is intended for rapid prototyping of machine vision and the migration to FPGA accelerator platform, and it is distributed for academic purposes.

A FPGA Approach in a Motorised Linear Stage Remote Controlled Experiment

Directory of Open Access Journals (Sweden)

Stamen Gadzhanov

2013-04-01

Full Text Available In recent years, an advanced motion control software for rapid development has been introduced by National Instruments, accompanied by innovative and improved FPGA-based hardware platforms. Compared to the well-known standard NI DAQ PCI/USB board solutions, this new approach offers robust stability in a deterministic real-time environment combined with the highest possible performance and re-configurability of the FPGA core. The NI Compact RIO (cRIO Real Time Controller utilises two distinctive interface modes of functionality: Scan and FPGA modes. This paper presents an application of a motion control flexible workbench based on the FPGA module, and analyses the advantages and disadvantages in comparison to another approach - the LabVIEW NI SoftMotion module run in scan interface mode. The workbench replicates real industrial applications and is very useful for experimentation with Brushless DC/ Permanent Magnet Synchronous motors and drives, and feedback devices.

Simultaneous Perturbation Particle Swarm Optimization and Its FPGA Implementation

OpenAIRE

Maeda, Yutaka; Matsushita, Naoto

2009-01-01

In this paper, we presented hardware implementation of the particle swarm optimization algorithm which is combination of the ordinary particle swarm optimization and the simultaneous perturbation method. FPGA is used to realize the system. This algorithm utilizes local information of objective function effectively without lack of advantage of the original particle swarm optimization. Moreover, the FPGA implementation gives higher operation speed effectively using parallelism of the particle s...

An FPGA-Based Electronic Cochlea

Directory of Open Access Journals (Sweden)

M. P. Leong

2003-06-01

Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

Uso de redes sociales digitales entre estudiantado universitario: Comunicación, socialización y colaboración

OpenAIRE

Marini Munguía, Verónica; Jácome Ávila, Nancy; López González, Rocío

2017-01-01

Este artículo describe resultados sobre el uso de redes sociales digitales en actividades de comunicación, socialización y colaboración. Es parte de una investigación en proceso, cuyo propósito es analizar el uso que le da el estudiantado universitario a los dispositivos digitales portátiles (DDP) –laptop, tableta y teléfono inteligente–. Para recolectar la información se aplicó un cuestionario diseñado en el marco del proyecto Brecha digital entre estudiantes y profesores de la Universidad V...

FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

Science.gov (United States)

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2012-07-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

Development of a multi-purpose logic module with the FPGA

International Nuclear Information System (INIS)

Nanbu, K.; Ishikawa, T.; Shimizu, H.

2008-01-01

We have developed a multi-purpose logic module (MPLM) with an FPGA. The internal circuit of this module can be modified easily with the FPGA. This kind of module enables trigger pulse processing for nuclear science. As a first step, the MPLM is used as an event tag generator in experiments with the FOREST detector system. (author)

New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project

CERN Document Server

Mendez, Julian Maxime; Caratelli, Alessandro; Leitao, Pedro Vicente

2018-01-01

The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

Integración de tabletas digitales como herramienta mediadora en procesos de aprendizaje

Directory of Open Access Journals (Sweden)

Claudia Sahagún Jiménez

2016-10-01

Full Text Available En este artículo presenta los resultados de un estudio sobre la manera en que las tabletas digitales se implementan como herramienta mediadora en educación básica para favorecer la construcción de aprendizajes significativos y el desarrollo de habilidades de trabajo colaborativo. La investigación fue diseñada metodológicamente como un estudio intrínseco de casos centrado en el trabajo de alumnos de cuarto grado de primaria del Centro Educativo Monarca, escuela particular situada en Zamora, Michoacán. Se utilizaron como instrumentos de recolección de datos la observación directa, el análisis de documentos y de aplicaciones en tabletas digitales, lo que permitió una reflexión sobre el proceso de construcción del conocimiento y sus desafíos y la intervención del maestro como gestor del ambiente de aprendizaje.   Los resultados muestran que el uso de tabletas, a través de sus aplicaciones, impulsa un acercamiento real al conocimiento y a la posibilidad de crear y compartir saberes, lo que amplía rutas de acceso a la información y permite la organización del conocimiento y la comunicación de lo que se aprende. El documento apunta a posibles líneas de acción, como explorar con mayor profundidad los contenidos digitales elaborados por los alumnos en relación con el desarrollo de habilidades de pensamiento crítico y creativo.  

Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

International Nuclear Information System (INIS)

Pappas, I; Kalenteridis, V; Vassiliadis, N; Pournara, H; Siozios, K; Koutroumpezis, G; Tatas, K; Nikolaidis, S; Siskos, S; Soudris, D J; Thanailakis, A

2005-01-01

A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 μm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools

Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

Energy Technology Data Exchange (ETDEWEB)

Pappas, I [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Kalenteridis, V [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Vassiliadis, N [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Pournara, H [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siozios, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Koutroumpezis, G [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Tatas, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Nikolaidis, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siskos, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Soudris, D J [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Thanailakis, A [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece)

2005-01-01

A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 {mu}m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

High Performance and Energy Efficient Traffic Light Controller Design Using FPGA

DEFF Research Database (Denmark)

Pandey, Sujeet; Shrivastav, Vivek Kumar; Sharma, Rashmi

2017-01-01

and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER......In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA...

Development of an FPGA-Based Motion Control IC for Caving Machine

Directory of Open Access Journals (Sweden)

Chiu-Keng Lai

2014-03-01

Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

Geschäftsmodelle für die digitale Langzeitarchivierung

OpenAIRE

Beucke, Daniel

2010-01-01

Forschungsdaten liegen zunehmend in digitaler Form vor bzw. werden ausschließlich digital produziert. Die Produktion ist zum einen sehr aufwendig und Kostenintensiv, zum anderen können sie Daten nicht ein zweites Mal erhoben werden. Daraus ergeben sich für Gedächtnisorganisationen wie Bibliotheken, Archive und Museen sowie auch für die Industrie bezogen auf die Möglichkeit der dauerhaften Verfügbarkeit dieser Daten neue Herausforderungen: Sie müssen Strategien und Geschäftsmodelle entwickeln,...

FPGA Implementation of Heart Rate Monitoring System.

Science.gov (United States)

Panigrahy, D; Rakshit, M; Sahu, P K

2016-03-01

This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

Design for an IO block array in a tile-based FPGA

International Nuclear Information System (INIS)

Ding Guangxin; Chen Lingdou; Liu Zhongli

2009-01-01

A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 μm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process. (semiconductor integrated circuits)

An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

International Nuclear Information System (INIS)

Jung, Sejin; Kim, Eui-Sub; Yoo, Junbeom; Kim, Jang-Yeol; Choi, Jong Gyun

2016-01-01

Highlights: • All direct/indirect COTS SW should be dedicated. • FPGA synthesis tools are important for the safety of new digital I&Cs. • No standards/reports are yet available to deal with the indirect SW – FPGA synthesis tools. • This paper proposes a new evaluation/acceptance process and criteria for indirect SW. - Abstract: FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

The integration of FPGA TDC inside White Rabbit node

International Nuclear Information System (INIS)

Li, H.; Xue, T.; Gong, G.; Li, J.

2017-01-01

White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

The integration of FPGA TDC inside White Rabbit node

Science.gov (United States)

Li, H.; Xue, T.; Gong, G.; Li, J.

2017-04-01

White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

Energy Technology Data Exchange (ETDEWEB)

Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

2017-04-20

Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

A natural-color mapping for single-band night-time image based on FPGA

Science.gov (United States)

Wang, Yilun; Qian, Yunsheng

2018-01-01

A natural-color mapping for single-band night-time image method based on FPGA can transmit the color of the reference image to single-band night-time image, which is consistent with human visual habits and can help observers identify the target. This paper introduces the processing of the natural-color mapping algorithm based on FPGA. Firstly, the image can be transformed based on histogram equalization, and the intensity features and standard deviation features of reference image are stored in SRAM. Then, the real-time digital images' intensity features and standard deviation features are calculated by FPGA. At last, FPGA completes the color mapping through matching pixels between images using the features in luminance channel.

Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

Energy Technology Data Exchange (ETDEWEB)

Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

2017-04-20

The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.

Implementación de certificados y firmas digitales para sistemas de información transaccionales en una empresa gubernamental

OpenAIRE

Espol; Palomeque Avila, John Guillermo

2015-01-01

Esta tesis trata de un ámbito teórico, conceptos de organización, tipos de organizaciones y sus procesos, significado de sistemas de información en los cuales se involucra la firma digital; y permite conocer detalles de certificados digitales, firmas digitales, el uso, los organismos relacionados y leyes. Contiene el análisis de procesos diseñados de una organización de gobierno para implementar el procedimiento de legalización de documentos mediante el uso de firma digital. Guayaquil ...

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

NARCIS (Netherlands)

Becher, Andreas; Bauer, Florian; Ziener, Daniel; Teich, Jürgen

2014-01-01

In this paper, we propose an approach for energy-aware FPGA-based query acceleration for databases on embedded devices. After the analysis of an incoming query, a query-specific hardware accelerator is generated on-the-fly and loaded on the FPGA for subsequent query execution using partial dynamic

Hardware and Software Integration in Project Development of Automated Controller System Using LABVIEW FPGA

International Nuclear Information System (INIS)

Mohd Khairulezwan Abd Manan; Mohd Sabri Minhat; Izhar Abu Hussin

2014-01-01

The Field-Programmable Gate Array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows user to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field, hence the name field-programmable. This project developed a control system using LabVIEW FPGA. LabVIEW FPGA is easier where it is programmed by using drag and drop icon. Then it will be integrated with the hardware input and output. (author)

Carry-chain propagation delay impacts on resolution of FPGA-based TDC

International Nuclear Information System (INIS)

Dong Lei; Yang Junfeng; Song Kezhu

2014-01-01

The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy. (authors)

Un approccio multidisciplinare per l’archeologia digitale

Directory of Open Access Journals (Sweden)

Rodolfo Maria Strollo

2017-12-01

Full Text Available Obiettivo del contributo è quello di indagare le potenzialità offerte da una metodologia multidisciplinare volta alla creazione di un database digitale facilmente interrogabile, sempre disponibile e scientificamente valido da impiegare per le diverse finalità legate al patrimonio culturale immobile (ricerca scientifica, interventi di manutenzione e restauro, valorizzazione culturale, promozione turistica. La banca dati è composta da modelli infografici elaborati con riferimento a rilievi tridimensionali affidabili dal punto di vista metrico e cromatico e rappresentativi di una realtà virtuale ‘aumentata’ delle informazioni storiche, iconografico-documentali e archivistiche riferite al bene. Caso studio su cui è stato sperimentato tale approccio metodologico è l’area archeologica di Tuscolo, sui Colli Albani a sud di Roma.

FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG

Science.gov (United States)

2014-06-01

is normalized to π. The proposed burst-mode architecture is written in VHDL and verified using Modelsim. The VHDL design is implemented on a Xilinx...Document Number: SET 2014-0043 412TW-PA-14298 FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG June 2014 Final Report Test...To) 9/11 -- 8/14 4. TITLE AND SUBTITLE FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG 5a. CONTRACT NUMBER: W900KK-11-C-0032 5b

An FPGA-based heterogeneous image fusion system design method

Science.gov (United States)

Song, Le; Lin, Yu-chi; Chen, Yan-hua; Zhao, Mei-rong

2011-08-01

Taking the advantages of FPGA's low cost and compact structure, an FPGA-based heterogeneous image fusion platform is established in this study. Altera's Cyclone IV series FPGA is adopted as the core processor of the platform, and the visible light CCD camera and infrared thermal imager are used as the image-capturing device in order to obtain dualchannel heterogeneous video images. Tailor-made image fusion algorithms such as gray-scale weighted averaging, maximum selection and minimum selection methods are analyzed and compared. VHDL language and the synchronous design method are utilized to perform a reliable RTL-level description. Altera's Quartus II 9.0 software is applied to simulate and implement the algorithm modules. The contrast experiments of various fusion algorithms show that, preferably image quality of the heterogeneous image fusion can be obtained on top of the proposed system. The applied range of the different fusion algorithms is also discussed.

Adaptive Hardware Cryptography Engine Based on FPGA

International Nuclear Information System (INIS)

Afify, M.A.A.

2011-01-01

In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

Museos virtuales: nuevos balcones digitales

Directory of Open Access Journals (Sweden)

Laura Regil Vargas

2006-01-01

Full Text Available Las tecnologías están provocando cambios en los museos. Por una parte, se transforma el espacio museístico; por otra, la tecnología —como herramienta— genera nuevas formas de creación artística y, en consecuencia, estas dos modificaciones repercuten en la formación de sus públicos. El vertiginoso desarrollo de las tecnologías digitales ha generado posturas extremas. Por un lado, desde el ágora donde se reúnen los apocalípticos, se habla ya del final de los museos; por el otro, entre los integrados, se especula con su evolución. Sabemos que la única conjura frente a posturas absolutas es la reflexión crítica. De ahí, mi invitación a analizar la transformación que las tecnologías han provocado en el continente y en el contenido.

Porting VIRTEX4 data acquisition design to SPARTAN6 FPGA

International Nuclear Information System (INIS)

Suetoe, J.; Hegyesi, G.

2012-01-01

Complete text of publication follows. The Atomki's Virtex 4 based 4 channel data acquisition card (LIR) card was used in many applications (miniPET-II, miniPET-III, data acquisition system for the multichannel plate installed at the ECR lab). The goal of the work was to improve the LIR using a higher performance FPGA (Spartan6 Trenz module). The Trenz module based system also supports ADC channels up to 16 channels. This work also implied the porting of the Virtex4 based VHDL code to Spartan 6. Further advantage of the proposed system, besides the improvement in the number of ADC channels, that the Spartan6 FPGA is able to run more complex digital signal processing algorithms than the Virtex 4 FPGA. Easy access to the control parameters (via serial interface or Ethernet), flexibility and high performance were considered during the development. SPARTAN6 FPGA based data acquisition provides more facilities than the VIRTEX4 based. SPARTAN6 is a newer generation of XILINX’s FPGAs, which excellent into the high-speed data acquisition. We ported the HDL code, which runs on LIR module (VIRTEX4 based), to the Trenz module (SPARTAN6 based). The main parts of the whole program code are the command line interpreter, GMII interface, DHCP process, ARP process and the data read out. Those parts were implemented by picoblaze embedded system. Figure 1 shows the command line interpreter process in the Hyper Terminal. The command line interpreter communicates with the PC via serial port. In addition, the AdamIOSetting software also use the serial communication, which was created to the VIRTEX FPGA based data collector. In the Wireshark network analyzer software we examined the DHCP and ARP process and using the AdamIOSettings software we tested the data read out from the flash memory of FPGA board. Figure 2 shows the AdamIOSettings program. Acknowledgements. This work was supported by the ENIAC CSI Project (No.120209).

FPGA hardware acceleration for high performance neutron transport computation based on agent methodology - 318

International Nuclear Information System (INIS)

Shanjie, Xiao; Tatjana, Jevremovic

2010-01-01

The accurate, detailed and 3D neutron transport analysis for Gen-IV reactors is still time-consuming regardless of advanced computational hardware available in developed countries. This paper introduces a new concept in addressing the computational time while persevering the detailed and accurate modeling; a specifically designed FPGA co-processor accelerates robust AGENT methodology for complex reactor geometries. For the first time this approach is applied to accelerate the neutronics analysis. The AGENT methodology solves neutron transport equation using the method of characteristics. The AGENT methodology performance was carefully analyzed before the hardware design based on the FPGA co-processor was adopted. The most time-consuming kernel part is then transplanted into the FPGA co-processor. The FPGA co-processor is designed with data flow-driven non von-Neumann architecture and has much higher efficiency than the conventional computer architecture. Details of the FPGA co-processor design are introduced and the design is benchmarked using two different examples. The advanced chip architecture helps the FPGA co-processor obtaining more than 20 times speed up with its working frequency much lower than the CPU frequency. (authors)

La seguridad en las competencias digitales de los millennials

Directory of Open Access Journals (Sweden)

Berenice Castillejos López

2016-10-01

Full Text Available Basados en un estudio mixto, en este documento valoramos la percepción del universitario sobre el tema de la seguridad en la Red, considerada una de las áreas de las competencias digitales. Apoyados en los descriptores del proyecto Ikanos del Instituto Vasco de Cualificaciones y Formación Profesional (2014, consideramos cuatro temas: la protección de los dispositivos, los datos personales, la salud y el uso sostenible de los recursos tecnológicos (INTEF, 2014. En la recolección de los datos, empleamos un cuestionario en línea y un guion de entrevista individual semiestructurado. Los resultados señalan que los millennials realizan prácticas básicas de seguridad, tales como el uso de antivirus, el manejo de contraseñas, ajustes en la configuración de las herramientas web, entre otros. Respecto a la identidad digital y la salud, es necesario promover el empleo adecuado de los datos personales, así como fomentar hábitos mediáticos saludables. En la protección del entorno natural identificamos la necesidad de crear conciencia sobre la adquisición de equipos, el manejo de los energéticos, el reciclaje y los desechos tecnológicos. Por último, este trabajo busca contribuir a la discusión sobre la seguridad y el consumo mediático dentro del marco de las competencias digitales.   

New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

Science.gov (United States)

Berg, Melanie D.; Label, Kenneth A.; Pellish, Jonathan

2016-01-01

It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

Multifunctional data acquisition system based on USB and FPGA

International Nuclear Information System (INIS)

Huang Tuchen; Gong Hui; Shao Beibei

2013-01-01

A multifunctional data acquisition system based on USB and FPGA was developed. The system has four analog inputs digitalized by fast ADC. Based on flexibility of FPGA, different functions can be implemented such as waveform sampling, pulse counting, multi-channel pulse height analysis, and charge division readout process. The hardware communicates with host PC via USB interface. The Labview based user soft ware initializes the hardware, configures the running parameters, reads and processes the data as well as displays the result online. (authors)

Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

Directory of Open Access Journals (Sweden)

He Chen

2011-12-01

Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Directory of Open Access Journals (Sweden)

Swapnil Mhaske

2017-01-01

Full Text Available We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

Demands on digital automation; Anforderungen an die Digitale Automation

Energy Technology Data Exchange (ETDEWEB)

Bieler, P.

1995-12-31

In chapter 12 of the anthology about building control the demands on digital automation are presented. The following aspects are discussed: variety of the companies` philosophies, demands of the customer/investor, demands of the use of buildings/rooms, the user, point of view of manufacturer of technical plants. (BWI) [Deutsch] Kapitel 12 des Sammelbandes ueber Building Control stellt die Anforderungen an die Digitale Automation vor. In diesem Zusammenhang wird auf folgende Themenbereiche eingegangen: Spektrum der Firmenphilosophien, Forderungen der Auftraggeber/Investoren, der Gebaeude-/Raumnutzung, der Betreiber sowie Sicht der Ersteller betriebstechnischer Anlagen. (BWI)

The RTE inversion on FPGA aboard the solar orbiter PHI instrument

Science.gov (United States)

Cobos Carrascosa, J. P.; Aparicio del Moral, B.; Ramos Mas, J. L.; Balaguer, M.; López Jiménez, A. C.; del Toro Iniesta, J. C.

2016-07-01

In this work we propose a multiprocessor architecture to reach high performance in floating point operations by using radiation tolerant FPGA devices, and under narrow time and power constraints. This architecture is used in the PHI instrument that carries out the scientific analysis aboard the ESA's Solar Orbiter mission. The proposed architecture, in a SIMD flavor, is aimed to be an accelerator within the Data Processing Unit (it is composed by a main Leon processor and two FPGAs) for carrying out the RTE inversion on board the spacecraft using a relatively slow FPGA device - Xilinx XQR4VSX55-. The proposed architecture squeezes the FPGA resources in order to reach the computational requirements and improves the ground-based system performance based on commercial CPUs regarding time and power consumption. In this work we demonstrate the feasibility of using this FPGA devices embedded in the SO/PHI instrument. With that goal in mind, we perform tests to evaluate the scientific results and to measure the processing time and power consumption for carrying out the RTE inversion.

Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

Science.gov (United States)

Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

2004-06-01

Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

Three-dimensional design methodologies for tree-based FPGA architecture

CERN Document Server

Pangracious, Vinod; Mehrez, Habib

2015-01-01

This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

Curso MOOC para fomentar el desarrollo de competencias digitales en estudiantes universitarios y autodidactas

Directory of Open Access Journals (Sweden)

Prince, Marcella Solange

2016-06-01

Full Text Available Este proyecto diseñó e implementó un MOOC, con el objetivo de encontrar respuesta a ¿Cómo el uso de los REA promueve el desarrollo de competencias básicas digitales en alumnos de nivel superior de tres universidades de México y una de Venezuela y de autodidactas ubicados en distintos países de América?, mediante el uso de la herramienta BlackBoard en su versión gratuita de CourseSites se elaboró el REA. La duración del curso fue de quince días, para diseminar en tres unidades de trabajo, el conocimiento respecto al desarrollo de habilidades digitales de búsqueda y filtración de información gráfica, elección y reutilización de imágenes respectando los derechos de autor; para la recolección de datos se realizaron entrevistas a estudiantes, profesores, un experto en REA y un experto en diseño y se analizaron datos de la bitácora, contrastándolos con la teoría. Los resultados muestran las dificultades que se pueden presentar en la implementación de un curso MOOC y que, el grado de apropiación de las herramientas tecnológicas, deviene de su utilización no solo socialmente sino de su utilización en forma sistemática en el proceso de actividades académicas o de aprendizaje autónomo, y en consecuencia el desarrollo de competencias digitales.

Profesores, aprendan de los nativos digitales. Propuesta de utilización de sistemas colaborativos en la educación pública

Directory of Open Access Journals (Sweden)

Daniel Fajardo

2012-03-01

Full Text Available El texto propone cuatro claves primordiales para el uso y desarrollo de las TIC en comunidades educativas. Promueve el uso de plataformas libres como apoyo a todas las materias de bachillerato, a partir de algunas experiencias exitosas en Chile. El autor recomienda que los docentes secundarios se muevan en los mismos espacios digitales que sus alumnos (nativos digitales para promover la cooperación y creatividad lúdica de la enseñanza.

Motion camera based on a custom vision sensor and an FPGA architecture

Science.gov (United States)

Arias-Estrada, Miguel

1998-09-01

A digital camera for custom focal plane arrays was developed. The camera allows the test and development of analog or mixed-mode arrays for focal plane processing. The camera is used with a custom sensor for motion detection to implement a motion computation system. The custom focal plane sensor detects moving edges at the pixel level using analog VLSI techniques. The sensor communicates motion events using the event-address protocol associated to a temporal reference. In a second stage, a coprocessing architecture based on a field programmable gate array (FPGA) computes the time-of-travel between adjacent pixels. The FPGA allows rapid prototyping and flexible architecture development. Furthermore, the FPGA interfaces the sensor to a compact PC computer which is used for high level control and data communication to the local network. The camera could be used in applications such as self-guided vehicles, mobile robotics and smart surveillance systems. The programmability of the FPGA allows the exploration of further signal processing like spatial edge detection or image segmentation tasks. The article details the motion algorithm, the sensor architecture, the use of the event- address protocol for velocity vector computation and the FPGA architecture used in the motion camera system.

Design and demonstration of a multitechnology FPGA for photonic information processing

Science.gov (United States)

Mal, Prosenjit; Hawk, Chris; Toshniwal, Kavita; Beyette, Fred R., Jr.

2003-11-01

We present here a novel architecture for a multi-technology field programmabler gate array (MT-FPGA). Implemented with a conventional CMOS VLSI technology the architecture is suitable for prototyping photonic information processing systems. We report here that this new FPGA architecture will enable the design of reconfigurable systems that incorporate technologies outside the traditional electronic domain.

Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

Directory of Open Access Journals (Sweden)

Bhattacharyya Shuvra S

2003-01-01

Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

FPGA Vision Data Architecture

Science.gov (United States)

Morfopoulos, Arin C.; Pham, Thang D.

2013-01-01

JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

Un acercamiento a los servicios de información y colecciones de las bibliotecas digitales en México

Directory of Open Access Journals (Sweden)

Brenda Cabral Vargas

2008-07-01

Full Text Available Realiza un acercamiento a los servicios y colecciones de las bibliotecas digitales en México. A travésde una investigación bibliográfica y de campo, se brinda un panorama sobre la trayectoria que siguióla sociedad de la información con el surgimiento y desarrollo de la electrónica en los servicios deinformación. Se hace un recorrido por los sitios Web de servicios digitales, a través de la recopilaciónde información en cuestionarios y encuestas a los encargados de dichos sitios. El trabajo está estructuradoen tres apartados: en el primero se lleva a cabo la conceptualización teórica sobre la bibliotecadigital (BD; en el segundo se muestran las diferencias del trabajo virtual, tanto para los usuarios comopara sus bibliotecarios, y las interacciones entre ambos y los recursos; y en el tercero se exhibe lasituación de algunos servicios digitales en México, con especial énfasis en el servicio de referencia, asícomo el impacto de éstos en la profesión.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

Millar James

2006-01-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

James Millar

2006-10-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

De la Amintiri de familie la Arhive digitale – Europeana Şi valenţele educative ale colecţiilor sale digitale

Directory of Open Access Journals (Sweden)

Cristina Ioana Roiu

2015-01-01

Full Text Available Digitizarea în masă a colecţiilor instituţiilor de tip GLAM (galerii, biblioteci, arhive si muzee pune la dispoziţia utilizatorilor uriaşe resurse informaţionale istorice, culturale, lingvistice în format digital care sunt tot mai mult folosite în procesul educaţional de pretutindeni. Articolul descrie experienţa si rezultatele derulării în Romania a unor activităţi şi proiecte educative non formale ce au vizat crearea Şi utilizarea arhivelor digitale Europeana 1914-1918 Şi Europeana 1989.

Empoderar a los profesores en su quehacer académico a través de certificaciones internacionales en competencias digitales

Directory of Open Access Journals (Sweden)

Arturo Amaya Amaya

2018-03-01

Full Text Available Este trabajo tiene el objetivo de evidenciar la importancia del desarrollo de las competencias digitales en los profesores universitarios para empoderar su quehacer académico con el apoyo de las tecnologías de la información y la comunicación. En este sentido, la Universidad Autónoma de Tamaulipas ha capacitado a 124 profesores de las diferentes facultades en el Programa de Certificación Internacional en Competencias Digitales (ICDL, de los cuales hasta el momento 76 han acreditado la certificación base-ICDL relacionada con conocimientos fundamentales de computación, conocimientos fundamentales de cursos en línea, procesador de textos y hojas de cálculo. Para ello, los profesores tuvieron que realizar pruebas de nivel, estudiar lecciones y desarrollar de manera autodidacta distintos tipos de ejercicios y prácticas hasta presentar su examen de certificación. Este trabajo da cuenta de sus avances en la adquisición de las competencias digitales y compara los resultados que alcanzaron al inicio y final de la certificación. Para que las universidades brinden respuesta a los desafíos de la educación superior del siglo XXI, estas han de invertir en la capacitación de sus profesores, quienes deben tener un perfil docente especializado, conocer métodos pedagógicos, ser expertos en contenidos y obtener certificaciones en competencias digitales reconocidas por organismos internacionales que garanticen su calidad.

Programovatelná hradlová pole - FPGA

Czech Academy of Sciences Publication Activity Database

Daněk, Martin

2006-01-01

Roč. 12, č. 2 (2006), s. 9-13 ISSN 1210-9592 R&D Projects: GA ČR GA102/04/2137 Institutional research plan: CEZ:AV0Z10750506 Keywords : FPGA architecture * physical design * design flow Subject RIV: JC - Computer Hardware ; Software

Implementation of a feed-forward artificial neural network in VHDL on FPGA

NARCIS (Netherlands)

Dondon, P.; Carvalho, J.; Gardere, R.; Lahalle, P.; Tsenov, G.; Mladenov, V.M.; Reljin, B.; Stankovic, S.

2014-01-01

Describing an Artificial Neural Network (ANN) using VHDL allows a further implementation of such a system on FPGA. Indeed, the principal point of using FPGA for ANNs is flexibility that gives it an advantage toward other systems like ASICS which are entirely dedicated to one unique architecture and

Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

International Nuclear Information System (INIS)

Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I.; Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A.

2010-10-01

The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY TM platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY TM platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY TM platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

Logic synthesis for FPGA-based finite state machines

CERN Document Server

Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

2016-01-01

This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

Diversity for security: case assessment for FPGA-based safety-critical systems

Directory of Open Access Journals (Sweden)

Kharchenko Vyacheslav

2016-01-01

Full Text Available Industrial safety critical instrumentation and control systems (I&Cs are facing more with information (in general and cyber, in particular security threats and attacks. The application of programmable logic, first of all, field programmable gate arrays (FPGA in critical systems causes specific safety deficits. Security assessment techniques for such systems are based on heuristic knowledges and the expert judgment. Main challenge is how to take into account features of FPGA technology for safety critical I&Cs including systems in which are applied diversity approach to minimize risks of common cause failure. Such systems are called multi-version (MV systems. The goal of the paper is in description of the technique and tool for case-based security assessment of MV FPGA-based I&Cs.

Repositorios institucionales digitales: Análisis comparativo entre SEDICI (Argentina y Kérwá (Costa Rica

Directory of Open Access Journals (Sweden)

Juan Carlos Sandí Delgado

2017-01-01

Full Text Available Este trabajo tiene como objetivo comparar dos repositorios institucionales digitales a nivel internacional para encontrar convergencias y divergencias con respecto al manejo y la operación de los datos, información y contenidos. Además, contribuye a ampliar el panorama y conocimiento con respecto a la importancia e impacto de los repositorios digitales en las Instituciones de Educación Superior (IES. Los repositorios en estudio corresponden al Servicio de Difusión de la Creación Intelectual (SEDICI, repositorio institucional central de la Universidad Nacional de La Plata (UNLP, Argentina y Kérwá, repositorio institucional principal de la Universidad de Costa Rica (UCR, Costa Rica. Para responder al objetivo de investigación, se desarrolló un análisis metodológico cualitativo. La información se recolectó a través de la aplicación de un cuestionario a las personas responsables de la gestión administrativa de ambos repositorios y una exploración bibliográfica de documentos en formato electrónico, como artículos publicados en congresos, revistas internacionales, entre otros. El análisis se realizó acorde a los siguientes criterios y características: representación de recursos, interoperabilidad, normalización, visibilidad, preservación, entre otros. Se concluyó que los repositorios institucionales digitales se han convertido en una tendencia de innovación para las IES, ya que utilizan y promueven herramientas tecnológicas para producir cambios significativos con respecto al uso y manejo de la información. Asimismo, los repositorios digitales analizados convergen en aspectos como: software, metadatos, números normalizados, representación de recursos, accesibilidad, identificador, derechos de autor, depósito de contenidos, buscadores y preservación. Divergen en interoperabilidad, proceso de digitalización, depósito remoto, visibilidad, licenciamiento y divulgación.

VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

Science.gov (United States)

Rais, Muhammad H.; Qasim, Syed M.

2010-06-01

In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

FPGA prototyping by Verilog examples Xilinx Spartan-3 version

CERN Document Server

Chu, Pong P

2008-01-01

FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a "learn by doing" approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

High-Performance Linear Algebra Processor using FPGA

National Research Council Canada - National Science Library

Johnson, J

2004-01-01

With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

New Developments in FPGA Devices: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

Science.gov (United States)

Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

2016-01-01

It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

FPGA Flash Memory High Speed Data Acquisition

Science.gov (United States)

Gonzalez, April

2013-01-01

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

On the speed of response of an FPGA-based shutdown system in CANDU nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

She Jingke, E-mail: jshe2@uwo.ca [Department of Electrical and Computer Engineering, The University of Western Ontario, London, Ontario, N6A 5B9 (Canada); Jiang Jin, E-mail: jjiang@eng.uwo.ca [Department of Electrical and Computer Engineering, The University of Western Ontario, London, Ontario, N6A 5B9 (Canada)

2011-06-15

Highlights: > Design and implementation of an FPGA-based CANDU SDS1. > Hardware-in-the-loop simulation for performance evaluation involved with an NPP simulator. > Comparison of the response time between FPGA-based trip channel and software-based PLC. - Abstract: Several issues in an FPGA based implementation of shutdown systems in CANDU nuclear power plants have been investigated in this paper. A particular attention is on the response time of an FPGA implementation of safety shutdown systems in comparison with operating system based software solutions as in existing CANDU plants. The trip decision logic under 'steam generator (SG) level low' condition has been examined in detail. The design and implementation of this logic on an FPGA platform have been carried out. The functionality tests are performed in a hardware-in-the-loop (HIL) environment by connecting the FPGA based system to an NPP simulator, and replacing one channel of Shutdown System Number 1 (SDS1) in the simulator by the FPGA implementation. The response time of the designed system is also measured through multiple tests under different conditions, and statistical data analysis has been performed. The results of the response time tests are compared against those of a software-based implementation of the same trip logic.

Test results of an ITER relevant FPGA when irradiated with neutrons

Energy Technology Data Exchange (ETDEWEB)

Batista, Antonio J. N.; Santos, Bruno; Fernandes, Ana; Goncalves, Bruno [Instituto de Plasmas e Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Leong, Carlos; Teixeira, Joao P. [Instituto de Engenharia de Sistemas e Computadores - Investigacao e Desenvolvimento, 1000-029 Lisboa, (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, Jose G. [Centro de Ciencias e Tecnologias Nucleares, Instituto Superior Tecnico, Universidade de Lisboa, 2695-066 Bobadela, (Portugal)

2015-07-01

The data acquisition and control instrumentation cubicles room of the ITER tokamak will be irradiated with neutrons during the fusion reactor operation. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of I and C products - Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), functional data stored in dedicated Block RAM (BRAM) and functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons causes soft errors, unintended changes (bit-flips) to the values stored in state elements of the FPGA. The SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA configuration memory. Novel SEU sensors with Error Correction Code (ECC) detect and repair the BRAM memories. Proper management of SEU can increase reliability and availability of control instrumentation hardware for nuclear applications. The results of the tests performed using the SEM controller and the BRAM SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU errors in the configuration and BRAM memories. (authors)

Moessbauer spectrometric data acquisition based on FPGA

International Nuclear Information System (INIS)

Zhang Yuan; Li Shimin; Chen Nan; Zhu Jingbo; Xia Yuanfu

2008-01-01

FPGA(Field Programmable Gate Array) is a programmable device with strong logical function and timing control ability. It is extremely potent in acquiring and processing timing signals. By replacing the traditional used SCM (Single-Chip Microcomputer) with FPGA, counting speed of Moessbauer spectrometric data acquisition can be improved markedly with significantly decreased size of the spectrometer. The counter, RAM and RS-232 communication of the module are developed on Altera Cyclone series chip EP1C6T144C8 with Quartus II. EP1C6T144C8 has 5980 logical units accompanied by 92160 bits of memory space. It is so powerful that all needs in data acquisition of the Moessbauer spectrometer can be perfectly satisfied while allowing modifications in functions and parameters. (authors)

The Codice digitale degli archivi veronesi. A research instrument

Directory of Open Access Journals (Sweden)

Andrea Brugnoli

2014-04-01

Full Text Available The Codice digitale degli archivi veronesi (Verona’s archives digital code ‹http://cdavr.dtesis.univr.it› makes available online the digital reproductions of the documents produced by corporate bodies and family of Verona between the eighth and twelfth century. The framework of the site reflects the current organisation of the archives. A brief description of the circumstances around the creation of each archive, the corporate body or individual responsible for it and its structure is provided. Each archival unit is identified by its key elements: chronological date, name and qualification of the notary, original/copy, main editions.

Digitale Transformation, aber wie? - Von der Spielwiese zur Umsetzungsplanung

Science.gov (United States)

Kaiser, Thomas

Es besteht wohl kaum Anlass zur Annahme, dass die seit Jahrzehnten etablierten Markt- und Technologiestrukturen der Energiewirtschaft sich nicht in einem radikalen Ablöseprozess mit Gewinnern und Verlierern befinden. Aber Vorsicht - vordergründig bereits verloren erscheinende Geschäftsmodelle erfahren im Zuge der Digitalisierung einerseits noch intensiveren Wettbewerbsdruck, können aber andererseits von diesem "technologischen Jungbrunnen" profitieren, um verlorenes Terrain zurückzugewinnen. Im folgenden Kapitel wird ein Managementzyklus aufgezeigt, der in Anlehnung an die bereits erfolgreiche Implementierung digitaler R/Evolutionen anderer Branchen aufzeigt, wie die Geschäftsleitung systematisch kostenbewusst und zielorientiert die Digitalisierung umsetzen kann.

Development, verification and validation of an FPGA-based core heat removal protection system for a PWR

Energy Technology Data Exchange (ETDEWEB)

Wu, Yichun, E-mail: ycwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China); Shui, Xuanxuan, E-mail: 807001564@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Cai, Yuanfeng, E-mail: 1056303902@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Zhou, Junyi, E-mail: 1032133755@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Wu, Zhiqiang, E-mail: npic_wu@126.com [State Key Laboratory of Reactor System Design Technology, Nuclear Power Institute of China, Chengdu 610041 (China); Zheng, Jianxiang, E-mail: zwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China)

2016-05-15

Highlights: • An example on life cycle development process and V&V on FPGA-based I&C is presented. • Software standards and guidelines are used in FPGA-based NPP I&C system logic V&V. • Diversified FPGA design and verification languages and tools are utilized. • An NPP operation principle simulator is used to simulate operation scenarios. - Abstract: To reach high confidence and ensure reliability of nuclear FPGA-based safety system, life cycle processes of discipline specification and implementation of design as well as regulations verification and validation (V&V) are needed. A specific example on how to conduct life cycle development process and V&V on FPGA-based core heat removal (CHR) protection system for CPR1000 pressure water reactor (PWR) is presented in this paper. Using the existing standards and guidelines for life cycle development and V&V, a simplified FPGA-based CHR protection system for PWR has been designed, implemented, verified and validated. Diversified verification and simulation languages and tools are used by the independent design team and the V&V team. In the system acceptance testing V&V phase, a CPR1000 NPP operation principle simulator (OPS) model is utilized to simulate normal and abnormal operation scenarios, and provide input data to the under-test FPGA-based CHR protection system and a verified C code CHR function module. The evaluation results are applied to validate the under-test FPGA-based CHR protection system. The OPS model operation outputs also provide reasonable references for the tests. Using an OPS model in the system acceptance testing V&V is cost-effective and high-efficient. A dedicated OPS, as a commercial-off-the-shelf (COTS) item, would contribute as an important tool in the V&V process of NPP I&C systems, including FPGA-based and microprocessor-based systems.

Competencias digitales en docentes de la Carrera de Enfermería de la Universidad Técnica de Ambato

Directory of Open Access Journals (Sweden)

Diana Nancy Martínez García

2017-03-01

Full Text Available Introducción: El aprendizaje electrónico e-learning, incorporó la conectividad a través del Internet acercando el conocimiento y el desarrollo académico por medio de los espacios de aprendizaje virtuales. Del tradicional e-learning a la masificación de los cursos abiertos Massive Open Online Course, se ha revolucionado el mundo educativo en función de la oferta de formación académica abierta y de calidad. Objetivo: Evaluar las competencias digitales de los docentes de la Carrera de Enfermería de la Universidad Técnica de Ambato. Métodos: Se realizó un estudio observacional, descriptivo y retrospectivo con el objetivo de conocer las competencias digitales de los docentes de la Carrera de Enfermería. La población estuvo formada por 30 docentes, a los que se les aplicó un instrumento de evaluación para conocer las competencias digitales que poseían. Resultados: Los docentes estuvieron bien familiarizados con el uso de la Internet (n=19; 63%, y el uso de software educativos (n=8; 27%. El 37% de los docentes utilizó el Internet para el desarrollo de sus clases, el 33% lo utilizó a menudo, mientras que el 2,7% lo utilizó en determinadas ocasiones. Conclusiones: Las competencias digitales de los docentes estuvieron en un nivel medio de pericia, los docentes conocieron y manejaron las herramientas informáticas que integraron a su práctica docente, no obstante se evidenció la necesidad de acompañamiento por parte de personal especializado en el área de tecnologías de la información y la comunicación.

Sugli studi medievali e il mutamento digitale On the medieval studies and the digital change

Directory of Open Access Journals (Sweden)

Redazione Reti Medievali (a cura di

2004-12-01

Full Text Available

La sezione raccoglie tre brevi comunicazioni, tenute nell’ambito del seminario Medium-Evo. Gli studi medievali e il mutamento digitale (Firenze, 2001 e dedicate rispettivamente ai periodici e alle forme di comunicazione del sapere (Giorgio Chittolini, al problema del reperimento delle risorse e della repertoriazione delle fonti (Paolo Delogu, ai contraccolpi dell’uso del mezzo informatico sulla scrittura della storia (Giuseppe Sergi.

This section includes three short papers - presented at the seminar on Medium-Evo. Gli studi medievali e il mutamento digitale (Firenze, 2001 (Medium-Evo. Medieval studies and the digital change - which are respectively focused on periodicals, different types of learning communication (Giorgio Chittolini, problems linked to document searching and filing (Paolo Delogu, backlashes  coming from the use of computer in writing history (Giuseppe Sergi.

Optimization on fixed low latency implementation of the GBT core in FPGA

Science.gov (United States)

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

2017-07-01

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Optimization on fixed low latency implementation of the GBT core in FPGA

International Nuclear Information System (INIS)

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

2017-01-01

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

A configurable FPGA FEC unit for Tb/s optical communication

DEFF Research Database (Denmark)

Andersen, Jakob Dahl; Larsen, Knud J.; Bering Bøgh, Christian

2017-01-01

Decoding of FEC (forward error correction) for optical communication beyond 1 Tb/s is investigated. A configurable single FPGA solution is presented having configurations supporting bit-rates in the range from 40 Gb/s to 1.6 Tb/s. The design allows for trade-offs of bit-rate, footprint, and latency...... within the resources of the FPGA. A proof-of-concept lab experiment at 40 Gb/s was conducted and pre-FEC — post-FEC performance validated with simulated results....

RADIOMETRIC CALIBRATION OF MARS HiRISE HIGH RESOLUTION IMAGERY BASED ON FPGA

Directory of Open Access Journals (Sweden)

Y. Hou

2016-06-01

Full Text Available Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

Application-specific mesh-based heterogeneous FPGA architectures

CERN Document Server

Parvez, Husain

2011-01-01

This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

Energy Technology Data Exchange (ETDEWEB)

Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I. [Research and Production Corporation Radiy, 29 Geroev Stalingrada Str., Kirovograd 25006 (Ukraine); Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A., E-mail: marketing@radiy.co [Center for Safety Infrastructure-Oriented Research and Analysis, 37 Astronomicheskaya Str., Kharkiv 61085 (Ukraine)

2010-10-15

The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY{sup TM} platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY{sup TM} platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY{sup TM} platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

International Nuclear Information System (INIS)

Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

2016-01-01

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

Using FPGA coprocessor for ATLAS level 2 trigger application

International Nuclear Information System (INIS)

Khomich, Andrei; Hinkelbein, Christian; Kugel, Andreas; Maenner, Reinhard; Mueller, Matthias

2006-01-01

Tracking has a central role in the event selection for the High-Level Triggers of ATLAS. It is particularly important to have fast tracking algorithms in the trigger system. This paper investigates the feasibility of using FPGA coprocessor for speeding up of the TRT LUT algorithm-one of the tracking algorithms for second level trigger for ATLAS experiment (CERN). Two realisations of the same algorithm have been compared: one in C++ and a hybrid C++/VHDL implementation. Using a FPGA coprocessor gives an increase of speed by a factor of two compared to a CPU-only implementation

Exposiciones digitales y reutilización: aplicación del software libre Omeka para la publicación estructurada

Directory of Open Access Journals (Sweden)

Saorín Pérez, Tomás

2011-06-01

Full Text Available El artículo contextualiza las exposiciones digitales en el marco de la difusión digital de las colecciones de museos y patrimonio, presentando las funcionalidades del software libre Omeka para la gestión especializadas de este tipo de contenidos, a través de una combinación ágil de gestor de colecciones digitales vinculado a generador de exposiciones. El sistema usa metadatos normalizados y aplica Oai/PMH, de forma que permite la reutilización y distribución de contenidos en la web. También se analizan las ventajes del software como servicio (SaaS para el caso de Omeka Net.

Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

DEFF Research Database (Denmark)

Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

2012-01-01

This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

A single FPGA-based portable ultrasound imaging system for point-of-care applications.

Science.gov (United States)

Kim, Gi-Duck; Yoon, Changhan; Kye, Sang-Bum; Lee, Youngbae; Kang, Jeeun; Yoo, Yangmo; Song, Tai-kyong

2012-07-01

We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

High-definition video display based on the FPGA and THS8200

Science.gov (United States)

Qian, Jia; Sui, Xiubao

2014-11-01

This paper presents a high-definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data-storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high-definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I2C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high-definition video display, which conforms to the input requirements of the new high-definition display devices.

Guide to FPGA Implementation of Arithmetic Functions

CERN Document Server

Deschamps, Jean-Pierre; Cantó, Enrique

2012-01-01

This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components.  The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption.  This is not a book on algorithms.  It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others.  Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

An Improved Rotary Interpolation Based on FPGA

Directory of Open Access Journals (Sweden)

Mingyu Gao

2014-08-01

Full Text Available This paper presents an improved rotary interpolation algorithm, which consists of a standard curve interpolation module and a rotary process module. Compared to the conventional rotary interpolation algorithms, the proposed rotary interpolation algorithm is simpler and more efficient. The proposed algorithm was realized on a FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe, which uses rotary ellipse and rotary parabolic as an example. According to the theoretical analysis and practical process validation, the algorithm has the following advantages: firstly, less arithmetic items is conducive for interpolation operation; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

FPGA-based digital convolution for wireless applications

CERN Document Server

Guan, Lei

2017-01-01

This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

Note: Design of FPGA based system identification module with application to atomic force microscopy

Science.gov (United States)

Ghosal, Sayan; Pradhan, Sourav; Salapaka, Murti

2018-05-01

The science of system identification is widely utilized in modeling input-output relationships of diverse systems. In this article, we report field programmable gate array (FPGA) based implementation of a real-time system identification algorithm which employs forgetting factors and bias compensation techniques. The FPGA module is employed to estimate the mechanical properties of surfaces of materials at the nano-scale with an atomic force microscope (AFM). The FPGA module is user friendly which can be interfaced with commercially available AFMs. Extensive simulation and experimental results validate the design.

Deporte Salud y Vida para oyentes de radio Familia 96.9 empleando pausa activa

OpenAIRE

Martínez Sarmiento, Marcia Fabiola

2011-01-01

Deporte Salud y Vida para oyentes de radio Familia 96.9 empleando pausa activa, un programa de radio que promueve a la práctica de actividad física, que permita contrarrestar las grandes escalas de sedentarismo en nuestra ciudad, gracias al apoyo de este medio de comunicación se implementó la Pausa activa para oyentes de Radio Familia, especialmente amas de casa que fluctúan desde los 20 hasta 75 años. El proyecto tiene también el objetivo de la ejercitación mediante la Pausa Activa dentro...

Fuzzy Controller Design Using FPGA for Photovoltaic Maximum Power Point Tracking

OpenAIRE

Basil M Hamed; Mohammed S. El-Moghany

2012-01-01

The cell has optimum operating point to be able to get maximum power. To obtain Maximum Power from photovoltaic array, photovoltaic power system usually requires Maximum Power Point Tracking (MPPT) controller. This paper provides a small power photovoltaic control system based on fuzzy control with FPGA technology design and implementation for MPPT. The system composed of photovoltaic module, buck converter and the fuzzy logic controller implemented on FPGA for controlling on/off time of MOSF...

FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool

Directory of Open Access Journals (Sweden)

Mohammed Bahoura

2016-02-01

Full Text Available In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA using Xilinx System Generator (XSG and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls.

A scalable FPGA-based digitizing platform for radiation data acquisition

International Nuclear Information System (INIS)

Schiffer, Randolph T.; Flaska, Marek; Pozzi, Sara A.; Carney, Sean; Wentzloff, David D.

2011-01-01

Regulating the proliferation of nuclear materials has become an important issue in our society. In order to detect the radiation given off by nuclear materials, systems implementing detectors connected to data processing modules have been developed. We have implemented a scalable, portable detection platform with a data processing module about the size of an external DVD drive. The data processing component of our system utilizes real-time data handling and has the potential for growth and behavior modifications through custom FPGA code editing. The size of our system is dynamic, so additional input channels can be implemented if necessary. This paper presents a scalable, portable detection system capable of transmitting streaming data from its inputs to a PC or laptop. The system also performs tail/total integral pulse shape discrimination (PSD) in real time on the FPGA to filter the data and selectively transmit pulses to a PC. The data arrives at the inputs of the data capturing module, is processed in real time by the onboard FPGA and is then transferred to a PC or laptop via a PCIe cord in discrete packets. The maximum transfer rate from the FPGA to the PC is 2000 MB/s. The Detection for Nuclear Non-Proliferation Group at University of Michigan will use the detection platform to achieve pre-processing of radiation data in real time. Such pre-processing includes PSD, pulse height distributions and particle times of arrival.

Economical Implementation of a Filter Engine in an FPGA

Science.gov (United States)

Kowalski, James E.

2009-01-01

A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be

An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

Directory of Open Access Journals (Sweden)

Lai Chiu-Keng

2016-01-01

Full Text Available A Field Programmable Gate Array based system is a great hardware platform to support the implementation of hardware controllers such as PID controller and fuzzy controller. It is also programmed as hardware accelerator to speed up the mathematic calculation and greatly enhance the performance as applied to motor drive and motion control. Furthermore, the open structure of FPGA-based system is suitable for those designs with the ability of parallel processing or soft code processor embedded. In this paper, we apply the FPGA to a multi-axis velocity controller design. The developed system integrated three functions inside the FPGA chip, which are respectively the stepping motor drive, the multi-axis motion controller and the motion planning. Furthermore, an embedded controller with a soft code processor compatible to 8051 micro-control unit (MCU is built to handle the data transfer between the FPGA board and host PC. The MCU is also used to initialize the motion control and run the interpolator. The designed system is practically applied to a XYZ motion platform which is driven by stepping motors to verify its performance.

Design and FPGA Implementation of a new hyperchaotic system

International Nuclear Information System (INIS)

Wang Guangyi; Bao Xulei; Wang Zhonglin

2008-01-01

In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic Nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array (FPGA) technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup. (general)

Diseño de una estrategia para el análisis didáctico de contenidos digitales en anatomía osteo-muscular

OpenAIRE

Gamboa Latorre, Lina Fernanda

2014-01-01

Este artículo propone una estrategia fundamentada teóricamente en el aprendizaje significativo para orientar el análisis didáctico de los contenidos digitales en anatomía osteo-muscular, asignatura que es requisito curricular en las carreras de la salud. Para el estudio de la asignatura, docentes y estudiantes utilizan recursos tradicionales y emergentes. Parte de los recursos emergentes son los contenidos digitales, modalidades de tecnologías de la información y comunicaciones (TIC) disponib...

Het digitale sport medisch dossier: zucht of zegen? [Digital Sport Medical Record: Sigh or a blessing?

NARCIS (Netherlands)

Stege, J.P.; Fleuren, M.A.H.; Knaap, E.T.W. van der; Stubbe, J.H.

2013-01-01

Sinds 2004 zijn er verschillende initiatieven ontplooid rondom de ontwikkeling van een digitaal Sport Medisch Dossier (SMD). Uit gesprekken met de Vereniging voor Sportgeneeskunde (VSG) blijkt dat er vooral problemen worden gesignaleerd met de ingebruikname van het digitale SMD. In het voorjaar van

Multichannel analyzer embedded in FPGA; Analizador multicanal embebido en FPGA

Energy Technology Data Exchange (ETDEWEB)

Garcia D, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98060 Zacatecas, Zac. (Mexico); Ordaz G, O. O. [Universidad de Cordoba, Departamento de Arquitectura de Computadores, Electronica y Tecnologia Electronica, Campus de Rabanales, Ctra. N-IVa Km 396, 14071 Cordoba (Spain); Bravo M, I., E-mail: angelogarciad@hotmail.com [Universidad de Alcala de Henares, Departamento de Electronica, Campus Universitario, Carretera Madrid-Barcelona Km 33.600, 28801 Alcala de Henares, Madrid (Spain)

2017-10-15

Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

La construcción colaborativa de proyectos como metodología para adquirir competencias digitales

Directory of Open Access Journals (Sweden)

María Pérez Mateo

2014-01-01

Full Text Available Actualmente presenciamos una etapa de importantes cambios como consecuencia de la emergencia de las tecnologías de la información y la comunicación (TIC. La educación superior ejerce un papel clave para ayudar a los estudiantes a adquirir las competencias que les permitan desenvolverse en los entornos académico y profesional. Entre éstas, las vinculadas a las TIC y los procesos de colaboración se consideran claves. La finalidad del presente estudio es analizar la percepción de los estudiantes a fin de evidenciar cómo la construcción colaborativa de un proyecto digital facilita la adquisición de las competencias digitales. Para ello, se aborda el planteamiento metodológico de la asignatura «Competencias TIC» de la Universitat Oberta de Catalunya, la cual se desarrolla a través de un proyecto colaborativo en red organizado en cuatro fases: inicio, estructuración, desarrollo y conclusión y cierre. Mediante una investigación evaluativa se triangulan datos de naturaleza cuantitativa y cualitativa provenientes de un cuestionario. Los resultados muestran la evolución en la propuesta metodológica de la asignatura a la vez que ponen de manifiesto cómo el proyecto digital en equipo facilita la adquisición de las competencias digitales, destacando concretamente las vinculadas al trabajo en equipo en red y la actitud digital. Las conclusiones refuerzan la importancia de los procesos CSCL, la necesidad de trabajar propuestas pedagógicas para la adquisición de competencias digitales.

Inclusión digital de los estudiantes adultos que acceden a la universidad: análisis de sus actitudes y competencias digitales

OpenAIRE

M. Teresa PADILLA-CARMONA; Magdalena SUÁREZ-ORTEGA; María Fe SÁNCHEZ-GARCÍA

2016-01-01

Esta investigación se propone identificar las actitudes y competencias de los estudiantes adultos en relación con el uso de las TIC, con especial atención al uso de plataformas digitales de aprendizaje y redes sociales (Web 2.0). Asimismo, evalúa la incidencia de algunas variables sociodemográficas (género y edad) en el uso estas herramientas y en la autopercepción de los estudiantes sobre sus competencias digitales. Se ha realizado un estudio tipo encuesta con una muestra de 3...

Når mobilen tager magten - nærvær i den digitale tidsalter

DEFF Research Database (Denmark)

Fenger, Morten Munthe

at se ind i en skærm? "Når mobilen tager magten" beskriver, hvordan den digitale teknologi og sociale medier såsom Facebook, Instagram og Snapchat går direkte ind og udnytter menneskets instikter, og tilfredsstiller vores behov hurtigere end vores forstand og vilje kan følge med og sige fra. "Når...

Rezension: Digitale Körperinnenwelten. Endoskopische 3D-Animationen zwischen Medien und Populärkultur. von Sven Stollfuß

Directory of Open Access Journals (Sweden)

Petra Missomelius

2015-09-01

Full Text Available Sven Stollfuß’ Studie über die digitale Darstellung körperlicher Innenwelten bewegt sich zwischen medienwissenschaftlicher Theoriebildung, Bildtheorie und Science and Technology Studies. Petra Missomelius hat rezensiert ...

High performance parallel backprojection on FPGA

Energy Technology Data Exchange (ETDEWEB)

Pfanner, Florian; Knaup, Michael; Kachelriess, Marc [Erlangen-Nuernberg Univ., Erlangen (Germany). Inst. of Medical Physics (IMP)

2011-07-01

Reconstruction of tomographic images, i.e., images from a Computed Tomography scanner, is a very time consuming issue. The most calculation power is needed for the backprojection step. A closer inspection shows that the algorithm for backprojection is easy to parallelize. FPGAs are able to execute many operations in the same time, so a highly parallel algorithm is a requirement for a powerful acceleration. For data flow rate maximization, we realized the backprojection in a pipelined structure with data throughput of one clock cycle. Due the hardware limitations of the FPGA, it is not possible to reconstruct the image as a whole. So it is necessary to split up the image and reconstruct these parts separately. Despite that, a reconstruction of 512 projections into a 5122 image is calculated within 13 ms on a Virtex 5 FPGA. To save hardware resources we use fixed point arithmetic with an accuracy of 23 bit for calculation. A comparison of the result image and an image, calculated with floating point arithmetic on CPU, shows that there are no differences between these images. (orig.)

A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

International Nuclear Information System (INIS)

Quinn, Heather M.; Graham, Paul S.; Morgan, Keith S.; Caffrey, Michael P.

2008-01-01

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

A novel FPGA-based bunch purity monitor system at the APS storage ring

International Nuclear Information System (INIS)

Norum, W.E.

2008-01-01

Bunch purity is an important source quality factor for the magnetic resonance experiments at the Advanced Photon Source. Conventional bunch-purity monitors utilizing time-to-amplitude converters are subject to dead time. We present a novel design based on a single field- programmable gate array (FPGA) that continuously processes pulses at the full speed of the detector and front-end electronics. The FPGA provides 7778 single-channel analyzers (six per rf bucket). The starting time and width of each single-channel analyzer window can be set to a resolution of 178 ps. A detector pulse arriving inside the window of a single-channel analyzer is recorded in an associated 32-bit counter. The analyzer makes no contribution to the system dead time. Two channels for each rf bucket count pulses originating from the electrons in the bucket. The other four channels on the early and late side of the bucket provide estimates of the background. A single-chip microcontroller attached to the FPGA acts as an EPICS IOC to make the information in the FPGA available to the EPICS clients.

A low delay transmission method of multi-channel video based on FPGA

Science.gov (United States)

Fu, Weijian; Wei, Baozhi; Li, Xiaobin; Wang, Quan; Hu, Xiaofei

2018-03-01

In order to guarantee the fluency of multi-channel video transmission in video monitoring scenarios, we designed a kind of video format conversion method based on FPGA and its DMA scheduling for video data, reduces the overall video transmission delay.In order to sace the time in the conversion process, the parallel ability of FPGA is used to video format conversion. In order to improve the direct memory access (DMA) writing transmission rate of PCIe bus, a DMA scheduling method based on asynchronous command buffer is proposed. The experimental results show that this paper designs a low delay transmission method based on FPGA, which increases the DMA writing transmission rate by 34% compared with the existing method, and then the video overall delay is reduced to 23.6ms.

FiMAN: SISTEMA COMPUTARIZADO PARA ANÁLISIS DE MOVIMIENTOS DIGITALES

Directory of Open Access Journals (Sweden)

Miguel Carballo

2016-07-01

Full Text Available La reciente tecnología de dispositivos y sensores infrarrojos han abierto nuevas posibilidades para el desarrollo de software relacionado con el área de análisis de movimientos corporales. Esta tecnología puede ser utilizada en áreas como la salud, la enseñanza, la realidad virtual y aumentada, control de robots y entretenimiento. En este artículo presentamos el desarrollo de FiMAN, un sistema que permite visualizar los movimientos detallados de las manos en tiempo real y en 3D utilizando el dispositivo infrarrojo Leap Motion para la captura de datos, permitiendo la realización de grabaciones y reproducciones de movimientos para su posterior análisis. Para su desarrollo fue necesaria la división modular de los componentes visuales, estructurales, analíticos, estadísticos y de sonido, además de la captura y manipulación de datos. Gracias a su diseño modular, se obtuvo un entorno genérico de desarrollo para aplicaciones especializadas en movimientos digitales. Como Estudio de Caso, se utilizó el sistema al área de la educación musical, específicamente a la enseñanza de la técnica del piano, para lo cual se extendió FiMAN con un teclado virtual y manejo de sonido. El uso real de FiMAN en este escenario, demostró su modularidad y extensibilidad a diferentes áreas relacionadas al análisis de movimientos digitales.

Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support

Directory of Open Access Journals (Sweden)

Burhan Khurshid

2015-05-01

Full Text Available Modern Field Programmable Gate Arrays (FPGA are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC primarily because of the low Non-recurring Engineering (NRE costs associated with FPGA platforms. This has prompted FPGA vendors to improve the capacity and flexibility of the underlying primitive fabric and include specialized macro support and intellectual property (IP cores in their offerings. However, most of the work related to FPGA implementations does not take full advantage of these offerings. This is primarily because designers rely mainly on the technology-independent optimization to enhance the performance of the system and completely neglect the speed-up that is achievable using these embedded primitives and macro support. In this paper, we consider the technology-dependent optimization of fixed-point bit-parallel multipliers by carrying out their implementations using embedded primitives and macro support that are inherent in modern day FPGAs. Our implementation targets three different FPGA families viz. Spartan-6, Virtex-4 and Virtex-5. The implementation results indicate that a considerable speed up in performance is achievable using these embedded FPGA resources.

De digitale stresscoach : totale controle over je mentale gezondheid of Big Brother is watching you?

NARCIS (Netherlands)

Lieshout, M. van; Wiezer, N.; Korte, E. de

2014-01-01

Een digitale coach die je helpt stress op je werk te verminderen en meer energie uit je werk te halen klinkt aantrekkelijk. Stress ervaren we immers allemaal. Net zoals we allemaal streven naar werk waar je energie van krijgt. En stress vermijden we liever. Stress is een maatschappelijk probleem en

FPGA BASED ASYNCHRONOUS PIPELINED MB-OFDM UWB TRANSMITTER BACKEND MODULES

Directory of Open Access Journals (Sweden)

M. Santhi

2010-03-01

Full Text Available In this paper, a novel scheme is proposed which comprises the advantages of asynchronous pipelining techniques and the advantages of FPGAs for implementing a 200Mbps MB-OFDM UWB transmitter digital backend modules. In asynchronous pipelined system, registers are used as in synchronous system. But they are controlled by handshaking signals. Since FPGAs are rich in registers, design and implementation of asynchronous pipelined MBOFDM UWB transmitter on FPGA using four-phase bundled-data protocol is considered in this paper. Novel ideas have also been proposed for designing asynchronous OFDM using Modified Radix-24 SDF and asynchronous interleaver using two RAM banks. Implementation has been performed on ALTERA STRATIX II EP2S60F1020C4 FPGA and it is operating at a speed of 350MHz. It is assured that the proposed MB-OFDM UWB system can be made to work on STRATIX III device with the operating frequency of 528MHz in compliance to the ECMA-368 standard. The proposed scheme is also applicable for FPGA from other vendors and ASIC.

Relatos digitales: activando las competencias comunicativa, narrativa y digital en la formación inicial del profesorado

Directory of Open Access Journals (Sweden)

María Esther del Moral

2016-01-01

Full Text Available Los relatos digitales constituyen una técnica narrativa con gran potencial educativo al adoptar fórmulas creativas que integran información multiformato e instrumentos tecnológicos para comunicar ideas. Esta investigación evalúa el nivel de competencia comunicativa, narrativa y digital ligado al diseño de relatos en entornos digitales, alcanzado por estudiantes del Grado de Maestro de Primaria (N=143 -tras participar en una experiencia de creación colaborativa-, utilizando una rúbrica integrada por 28 indicadores: 12 relacionados con la competencia comunicativa (comunicación escrita y oral, 6 con la narrativa, y otros 10 específicos con la digital. Los resultados evidencian que si bien presentan gran destreza con las tecnologías, casi un tercio registra niveles medio-bajos en la competencia comunicativa. Se detectan dificultades en la elaboración y adaptación del guión escrito de los relatos al registro elegido -pobre vocabulario y precaria puntuación-, junto a limitaciones en la dicción al locutar los diálogos, no logrando imprimir expresividad al relato. Respecto a la competencia narrativa, solo un 40% muestra originalidad al resolver las tramas y construir personajes. Sin duda, este tipo de experiencias innovadoras ofrece un escenario idóneo para desarrollar habilidades narrativas y creativas en contextos digitales, y brinda numerosas oportunidades para la formación de los futuros docentes.

Modelo de gestión de objetos digitales para la gestión de soluciones tecnológicas/Digital object management model for the management of technological solutions

Directory of Open Access Journals (Sweden)

Dayni Pérez-Hernández

2013-01-01

Full Text Available En los últimos años se ha incrementado el uso y el volumen de los contenidos digitales en lasdiferentes organizaciones, los cuales requieren de un tratamiento y gestión que se adecúe a laelevada complejidad tecnológica existente. Las herramientas desarrolladas bajo este contexto sehan denominado Sistemas de Gestión de Contenidos o Gestores de Contenidos. Algunos sistemasextienden sus funcionalidades, debido a la necesidad de garantizar en todas las dimensiones lagestión de Objetos Digitales. Este trabajo presenta una propuesta de modelo de gestión deObjetos Digitales para dar soporte a la producción de componentes de software. Se detallan losprocesos, subprocesos y roles necesarios, que dan soporte a las actividades del modelo propuesto.Se presenta, además, un diseño para la estructura de los Objetos Digitales y se finaliza con ladescripción de los resultados de aplicación del modelo en 2 entidades y la comparación con otrasherramientas existentes en el mercado.

A Research on Seamless Platform Change of Reactor Protection System From PLC to FPGA

Energy Technology Data Exchange (ETDEWEB)

Yoo, Junbeom; Lee, Jonghoon [Konkuk Univ., Seoul (Korea, Republic of); Lee, Jangsoo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2013-08-15

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

A Research on Seamless Platform Change of Reactor Protection System From PLC to FPGA

International Nuclear Information System (INIS)

Yoo, Junbeom; Lee, Jonghoon; Lee, Jangsoo

2013-01-01

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea

A RESEARCH ON SEAMLESS PLATFORM CHANGE OF REACTOR PROTECTION SYSTEM FROM PLC TO FPGA

Directory of Open Access Journals (Sweden)

JUNBEOM YOO

2013-08-01

Full Text Available The PLC (Programmable Logic Controller has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems. Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array. Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system

Science.gov (United States)

Chen, Yi-Pin; Chang, Chia-Yuan; Chen, Shean-Jen

2018-02-01

In this study, a field programmable gate array (FPGA)-based Shack-Hartmann wavefront sensor (SHWS) programmed on LabVIEW can be highly integrated into customized applications such as adaptive optics system (AOS) for performing real-time wavefront measurement. Further, a Camera Link frame grabber embedded with FPGA is adopted to enhance the sensor speed reacting to variation considering its advantage of the highest data transmission bandwidth. Instead of waiting for a frame image to be captured by the FPGA, the Shack-Hartmann algorithm are implemented in parallel processing blocks design and let the image data transmission synchronize with the wavefront reconstruction. On the other hand, we design a mechanism to control the deformable mirror in the same FPGA and verify the Shack-Hartmann sensor speed by controlling the frequency of the deformable mirror dynamic surface deformation. Currently, this FPGAbead SHWS design can achieve a 266 Hz cyclic speed limited by the camera frame rate as well as leaves 40% logic slices for additionally flexible design.

Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research

Directory of Open Access Journals (Sweden)

Burgess Shane C

2008-04-01

Full Text Available Abstract Background This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences. Results This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs. Conclusion Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.

Design Verification Enhancement of FPGA-based Plant Protection System Trip Logics for Nuclear Power Plant

International Nuclear Information System (INIS)

Ahmed, Ibrahim; Jung, Jae Cheon; Heo, Gyun Young

2016-01-01

As part of strengthening the application of FPGA technology and find solution to its challenges in NPPs, international atomic energy agency (IAEA) has indicated interest by joining sponsorship of Topical Group on FPGA Applications in NPPs (TG-FAN) that hold meetings up to 7th times until now, in form of workshop (International workshop on the application of FPGAs in NPPs) annually since 2008. The workshops attracted a significant interest and had a broad representation of stakeholders such as regulators, utilities, research organizations, system designers, and vendors, from various countries that converge to discuss the current issues regarding instrumentation and control (I and C) systems as well as FPGA applications. Two out of many technical issues identified by the group are lifecycle of FPGA-based platforms, systems, and applications; and methods and tools for V and V. Therefore, in this work, several design steps that involved the use of model-based systems engineering process as well as MATLAB/SIMULINK model which lead to the enhancement of design verification are employed. The verified and validated design output works correctly and effectively. Conclusively, the model-based systems engineering approach and the structural step-by-step design modeling techniques including SIMULINK model utilized in this work have shown how FPGA PPS trip logics design verification can be enhanced. If these design approaches are employ in the design of FPGA-based I and C systems, the design can be easily verified and validated

Data acquisition system for charge-division mechanism based on FPGA

International Nuclear Information System (INIS)

Yang Litao; Li Dongcang; Yang Lei; Wu Huaiyi; Qi Zhong

2010-01-01

Design a system of Peak value acquisition, data processing and data output for 4 channels nuclear signal at the same time by FPGA that base on the basic principle of position information readout for particle through Charger-division Mechanism. In view of the randomness of nuclear signal, so insert asynchronous FIFO in the system, which greatly improve the sampling rate of system. In the article has produced the conjunctive relation and inner circuit structure and give out simulation. From here, you can see the great power of FPGA which used in nuclear data acquisition and processing system. (authors)

Herramienta ALTER. Recursos educativos digitales en red y actividades con herramientas Web 2.0 para aulas hospitalarias

OpenAIRE

Serrano Sánchez, José Luis; Torres Soto, Ana

2012-01-01

Serrano, J.L. y Torres, A. (2012). Herramienta ALTER. Recursos educativos digitales en red y actividades con herramientas Web 2.0 para aulas hospitalarias. En M.P. Prendes y J.L. Serrano (Coords.), Las TIC en las aulas hospitalarias. Alicante: Marfil.

LDPC decoder with a limited-precision FPGA-based floating-point multiplication coprocessor

Science.gov (United States)

Moberly, Raymond; O'Sullivan, Michael; Waheed, Khurram

2007-09-01

Implementing the sum-product algorithm, in an FPGA with an embedded processor, invites us to consider a tradeoff between computational precision and computational speed. The algorithm, known outside of the signal processing community as Pearl's belief propagation, is used for iterative soft-decision decoding of LDPC codes. We determined the feasibility of a coprocessor that will perform product computations. Our FPGA-based coprocessor (design) performs computer algebra with significantly less precision than the standard (e.g. integer, floating-point) operations of general purpose processors. Using synthesis, targeting a 3,168 LUT Xilinx FPGA, we show that key components of a decoder are feasible and that the full single-precision decoder could be constructed using a larger part. Soft-decision decoding by the iterative belief propagation algorithm is impacted both positively and negatively by a reduction in the precision of the computation. Reducing precision reduces the coding gain, but the limited-precision computation can operate faster. A proposed solution offers custom logic to perform computations with less precision, yet uses the floating-point format to interface with the software. Simulation results show the achievable coding gain. Synthesis results help theorize the the full capacity and performance of an FPGA-based coprocessor.

Control de acceso usando FPGA y RFID

Directory of Open Access Journals (Sweden)

Dora Luz Almanza Ojeda

2012-10-01

Full Text Available Este trabajo presenta el diseño e implementación de un sistema de control de acceso mediante Identificación por Radiofrecuencia (RFID, Radio Frequency Identification controlado por una Matriz de compuertas programables (FPGA, Field Programmable Gate Array. El sistema está constituido por un par de dispositivos de adquisición de radiofrecuencia, una FPGA, un juego de etiquetas y tarjetas pasivas de identificación. Mediante una interfaz gráfica de usuario es posible controlar todo movimiento dentro de una zona determinada, desde los accesos hasta la disponibilidad de equipo; utilizando los dispositivos de adquisición de radiofrecuencia se puede acceder a la información de los usuarios autorizados, así como al control del equipo. Con este sistema es posible monitorear, administrar y reportar todo acceso de personal, movimiento de equipo o plagio de manera eficiente y evitando un gran número de errores humanos.  

The implementing of high resolution time measuring circuit based on FPGA

International Nuclear Information System (INIS)

Zhang Ji; Zeng Yun; Wang Zheng; Li Quiju; Lu Jifang; Wu Jinyuan

2011-01-01

It presents the implementing of TDC based on FPGA. The fine timing function part is accomplished through the time interpolators that are composed of the carry chain of intrinsic adders in FPGA. This architecture dates back to the latest technology-WUTDC (Wave Union TDC) that is developed to sub-divide the ultra-wide bins and improve the measure resolution. The board and the online test have been proved that the linearity of converters is satisfying and the time resolution is better than 40 ps. (authors)

Cosificación de las adolescentes en las redes sociales digitales

OpenAIRE

Urdangarin Aranbarri, Garazi

2015-01-01

La cosificación se refiere a la representación de una mujer a través de su cuerpo o partes de éste. La utilización masiva por parte de adolescentes de las Redes Sociales Digitales, hacen de éste fenómeno una forma tangible de discriminación sexista. Este estudio, tiene como objetivo analizar la cosificación de las adolescentes en las redes sociales y su influencia en la autoestima de cada joven. Para ello, se han aplicado diferentes escalas a 1087 adolescentes de 11 centros edu...

Insignias digitales como acreditación de competencias en la Universidad

OpenAIRE

Borrás Gené, Oriol

2017-01-01

Las insignias digitales son archivos en formato PNG cuyo principal objetivo consiste en mostrar algún tipo de logro. Están formados por una imagen y una serie de metadatos que ofrecen todos los datos relativos a la acreditación que representan, normalmente competencias. Ofrece la ventaja de mostrar una información mucho más completa que los clásicos certificados en papel, como por ejemplo asociar evidencias educativas resultantes de la formación asociada a la insignia. Por otro lado al ser un...

Formación digital de profesores. Una revisión del tema con énfasis en los modelos de competencias/literacidades digitales

Directory of Open Access Journals (Sweden)

Gonzalo Abio

2017-03-01

Full Text Available En este trabajo de cuño teórico-reflexivo, se discuten algunos factores que influyen en el uso de las tecnologías en las escuelas y se focaliza en las competencias que necesita el profesor para un trabajo integrado y efectivo apoyado por las tecnologías digitales. Con ese objetivo, se lleva a cabo una revisión bibliográfica sobre algunos modelos de competencias/literacidades digitales con énfasis en el profesor. Por último, se brindan algunos comentarios sobre las necesidades de formación digital de los profesores.

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

International Nuclear Information System (INIS)

Ren, Y J; Zhu, J G; Yang, X Y; Ye, S H

2006-01-01

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

Science.gov (United States)

Ren, Y. J.; Zhu, J. G.; Yang, X. Y.; Ye, S. H.

2006-10-01

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent.

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

DEFF Research Database (Denmark)

Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

2015-01-01

standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

Timing measurements of some tracking algorithms and suitability of FPGA's to improve the execution speed

CERN Document Server

Khomich, A; Kugel, A; Männer, R; Müller, M; Baines, J T M

2003-01-01

Some of track reconstruction algorithms which are common to all B-physics channels and standard RoI processing have been tested for execution time and assessed for suitability for speed-up by using FPGA coprocessor. The studies presented in this note were performed in the C/C++ framework, CTrig, which was the fullest set of algorithms available at the time of study For investigation of possible speed-up of algorithms most time consuming parts of TRT-LUT was implemented in VHDL for running in FPGA coprocessor board MPRACE. MPRACE (Reconfigurable Accelerator / Computing Engine) is an FPGA-Coprocessor based on Xilinx Virtex-2 FPGA and made as 64Bit/66MHz PCI card developed at the University of Mannheim. Timing measurements results for a TRT Full Scan algorithm executed on the MPRACE are presented here as well. The measurement results show a speed-up factor of ~2 for this algorithm.

Det digitale interaktive fjernsyn i hverdagslivet

Directory of Open Access Journals (Sweden)

Thomas Bjørner

2007-04-01

Full Text Available Digitaliseringen af tv-mediet er allerede i fuld gang, og der er i Danmark fastlagt en analog slukdato for public servicekanalerne i 2009. I forlængelse heraf leverer denne artikel en række indsigter i, hvordan den nye teknologi potentielt forandrer hverdagen, men samtidig er det også en pointe, at den digitale teknologi indpasses i eksisterende mønstre for tv-sening. Med baggrund i forsøgskanalen TV2/Nord-Digital, som var den første kanal der udsendte digitalt interaktivt tv i Danmark, vil denne artikel give nogle svar på, hvad der sker når digitalt tv (med de øgede interaktive muligheder vinder indpas i husstanden. Hvem skal bestemme i forhold til hvad der skal ses af interaktivt indhold? Vil digitaliseringen dermed fremme den stigende tendens til at vi ser mere tv hver for sig? Og ønsker seerne overhovedet at være interaktive med deres fjernsyn – og i givet fald om hvad og hvorfor?

Repositorios digitales y software open source

Directory of Open Access Journals (Sweden)

Doria, María Vanesa

2015-06-01

Full Text Available En la actualidad las universidades se encuentran en constante evolución, fruto de la transformación generada por la sociedad de la información y el conocimiento, donde la transversalidad son las Tecnologías de la Información y Comunicación (TIC, que tienen como objetivo ampliar el acceso a la información y el conocimiento a través de su herramienta digital más distinguida, Internet. Las universidades retroalimentan su conocimiento e información, mediante las producciones científicasacadémicas, y para promover el acceso a ellas, muchas universidades están inclinándose al movimiento del Acceso Abierto (AA siguiendo la vía verde en el desarrollo de repositorios digitales (RD. Para la creación de RD es necesario analizar los software open source disponibles, dado que estos son las herramientas que facilitan la automatización de los mismos. El presente estudio se centra en el análisis de los software open source existentes en el mercado.

An FPGA bridge preserving traffing quality of service for on-chip network-based systems

NARCIS (Netherlands)

Nejad, A.B.; Escudero Martinez, M.; Goossens, K.G.W.

2011-01-01

FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into

A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

Science.gov (United States)

Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

2015-10-01

Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

Science.gov (United States)

Du, Hongtao; Qi, Hairong; Szu, Harold H.

2005-03-01

Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called jitter effect in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application

Monitoreo de cambios en la densidad de cobertura forestal en bosque templado usando fotografías aéreas digitales de alta resolución

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José López García

2016-08-01

Full Text Available Se utilizaron series multitemporales de fotografías aéreas digitales de alta resolución de pequeño formato para evaluar los cambios en la densidad de cobertura forestal en un bosque templado. Una combinación de técnicas convencionales y adaptadas de fotogrametría y fotointerpretación fueron utilizadas para establecer un método específico de evaluación.  Este método ha sido probado en un periodo de doce años (1999-2011 en la zona núcleo de la Reserva de la Biósfera Mariposa Monarca, localizada en los estados de México y Michoacán, en México, usando mosaicos ortorectificados como mapas base para evaluar cambios bienales. Las imágenes fueron fotointerpretadas de manera tradicional marcando los cambios sobre acetatos, colocados sobre las imágenes impresas, creando así nuevos polígonos. Estos fueron transferidos directamente de los acetatos al ortomosaico a través de la pantalla de la computadora, usando al menos tres puntos de control, cumpliendo así con el principio de triangulación radial. El bosque fue separado en las siguientes clases de cobertura forestal: cerrada, semi-cerrada, semi-abierta, abierta y deforestada. La evaluación en la exactitud en la clasificación de densidad de cobertura fue estimada a través de muestreos en campo, empleando matrices de confusión, siendo del 95%. A partir de 2003, este método ha sido utilizado para determinar el pago por servicios ambientales. Dicho pago, junto con una gran interacción con las comunidades, se ha traducido en una reducción en la degradación forestal y la deforestación en la zona núcleo de la Reserva.

Investigation of Electromagnetic Signatures of a FPGA Using an APREL EM-ISIGHT System

Science.gov (United States)

2015-12-01

shelf (COTS) field- programmable gate array (FPGA) at the optimized factor levels established from the DOE and varying the programmed signal. This...signature using APREL’s EM-ISight automated system is hypothesized to be a novel way to accomplish this task. Research Questions The research...a field programmable gate array (FPGA) is the circuit board utilized for testing the inherent electromagnetic signature. Every device produces an

Desain Protokol Suara Sebagai Pengendali Dalam Smart Home Menggunakan FPGA

Directory of Open Access Journals (Sweden)

Barlian Henryranu Prasetio

2017-05-01

Smart home is a system that uses computers and information technology to control home-like equipment such as windows and lights. The system can be a simple control system to a complex system. Computer / microcontroller based on internet/ethernet network equipped with intelligent system and automation system so as to make home to work automatically. Many computer devices / microcontrollers that can be implemented as a controller in the smart home. Smart home control system in this study using Xilinx xpartan-3e that controls the equipment in the house through LAN (Local Area Networking. This control system communicates using broadcast voice on the local network. The Controller System is designed to be able to transmit a voice signal packet from the microphone input and then send it using the ethernet protocol in the home local network using the FPGA. The FPGA is programmed to transmit and encode data packets, converting digital data into analog data to be able to control the equipment in the home. From the simulation test results using ISIM, it is seen that the system works in realtime. Keywords: smart home, voice, fpga, control

An FPGA-Based People Detection System

Directory of Open Access Journals (Sweden)

James J. Clark

2005-05-01

Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

Superconducting cavity driving with FPGA controller

Energy Technology Data Exchange (ETDEWEB)

Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland); Simrock, S.; Brand, A. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Chase, B.; Carcagno, R.; Cancelo, G. [Fermi National Accelerator Lab., Batavia, IL (United States); Koeth, T.W. [Rutgers - the State Univ. of New Jersey, NJ (United States)

2006-07-01

The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

Superconducting cavity driving with FPGA controller

International Nuclear Information System (INIS)

Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S.; Simrock, S.; Brand, A.; Chase, B.; Carcagno, R.; Cancelo, G.; Koeth, T.W.

2006-01-01

The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

La lectura en formatos digitales en el Chile actual: nuevas prácticas y viejas desigualdades

Directory of Open Access Journals (Sweden)

Cristóbal Moya

2017-01-01

Full Text Available En el presente artículo se caracteriza la fisionomía de la lectura en formatos digitales, especialmente en comparación con los impresos. Para esto se analiza la lectura en formatos digitales de cuatro materiales de lectura en el Chile actual (libros, revistas, periódicos e historietas a partir del Estudio de Comportamiento Lector 2014. Las prácticas lectoras son analizadas en cuanto prácticas culturales más amplias, lo que permite dar cuenta de la afinidad existente entre prácticas lectoras y determinados grupos sociales. En particular, se examinan las implicancias de ser un “lector omnívoro” en términos de formatos digitales e impresos. Se encuentra que los “lectores omnívoros” corresponden a perfiles lectores de posiciones sociales aventajadas en términos de educación e ingresos del hogar. Además, los omnívoros son quienes exhiben una mayor disposición a leer distintos materiales y en distintos formatos. Finalmente, se evidencia que existe una reproducción intergeneracional de la desigual disposición a leer en formatos digitales a partir del análisis de la educación de los padres. PALABRAS CLAVE: lectura digital en Chile, prácticas lectoras en Chile, lectura y distinción social, omnivorismo lector. In this article the main features of the format of digital reading are presented, particularly in comparison with print. In order to carry out this aim, the reading in digital format of four reading materials in contemporary Chile (books, magazines, newspapers and comics is analyzed drawing on the Estudio de Comportamiento Lector 2014 (Study of Reading Behavior. Reading practices are analyzed as broader cultural practices, which allows to establish links between reading practices and certain social groups. Particularly, the implications of being an ‘omnivore reader’ are examined, considering digital and print formats. Results show that ‘omnivore readers’ correspond to reading profiles of advantaged social

A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

Science.gov (United States)

Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

2014-01-01

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. PMID:24379047

A FPGA embedded web server for remote monitoring and control of smart sensors networks.

Science.gov (United States)

Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

2013-12-27

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

Directory of Open Access Journals (Sweden)

Eduardo Magdaleno

2013-12-01

Full Text Available This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI. The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A. Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

Intermediate Frequency Digital Receiver Based on Multi-FPGA System

Directory of Open Access Journals (Sweden)

Chengchang Zhang

2016-01-01

Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

FPGA Implementation of a SAR Two-dimensional Autofocus Approach

Directory of Open Access Journals (Sweden)

Guo Jiangzhe

2016-08-01

Full Text Available For real-time autofocus of defocused images produced by Synthetic Aperture Radar (SAR, the twodimensional autofocus approach proposed in this study is used to correct the residual range cell migration and compensate for the phase error. Next, a block-wise Phase Gradient Autofocus (PGA is used to correct the space-variant phase error. The Field-Programmable Gate Array (FPGA design procedures, resource utilization, processing speed, accuracy, and autofocus are discussed in detail. The system is able to autofocus an 8K × 8K complex image with single precision within 5.7 s when the FPGA works at 200 MHz. The processing of the measured data verifies the effectiveness and real-time capability of the proposed method.

FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods

Directory of Open Access Journals (Sweden)

Bakos Jason D

2010-04-01

Full Text Available Abstract Background Likelihood (ML-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a Field Programmable Gate Array (FPGA-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. Results We use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10× speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture. Conclusions Heterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs 1.

FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications

Directory of Open Access Journals (Sweden)

S. Tsakiris

2009-09-01

Full Text Available This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.

FPGA Implementation of Block Parallel DF-MPIC Detectors for DS-CDMA Systems in Frequency-Nonselective Channels

Directory of Open Access Journals (Sweden)

Adel Omar Dahmane

2008-01-01

Full Text Available Multistage parallel interference cancellation- (MPIC- based detectors allow to mitigate multiple-access interference in direct-sequence code-division multiple-access (DS-CDMA systems. They are considered serious candidates for practical implementation showing a good tradeoff between performance and complexity. Better performance is obtained when decision feedback (DF is employed. Although MPIC and DF-MPIC have the same arithmetic complexity, DF-MPIC needs much more FPGA resources when compared to MPIC without decision feedback. In this letter, FPGA implementation of block parallel DF-MPIC (BP-DF-MPIC is proposed allowing better tradeoff between performance and FPGA area occupancy. To reach an uncoded bit-error rate of 10−3, BP-DF-MPIC shows a 1.5 dB improvement over the MPIC without decision feedback with only 8% increase in FPGA resources compared to 69% for DF-MPIC.

FPGA Realization of Memory 10 Viterbi Decoder

DEFF Research Database (Denmark)

Paaske, Erik; Bach, Thomas Bo; Andersen, Jakob Dahl

1997-01-01

sequence mode when feedback from the Reed-Solomon decoder is available. The Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's. The overall operating speed is 30 kbit/s, and since up to three iterations are performed for each frame and only one decoder is used, the operating speed...

Development of FPGA-based digital signal processing system for radiation spectroscopy

International Nuclear Information System (INIS)

Lee, Pil Soo; Lee, Chun Sik; Lee, Ju Hahn

2013-01-01

We have developed an FPGA-based digital signal processing system that performs both online digital signal filtering and pulse-shape analysis for both particle and gamma-ray spectroscopy. Such functionalities were made possible by a state-of-the-art programmable logic device and system architectures employed. The system performance as measured, for example, in the system dead time and accuracy for pulse-height and rise-time determination, was evaluated with standard alpha- and gamma-ray sources using a CsI(Tl) scintillation detector. It is resulted that the present system has shown its potential application to various radiation-related fields such as particle identification, radiography, and radiation imaging. - Highlights: ► An FPGA-based digital processing system was developed for radiation spectroscopy. ► Our digital system has a 14-bit resolution and a 100-MHz sampling rate. ► The FPGA implements the online digital filtering and pulse-shape analysis. ► The pileup rejection is implemented in trigger logic before digital filtering process. ► Our digital system was verified in alpha-gamma measurements using a CsI detector

Contenidos educativos digitales que promueven la integración efectiva de las tecnologías de la información y comunicación

OpenAIRE

Manso, Micaela; Garzón, Magdalena; Rodríguez, Cecilia; Pérez, Paula

2011-01-01

Este estudio cualitativo indagó la relación que existe entre la calidad de los contenidos educativos digitales y la calidad de la implementación que los docentes hacen de esos contenidos educativos. Se utilizaron 10 cualidades basadas en TPACK y el Marco de Enseñanza para la Comprensión (EpC) para analizar la calidad de ambos. Además, se seleccionaron 3 contenidos educativos digitales y se realizaron entrevistas a 6 docentes, 34 estudiantes secundarios y 3 diseñadores de proyectos TIC en Méx...

A Design Methodology for Efficient Implementation of Deconvolutional Neural Networks on an FPGA

OpenAIRE

Zhang, Xinyu; Das, Srinjoy; Neopane, Ojash; Kreutz-Delgado, Ken

2017-01-01

In recent years deep learning algorithms have shown extremely high performance on machine learning tasks such as image classification and speech recognition. In support of such applications, various FPGA accelerator architectures have been proposed for convolutional neural networks (CNNs) that enable high performance for classification tasks at lower power than CPU and GPU processors. However, to date, there has been little research on the use of FPGA implementations of deconvolutional neural...

Design of CMOS imaging system based on FPGA

Science.gov (United States)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

FPGA-based network data transmission scheme for CSNS

International Nuclear Information System (INIS)

Wang Xiuku; Zhang Hongyu; Gu Minhao; Xiao Liang

2012-01-01

This paper presents the FPGA-based network data transmission solutions for the Data Acquisition System of China Spallation Neutron Source (CSNS). The board with FPGA as the core is used as the hardware platform to realize the transmission of network data. A SOPC system is built and an embedded Linux is transplanted on PowerPC Core. An application program based on Linux has been finished to realize the data transmission via embedded Gigabit Ethernet. The relationship between network transfer performance and packet size was obtained by a test program. In addition, the paper also tried to realize some other ways to transfer data: transplanting PetaLinux on Microblaze, transplanting Lwip protocol stack on PowerPC Core and Microblaze. Their advantages and disadvantages are analyzed and compared in this paper, so that different options and recommendations can be given to meet the actual needs of different projects in the future. (authors)

FPGA Implementation of the Coupled Filtering Method and the Affine Warping Method.

Science.gov (United States)

Zhang, Chen; Liang, Tianzhu; Mok, Philip K T; Yu, Weichuan

2017-07-01

In ultrasound image analysis, the speckle tracking methods are widely applied to study the elasticity of body tissue. However, "feature-motion decorrelation" still remains as a challenge for the speckle tracking methods. Recently, a coupled filtering method and an affine warping method were proposed to accurately estimate strain values, when the tissue deformation is large. The major drawback of these methods is the high computational complexity. Even the graphics processing unit (GPU)-based program requires a long time to finish the analysis. In this paper, we propose field-programmable gate array (FPGA)-based implementations of both methods for further acceleration. The capability of FPGAs on handling different image processing components in these methods is discussed. A fast and memory-saving image warping approach is proposed. The algorithms are reformulated to build a highly efficient pipeline on FPGA. The final implementations on a Xilinx Virtex-7 FPGA are at least 13 times faster than the GPU implementation on the NVIDIA graphic card (GeForce GTX 580).

Design and Implementation of Radar Cross-Section Models on a Virtex-6 FPGA

Directory of Open Access Journals (Sweden)

B. U. V. Prashanth

2014-01-01

Full Text Available The simulation of radar cross-section (RCS models in FPGA is illustrated. The models adopted are the Swerling ones. Radar cross-section (RCS which is also termed as echo area gives the amount of scattered power from a target towards the radar. This paper elucidates the simulation of RCS to represent the specified targets under different conditions, namely, aspect angle and frequency. This model is used for the performance evaluation of radar. RCS models have been developed for various targets like simple objects to complex objects like aircrafts, missiles, tanks, and so forth. First, the model was developed in MATLAB real time simulation environment and after successful verification, the same was implemented in FPGA. Xilinx ISE software was used for VHDL coding. This simulation model was used for the testing of a radar system. The results were compared with MATLAB simulations and FPGA based timing diagrams and RTL synthesis. The paper illustrates the simulation of various target radar cross-section (RCS models. These models are simulated in MATLAB and in FPGA, with the aim of implementing them efficiently on a radar system. This method can be generalized to apply to objects of arbitrary geometry for the two configurations of transmitter and receiver in the same as well as different locations.

Automated Metabolic P System Placement in FPGA

Directory of Open Access Journals (Sweden)

Kulakovskis Darius

2016-07-01

Full Text Available An original Very High Speed Integrated Circuit Hardware Description Language (VHDL code generation tool that can be used to automate Metabolic P (MP system implementation in hardware such as Field Programmable Gate Arrays (FPGA is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT, and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP, slice, and 4-input LUT usage.

Embedded Active Vision System Based on an FPGA Architecture

Directory of Open Access Journals (Sweden)

Chalimbaud Pierre

2007-01-01

Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

Embedded Active Vision System Based on an FPGA Architecture

Directory of Open Access Journals (Sweden)

Pierre Chalimbaud

2006-12-01

Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

Efficient and side-channel resistant authenticated encryption of FPGA bitstreams

DEFF Research Database (Denmark)

Bogdanov, Andrey; Moradi, Amir; Yalcin, Tolga

2013-01-01

AE modes of operation with the same countermeasure. We conclude that the deployment of dedicated AE schemes such as ALE significantly facilitates the real-world efficiency and security of FPGA bitstream protection in practice: Not only our solution enables authenticated encryption for bitstream...... on low-cost FPGAs but it also aims to mitigate physical attacks which have been lately shown to undermine the security of the bitstream protection mechanisms in the field.......State-of-the-art solutions for FPGA bitstream protection rely on encryption and authentication of the bitstream to both ensure its confidentiality, thwarting unauthorized copying and reverse engineering, and prevent its unauthorized modification, maintaining a root of trust in the field. Adequate...

Signal compression in radar using FPGA

OpenAIRE

Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

2010-01-01

We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

Revistas nativas digitales en el ámbito del deporte en España: el caso de MARCA Plus

Directory of Open Access Journals (Sweden)

Ignacio LABARGA-ADÁN

2018-01-01

Full Text Available Desde su aparición en el verano de 2014, MARCA Plus se ha convertido en un referente para las publicaciones nativas digitales. Prueba de ello es el reconocimiento por parte de Apple como una de las mejores 'apps' para iPad y ganar los 'Digital Magazine Awards' en 2015 y 2016. Este artículo pretende abordar las características de este nuevo formato en el panorama actual de los medios: el de las revistas nativas digitales. La revista objeto de estudio es una de las apuestas de Unidad Editorial por las nuevas tecnologías, habiendo conseguido en tres años un posicionamiento excepcional en el mercado digital. MARCA Plus destaca por su diseño, creatividad, carácter innovador, interactividad y nuevas narrativas audiovisuales, a lo que se suma el ser un soporte ideal para las nuevas tendencias en publicidad.

Mercados municipales y tecnologías digitales: entre el e-comercio y nuevas formas de convivialidad

Directory of Open Access Journals (Sweden)

Juan Robles

2014-01-01

Full Text Available Los escaparates virtuales, la venta online y la puesta en valor de los circuitos de producción cortos y agroecológicos a través de eficaces políticas de comunicación en las redes sociales son ejemplos de lo que hoy están usando muchos pequeños comerciantes para poner en valor su expertise tradicional, paradójicamente basada en la cercanía y el trato directo. En este artículo analizamos el papel de las tecnologías digitales en la re-significación y re-activación del pequeño comercio y de los mercados de abastos tradicionales. El uso de tecnologías digitales pone en entredicho la visión de Internet como agente de desterritorialización y de creación de una cultura global, ante la presencia de nuevas formas de localización basadas en la emergencia de nuevas formas de convivialidad, agroecología y alimentación saludable.

The current state of FPGA technology in the nuclear domain

Energy Technology Data Exchange (ETDEWEB)

Ranta, J.

2012-07-01

Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

The current state of FPGA technology in the nuclear domain

International Nuclear Information System (INIS)

Ranta, J.

2012-01-01

Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

Recursos digitales para el aprendizaje del dibujo tecnológico

Directory of Open Access Journals (Sweden)

Gavino, Sergio

2012-01-01

Full Text Available El presente trabajo sintetiza el proceso de diseño y creación de medios digitales en distintos formatos: animaciones en formato swf, modelos 3D interactivos en formato skp, java o pdf y la implementación de una aplicación on-line para el dibujo asistido por computadora. Las animaciones en formato swf se utilizan como apoyo para el aprendizaje presencial; en ellas, se modelizan los elementos que constituyen los fundamentos del dibujo tecnológico: el Sistema Monge o Sistema Diédrico, con el dinamismo que su organización implica, permitiendo la interacción del alumno con los elementos del sistema modelizado. Los modelos 3D interactivos pueden orientarse para la visualización de componentes de ingeniería, arquitectura, diseño industrial, etc., haciendo posible ampliar el repertorio de recursos morfológicos y así consolidar el aprendizaje del dibujo tecnológico. La actividad online para el dibujo asistido por computadora está basada en la aplicación Compass and Ruler, de código abierto bajo licencia GNU GPL; a través de esta aplicación los alumnos resuelven diversas ejercitaciones del concepto de isometría, otro contenido del dibujo tecnológico. Los recursos digitales presentados en el presente artículo son desarrollados por la Unidad de Investigación y Desarrollo Grupo de Ingeniería Gráfica Aplicada (UID-GIGA de la Facultad de Ingeniería de la UNLP para las asignaturas Gráfica para Ingeniería (de las especialidades Ingeniería Aeronáutica, Mecánica, Electromecánica y Materiales y Sistemas de Representación “C” (de las especialidades Ingeniería Química, Industrial y Computación.

Flujo de carga con armónicos empleando la matriz impedancia de barras

Directory of Open Access Journals (Sweden)

José A González Quintero

2011-03-01

Full Text Available Se describe un flujo de armónicos empleando la matriz impedancia de barras. El algoritmo propuesto permite hallar losvoltajes de cada nodo del circuito sin tener que realizar la solución simultánea de todas las ecuaciones no linealescorrespondientes a cada nodo, ni siquiera la solución simultánea de las ecuaciones correspondientes a una redreducida de nodos no lineales solamente.  This work describes a harmonic load flow using the bar impedance matrix. The proposed algorithm permit to findevery node voltage of the circuit without to realize the simultaneous solution of all the non-linear equationscorresponding to each node, not even the simultaneous solution of the equations corresponding to a reducednetwork of only non-linear nodes.

Subjetividades juveniles, expresiones políticas y uso de tecnologías digitales

Directory of Open Access Journals (Sweden)

Mónica María Bermúdez Grajales

2017-05-01

Full Text Available El presente artículo da cuenta de algunos hallazgos derivados de una revisión documental que tuvo como fin indagar en la relación entre subjetividades juveniles, expresiones políticas y uso de tecnologías digitales. Fueron revisadas 150 investigaciones publicadas a partir del año 2000 hasta el 2014, tanto en el ámbito internacional —Europa y Estados Unidos— como en el nacional. Uno de los principales hallazgos plantea que con las actuales tecnologías digitales se están cultivando prácticas políticas de gran trascendencia, en tanto se produce una comunicación apasionada, multimodal e incidental que logra distanciarse de una política tradicional-representativa, para articularse a los deseos y pulsiones de la subjetividad juvenil contemporánea. Además se plantea que el uso de las tecnologías se integra a propuestas contrahegemónicas en las que la apropiación de lenguajes hipertextuales constituye la des-identificación con una lógica dominante. En tal sentido, los videos, las imágenes, la música, las animaciones, los enlaces y los mensajes de texto se convierten en la construcción de una sintaxis que contribuye a traducir con más convencimiento la emoción, el afecto y el malestar del presente.

Fpga based L-band pulse doppler radar design and implementation

Science.gov (United States)

Savci, Kubilay

As its name implies RADAR (Radio Detection and Ranging) is an electromagnetic sensor used for detection and locating targets from their return signals. Radar systems propagate electromagnetic energy, from the antenna which is in part intercepted by an object. Objects reradiate a portion of energy which is captured by the radar receiver. The received signal is then processed for information extraction. Radar systems are widely used for surveillance, air security, navigation, weather hazard detection, as well as remote sensing applications. In this work, an FPGA based L-band Pulse Doppler radar prototype, which is used for target detection, localization and velocity calculation has been built and a general-purpose Pulse Doppler radar processor has been developed. This radar is a ground based stationary monopulse radar, which transmits a short pulse with a certain pulse repetition frequency (PRF). Return signals from the target are processed and information about their location and velocity is extracted. Discrete components are used for the transmitter and receiver chain. The hardware solution is based on Xilinx Virtex-6 ML605 FPGA board, responsible for the control of the radar system and the digital signal processing of the received signal, which involves Constant False Alarm Rate (CFAR) detection and Pulse Doppler processing. The algorithm is implemented in MATLAB/SIMULINK using the Xilinx System Generator for DSP tool. The field programmable gate arrays (FPGA) implementation of the radar system provides the flexibility of changing parameters such as the PRF and pulse length therefore it can be used with different radar configurations as well. A VHDL design has been developed for 1Gbit Ethernet connection to transfer digitized return signal and detection results to PC. An A-Scope software has been developed with C# programming language to display time domain radar signals and detection results on PC. Data are processed both in FPGA chip and on PC. FPGA uses fixed

Single Event Effects in FPGA Devices 2015-2016

Science.gov (United States)

Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

2016-01-01

This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

Medienkompetenz und digitale Bildung aus medienpädagogischer Perspektive - Bericht für das Grünbuch "Digitalisierung und Politik" des Zukunfts- und Verfassungsausschuss des österreichischen Bundesrates.

Directory of Open Access Journals (Sweden)

Christian Swertz

2017-03-01

Full Text Available Medienkompetenz und digitale Bildung können die Fähigkeit zur Teilnahme an öffentlichen Debatten und zum Umgang mit widersprüchlichen Wahrheiten fördern. Daher sind die Vermittlung von Medienkompetenz und digitaler Bildung nicht nur für die Bildung des Menschen, sondern auch für den demokratischen Staat erforderlich. Vor diesem Hintergrund werden Vorschläge für Gesetzesänderungen, mit denen Medienkompetenz und digitale Bildung in allen pädagogischen Handlungsfeldern vermittelt werden können, entwickelt. Media Literacy and Digital Education might increase the ability to participate in public debates and to handle contradictory truths. That's why Media Literacy and Digital Education do not only contribute to personality development, but are necessary for the democratic state. Based on these arguments suggestions for legislative changes in Austria are made.

A new FPGA architecture suitable for DSP applications

Energy Technology Data Exchange (ETDEWEB)

Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan, E-mail: 071021037@fudan.edu.cn [ASIC and System State Key Laboratory, Fudan University, Shanghai 201203 (China)

2011-05-15

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 {mu}m CMOS technology successfully. The die size is 6.3 x 4.5 mm{sup 2} with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

A new FPGA architecture suitable for DSP applications

International Nuclear Information System (INIS)

Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan

2011-01-01

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 x 4.5 mm 2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

FPGA-Based Embedded Motion Estimation Sensor

Directory of Open Access Journals (Sweden)

Zhaoyi Wei

2008-01-01

Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

Design of the device of auto-measuring radon continuously based on FPGA

International Nuclear Information System (INIS)

Wang Yan; Shen Zhengqin; Chen Qiong

2004-01-01

This paper introduces the design of the device of auto-measuring radon continuously. The core of the system is the design of controlling system by FPGA, which consists of preset module, electrical calendar module and driving module. The system can automatically measure the consistence of the radon and the separating out rate of it. The information data is displayed by LCD. The high speed micro printer is used to print the measuring result. It adopts FPGA to design the measuring system of the device, which can improve the precision and stability of the system. (authors)

Hilvanar tecnologías digitales y procesos de tejido o costura artesanal: una revisión crítica de prácticas

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Tania Pérez-Bustos

2017-01-01

Full Text Available El presente artículo hace una revisión de algunas tecnologías digitales diseñadas en torno a prácticas artesanales de tejido, bordado y costura. Esta revisión busca identificar las tensiones y encuentros que existen entre los saberes asociados a lo textil y artesanal, y los relativos a la tecnología y la informática. En particular, el artículo se enfoca en tres tipos de diseño de tecnologías de la información: en primera instancia, en aquel orientado a la construcción de repositorios digitales de prácticas textiles artesanales; en segundo lugar, en el desarrollo de interfaces tangibles de usuario inspiradas en la materialidad de lo textil y, por último, en iniciativas que, para idear tecnologías digitales, se centran en el potencial creativo de los lenguajes-materiales de la producción textil artesanal. El artículo se cierra con una reflexión establecida en torno a las posibilidades de co-aprendizaje que emergen de los encuentros que se dan entre tecnología digital y tejido o bordado artesanal.

Autonomous Lawnmower using FPGA implementation.

Science.gov (United States)

Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

2016-11-01

Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

Embedded algorithms within an FPGA-based system to process nonlinear time series data

Science.gov (United States)

Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

2008-03-01

This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better

Design of optical axis jitter control system for multi beam lasers based on FPGA

Science.gov (United States)

Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

2018-02-01

A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

Directory of Open Access Journals (Sweden)

Chiung-Wei Huang

2018-01-01

Full Text Available We propose a prototype of field programmable gate array (FPGA implementation for optimal pixel adjustment process (OPAP algorithm of image steganography. In the proposed scheme, the cover image and the secret message are transmitted from a personal computer (PC to an FPGA board using RS232 interface for hardware processing. We firstly embed k-bit secret message into each pixel of the cover image by the last-significant-bit (LSB substitution method, followed by executing associated OPAP calculations to construct a stego pixel. After all pixels of the cover image have been embedded, a stego image is created and transmitted from FPGA back to the PC and stored in the PC. Moreover, we have extended the basic pixel-wise structure to a parallel structure which can fully use the hardware devices to speed up the embedding process and embed several bits of secret message at the same time. Through parallel mechanism of the hardware based design, the data hiding process can be completed in few clock cycles to produce steganography outcome. Experimental results show the effectiveness and correctness of the proposed scheme.

An FPGA-based reconfigurable DDC algorithm

Science.gov (United States)

Juszczyk, B.; Kasprowicz, G.

2016-09-01

This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

SIMULACIÓN DE CONTROLADORES DIGITALES SIMULATION OF DIGITAL CONTROLLERS

Directory of Open Access Journals (Sweden)

Carlos Álvarez G

2009-12-01

Full Text Available El presente trabajo tiene como objetivo la implementación de controladores digitales en un entorno de simulación controlado, para esto se desarrolla una plataforma de hardware que permite ejecutar los programas en lenguaje C generados en una estación de trabajo. Estos programas corresponden al controlador y a la planta que son generados por un software que genera dichos programas a partir de sus parámetros de modelación aplicando teoría de control digital sobre procesos reales.This paper describes an implementation of digital controllers in a simulation environment for including a hardware platform for running programs generated on a workstation. These programs for both the controller and the plant are generated by software based on parameters using digital control theory for real processes.

Rad-Hard and ULP FPGA with "Full" Functionality, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

International Nuclear Information System (INIS)

Messai, A.; Mellit, A.; Massi Pavan, A.; Guessoum, A.; Mekki, H.

2011-01-01

Research highlights: → FL-MPPT controller is implemented on FPGA. → Results obtained with ModelSim show a satisfactory performance. → Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

FPGA-based implementation of a fuzzy controller (MPPT) for photovoltaic module

Energy Technology Data Exchange (ETDEWEB)

Messai, A. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mellit, A., E-mail: a.mellit@yahoo.co.u [Department of Electronics, Faculty of Sciences and Technology, Jijel University, Ouled-aissa, P.O. Box 98, Jijel 18000 (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Massi Pavan, A. [Department of Materials and Natural Resources, University of Trieste, Via A. Valerio, 2 - 34127 Trieste (Italy); Guessoum, A. [Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria); Mekki, H. [CRNB Ain Oussera, P.O. Box 180, 17200, Djelfa (Algeria); Department of Electronics, Faculty of Sciences Engineering, Blida University, Blida 90000 (Algeria)

2011-07-15

Research highlights: {yields} FL-MPPT controller is implemented on FPGA. {yields} Results obtained with ModelSim show a satisfactory performance. {yields} Results will be useful for future development in PV. -- Abstract: This paper describes the hardware implementation of a two-inputs one-output digital Fuzzy Logic Controller (FLC) on a Xilinx reconfigurable Field-Programmable Gate Array (FPGA) using VHDL Hardware Description Language. The FLC is designed for seeking the maximum power point deliverable by a photovoltaic module using the measures of the photovoltaic current and voltage. The simulation results obtained with ModelSim Xilinx Edition-III show a satisfactory performance with a good agreement between the expected and the obtained values.

VHDL, FPGA and the master trigger controller of BES

International Nuclear Information System (INIS)

Guo Yanan; Wang Jufang; Zhao Dixin

1996-01-01

A Master Trigger Controller was made using fast FPGA (Field-Programmable Gate Array) instead of ECLIC (Emitter-Coupled Logic Integrated Circuit). VHDL (Verilog Hardware Description Language) was used in its design. The same performance was obtained with increased flexibility

Performance enhancement of multi-core fiber transmission using real-time FPGA based pre-emphasis

DEFF Research Database (Denmark)

Hasanuzzaman, G. K.M.; Spolitis, Sandis; Salgals, T.

2017-01-01

We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA.......We experimentally demonstrate pre-emphasis based performance for a 2 km long 7-core multicore fiber link. Simultaneous transmission below the FEC threshold is achievable for all cores by using signal equalization in a FPGA....

Acceleration of Cherenkov angle reconstruction with the new Intel Xeon/FPGA compute platform for the particle identification in the LHCb Upgrade

Science.gov (United States)

Faerber, Christian

2017-10-01

The LHCb experiment at the LHC will upgrade its detector by 2018/2019 to a ‘triggerless’ readout scheme, where all the readout electronics and several sub-detector parts will be replaced. The new readout electronics will be able to readout the detector at 40 MHz. This increases the data bandwidth from the detector down to the Event Filter farm to 40 TBit/s, which also has to be processed to select the interesting proton-proton collision for later storage. The architecture of such a computing farm, which can process this amount of data as efficiently as possible, is a challenging task and several compute accelerator technologies are being considered for use inside the new Event Filter farm. In the high performance computing sector more and more FPGA compute accelerators are used to improve the compute performance and reduce the power consumption (e.g. in the Microsoft Catapult project and Bing search engine). Also for the LHCb upgrade the usage of an experimental FPGA accelerated computing platform in the Event Building or in the Event Filter farm is being considered and therefore tested. This platform from Intel hosts a general CPU and a high performance FPGA linked via a high speed link which is for this platform a QPI link. On the FPGA an accelerator is implemented. The used system is a two socket platform from Intel with a Xeon CPU and an FPGA. The FPGA has cache-coherent memory access to the main memory of the server and can collaborate with the CPU. As a first step, a computing intensive algorithm to reconstruct Cherenkov angles for the LHCb RICH particle identification was successfully ported in Verilog to the Intel Xeon/FPGA platform and accelerated by a factor of 35. The same algorithm was ported to the Intel Xeon/FPGA platform with OpenCL. The implementation work and the performance will be compared. Also another FPGA accelerator the Nallatech 385 PCIe accelerator with the same Stratix V FPGA were tested for performance. The results show that the Intel

Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

Science.gov (United States)

Xia, Fei; Jin, Guoqing

2014-06-01

PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

Parallel Hough Transform-Based Straight Line Detection and Its FPGA Implementation in Embedded Vision

Directory of Open Access Journals (Sweden)

Nam Ling

2013-07-01

Full Text Available Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

Remote monitoring and fault recovery for FPGA-based field controllers of telescope and instruments

Science.gov (United States)

Zhu, Yuhua; Zhu, Dan; Wang, Jianing

2012-09-01

As the increasing size and more and more functions, modern telescopes have widely used the control architecture, i.e. central control unit plus field controller. FPGA-based field controller has the advantages of field programmable, which provide a great convenience for modifying software and hardware of control system. It also gives a good platform for implementation of the new control scheme. Because of multi-controlled nodes and poor working environment in scattered locations, reliability and stability of the field controller should be fully concerned. This paper mainly describes how we use the FPGA-based field controller and Ethernet remote to construct monitoring system with multi-nodes. When failure appearing, the new FPGA chip does self-recovery first in accordance with prerecovery strategies. In case of accident, remote reconstruction for the field controller can be done through network intervention if the chip is not being restored. This paper also introduces the network remote reconstruction solutions of controller, the system structure and transport protocol as well as the implementation methods. The idea of hardware and software design is given based on the FPGA. After actual operation on the large telescopes, desired results have been achieved. The improvement increases system reliability and reduces workload of maintenance, showing good application and popularization.

Parallel Hough Transform-based straight line detection and its FPGA implementation in embedded vision.

Science.gov (United States)

Lu, Xiaofeng; Song, Li; Shen, Sumin; He, Kang; Yu, Songyu; Ling, Nam

2013-07-17

Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA) provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT) and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

National Research Council Canada - National Science Library

Bardouleau, Graham; Kulp, James

2005-01-01

In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment...

Pensamiento computacional: rompiendo brechas digitales y educativas

Directory of Open Access Journals (Sweden)

Mauricio Javier Rico

2018-03-01

Full Text Available Este artículo describe una iniciativa pragmática de colaboración internacional en el ámbito de la formación del Pensamiento Computacional de los jóvenes estudiantes de Colombia. El proyecto “Introducción del Pensamiento Computacional en las escuelas de Bogotá y Colombia” (RENATA/EHU involucra el pensamiento computacional en el currículo escolar de una manera asequible y eficaz para los estudiantes, los docentes y los centros educativos. Las nuevas generaciones de este país tienen ahora la posibilidad de adquirir habilidades del siglo XXI al igual que las nuevas generaciones de otros países donde la computación es parte del currículo educativo desde los primeros años escolares. Este proyecto está en su fase de implementación en escuelas de diferentes regiones de Colombia; puede ser un ejemplo de cómo romper brechas digitales y educativas utilizando las TIC y la educación como principales herramientas de transformación social.

Small Microprocessor for ASIC or FPGA Implementation

Science.gov (United States)

Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

2011-01-01

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

FPGA Implementation of Computer Vision Algorithm

OpenAIRE

Zhou, Zhonghua

2014-01-01

Computer vision algorithms, which play an significant role in vision processing, is widely applied in many aspects such as geology survey, traffic management and medical care, etc.. Most of the situations require the process to be real-timed, in other words, as fast as possible. Field Programmable Gate Arrays (FPGAs) have a advantage of parallelism fabric in programming, comparing to the serial communications of CPUs, which makes FPGA a perfect platform for implementing vision algorithms. The...

Desarrollo de un cuestionario para estimar las habilidades digitales de estudiantes universitarios

Directory of Open Access Journals (Sweden)

Javier Organista-Sandoval

2017-01-01

Full Text Available El propósito del artículo es mostrar la ruta metodológica seguida para desarrollar un cuestionario para estimar las habilidades digitales con propósito educativo que tienen los estudiantes de una universidad pública mexicana. Se describe el desarrollo de un cuestionario basado en cuatro dimensiones: manejo de información, de comunicación, de organización y de tecnología portátil. Se recurre a la consulta de expertos para la delimitación de los factores, la elaboración de los reactivos y la estimación de un indicador de univocidad. Se aplica un análisis preliminar basado en modelado estructural de ecuaciones para obtener evidencias de validez de la escala desarrollada. El cuestionario se aplicó al azar a una muestra de 350 estudiantes. Se propuso un modelo conceptual para el constructo de habilidad digital, el cual tuvo la congruencia esperada entre las variables observadas y la estructura propuesta. Tras una primera aplicación se obtuvieron valores aceptables en tres de los índices de bondad de ajuste (RMSEA, GFI y AGFI, con excepción de Chi-cuadrada y se detectaron posibilidades de adecuar la escala con base en los índices de modificación derivados del programa AMOS. La información obtenida permitirá mejorar la escala propuesta. Determinar las habilidades digitales de los estudiantes es un punto de interés actual en la búsqueda de la innovación y eficiencia de las actividades educativas.

Direct Measurement of Power Dissipated by Monte Carlo Simulations on CPU and FPGA Platforms

OpenAIRE

Albicocco, Pietro; Papini, Davide; Nannarelli, Alberto

2012-01-01

In this technical report, we describe how power dissipation measurements on different computing platforms (a desktop computer and an FPGA board) are performed by using a Hall effectbased current sensor. The chosen application is a Monte Carlo simulation for European option pricing which is a popular algorithm used in financial computations. The Hall effect probe measurements complement the measurements performed on the core of the FPGA by a built-in Xilinxpower monitoring system.

Toma de medidas usando fotografías digitales: Repaso experimental a procedimientos existentes, posibles fuentes de error, reproductividad del método y usos potenciales

OpenAIRE

Bustos-Pérez, Guillermo

2016-01-01

El uso de medios digitales para el análisis arqueológico está a la orden del día. Un ejemplo es el uso de fotografías digitales para la obtención de medidas en diferentes objetos. Se presenta aquí un repaso al procedimiento de medida de filos en lascas publicado por Eren et al., (2008), una experiencia de reproductividad del método, y una ampliación experimental de sus potenciales usos para el análisis de industria lítica. Los resultados muestran que se trata de un procedimient...

Using Simulated Partial Dynamic Run-Time Reconfiguration to Share Embedded FPGA Compute and Power Resources across a Swarm of Unpiloted Airborne Vehicles

Directory of Open Access Journals (Sweden)

Kearney David

2007-01-01

Full Text Available We show how the limited electrical power and FPGA compute resources available in a swarm of small UAVs can be shared by moving FPGA tasks from one UAV to another. A software and hardware infrastructure that supports the mobility of embedded FPGA applications on a single FPGA chip and across a group of networked FPGA chips is an integral part of the work described here. It is shown how to allocate a single FPGA's resources at run time and to share a single device through the use of application checkpointing, a memory controller, and an on-chip run-time reconfigurable network. A prototype distributed operating system is described for managing mobile applications across the swarm based on the contents of a fuzzy rule base. It can move applications between UAVs in order to equalize power use or to enable the continuous replenishment of fully fueled planes into the swarm.

OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

Directory of Open Access Journals (Sweden)

Hasitha Muthumala Waidyasooriya

2017-01-01

Full Text Available Finite difference time domain (FDTD method is a very poplar way of numerically solving partial differential equations. FDTD has a low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently, deeply pipelined FPGA accelerators have shown a lot of success by exploiting streaming data flows in FDTD computation. In spite of this success, many FPGA accelerators are not suitable for real-world applications that contain complex boundary conditions. Boundary conditions break the regularity of the data flow, so that the performances are significantly reduced. This paper proposes an FPGA accelerator that computes commonly used absorbing and periodic boundary conditions in many 3D FDTD applications. Accelerator is designed using a “C-like” programming language called OpenCL (open computing language. As a result, the proposed accelerator can be customized easily by changing the software code. According to the experimental results, we achieved over 3.3 times and 1.5 times higher processing speed compared to the CPUs and GPUs, respectively. Moreover, the proposed accelerator is more than 14 times faster compared to the recently proposed FPGA accelerators that are capable of handling complex boundary conditions.

Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

International Nuclear Information System (INIS)

Jinyuan Wu; Zonghan Shi; Irena Y Wang

2003-01-01

A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

Architecture exploration of FPGA based accelerators for bioinformatics applications

CERN Document Server

Varma, B Sharat Chandra; Balakrishnan, M

2016-01-01

This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.

Real-time digital simulation of power electronics systems with Neutral Point Piloted multilevel inverter using FPGA

Energy Technology Data Exchange (ETDEWEB)

Rakotozafy, Mamianja [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France); Poure, Philippe [Laboratoire d' Instrumentation Electronique de Nancy (LIEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Saadate, Shahrokh [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Bordas, Cedric; Leclere, Loic [CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France)

2011-02-15

Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling complexities. Therefore, simulation of fast switching converters' instantaneous models requires smaller computing time step. The approach presented in this paper proposes an answer to such limited modeling accuracies and computational bandwidth of the currently available digital simulators.As an example, the authors present a low cost, flexible and high performance FPGA-based real-time digital simulator for a complete complex power system with Neutral Point Piloted (NPP) three-level inverter. The proposed real-time simulator can model accurately and efficiently the complete power system, reducing costs, physical space and avoiding any damage to the actual equipment in the case of any dysfunction of the digital controller prototype. The converter model is computed at a small fixed time step as low as 100 ns. Such a computation time step allows high precision account of the gating signals and thus avoids averaging methods and event compensations. Moreover, a novel high performance model of the NPP three-level inverter has also been proposed for FPGA implementation. The proposed FPGA-based simulator models the environment of the NPP converter: the dc link, the RLE load and the digital controller and gating signals. FPGA-based real time simulation results are presented and compared with offline results obtained using PLECS software. They validate the efficiency and accuracy of the modeling for the proposed high performance FPGA-based real-time simulation approach. This paper also introduces new potential FPGA-based applications such as low cost real time simulator for power systems by developing a library of flexible and portable models for power converters, electrical machines and drives. (author)

Objetos nómadas digitales: caso de estudio las comunidades shuar ecuatorianas

Directory of Open Access Journals (Sweden)

Yolanda Martinez Suarez

2015-05-01

Full Text Available En este texto focalizaremos la atención hacia los “objetos nómadas” (Lasén, 2006, fundamentalmente, en su versión de teléfono móvil, en el contexto de las comunidades indígenas ecuatorianas shuar meridionales de tradición nómada. La finalidad es analizar los flujos y movilidades, las fricciones y cosmovisiones que estos dispositivos revelan mediante sus usos e imaginarios. A la luz de esto, ¿cómo se apropian los shuar ecuatorianos de las tecnologías móviles digitales?

A FPGA-based signal processing unit for a GEM array detector

International Nuclear Information System (INIS)

Yen, W.W.; Chou, H.P.

2013-06-01

in the present study, a signal processing unit for a GEM one-dimensional array detector is presented to measure the trajectory of photoelectrons produced by cosmic X-rays. The present GEM array detector system has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies. The prototype of the processing unit is implemented using commercial field programmable gate array circuit boards. The FPGA based system is linked to a personal computer for testing and data analysis. Tests using simulated signals indicated that the FPGA-based signal processing unit has a good linearity and is flexible for parameter adjustment for various experimental conditions (authors)

Implementation of the 2-D Wavelet Transform into FPGA for Image

Science.gov (United States)

León, M.; Barba, L.; Vargas, L.; Torres, C. O.

2011-01-01

This paper presents a hardware system implementation of the of discrete wavelet transform algoritm in two dimensions for FPGA, using the Daubechies filter family of order 2 (db2). The decomposition algorithm of this transform is designed and simulated with the Hardware Description Language VHDL and is implemented in a programmable logic device (FPGA) XC3S1200E reference, Spartan IIIE family, by Xilinx, take advantage the parallels properties of these gives us and speeds processing that can reach them. The architecture is evaluated using images input of different sizes. This implementation is done with the aim of developing a future images encryption hardware system using wavelet transform for security information.

Implementation of the 2-D Wavelet Transform into FPGA for Image

Energy Technology Data Exchange (ETDEWEB)

Leon, M; Barba, L; Vargas, L; Torres, C O, E-mail: madeleineleon@unicesar.edu.co [Laboratorio de Optica e Informatica, Universidad Popular del Cesar, Sede balneario Hurtado, Valledupar, Cesar (Colombia)

2011-01-01

This paper presents a hardware system implementation of the of discrete wavelet transform algorithm in two dimensions for FPGA, using the Daubechies filter family of order 2 (db2). The decomposition algorithm of this transform is designed and simulated with the Hardware Description Language VHDL and is implemented in a programmable logic device (FPGA) XC3S1200E reference, Spartan IIIE family, by Xilinx, take advantage the parallels properties of these gives us and speeds processing that can reach them. The architecture is evaluated using images input of different sizes. This implementation is done with the aim of developing a future images encryption hardware system using wavelet transform for security information.

Modelo de gestión de objetos digitales para la gestión de soluciones tecnológicas/Digital object management model for the management of technological solutions

OpenAIRE

Dayni Pérez-Hernández; Martha Dunia Delgado-Dapena

2013-01-01

En los últimos años se ha incrementado el uso y el volumen de los contenidos digitales en lasdiferentes organizaciones, los cuales requieren de un tratamiento y gestión que se adecúe a laelevada complejidad tecnológica existente. Las herramientas desarrolladas bajo este contexto sehan denominado Sistemas de Gestión de Contenidos o Gestores de Contenidos. Algunos sistemasextienden sus funcionalidades, debido a la necesidad de garantizar en todas las dimensiones lagestión de Objetos Digitales. ...

Signal compression in radar using FPGA

Directory of Open Access Journals (Sweden)

Enrique Escamilla Hemández

2010-01-01

Full Text Available El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array. El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR. El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde nos centramos en obtener una mejor atenuación para los valores de lóbulos laterales. La arquitectura propuesta explota los recursos de computación paralela de los dispositivos FPGA para alcanzar una mejor velocidad de cómputo. Las investigaciones experimentales han demostrado que los mejores resultados para el funcionamiento de la compresión del pulso se han obtenido usando las funciones atómicas, mejorando el funcionamiento del sistema del radar en presencia de ruido, y consiguiendo una pequeña degradación en la resolución de rango. La puesta en práctica del tratamiento de señales en el sistema de radar en tiempo real se discute y se justifica la eficiencia de la arquitectura de hardware propuesta.

Wire Position Monitoring with FPGA based Electronics

International Nuclear Information System (INIS)

Eddy, N.; Lysenko, O.

2009-01-01

This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. An FPGA based digitizer

An efficient HW and SW design of H.264 video compression, storage and playback on FPGA devices for handheld thermal imaging systems

Science.gov (United States)

Gunay, Omer; Ozsarac, Ismail; Kamisli, Fatih

2017-05-01

Video recording is an essential property of new generation military imaging systems. Playback of the stored video on the same device is also desirable as it provides several operational benefits to end users. Two very important constraints for many military imaging systems, especially for hand-held devices and thermal weapon sights, are power consumption and size. To meet these constraints, it is essential to perform most of the processing applied to the video signal, such as preprocessing, compression, storing, decoding, playback and other system functions on a single programmable chip, such as FPGA, DSP, GPU or ASIC. In this work, H.264/AVC (Advanced Video Coding) compatible video compression, storage, decoding and playback blocks are efficiently designed and implemented on FPGA platforms using FPGA fabric and Altera NIOS II soft processor. Many subblocks that are used in video encoding are also used during video decoding in order to save FPGA resources and power. Computationally complex blocks are designed using FPGA fabric, while blocks such as SD card write/read, H.264 syntax decoding and CAVLC decoding are done using NIOS processor to benefit from software flexibility. In addition, to keep power consumption low, the system was designed to require limited external memory access. The design was tested using 640x480 25 fps thermal camera on CYCLONE V FPGA, which is the ALTERA's lowest power FPGA family, and consumes lower than 40% of CYCLONE V 5CEFA7 FPGA resources on average.

fpga controller design and simulation of a portable dough mixing

African Journals Online (AJOL)

modelled and simulated with Matlab/Simulink. Synthesizable VHDL ... Keywords: FPGA, VHDL, PID controller, Pulse Width Modulation, Full H-Bridge DC motor driver. 1. ... and (b) to simulate the control process in a virtual environment, using.

Real-time distortion correction for visual inspection systems based on FPGA

Science.gov (United States)

Liang, Danhua; Zhang, Zhaoxia; Chen, Xiaodong; Yu, Daoyin

2008-03-01

Visual inspection is a kind of new technology based on the research of computer vision, which focuses on the measurement of the object's geometry and location. It can be widely used in online measurement, and other real-time measurement process. Because of the defects of the traditional visual inspection, a new visual detection mode -all-digital intelligent acquisition and transmission is presented. The image processing, including filtering, image compression, binarization, edge detection and distortion correction, can be completed in the programmable devices -FPGA. As the wide-field angle lens is adopted in the system, the output images have serious distortion. Limited by the calculating speed of computer, software can only correct the distortion of static images but not the distortion of dynamic images. To reach the real-time need, we design a distortion correction system based on FPGA. The method of hardware distortion correction is that the spatial correction data are calculated first under software circumstance, then converted into the address of hardware storage and stored in the hardware look-up table, through which data can be read out to correct gray level. The major benefit using FPGA is that the same circuit can be used for other circularly symmetric wide-angle lenses without being modified.

A PMSM current controller system on FPGA platform | Ahmadian ...

African Journals Online (AJOL)

Journal of Fundamental and Applied Sciences ... Proposed system architecture and computational blocks are described and system level and RTL simulation results are presented. Simulation results show that the total computation cycle time of implemented system on Altera Cyclone II FPGA is 456ns. Keywords: PMSM ...

N queens on an fpga: mathematics,programming, or both?

NARCIS (Netherlands)

Kuper, Jan; Wester, Rinse

2014-01-01

This paper presents a design methodology for deriving an FPGA implementation directly from a mathematical specification, thus avoiding the switch in semantic perspective as is present in widely applied methods which include an imperative implementation as an intermediate step. The first step in the

Effective and efficient FPGA synthesis through general functional decomposition

NARCIS (Netherlands)

Jozwiak, L.; Slusarczyk, A.S.; Chojnacki, A.

2003-01-01

In this paper, a new information-driven circuit synthesis method is discussed that targets LUT-based FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The method is based on the bottom–up general functional decomposition and theory of information relationship measures that we

FPGA-based implementation of sorting networks in MMC applications

DEFF Research Database (Denmark)

Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

2016-01-01

, and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance...

An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm

Directory of Open Access Journals (Sweden)

Peter Irgens

2017-04-01

Full Text Available We present an field programmable gate arrays (FPGA based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping.

Implementació d'una Cache per a un processador MIPS d'una FPGA

OpenAIRE

Riera Villanueva, Marc

2013-01-01

[CATALÀ] Primer s'explicarà breument l'arquitectura d'un MIPS, la jerarquia de memòria i el funcionament de la cache. Posteriorment s'explicarà com s'ha dissenyat i implementat una jerarquia de memòria per a un MIPS implementat en VHDL en una FPGA. [ANGLÈS] First, the MIPS architecture, memory hierarchy and the functioning of the cache will be explained briefly. Then, the design and implementation of a memory hierarchy for a MIPS processor implemented in VHDL on an FPGA will be explained....

Advanced Image Processing Package for FPGA-Based Re-Programmable Miniature Electronics

National Research Council Canada - National Science Library

Ovod, Vladimir I; Baxter, Christopher R; Massie, Mark A; McCarley, Paul L

2005-01-01

.... An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical background...

Modelado de acervos en bibliotecas digitales

Directory of Open Access Journals (Sweden)

Carlos Proal A.

2004-01-01

Full Text Available Este artículo expone los distintos tipos de datos que son comunes en una biblioteca digital, así como las técnicas y herramientas para su manipulación. Se considera la diversidad de recursos y servicios que las conforman por lo que se proponen modelos alternativos para almacenamiento y recuperación de información, los cuales mejoran la extensión y desempeño tanto en las colecciones como en los servicios desarrollados para su manejo. En particular, estas propuestas permiten integrar por primera vez en una sola biblioteca digital, datos estructurados, semiestructurados y no estructurados. La idea de modelos de datos está basada en las experiencias de desarrollo y uso de las bibliotecas digitales, cuya arquitectura ha evolucionado en un escenario real durante casi cuatro años. Se describe la integración de nuevos componentes y servicios para la recuperación de información, los cuales extienden y armonizan con la estructura actual. Finalmente se mencionan las evaluaciones que se obtuvieron al analizar las ventajas y desventajas de la incorporación y combinación de estos servicios, así como del uso de los modelos alternativos propuestos.

FPGA-based Upgrade to RITS-6 Control System, Designed with EMP Considerations

International Nuclear Information System (INIS)

Anderson, Harold D.; Williams, John T.

2009-01-01

The existing control system for the RITS-6, a 20-MA 3-MV pulsed-power accelerator located at Sandia National Laboratories, was built as a system of analog switches because the operators needed to be close enough to the machine to hear pulsed-power breakdowns, yet the electromagnetic pulse (EMP) emitted would disable any processor-based solutions. The resulting system requires operators to activate and deactivate a series of 110-V relays manually in a complex order. The machine is sensitive to both the order of operation and the time taken between steps. A mistake in either case would cause a misfire and possible machine damage. Based on these constraints, a field-programmable gate array (FPGA) was chosen as the core of a proposed upgrade to the control system. An FPGA is a series of logic elements connected during programming. Based on their connections, the elements can mimic primitive logic elements, a process called synthesis. The circuit is static; all paths exist simultaneously and do not depend on a processor. This should make it less sensitive to EMP. By shielding it and using good electromagnetic interference-reduction practices, it should continue to operate well in the electrically noisy environment. The FPGA has two advantages over the existing system. In manual operation mode, the synthesized logic gates keep the operators in sequence. In addition, a clock signal and synthesized countdown circuit provides an automated sequence, with adjustable delays, for quickly executing the time-critical portions of charging and firing. The FPGA is modeled as a set of states, each state being a unique set of values for the output signals. The state is determined by the input signals, and in the automated segment by the value of the synthesized countdown timer, with the default mode placing the system in a safe configuration. Unlike a processor-based system, any system stimulus that results in an abort situation immediately executes a shutdown, with only a tens

FPGA implementation of a hybrid on-line process monitoring in PC based real-time systems

Directory of Open Access Journals (Sweden)

Jovanović Bojan

2011-01-01

Full Text Available This paper presents one way of FPGA implementation of hybrid (hardware-software based on-line process monitoring in Real-Time systems (RTS. The reasons for RTS monitoring are presented at the beginning. The summary of different RTS monitoring approaches along with its advantages and drawbacks are also exposed. Finally, monitoring module is described in details. Also, FPGA implementation results and some useful monitoring system applications are mentioned.

FPGA Implementation of a Simple 3D Graphics Pipeline

Directory of Open Access Journals (Sweden)

Vladimir Kasik

2015-01-01

Full Text Available Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGA-based implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance Computing.

Los Objetos de Aprendizaje del Portal Educ.ar: inclusión de tecnologías digitales en materiales didácticos de Lengua y Literatura

Directory of Open Access Journals (Sweden)

Alejo Ezequiel González López Ledesma

2016-06-01

Full Text Available En este estudio se presentan los primeros avances de una investigación de tesis de maestría cuyo tema es la inclusión de tecnologías digitales en los materiales didácticos de Lengua y Literatura del Portal Educ.ar dedicados a la enseñanza de la escritura. A lo largo de este trabajo, expondremos nuestro marco teórico, que incorpora las discusiones en torno a los materiales didácticos que incluyen tecnologías digitales y el enfoque sobre la enseñanza de la escritura que guía nuestro análisis. Luego, detallaremos la metodología utilizada y expondremos los resultados de nuestro análisis a partir de una serie de ejemplos representativos de la muestra seleccionada. De este modo, buscaremos dar cuenta de la forma en que un enfoque didáctico-disciplinar puede arrojar luz sobre las posibilidades que ofrece la inclusión de tecnologías digitales para la enseñanza de la escritura en el marco de las propuestas de los materiales didácticos.

SEU mitigation technique by Dynamic Reconfiguration method in FPGA based DSP application

International Nuclear Information System (INIS)

Dey, Madhusudan; Singh, Abhishek; Roy, Amitava

2012-01-01

Field Programmable Gate Array (FPGA), an SRAM based configurable devices meant for implementation of any digital circuits is susceptible to malfunction in the harsh radiation environment. It causes the corruption of the configuration memory of FPGA and the digital circuits starts malfunctioning. There is a need to restore the system as early as possible. This paper discusses about one such technique named dynamic partial reconfiguration (DPR) method. This paper also touches upon the signal processing by DPR method. The framework consisting of ADC, DAC and ICAP controllers designed using dedicated state machines to study the best possible downtime also for verifying the performance of digital filters for signal processing

Integration of multi-interface conversion channel using FPGA for modular photonic network

Science.gov (United States)

Janicki, Tomasz; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.

2010-09-01

The article discusses the integration of different types of interfaces with FPGA circuits using a reconfigurable communication platform. The solution has been implemented in practice in a single node of a distributed measurement system. Construction of communication platform has been presented with its selected hardware modules, described in VHDL and implemented in FPGA circuits. The graphical user interface (GUI) has been described that allows a user to control the operation of the system. In the final part of the article selected practical solutions have been introduced. The whole measurement system resides on multi-gigabit optical network. The optical network construction is highly modular, reconfigurable and scalable.

Implementation of FPGA based PID Controller for DC Motor Speed Control System

Directory of Open Access Journals (Sweden)

Savita SONOLI

2010-03-01

Full Text Available In this paper, the implementation of software module using ‘VHDL’ for Xilinx FPGA (XC3S400 based PID controller for DC motor speed control system is presented. The tools used for building and testing the software modules are Xilinx ISE 9.2i and ModelSim XE III 6.3c. Before verifying the design on FPGA the complete design is simulated using Modelsim Simulation tool. A test bench is written where the set speed can be changed for the motor. It is observed that the motor speed gradually changes to the set speed and locks to the set speed.

An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

International Nuclear Information System (INIS)

Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah; Choi, Jong Gyun

2014-01-01

NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity

An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

Energy Technology Data Exchange (ETDEWEB)

Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun [KAERI, Daejeon (Korea, Republic of)

2014-08-15

NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity.

Elaboración de mapas digitales de inundación por tsunamis para Machala y Salinas basados en el tsunami histórico de 1953

OpenAIRE

Rentería, W.

2007-01-01

Para la generación de mapas digitales de inundación es necesario tener presente los conceptos de cartografía y modelación numérica de tsunamis, usando como nexo a los Sistemas de Información Geográfica (SIG). La utilización SIG no es nuevo en el modelamiento de tsunamis, sin embargo el uso general de esta técnica en países como el Ecuador es reciente. Por esta razón, como contribución a la determinación del riesgo por tsunamis, se presenta esta metodología para elaborar cartas digitales de in...

An Intelligent FPGA Based Anti-Sweating System for Bed Sore Prevention in a Clinical Environment

Directory of Open Access Journals (Sweden)

K. S. Jaichandar

2011-01-01

Full Text Available Bed sores, a common problem among immobile patients occur as a result of continuous sweating due to increase in skin to bed surface temperature in patients lying on same posture for prolonged period. If left untreated, the skin can break open and become infected. Currently adopted methods for bed sores prevention include: use of two hourly flip chat for repositioning patient or use of air fluidized beds. However, the setbacks of these preventive measures include either use of costly equipment or wastage of human resources. This paper introduces an intelligent low cost FPGA based anti-sweating system for bed sores prevention in a clinical environment. The developed system consists of bed surface implanted temperature sensors interfaced with an FPGA chip for sensing the temperature change in patient’s skin to bed surface. Based on the temperature change, the FPGA chip select the - mode (heater/cooler and speed of the fan module. Furthermore, an alarm module was implemented to alert the nurse to reposition the patient only if patient’s skin to bed surface temperature exceeds a predefined threshold thereby saving human resources. By integrating the whole system into a single FPGA chip, we were able to build a low cost compact system without sacrificing processing power and flexibility.

A Signature-Based Power Model for MPSoC on FPGA

Directory of Open Access Journals (Sweden)

Roberta Piscitelli

2012-01-01

Full Text Available This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

Embedded System Implementation on FPGA System With μCLinux OS

International Nuclear Information System (INIS)

Amin, Ahmad Fairuz Muhd; Aris, Ishak; Abdullah, Raja Syamsul Azmir Raja; Sahbudin, Ratna Kalos Zakiah

2011-01-01

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

Embedded System Implementation on FPGA System With μCLinux OS

Science.gov (United States)

Fairuz Muhd Amin, Ahmad; Aris, Ishak; Syamsul Azmir Raja Abdullah, Raja; Kalos Zakiah Sahbudin, Ratna

2011-02-01

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

Embedded System Implementation on FPGA System With {mu}CLinux OS

Energy Technology Data Exchange (ETDEWEB)

Amin, Ahmad Fairuz Muhd [Institute of Advanced Technology, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Aris, Ishak [Department of Electrical and Electronic Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor (Malaysia); Abdullah, Raja Syamsul Azmir Raja; Sahbudin, Ratna Kalos Zakiah, E-mail: gs20613@mutiara.upm.edu.my, E-mail: ishak@eng.upm.edu.my, E-mail: rsa@eng.upm.edu.my [Department of Computer and Communication Systems Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor (Malaysia)

2011-02-15

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), {mu}Clinux. In this paper, an example of web server is explained and demonstrated

Research on acceleration method of reactor physics based on FPGA platforms

International Nuclear Information System (INIS)

Li, C.; Yu, G.; Wang, K.

2013-01-01

The physical designs of the new concept reactors which have complex structure, various materials and neutronic energy spectrum, have greatly improved the requirements to the calculation methods and the corresponding computing hardware. Along with the widely used parallel algorithm, heterogeneous platforms architecture has been introduced into numerical computations in reactor physics. Because of the natural parallel characteristics, the CPU-FPGA architecture is often used to accelerate numerical computation. This paper studies the application and features of this kind of heterogeneous platforms used in numerical calculation of reactor physics through practical examples. After the designed neutron diffusion module based on CPU-FPGA architecture achieves a 11.2 speed up factor, it is proved to be feasible to apply this kind of heterogeneous platform into reactor physics. (authors)

Modified SURF Algorithm Implementation on FPGA For Real-Time Object Tracking

Directory of Open Access Journals (Sweden)

Tomyslav Sledevič

2013-05-01

Full Text Available The paper describes the FPGA-based implementation of the modified speeded-up robust features (SURF algorithm. FPGA was selected for parallel process implementation using VHDL to ensure features extraction in real-time. A sliding 84×84 size window was used to store integral pixels and accelerate Hessian determinant calculation, orientation assignment and descriptor estimation. The local extreme searching was used to find point of interest in 8 scales. The simplified descriptor and orientation vector were calculated in parallel in 6 scales. The algorithm was investigated by tracking marker and drawing a plane or cube. All parts of algorithm worked on 25 MHz clock. The video stream was generated using 60 fps and 640×480 pixel camera.Article in Lithuanian

Analysis of Thermal Stability of Different Counter on 28nm FPGA

DEFF Research Database (Denmark)

Gupta, Daizy; Yadav, Amit; Hussain, Dil muhammed Akbar

2016-01-01

In this paper we are presenting the power analysis for thermal awareness of different counters. The technique we are using to do the analysis is based on 28 nm FPGA tech-nique. In this work during implementation on FPGA, we are going to analyze thermal stability of different counters in temperatu...... range of 10oC, 30oC, 60oC, 90oC, 120oC. There is 90.36% reduction in leakage power of divide by 2 counter when we scale down the temperature from 120oC to 10oC and 49.61% reduction in leakage power of LFSR up counter when we scale down the temperature from 120oC to 10oC....

Spacewire Routers Implemented with FPGA Technology

Science.gov (United States)

Habinc, Sandi; Isomaki, Marko

2011-08-01

Routers are an integral part of SpaceWire networks. Aeroflex Gaisler has developed a highly configurable SpaceWire router VHDL IP core to meet the needs for technology independent router designs. The main design goals have been configurability, technology independence, support of the standard and expandability. The IP core being technologically independent allows it to be used in both ASIC and FPGA technology. The latter is now being used to produce versatile standard products that can reach the market faster than for example an ASIC based product.

Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation

Science.gov (United States)

Yokoyama, Yoshiaki; Kim, Minseok; Arai, Hiroyuki

At present, when using space-time processing techniques with multiple antennas for mobile radio communication, real-time weight adaptation is necessary. Due to the progress of integrated circuit technology, dedicated processor implementation with ASIC or FPGA can be employed to implement various wireless applications. This paper presents a resource and performance evaluation of the QRD-RLS systolic array processor based on fixed-point CORDIC algorithm with FPGA. In this paper, to save hardware resources, we propose the shared architecture of a complex CORDIC processor. The required precision of internal calculation, the circuit area for the number of antenna elements and wordlength, and the processing speed will be evaluated. The resource estimation provides a possible processor configuration with a current FPGA on the market. Computer simulations assuming a fading channel will show a fast convergence property with a finite number of training symbols. The proposed architecture has also been implemented and its operation was verified by beamforming evaluation through a radio propagation experiment.

Design issues on using FPGA-based I and C systems in nuclear reactors

Energy Technology Data Exchange (ETDEWEB)

Farias, Marcos S.; Carvalho, Paulo Victor R. de; Santos, Isaac Jose A.L. dos; Lacerda, Fabio de, E-mail: msantana@ien.gov.br, E-mail: paulov@ien.gov.br, E-mail: luquetti@ien.gov.br, E-mail: acerda@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Div. de Engenharia Nuclear

2015-07-01

The FPGA (field programmable gate array) is widely used in various fields of industry. FPGAs can be used to perform functions that are safety critical and require high reliability, like in automobiles, aircraft control and assistance and mission-critical applications in the aerospace industry. With these merits, FPGAs are receiving increased attention worldwide for application in nuclear plant instrumentation and control (I and C) systems, mainly for Reactor Protection System (RPS). Reasons for this include the fact that conventional analog electronics technologies are become obsolete. I and C systems of new Reactors have been designed to adopt the digital equipment such as PLC (Programmable Logic Controller) and DCS (Distributed Control System). But microprocessors-based systems may not be simply qualified because of its complex characteristics. For example, microprocessor cores execute one instruction at a time, and an operating system is needed to manage the execution of programs. In turn, FPGAs can run without an operating system and the design architecture is inherently parallel. In this paper we aim to assess these and other advantages, and the limitations, on FPGA-based solutions, considering the design guidelines and regulations on the use of FPGAs in Nuclear Plant I and C Systems. We will also examine some circuit design techniques in FPGA to help mitigate failures and provide redundancy. The objective is to show how FPGA-based systems can provide cost-effective options for I and C systems in modernization projects and to the RMB (Brazilian Multipurpose Reactor), ensuring safe and reliable operation, meeting licensing requirements, such as separation, redundancy and diversity. (author)

Realization of manchester encoding and decoding and fast-speed communication for digital power supply based on FPGA

International Nuclear Information System (INIS)

Chen Huanguang; Xu Ruinian; Shen Tianjian; Li Deming

2008-01-01

A design and simulation to realize the process of Manchester encoding and decoding, to realize the process of SPI communication between FPGA and DSP, using Altera company's Quartus II IDE on FPGA is presented in this paper. And the application on the digital power supply controller with Manchester communication by optical fiber is introduced. (authors)

Publicidad dinámica y plataformas digitales: brand placement en espacios públicos y transmisiones deportivas en televisión

OpenAIRE

Ortiz Sobrino, Miguel Ángel; Montemayor Ruiz, Francisco Javier

2014-01-01

Las imágenes virtuales, la publicidad digital dinámica multimedia diseñada para espacios públicos y las plataformas digitales utilizadas en las transmisiones deportivas en televisión son hoy herramientas esenciales para la estrategia del emplazamiento de las marcas publicitarias.

Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

Directory of Open Access Journals (Sweden)

Alisson C. D. de Souza

2014-09-01

Full Text Available This paper proposes a parallel fixed point radial basis function (RBF artificial neural network (ANN, implemented in a field programmable gate array (FPGA trained online with a least mean square (LMS algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx, with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.

TESLA cavity modeling and digital implementation in FPGA technology for control system development

International Nuclear Information System (INIS)

Czarski, T.; Pozniak, K.T.; Romaniuk, R.S.; Simrock, S.

2006-01-01

The electromechanical model of the TESLA cavity has been implemented in FPGA technology for real-time testing of the control system. The model includes Lorentz force detuning and beam loading effects. Step operation and vector stimulus operation modes are applied for the evaluation of a FPGA cavity simulator operated by a digital controller. The performance of the cavity hardware model is verified by comparing with a software model of the cavity implemented in the MATLAB system. The numerical aspects are considered for an optimal DSP calculation. Some experimental results are presented for different cavity operational conditions. (orig.)

Deshidratación de etanol empleando líquidos iónicos de naturaleza prótica

OpenAIRE

Acosta Cordero, L.; Pérez Ones, O.; Zumalacárregui de Cárdenas, L.

2017-01-01

En este trabajo se presenta el estudio experimental de la deshidratación de etanol empleando líquidos iónicos de naturaleza prótica, con el objetivo de determinar un líquido iónico prótico efectivo en este proceso de separación. Para ello se sintetizaron tres líquidos iónicos (formiato de 2-hidroxietilamonio, lactato de2-hidroxietilamonio y propionato de 2-hidroxietilamonio) y se determinaron sus propiedades críticas y densidad apartir de métodos de contribución de grupos. Además se confirmó ...

Cómo una microempresa logró un desarrollo de productos ágil y generador de valor empleando Lean

OpenAIRE

Barón Maldonado, Diana Isabel; Rivera Cadavid, Leonardo

2014-01-01

El propósito del presente artículo es mostrar un ejemplo de cómo una microempresa puede hacer que su desarrollo de productos sea más ágil, flexible y generador de valor empleando Lean. Se tomaron como referentes el proceso genérico de desarrollo de productos, el proceso de desarrollo tradicional en el sector de confecciones, el sistema Toyota de desarrollo de productos y el antiguo sistema de desarrollo de la empresa. Se destacan el rol del lugar de reunión virtual y el papel del ingeniero je...

Cómo una microempresa logró un desarrollo de productos ágil y generador de valor empleando Lean

OpenAIRE

Barón Maldonado, Diana Isabel; Rivera Cadavid, Leonardo

2014-01-01

El propósito del presente artículo es mostrar un ejemplo de cómo una microempresa puede hacer que su desarrollo de productos sea más ágil, flexible y generador de valor empleando Lean. Se tomaron como referentes el proceso genérico de desarrollo de productos, el proceso de desarrollo tradicional en el sector de confecciones, el sistema Toyota de desarrollo de productos y el antiguo sistema de desarrollo de la empresa. Se destacan el rol del lugar de reunión virtual y el papel del ...

Design and implementation of a programming circuit in radiation-hardened FPGA

International Nuclear Information System (INIS)

Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Chen, Stanley L.

2011-01-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 x 10 5 rad(Si), dose rate survivability of 1.5 x 10 11 rad(Si)/s and neutron fluence immunity of 1 x 10 14 n/cm 2 .

A low-cost, FPGA-based servo controller with lock-in amplifier

International Nuclear Information System (INIS)

Yang, G; Barry, J F; Shuman, E S; Steinecker, M H; DeMille, D

2012-01-01

We describe the design and implementation of a low-cost, FPGA-based servo controller with an integrated waveform synthesizer and lock-in amplifier. This system has been designed with the specific application of laser frequency locking in mind but should be adaptable to a variety of other purposes as well. The system incorporates an onboard waveform synthesizer, a lock-in amplifier, two channels of proportional-integral (PI) servo control, and a ramp generator on a single FPGA chip. The system is based on an inexpensive, off-the-shelf FPGA evaluation board with a wide variety of available accessories, allowing the system to interface with standard laser controllers and detectors while minimizing the use of custom hardware and electronics. Gains, filter constants, and other relevant parameters are adjustable via onboard knobs and switches. These parameters and other information are displayed to the user via an integrated LCD, allowing full operation of the device without an accompanying computer. We demonstrate the performance of the system in a test setup, in which the frequency of a tunable external-cavity diode laser (ECDL) is locked to a resonant optical transmission peak of a Fabry-Perot cavity. In this setup, we achieve a total servo-loop bandwidth of ∼ 7 kHz and achieve locking of the ECDL to the cavity with a full-width-at-half-maximum (FWHM) linewidth of ∼ 200 kHz.

Design and implementation of a programming circuit in radiation-hardened FPGA

Science.gov (United States)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

Junction Temperature Aware Energy Efficient Router Design on FPGA

DEFF Research Database (Denmark)

Thind, Vandana; Sharma, Shivani; Minwer, M H

2015-01-01

Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature...

Neue Möglichkeiten in der archäologischen arbeit durch den Einsatz digitales Bildauswertung und photogrammetrischer Messtechniken

Directory of Open Access Journals (Sweden)

Jan Wesbuer

2005-01-01

Full Text Available Die digitale Bildbearbeitung und die digitale Photogrammetrie haben in den letzten Jahren, neben vielen anderen Gebieten, die Dokumentation von Ausgrabungsstätten beeinflusst. Die Photogrammetrie hat ihren Ursprung in der Vermessungskunde. Sie wird heutzutage in vielen Bereichen der Ingenieurwissenschaften eingesetzt und hat somit viele Schnittbereiche zu angrenzenden wissenschaftlichen Gebieten. In der Archäologie hat sie daher die Möglichkeit, in vielen Bereichen die herkömmliche Geodäsie zu erweitern bzw. neue Möglichkeiten der Visualisierung zu schaffen oder bei der Bildauswertung zu helfen.Durch die Bildbearbeitung ist es heutzutage möglich, schnell und vor Ort die Dokumentation vorzunehmen. Mit ihrer Hilfe können z.B. nicht orthogonale Aufnahmen perspektivisch entzerrt werden, so dass in ihnen wieder gemessen werden kann.Der Artikel unterteilt sich in 3 Bereiche:• als erstes werden die Möglichkeiten der digitalen Bildbearbeitung bzw. Auswertung von Photos dargestellt.• danach wird auf die photogrammetrische Auswertung und Vermessung von Ausgrabungsstätten eingegangen. • und zuletzt werden einige Visualisierungsmöglichkeiten gezeigt, die mit Hilfe der photogrammetrischen Auswertung und 3DModellerstellung realisiert werden können.

A Translator Verification Technique for FPGA Software Development in Nuclear Power Plants

Energy Technology Data Exchange (ETDEWEB)

Kim, Jae Yeob; Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of)

2014-10-15

Although the FPGAs give a high performance than PLC (Programmable Logic Controller), the platform change from PLC to FPGA impose all PLC software engineers give up their experience, knowledge and practices accumulated over decades, and start a new FPGA-based hardware development from scratch. We have researched to fine the solution to this problem reducing the risk and preserving the experience and knowledge. One solution is to use the FBDtoVerilog translator, which translates the FBD programs into behavior-preserving Verilog programs. In general, the PLCs are usually designed with an FBD, while the FPGAs are described with a HDL (Hardware Description Language) such as Verilog or VHDL. Once PLC designer designed the FBD programs, the FBDtoVerilog translates the FBD into Verilog, mechanically. The designers, therefore, need not consider the rest of FPGA development process (e.g., Synthesis and Place and Routing) and can preserve the accumulated experience and knowledge. Even if we assure that the translation from FBD to Verilog is correct, it must be verified rigorously and thoroughly since it is used in nuclear power plants, which is one of the most safety critical systems. While the designer develops the FPGA software with the FBD program translated by the translator, there are other translation tools such as synthesis tool and place and routing tool. This paper also focuses to verify them rigorously and thoroughly. There are several verification techniques for correctness of translator, but they are hard to apply because of the outrageous cost and performance time. Instead, this paper tries to use an indirect verification technique for demonstrating the correctness of translator using the co-simulation technique. We intend to prove only against specific inputs which are under development for a target I and C system, not against all possible input cases.

A Translator Verification Technique for FPGA Software Development in Nuclear Power Plants

International Nuclear Information System (INIS)

Kim, Jae Yeob; Kim, Eui Sub; Yoo, Jun Beom

2014-01-01

Although the FPGAs give a high performance than PLC (Programmable Logic Controller), the platform change from PLC to FPGA impose all PLC software engineers give up their experience, knowledge and practices accumulated over decades, and start a new FPGA-based hardware development from scratch. We have researched to fine the solution to this problem reducing the risk and preserving the experience and knowledge. One solution is to use the FBDtoVerilog translator, which translates the FBD programs into behavior-preserving Verilog programs. In general, the PLCs are usually designed with an FBD, while the FPGAs are described with a HDL (Hardware Description Language) such as Verilog or VHDL. Once PLC designer designed the FBD programs, the FBDtoVerilog translates the FBD into Verilog, mechanically. The designers, therefore, need not consider the rest of FPGA development process (e.g., Synthesis and Place and Routing) and can preserve the accumulated experience and knowledge. Even if we assure that the translation from FBD to Verilog is correct, it must be verified rigorously and thoroughly since it is used in nuclear power plants, which is one of the most safety critical systems. While the designer develops the FPGA software with the FBD program translated by the translator, there are other translation tools such as synthesis tool and place and routing tool. This paper also focuses to verify them rigorously and thoroughly. There are several verification techniques for correctness of translator, but they are hard to apply because of the outrageous cost and performance time. Instead, this paper tries to use an indirect verification technique for demonstrating the correctness of translator using the co-simulation technique. We intend to prove only against specific inputs which are under development for a target I and C system, not against all possible input cases

Hyperchaotic Chameleon: Fractional Order FPGA Implementation

Directory of Open Access Journals (Sweden)

Karthikeyan Rajagopal

2017-01-01

Full Text Available There are many recent investigations on chaotic hidden attractors although hyperchaotic hidden attractor systems and their relationships have been less investigated. In this paper, we introduce a hyperchaotic system which can change between hidden attractor and self-excited attractor depending on the values of parameters. Dynamic properties of these systems are investigated. Fractional order models of these systems are derived and their bifurcation with fractional orders is discussed. Field programmable gate array (FPGA implementations of the systems with their power and resource utilization are presented.

Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

DEFF Research Database (Denmark)

Pandey, Bishwajeet; Jain, Vishal; Sharma, Rashmi

2017-01-01

In this work, we are going to analyze the effect of main supply voltage, auxiliary supply voltage, local voltage of different power bank, and supply voltage in GTX transceiver and BRAM on power dissipation of our FIR design using Verilog during implementation on 28nm FPGA. We have also taken three.......33%, 86%, 90.67%, 65.33%, 52%, and 48.67% reduction in IO power dissipation of FIR Filter design on CSG324 package of Artix-7 FPGA family....

Implementación de un procesador MIPS en una FPGA

OpenAIRE

Guillen Fandos, David

2012-01-01

L'objectiu del projecte és el disseny i implementació d'un computador al voltant d'un processador MIPS. Aquest computador ha de funcionar a una placa de demostració Terasic DE2-115, que disposa d'una FPGA Altera Cyclone IV.

Bayerische Staatsbibliothek Ludwig-Maximilian Universität München Historisches Seminar /Abteilung geschichtliche Wissenschaften, Projektbereich 'Digitale Tafelwerke Pilotprojekt Digitalisierung Sybel/Sickel: "Kaiserurkunden in Abbildungen"

Directory of Open Access Journals (Sweden)

Antonella Ghignoli

2006-12-01

Full Text Available Review of Bayerische Staatsbibliothek Ludwig-Maximilian Universität München Historisches Seminar /Abteilung geschichtliche Wissenschaften, Projektbereich 'Digitale Tafelwerke Pilotprojekt Digitalisierung Sybel/Sickel: "Kaiserurkunden in Abbildungen"

Competencia Digital: Uso y manejo de modelos 3D tridimensionales digitales e impresos en 3D

Directory of Open Access Journals (Sweden)

Jose Luis Saorín

2017-07-01

Full Text Available El uso y manejo de modelos tridimensionales digitales no está concebido dentro de la competencia digital de los currículos de secundaria y Bachillerato. Sin embargo muchos autores relacionan la competencia digital con el manejo de modelos 3D, el modelado 3D y entornos virtuales tridimensionales (Realidad aumentada, virtual,…. En este artículo se presenta un recurso educativo para facilitar el acceso a contenidos didácticos de carácter tridimensional digital y tangible. Determinadas materias precisan de la comprensión e interpretación de conceptos volumétricos: los recursos didácticos innovadores para la edición, visualización e impresión 3D ofrecen una alternativa a las representaciones 2D en los procesos de enseñanza y aprendizaje. En este artículo se describe la creación de un catálogo escultórico que contempla versiones digitales y tangibles de modelos tridimensionales de las esculturas a través de tecnologías innovadoras de bajo coste como la visualización e impresión 3D. La prueba piloto desarrollada con 15 alumnos de bachillerato recoge una alta valoración de los participantes sobre las tecnologías empleadas.

Input/output Buffer based Vedic Multiplier Design for Thermal Aware Energy Efficient Digital Signal Processing on 28nm FPGA

DEFF Research Database (Denmark)

Goswami, Kavita; Pandey, Bishwajeet; Hussain, Dil muhammed Akbar

2016-01-01

Multiplier is used for multiplication of a signal and a constant in digital signal processing (DSP). 28nm technology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and XPower Analyzer. Vedic multiplier gain speed improvements by parallelizing the generation...... Programmable Gate Array (FPGA) in order to reduce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy...... efficient Vedic multiplier.There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7oC, 53.5oC, 40oC and 21oC respectively....

A Sea-of-Gates Style FPGA Placement Algorithm

Directory of Open Access Journals (Sweden)

Kalapi Roy

1996-01-01

Full Text Available Field Programmable Gate Arrays (FPGAs have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool developed specifically for this architecture.

Anti Theft Mechanism Through Face recognition Using FPGA

Science.gov (United States)

Sundari, Y. B. T.; Laxminarayana, G.; Laxmi, G. Vijaya

2012-11-01

The use of vehicle is must for everyone. At the same time, protection from theft is also very important. Prevention of vehicle theft can be done remotely by an authorized person. The location of the car can be found by using GPS and GSM controlled by FPGA. In this paper, face recognition is used to identify the persons and comparison is done with the preloaded faces for authorization. The vehicle will start only when the authorized personís face is identified. In the event of theft attempt or unauthorized personís trial to drive the vehicle, an MMS/SMS will be sent to the owner along with the location. Then the authorized person can alert the security personnel for tracking and catching the vehicle. For face recognition, a Principal Component Analysis (PCA) algorithm is developed using MATLAB. The control technique for GPS and GSM is developed using VHDL over SPTRAN 3E FPGA. The MMS sending method is written in VB6.0. The proposed application can be implemented with some modifications in the systems wherever the face recognition or detection is needed like, airports, international borders, banking applications etc.

FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

Science.gov (United States)

Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

2017-06-01

A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

Application of the Information Encryption Technology in the Industrial Control Network Based on FPGA

Directory of Open Access Journals (Sweden)

Guo Yao-Hua

2014-07-01

Full Text Available With the rapid development of information technology industry, Information encryption is an effective means of information security. Data encryption system based on FPGA in the field of industry is elaborated in this paper, and the data acquisition module, the basic principle of 3DES algorithm, its implementation in FPGA and PMC bus interface module are introduced. Based on the function simulation, test and analysis of the design results, this scheme has the characteristics of high reliability, fast algorithm and less hardware resources, and it can be widely used in industrial networks.

An FPGA-based bolometer for the MAST-U Super-X divertor

Energy Technology Data Exchange (ETDEWEB)

Lovell, Jack, E-mail: jack.lovell@durham.ac.uk [Durham University, South Road, Durham DH1 3LE (United Kingdom); Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Naylor, Graham; Field, Anthony [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Drewelow, Peter [MPI für Plasmaphysik, Greifswald (Germany); Sharples, Ray [Durham University, South Road, Durham DH1 3LE (United Kingdom); Collaboration: EUROfusion Consortium, JET, Culham Science Centre, Abingdon OX14 3DB (United Kingdom)

2016-11-15

A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of the JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.

V&V Plan for FPGA-based ESF-CCS Using System Engineering Approach.

Science.gov (United States)

Maerani, Restu; Mayaka, Joyce; El Akrat, Mohamed; Cheon, Jung Jae

2018-02-01

Instrumentation and Control (I&C) systems play an important role in maintaining the safety of Nuclear Power Plant (NPP) operation. However, most current I&C safety systems are based on Programmable Logic Controller (PLC) hardware, which is difficult to verify and validate, and is susceptible to software common cause failure. Therefore, a plan for the replacement of the PLC-based safety systems, such as the Engineered Safety Feature - Component Control System (ESF-CCS), with Field Programmable Gate Arrays (FPGA) is needed. By using a systems engineering approach, which ensures traceability in every phase of the life cycle, from system requirements, design implementation to verification and validation, the system development is guaranteed to be in line with the regulatory requirements. The Verification process will ensure that the customer and stakeholder’s needs are satisfied in a high quality, trustworthy, cost efficient and schedule compliant manner throughout a system’s entire life cycle. The benefit of the V&V plan is to ensure that the FPGA based ESF-CCS is correctly built, and to ensure that the measurement of performance indicators has positive feedback that “do we do the right thing” during the re-engineering process of the FPGA based ESF-CCS.

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Directory of Open Access Journals (Sweden)

Paolo Meloni

2012-01-01

Full Text Available Application Specific Instruction-set Processors (ASIPs expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

Specification of requirements for the implementation of ASICs and FPGA in instrumentation and control systems important to safety in German NPPs

International Nuclear Information System (INIS)

Schnurer, G.

2007-01-01

This paper gives an overview concerning the design as well as the verification and validation of Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGA) in German NPPs which are applied to carry out I and C functions. The qualification procedures dealt with restricted on ASICs without any microcontroller core. Dependent on the different safety categories, recommendations concerning the qualification level and procedures are elaborated which have to be achieved for ASICs and FPGA. Important aspects within the framework of the expert judgement for upgrading of safety relevant I and C by ASICs and FPGA are dealt with. These aspects are of general character and are mainly focused on suitability test procedures and robustness requirements of ASICs and FPGA

Optical network and FPGA/DSP based control system for free electron laser

International Nuclear Information System (INIS)

Romaniuk, R.S.; Pozniak, K.T.; Czarski, T.; Czuba, K.; Giergusiewicz, W.; Kasprowicz, G.; Koprek, W.

2005-01-01

The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to

Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA

DEFF Research Database (Denmark)

Pandey, Bishwajeet; Rehman, M. Atiqur; Hussain, Dil muhammed Akbar

2016-01-01

, SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA......nm FPGA....

A signature-based power model for MPSoC on FPGA

NARCIS (Netherlands)

Piscitelli, R.; Pimentel, A.D.

2012-01-01

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used

A high-level power model for MPSoC on FPGA

NARCIS (Netherlands)

Piscitelli, R.; Pimentel, A.D.

2012-01-01

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures. As a result, it is capable of achieving good evaluation performance, thereby making the

Controlador empotrado en FPGA para Sistema Inteligente de Transporte

Directory of Open Access Journals (Sweden)

Alejandro José Cabrera Sarmiento

2011-11-01

Full Text Available 1024x768 Normal 0 21 false false false ES X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;} En el presente trabajo se expone la concepción, desarrollo e implementación de un controlador empotrado en un FPGA de Xilinx para ser utilizado en un Sistema Inteligente de Transporte (SIT. La estructura hardware del controlador está basada en la utilización de diversos módulos de propiedad intelectual del sistema de procesamiento MicroBlaze y el soporte de software está basado en la utilización del sistema operativo Petalinux. El controlador empotrado dispone de interfaces Ethernet, USB, UART, SPI e I2C para la comunicación con los diferentes niveles jerárquicos del SIT. Ha sido implementado sobre una placa de desarrollo basada en un FPGA Spartan3E de 1.200 k compuertas, ocupando un 59% de sus recursos configurables. El resto de los recursos disponibles en el FPGA permite, además de la posible actualización del controlador, la implementación hardware de algoritmos que requieren una alta velocidad de procesamiento.

Multirate Digital Filters Based on FPGA and Its Applications

International Nuclear Information System (INIS)

Sharaf El-Din, R.M.A.

2013-01-01

Digital Signal Processing (DSP) is one of the fastest growing techniques in the electronics industry. It is used in a wide range of application fields such as, telecommunications, data communications, image enhancement and processing, video signals, digital TV broadcasting, and voice synthesis and recognition. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high performance DSP systems. The focus of this thesis is on one of the basic DSP functions, namely filtering signals to remove unwanted frequency bands. Multi rate Digital Filters (MDFs) are the main theme here. Theory and implementation of MDF, as a special class of digital filters, will be discussed. Multi rate digital filters represent a class of digital filters having a number of attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. This thesis introduces an efficient FPGA realization of a multi rate decimation filter with narrow pass-band and narrow transition band to reduce the frequency sample rate by factor of 64 for noise thermometer applications. The proposed multi rate decimation filter is composed of three stages; the first stage is a Cascaded Integrator Comb (CIC) decimation filter, the second stage is a two-coefficient Half-Band (HB) filter and the last stage is a sharper transition HB filter. The frequency responses of individual stages as well as the overall filter response have been demonstrated with full simulation using MATLAB. The design and implementation of the proposed MDF on FPGA (XILINX Virtex XCV800 BG432-4), using VHSIC Hardware Description Language (VHDL), has been introduced. The implementation areas of the proposed filter stages are compared. Using CIC-HB technique saves 18% of the design area, compared to using six stages HB decimation filters.

Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

Directory of Open Access Journals (Sweden)

Manuel Saldaña

2012-01-01

Full Text Available Partial reconfiguration (PR is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the system continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this paper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to allow hardware designers to create template bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused for multiple applications. As an example of the generality of this approach, four different applications that use the same template bitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired application engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines. PR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by some examples and preliminary PR overhead measurements.

FPGA based phase detection technique for electron density measurement in SST-1 tokamak

International Nuclear Information System (INIS)

Pramila; Mandaliya, Hitesh; Rajpal, Rachana; Kaur, Rajwinder

2016-01-01

A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper.

FPGA based phase detection technique for electron density measurement in SST-1 tokamak

Energy Technology Data Exchange (ETDEWEB)

Pramila, E-mail: pramila@ipr.res.in; Mandaliya, Hitesh; Rajpal, Rachana; Kaur, Rajwinder

2016-11-15

A multi-channel signal-conditioning and phase-detection concept is implemented in the prototype design using the high-precision OPAMP, high-speed comparators, high Q filters, high-density FPGA (Field Programmable Gate array), 10 MHz parallel-multiplying DACs (Digital to Analog Converter), etc. The complete digital-logic for the phase-detection is implemented inside the logic cells of FPGA using VHDL code, with high speed 100 MHz clock generated from Digital Clock Manager (DCM), which is used to measure the time elapsed between zero crossings of the two signals coming from reference and probe paths of the diagnostics. The logic is implemented to measure either leading or lagging phase and also to accumulate the total phase difference throughout the shot duration with the maximum value of accumulated phase of 5760 (16 cycles × 360°) degree and a resolution of 3.6 °. A precision high speed and high bandwidth (80 MHz) operational amplifiers are used as the front end-electronics component for conditioning the high-frequency (1 MHz) and low amplitude signal (μV). The hardware detail, implementation concept in FPGA and testing results will be presented in the paper.

FPGA based fast synchronous serial multi-wire links synchronization

Science.gov (United States)

Pozniak, Krzysztof T.

2013-10-01

The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

A New FPGA Architecture of FAST and BRIEF Algorithm for On-Board Corner Detection and Matching.

Science.gov (United States)

Huang, Jingjin; Zhou, Guoqing; Zhou, Xiang; Zhang, Rongting

2018-03-28

Although some researchers have proposed the Field Programmable Gate Array (FPGA) architectures of Feature From Accelerated Segment Test (FAST) and Binary Robust Independent Elementary Features (BRIEF) algorithm, there is no consideration of image data storage in these traditional architectures that will result in no image data that can be reused by the follow-up algorithms. This paper proposes a new FPGA architecture that considers the reuse of sub-image data. In the proposed architecture, a remainder-based method is firstly designed for reading the sub-image, a FAST detector and a BRIEF descriptor are combined for corner detection and matching. Six pairs of satellite images with different textures, which are located in the Mentougou district, Beijing, China, are used to evaluate the performance of the proposed architecture. The Modelsim simulation results found that: (i) the proposed architecture is effective for sub-image reading from DDR3 at a minimum cost; (ii) the FPGA implementation is corrected and efficient for corner detection and matching, such as the average value of matching rate of natural areas and artificial areas are approximately 67% and 83%, respectively, which are close to PC's and the processing speed by FPGA is approximately 31 and 2.5 times faster than those by PC processing and by GPU processing, respectively.

FPGA based algorithms for data reduction at Belle II

Energy Technology Data Exchange (ETDEWEB)

Muenchow, David; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liu, Ming; Spruck, Bjoern [II. Physikalisches Institut, Universitaet Giessen (Germany)

2011-07-01

Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e{sup +}e{sup -} collider with a design luminosity of 8.10{sup 35}cm{sup -2}s{sup -1}. At Belle II the estimated event rate is {<=}30 kHz. The resulting data rate at the Pixel Detector (PXD) will be {<=}7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for buffering and storing the data. The status of the implementation and performance tests of the memory manager and data reduction algorithm is presented.

Optimizing latency in Xilinx FPGA implementations of the GBT

CERN Document Server

Muschter, S; Bohm, C; Cachemiche, J-P; Baron, S

2010-01-01

The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation {[}3]. This code was optimized for resource utilization {[}4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The la...

FPGA Dynamic Power Minimization through Placement and Routing Constraints

Directory of Open Access Journals (Sweden)

Deepak Agarwal

2006-08-01

Full Text Available Field-programmable gate arrays (FPGAs are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits mapped into 0.12 μm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.

Clock Gating Based Energy Efficient and Thermal Aware Design for Vedic Equation Solver on 28nm and 40nm FPGA

DEFF Research Database (Denmark)

Pandey, Bishwajeet; Pandey, Sujeet; Sharma, Shivani

2016-01-01

In this paper, we are integrating clock gating in design of energy efficient equation solver circuits based on Vedic mathematics. Clock gating is one of the best energy efficient techniques. The Sutra 'SunyamSamyasamuccaye' says thatif sum of numerator and sum of denominator is same then we can e......, 94.54% for 1800MHz, and 94.02% for 2.2GHz, when we use gated clock instead of un gated one on 40nm FPGA and temperature is 329.85K. Power consumption in 28nm FPGA is less than 40nm FPGA....

FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling.

Science.gov (United States)

Kim, Chang-Min; Park, Hyung-Min; Kim, Taesu; Choi, Yoon-Kyung; Lee, Soo-Young

2003-01-01

An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time.

Fault injection as a test method for an FPGA in charge of data readout for a large tracking detector

CERN Document Server

Roed, K; Richter, M; Fehlker, D; Helstrup, H; Alme, J; Ullaland, K

2011-01-01

This paper describes how fault injection has been implemented as a test method for an FPGA in an existing hardware configuration setup. As this FPGA is in charge of data readout for a large tracking detector, the reliability of this FPGA is of high importance. Due to the complexity of the readout electronics, irradiation testing is technically difficult at this stage of the system commissioning. The work presented in this paper is therefore motivated by introducing fault injection as an alternative method to characterize failures caused by SEUs. It is a method to study the effect that a configuration upset may have on the operation of the FPGA. The target platform consists of two independent modules for data acquisition and detector control functionality. Fault injection to test the response of the data acquisition module is made possible by implementing the solution as part of the detector control functionality. Correct implementation is validated by a simple shift register design. Our results demonstrate th...

Multichannel analyzer embedded in FPGA

International Nuclear Information System (INIS)

Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Bravo M, I.

2017-10-01

Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

An improved real time superresolution FPGA system

Science.gov (United States)

Lakshmi Narasimha, Pramod; Mudigoudar, Basavaraj; Yue, Zhanfeng; Topiwala, Pankaj

2009-05-01

In numerous computer vision applications, enhancing the quality and resolution of captured video can be critical. Acquired video is often grainy and low quality due to motion, transmission bottlenecks, etc. Postprocessing can enhance it. Superresolution greatly decreases camera jitter to deliver a smooth, stabilized, high quality video. In this paper, we extend previous work on a real-time superresolution application implemented in ASIC/FPGA hardware. A gradient based technique is used to register the frames at the sub-pixel level. Once we get the high resolution grid, we use an improved regularization technique in which the image is iteratively modified by applying back-projection to get a sharp and undistorted image. The algorithm was first tested in software and migrated to hardware, to achieve 320x240 -> 1280x960, about 30 fps, a stunning superresolution by 16X in total pixels. Various input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as in FPGA hardware, which gives us a fine balance between the number of bits and performance. The proposed system is robust and highly efficient. We have shown the performance improvement of the hardware superresolution over the software version (C code).

FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

Science.gov (United States)

Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

2016-05-01

This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

Real Time Implementation of a DC Motor Speed Control by Fuzzy Logic Controller and PI Controller Using FPGA

Directory of Open Access Journals (Sweden)

G. Sakthivel

2010-10-01

Full Text Available Fuzzy logic control has met with growing interest in many motor control applications due to its non-linearity, handling features and independence of plant modelling. The hardware implementation of fuzzy logic controller (FLC on FPGA is very important because of the increasing number of fuzzy applications requiring highly parallel and high speed fuzzy processing. Implementation of a fuzzy logic controller and conventional PI controller on an FPGA using VHDL for DC motor speed control is presented in this paper. The proposed scheme is to improve tracking performance of D.C. motor as compared to the conventional (PI control strategy .This paper describes the hardware implementation of two inputs (error and change in error, one output fuzzy logic controller based on PI controller and conventional PI controller using VHDL. Real time implementation FLC and conventional PI controller is made on Spartan-3A DSP FPGA (XC3SD1800A FPGA for the speed control of DC motor. It is observed that fuzzy logic based controllers give better responses than the conventional PI controller for the speed control of dc motor.

General method of synthesis by PLIC/FPGA digital devices to ...

African Journals Online (AJOL)

A general method is proposed to synthesize digital devices in order to perform discrete orthogonal transformations (DOT) on programmable logic integrated circuits (PLIC) of FPGA class. The basic and the most "slow" operation during DOT performance is the operation of multiplying by a constant factor (constant) - OMC.

Using an FPGA for Fast Bit Accurate SoC Simulation

NARCIS (Netherlands)

Wolkotte, P.T.; Holzenspies, P.K.F.; Smit, Gerardus Johannes Maria

In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit

A high-level power model for MPSoC on FPGA

NARCIS (Netherlands)

Piscitelli, R.; Pimentel, A.D.

2011-01-01

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, e.g., commonly-used instruction-set

Test of Gb Ethernet with FPGA for HADES upgrade

Energy Technology Data Exchange (ETDEWEB)

Gilardi, C. [II. Physikalisches Inst., Giessen Univ. (Germany)

2007-07-01

Within the HADES experiment, we are investigating a trigger upgrade in order to run heavier systems (Au + Au). We investigate Gigabit Ethernet transfers with Xilinx Virtex II FPGA on the commercial board Celoxica RC300E. We implement the transfer protocols (UDP, ICMP, ARP) with Handel-C. First results of bandwidth and latency will be presented. (orig.)

Real-time particle image velocimetry based on FPGA technology;Velocimetria PIV en tiempo real basada en logica programable FPGA

Energy Technology Data Exchange (ETDEWEB)

Iriarte Munoz, Jose Miguel [Universidad Nacional de Cuyo, Instituto Balseiro, Centro Atomico Bariloche (Argentina)

2008-07-01

Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach.;La velocimetria por imagenes de particulas (PIV), basada en plano laser, es una potente herramienta de medicion en dinamica de fluidos, capaz de medir sin grandes errores, un campo de velocidades distribuido en liquidos, gases y flujo multifase.Los altos requerimientos computacionales de los algoritmos PIV dificultan su empleo en tiempo-real.En este trabajo presentamos el diseno de una plataforma basada en tecnologia FPGA para capturar video y procesar en tiempo real el algoritmo de correlacion cruzada bidimensional.Mostramos resultados de un primer abordaje de la captura de imagenes y procesamiento de un campo fisico de velocidades en tiempo real.

Design of a dedicated processor for AC motor control implemented in a low cost FPGA

DEFF Research Database (Denmark)

Jakobsen, Uffe; Matzen, Torben N.

2008-01-01

of drives. Furthermore the softcore processor is designed with a system for plug in of external logic. Doing so shortens development time, since functionality is simply added to or removed from the softcore. The designer can then choose between resource usage on the FPGA and execution speed in more degrees....... The approach is tested for two different motor types, synchronousand hybrid switched reluctance motors, using a Spartan 3E FPGA. The impact of having ADC-communication in VHDL versus in assembler is also presented....

FPGA implementation of self organizing map with digital phase locked loops.

Science.gov (United States)

Hikawa, Hiroomi

2005-01-01

The self-organizing map (SOM) has found applicability in a wide range of application areas. Recently new SOM hardware with phase modulated pulse signal and digital phase-locked loops (DPLLs) has been proposed (Hikawa, 2005). The system uses the DPLL as a computing element since the operation of the DPLL is very similar to that of SOM's computation. The system also uses square waveform phase to hold the value of the each input vector element. This paper discuss the hardware implementation of the DPLL SOM architecture. For effective hardware implementation, some components are redesigned to reduce the circuit size. The proposed SOM architecture is described in VHDL and implemented on field programmable gate array (FPGA). Its feasibility is verified by experiments. Results show that the proposed SOM implemented on the FPGA has a good quantization capability, and its circuit size very small.

Procedimiento para elaborar una lente intraocular monofocal asférica isoplanática y lente obtenida empleando dicho procedimiento

OpenAIRE

Barbero, Sergio; Marcos, Susana; Dorronsoro, Carlos; Montejo, Javier; Salazar Salegui, Pedro

2010-01-01

Procedimiento para elaborar una lente intraocular monofocal asférica isoplanática y lente obtenida empleando dicho procedimiento. Permite obtener lentes oftálmicas monofocales asféricas isoplanáticas en un rango visual de hasta 25º (preferentemente hasta 10º) de amplitud. El procedimiento comprende las etapas de: 1.- Definición matemática de un modelo de ojo afáquico; 2.- Definición matemática de un modelo de lente intraocular; 3.- Definición matemática de la implantac...

Signal compression in radar using FPGA

OpenAIRE

Enrique Escamilla Hemández; Víctor Kravchenko; Volodymyr Ponomaryov; Gonzalo Duchen Sánchez; David Hernández Sánchez

2010-01-01

El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array). El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR). El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde n...

Re-Form: FPGA-Powered True Codesign Flow for High-Performance Computing In The Post-Moore Era

Energy Technology Data Exchange (ETDEWEB)

Cappello, Franck; Yoshii, Kazutomo; Finkel, Hal; Cong, Jason

2016-11-14

Multicore scaling will end soon because of practical power limits. Dark silicon is becoming a major issue even more than the end of Moore’s law. In the post-Moore era, the energy efficiency of computing will be a major concern. FPGAs could be a key to maximizing the energy efficiency. In this paper we address severe challenges in the adoption of FPGA in HPC and describe “Re-form,” an FPGA-powered codesign flow.

Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications

DEFF Research Database (Denmark)

Hegner, Jonas Stenbæk; Sindholt, Joakim; Nannarelli, Alberto

2012-01-01

Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation...

An Accelerating Solution for N-Body MOND Simulation with FPGA-SoC

Directory of Open Access Journals (Sweden)

Bo Peng

2016-01-01

Full Text Available As a modified-gravity proposal to handle the dark matter problem on galactic scales, Modified Newtonian Dynamics (MOND has shown a great success. However, the N-body MOND simulation is quite challenged by its computation complexity, which appeals to acceleration of the simulation calculation. In this paper, we present a highly integrated accelerating solution for N-body MOND simulations. By using the FPGA-SoC, which integrates both FPGA and SoC (system on chip in one chip, our solution exhibits potentials for better performance, higher integration, and lower power consumption. To handle the calculation bottleneck of potential summation, on one hand, we develop a strategy to simplify the pipeline, in which the square calculation task is conducted by the DSP48E1 of Xilinx 7 series FPGAs, so as to reduce the logic resource utilization of each pipeline; on the other hand, advantages of particle-mesh scheme are taken to overcome the bottleneck on bandwidth. Our experiment results show that 2 more pipelines can be integrated in Zynq-7020 FPGA-SoC with the simplified pipeline, and the bandwidth requirement is reduced significantly. Furthermore, our accelerating solution has a full range of advantages over different processors. Compared with GPU, our work is about 10 times better in performance per watt and 50% better in performance per cost.

Medansvar og fagligt engagement gennem digitale skriveøvelser

Directory of Open Access Journals (Sweden)

Henriette Roued-Cunliffe

2016-10-01

Full Text Available Vi rapporterer om vores forsøg på at promovere medansvar og fagligt engagement blandt vores studerende gennem digitale skriveøvelser. Disse kombinerer skriftlighed i læring (som en refleksionsfremmende og forpligtende øvelse med de kollaborative muligheder, der ligger i at benytte digitale platforme. Dybde i læring og reflekteret/reflekterende feedback er aspekter, som bliver centrale, når fagligt indhold på skrift indlejres i en digital læringskontekst. I artiklen tages udgangspunkt i TEACHs universitetspædagogiske initiativer inden for skriftlig læring og erfaringerne fra universitetspædagogikum. Forfatterne afprøvede nogle af disse idéer i form af kollaborative skriveøvelser på et bachelorkursus på Det Informationsvidenskabelige Akademi (Københavns Universitet. Forfatternes praktiske fremgangsmåde dokumenteres, og der gøres rede for de erfaringer, de har gjort sig. I den forbindelse diskuteres aspekter som tekstnære vs. åbne spørgsmål, de studerendes motivation for skrivning, deres vurdering af egen arbejdsindsats, en vurdering af de studerendes tidsforbrug og de studerendes holdning over for den foretrukne feedback - underviserens eller peer-to-peer. Der afsluttes med anbefalinger, som baserer sig på dette forsøg. This article reports on our attempts to promote accountability and commitment among our students through digital writing exercises. These combine writing as a reflective and required learning process with the collaborative possibilities that exist in using a digital platform. When using this kind of platform the depth of understanding and the quality of the feedback are important aspects of the learning experience. The study is based on the university’s TEACH programme, which focuses on writing in higher education, and it also draws on our experience from the university’s pedagogy course. Some of the ideas were tested on students from the Bachelor programme at the Royal School of Library and

Det digitale imperativ: En epistemologisk bestræbelse [The Digital Imperative: An Epistemological Endeavour

Directory of Open Access Journals (Sweden)

Sisse Siggaard Jensen

2014-12-01

Full Text Available I denne artikel argumenteres der for, at forskning inden for feltet tredje-bølge digital humaniora er væsentlig for vores forståelse af, hvordan de sociale netværksmediers digitale infrastrukturer og datastrømme – status-opdateringer, selv-profilering, mikro-koordinering, mikro-blogging og vlogging – i stigende grad påvirker menneskelige relationer og ‘the structure of feeling’ (Berry, 2012. Som led i at underbygge dette synspunkt analyseres fire emergente temaer baseret på Facebook-data: Facebook-venner, Events, Self-profilering og Stalking. Analyserne tager afsæt i data, der er tilvejebragt gennem kondensering af design-konceptformuleringer fra 73 unge studerende (alder 20-24 som led i et universitetskursus inden for feltet digital humaniora (2013. To begrebspar er centrale for analyserne: ‘Forbundethed og forbindelser’ (van Dijck, 2013 og ‘synlighed og overvågning’ (Bucher, 2012. Der identificeres en række spændingsfelter mellem interpersonelle normer og påvirkningerne fra Facebook-datastrømme i forhold til: Venskab, troværdighed, ansvarlighed, prestige, selvpromovering og fælles interesser. Det konkluderes, at en væsentlig erkendelsesteoretiske bestræbelse for forskning inden for tredje-bølge digital humaniora må være at producere viden, der kan bidrage til vores individuelle såvel som kollektive forståelse af de mange spændingsfelter, der opstår i datastrømmenes og de menneskelige relationers gensidige påvirkning. Denne bestræbelse er sammenfattet i artiklens titel ‘det digitale imperativ’.

Energy-Efficient FPGA-Based Parallel Quasi-Stochastic Computing

Directory of Open Access Journals (Sweden)

Ramu Seva

2017-11-01

Full Text Available The high performance of FPGA (Field Programmable Gate Array in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of 3.5 and 4.5 for the edge detection circuit and multiplication circuit, respectively.

FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments

CERN Document Server

Pozniak, Krzysztof T

2004-01-01

The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY) . A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.

A New FPGA Architecture of FAST and BRIEF Algorithm for On-Board Corner Detection and Matching

Directory of Open Access Journals (Sweden)

Jingjin Huang

2018-03-01

Full Text Available Although some researchers have proposed the Field Programmable Gate Array (FPGA architectures of Feature From Accelerated Segment Test (FAST and Binary Robust Independent Elementary Features (BRIEF algorithm, there is no consideration of image data storage in these traditional architectures that will result in no image data that can be reused by the follow-up algorithms. This paper proposes a new FPGA architecture that considers the reuse of sub-image data. In the proposed architecture, a remainder-based method is firstly designed for reading the sub-image, a FAST detector and a BRIEF descriptor are combined for corner detection and matching. Six pairs of satellite images with different textures, which are located in the Mentougou district, Beijing, China, are used to evaluate the performance of the proposed architecture. The Modelsim simulation results found that: (i the proposed architecture is effective for sub-image reading from DDR3 at a minimum cost; (ii the FPGA implementation is corrected and efficient for corner detection and matching, such as the average value of matching rate of natural areas and artificial areas are approximately 67% and 83%, respectively, which are close to PC’s and the processing speed by FPGA is approximately 31 and 2.5 times faster than those by PC processing and by GPU processing, respectively.

Tabletas digitales para la docencia del dibujo, diseño y artes plásticas

Directory of Open Access Journals (Sweden)

José Luis SAORÍN PÉREZ

2011-07-01

Full Text Available El uso de dispositivos móviles en la enseñanza está aumentando cada día y las tabletas digitales, de reciente aparición, se perfilan como uno de los instrumentos más flexibles para el ámbito de la educación denominando a la enseñanza sobre este dispositivo como Tablet-Learning. Las posibilidades gráficas de estos dispositivos permiten utilizarlas adecuadamente para la enseñanza de aquellas asignaturas donde la expresión gráfica de las ideas es importante (representación de formas, dibujos artísticos, visualización de modelos tridimensionales, aplicaciones geoespaciales…. En este artículo pretendemos establecer la situación actual de estas tabletas digitales en el mundo educativo y hacer una valoración de las posibilidades de estos dispositivos como herramienta para la docencia del dibujo, diseño y artes plásticas. Analizamos aquellas aplicaciones disponibles para estos dispositivos y que se pueden utilizar en la docencia de estas disciplinas. Dichas aplicaciones se categorizarán de acuerdo a las características de los formatos de trabajo. Dentro de cada una de estas categorías se tratará de encontrar aquellas características que las definen. Se pretende con dicha recopilación que los profesores de estas asignaturas conozcan estas aplicaciones y puedan organizar talleres utilizando estos nuevos dispositivos.

A Correctness Verification Technique for Commercial FPGA Synthesis Tools

International Nuclear Information System (INIS)

Kim, Eui Sub; Yoo, Jun Beom; Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo

2014-01-01

Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

A Correctness Verification Technique for Commercial FPGA Synthesis Tools

Energy Technology Data Exchange (ETDEWEB)

Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2014-10-15

Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

Directory of Open Access Journals (Sweden)

Sanjay Singh

2017-06-01

Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

FPGA based mixed-signal circuit novel testing techniques

International Nuclear Information System (INIS)

Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

2013-01-01

Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

DEFF Research Database (Denmark)

Singh, Ritu; Kalia, Kartik; Minver, M. H.

2016-01-01

Abstract-In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobile...

GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

International Nuclear Information System (INIS)

Mitra, Jubin; Khan, Shuaib A.; Nayak, Tapan K.; Marin, Manoel Barros; Baron, Sophie; Kluge, Alex; Cachemiche, Jean-Pierre; Hachon, Frédéric; Rethore, Frédéric; David, Erno; Kiss, Tivadar

2016-01-01

The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA

UNIX veida mikrokodola operētājsistēma FPGA procesoram

OpenAIRE

Liepkalns, Ansis

2012-01-01

Risinājumos, kuros izmanto programmējamo loģisko mezglu masīvu (FPGA) procesorus, programmatūras pieejamība ir svarīga, lai samazinātu galaprodukta iegūšanai nepieciešamo laiku. Plašu programmatūras atbalstu ir ieguvušas UNIX veida operētājsistēmas. To kombinācija ar FPGA procesoriem spēj nodrošināt vēlamo izstrādes ātrumu. Lai apmierinātu kvalitātes prasības, tiek piedāvāts izmantot mikrokodola operētājsistēmu. Darbā tiek apskatīta sistēmas mikroshēmā izveide darbībai ar „Minix 3“ mikrokodol...

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

Directory of Open Access Journals (Sweden)

Y. H. Lee

2016-01-01

Full Text Available Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

Natrium: Use of FPGA embedded processors for real-time data compression

Energy Technology Data Exchange (ETDEWEB)

Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

2011-12-15

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Natrium: Use of FPGA embedded processors for real-time data compression

International Nuclear Information System (INIS)

Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

2011-01-01

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

A Framework for Dynamically-Loaded Hardware Library (HLL) in FPGA Acceleration

DEFF Research Database (Denmark)

Cardarilli, Gian Carlo; Di Carlo, Leonardo; Nannarelli, Alberto

2016-01-01

Hardware acceleration is often used to address the need for speed and computing power in embedded systems. FPGAs always represented a good solution for HW acceleration and, recently, new SoC platforms extended the flexibility of the FPGAs by combining on a single chip both high-performance CPUs...... and FPGA fabric. The aim of this work is the implementation of hardware accelerators for these new SoCs. The innovative feature of these accelerators is the on-the-fly reconfiguration of the hardware to dynamically adapt the accelerator’s functionalities to the current CPU workload. The realization...... of the accelerators preliminarily requires also the profiling of both the SW (ARM CPU + NEON Units) and HW (FPGA) performance, an evaluation of the partial reconfiguration times and the development of an applicationspecific IP-cores library. This paper focuses on the profiling aspect of both the SW and HW...

Comparing an FPGA to a Cell for an Image Processing Application

Science.gov (United States)

Rakvic, Ryan N.; Ngo, Hau; Broussard, Randy P.; Ives, Robert W.

2010-12-01

Modern advancements in configurable hardware, most notably Field-Programmable Gate Arrays (FPGAs), have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. On the other hand, PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high performance. In this research project, our aim is to study the differences in performance of a modern image processing algorithm on these two hardware platforms. In particular, Iris Recognition Systems have recently become an attractive identification method because of their extremely high accuracy. Iris matching, a repeatedly executed portion of a modern iris recognition algorithm, is parallelized on an FPGA system and a Cell processor. We demonstrate a 2.5 times speedup of the parallelized algorithm on the FPGA system when compared to a Cell processor-based version.

Comparing an FPGA to a Cell for an Image Processing Application

Directory of Open Access Journals (Sweden)

Robert W. Ives

2010-01-01

Full Text Available Modern advancements in configurable hardware, most notably Field-Programmable Gate Arrays (FPGAs, have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. On the other hand, PlayStation3 (PS3 game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high performance. In this research project, our aim is to study the differences in performance of a modern image processing algorithm on these two hardware platforms. In particular, Iris Recognition Systems have recently become an attractive identification method because of their extremely high accuracy. Iris matching, a repeatedly executed portion of a modern iris recognition algorithm, is parallelized on an FPGA system and a Cell processor. We demonstrate a 2.5 times speedup of the parallelized algorithm on the FPGA system when compared to a Cell processor-based version.

Competencia Digital: Uso y manejo de modelos 3D tridimensionales digitales e impresos en 3D

OpenAIRE

Jose Luis Saorín; Cecile Meier; Jorge de la Torre-Cantero; Carlos Carbonell-Carrera; Dámari Melián-Díaz; Alejandro Bonnet de León

2017-01-01

El uso y manejo de modelos tridimensionales digitales no está concebido dentro de la competencia digital de los currículos de secundaria y Bachillerato. Sin embargo muchos autores relacionan la competencia digital con el manejo de modelos 3D, el modelado 3D y entornos virtuales tridimensionales (Realidad aumentada, virtual,…). En este artículo se presenta un recurso educativo para facilitar el acceso a contenidos didácticos de carácter tridimensional digital y tangible. Determinadas materias ...

Dynamic Reconfiguration Of FPGA Nodes In A Distributed Computing System: A Preliminary Investigation

National Research Council Canada - National Science Library

Nixon, Patrick

2002-01-01

This report results from a contract tasking Trinity College, Dublin to investigate a specialized portion of a heterogeneous information system, specifically, Field Programmable Gate Array (FPGA)-based nodes...

Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo Vision Algorithm on FPGA

Directory of Open Access Journals (Sweden)

Beau Tippetts

2014-01-01

Full Text Available A variety of platforms, such as micro-unmanned vehicles, are limited in the amount of computational hardware they can support due to weight and power constraints. An efficient stereo vision algorithm implemented on an FPGA would be able to minimize payload and power consumption in microunmanned vehicles, while providing 3D information and still leaving computational resources available for other processing tasks. This work presents a hardware design of the efficient profile shape matching stereo vision algorithm. Hardware resource usage is presented for the targeted micro-UV platform, Helio-copter, that uses the Xilinx Virtex 4 FX60 FPGA. Less than a fifth of the resources on this FGPA were used to produce dense disparity maps for image sizes up to 450 × 375, with the ability to scale up easily by increasing BRAM usage. A comparison is given of accuracy, speed performance, and resource usage of a census transform-based stereo vision FPGA implementation by Jin et al. Results show that the profile shape matching algorithm is an efficient real-time stereo vision algorithm for hardware implementation for resource limited systems such as microunmanned vehicles.

The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments.

Science.gov (United States)

Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J; Madison, Kirk W

2018-02-01

In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

Development of An Embedded FPGA-Based Data Acquisition System Dedicated to Zero Power Reactor Noise Experiments

Directory of Open Access Journals (Sweden)

Arkani Mohammad

2014-08-01

Full Text Available An embedded time interval data acquisition system (DAS is developed for zero power reactor (ZPR noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA. The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.

The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments

Science.gov (United States)

Yu, Shi Jing; Fajeau, Emma; Liu, Lin Qiao; Jones, David J.; Madison, Kirk W.

2018-02-01

In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

Multichannel FPGA based MVT system for high precision time (20 ps RMS) and charge measurement

Science.gov (United States)

Pałka, M.; Strzempek, P.; Korcyl, G.; Bednarski, T.; Niedźwiecki, Sz.; Białas, P.; Czerwiński, E.; Dulski, K.; Gajos, A.; Głowacz, B.; Gorgol, M.; Jasińska, B.; Kamińska, D.; Kajetanowicz, M.; Kowalski, P.; Kozik, T.; Krzemień, W.; Kubicz, E.; Mohhamed, M.; Raczyński, L.; Rudy, Z.; Rundel, O.; Salabura, P.; Sharma, N. G.; Silarski, M.; Smyrski, J.; Strzelecki, A.; Wieczorek, A.; Wiślicki, W.; Zieliński, M.; Zgardzińska, B.; Moskal, P.

2017-08-01

In this article it is presented an FPGA based Multi-Voltage Threshold (MVT) system which allows of sampling fast signals (1-2 ns rising and falling edge) in both voltage and time domain. It is possible to achieve a precision of time measurement of 20 ps RMS and reconstruct charge of signals, using a simple approach, with deviation from real value smaller than 10%. Utilization of the differential inputs of an FPGA chip as comparators together with an implementation of a TDC inside an FPGA allowed us to achieve a compact multi-channel system characterized by low power consumption and low production costs. This paper describes realization and functioning of the system comprising 192-channel TDC board and a four mezzanine cards which split incoming signals and discriminate them. The boards have been used to validate a newly developed Time-of-Flight Positron Emission Tomography system based on plastic scintillators. The achieved full system time resolution of σ(TOF) ≈ 68 ps is by factor of two better with respect to the current TOF-PET systems.

Digitale Lernprogramme – Konkurrenz für das Mikroskop? [Digital learning programs - competition for the classical microscope?

Directory of Open Access Journals (Sweden)

Schmidt, Peter

2013-02-01

Full Text Available [english] The development of digital media has been impressive in recent years which is also among the reason for their increasing use in academic teaching.This is especially true for teaching Anatomy and Histology in the first two years in medical and dental curricula. Modern digital technologies allow for efficient, affordable and easily accessible distribution of histological images in high quality. Microscopy depends almost exclusively on such images. Since 20 years numerous digital teaching systems have been developed for this purpose. Respective developments have changed the ways students acquire knowledge and prepare for exams. Teaching staff should adapt lectures, seminars and labs accordingly. As a first step, a collection of high resolution digital microscopic slides was made available for students at the Friedrich-Schiller-University in Jena. The aim of the present study was to evaluate the importance of conventional light microscopy and related technologies in current and future medical and dental education aswell. A survey was done among 172 medical and dental students at the Friedrich-Schiller-University Jena. 51% of students use now frequently new digital media for learning histology in contrast to 5% in the year 2000 . Digital media including Internet, CD- based learning combined with social networks successfully compete with classical light microscopy.[german] Die Entwicklung digitaler Medien wuchs in jüngster Zeit beträchtlich an, was mitunter als Ursache für deren wachsende Nutzung in der universitären Lehre anzusehen ist. Zutreffend ist dies insbesondere auch im Bereich der Anatomie und Histologie, welche Bestandteile des Studiums für Ärzte und Zahnärzte in den ersten zwei Studienjahren darstellen. Moderne digitale Technologien erlauben es eine leistungsfähige, bezahlbare und begreifbare Verbreitung histologischer Bilder in hoher Qualität zu gewährleisten. Die Mikroskopie hängt fast ausschließlich von Bildern ab

FPGA platform for MEMS Disc Resonance Gyroscope (DRG) control

Science.gov (United States)

Keymeulen, Didier; Peay, Chris; Foor, David; Trung, Tran; Bakhshi, Alireza; Withington, Phil; Yee, Karl; Terrile, Rich

2008-04-01

Inertial navigation systems based upon optical gyroscopes tend to be expensive, large, power consumptive, and are not long lived. Micro-Electromechanical Systems (MEMS) based gyros do not have these shortcomings; however, until recently, the performance of MEMS based gyros had been below navigation grade. Boeing and JPL have been cooperating since 1997 to develop high performance MEMS gyroscopes for miniature, low power space Inertial Reference Unit applications. The efforts resulted in demonstration of a Post Resonator Gyroscope (PRG). This experience led to the more compact Disc Resonator Gyroscope (DRG) for further reduced size and power with potentially increased performance. Currently, the mass, volume and power of the DRG are dominated by the size of the electronics. This paper will detail the FPGA based digital electronics architecture and its implementation for the DRG which will allow reduction of size and power and will increase performance through a reduction in electronics noise. Using the digital control based on FPGA, we can program and modify in real-time the control loop to adapt to the specificity of each particular gyro and the change of the mechanical characteristic of the gyro during its life time.

FPGA-based architecture for motion recovering in real-time

Science.gov (United States)

Arias-Estrada, Miguel; Maya-Rueda, Selene E.; Torres-Huitzil, Cesar

2002-03-01

A key problem in the computer vision field is the measurement of object motion in a scene. The main goal is to compute an approximation of the 3D motion from the analysis of an image sequence. Once computed, this information can be used as a basis to reach higher level goals in different applications. Motion estimation algorithms pose a significant computational load for the sequential processors limiting its use in practical applications. In this work we propose a hardware architecture for motion estimation in real time based on FPGA technology. The technique used for motion estimation is Optical Flow due to its accuracy, and the density of velocity estimation, however other techniques are being explored. The architecture is composed of parallel modules working in a pipeline scheme to reach high throughput rates near gigaflops. The modules are organized in a regular structure to provide a high degree of flexibility to cover different applications. Some results will be presented and the real-time performance will be discussed and analyzed. The architecture is prototyped in an FPGA board with a Virtex device interfaced to a digital imager.

Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA

Czech Academy of Sciences Publication Activity Database

Pohl, Zdeněk; Tichý, Milan; Kadlec, Jiří

2008-01-01

Roč. 2008, č. 2008 (2008), s. 1-11 ISSN 1687-6172 R&D Projects: GA MŠk(CZ) 1M0567 EU Projects: European Commission(XE) 027611 - AETHER Program:FP6 Institutional research plan: CEZ:AV0Z10750506 Keywords : DSP * Least-squares lattice * order estimation * exponential forgetting factor estimation * FPGA implementation * scheduling * dynamic reconfiguration * microblaze Subject RIV: IN - Informatics, Computer Science Impact factor: 1.055, year: 2008 http://library.utia.cas.cz/separaty/2008/ZS/pohl-tichy-kadlec-implementation%20of%20the%20least-squares%20lattice%20with%20order%20and%20forgetting%20factor%20estimation%20for%20fpga.pdf

Radiation tolerance and mitigation strategies for FPGA:s in the ATLAS TileCal Demonstrator

CERN Document Server

Akerstedt, H; The ATLAS collaboration

2013-01-01

During 2014, demonstrator electronics will be installed in a Tile calorimeter "drawer" to get long term experience with the inherently redundant electronics proposed for a full upgrade scheduled for 2022. The new system, being FPGA-based, uses dense programmable logic which must be proven to be sufficently radiation tolerant. It must be protected against radiation induced single event upsets that corrupt memory and logic functions. Radiation induced errors need to be found and compensated for in time, to minimize data loss but also to avoid permanent damage. Strategies for detecting and correcting radiation induced errors in the Kintex-7 FPGA:s of the demonstrator are evaluated and discussed.

Superconducting cavity driving with FPGA controller

International Nuclear Information System (INIS)

Czarski, Tomasz; Koprek, Waldemar; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Simrock, Stefan; Brandt, Alexander; Chase, Brian; Carcagno, Ruben; Cancelo, Gustavo; Koeth, Timothy W.

2006-01-01

A digital control of superconducting cavities for a linear accelerator is presented. FPGA-based controller, supported by Matlab system, was applied. Electrical model of a resonator was used for design of a control system. Calibration of the signal path is considered. Identification of cavity parameters has been carried out for adaptive control algorithm. Feed-forward and feedback modes were applied in operating the cavities. Required performance has been achieved; i.e. driving on resonance during filling and field stabilization during flattop time, while keeping reasonable level of the power consumption. Representative results of the experiments are presented for different levels of the cavity field gradient

Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control

Directory of Open Access Journals (Sweden)

E.A. Ramadan

2014-09-01

Full Text Available This paper presents an improved adaptive fuzzy logic speed controller for a DC motor, based on field programmable gate array (FPGA hardware implementation. The developed controller includes an adaptive fuzzy logic control (AFLC algorithm, which is designed and verified with a nonlinear model of DC motor. Then, it has been synthesised, functionally verified and implemented using Xilinx Integrated Software Environment (ISE and Spartan-3E FPGA. The performance of this controller has been successfully validated with good tracking results under different operating conditions.

Bridging FPGA and GPU technologies for AO real-time control

Science.gov (United States)

Perret, Denis; Lainé, Maxime; Bernard, Julien; Gratadour, Damien; Sevin, Arnaud

2016-07-01

Our team has developed a common environment for high performance simulations and real-time control of AO systems based on the use of Graphics Processors Units in the context of the COMPASS project. Such a solution, based on the ability of the real time core in the simulation to provide adequate computing performance, limits the cost of developing AO RTC systems and makes them more scalable. A code developed and validated in the context of the simulation may be injected directly into the system and tested on sky. Furthermore, the use of relatively low cost components also offers significant advantages for the system hardware platform. However, the use of GPUs in an AO loop comes with drawbacks: the traditional way of offloading computation from CPU to GPUs - involving multiple copies and unacceptable overhead in kernel launching - is not well suited in a real time context. This last application requires the implementation of a solution enabling direct memory access (DMA) to the GPU memory from a third party device, bypassing the operating system. This allows this device to communicate directly with the real-time core of the simulation feeding it with the WFS camera pixel stream. We show that DMA between a custom FPGA-based frame-grabber and a computation unit (GPU, FPGA, or Coprocessor such as Xeon-phi) across PCIe allows us to get latencies compatible with what will be needed on ELTs. As a fine-grained synchronization mechanism is not yet made available by GPU vendors, we propose the use of memory polling to avoid interrupts handling and involvement of a CPU. Network and Vision protocols are handled by the FPGA-based Network Interface Card (NIC). We present the results we obtained on a complete AO loop using camera and deformable mirror simulators.

A novel integrated renewable energy system modelling approach, allowing fast FPGA controller prototyping

DEFF Research Database (Denmark)

Teodorescu, Remus; Ruiz, Alberto Parera; Cirstea, Marcian

2008-01-01

The paper describes a new holistic approach to the modeling of integrated renewable energy systems. The method is using the DK5 modeling/design environment from Celoxica and is based on the new Handel-C programming language. The goal of the work carried out was to achieve a combined model...... containing a Xilinx Spartan II FPGA and was successfully experimentally tested. This approach enables the design and fast hardware implementation of efficient controllers for Distributed Energy Resource (DER) hybrid systems....... of a photovoltaic energy system and a wind power system, which would allow an optimized holistic digital control system design, followed by rapid prototyping of the controller into a single Field Programmable Gate Array (FPGA). Initially, the system was simulated using Matlab / Simulink, to create a reference...