WorldWideScience

Sample records for digitales empleando fpga

  1. Transferencia de datos por puerto USB de una tarjeta FPGA Nexys 2 empleando LabWindows CVI v9.0

    Directory of Open Access Journals (Sweden)

    Juan Raúl Rodríguez Suárez

    2011-05-01

    Full Text Available Normal 0 21 false false false MicrosoftInternetExplorer4 st1:*{behavior:url(#ieooui } /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} En el trabajo se presenta la implementación de la comunicación por puerto USB entre una computadora con sistema operativo Windows y una tarjeta FPGA Nexys2.  Dicha tarjeta posee un microcontrolador Cypress CY7C68013A que maneja un puerto  USB2 de alta velocidad que ha sido programado para emular un puerto paralelo EPP. Se expone el diseño y evaluación  de una interfaz gráfica de usuario con programación LabWindows que maneja la biblioteca DPCUTIL y que posibilita la transferencia y visualización de datos desde la Nexys2. La aplicación permite  la transferencia en tiempo real de un procesador digital de 12bits, de dos canales implementado con frecuencia de muestreo de 1MHz en la FPGA. En el trabajo se evalúa los resultados alcanzados en cuanto a la velocidad de transferencia de datos efectiva.

  2. IMPLEMENTACIÓN EN HARDWARE DEL ESTÁNDAR DE ENCRIPTACIÓN AVANZADO (AES, EN UNA PLATAFORMA FPGA, EMPLEANDO EL MICROCONTROLADOR PICOBLAZETM

    Directory of Open Access Journals (Sweden)

    J. Fernando Piñal M.

    2009-01-01

    Full Text Available En este trabajo analizamos las características del estándar de encriptación avanzado AES y suimplementación en una tarjeta de desarrollo FPGA Spartan-3E , utilizando una de las herramientas de procesamiento embebido del fabricante Xilinx®, el microcontrolador PicoBlaze¿. Además se diseñó un bloque en VHDL, el cual es el encargado de realizar la interfaz entre el microcontrolador y los periféricos de entrada- salida de la tarjeta. El ingreso de los datos a cifrar puede realizarse de dos maneras: mediante un teclado conectado al puerto PS/2 de la tarjeta o transmitiéndolos por el puerto serie de una computadora personal; para esto se diseñó una interfaz programada en Matlab¿. Los datos cifrados pueden observarse en el exhibidor LCD de la tarjeta de desarrollo, o bien se pueden transmitir en modo serial hacia una computadora personal. Estas opciones de funcionamiento del sistema se seleccionan mediante los interruptores deslizables de la tarjeta de desarrollo. La verificación del funcionamiento del sistema se realiza haciendo uso del documento oficial que describe a AES: FIPS-PUB 197. Aun cuando se implementó el algoritmo en un sistema basado en un procesador, se obtuvo un buen rendimiento. Se incluye la comparación del desempeño de nuestro diseño con otras arquitecturas que implementan también el mismo algoritmo.

  3. Digitale Antidiskriminierungsarbeit

    Directory of Open Access Journals (Sweden)

    Simone Rafael

    2017-12-01

    Full Text Available Rechtsextreme und andere Menschenfeind_innen nutzen das Internet intensiv, um Abwertung von Gruppen zu normalisieren und Bedrohung und Hass zu verbreiten. Wie tritt die digitale demokratische Zivilgesellschaft dem entgegen? – Mit Fakten und Argumentationsstrategien, der Stärkung von Gegenrede durch NGOs und Privatpersonen und digitaler Streetwork mit gefährdeten Jugendlichen.

  4. De digitale verdeners (vidunder

    Directory of Open Access Journals (Sweden)

    Angela Ndalianis

    2003-09-01

    Full Text Available I tidens blockbusterfilm spiller digitale special effects en stadig større rolle. Fra at have været et ‘usynligt’ redskab, der muliggjorde impone- rende stunts som bussen, der flyver over et hul i motorvejen i Speed, har digitale effekter erobret hovedrollen. Siden den morfende termi- nator i Terminator 2: Judgment Day og de realistiske dinosaurer i Jurassic Park har digitale elementer opnået en stjernestatus, der ofte overgår skuespillernes. Således er den digitale Gollum i Lord of the Rings: The Two Towers mere troværdig end de øvrige ‘fysiske’ stjer- ner. De amerikanske blockbusterfilm, der anvender en iøjnefaldende brug af digital æstetik, er ofte science fiction- og fantasy-film, der af den kritiske teori har været anset for “usundt slik for øjet.” Forfatteren viser, hvordan filmens digitale undere kan sættes i relation til Rene Descartes’ tanker om underet/det vidunderlige, der hensætter tilsku- eren i en æstetisk undren, der fører til en intellektuel trang til forståelse (som første gang stjernesystemet lod sig se i en kikkert. Samme und- ren bliver hos Blaise Pascal en ’afgrund’ (une abîme, der indgiver ære- frygt og fører os til det religiøse og mystiske, til overvejelser over natu- rens undere og Guds natur. Det digitale liv er ikke blot æstetik; det får sit eget, uforudsigelige liv - som de digitale figurer i The Two Towers der er programmeret til at slås, men foretrækker at flygte, og derfor må re- programmeres. Det digitale liv udfordrer os med intet mindre end over- vejelser over naturens orden, menneskets natur, teknologiens rolle, livet, døden og fremtiden.

  5. FPGA design

    CERN Document Server

    Simpson, Philip

    2010-01-01

    This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

  6. Materiales y recursos digitales

    OpenAIRE

    Silva i Galán, Josep M.

    2011-01-01

    La oferta de herramientas, materiales y contenidos educativos digitales es ilimitada y obliga al profesorado a buscarlos, seleccionarlos y almacenarlos de una forma muy distinta a cómo estaba acostumbrado. ¿De qué recursos dispone? ¿Cómo puede organizarlos? ¿Y compartirlos?

  7. Digital building planning - digital construction; Digitale Gebaeudeplanung - digitales Bauen

    Energy Technology Data Exchange (ETDEWEB)

    Friedrichs, K. [Karlsruhe Univ. (T.H.) (Germany). Fakultaet fuer Architektur

    1995-12-31

    In chapter 3 of the anthology about building control the following aspects are discussed: digital building planning and digital construction, which are characterised by an increasing complexity of planning, buildings, construction technology and construction processes. In this respect the digital-technical scenarios, passive and active objects as well as digital construction are described. (BWI) [Deutsch] Kapitel 3 des Sammelbandes ueber Building Control ist den Themen Digitale Gebaeudeplanung und Digitales Bauen gewidmet, die durch die zunehmende Komplexitaet von Planung, Gebaeuden, Bautechnologien und -prozessen bedingt sind. In diesem Zusammenhang werden folgende Themen angesprochen: Digitale technische Szenarien, passive und aktive Objekte sowie digitales Bauen. (BWI)

  8. Nativos digitales y aprendizaje

    Directory of Open Access Journals (Sweden)

    Ramón Ovelar Beltrán

    2012-04-01

    Full Text Available En el presente artículo se realiza una descripción y comentario de las aportaciones más relevan-tes que se han realizado en sobre el fenómeno de los "nativos digitales" o "Net Generation". Se recogen distintas posiciones sobre el desarrollo de nuevas habilidades cognitivas y nuevas tareas y necesidades de estas nuevas generaciones afectadas por el cambio tecnológico, así como sus implicaciones para las políticas educativas y prácticas docentes.

  9. Case Study: Derechos Digitales

    Directory of Open Access Journals (Sweden)

    Cameron Neylon

    2017-10-01

    Full Text Available Derechos Digitales is a Latin American advocacy and research network focussed on freedom on the internet, privacy and copyright reform. For the pilot project a specific IDRC funded project was the notional focus of study. However in practice the effort for considering data sharing was aimed at being organisation wide. The organisation already shares reports and other resources (particularly images and infographics by default. While open data was described as being “in the DNA of the organisation” there was little practice across the network of sharing preliminary and in-process materials. Some aspects of data collection on research projects, particularly to do with copyright and legal issues, have significant privacy issues and as the organisation focuses on privacy as one of its advocacy areas this is taken very seriously. Many materials from research projects are not placed online at all. Derechos Digitales run distributed projects and this creates challenges for consistent management. Alongside this the main contact at DD changed during the course of the pilot. This exchange exemplified the challenges of maintaining organisational systems and awareness through a personnel change.

  10. Development of γ dose rate monitor based on FPGA and single-chip microcomputer

    International Nuclear Information System (INIS)

    He Zhiguo; Ling Qiu; Guo Lanying; Yang Binhua

    2009-01-01

    A novelγdose rate monitor with multiple channels signal collection in which takes the FPGA as the core process chip and single-chip microcomputer as the data processor had been developed. This paper introduced the communication interface design between FPGA and MCU, and gave the data acquisition module and the function simulation chart designed by FPGA. In addition, the software and hardware design diagrams of MCU had been given in this paper. The maximum digitallization was carried on in the designing process. The experiments showed that the scheme for the system matched to the requests completely. (authors)

  11. Rapport om digitale oplysninger ved Aalborg Universitet

    DEFF Research Database (Denmark)

    Bønsing, Sten

    Rapport til Aalborg Universitets ledelse vedr. brug af digitale oplysninger i forbindelse med e-mailing, databaser, hjemmesider mv.......Rapport til Aalborg Universitets ledelse vedr. brug af digitale oplysninger i forbindelse med e-mailing, databaser, hjemmesider mv....

  12. Interconnectedness und digitale Texte

    Directory of Open Access Journals (Sweden)

    Detlev Doherr

    2013-04-01

    Full Text Available Zusammenfassung Die multimedialen Informationsdienste im Internet werden immer umfangreicher und umfassender, wobei auch die nur in gedruckter Form vorliegenden Dokumente von den Bibliotheken digitalisiert und ins Netz gestellt werden. Über Online-Dokumentenverwaltungen oder Suchmaschinen können diese Dokumente gefunden und dann in gängigen Formaten wie z.B. PDF bereitgestellt werden. Dieser Artikel beleuchtet die Funktionsweise der Humboldt Digital Library, die seit mehr als zehn Jahren Dokumente von Alexander von Humboldt in englischer Übersetzung im Web als HDL (Humboldt Digital Library kostenfrei zur Verfügung stellt. Anders als eine digitale Bibliothek werden dabei allerdings nicht nur digitalisierte Dokumente als Scan oder PDF bereitgestellt, sondern der Text als solcher und in vernetzter Form verfügbar gemacht. Das System gleicht damit eher einem Informationssystem als einer digitalen Bibliothek, was sich auch in den verfügbaren Funktionen zur Auffindung von Texten in unterschiedlichen Versionen und Übersetzungen, Vergleichen von Absätzen verschiedener Dokumente oder der Darstellung von Bilden in ihrem Kontext widerspiegelt. Die Entwicklung von dynamischen Hyperlinks auf der Basis der einzelnen Textabsätze der Humboldt‘schen Werke in Form von Media Assets ermöglicht eine Nutzung der Programmierschnittstelle von Google Maps zur geographischen wie auch textinhaltlichen Navigation. Über den Service einer digitalen Bibliothek hinausgehend, bietet die HDL den Prototypen eines mehrdimensionalen Informationssystems, das mit dynamischen Strukturen arbeitet und umfangreiche thematische Auswertungen und Vergleiche ermöglicht. Summary The multimedia information services on Internet are becoming more and more comprehensive, even the printed documents are digitized and republished as digital Web documents by the libraries. Those digital files can be found by search engines or management tools and provided as files in usual formats as

  13. Genfortryllelse i den digitale tidsalder

    DEFF Research Database (Denmark)

    Madsen, Theis Vallø

    , hvilket bl.a. kommer til udtryk i en ny vinylplade- og polaroidbillede-interesse. Denne undersøgelse går tilbage til begyndelsen af oplysningstiden, op igennem det 20. århundrede og frem til vores digitale kultur for at beskrive baggrunden og forestillingerne bag denne form for “analog æstetik”.......I den digitale tidsalder bliver uhyre mængder af information, billeder og musik noget nær frit tilgængelige, uendeligt reproducérbare og frigjort fra sit ”her” og ”nu”. I samme stund er der opstået en fornyet interesse for artefakter, der er stoflige, håndgribelige og u- eller anti-digitale...

  14. Visuel kommunikation på digitale medier

    DEFF Research Database (Denmark)

    Thorlacius, Lisbeth

    Visuel kommunikation på digitale medier er en teoretisk forankret bog, som med afsæt i nye begrebsudviklinger og aktuel forskning inden for feltet præsenterer de væsentligste visuelle virkemidler, som indgår på de digitale medieplatforme. Derudover gennemgås de mest udbredte genrer og aktuelle st...

  15. Digital Natives: Digitale Teknologier og Engagerende Publikumsoplevelser

    DEFF Research Database (Denmark)

    Smith, Rachel Charlotte; Iversen, Ole Sejer

    2011-01-01

    Nye teknologier, sociale medier og digitale kulturer stiller museerne overfor nye formidlingsmæssige udfordringer, men også muligheder. Brug af digitale teknologier kan skabe engagerende og dynamiske oplevelser i museumsverdenen der åbner for nye kommunikationsformer og inddragelse af publikum. Men...

  16. Byens Digitale Liv. Digital Urban Living

    DEFF Research Database (Denmark)

    Byens Digitale Liv udforsker de nye digitale lags udfordringer og potentiale inden for mediearkitektur, interaktive installationer og medieprodukter på mobile og andre platforme. Bogen formidler resultaterne af en række analyser og eksperimentelle udviklingsprojekter, foretaget i regi af forsknin...... forskningscentret Digital Urban Living fra 2008 til 2012....

  17. Dos generaciones de nativos digitales

    Directory of Open Access Journals (Sweden)

    Joaquín Linne

    Full Text Available A partir de encuestas, entrevistas y observaciones en la Ciudad Autónoma de Buenos Aires, afirmamos que existen dos generaciones de nativos digitales (ND: los jóvenes 1.0 y los adolescentes 2.0. Si bien ambas comparten características comunes, los 2.0 poseen rasgos propios: son una generación post-mail, suelen haberse criado alrededor de entornos digitales y manifiestan de modo online sus aspectos íntimos. Estos contenidos personales, que comparten con su grupo de pares a través de sitios de redes sociales, expresan una nueva concepción de la intimidad que podemos denominar "multimidad". A su vez, dividimos a los ND 2.0 según su nivel de alfabetización digital, condicionado por su entorno tecnológico, su capital cultural y su uso de las TIC, con el objetivo de brindar herramientas analíticas que contribuyan a mejorar las políticas públicas de inclusión digital.

  18. Digitale Editionen in den Altertumswissenschaften?

    Directory of Open Access Journals (Sweden)

    Friedrich Meins

    2016-02-01

    Full Text Available In his extensive study „Digitale Editionsformen“, Patrick Sahle gives a broad survey of the history of text-editions in general and the new possibilities as provided by digital technology. In the course of this, he passes harsh criticism on the „Critical edition“. In his eyes the „Critical edition“ is an outdated means, whose ontological and hence scientifical limitations are mainly a result of the technological limitations and ideological preconditions of the times when it came into being. This short paper argues that at least in the case of the „Critical edition“ as it is still the basis of Classical Studies both historical and linguistical, its own significance as an outcome of research cannot simply be depreciated against a general claim for „editions“ in a mere documentary meaning.

  19. Digitale Medien in der Grundschule

    Directory of Open Access Journals (Sweden)

    Birgit Eickelmann

    2013-06-01

    Full Text Available Mit der internationalen Grundschulleistungsstudie Trends in International Mathematics and Science Study (TIMSS 2011; vgl. Bos/Wendt/Köller/Selter 2012; Suchań/Wallner-Paschon/Bergmüller/Schreiner 2012 liegen aktuelle Daten zur schulischen und außerschulischen Nutzung digitaler Medien durch GrundschülerInnen sowie Lehrerdaten über den Einsatz von digitalen Medien in der Schule sowie im Fachunterricht in den Fächern Mathematik und Naturwissenschaften vor. Mit diesem Beitrag sollen die für die beteiligten Länder repräsentativen Daten genutzt werden, um Einblicke in die schulische und außerschulische Nutzung digitaler Medien durch Grundschulkinder am Ende der vierten Klasse zu geben. Dabei werden die Länder Deutschland und Österreich fokussiert und verglichen. Die Befunde werden theoretisch im Gesamtkontext der Medienpädagogik und vor dem Hintergrund der Qualitätsentwicklung von Schulsystemen im internationalen Vergleich diskutiert.With the international large-scale assessment study TIMSS 2011 (Trends in International Mathematics and Science Study; cf. Bos/Wendt/Köller/Selter 2012; Suchań/Wallner-Paschon/Bergmüller/Schreiner 2012 rich data concerning primary students’ and teachers’ use of computers is available. This data gives insights into the use of digital media both at school and in subject specific courses such as mathematics and science. With this contribution representative TIMSS-data is used to examine the role of new technologies at the end of Grade 4. In this process, a description and a comparison of the educational systems in Germany and in Austria will be focused. Findings will be discussed in the light of media education and the quality of school systems in the context of international developments.

  20. Museos virtuales: nuevos balcones digitales

    Directory of Open Access Journals (Sweden)

    Laura Regil Vargas

    2006-01-01

    Full Text Available Las tecnologías están provocando cambios en los museos. Por una parte, se transforma el espacio museístico; por otra, la tecnología —como herramienta— genera nuevas formas de creación artística y, en consecuencia, estas dos modificaciones repercuten en la formación de sus públicos. El vertiginoso desarrollo de las tecnologías digitales ha generado posturas extremas. Por un lado, desde el ágora donde se reúnen los apocalípticos, se habla ya del final de los museos; por el otro, entre los integrados, se especula con su evolución. Sabemos que la única conjura frente a posturas absolutas es la reflexión crítica. De ahí, mi invitación a analizar la transformación que las tecnologías han provocado en el continente y en el contenido.

  1. Categorizando a los usuarios de sistemas digitales

    OpenAIRE

    Hernández y Hernández, Denise; Ramírez Martinell, Alberto; Cassany, Daniel

    2014-01-01

    Repasamos las categorías más utilizadas para aludir a las características de las personas que utilizan algún tipo de sistema digital, ya sea por su grado de participación en la comunicación global y en los sistemas web -1.0 o 2.0-; por la actitud que toman ante el contenido digital -consumidores o productores-; por su intermitencia en el mundo digital -residentes o visitantes-; o por el momento histórico en el que nacieron -nativos digitales o inmigrantes digitales-, con el propósito de refle...

  2. CATEGORIZANDO A LOS USUARIOS DE SISTEMAS DIGITALES.

    OpenAIRE

    Denise Hernández y Hernández; Alberto Ramírez-Martinell; Daniel Cassany

    2014-01-01

    Repasamos las categorías más utilizadas para aludir a las características de las personas que utilizan algún tipo de sistema digital, ya sea por su grado de participación en la comu- nicación global y en los sistemas web -1.0 o 2.0-; por la actitud que toman ante el contenido digital -consumidores o productores-; por su intermitencia en el mundo digital -residentes o visitantes-; o por el momento histórico en el que nacieron -nativos digitales o inmigrantes digitales-, con el propósito de ref...

  3. Vertrouwen in vrije digitale X.509 certificaten

    NARCIS (Netherlands)

    Koot, M.

    2008-01-01

    Public Key Infrastructuren (PKIs) worden vanwege hun gecentraliseerde karakter waarschijnlijk eerder geassocieerd met inbreuk op privacy dan met privacy bescherming. Dit artikel laat PKIs van een andere kant zien door een beschouwing van CAcert, een non-profit vereniging die kosteloos digitale X.509

  4. FPGA Vision Data Architecture

    Science.gov (United States)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  5. From OO to FPGA :

    Energy Technology Data Exchange (ETDEWEB)

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  6. FPGA programming using FX3

    CERN Document Server

    Calleja, Stefano

    2014-01-01

    An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

  7. WATERMARK RESISTENTE EN EL DOMINIO DE LAS FRECUENCIAS DE IMÁGENES DIGITALES PARA SU AUTENTICACIÓN SEGURA MEDIANTE AUTÓMATAS CELULARES

    Directory of Open Access Journals (Sweden)

    Luz Fátima Huallpa Vargas

    2011-01-01

    Full Text Available En este trabajo se presenta el desarrollo de un procedimiento de autenticación de imágenes digitales combinando diversos métodos relacionados con watermarks (marcas de agua digitales y métodos de cifrado, con el fin de proteger los derechos de autor de imágenes digitales. Para que este procedimiento sea robusto, imperceptible y resistente a diferentes ataques intencionales o no intencionales se trabaja en el dominio de las frecuencias de la imagen utilizando la Transformada Discreta del Coseno (Discrete Cosine Transform, DCT. Para agregar mayor nivel de protección y seguridad a la imagen marcada, se cifra el mensaje insertado a partir de una clave del autor empleando el método de Autómatas Celulares. El mensaje insertado es resistente a la compresión JPEG, a los ruidos y filtros gaussiano y salt-and-pepper. La extracción del mensaje se realiza a partir de la imagen marcada para lo cual se hace uso estricto de la clave del autor para verificar la autenticidad del mismo.

  8. Digital techniques. Special issue; Digitale techniek. Themanummer

    Energy Technology Data Exchange (ETDEWEB)

    Rigter, L.J.M. [Siemens Nederland, Building Technologies, Den Haag (Netherlands); Meiring, O.; Hut, W. [Getronics Industrial Automation, Amsterdam (Netherlands); Van Dijk, K.W. [Van Dijk Woon-ICT Adviseur Domotica, Dordrecht (Netherlands); Aartman, M.J. [Siemens Nederland, Fire Safety, Den Haag (Netherlands); Spies, R.J. [Deerns raadgevende ingenieurs, Rijswijk (Netherlands); Burgers, H. [Honeywell, Amsterdam (Netherlands); Stouthart, F.J. [Merlijn Media, Waddinxveen (Netherlands); Van Gurp, J.P. [GTI Electroproject, Zaanstad (Netherlands); Draijer, G.W.

    2003-06-01

    In 11 articles several aspects of the principles and uses of digital techniques in buildings are highlighted: Building Automation and Control network (BACnet); trends in building automation and building management; technology and uses of domotics; developments and trends in fire alarm systems; control of thermal comfort (LonWorks); process control technology; use of internet in building management systems; and frequency control of indoor climate systems. [Dutch] In 11 artikelen wordt aandacht besteed aan de principes en het gebruik van digitale technieken in gebouwen: Building Automation and Control network (BACnet); gebouwautomatisering en gebouwbeheer nu en in de nabije toekomst; techniek, toepassing en uitvoering van domotica; ontwikkelingen en trends in brandmelders; het gebruik van LonWorks voor flexibele ruimtecomfortregelingen; digitale technieken in de meet- en regeltechniek; gebouwbeheerssytemen met geintegreerde internettechnologie; en frequentiegeregelde aandrijvingen voor de klimaattechniek.

  9. Digitale Indfødte - Findes De?

    DEFF Research Database (Denmark)

    Ivang, Reimer

    2011-01-01

    De digitale indfødte er i flere år blevet omtalt som samfundets redning. De har fået de grundlæggende IT kompetencer med modermælken og de anvender sociale medier, smartphones osv. i stort omfang. Når denne tsunami af progressive IT-individer rammer vores arbejdsmarked skal meget ændres. Spørgsmå......De digitale indfødte er i flere år blevet omtalt som samfundets redning. De har fået de grundlæggende IT kompetencer med modermælken og de anvender sociale medier, smartphones osv. i stort omfang. Når denne tsunami af progressive IT-individer rammer vores arbejdsmarked skal meget ændres...

  10. Medios digitales en Ecuador: perspectivas de futuro

    Directory of Open Access Journals (Sweden)

    María Isabel Punín Larrea

    2014-01-01

    Full Text Available El avance de la tecnología, en especial, en el ámbito de la comunicación, obliga a los medios a evolucionar constantemente para no morir en un escenario marcado por una serie de transformaciones y cambios mediáticos que han afectado al periodismo como profesión y a los medios de comunicación, proceso que ha generado estudios de todo orden. Este trabajo analiza el panorama mediático digital en Ecuador, las características de cultura periodística y el consumo de contenidos en la Red. Describe las tendencias de los principales medios digitales en el país, seleccionados para realizar un estudio de caso. El artículo toma como referencia central el estudio de las diez tendencias digitales en medios de comunicación de Cerezo-Gilarranz, especialista en estrategias digitales. Posteriormente se identifican las deficiencias que tienen los medios en Ecuador; principalmente por la falta de domino de los entornos tecnológicos y la escasa vinculación del proyecto empresarial y periodístico con soportes tecnológicos e innovadores, como el uso de redes sociales... El resultado final es una guía detallada de las debilidades y las fortalezas de cada medio digital en estudio. Asimismo, este trabajo propone tendencias fiables para que los medios estudiados puedan encaminarse firmes en entornos digitales, asumiendo a las herramientas tecnológicas como oportunidad de negocio y de servicio.

  11. Digitalisering af arbejdet og digitale platforme i Danmark

    DEFF Research Database (Denmark)

    Ilsøe, Anna; Madsen, Louise Weber

    2017-01-01

    Halvdelen af de erhvervsaktive i Danmark bruger i udstrakt grad computere eller andre digitale devices i deres arbejde, mens hver femte bruger computerstyrede maskiner. Flere end 100.000 danskere tjener penge via digitale arbejds- eller kapitalplatforme. Det viser den hidtil største undersøgelse ...

  12. The FPGA Pixel Array Detector

    International Nuclear Information System (INIS)

    Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

    2013-01-01

    A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

  13. Flexible experimental FPGA based platform

    DEFF Research Database (Denmark)

    Andersen, Karsten Holm; Nymand, Morten

    2016-01-01

    This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

  14. Biosorción de metales pesados empleando lodos activados

    OpenAIRE

    Santos Bonilla, Karín Ángela; Santos Bonilla, Karín Ángela

    2010-01-01

    Aunque las tecnologías existentes, tales como: precipitación química, osmosis inversa, intercambio iónico y separación por membranas representan una alternativa potencial para el tratamiento de drenajes ácidos de mina, presentan significativas desventajas como requerimientos altos de reactivos y energía; además de la generación de lodos tóxicos y otros subproductos a disponer. En este contexto, la biosorción empleando lodos activados procedentes de una planta de tratamiento de aguas residuale...

  15. Habilidades digitales y lectura en entornos digitales: Desarrollos recientes sobre comprensión lectora digital

    Directory of Open Access Journals (Sweden)

    Debora I. Burin

    2016-05-01

    Full Text Available Los estudiantes nacidos en la era de las tecnologías digitales (los “nativos digitales” pueden tener mayor acceso a las mismas, pero la idea de que aprenden más y mejor solo por implementar dispositivos de aprendizaje con la última tecnología disponible es simplista y no se correspondería con la evidencia. El uso para objetivos académicos requeriría habilidades digitales. Éstas aluden no solo al dominio técnico y operacional, sino sobre todo al dominio cognitivo, como habilidades de búsqueda y navegación, integración, evaluación de fuentes, y de uso estratégico de la información. Se han investigado mediante cuestionarios, o tareas informatizadas que plantean escenarios de búsqueda y comprensión de materiales. Entre las medidas de auto-informe, se ha avanzado en diseñar cuestionarios con propiedades psicométricas conocidas. Entre las segundas, se han creado entornos de tarea que remedan la situación en Internet (sitios, páginas… y se toman indicadores de precisión en las tareas, tiempos, y caminos de navegación. Si bien las investigaciones todavía son escasas, apuntan a una relación entre habilidades digitales y comprensión lectora, y cuando se investiga en tareas en ambientes controlados, la definición de las habilidades digitales se solapa con la competencia lectora digital (p.ej., en las pruebas PISA. Futuras investigaciones deben pormenorizar en las relaciones entre distintos aspectos de las habilidades digitales, en relación a los resultados en comprensión lectora u otros objetivos de aprendizaje, para poder caracterizar estrategias de intervención educativa.

  16. Competencias docentes digitales: propuesta de un perfil

    OpenAIRE

    Adriana Rangel Baca

    2015-01-01

    En este artículo se presenta la propuesta de un perfil de competencias docentes digitales y se describen las dimensiones, competencias e indicadores que lo componen. Se analizan distintas fuentes para determinar el conjunto de recursos a movilizar por los docentes en materia digital y se elabora una versión preliminar del perfil, la cual es puesta a consideración de un grupo de expertos en el uso de las Tecnologías de la Información y la Comunicación (TIC) para su validación. Los resultados m...

  17. FPGA-Based Sonar Processing

    National Research Council Canada - National Science Library

    Graham, Paul; Nelson, Brent

    1998-01-01

    This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays...

  18. Exploration of Heterogeneous FPGA Architectures

    Directory of Open Access Journals (Sweden)

    Umer Farooq

    2011-01-01

    mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

  19. eLeadership: il digitale sfida i manager

    Directory of Open Access Journals (Sweden)

    Andrea Granelli

    2017-06-01

    Per questo motivo bisogna reintrodurre il pensiero critico soprattutto nei confronti del digitale e sfatare i suoi luoghi comuni, sempre più diffusi e consolidati tra i non esperti, grazie anche allo zampino interessato dei fornitori di soluzioni digitali e del mondo dei giornalisti, divulgatori, champion, che gli ruota attorno.  Pertanto anche la conoscenza dei lati oscuri gioca un ruolo educativo fondamentale. Anzi, volendo parafrasare il celebre incipit di Anna Karenina: tutte le applicazioni utili del digitale sono simili fra loro; ogni lato oscuro del digitale, invece, è problematico a modo suo.

  20. Cálculo de la distribución espacial de la insolación potencial en el terreno empleando MDE en un ambiente SIG

    Directory of Open Access Journals (Sweden)

    Alberto Gómez Tagle Chávez

    2012-02-01

    Full Text Available Se presenta un estudio de caso donde se calcula la insolación potencial (IP y la insolación real (IR para un área pequeña (634.4 ha empleando los programas Insol_Día e Insol_Mes a partir de un modelo digital de elevaciones (MDE. Estos programas calculan la IP utilizando la ubicación geográfica de la cuenca y el MDE mediante procedimientos de sistemas de información geográfica (SIG y ecuaciones de geometría esférica. La IR se obtuvo empleando los mapas digitales de IP calculada y corrigiendo los datos con información del observatorio meteorológico (15-0040, Morelia, Mich. del Servicio Meteorológico Nacional. Los resultados son una serie de mapas digitales dentro de un SIG que permiten conocer la distribución espacial de la IP y la IR en esta zona, para fechas definidas, meses enteros, estaciones y totales anuales. La IP anual máxima fue de 4 389 horas, mientras que la mínima fue de 2 946 horas. Los valores de IR máxima y mínima fueron 2 144.9 y 1 439.7 horas. Los promedios diarios anuales de IP máximo y mínimo fueron de 12.05 hr/día y 8.07 hr/día, siendo para IR de 5.88 hr/día y 3.944 hr/día, indicando una gran diferencia entre la IP y la IR. Se considera que este tipo de información puede ser de gran utilidad en estudios de distribución de la vegetación, balances hidrológicos, distribución de propiedades edáficas, velocidad de intemperismo de los materiales geológicos, arquitectura bioclimática y otras áreas donde la distribución espacial de la insolación se considere como una variable importante.

  1. Det digitale interaktive fjernsyn i hverdagslivet

    DEFF Research Database (Denmark)

    Bjørner, Thomas

    2007-01-01

    , at den digitale teknologi indpasses i eksisterende mønstre for tv-sening. Med baggrund i forsøgskanalen TV2/Nord-Digital, som var den første kanal der udsendte digitalt interaktivt tv i Danmark, vil denne artikel give nogle svar på, hvad der sker når digitalt tv (med de øgede interaktive muligheder......Digitaliseringen af tv-mediet er allerede i fuld gang, og der er i Danmark fastlagt en analog slukdato for public servicekanalerne i 2009. I forlængelse heraf leverer denne artikel en række indsigter i, hvordan den nye teknologi potentielt forandrer hverdagen, men samtidig er det også en pointe...

  2. Digitale prøver – et litteraturstudie

    Directory of Open Access Journals (Sweden)

    Karen Louise Møller

    2015-10-01

    Full Text Available Digitale prøveformer bliver efterhånden mere og mere udbredte. Denne artikel er baseret på et litteraturstudie foretaget for at få indsigt i primært forskningslitteraturen om digitale prøveformer. I artiklen præsenterer vi de forskellige typer digitale prøver, der omtales og diskuteres i litteraturen, og vi beskriver de potentielle fordele af bl.a. økonomisk, administrativ og pædagogisk karakter, der ifølge litteraturen kan opnås ved at bruge digitale prøver. Vi beskriver endvidere de udfordringer og potentielle ulemper, der kan være forbundet med indførelse af digitale prøver. Det drejer sig bl.a. om udfordringer hvad angår prøvesystem, organisation, teknologi, kompetenceudvikling og uddannelseskultur. Vi beskriver i artiklen en række konkrete eksempler på digitale prøver, og vi præsenterer resultater fra undersøgelser af underviseres og studerendes oplevelser med digitale prøveformer. Against the backdrop of the rapid spread of digitized tests and exams, this article sets out to present some of the results of a literature study carried out with the aim of gaining insight into the research literature on this topic. The article presents different types of tests, focusing on the financial, administrative, and pedagogical advantages described and discussed in the literature as potentially attainable through the use of digitized exams. In addition, the challenges and potential problems connected with the introduction of digitized tests are described. Among these are challenges related to the test system or to competence development as well as organizational, technological, and cultural challenges. Finally, the article provides concrete descriptions of tests and presents results from select studies of teacher and student experiences of digitized tests.

  3. Pensamiento computacional: rompiendo brechas digitales y educativas

    Directory of Open Access Journals (Sweden)

    Mauricio Javier Rico

    2018-03-01

    Full Text Available Este artículo describe una iniciativa pragmática de colaboración internacional en el ámbito de la formación del Pensamiento Computacional de los jóvenes estudiantes de Colombia. El proyecto “Introducción del Pensamiento Computacional en las escuelas de Bogotá y Colombia” (RENATA/EHU involucra el pensamiento computacional en el currículo escolar de una manera asequible y eficaz para los estudiantes, los docentes y los centros educativos. Las nuevas generaciones de este país tienen ahora la posibilidad de adquirir habilidades del siglo XXI al igual que las nuevas generaciones de otros países donde la computación es parte del currículo educativo desde los primeros años escolares. Este proyecto está en su fase de implementación en escuelas de diferentes regiones de Colombia; puede ser un ejemplo de cómo romper brechas digitales y educativas utilizando las TIC y la educación como principales herramientas de transformación social.

  4. Det digitale interaktive fjernsyn i hverdagslivet

    Directory of Open Access Journals (Sweden)

    Thomas Bjørner

    2007-04-01

    Full Text Available Digitaliseringen af tv-mediet er allerede i fuld gang, og der er i Danmark fastlagt en analog slukdato for public servicekanalerne i 2009. I forlængelse heraf leverer denne artikel en række indsigter i, hvordan den nye teknologi potentielt forandrer hverdagen, men samtidig er det også en pointe, at den digitale teknologi indpasses i eksisterende mønstre for tv-sening. Med baggrund i forsøgskanalen TV2/Nord-Digital, som var den første kanal der udsendte digitalt interaktivt tv i Danmark, vil denne artikel give nogle svar på, hvad der sker når digitalt tv (med de øgede interaktive muligheder vinder indpas i husstanden. Hvem skal bestemme i forhold til hvad der skal ses af interaktivt indhold? Vil digitaliseringen dermed fremme den stigende tendens til at vi ser mere tv hver for sig? Og ønsker seerne overhovedet at være interaktive med deres fjernsyn – og i givet fald om hvad og hvorfor?

  5. Modelado de acervos en bibliotecas digitales

    Directory of Open Access Journals (Sweden)

    Carlos Proal A.

    2004-01-01

    Full Text Available Este artículo expone los distintos tipos de datos que son comunes en una biblioteca digital, así como las técnicas y herramientas para su manipulación. Se considera la diversidad de recursos y servicios que las conforman por lo que se proponen modelos alternativos para almacenamiento y recuperación de información, los cuales mejoran la extensión y desempeño tanto en las colecciones como en los servicios desarrollados para su manejo. En particular, estas propuestas permiten integrar por primera vez en una sola biblioteca digital, datos estructurados, semiestructurados y no estructurados. La idea de modelos de datos está basada en las experiencias de desarrollo y uso de las bibliotecas digitales, cuya arquitectura ha evolucionado en un escenario real durante casi cuatro años. Se describe la integración de nuevos componentes y servicios para la recuperación de información, los cuales extienden y armonizan con la estructura actual. Finalmente se mencionan las evaluaciones que se obtuvieron al analizar las ventajas y desventajas de la incorporación y combinación de estos servicios, así como del uso de los modelos alternativos propuestos.

  6. Repositorios digitales y software open source

    Directory of Open Access Journals (Sweden)

    Doria, María Vanesa

    2015-06-01

    Full Text Available En la actualidad las universidades se encuentran en constante evolución, fruto de la transformación generada por la sociedad de la información y el conocimiento, donde la transversalidad son las Tecnologías de la Información y Comunicación (TIC, que tienen como objetivo ampliar el acceso a la información y el conocimiento a través de su herramienta digital más distinguida, Internet. Las universidades retroalimentan su conocimiento e información, mediante las producciones científicasacadémicas, y para promover el acceso a ellas, muchas universidades están inclinándose al movimiento del Acceso Abierto (AA siguiendo la vía verde en el desarrollo de repositorios digitales (RD. Para la creación de RD es necesario analizar los software open source disponibles, dado que estos son las herramientas que facilitan la automatización de los mismos. El presente estudio se centra en el análisis de los software open source existentes en el mercado.

  7. Mediología, icono, redes sociales digitales.

    OpenAIRE

    Prado Flores, Rogelio del

    2016-01-01

    En el presente trabajo se abordan los temas de la mediología y las redes sociales digitales. Se analizan las categorías de icono digital, de lo virtual, de la interacción en las redes sociales digitales, con el apoyo de la hermenéutica analógica, la deconstrucción, la ética y la sociología desde el enfoque de un realismo crítico. Analizo el tipo de interacción que acontece en las redes sociales digitales y sus efectos en el tejido social, con la intención de invitar a un uso prudente y respon...

  8. Las tecnologías digitales en contextos interculturales.

    Directory of Open Access Journals (Sweden)

    Pedro Hepp K

    2009-07-01

    Full Text Available El presente trabajo ofrece un panorama general sobre la educación chilena con énfasis en los sectores de población más vulnerable. En seguida, aborda el uso de las tecnologías digitales en contextos interculturales en general y en el ámbito mapuche en particular. A continuación describe el estado de las tecnologías digitales en Chile y las oportunidades que esta situación ofrece para el trabajo educativo intercultural. Finalmente, presenta la línea de tecnologías digitales en contextos indígenas e interculturales del Núcleo Iniciativa Científica Milenio Centro de Investigación en Educación en Contexto Indígena e Intercultural (CIECII de la Universidad Católica de Temuco

  9. Generación de contenidos educativos digitales

    OpenAIRE

    Russo, Claudia Cecilia; Durán, Laura; Calderone, Marina; Saenz, Mariana; Sarobe, Mónica; Alonso, Nicolás; Esnaola, Leonardo; Pérez, Daniela; De Vito, María Cecilia; Piergallini, Maria Rosana; Segura, Natalia; Picco, Trinidad; Osella Massa, Germán Leandro; Ramón, Hugo Dionisio

    2014-01-01

    La presente línea de investigación propone desde una mirada interdisciplinaria determinar y sistematizar aspectos determinantes en el desarrollo de materiales didácticos digitales a fin de generar un manual de buenas prácticas para la producción, administración y almacenamiento. Se consideran materiales digitales aquellos desarrollados para su utilización en los EVEA (Entornos Virtuales de Enseñanza y Aprendizaje), PLE (Entornos Personales de Aprendizaje), televisión digital, etc. A la hor...

  10. Strategie di spazializzazione dei contenuti nel GeniusLoci Digitale

    Directory of Open Access Journals (Sweden)

    Davide Gasperi

    2013-07-01

    Full Text Available GeniusLoci Digitale is a software architecture of virtual tour that integrates various multimedia technologies (3D computer graphics, panoramas, dynamic maps, movies, pictures to represent the identity of places. The designer is interested in reproducing virtually complex aspects that define a context, which means the effect of meaning that distinguishes one place. GeniusLoci Digitale is in fact an architecture that evolves in search of a reproductive and communicative function which is recognizable to extend its development to the Open Source community.

  11. The MCD circuit based on FPGA

    International Nuclear Information System (INIS)

    Vu Quoc Trong

    2003-01-01

    Two MCD circuits based on different FPGA are presented as results of the study of the MAX+PLUS II software and FPGA devices. An external memory like 62256 and programmed EPM7064S will be able to form a MCD with 8 kilo channels. (NHA)

  12. Nativos digitales. Presentación.

    Directory of Open Access Journals (Sweden)

    Manuel Gertrudix-Barrio

    2012-06-01

    Full Text Available El término “nativo digital”, acuñado por Mark Prensky (2001, 2005 forma parte ya del imaginario colectivo de nuestra sociedad, al designar a aquellos grupos poblacionales (esencialmente jóvenes y adolescentes que han crecido en un marco tecnológico digital (ordenadores, Internet, teléfonos móviles, MP3... y cuyos usos y habilidades en relación a estos medios está completa- mente naturalizado; de alguna manera, podríamos decir , que se ha “transparentado” el dominio digital y discreto de la tecnología a favor de una experiencia de usuario integral. La evolución de la Red hacia una Red Universal Digital y la consolidación del fenómeno denominado Web 2.0, está produciendo una modificación de las conductas, usos y competencias de los internautas. Este proceso es más acusado en los denominados “nativos digitales”, y, especialmente entre los adoles- centes y jóvenes. En este marco, los sistemas de colaboración social facilitan nuevos mo- delos de creación compartida de la informa- ción (elaboración y publicación de imágenes fijas y vídeos, elaboración de weblogs y podcasting, elaboración participada de con- tenidos en wikis, sindicación de contenidos digitales, etc. de gestión del conocimiento (utilización y participación de buscadores 2.0, marcadores sociales, sistemas de perso- nalización de la información, sistemas de ranking y directorios sociales, sistemas de geoposicionamiento de contenidos, etc., y de relaciones sociales (participación activa en redes y comunidades virtuales, entornos multijugador , sistemas de comunicación en Red, etc.

  13. Autonomous Lawnmower using FPGA implementation.

    Science.gov (United States)

    Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

    2016-11-01

    Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

  14. 'De digitale elever' som genstand for ledelse af læring i folkeskolen

    DEFF Research Database (Denmark)

    Stenbøg, Sofie

    2016-01-01

    Mange børn er i dag allerede fra en tidlig alder erfarne teknologibrugere. Denne omstændighed har fået flere folkeskoler til at medtænke elevernes digitale erfaringer og kompetencer fra fritidslivet som centrale ressourcer i undervisningen. Kapitlet undersøger, hvordan ’de digitale elever’ på...... forskellige måder gøres til genstand for ledelse på en skole, der arbejder med at inddrage elevernes digitale erfaringer og kompetencer gennem digitalt projektarbejde. Kapitlet viser, at der knytter sig en lang række kausale antagelser og forhåbninger til de digitale elever, og at disse virker bestemmende...... for både lærerens ledelsesopgave og rollefordelingen mellem lærer og elever i det digitale projektarbejde. Disse antagelser og forhåbninger diskuteres kritisk i lyset af nyere studier af folkeskoleelevers digitale kompetencer....

  15. Digitale Bildung› und die Genealogie digitaler Kultur: historiographische Skizzen

    Directory of Open Access Journals (Sweden)

    Benjamin Jörissen

    2016-10-01

    Full Text Available Wenn Aspekte ‹Digitaler Kultur› und Effekte der ‹Digitalisierung› der Selbst- und Weltverhältnisse thematisiert werden – vom Selfie über das quantified Self zur Big Data – so geschieht dies meist unter der Perspektive emergenter medientechnologischer Brüche und Umbrüche von Kultur. Man findet entsprechend dort, wo überhaupt historische Perpektiven bemüht werden, vor allem technik-, medien- und kommunikationszentrierte Emergenznarrationen. Es stellt sich angesichts der enormen Entwicklungsgeschwindigkeit der Digitalisierung jedoch die Frage nach ihren kulturellen Möglichkeitsbedingungen. Die offenkundig hohe Anschlussfähigkeit des Digitalen setzt auf – prinzipiell bekannten – kulturhistorischen Strukturbildungen auf, die ihm überhaupt erst ‹Bedeutung› geben können. Eine solche ‹Digitalisierung avant la technique› skizziert der Beitrag anhand dreier historischer Prozesslinien seit der Neuzeit – der Quantifizierung von Zahlverständnissen, der Organisation von ‹Wissen› im proto-datenbankförmigen Tableau und der Verknüpfung von Subjektivität und Sichtbarkeit.

  16. Multichannel analyzer embedded in FPGA; Analizador multicanal embebido en FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98060 Zacatecas, Zac. (Mexico); Ordaz G, O. O. [Universidad de Cordoba, Departamento de Arquitectura de Computadores, Electronica y Tecnologia Electronica, Campus de Rabanales, Ctra. N-IVa Km 396, 14071 Cordoba (Spain); Bravo M, I., E-mail: angelogarciad@hotmail.com [Universidad de Alcala de Henares, Departamento de Electronica, Campus Universitario, Carretera Madrid-Barcelona Km 33.600, 28801 Alcala de Henares, Madrid (Spain)

    2017-10-15

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  17. La protección de los contenidos digitales en España

    OpenAIRE

    Rodríguez de las Heras Ballell, Teresa

    2010-01-01

    En: Jornadas abiertas: investigadores, empresas y estudiantes. Protección del software y contenidos digitales. Getafe, 21 de diciembre de 2010 Esta jornada persigue dar respuesta a las dudas de los investigadores y profundizar en los aspectos relacionados con la protección de los contenidos digitales con expertos sobre: Protección intelectual de los contenidos digitales. Aspectos legales a tener en cuenta. Gestión y acceso a los contenidos digitales en Internet. Aspectos práct...

  18. Barrierefreiheit zur Routine machen – Praxisfall: Digitale Bibliothek

    Directory of Open Access Journals (Sweden)

    Susanne Baudisch

    2015-04-01

    Full Text Available Sechs Jahre sind vergangen seit Deutschland am 24. Februar 2009 die Behindertenrechtskonvention der Vereinten Nationen (BRK, die die volle Teilhabe aller Menschen an der Gesellschaft als Menschenrecht festschreibt, ratifizierte. Bereits seit 2002 gibt es in Deutschland ein Behindertengleichstellungsgesetz (BGG, den barrierefreien Zugang zu Informations- und Kommunikationstechnologien regelt die Barrierefreie Informationstechnik-Verordnung (BITV. Aus Sicht des Gesetzgebers sind die Rahmenbedingungen gegeben, Barrierefreiheit gehört inzwischen zum gängigen Vokabular im öffentlichen und teils auch privatwirtschaftlichen Bereich. Längst möchte man meinen, es sei ein alter Hut, Barrierefreiheit als Kernanliegen zu thematisieren oder gar einzufordern. Dies betrifft auch den rasant wachsenden Bereich digitaler Medien, der Wissen und Bildung für jedermann verfügbar macht - oder machen sollte. Vor diesem Hintergrund stellen sich die Autoren der Frage, inwieweit Barrierefreiheit in den digitalen Angeboten wissenschaftlicher und öffentlicher Bibliotheken in Deutschland angekommen ist; ob diese Angebote tatsächlich von allen genutzt werden können. Ausgehend von rechtlichen Grundlagen und Normen werden Formate und Standards für barrierefreie Netzpublikationen an Beispielen diskutiert. Im Fokus stehen einerseits Werkzeuge zum Suchen und Finden digitaler Information (Kataloge und Rechercheoberflächen, andererseits Ausgabeformate digitaler Dokumente (wie XML, PDF, EPUB oder TEI. Den Abschluss bilden Empfehlungen für (Digitale Bibliotheken und deren Verbände, um Barrierefreiheit künftig zur Routine zu machen. Das Fazit: Barrierefreiheit muss gewollt, geplant und sinnvoll umgesetzt werden. Technische Komponenten sind ein wichtiger, doch meist erst der zweite Schritt.

  19. Multichannel analyzer embedded in FPGA

    International Nuclear Information System (INIS)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Bravo M, I.

    2017-10-01

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  20. Irradiation test of FPGA for BES III

    International Nuclear Information System (INIS)

    Chen Yixin; Liang Hao; Xue Jundong; Liu Baoying; Liu Qiang; Yu Xiaoqi; Zhou Yongzhao; Hou Long

    2005-01-01

    The irradiation effect of FPGA, applied in Front-end Electronics for experiments of High-Energy Physics, is a serious problem. The performance of FPGA, used in the front-end card of Muon Counters of BES III project, needs to be evaluated under irradiation. SEUs on Altera ACEX 1K FPGA, observed in the experiment under the irradiation of γ ray, 14 and 2.5 MeV neutrons, was investigated. The authors calculated involved cross-section and provided reasonable analysis and evaluation for the result of the experiment. The conclusion about feasibility of applying ACEX 1K FPGA in the front-end card of the readout system of Muon Counters for BES III was given. (authors)

  1. Algorithmic strategies for FPGA-based vision

    OpenAIRE

    Lim, Yoong Kang

    2016-01-01

    As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

  2. Protection and Control with FPGA technology

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-03-15

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

  3. Protection and Control with FPGA technology

    International Nuclear Information System (INIS)

    Sohn, K. Y.; Yi, W. J.; Koo, I. S.

    2012-01-01

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper

  4. Tethered Forth system for FPGA applications

    Science.gov (United States)

    Goździkowski, Paweł; Zabołotny, Wojciech M.

    2013-10-01

    This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

  5. El Español y El Confidencial, exponentes del periodismo deportivo de datos en los medios nativos digitales españoles

    Directory of Open Access Journals (Sweden)

    José Luis Rojas Torrijos

    2016-11-01

    Full Text Available La presente investigación tiene como objetivo evaluar el grado de desarrollo y la potencialidad del periodismo de datos en la información deportiva en España a través del estudio de dos de los medios nativos digitales de información general más destacados, El Español y El Confidencial. Para ello, se ha realizado un análisis de contenido de las piezas publicadas por estos medios en el periodo comprendido entre febrero de 2015 y julio de 2016 y diferentes entrevistas a sus respectivos responsables de Deportes y Análisis de Datos; todo ello con el fin de comprobar si en este campo se han empezado a desarrollar técnicas de análisis de estadística avanzada y de representación visual de datos que ya se están empleando en otras áreas informativas y en otros países.

  6. Allemaal digitaal : Een overzicht van digitale spelvormen voor mensen met een licht verstandelijke beperking

    NARCIS (Netherlands)

    Alyssa de Kruif; Carly Kuijper; Josje Louisse

    Voor u ligt een overzicht van vrij toegankelijke digitale spelvormen ter bevordering van de zelfredzaamheid van mensen met een licht verstandelijke beperking. In dit overzicht vindt u digitale spelvormen die beschikbaar zijn als website en/of als applicatie voor op de smartphone of tablet. Voor de

  7. Quickscan QTI addendum #1 - Usability study of QTI for De Digitale Universiteit

    NARCIS (Netherlands)

    dr. Pierre Gorissen

    2003-01-01

    De Digitale Universiteit (DU) performed a quickscan to determine the usability of the IMS Question and TestInteroperability (QTI) specification as a format to store questions and tests developed for and by the consortium. The original report is available in Dutch from the website of De Digitale

  8. Fault tolerance based on serial communication of FPGA

    International Nuclear Information System (INIS)

    Peng Jing; Fang Zongliang; Xu Quanzhou; Hu Jiewei; Ma Guizhen

    2012-01-01

    There maybe appear mistake in serial communication. This paper was described the intellectual detector of γ dose ratemeter communication with FPGA. The software of FPGA designed the code about fault tolerance, prevented mistake effectively. (authors)

  9. Computer vision camera with embedded FPGA processing

    Science.gov (United States)

    Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

    2000-03-01

    Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

  10. The Codice digitale degli archivi veronesi. A research instrument

    Directory of Open Access Journals (Sweden)

    Andrea Brugnoli

    2014-04-01

    Full Text Available The Codice digitale degli archivi veronesi (Verona’s archives digital code ‹http://cdavr.dtesis.univr.it› makes available online the digital reproductions of the documents produced by corporate bodies and family of Verona between the eighth and twelfth century. The framework of the site reflects the current organisation of the archives. A brief description of the circumstances around the creation of each archive, the corporate body or individual responsible for it and its structure is provided. Each archival unit is identified by its key elements: chronological date, name and qualification of the notary, original/copy, main editions.

  11. Digitale Transformation, aber wie? - Von der Spielwiese zur Umsetzungsplanung

    Science.gov (United States)

    Kaiser, Thomas

    Es besteht wohl kaum Anlass zur Annahme, dass die seit Jahrzehnten etablierten Markt- und Technologiestrukturen der Energiewirtschaft sich nicht in einem radikalen Ablöseprozess mit Gewinnern und Verlierern befinden. Aber Vorsicht - vordergründig bereits verloren erscheinende Geschäftsmodelle erfahren im Zuge der Digitalisierung einerseits noch intensiveren Wettbewerbsdruck, können aber andererseits von diesem "technologischen Jungbrunnen" profitieren, um verlorenes Terrain zurückzugewinnen. Im folgenden Kapitel wird ein Managementzyklus aufgezeigt, der in Anlehnung an die bereits erfolgreiche Implementierung digitaler R/Evolutionen anderer Branchen aufzeigt, wie die Geschäftsleitung systematisch kostenbewusst und zielorientiert die Digitalisierung umsetzen kann.

  12. UNE 71362: calidad de los materiales educativos digitales

    OpenAIRE

    Fernández-Pampillón Cesteros, Ana María

    2017-01-01

    La norma UNE 71362:2017 proporciona un modelo de base para definir y evaluar cuantitativa y cualitativamente la calidad de los materiales educativos digitales. En la elaboración de la norma han participado especialistas en enseñanza y aprendizaje, tecnologías, accesibilidad y gestión educativa pertenecientes a los tres sectores implicados en la creación y uso de estos materiales: académico, empresarial y de las administraciones públicas. El propósito de la norma es responder al reto y a la ne...

  13. Demands on digital automation; Anforderungen an die Digitale Automation

    Energy Technology Data Exchange (ETDEWEB)

    Bieler, P.

    1995-12-31

    In chapter 12 of the anthology about building control the demands on digital automation are presented. The following aspects are discussed: variety of the companies` philosophies, demands of the customer/investor, demands of the use of buildings/rooms, the user, point of view of manufacturer of technical plants. (BWI) [Deutsch] Kapitel 12 des Sammelbandes ueber Building Control stellt die Anforderungen an die Digitale Automation vor. In diesem Zusammenhang wird auf folgende Themenbereiche eingegangen: Spektrum der Firmenphilosophien, Forderungen der Auftraggeber/Investoren, der Gebaeude-/Raumnutzung, der Betreiber sowie Sicht der Ersteller betriebstechnischer Anlagen. (BWI)

  14. Digitale modeller af danske arkitekturværker

    DEFF Research Database (Denmark)

    Villaume, René; Rude Ørstrup, Finn

    2001-01-01

    Digitale modeller af dansk arkitektur åbner op for helt nye muligheder og faciliteter, fordi den enkelte bruger får et nyt redskab til at tilegne sig viden om dansk arkitektur med modeller, der kan anvendes til at iagtage og analysere både opførte og skitserede danske bygningsværker. Internettet ...... arbejder fra analyseopgaver i studiet. Der er store ressourcer og muligheder for opbygning af en samling, der systematisk kan udbygges og udvikles år for år. En helt ny dimension når man ønsker at indhente viden om dansk arkitektur og arkitekter....

  15. Generación de objetos de aprendizaje empleando un enfoque asistido

    OpenAIRE

    Menéndez Domínguez, Victor Hugo; Castellanos Bolaños, María Enriqueta; Zapata González, Alfredo; Prieto Méndez, Manuel Emilio:

    2011-01-01

    El etiquetado de un Objeto de Aprendizaje generalmente es una actividad extenuante y propensa a errores, lo cual afecta directamente la reutilización e interoperabilidad del recurso. En este trabajo se describe un modelo que genera Objetos de Aprendizaje a partir de recursos digitales existentes. El modelo emplea la similitud entre objetos, así como reglas inferidas del conocimiento existente, para proponer metadatos y de esta manera facilitar la descripción del recurso. El modelo ha sido imp...

  16. FPGA based Smart Wireless MIMO Control System

    International Nuclear Information System (INIS)

    Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-01-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

  17. FPGA controlled artificial vascular system

    Directory of Open Access Journals (Sweden)

    Laqua D.

    2015-09-01

    Full Text Available Monitoring the oxygen saturation of an unborn child is an invasive procedure, so far. Transabdominal fetal pulse oximetry is a promising method under research, used to estimate the oxygen saturation of a fetus noninvasively. Due to the nature of the method, the fetal information needs to be extracted from a mixed signal. To properly evaluate signal processing algorithms, a phantom modeling fetal and maternal blood circuits and tissue layers is necessary. This paper presents an improved hardware concept for an artificial vascular system, utilizing an FPGA based CompactRIO System from National Instruments. The experimental model to simulate the maternal and fetal blood pressure curve consists of two identical hydraulic circuits. Each of these circuits consists of a pre-pressure system and an artificial vascular system. Pulse curves are generated by proportional valves, separating these two systems. The dilation of the fetal and maternal artificial vessels in tissue substitutes is measured by transmissive and reflective photoplethysmography. The measurement results from the pressure sensors and the transmissive optical sensors are visualized to show the functionality of the pulse generating systems. The trigger frequency for the maternal valve was set to 1 per second, the fetal valve was actuated at 0.7 per second for validation. The reflective curve, capturing pulsations of the fetal and maternal circuit, was obtained with a high power LED (905 nm as light source. The results show that the system generates pulse curves, similar to its physiological equivalent. Further, the acquired reflective optical signal is modulated by the alternating diameter of the tubes of both circuits, allowing for tests of signal processing algorithms.

  18. FPGA Implementation of the stepwise shutdown system

    Energy Technology Data Exchange (ETDEWEB)

    Lotjonen, L.

    2012-07-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  19. FPGA Implementation of the stepwise shutdown system

    International Nuclear Information System (INIS)

    Lotjonen, L.

    2012-01-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and standards can be used to some extent but the hardware aspects bring new challenges that cannot be tackled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation process from the requirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  20. Burst-Mode Asynchronous Controllers on FPGA

    Directory of Open Access Journals (Sweden)

    Duarte L. Oliveira

    2008-01-01

    Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

  1. FPGA Design and Verification Procedure for Nuclear Power Plant MMIS

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Yoo, Kawnwoo; Ryoo, Kwangki [Hanbat National Univ., Daejeon (Korea, Republic of)

    2013-05-15

    In this paper, it is shown that it is possible to ensure reliability by performing the steps of the verification based on the FPGA development methodology, to ensure the safety of application to the NPP MMIS of the FPGA run along the step. Currently, the PLC (Programmable Logic Controller) which is being developed is composed of the FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit). As the importance of the FPGA in the NPP (Nuclear Power Plant) MMIS (Man-Machine Interface System) has been increasing than before, the research on the verification of the FPGA has being more and more concentrated recently.

  2. OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

  3. Qualification of FPGA-Based Safety-Related PRM System

    International Nuclear Information System (INIS)

    Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

    2011-01-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

  4. Digitalisierung und Energie 4.0 - Wie schaffen wir die digitale Energiewende?

    Science.gov (United States)

    Irlbeck, Maximilian

    Die digitale Energiewende verändert nachhaltig die Systeme der "alten" Energiewelt. Ein Zusammenwachsen verschiedener Domänen im Energiesystem, die durch digitale Technologie möglich wird, birgt enorme Herausforderungen, ist aber notwendig, um die Energiewende und ihre Ziele zu meistern. Dieser Beitrag beschreibt die Wirkung der Digitalisierung auf das Energiesystem, listet Charakteristika der digitalen Energiewende auf und schildert für verschiedene Domänen mögliche Zielvorstellungen, die durch digitale Technologie umsetzbar sind. Am Ende erläutert der Beitrag Handlungsschritte, die auf dem Weg zu einem erneuerbaren Energiesystem gegangen werden sollten und zeigt Probleme und Risiken einer Fehlentwicklung auf.

  5. FPGA Realization of Memory 10 Viterbi Decoder

    DEFF Research Database (Denmark)

    Paaske, Erik; Bach, Thomas Bo; Andersen, Jakob Dahl

    1997-01-01

    sequence mode when feedback from the Reed-Solomon decoder is available. The Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's. The overall operating speed is 30 kbit/s, and since up to three iterations are performed for each frame and only one decoder is used, the operating speed...

  6. Prototyping Advanced Control Systems on FPGA

    Directory of Open Access Journals (Sweden)

    Simard Stéphane

    2009-01-01

    Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

  7. Commercial FPGA based multipurpose controller: implementation perspective

    International Nuclear Information System (INIS)

    Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

    2012-01-01

    This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

  8. ¿Son realmente tan buenos los nativos digitales?: relación entre las habilidades digitales y la lectura digital

    Directory of Open Access Journals (Sweden)

    Inmaculada Fajardo

    2016-01-01

    Full Text Available La competencia en la lectura digital consiste en la comprensión, uso, reflexión y disfrute de los textos escritos con el fin de conseguir nuestros objetivos, desarrollar nuestro conocimiento y potencial, y participar en nuestra sociedad. En la actualidad se considera que los "nativos digitales", aquellos estudiantes que desde la infancia han crecido rodeados de las tecnologías de la información, poseen las habilidades digitales básicas (usar el ratón, el navegador, ... necesarias para desarrollar la competencia en la lectura digital. En el presente estudio ponemos a prueba esta visión, a partir de un estudio en el que estudiantes de 5º de Primaria y 3º de Secundaria realizaron una serie de tareas de lectura digital. Los estudiantes completaron asimismo varias pruebas objetivas para medir sus habilidades digitales básicas, así como su nivel de competencia lectora en papel. Los resultados mostraron que los estudiantes no sólo presentaban dificultades en numerosas habilidades digitales básicas, si no que éstas estaban relacionadas directamente con el éxito en tareas de lectura digital. Para concluir, se reflexiona sobre la necesidad de considerar la instrucción en las habilidades digitales básicas como parte de los esfuerzos actuales por mejorar la competencia en la lectura digital.

  9. Asesinatos empleando relajantes musculares, opioides y otras drogas anestésicas

    OpenAIRE

    Martínez Hurtado, Eugenio; Gómez García, Ana María

    2012-01-01

    Los anestésicos, los opiáceos y los relajantes musculares pueden deprimir la respiración y otros procesos vitales hasta el extremo de producir la muerte si no se mantiene la ventilación. De modo que estos fármacos se han empleado para la eutanasia, el suicidio y las ejecuciones. Los criminales también han reparado en las posibilidades letales de los anestésicos, y durante los años recientes se han cometido homicidios empleando hipnóticos, anestésicos generales inhalados, opiáceos y relajantes...

  10. Deporte Salud y Vida para oyentes de radio Familia 96.9 empleando pausa activa

    OpenAIRE

    Martínez Sarmiento, Marcia Fabiola

    2011-01-01

    Deporte Salud y Vida para oyentes de radio Familia 96.9 empleando pausa activa, un programa de radio que promueve a la práctica de actividad física, que permita contrarrestar las grandes escalas de sedentarismo en nuestra ciudad, gracias al apoyo de este medio de comunicación se implementó la Pausa activa para oyentes de Radio Familia, especialmente amas de casa que fluctúan desde los 20 hasta 75 años. El proyecto tiene también el objetivo de la ejercitación mediante la Pausa Activa dentro...

  11. Een Digitale bibliotheek van dateringen: de internationale doorwerking van een Nederlands initiatief

    NARCIS (Netherlands)

    Jansma, E.; Lanen, R.J. van

    De Rijksdienst voor het Cultureel Erfgoed en Data Archiving and Networked Services (DANS) hebben met NWO-gelden een internationale digitale bibliotheek ontwikkeld voor ouderdomsbepalingen met behulp van houtonderzoek. Alle in Nederland ontwikkelde jaarringarchieven over het cultureel erfgoed

  12. Digitale inhoud en consumentenkooprecht : Een groot bezwaar en een kleine wijziging

    NARCIS (Netherlands)

    Neppelenbroek, E.D.C.

    2014-01-01

    Met de voorgestelde wijze van implementatie van de Europese Richtlijn consumentenrechten worden de bepalingen over consumentenkoop grotendeels vant toepassing op digitale inhoud die niet op dragers wordt geleverd. Hiermee lijkt het consumentenkooprecht van toepassing te worden op alle overeengekomen

  13. Het verbonden winkelgebied : hoe collectieve digitale marketing kan bijdragen aan een aantrekkelijke binnenstad

    NARCIS (Netherlands)

    Risselada, A.H.; Hagen, D.; Weltevreden, J.W.J.; Atzema, O.A.L.C.; Spierings, B.; Janssen, J.W.H.; Ghaus, F.

    2018-01-01

    Met het handboek ‘Het verbonden winkelgebied’ willen we inzichtelijk maken hoe collectieve digitale marketing kan bijdragen aan een aantrekkelijke binnenstad. Het handboek bevat naast onderzoeksresultaten ook een toolkit met een plan van aanpak voor collectieve marketing. Collectieven,

  14. Happing: Nativos digitales al servicio de la imagen corporativa de Coca-Cola

    Directory of Open Access Journals (Sweden)

    Carmen Llorente Barroso

    2012-04-01

    Full Text Available Happing, la comunidad de la gente que se atreve a ser feliz, es la nueva propuesta de la compañía Coca-Cola para su promoción web en España; su éxito entre los nativos digitales pone de manifiesto el acierto de esta gran marca internacional, que ha sabido aprovechar la creatividad de los nativos digitales que participan en la comunidad, para dar brillo a una Imagen Corporativa Intencional de sobra solvente. Los nativos digitales que contribuyen a la creación del mágico mundo Coca-Cola, participan gustosos de la oportunidad expresiva que les brida la compañía, fascinados por la filosofía de vida que siempre ha sido bandera de la Imagen de marca de Coca-Cola, ahora alimentada y, en parte, creada por esos nativos digitales.

  15. Un approccio multidisciplinare per l’archeologia digitale

    Directory of Open Access Journals (Sweden)

    Rodolfo Maria Strollo

    2017-12-01

    Full Text Available Obiettivo del contributo è quello di indagare le potenzialità offerte da una metodologia multidisciplinare volta alla creazione di un database digitale facilmente interrogabile, sempre disponibile e scientificamente valido da impiegare per le diverse finalità legate al patrimonio culturale immobile (ricerca scientifica, interventi di manutenzione e restauro, valorizzazione culturale, promozione turistica. La banca dati è composta da modelli infografici elaborati con riferimento a rilievi tridimensionali affidabili dal punto di vista metrico e cromatico e rappresentativi di una realtà virtuale ‘aumentata’ delle informazioni storiche, iconografico-documentali e archivistiche riferite al bene. Caso studio su cui è stato sperimentato tale approccio metodologico è l’area archeologica di Tuscolo, sui Colli Albani a sud di Roma.

  16. SIMULACIÓN DE CONTROLADORES DIGITALES SIMULATION OF DIGITAL CONTROLLERS

    Directory of Open Access Journals (Sweden)

    Carlos Álvarez G

    2009-12-01

    Full Text Available El presente trabajo tiene como objetivo la implementación de controladores digitales en un entorno de simulación controlado, para esto se desarrolla una plataforma de hardware que permite ejecutar los programas en lenguaje C generados en una estación de trabajo. Estos programas corresponden al controlador y a la planta que son generados por un software que genera dichos programas a partir de sus parámetros de modelación aplicando teoría de control digital sobre procesos reales.This paper describes an implementation of digital controllers in a simulation environment for including a hardware platform for running programs generated on a workstation. These programs for both the controller and the plant are generated by software based on parameters using digital control theory for real processes.

  17. Mesa redonda sobre nuevos modelos organizativos en la gestión de proyectos digitales

    OpenAIRE

    Taladriz Mas, Margarita; Magriñá Contreras, Marta; Martín Marichal, Carmen; Cabo Rigol, Mercé; X Workshop Rebiun sobre proyectos digitales. Valencia, 7-8 Octubre de 2010

    2010-01-01

    Mesa redonda dentro del X Workshop Rebiun sobre proyectos digitales, celebrado en Valencia, 7-8 Ocubre de 2010, sobre: Nuevos modelos organizativos en la gestión de proyectos digitales. Moderador: José Manuel Barrueco (UV). Intervienen: Margarita Taladriz Mas(UC3M), Marta Magriñá Contreras (UNIRIOJA), Carmen Martín Marichal (ULPGC) y Mercé Cabo Rigol (UPF).

  18. Jóvenes, migraciones digitales y brecha tecnológica

    Directory of Open Access Journals (Sweden)

    Delia María Crovi Druetta

    2010-01-01

    Full Text Available Este trabajo tiene como propósito reflexionar en torno a los procesos y condiciones en que actualmente se realiza la articulación juventud-digitalización. Para ello, y a partir de una caracterización de los jóvenes como nativos digitales, se definen estos dos factores identificando la existencia de brechas (digitales y cognitivas que configuran una nueva causa de exclusión para el sector juvenil.

  19. La seguridad en las competencias digitales de los millennials

    Directory of Open Access Journals (Sweden)

    Berenice Castillejos López

    2016-10-01

    Full Text Available Basados en un estudio mixto, en este documento valoramos la percepción del universitario sobre el tema de la seguridad en la Red, considerada una de las áreas de las competencias digitales. Apoyados en los descriptores del proyecto Ikanos del Instituto Vasco de Cualificaciones y Formación Profesional (2014, consideramos cuatro temas: la protección de los dispositivos, los datos personales, la salud y el uso sostenible de los recursos tecnológicos (INTEF, 2014. En la recolección de los datos, empleamos un cuestionario en línea y un guion de entrevista individual semiestructurado. Los resultados señalan que los millennials realizan prácticas básicas de seguridad, tales como el uso de antivirus, el manejo de contraseñas, ajustes en la configuración de las herramientas web, entre otros. Respecto a la identidad digital y la salud, es necesario promover el empleo adecuado de los datos personales, así como fomentar hábitos mediáticos saludables. En la protección del entorno natural identificamos la necesidad de crear conciencia sobre la adquisición de equipos, el manejo de los energéticos, el reciclaje y los desechos tecnológicos. Por último, este trabajo busca contribuir a la discusión sobre la seguridad y el consumo mediático dentro del marco de las competencias digitales.   

  20. An FPGA-based torus communication network

    Energy Technology Data Exchange (ETDEWEB)

    Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

    2011-02-15

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  1. Moessbauer spectrometric data acquisition based on FPGA

    International Nuclear Information System (INIS)

    Zhang Yuan; Li Shimin; Chen Nan; Zhu Jingbo; Xia Yuanfu

    2008-01-01

    FPGA(Field Programmable Gate Array) is a programmable device with strong logical function and timing control ability. It is extremely potent in acquiring and processing timing signals. By replacing the traditional used SCM (Single-Chip Microcomputer) with FPGA, counting speed of Moessbauer spectrometric data acquisition can be improved markedly with significantly decreased size of the spectrometer. The counter, RAM and RS-232 communication of the module are developed on Altera Cyclone series chip EP1C6T144C8 with Quartus II. EP1C6T144C8 has 5980 logical units accompanied by 92160 bits of memory space. It is so powerful that all needs in data acquisition of the Moessbauer spectrometer can be perfectly satisfied while allowing modifications in functions and parameters. (authors)

  2. An Improved Rotary Interpolation Based on FPGA

    Directory of Open Access Journals (Sweden)

    Mingyu Gao

    2014-08-01

    Full Text Available This paper presents an improved rotary interpolation algorithm, which consists of a standard curve interpolation module and a rotary process module. Compared to the conventional rotary interpolation algorithms, the proposed rotary interpolation algorithm is simpler and more efficient. The proposed algorithm was realized on a FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe, which uses rotary ellipse and rotary parabolic as an example. According to the theoretical analysis and practical process validation, the algorithm has the following advantages: firstly, less arithmetic items is conducive for interpolation operation; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

  3. An FPGA-based torus communication network

    International Nuclear Information System (INIS)

    Pivanti, Marcello; Schifano, Sebastiano Fabio; Simma, Hubert

    2011-02-01

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  4. An FPGA-Based Electronic Cochlea

    Directory of Open Access Journals (Sweden)

    M. P. Leong

    2003-06-01

    Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

  5. Guide to FPGA Implementation of Arithmetic Functions

    CERN Document Server

    Deschamps, Jean-Pierre; Cantó, Enrique

    2012-01-01

    This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components.  The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption.  This is not a book on algorithms.  It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others.  Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

  6. Adaptive Hardware Cryptography Engine Based on FPGA

    International Nuclear Information System (INIS)

    Afify, M.A.A.

    2011-01-01

    In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

  7. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  8. FPGA Flash Memory High Speed Data Acquisition

    Science.gov (United States)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  9. Signal compression in radar using FPGA

    OpenAIRE

    Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

    2010-01-01

    We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

  10. An FPGA-based reconfigurable DDC algorithm

    Science.gov (United States)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  11. FPGA Implementation of Computer Vision Algorithm

    OpenAIRE

    Zhou, Zhonghua

    2014-01-01

    Computer vision algorithms, which play an significant role in vision processing, is widely applied in many aspects such as geology survey, traffic management and medical care, etc.. Most of the situations require the process to be real-timed, in other words, as fast as possible. Field Programmable Gate Arrays (FPGAs) have a advantage of parallelism fabric in programming, comparing to the serial communications of CPUs, which makes FPGA a perfect platform for implementing vision algorithms. The...

  12. FPGA remote update for nuclear environments

    Energy Technology Data Exchange (ETDEWEB)

    Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

    2015-07-01

    The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

  13. FPGA communications based on Gigabit Ethernet

    International Nuclear Information System (INIS)

    Doolittle, L.R.; Serrano, C.

    2012-01-01

    The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

  14. FPGA Implementation of Heart Rate Monitoring System.

    Science.gov (United States)

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  15. Medansvar og fagligt engagement gennem digitale skriveøvelser

    Directory of Open Access Journals (Sweden)

    Henriette Roued-Cunliffe

    2016-10-01

    Full Text Available Vi rapporterer om vores forsøg på at promovere medansvar og fagligt engagement blandt vores studerende gennem digitale skriveøvelser. Disse kombinerer skriftlighed i læring (som en refleksionsfremmende og forpligtende øvelse med de kollaborative muligheder, der ligger i at benytte digitale platforme. Dybde i læring og reflekteret/reflekterende feedback er aspekter, som bliver centrale, når fagligt indhold på skrift indlejres i en digital læringskontekst. I artiklen tages udgangspunkt i TEACHs universitetspædagogiske initiativer inden for skriftlig læring og erfaringerne fra universitetspædagogikum. Forfatterne afprøvede nogle af disse idéer i form af kollaborative skriveøvelser på et bachelorkursus på Det Informationsvidenskabelige Akademi (Københavns Universitet. Forfatternes praktiske fremgangsmåde dokumenteres, og der gøres rede for de erfaringer, de har gjort sig. I den forbindelse diskuteres aspekter som tekstnære vs. åbne spørgsmål, de studerendes motivation for skrivning, deres vurdering af egen arbejdsindsats, en vurdering af de studerendes tidsforbrug og de studerendes holdning over for den foretrukne feedback - underviserens eller peer-to-peer. Der afsluttes med anbefalinger, som baserer sig på dette forsøg. This article reports on our attempts to promote accountability and commitment among our students through digital writing exercises. These combine writing as a reflective and required learning process with the collaborative possibilities that exist in using a digital platform. When using this kind of platform the depth of understanding and the quality of the feedback are important aspects of the learning experience. The study is based on the university’s TEACH programme, which focuses on writing in higher education, and it also draws on our experience from the university’s pedagogy course. Some of the ideas were tested on students from the Bachelor programme at the Royal School of Library and

  16. Flujo de carga con armónicos empleando la matriz impedancia de barras

    Directory of Open Access Journals (Sweden)

    José A González Quintero

    2011-03-01

    Full Text Available Se describe un flujo de armónicos empleando la matriz impedancia de barras. El algoritmo propuesto permite hallar losvoltajes de cada nodo del circuito sin tener que realizar la solución simultánea de todas las ecuaciones no linealescorrespondientes a cada nodo, ni siquiera la solución simultánea de las ecuaciones correspondientes a una redreducida de nodos no lineales solamente.  This work describes a harmonic load flow using the bar impedance matrix. The proposed algorithm permit to findevery node voltage of the circuit without to realize the simultaneous solution of all the non-linear equationscorresponding to each node, not even the simultaneous solution of the equations corresponding to a reducednetwork of only non-linear nodes.

  17. Tras las competencias de los nativos digitales: avances de una metasíntesis

    Directory of Open Access Journals (Sweden)

    David Arturo Acosta\\u2013Silva

    2017-01-01

    Full Text Available En el presente documento reporto los avances de una metasíntesis realizada sobre investigaciones que en los últimos 15 años han buscado evaluar las competencias digitales de los jóvenes; ello con el fin de establecer si sus resultados soportan las posturas que afirman que los jóvenes y las jóvenes tienen unas competencias digitales generalizadas y de alto nivel. Para tal fin realicé una selección en la literatura de reportes de investigaciones cuyos objetivos se dirigieran al análisis de las competencias digitales, posteriores al planteamiento original de los nativos digitales y que presentaran resultados empíricos. De los artículos obtenidos analicé sus concepciones, métodos y resultados. El producto de este proceso indica que la mayoría de tales estudios concluyen que las aseveraciones sobre las superiores competencias digitales de los sujetos jóvenes no están soportadas empíricamente.

  18. FPGA based Control of a Production Cell System

    NARCIS (Netherlands)

    Groothuis, M.A.; van Zuijlen, Jasper J.P.; Broenink, Johannes F.

    Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control

  19. Automatic generation of application specific FPGA multicore accelerators

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

    2014-01-01

    High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

  20. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    -the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

  1. Hyperchaotic Chameleon: Fractional Order FPGA Implementation

    Directory of Open Access Journals (Sweden)

    Karthikeyan Rajagopal

    2017-01-01

    Full Text Available There are many recent investigations on chaotic hidden attractors although hyperchaotic hidden attractor systems and their relationships have been less investigated. In this paper, we introduce a hyperchaotic system which can change between hidden attractor and self-excited attractor depending on the values of parameters. Dynamic properties of these systems are investigated. Fractional order models of these systems are derived and their bifurcation with fractional orders is discussed. Field programmable gate array (FPGA implementations of the systems with their power and resource utilization are presented.

  2. Superconducting cavity driving with FPGA controller

    International Nuclear Information System (INIS)

    Czarski, Tomasz; Koprek, Waldemar; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Simrock, Stefan; Brandt, Alexander; Chase, Brian; Carcagno, Ruben; Cancelo, Gustavo; Koeth, Timothy W.

    2006-01-01

    A digital control of superconducting cavities for a linear accelerator is presented. FPGA-based controller, supported by Matlab system, was applied. Electrical model of a resonator was used for design of a control system. Calibration of the signal path is considered. Identification of cavity parameters has been carried out for adaptive control algorithm. Feed-forward and feedback modes were applied in operating the cavities. Required performance has been achieved; i.e. driving on resonance during filling and field stabilization during flattop time, while keeping reasonable level of the power consumption. Representative results of the experiments are presented for different levels of the cavity field gradient

  3. Spacewire Routers Implemented with FPGA Technology

    Science.gov (United States)

    Habinc, Sandi; Isomaki, Marko

    2011-08-01

    Routers are an integral part of SpaceWire networks. Aeroflex Gaisler has developed a highly configurable SpaceWire router VHDL IP core to meet the needs for technology independent router designs. The main design goals have been configurability, technology independence, support of the standard and expandability. The IP core being technologically independent allows it to be used in both ASIC and FPGA technology. The latter is now being used to produce versatile standard products that can reach the market faster than for example an ASIC based product.

  4. Signal compression in radar using FPGA

    OpenAIRE

    Enrique Escamilla Hemández; Víctor Kravchenko; Volodymyr Ponomaryov; Gonzalo Duchen Sánchez; David Hernández Sánchez

    2010-01-01

    El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array). El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR). El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde n...

  5. Medios digitales en Ecuador, cuántos son y qué hacen

    Directory of Open Access Journals (Sweden)

    Jose Rivera Costales

    2013-06-01

    Full Text Available El mapa de medios digitales es un estudio realizado por CIESPAL para conocer los medios que publican, investigan y difunden información noticiosa en Internet. Los formatos digitales de radio, prensa y televisión así como los nativos en Internet fueron parte de este estudio que integra 254 medios ecuatorianos. En el estudio se logró determinar: distribución geográfica, origen del medio, inmediatez, tipo de información, formatos, niveles de actualización, secciones, hipertextualidad, multimedialidad, interactividad, redes sociales y herramientas multimedia, para comprender los procesos y lógicas de los medios de comunicación digitales.

  6. Exploración de nuevos soportes digitales. Tadvertising como oportunidad para la creatividad publicitaria.

    Directory of Open Access Journals (Sweden)

    Patricia Comesaña Comesaña

    2015-02-01

    Full Text Available Las tabletas digitales han revolucionado el mercado de los dispositivos móviles y han cambiado la forma en la que el usuario interactúa con la publicidad. Se han definido nuevas estrategias, nuevas tipologías de apps, nuevos formatos interactivos y no interactivos; y se han encontrado grandes posibilidades para los anunciantes. Este libro pretende mostrar algunas de las estrategias publicitarias más comunes entre el anunciante, así casos de éxito en el mundo de las tabletas digitales que los ejemplifiquen. El storytelling, el advergaming, el advertainment, la publicidad para revistas,la prensa diaria o las aplicaciones de anunciantes más descargadas configuran el Tabvertising, la denominada por el Interactive Advertising Bureau como publicidad creada para tabletas digitales.

  7. Modelo de Producción de Contenidos Digitales para la Educación Online

    Directory of Open Access Journals (Sweden)

    Evelio Granizo

    2016-11-01

    Full Text Available A partir de un análisis del estado actual de la industria de contenidos digitales y del entorno normativo y legal del Ecuador, referido principalmente a temas de seguridad en Internet y derechos de propiedad intelectual; y a través de una investigación de mercado, para identificar las necesidades de los usuarios y aprovechar las oportunidades y retos que presenta la educación en línea; se recomienda un modelo de producción de contenidos digitales para la educación en línea, basado en un esquema colaborativo y de ecosistema inteligente, y en un conjunto de políticas públicas para el fomento de la industria de contenidos digitales en el Ecuador.

  8. Aspectos tributarios de las plataformas digitales en Colombia: actualidad y retos

    OpenAIRE

    Cabrera Cabrera, Omar Sebastián

    2017-01-01

    Los agigantados avances en las tecnologías de la comunicación y la información han labrado el terreno para el arribo de la economía digital. Esta situación lleva a señalar que es una realidad ineludible que la mayoría de las operaciones de negocios se canalizan hoy a través del comercio electrónico, donde las últimas décadas atestiguan el auge y revolución de todas las formas de las plataformas digitales. No obstante, estos nuevos modelos digitales de negocios conllevan importantes intrincaci...

  9. Exploración de nuevos soportes digitales. Tadvertising como oportunidad para la creatividad publicitaria.

    OpenAIRE

    Patricia Comesaña Comesaña

    2015-01-01

    Las tabletas digitales han revolucionado el mercado de los dispositivos móviles y han cambiado la forma en la que el usuario interactúa con la publicidad. Se han definido nuevas estrategias, nuevas tipologías de apps, nuevos formatos interactivos y no interactivos; y se han encontrado grandes posibilidades para los anunciantes. Este libro pretende mostrar algunas de las estrategias publicitarias más comunes entre el anunciante, así casos de éxito en el mundo de las tabletas digitales que los ...

  10. Kommunen er død - længe leve den digitale disruption

    DEFF Research Database (Denmark)

    Andersen, Kim Normann

    2017-01-01

    "New Public Management is Dead. Long Live the Digital Era." Sådan proklamerede Patrick Donleavy digitaliseringens muligheder i en banebrydende artikel fra 2005. Med en omskrivning af dette citat til "Kommunen er død, længe leve den digitale disruption", er ballet åbnet for denne artikel......."New Public Management is Dead. Long Live the Digital Era." Sådan proklamerede Patrick Donleavy digitaliseringens muligheder i en banebrydende artikel fra 2005. Med en omskrivning af dette citat til "Kommunen er død, længe leve den digitale disruption", er ballet åbnet for denne artikel....

  11. Desarrollo de competencias digitales docentes en la educación básica

    Directory of Open Access Journals (Sweden)

    Víctor Gerardo Morales Arce

    2013-04-01

    Full Text Available Este documento tiene como objetivo presentar un breve análisis de cómo se está favoreciendo la formación de competencias digitales en docentes de educación básica con el programa Habilidades Digitales para Todos (HDT; se destaca la importancia y trascendencia de la formación digital para hacer frente a las expectativas y retos que plantea el nuevo paradigma educativo, al introducir las nuevas tecnologías de la información y la comunicación (TIC a las prácticas educativas propias del siglo XXI.

  12. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  13. Superconducting cavity driving with FPGA controller

    Energy Technology Data Exchange (ETDEWEB)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland); Simrock, S.; Brand, A. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Chase, B.; Carcagno, R.; Cancelo, G. [Fermi National Accelerator Lab., Batavia, IL (United States); Koeth, T.W. [Rutgers - the State Univ. of New Jersey, NJ (United States)

    2006-07-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

  14. Control de acceso usando FPGA y RFID

    Directory of Open Access Journals (Sweden)

    Dora Luz Almanza Ojeda

    2012-10-01

    Full Text Available Este trabajo presenta el diseño e implementación de un sistema de control de acceso mediante Identificación por Radiofrecuencia (RFID, Radio Frequency Identification controlado por una Matriz de compuertas programables (FPGA, Field Programmable Gate Array. El sistema está constituido por un par de dispositivos de adquisición de radiofrecuencia, una FPGA, un juego de etiquetas y tarjetas pasivas de identificación. Mediante una interfaz gráfica de usuario es posible controlar todo movimiento dentro de una zona determinada, desde los accesos hasta la disponibilidad de equipo; utilizando los dispositivos de adquisición de radiofrecuencia se puede acceder a la información de los usuarios autorizados, así como al control del equipo. Con este sistema es posible monitorear, administrar y reportar todo acceso de personal, movimiento de equipo o plagio de manera eficiente y evitando un gran número de errores humanos.  

  15. An FPGA-Based People Detection System

    Directory of Open Access Journals (Sweden)

    James J. Clark

    2005-05-01

    Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

  16. High performance parallel backprojection on FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Pfanner, Florian; Knaup, Michael; Kachelriess, Marc [Erlangen-Nuernberg Univ., Erlangen (Germany). Inst. of Medical Physics (IMP)

    2011-07-01

    Reconstruction of tomographic images, i.e., images from a Computed Tomography scanner, is a very time consuming issue. The most calculation power is needed for the backprojection step. A closer inspection shows that the algorithm for backprojection is easy to parallelize. FPGAs are able to execute many operations in the same time, so a highly parallel algorithm is a requirement for a powerful acceleration. For data flow rate maximization, we realized the backprojection in a pipelined structure with data throughput of one clock cycle. Due the hardware limitations of the FPGA, it is not possible to reconstruct the image as a whole. So it is necessary to split up the image and reconstruct these parts separately. Despite that, a reconstruction of 512 projections into a 5122 image is calculated within 13 ms on a Virtex 5 FPGA. To save hardware resources we use fixed point arithmetic with an accuracy of 23 bit for calculation. A comparison of the result image and an image, calculated with floating point arithmetic on CPU, shows that there are no differences between these images. (orig.)

  17. Signal compression in radar using FPGA

    Directory of Open Access Journals (Sweden)

    Enrique Escamilla Hemández

    2010-01-01

    Full Text Available El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array. El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR. El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde nos centramos en obtener una mejor atenuación para los valores de lóbulos laterales. La arquitectura propuesta explota los recursos de computación paralela de los dispositivos FPGA para alcanzar una mejor velocidad de cómputo. Las investigaciones experimentales han demostrado que los mejores resultados para el funcionamiento de la compresión del pulso se han obtenido usando las funciones atómicas, mejorando el funcionamiento del sistema del radar en presencia de ruido, y consiguiendo una pequeña degradación en la resolución de rango. La puesta en práctica del tratamiento de señales en el sistema de radar en tiempo real se discute y se justifica la eficiencia de la arquitectura de hardware propuesta.

  18. Superconducting cavity driving with FPGA controller

    International Nuclear Information System (INIS)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S.; Simrock, S.; Brand, A.; Chase, B.; Carcagno, R.; Cancelo, G.; Koeth, T.W.

    2006-01-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

  19. Automated Metabolic P System Placement in FPGA

    Directory of Open Access Journals (Sweden)

    Kulakovskis Darius

    2016-07-01

    Full Text Available An original Very High Speed Integrated Circuit Hardware Description Language (VHDL code generation tool that can be used to automate Metabolic P (MP system implementation in hardware such as Field Programmable Gate Arrays (FPGA is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT, and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP, slice, and 4-input LUT usage.

  20. FPGA-Based Embedded Motion Estimation Sensor

    Directory of Open Access Journals (Sweden)

    Zhaoyi Wei

    2008-01-01

    Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

  1. An improved real time superresolution FPGA system

    Science.gov (United States)

    Lakshmi Narasimha, Pramod; Mudigoudar, Basavaraj; Yue, Zhanfeng; Topiwala, Pankaj

    2009-05-01

    In numerous computer vision applications, enhancing the quality and resolution of captured video can be critical. Acquired video is often grainy and low quality due to motion, transmission bottlenecks, etc. Postprocessing can enhance it. Superresolution greatly decreases camera jitter to deliver a smooth, stabilized, high quality video. In this paper, we extend previous work on a real-time superresolution application implemented in ASIC/FPGA hardware. A gradient based technique is used to register the frames at the sub-pixel level. Once we get the high resolution grid, we use an improved regularization technique in which the image is iteratively modified by applying back-projection to get a sharp and undistorted image. The algorithm was first tested in software and migrated to hardware, to achieve 320x240 -> 1280x960, about 30 fps, a stunning superresolution by 16X in total pixels. Various input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as in FPGA hardware, which gives us a fine balance between the number of bits and performance. The proposed system is robust and highly efficient. We have shown the performance improvement of the hardware superresolution over the software version (C code).

  2. LIDAR e Fotogrammetria Digitale verso una nuova integrazione

    Directory of Open Access Journals (Sweden)

    Fulvio Rinaudo

    2012-04-01

    Full Text Available In tutte le applicazioni del rilevo metrico la tecnica LIDAR e la Fotogrammetria Digitale giocano ormai un ruoloquasi esclusivo. Gli efficienti servizi forniti dalle reti di stazioni permanenti e dalle piattaforme GNSS/IMU hannoconsentito una rapida diffusione e una affidabilità mai raggiunta per altre tecniche di rilievo in ambito territoriale,così come pure nelle applicazioni terrestri quali il rilievo architettonico o il monitoraggio di fenomeni naturali, ovesono stati sostituiti quasi integralmente gli approcci tradizionali del rilievo topografico terrestre.LIDAR and Digital Photogrammetry towards a new integration A new integration approach between digital photogrammetry and LiDAR is presented in this paper. Up to now LiDAR use some  photogrammetric  topics  to  manage  point  clouds  and digital photogrammetry extract useful information from LiDAR data to produce traditional and accurate orthophoto. Considering that in traditional photogrammetric plotting the surveyor define the 3D location of the break-lines and add points just in those parts of the object where smooth surfaces can be defined, the proposed solution foresees a continuous exchange of information between those techniques in order to automatically extract the break-lines of the surveyed object. The final results  is  the  complete  breack-lines  3D  description  and  the point clouds portions useful to define smooth surfaces.  At the end of the automatic procedure a complete 3D set of information is produced in order to build up the fine 3D model of the surveyed object.

  3. LIDAR e Fotogrammetria Digitale verso una nuova integrazione

    Directory of Open Access Journals (Sweden)

    Fulvio Rinaudo

    2012-04-01

    Full Text Available In tutte le applicazioni del rilevo metrico la tecnica LIDAR e la Fotogrammetria Digitale giocano ormai un ruoloquasi esclusivo. Gli efficienti servizi forniti dalle reti di stazioni permanenti e dalle piattaforme GNSS/IMU hannoconsentito una rapida diffusione e una affidabilità mai raggiunta per altre tecniche di rilievo in ambito territoriale,così come pure nelle applicazioni terrestri quali il rilievo architettonico o il monitoraggio di fenomeni naturali, ovesono stati sostituiti quasi integralmente gli approcci tradizionali del rilievo topografico terrestre. LIDAR and Digital Photogrammetry towards a new integration A new integration approach between digital photogrammetry and LiDAR is presented in this paper. Up to now LiDAR use some  photogrammetric  topics  to  manage  point  clouds  and digital photogrammetry extract useful information from LiDAR data to produce traditional and accurate orthophoto. Considering that in traditional photogrammetric plotting the surveyor define the 3D location of the break-lines and add points just in those parts of the object where smooth surfaces can be defined, the proposed solution foresees a continuous exchange of information between those techniques in order to automatically extract the break-lines of the surveyed object. The final results  is  the  complete  breack-lines  3D  description  and  the point clouds portions useful to define smooth surfaces.  At the end of the automatic procedure a complete 3D set of information is produced in order to build up the fine 3D model of the surveyed object.

  4. FPGA Design Methodologies Applicable to Nuclear Power Plants

    International Nuclear Information System (INIS)

    Kwong, Yongil; Jeong, Choongheui

    2013-01-01

    In order to solve the above problem, NPPs in some countries such as the US, Canada and Japan have already applied FPGA-based equipment which has advantages as follows: It is easier to verify the performance because it needs only HDL code to configure logic circuits without other software, compared to microprocessor-based equipment, It is much cheaper than ASIC in a small quantity, Its logic circuits are re configurable, It has enough resources like logic blocks and memory blocks to implement I and C functions, Multiple functions can be implemented in a FPGA chip, It is stronger with respect to carboy security than microprocessor-based equipment because its configuration cannot be changed by external access, It is simple to replace it with new one when it is obsolete, Its power consumption is lower. However, FPGA-based equipment does not have only the merits. There are some issues on its application to NPPs. First of all, the experiences in applying it to NPPs are much less than to other industries, and international standards or guidelines are also very few. And there is the small number of FPGA platforms for I and C systems. Finally, the specific guidelines on FPGA design are required because the design has both hardware and software characteristics. In order to handle the above issues, KINS(Korea Institute of Nuclear Safety) built a test platform last year and have developed regulatory guidelines for FPGA-application in NPPs. I and C systems of NPPs have been increasingly using FPGA-based equipment as an alternative of microprocessor-based equipment which is not simple to be evaluated for safety due to its complexity. This paper explained the FPGA design flow and design guidelines. Those methodologies can be used as the guidelines on FPGA verification for safety of I and C systems

  5. Síntesis de copolímeros de PS-b-PMMA empleando polimerización radicalaria controlada

    Directory of Open Access Journals (Sweden)

    Vivina Hanazumi

    2016-01-01

    Full Text Available Se estudió la síntesis de copolímeros bloque de poli (estireno y poli (metil metacrilato (PS-b-PMMA empleando polimerización radicalaria por transferencia atómica (ATRP. Se realizaron distintos experimentos variando las relaciones molares de monómero, ligando e iniciador para determinar su influencia en la síntesis de copolímeros PS-b-PMMA con masas molares determinadas y estructura homogénea. Los polímeros sintetizados se caracterizaron químicamente por espectroscopia infrarroja con Transformada de Fourier (FTIR y cromatografía por exclusión de tamaños (SEC, empleando un detector de índice de refracción. Se obtuvieron los copolímeros bloque propuestos, con un buen control de su estructura macromolecular (Mw/Mn < 1,90.

  6. Studerende og underviseres brug af digitale medier - En kvantitativ undersøgelse af Aarhus Universitets studerende og underviseres brug af digitale medier og internettet anno 2008

    Directory of Open Access Journals (Sweden)

    Maria Hvid Stenalt

    2009-06-01

    • Hvilke medier anvender universitetsstuderende generelt? • Ligner undervisernes medievalg/forbrug de studerendes? • Hvilke medier inddrager underviserne i undervisningen? Nærværende artikel vil forsøge at besvare disse spørgsmål på baggrund af en kvantitativ spørgeskemaundersøgelse af Aarhus Universitets studerende og underviseres brug af digitale medier og internettet. Undersøgelsen blev gennemført i efteråret 2008 af E-læringsenheden ved Aarhus Universitet som led i en almen kvalitetssikring på media- og e-læringsområdet, samt som led i en behovsafklaring vedrørende etablering af et medie- og podcastarkiv. E-læringsenheden er en administrativ enhed, der teknisk og pædagogisk understøtter underviseres inddragelse af digitale medier i undervisningen.

  7. Fpga As A Part Of Ms Windows Control Environment

    Directory of Open Access Journals (Sweden)

    Krzysztof Kołek

    2007-01-01

    Full Text Available The attention is focused on the Windows operating system (OS used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS.Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

  8. Long-distance configuration of FPGA based on serial communication

    International Nuclear Information System (INIS)

    Liu Xiang; Song Kezhu; Zhang Sifeng

    2010-01-01

    To solve FPGA configuration in some nuclear electronics, which works in radioactivity environment, the article introduces a way of long-distance configuration with PC and CPLD, based on serial communication. Taking CYCLONE series FPGA and EPCS configuration chip from ALTERA for example, and using the AS configuration mode, we described our design from the aspects of basic theory, hardware connection, software function and communication protocol. With this design, we could configure several FPGAs in the distance of 100 meters, or we could configure on FPGA in the distance of 150 meters. (authors)

  9. Når mobilen tager magten - nærvær i den digitale tidsalter

    DEFF Research Database (Denmark)

    Fenger, Morten Munthe

    at se ind i en skærm? "Når mobilen tager magten" beskriver, hvordan den digitale teknologi og sociale medier såsom Facebook, Instagram og Snapchat går direkte ind og udnytter menneskets instikter, og tilfredsstiller vores behov hurtigere end vores forstand og vilje kan følge med og sige fra. "Når...

  10. Het digitale sport medisch dossier: zucht of zegen? [Digital Sport Medical Record: Sigh or a blessing?

    NARCIS (Netherlands)

    Stege, J.P.; Fleuren, M.A.H.; Knaap, E.T.W. van der; Stubbe, J.H.

    2013-01-01

    Sinds 2004 zijn er verschillende initiatieven ontplooid rondom de ontwikkeling van een digitaal Sport Medisch Dossier (SMD). Uit gesprekken met de Vereniging voor Sportgeneeskunde (VSG) blijkt dat er vooral problemen worden gesignaleerd met de ingebruikname van het digitale SMD. In het voorjaar van

  11. De digitale stresscoach : totale controle over je mentale gezondheid of Big Brother is watching you?

    NARCIS (Netherlands)

    Lieshout, M. van; Wiezer, N.; Korte, E. de

    2014-01-01

    Een digitale coach die je helpt stress op je werk te verminderen en meer energie uit je werk te halen klinkt aantrekkelijk. Stress ervaren we immers allemaal. Net zoals we allemaal streven naar werk waar je energie van krijgt. En stress vermijden we liever. Stress is een maatschappelijk probleem en

  12. Effektregnskab for projektet Digitales ll – Det svære valg

    DEFF Research Database (Denmark)

    Mark, Stine

    Effektregnskabet for projektet Digitales ll – Det svære valg er udarbejdet af forskningscenteret INCEVIDA, Aalborg Universitet 2012. Rapporten er gennemført i et samarbejde mellem INCEVIDA, KulturarvNord og Bangsbo Museum. Effektregnskabet tager udgangspunkt i en model for oplevelsesøkonomisk...

  13. La evaluación de los recursos digitales para las humanidades

    OpenAIRE

    Galina Russell, Isabel

    2016-01-01

    Aunque ha habido un aumento en el reconocimiento de los proyectos de Humanidades Digitales (HD) como formas legítimas de investigación en Humanidades, su evaluación y valoración continúan siendo problemáticas. Una querella común para los humanistas

  14. Wire Position Monitoring with FPGA based Electronics

    International Nuclear Information System (INIS)

    Eddy, N.; Lysenko, O.

    2009-01-01

    This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. An FPGA based digitizer

  15. FPGA fabric specific optimization for RLT design

    International Nuclear Information System (INIS)

    Perwaiz, A.; Khan, S.A.

    2010-01-01

    This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced re configurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned Index Terms: Field Programmable Gate Arrays (FPGA), Compression Tree, Bit Width Reduction, Look Ahead Pipelining. (author)

  16. FPGA Design and Implementation of a Rangefinder

    Directory of Open Access Journals (Sweden)

    ALBU Răzvan-Daniel

    2017-10-01

    Full Text Available In this paper we will present the design and implementation of an ultrasonic non-contact rangefinder with FPGA. This rangefinder can be used in numerous applications, ranging from hardly accessible spaces to electromagnetically polluted environments. The experimental implementations proved to be accurate, portable, and easy to operate. Attributable to their programmable nature, FPGAs are an ideal fit for many dissimilar markets. Even though FPGAs used to be designated for lower speed and complexity designs in the past, today’s FPGAs effortlessly push the 500 MHz performance barricade. Since they bring features, such as embedded processors, DSP blocks, clocking, and high-speed serial at lower prices, FPGAs are a convincing alternative for almost any type of design.

  17. IL SEPPELLIMENTO DI S. LUCIA CARAVAGGIO E LA BIBLIOTECA DIGITALE

    Directory of Open Access Journals (Sweden)

    Francesca Salvemini

    2012-04-01

    Full Text Available

    Tra reificazione e anastilosi documentale, interpretazione dei pittori che copiarono e restaurarono le sue opere, astrazione di antiquari e bibliofili, il recupero del bene artistico e culturale in un indice bibliografico della fortuna del Seppellimento di S. Lucia, dipinto sulla tela a grande formato, a grandezza naturale. Nel sistema iconclassl’indimenticabile avventura del ‘brutto’, né falso né vero nel viaggio in Italia tra le rovine, fra eventi catastrofici e conservazione. Fruizione, estrapolazione ed incetta del mercato, la flagranza  dell’autografia inedita nel sublime: l’irreparabile e l’irreperibile nella cronistoria del gusto. Dall’edizione anastatica, dai microfilms e microfi shes degli originali all’e-book, la riproducibilità della scansione digitale in formato PDF nella storia della ‘legenda’ (avvertenza al lettore: la datazione delle ristampe è affidata all’impronta tipografica.

    The burial of Santa Lucia Caravaggio and the digital library

    Among anastylosis and reassembly and among documental interpretation of the painters who copied and restored his works, and abstraction of antique dealers and bibliophiles, the recovery of an object of art and culture in a bibliography of the luck of the Burial of St. Lucia, painted on large format canvas, on life size. In the Iconclass system the adventure non-objectifi able of the 'ugly', neither true nor false, while traveling through the ruins in Sicily, between the catastrophic events as the earthquakes and the history of restoration and retro-spective conservation of the masterpiece. Over the fruition, and the buying up and the extrapolation of the market, the sublime of the unpublished and flagrante authorship of both through the missed out either through the missing in the history of taste along with the religious feeling. From facsimile editions and original microfilms and micro

  18. Realise of PWM-generating based on FPGA

    International Nuclear Information System (INIS)

    Su Rongfeng; Xu Ruinian; Huang Maomao

    2012-01-01

    The power supply digital controllers of Shanghai Synchrotron Radiation Facility(SSRF) make use of the PWM (pulse width modulation) wave as the feedback to the power-electrical devices, so as to obtain constant current of high accuracy and stability. The design of PWM wave generation structure in FPGA is good for a compact controller,and the reduction of the usage of Integrated Circuits (ICs) decreases the interference from the noise among the ICs, hence better performance of the controller. In addition, FPGA can be programmed circularly at any time,so as to optimize the structure design and make a maximum use of the advantage of FPGA. As a part of transplanting the complete function of the DSP (digital signal processor/processing), realizing the generation of PWM wave in FPGA is feasible. In this paper, we report progress in this regard at SSRF. (authors)

  19. Application-specific mesh-based heterogeneous FPGA architectures

    CERN Document Server

    Parvez, Husain

    2011-01-01

    This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

  20. Technologies for faults diagnosis of FPGA logic blocks

    Directory of Open Access Journals (Sweden)

    C. U. Ngene

    2012-08-01

    Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

  1. Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

    National Research Council Canada - National Science Library

    Bardouleau, Graham; Kulp, James

    2005-01-01

    In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment...

  2. High-Performance Linear Algebra Processor using FPGA

    National Research Council Canada - National Science Library

    Johnson, J

    2004-01-01

    With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

  3. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

  4. A software radio platform based on ARM and FPGA

    Directory of Open Access Journals (Sweden)

    Yang Xin.

    2016-01-01

    Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

  5. fpga controller design and simulation of a portable dough mixing

    African Journals Online (AJOL)

    modelled and simulated with Matlab/Simulink. Synthesizable VHDL ... Keywords: FPGA, VHDL, PID controller, Pulse Width Modulation, Full H-Bridge DC motor driver. 1. ... and (b) to simulate the control process in a virtual environment, using.

  6. Real-time FPGA architectures for computer vision

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar

    2000-03-01

    This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

  7. Competencias digitales en maestros de escuelas de educación media superior privadas

    Directory of Open Access Journals (Sweden)

    Ramona Imelda García López

    2012-10-01

    Full Text Available El propósito de este estudio fue identificar los niveles de adquisición de las competencias digitales de los docentes de las preparatorias incorporadas al Instituto Tecnológico de Sonora (ITSON, a fin de obtener un diagnóstico que permita planear un programa de estrategias de formación en el área de tecnología aplicadas en la educación; lo anterior, debido a que no hay estudios que ayuden a precisar en qué aspectos se necesita capacitar a los maestros de dichas escuelas. La investigación fue descriptiva con enfoque cuantitativo y un diseño no experimental transeccional. Participaron 170 maestros, a quienes se les administró una encuesta compuesta por 47 reactivos que medían cinco dimensiones: conocimientos y habilidades en la Web, organización en formato digital, uso de herramientas o dispositivos digitales para la comunicación, búsqueda electrónica y diseño de recursos educativos digitales. Los resultados revelan que gran parte de los maestros poseen mayor dominio en la dimensión de organización en formato digital y la que menos dominan y en la requieren un curso de capacitación es en la de diseño de recursos educativos digitales. Asimismo, a mayor edad y a más años de servicio, los maestros tienden a hacer un menor uso de la tecnología, por lo que manifiestan un menor dominio de las competencias digitales.

  8. Simultaneous Perturbation Particle Swarm Optimization and Its FPGA Implementation

    OpenAIRE

    Maeda, Yutaka; Matsushita, Naoto

    2009-01-01

    In this paper, we presented hardware implementation of the particle swarm optimization algorithm which is combination of the ordinary particle swarm optimization and the simultaneous perturbation method. FPGA is used to realize the system. This algorithm utilizes local information of objective function effectively without lack of advantage of the original particle swarm optimization. Moreover, the FPGA implementation gives higher operation speed effectively using parallelism of the particle s...

  9. Sistemas de visualización para bibliotecas digitales

    Directory of Open Access Journals (Sweden)

    Bengochea, Luis

    2005-09-01

    Full Text Available The conventional functions of a library are to gather, process, broadcast, store and use the documental information to provide service to the society. And this definition can also be applied in the context of the digital age, where the work of the professionals of the information and documentation is daily related to the use of the available resources through Internet. Although the definition of Digital Library includes a wider term, the present article it will refer to the group of digital resources. Internet is the biggest encyclopedia in the world, but the information is not available in an orderly way and it is not easy to obtain. Although the users, librarians and documentalists have tools as search engines to locate the information, the way we obtain the results is decisive in order to their suitable exploitation. The traditional orderly list of references can loose its effectiveness when the number of obtained documents is very high. In this article, we show several available techniques and developments on visualization systems in the information retrieval in Internet. These systems use elements in two or three dimensions, and it will allow that users, librarians and documentalists have the feeling of moving among the recovered information as they would do in a surface or in the space.

    Las funciones convencionales de una biblioteca son reunir, procesar, difundir, almacenar y usar la información documental para dar servicio a la sociedad. Y esta definición debemos también entenderla dentro del contexto de la era digital, donde el campo de actuación de los profesionales de la información y documentación se ve abocado de forma cotidiana a la utilización de los recursos disponibles a través de Internet. Aunque la definición de Biblioteca Digital engloba un término más amplio, en el presente artículo se concreta en el conjunto de recursos digitales. Internet es la mayor enciclopedia del mundo pero la información no est

  10. Fast semivariogram computation using FPGA architectures

    Science.gov (United States)

    Lagadapati, Yamuna; Shirvaikar, Mukul; Dong, Xuanliang

    2015-02-01

    The semivariogram is a statistical measure of the spatial distribution of data and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. The semivariogram is a plot of semivariances for different lag distances between pixels. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O(n2). Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform tens of thousands of calculations per clock cycle while operating in the low range of power. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. The design consists of several modules dedicated to the constituent computational tasks. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. Anisotropic semivariogram implementation is anticipated to be an extension of the current architecture, ostensibly based on refinements to the current modules. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from MRI scans are utilized for the experiments

  11. Energy efficiency analysis and implementation of AES on an FPGA

    Science.gov (United States)

    Kenney, David

    The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

  12. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-05-23

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

  13. Monitoreo de cambios en la densidad de cobertura forestal en bosque templado usando fotografías aéreas digitales de alta resolución

    Directory of Open Access Journals (Sweden)

    José López García

    2016-08-01

    Full Text Available Se utilizaron series multitemporales de fotografías aéreas digitales de alta resolución de pequeño formato para evaluar los cambios en la densidad de cobertura forestal en un bosque templado. Una combinación de técnicas convencionales y adaptadas de fotogrametría y fotointerpretación fueron utilizadas para establecer un método específico de evaluación.  Este método ha sido probado en un periodo de doce años (1999-2011 en la zona núcleo de la Reserva de la Biósfera Mariposa Monarca, localizada en los estados de México y Michoacán, en México, usando mosaicos ortorectificados como mapas base para evaluar cambios bienales. Las imágenes fueron fotointerpretadas de manera tradicional marcando los cambios sobre acetatos, colocados sobre las imágenes impresas, creando así nuevos polígonos. Estos fueron transferidos directamente de los acetatos al ortomosaico a través de la pantalla de la computadora, usando al menos tres puntos de control, cumpliendo así con el principio de triangulación radial. El bosque fue separado en las siguientes clases de cobertura forestal: cerrada, semi-cerrada, semi-abierta, abierta y deforestada. La evaluación en la exactitud en la clasificación de densidad de cobertura fue estimada a través de muestreos en campo, empleando matrices de confusión, siendo del 95%. A partir de 2003, este método ha sido utilizado para determinar el pago por servicios ambientales. Dicho pago, junto con una gran interacción con las comunidades, se ha traducido en una reducción en la degradación forestal y la deforestación en la zona núcleo de la Reserva.

  14. FPGA fault tolerance in particle physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Gebelein, Jano; Engel, Heiko; Kebschull, Udo [Kirchhoff-Institute for Physics, Heidelberg University (Germany)

    2010-07-01

    The behavior of matter in physically extreme conditions is in focus of many high-energy-physics experiments. For this purpose, high energy charged particles (ions) are collided with each other and energy- or baryon densities are created similar to those at the beginning of the universe or to those which can be found in the center of neutron stars. In both cases a plasma of quarks and gluons (QGP) is present, which immediately decomposes to hadrons within a short period of time. At this process, particles are formed, which allow statements about the beginning of the universe when captured by large detectors, but which also lead to the massive occurance of hardware failures within the detector's electronic devices. This contribution is about methods to mitigate radiation susceptibility for Field Programmable Gate Arrays (FPGA), enabling them to be used within particle detector systems to directly gain valid data in the readout chain or to be used as detector-control-system.

  15. IMPLEMENTATION OF NEURAL - CRYPTOGRAPHIC SYSTEM USING FPGA

    Directory of Open Access Journals (Sweden)

    KARAM M. Z. OTHMAN

    2011-08-01

    Full Text Available Modern cryptography techniques are virtually unbreakable. As the Internet and other forms of electronic communication become more prevalent, electronic security is becoming increasingly important. Cryptography is used to protect e-mail messages, credit card information, and corporate data. The design of the cryptography system is a conventional cryptography that uses one key for encryption and decryption process. The chosen cryptography algorithm is stream cipher algorithm that encrypt one bit at a time. The central problem in the stream-cipher cryptography is the difficulty of generating a long unpredictable sequence of binary signals from short and random key. Pseudo random number generators (PRNG have been widely used to construct this key sequence. The pseudo random number generator was designed using the Artificial Neural Networks (ANN. The Artificial Neural Networks (ANN providing the required nonlinearity properties that increases the randomness statistical properties of the pseudo random generator. The learning algorithm of this neural network is backpropagation learning algorithm. The learning process was done by software program in Matlab (software implementation to get the efficient weights. Then, the learned neural network was implemented using field programmable gate array (FPGA.

  16. Fpga-based control of piezoelectric actuators

    Directory of Open Access Journals (Sweden)

    Juhász László

    2011-01-01

    Full Text Available In many industrial applications like semiconductor production and optical inspection systems, the availability of positioning systems capable to follow trajectory paths in the range of several centimetres, featuring at the same time a nanometre-range precision, is demanding. Pure piezoelectric stages and standard positioning systems with motor and spindle are not able to meet such requirements, because of the small operation range and inadequacies like backlash and friction. One concept for overcoming these problems consists of a hybrid positioning system built through the integration of a DC-drive in series with a piezoelectric actuator. The wide range of potential applications enables a considerable market potential for such an actuator, but due to the high variety of possible positioned objects and dynamic requirements, the required control complexity may be significant. In this paper, a real-time capable state-space control concept for the piezoelectric actuators, embedded in such a hybrid micropositioning system, is presented. The implementation of the controller together with a real-time capable hysteresis compensation measure is performed using a low-budget FPGA-board, whereas the superimposed integrated controller is realized with a dSPACE RCP-system. The advantages of the designed control over a traditional proportional-integral control structure are proven through experimental results using a commercially available hybrid micropositioning system. Positioning results by different dynamic requirements featuring positioning velocities from 1 μm/s up to 5 cm/s are given.

  17. Video Watermarking Implementation Based on FPGA

    International Nuclear Information System (INIS)

    EL-ARABY, W.S.M.S.

    2012-01-01

    The sudden increase in watermarking interest is most likely due to the increase in concern over copyright protection of content. With the rapid growth of the Internet and the multimedia systems in distributed environments, digital data owners are now easier to transfer multimedia documents across the Internet. However, current technology does not protect their copyrights properly. This leads to wide interest of multimedia security and multimedia copyright protection and it has become a great concern to the public in recent years. In the early days, encryption and control access techniques were used to protect the ownership of media. Recently, the watermarking techniques are utilized to keep safely the copyrights. In this thesis, a fast and secure invisible video watermark technique has been introduced. The technique based mainly on DCT and Low Frequency using pseudo random number (PN) sequence generator for embedding algorithm. The system has been realized using VHDL and the results have been verified using MATLAB. The implementation of the introduced watermark system done using Xilinx chip (XCV800). The implementation results show that the total area of watermark technique is 45% of total FPGA area with maximum delay equals 16.393ns. The experimental results show that the two techniques have mean square error (MSE) equal to 0.0133 and peak signal to noise ratio (PSNR) equal to 66.8984db. The results have been demonstrated and compared with conventional watermark technique using DCT.

  18. FPGA Congestion-Driven Placement Refinement

    Energy Technology Data Exchange (ETDEWEB)

    Vicente de, J.

    2005-07-01

    The routing congestion usually limits the complete proficiency of the FPGA logic resources. A key question can be formulated regarding the benefits of estimating the congestion at placement stage. In the last years, it is gaining acceptance the idea of a detailed placement taking into account congestion. In this paper, we resort to the Thermodynamic Simulated Annealing (TSA) algorithm to perform a congestion-driven placement refinement on the top of the common Bounding-Box pre optimized solution. The adaptive properties of TSA allow the search to preserve the solution quality of the pre optimized solution while improving other fine-grain objectives. Regarding the cost function two approaches have been considered. In the first one Expected Occupation (EO), a detailed probabilistic model to account for channel congestion is evaluated. We show that in spite of the minute detail of EO, the inherent uncertainty of this probabilistic model impedes to relieve congestion beyond the sole application of the Bounding-Box cost function. In the second approach we resort to the fast Rectilinear Steiner Regions algorithm to perform not an estimation but a measurement of the global routing congestion. This second strategy allows us to successfully reduce the requested channel width for a set of benchmark circuits with respect to the widespread Versatile Place and Route (VPR) tool. (Author) 31 refs.

  19. Development of FPGA-Based Control Board

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Yoon Hee; Jeong, See Chae; Choi, Woong Seock; Lee, Chang Jae; Jeong, Jin Kwon; Ha, Jae Hong [Korea Power Engineering Company Inc., Daejeon (Korea, Republic of)

    2009-10-15

    It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a FPGAbased control board performing user-defined control functions. An Actel ProASIC{sup plus} FPGA platform is implemented as the comparator of Plant Protection System (PPS). Functional simulation is implemented for the comparator.

  20. Multi-Softcore Architecture on FPGA

    Directory of Open Access Journals (Sweden)

    Mouna Baklouti

    2014-01-01

    Full Text Available To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication.

  1. Sugli studi medievali e il mutamento digitale On the medieval studies and the digital change

    Directory of Open Access Journals (Sweden)

    Redazione Reti Medievali (a cura di

    2004-12-01

    Full Text Available

    La sezione raccoglie tre brevi comunicazioni, tenute nell’ambito del seminario Medium-Evo. Gli studi medievali e il mutamento digitale (Firenze, 2001 e dedicate rispettivamente ai periodici e alle forme di comunicazione del sapere (Giorgio Chittolini, al problema del reperimento delle risorse e della repertoriazione delle fonti (Paolo Delogu, ai contraccolpi dell’uso del mezzo informatico sulla scrittura della storia (Giuseppe Sergi.

    This section includes three short papers - presented at the seminar on Medium-Evo. Gli studi medievali e il mutamento digitale (Firenze, 2001 (Medium-Evo. Medieval studies and the digital change - which are respectively focused on periodicals, different types of learning communication (Giorgio Chittolini, problems linked to document searching and filing (Paolo Delogu, backlashes  coming from the use of computer in writing history (Giuseppe Sergi.

  2. Modelo de Producción de Contenidos Digitales para la Educación Online

    OpenAIRE

    Evelio Granizo; Silvia Haro

    2016-01-01

    A partir de un análisis del estado actual de la industria de contenidos digitales y del entorno normativo y legal del Ecuador, referido principalmente a temas de seguridad en Internet y derechos de propiedad intelectual; y a través de una investigación de mercado, para identificar las necesidades de los usuarios y aprovechar las oportunidades y retos que presenta la educación en línea; se recomienda un modelo de producción de contenidos digitales para la educación en línea, basado en un esque...

  3. Embedded system in FPGA-based LLRF controller for FLASH

    Science.gov (United States)

    Szewinski, Jaroslaw; Pucyk, Piotr; Jalmuzna, Wojciech; Fafara, Przemyslaw; Pieciukiewicz, Marcin; Romaniuk, Ryszard; Pozniak, Krzysztof T.

    2006-10-01

    FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

  4. FAS: Using FPGA to Accelerate and Secure SDN Software Switches

    Directory of Open Access Journals (Sweden)

    Wenwen Fu

    2018-01-01

    Full Text Available Software-Defined Networking (SDN promises the vision of more flexible and manageable networks but requires certain level of programmability in the data plane to accommodate different forwarding abstractions. SDN software switches running on commodity multicore platforms are programmable and are with low deployment cost. However, the performance of SDN software switches is not satisfactory due to the complex forwarding operations on packets. Moreover, this may hinder the performance of real-time security on software switch. In this paper, we analyze the forwarding procedure and identify the performance bottleneck of SDN software switches. An FPGA-based mechanism for accelerating and securing SDN switches, named FAS (FPGA-Accelerated SDN software switch, is proposed to take advantage of the reconfigurability and high-performance advantages of FPGA. FAS improves the performance as well as the capacity against malicious traffic attacks of SDN software switches by offloading some functional modules. We validate FAS on an FPGA-based network processing platform. Experiment results demonstrate that the forwarding rate of FAS can be 44% higher than the original SDN software switch. In addition, FAS provides new opportunity to enhance the security of SDN software switches by allowing the deployment of bump-in-the-wire security modules (such as packet detectors and filters in FPGA.

  5. Digitale teknologier på det specialpædagogiske område

    DEFF Research Database (Denmark)

    Dupret, Katia

    2015-01-01

    Denne artikel handler om, hvordan forsøgsvis indførelse af digitale teknologier (tablets til kommunikation og kognitiv træning, virtuelle tavler og virtuel dagbog) på det specialpædagogiske område ændrer på grundlaget for brugernes livskvalitet, herunder autonomi og vilkår for social nærhed...

  6. Dimensiones e indicadores de la calidad informativa en los medios digitales

    Directory of Open Access Journals (Sweden)

    2016-10-01

    Full Text Available El actual ecosistema informativo, atravesado por una lógica de mediamorfosis, está generando con avidez el surgimiento de medios digitales y portales informativos que no siguen los procedimientos editoriales formales de los medios convencionales. La crisis de los medios de comunicación tradicionales ha cambiado también nuestra forma de informarnos. Sin embargo, la calidad informativa sigue siendo un factor de discusión al no existir unidad de criterios para su análisis. En este sentido surge la pregunta ¿Cómo evaluar y valorar la calidad informativa de los medios digitales? Este trabajo contribuye a buscar convergencias entre académicos y profesionales de la comunicación sobre las áreas y dimensiones de la calidad informativa de los medios digitales en función de valores objetivos o cuantificables. Para ello se ha realizado una taxonomía de dimensiones de la calidad informativa a partir de la revisión de la literatura científica, para posteriormente someterlo a la evaluación y validación por juicio de 40 expertos, académicos y profesionales de la comunicación, para verificar su fiabilidad. Como resultado, quedaron validadas tres macroáreas de la calidad informativa, contentivas en 21 ámbitos que consideran intrínsecamente un total de 75 dimensiones. Esta investigación propone finalmente un modelo estructurado que permitirá analizar la calidad informativa de los medios digitales, tanto en su fase pre-informativa, catalogadas en el medio-empresa, las características sociolaborales de los trabajadores del medio, así como el producto final y el contenido informativo.

  7. Interpretación de las competencias digitales profesorales presentes en el contexto universitario

    Directory of Open Access Journals (Sweden)

    Mariel Evelyn Castellanos Adarme

    2018-01-01

    Full Text Available La investigación tuvo como objetivo interpretar realidades en competencias digitales de docentes y estudiantes en Norte de Santander, buscó contribuir con la educación de calidad en la consolidación de competencias digitales, al innovar y transformar la realidad universitaria a través del pensamiento reflexivo hacia un aprendizaje significativo y colaborativo con horizonte pedagógico socio critico apoyado en las teorías de la complejidad y el constructivismo para lograr que concurran los tres elementos básicos: Estado-Profesores-Estudiantes. Siguió la metodología cualitativa, mediante la etnografía y con un método de análisis hermenéutico, a partir de cuatro fases sistemáticas para la correcta gestión de la investigación, se seleccionaron como informantes clave a profesores, estudiantes a quienes se les aplicó la entrevista a profundidad así como la observación participante, el análisis de la información se llevó mediante la categorización, emergiendo resultados cruciales en los espacios académicos para la consolidación de competencias digitales. Resultados muestran el escaso dominio de competencias digitales por parte de profesores y estudiantes en logro de un aprendizaje significativo; se concluye que existe un distanciamiento entre la realidad y el deber ser; es decir, entre la planeación y ejecución de acciones que conduzcan al uso, familiarización e integración de las tecnologías como se demanda y prácticas en el ámbito educativo y laboral actual.

  8. Digital radiography - from principles to practical testing; Digitale Radiografie - von den Grundlagen zur Pruefpraxis

    Energy Technology Data Exchange (ETDEWEB)

    Mattis, A. [Siemens KWU, Erlangen (Germany)

    1994-12-31

    Digital radiography is broken down into two branches: storage luminescence technology and digitalization of existing films. The principles of both methods are presented in a short outline. The main advantages of this technology include decay-proof archiving that dispenses with film storage, computerized analysis of images using quantitative assessment standards, and improved display readability as compared to visual analysis. As a neutral authority, the Federal Institute for Materials Research and Testing (BAM) was charged with making an assessment of digital radiography by means of the approved ROC method. Based on an extensive collection of test pieces, the respective final result of the analysis was compared with the transmission images, i.e. digital data were compared with original films. (orig./MM) [Deutsch] Die Digitale Radiografie teilt sich in zwei Zweige - die Speicherleuchtstofftechnik sowie die Digitalisierung vorhandener Filme. Die Prinzipien beider Verfahren werden in einem kurzen Abriss dargestellt. Hauptvorteile dieser Technik sind die verfallsgesicherte Archivierung, die die Aufbewahrung der Filme ueberfluessig macht, die rechnergestuetzte Analyse der Aufnahmen unter Einsatz quantitativer Beurteilungsmassstaebe sowie die verbesserte Anzeigenerkennbarkeit gegenueber der visuellen Auswertung. Als neutrale Instanz wurde die Bundesanstalt fuer Materialforschung (BAM) beauftragt, mithilfe des anerkannten ROC-Verfahrens die Digitale Radiografie zu beurteilen. Basierend auf einer umfangreichen Sammlung von Teststuecken wurde das jeweilige Endergebnis der Auswertung der Durchstrahlungsaufnahmen verglichen d.h. digitale Daten mit Original-Filmen. (orig./MM)

  9. The integration of FPGA TDC inside White Rabbit node

    International Nuclear Information System (INIS)

    Li, H.; Xue, T.; Gong, G.; Li, J.

    2017-01-01

    White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

  10. A low-power wave union TDC implemented in FPGA

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

    2011-01-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  11. FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

    Directory of Open Access Journals (Sweden)

    Tomyslav Sledevič

    2013-05-01

    Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

  12. The integration of FPGA TDC inside White Rabbit node

    Science.gov (United States)

    Li, H.; Xue, T.; Gong, G.; Li, J.

    2017-04-01

    White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

  13. Flexible, fpga-based electronics for modular robots

    DEFF Research Database (Denmark)

    Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

    2008-01-01

    In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

  14. An FPGA-based heterogeneous image fusion system design method

    Science.gov (United States)

    Song, Le; Lin, Yu-chi; Chen, Yan-hua; Zhao, Mei-rong

    2011-08-01

    Taking the advantages of FPGA's low cost and compact structure, an FPGA-based heterogeneous image fusion platform is established in this study. Altera's Cyclone IV series FPGA is adopted as the core processor of the platform, and the visible light CCD camera and infrared thermal imager are used as the image-capturing device in order to obtain dualchannel heterogeneous video images. Tailor-made image fusion algorithms such as gray-scale weighted averaging, maximum selection and minimum selection methods are analyzed and compared. VHDL language and the synchronous design method are utilized to perform a reliable RTL-level description. Altera's Quartus II 9.0 software is applied to simulate and implement the algorithm modules. The contrast experiments of various fusion algorithms show that, preferably image quality of the heterogeneous image fusion can be obtained on top of the proposed system. The applied range of the different fusion algorithms is also discussed.

  15. FPGA development board for applications in cosmic rays physics

    International Nuclear Information System (INIS)

    Angelov, Ivo; Damov, Krasimir; Dimitrova, Svetla

    2013-01-01

    The modern experiments in cosmic rays and particle physics are usually performed with large number of detectors and signal processing have to be done by complex electronics. The analog signals from the detectors are converted to digital (by discriminators or fast ADC) and connected to different type of logic implemented in FPGA (Field Programmable Gate Arrays). A FPGA development board based on Xilinx XC3S50AN was designed, assembled and tested. The board will be used for developing a modern registering controller (to replace the existing now) for the muon telescope in the University and can be used for other experiments in cosmic rays physics when fast digital pulses have to be processed. Keywords: FPGA, Spartan3A, muon telescope, cosmic rays variations

  16. Porting VIRTEX4 data acquisition design to SPARTAN6 FPGA

    International Nuclear Information System (INIS)

    Suetoe, J.; Hegyesi, G.

    2012-01-01

    Complete text of publication follows. The Atomki's Virtex 4 based 4 channel data acquisition card (LIR) card was used in many applications (miniPET-II, miniPET-III, data acquisition system for the multichannel plate installed at the ECR lab). The goal of the work was to improve the LIR using a higher performance FPGA (Spartan6 Trenz module). The Trenz module based system also supports ADC channels up to 16 channels. This work also implied the porting of the Virtex4 based VHDL code to Spartan 6. Further advantage of the proposed system, besides the improvement in the number of ADC channels, that the Spartan6 FPGA is able to run more complex digital signal processing algorithms than the Virtex 4 FPGA. Easy access to the control parameters (via serial interface or Ethernet), flexibility and high performance were considered during the development. SPARTAN6 FPGA based data acquisition provides more facilities than the VIRTEX4 based. SPARTAN6 is a newer generation of XILINX’s FPGAs, which excellent into the high-speed data acquisition. We ported the HDL code, which runs on LIR module (VIRTEX4 based), to the Trenz module (SPARTAN6 based). The main parts of the whole program code are the command line interpreter, GMII interface, DHCP process, ARP process and the data read out. Those parts were implemented by picoblaze embedded system. Figure 1 shows the command line interpreter process in the Hyper Terminal. The command line interpreter communicates with the PC via serial port. In addition, the AdamIOSetting software also use the serial communication, which was created to the VIRTEX FPGA based data collector. In the Wireshark network analyzer software we examined the DHCP and ARP process and using the AdamIOSettings software we tested the data read out from the flash memory of FPGA board. Figure 2 shows the AdamIOSettings program. Acknowledgements. This work was supported by the ENIAC CSI Project (No.120209).

  17. Proyecto de mejora de la durabilidad de los pavimentos usados en aeropuertos empleando materiales alternativos y geo-sintéticos

    OpenAIRE

    Cabezuelo Moreno, Juan José

    2015-01-01

    Contribuir a la mejora de la durabilidad de los pavimentos usados en las pistas de aeropuertos, en particular pavimentos de tipo flexible, empleando combinaciones de capas de diferentes materiales y geo-sintéticos. En particular, plantear el uso de materiales novedosos como alternativa a las típicas capas de pavimento a base de hormigón y mejora de la durabilidad de las mismas empleando combinaciones de sendos materiales y geo-sintéticos. El mundo de la aviación y en concreto el del diseño...

  18. Multifunctional data acquisition system based on USB and FPGA

    International Nuclear Information System (INIS)

    Huang Tuchen; Gong Hui; Shao Beibei

    2013-01-01

    A multifunctional data acquisition system based on USB and FPGA was developed. The system has four analog inputs digitalized by fast ADC. Based on flexibility of FPGA, different functions can be implemented such as waveform sampling, pulse counting, multi-channel pulse height analysis, and charge division readout process. The hardware communicates with host PC via USB interface. The Labview based user soft ware initializes the hardware, configures the running parameters, reads and processes the data as well as displays the result online. (authors)

  19. VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

    Science.gov (United States)

    Rais, Muhammad H.; Qasim, Syed M.

    2010-06-01

    In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

  20. Design and FPGA Implementation of a new hyperchaotic system

    International Nuclear Information System (INIS)

    Wang Guangyi; Bao Xulei; Wang Zhonglin

    2008-01-01

    In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic Nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array (FPGA) technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup. (general)

  1. B-DCGAN:Evaluation of Binarized DCGAN for FPGA

    OpenAIRE

    Terada, Hideo; Shouno, Hayaru

    2018-01-01

    We are trying to implement deep neural networks in the edge computing environment for real-world applications such as the IoT(Internet of Things), the FinTech etc., for the purpose of utilizing the significant achievement of Deep Learning in recent years. Especially, we now focus algorithm implementation on FPGA, because FPGA is one of the promising devices for low-cost and low-power implementation of the edge computer. In this work, we introduce Binary-DCGAN(B-DCGAN) - Deep Convolutional GAN...

  2. Logic synthesis for FPGA-based finite state machines

    CERN Document Server

    Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

    2016-01-01

    This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

  3. Using FPGA coprocessor for ATLAS level 2 trigger application

    International Nuclear Information System (INIS)

    Khomich, Andrei; Hinkelbein, Christian; Kugel, Andreas; Maenner, Reinhard; Mueller, Matthias

    2006-01-01

    Tracking has a central role in the event selection for the High-Level Triggers of ATLAS. It is particularly important to have fast tracking algorithms in the trigger system. This paper investigates the feasibility of using FPGA coprocessor for speeding up of the TRT LUT algorithm-one of the tracking algorithms for second level trigger for ATLAS experiment (CERN). Two realisations of the same algorithm have been compared: one in C++ and a hybrid C++/VHDL implementation. Using a FPGA coprocessor gives an increase of speed by a factor of two compared to a CPU-only implementation

  4. FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications

    Directory of Open Access Journals (Sweden)

    S. Tsakiris

    2009-09-01

    Full Text Available This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.

  5. Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

    Directory of Open Access Journals (Sweden)

    Bhattacharyya Shuvra S

    2003-01-01

    Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

  6. FPGA prototyping by Verilog examples Xilinx Spartan-3 version

    CERN Document Server

    Chu, Pong P

    2008-01-01

    FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a "learn by doing" approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

  7. CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

    CERN Document Server

    Zhu, Yu

    2010-01-01

    Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

  8. Random number generators for large-scale parallel Monte Carlo simulations on FPGA

    Science.gov (United States)

    Lin, Y.; Wang, F.; Liu, B.

    2018-05-01

    Through parallelization, field programmable gate array (FPGA) can achieve unprecedented speeds in large-scale parallel Monte Carlo (LPMC) simulations. FPGA presents both new constraints and new opportunities for the implementations of random number generators (RNGs), which are key elements of any Monte Carlo (MC) simulation system. Using empirical and application based tests, this study evaluates all of the four RNGs used in previous FPGA based MC studies and newly proposed FPGA implementations for two well-known high-quality RNGs that are suitable for LPMC studies on FPGA. One of the newly proposed FPGA implementations: a parallel version of additive lagged Fibonacci generator (Parallel ALFG) is found to be the best among the evaluated RNGs in fulfilling the needs of LPMC simulations on FPGA.

  9. Activismo y Prácticas Digitales en la Construcción de una Esfera LGTB en España

    Directory of Open Access Journals (Sweden)

    Begonya Enguix Grau

    Full Text Available RESUMEN A partir de una interrogación antropológica sobre las “comunidades” y la construcción de una “esfera pública”, este artículo aborda las estrategias digitales que sirven para dar forma a lo que podría denominarse como la esfera LGTB española. Consideramos el activismo LGTB como el principal productor de discurso social legitimado y por ello hemos analizado las páginas web de siete colectivos LGTB y otros recursos digitales para examinar la articulación de prácticas digitales y no digitales, que se basan en un conocimiento compartido que evoca las identidades colectivas y retroalimenta el activismo. Tras combinar trabajo de campo antropológico sobre el activismo y etnografías digitales de entornos virtuales, consideramos que a pesar del uso intensivo de los recursos digitales, la esfera LGTB sigue dependiendo en gran medida de las redes sociales tradicionales. Como consecuencia, ponemos en duda la utilidad de la conceptualización de las relaciones digitales y no digitales como separadas y distintas y discutimos esa imbricación como una característica del activismo contemporáneo.

  10. FPGA design best practices for team-based reuse

    CERN Document Server

    Simpson, Philip Andrew

    2015-01-01

    This book describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book’s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expand...

  11. A PMSM current controller system on FPGA platform | Ahmadian ...

    African Journals Online (AJOL)

    Journal of Fundamental and Applied Sciences ... Proposed system architecture and computational blocks are described and system level and RTL simulation results are presented. Simulation results show that the total computation cycle time of implemented system on Altera Cyclone II FPGA is 456ns. Keywords: PMSM ...

  12. VHDL, FPGA and the master trigger controller of BES

    International Nuclear Information System (INIS)

    Guo Yanan; Wang Jufang; Zhao Dixin

    1996-01-01

    A Master Trigger Controller was made using fast FPGA (Field-Programmable Gate Array) instead of ECLIC (Emitter-Coupled Logic Integrated Circuit). VHDL (Verilog Hardware Description Language) was used in its design. The same performance was obtained with increased flexibility

  13. FPGA based VME boards for Indus-2 timing control system

    International Nuclear Information System (INIS)

    Lulani, Nitin; Barpande, K.; Fatnani, P.; Sheth, Y.

    2009-01-01

    FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards. (author)

  14. FPGA based fast synchronous serial multi-wire links synchronization

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2013-10-01

    The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

  15. FPGA Mezzanine Cards for CERN’s Accelerator Control System

    CERN Document Server

    Alvarez, P R; Lewis, J; Serrano, J; Wlostowski, T

    2009-01-01

    Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, PCI and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed...

  16. N queens on an fpga: mathematics,programming, or both?

    NARCIS (Netherlands)

    Kuper, Jan; Wester, Rinse

    2014-01-01

    This paper presents a design methodology for deriving an FPGA implementation directly from a mathematical specification, thus avoiding the switch in semantic perspective as is present in widely applied methods which include an imperative implementation as an intermediate step. The first step in the

  17. Junction Temperature Aware Energy Efficient Router Design on FPGA

    DEFF Research Database (Denmark)

    Thind, Vandana; Sharma, Shivani; Minwer, M H

    2015-01-01

    Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature...

  18. Effective and efficient FPGA synthesis through general functional decomposition

    NARCIS (Netherlands)

    Jozwiak, L.; Slusarczyk, A.S.; Chojnacki, A.

    2003-01-01

    In this paper, a new information-driven circuit synthesis method is discussed that targets LUT-based FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The method is based on the bottom–up general functional decomposition and theory of information relationship measures that we

  19. Programovatelná hradlová pole - FPGA

    Czech Academy of Sciences Publication Activity Database

    Daněk, Martin

    2006-01-01

    Roč. 12, č. 2 (2006), s. 9-13 ISSN 1210-9592 R&D Projects: GA ČR GA102/04/2137 Institutional research plan: CEZ:AV0Z10750506 Keywords : FPGA architecture * physical design * design flow Subject RIV: JC - Computer Hardware ; Software

  20. Test of Gb Ethernet with FPGA for HADES upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Gilardi, C. [II. Physikalisches Inst., Giessen Univ. (Germany)

    2007-07-01

    Within the HADES experiment, we are investigating a trigger upgrade in order to run heavier systems (Au + Au). We investigate Gigabit Ethernet transfers with Xilinx Virtex II FPGA on the commercial board Celoxica RC300E. We implement the transfer protocols (UDP, ICMP, ARP) with Handel-C. First results of bandwidth and latency will be presented. (orig.)

  1. FPGA-based implementation of sorting networks in MMC applications

    DEFF Research Database (Denmark)

    Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

    2016-01-01

    , and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance...

  2. Uranus: a rapid prototyping tool for FPGA embedded computer vision

    Science.gov (United States)

    Rosales-Hernández, Victor; Castillo-Jimenez, Liz; Viveros-Velez, Gilberto; Zuñiga-Grajeda, Virgilio; Treviño Torres, Abel; Arias-Estrada, M.

    2007-01-01

    The starting point for all successful system development is the simulation. Performing high level simulation of a system can help to identify, insolate and fix design problems. This work presents Uranus, a software tool for simulation and evaluation of image processing algorithms with support to migrate them to an FPGA environment for algorithm acceleration and embedded processes purposes. The tool includes an integrated library of previous coded operators in software and provides the necessary support to read and display image sequences as well as video files. The user can use the previous compiled soft-operators in a high level process chain, and code his own operators. Additional to the prototyping tool, Uranus offers FPGA-based hardware architecture with the same organization as the software prototyping part. The hardware architecture contains a library of FPGA IP cores for image processing that are connected with a PowerPC based system. The Uranus environment is intended for rapid prototyping of machine vision and the migration to FPGA accelerator platform, and it is distributed for academic purposes.

  3. Single Event Effects in FPGA Devices 2015-2016

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  4. SEU mitigation exploratory tests in a ITER related FPGA

    International Nuclear Information System (INIS)

    Batista, Antonio J.N.; Leong, Carlos; Santos, Bruno; Fernandes, Ana; Ramos, Ana Rita; Santos, Joana P.; Marques, José G.; Teixeira, Isabel C.; Teixeira, João P.; Sousa, Jorge; Gonçalves, Bruno

    2017-01-01

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  5. Photoelectric radar servo control system based on ARM+FPGA

    Science.gov (United States)

    Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

    2016-01-01

    In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

  6. SEU mitigation exploratory tests in a ITER related FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

    2017-05-15

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  7. De la Amintiri de familie la Arhive digitale – Europeana Şi valenţele educative ale colecţiilor sale digitale

    Directory of Open Access Journals (Sweden)

    Cristina Ioana Roiu

    2015-01-01

    Full Text Available Digitizarea în masă a colecţiilor instituţiilor de tip GLAM (galerii, biblioteci, arhive si muzee pune la dispoziţia utilizatorilor uriaşe resurse informaţionale istorice, culturale, lingvistice în format digital care sunt tot mai mult folosite în procesul educaţional de pretutindeni. Articolul descrie experienţa si rezultatele derulării în Romania a unor activităţi şi proiecte educative non formale ce au vizat crearea Şi utilizarea arhivelor digitale Europeana 1914-1918 Şi Europeana 1989.

  8. Producción potencial de biogás empleando excretas de ganado porcino en el estado de Guanajuato

    Directory of Open Access Journals (Sweden)

    Miguel Martínez Lozano

    2015-01-01

    Full Text Available La actual reforma energética, así como los cambios mundiales en el uso y obtención de energía eléctrica o calorífica, empleando fuentes alternas, han llevado a replantear y maximizar el uso y explotación del biogás que se obtiene a partir de las excretas de diferentes tipos de ganado. El Estado de Guanajuato, posee un interesante número de cabezas de ganado en el ámbito bovino y porcino, lo que ha originado el planteamiento del presente artículo. En este trabajo, se presenta un estudio, empleando estadísticas locales, conducente a evaluar el potencial energético disponible a partir del uso de las excretas de ganado porcino, para producir Biogás y de ahí, establecer una valoración de la energía eléctrica anual obtenible, el ahorro en equivalente a barriles de petróleo que se podría manejar y la cantidad de gases que se dejarían de añadir a la atmósfera. El estudio se realiza dividiendo el estado por municipios y estableciendo los totales de cada variable de interés en el proceso. Los indicadores muestran que dada la sencillez de implementación de biodigestores para la producción de biogás, esta debe ser una alternativa interesante e importante a desarrollar y potenciar en los próximos años en el país. En el caso particular del Estado de Guanajuato, existen cerca de un millón de cerdos de diferentes edades registrados, pudiendo producir una energía potencial para alimentar a más de 60,000 viviendas estándar.

  9. Curso MOOC para fomentar el desarrollo de competencias digitales en estudiantes universitarios y autodidactas

    Directory of Open Access Journals (Sweden)

    Prince, Marcella Solange

    2016-06-01

    Full Text Available Este proyecto diseñó e implementó un MOOC, con el objetivo de encontrar respuesta a ¿Cómo el uso de los REA promueve el desarrollo de competencias básicas digitales en alumnos de nivel superior de tres universidades de México y una de Venezuela y de autodidactas ubicados en distintos países de América?, mediante el uso de la herramienta BlackBoard en su versión gratuita de CourseSites se elaboró el REA. La duración del curso fue de quince días, para diseminar en tres unidades de trabajo, el conocimiento respecto al desarrollo de habilidades digitales de búsqueda y filtración de información gráfica, elección y reutilización de imágenes respectando los derechos de autor; para la recolección de datos se realizaron entrevistas a estudiantes, profesores, un experto en REA y un experto en diseño y se analizaron datos de la bitácora, contrastándolos con la teoría. Los resultados muestran las dificultades que se pueden presentar en la implementación de un curso MOOC y que, el grado de apropiación de las herramientas tecnológicas, deviene de su utilización no solo socialmente sino de su utilización en forma sistemática en el proceso de actividades académicas o de aprendizaje autónomo, y en consecuencia el desarrollo de competencias digitales.

  10. La relevancia de los medios digitales en la Iniciativa Ciudadana Europea

    Directory of Open Access Journals (Sweden)

    Carlos Espaliú Berdud

    2016-02-01

    Full Text Available

    La corriente política y social que en todo el mundo tiende a una mayor participación ciudadana en la gobernanza de las instituciones se materializó en el Derecho comunitario, entre otras cosas, en la inclusión de la figura de la iniciativa ciudadana, en virtud del Tratado de Lisboa, como un derecho más dentro del abanico del estatuto de la ciudadanía europea.  Los textos normativos comunitarios han previsto un importante papel para los medios digitales, tanto para facilitar la información como la participación de los ciudadanos. Habiendo transcurrido ya unos tres años desde el comienzo de la posibilidad de presentar iniciativas ciudadanas y habiéndose promovido ya en la práctica unas cincuenta, se posee ya perspectiva suficiente para valorar si aquellas expectativas eran fundadas o no. Tras el estudio pertinente, hemos podido corroborar cómo los medios digitales han resultado esenciales para alcanzar los fines para los que se pensó la iniciativa ciudadana, tanto en el sentido de servir de altavoz de las iniciativas promovidas, como en el de facilitar las recogidas de apoyos mediante páginas web. Incluso, parece que la práctica demuestra que hoy en día ya sería imposible, por falta de tiempo y medios de todo tipo, alcanzar las cifras de apoyo requeridas por las normas pertinentes sobre la iniciativa ciudadana, en los plazos previstos, si no es con ayuda de los medios digitales.

  11. La industria musical colombiana en el mercado de los nuevos usos digitales

    Directory of Open Access Journals (Sweden)

    Juan Carlos Monroy Rodríguez

    2006-01-01

    Full Text Available Este artículo pone de presente una realidad que está transformando el mercado de la industria fonográfica, discográfica y cinematográfica. En efecto, hoy en día esta industria ha perdido competitividad en un mercado donde es más económico descargar archivos de música de Internet y fijarlos a través de quemadores en soportes físicos o fijarlos en formatos de comprensión digital (MP3, que comprar los soportes físicos que pagan derechos de autor. Con este panorama actual, el artículo propone alternativas para hacer viable un mercado legal de la música y el cine a través de usos digitales, con soluciones como el uso de ringtones y master tones como una de las posibilidades para poner obras musicales a disposición del público a través de usos digitales y así mismo buscar que los titulares de estos derechos puedan obtener un lucro. De otro lado, también se propone la opción de eliminar los soportes o medios físicos y hacer accesibles al público las obras a través de medios digitales, como un downloading oneroso, que requerirá la adopción de medidas tecnológicas que disuadan el downloading gratuito. Finalmente, el artículo rescata la labor que han realizado las sociedades de gestión colectiva en Colombia buscando poner acorde con el mercado a los autores y a los titulares de derechos conexos.

  12. Integración de tabletas digitales como herramienta mediadora en procesos de aprendizaje

    Directory of Open Access Journals (Sweden)

    Claudia Sahagún Jiménez

    2016-10-01

    Full Text Available En este artículo presenta los resultados de un estudio sobre la manera en que las tabletas digitales se implementan como herramienta mediadora en educación básica para favorecer la construcción de aprendizajes significativos y el desarrollo de habilidades de trabajo colaborativo. La investigación fue diseñada metodológicamente como un estudio intrínseco de casos centrado en el trabajo de alumnos de cuarto grado de primaria del Centro Educativo Monarca, escuela particular situada en Zamora, Michoacán. Se utilizaron como instrumentos de recolección de datos la observación directa, el análisis de documentos y de aplicaciones en tabletas digitales, lo que permitió una reflexión sobre el proceso de construcción del conocimiento y sus desafíos y la intervención del maestro como gestor del ambiente de aprendizaje.   Los resultados muestran que el uso de tabletas, a través de sus aplicaciones, impulsa un acercamiento real al conocimiento y a la posibilidad de crear y compartir saberes, lo que amplía rutas de acceso a la información y permite la organización del conocimiento y la comunicación de lo que se aprende. El documento apunta a posibles líneas de acción, como explorar con mayor profundidad los contenidos digitales elaborados por los alumnos en relación con el desarrollo de habilidades de pensamiento crítico y creativo.  

  13. Edición Especial: Las redes sociales digitales en la educación del siglo XXI

    OpenAIRE

    Pedagógicos, Ensayos

    2017-01-01

    Vivimos en una constante y acelerada innovación tecnológica, especialmente en el campo de las tecnologías de información y comunicación (TIC). Los recursos, servicios y espacios digitales se han ido transformando e incorporando en los últimos años a los estilos de vida de las personas, tanto para trabajar, comunicarse y producir conocimiento como consumir medios y contenido de entretenimiento, colaborar y socializar. En este sentido es innegable distinguir que las redes sociales digitales son...

  14. Conductas sociocomunicativas de los nativos digitales y los jóvenes en la web 2.0

    OpenAIRE

    García-García, F. (Francisco); Rosado-Millán, M.J. (María Jesús)

    2012-01-01

    La investigación se centra en el estudio de la percepción que los nativos digitales y los jóvenes tienen acerca de sus conductas y relaciones sociales en la Web 2.0. Se parte de la hipótesis de que la forma en que los adolescentes y jóvenes utilizan la red a través de los servicios y contenidos digitales abiertos, está transformando sus relacionales sociales en la medida en que son abiertas, activas, globales, inmediatas, y poco controlables por otros agentes sociales (familiares, educativos ...

  15. Competencias digitales y aprendizaje de ofimática en los estudiantes de una universidad privada - 2015

    OpenAIRE

    Neyra Herrera, Miguel Ángel

    2015-01-01

    El presente trabajo de investigación tuvo como problema general: ¿Qué relación que existe entre las competencias digitales y el aprendizaje de ofimática, en los estudiantes del I ciclo de ingeniería de sistemas e informática de la Universidad Alas Peruanas, 2015? y el objetivo general fue: Determinar si existe relación entre las competencias digitales y el aprendizaje de ofimática, en los estudiantes del I ciclo de ingeniería de sistemas e informática de la Universidad Alas ...

  16. El laberinto teatral de espejos digitales : la presentación de mexicano-americanos en Facebook

    OpenAIRE

    Arao Galhardi, Renato de Almeida

    2010-01-01

    Este trabajo explora las formas en las cuales mexicano-americanos universitarios actualmente viviendo en Estados Unidos, se presentan en un sitio de redes sociales, Facebook. Partiendo de los enfoques del interaccionismo simbólico, la fenomenología y la psicología social, investigando cómo éstos incorporan la mexicanidad dentro de sus presentaciones digitales. 1. Definición del marco analítico. -- 2. Internet: la red de redes. -- 3. Una introducción a Facebook. -- 4. Analogías digitales: s...

  17. Objetos nómadas digitales: caso de estudio las comunidades shuar ecuatorianas

    Directory of Open Access Journals (Sweden)

    Yolanda Martinez Suarez

    2015-05-01

    Full Text Available En este texto focalizaremos la atención hacia los “objetos nómadas” (Lasén, 2006, fundamentalmente, en su versión de teléfono móvil, en el contexto de las comunidades indígenas ecuatorianas shuar meridionales de tradición nómada. La finalidad es analizar los flujos y movilidades, las fricciones y cosmovisiones que estos dispositivos revelan mediante sus usos e imaginarios. A la luz de esto, ¿cómo se apropian los shuar ecuatorianos de las tecnologías móviles digitales?

  18. Competencia Digital: Uso y manejo de modelos 3D tridimensionales digitales e impresos en 3D

    OpenAIRE

    Jose Luis Saorín; Cecile Meier; Jorge de la Torre-Cantero; Carlos Carbonell-Carrera; Dámari Melián-Díaz; Alejandro Bonnet de León

    2017-01-01

    El uso y manejo de modelos tridimensionales digitales no está concebido dentro de la competencia digital de los currículos de secundaria y Bachillerato. Sin embargo muchos autores relacionan la competencia digital con el manejo de modelos 3D, el modelado 3D y entornos virtuales tridimensionales (Realidad aumentada, virtual,…). En este artículo se presenta un recurso educativo para facilitar el acceso a contenidos didácticos de carácter tridimensional digital y tangible. Determinadas materias ...

  19. Cosificación de las adolescentes en las redes sociales digitales

    OpenAIRE

    Urdangarin Aranbarri, Garazi

    2015-01-01

    La cosificación se refiere a la representación de una mujer a través de su cuerpo o partes de éste. La utilización masiva por parte de adolescentes de las Redes Sociales Digitales, hacen de éste fenómeno una forma tangible de discriminación sexista. Este estudio, tiene como objetivo analizar la cosificación de las adolescentes en las redes sociales y su influencia en la autoestima de cada joven. Para ello, se han aplicado diferentes escalas a 1087 adolescentes de 11 centros edu...

  20. Insignias digitales como acreditación de competencias en la Universidad

    OpenAIRE

    Borrás Gené, Oriol

    2017-01-01

    Las insignias digitales son archivos en formato PNG cuyo principal objetivo consiste en mostrar algún tipo de logro. Están formados por una imagen y una serie de metadatos que ofrecen todos los datos relativos a la acreditación que representan, normalmente competencias. Ofrece la ventaja de mostrar una información mucho más completa que los clásicos certificados en papel, como por ejemplo asociar evidencias educativas resultantes de la formación asociada a la insignia. Por otro lado al ser un...

  1. Geschäftsmodelle für die digitale Langzeitarchivierung

    OpenAIRE

    Beucke, Daniel

    2010-01-01

    Forschungsdaten liegen zunehmend in digitaler Form vor bzw. werden ausschließlich digital produziert. Die Produktion ist zum einen sehr aufwendig und Kostenintensiv, zum anderen können sie Daten nicht ein zweites Mal erhoben werden. Daraus ergeben sich für Gedächtnisorganisationen wie Bibliotheken, Archive und Museen sowie auch für die Industrie bezogen auf die Möglichkeit der dauerhaften Verfügbarkeit dieser Daten neue Herausforderungen: Sie müssen Strategien und Geschäftsmodelle entwickeln,...

  2. Competencia Digital: Uso y manejo de modelos 3D tridimensionales digitales e impresos en 3D

    Directory of Open Access Journals (Sweden)

    Jose Luis Saorín

    2017-07-01

    Full Text Available El uso y manejo de modelos tridimensionales digitales no está concebido dentro de la competencia digital de los currículos de secundaria y Bachillerato. Sin embargo muchos autores relacionan la competencia digital con el manejo de modelos 3D, el modelado 3D y entornos virtuales tridimensionales (Realidad aumentada, virtual,…. En este artículo se presenta un recurso educativo para facilitar el acceso a contenidos didácticos de carácter tridimensional digital y tangible. Determinadas materias precisan de la comprensión e interpretación de conceptos volumétricos: los recursos didácticos innovadores para la edición, visualización e impresión 3D ofrecen una alternativa a las representaciones 2D en los procesos de enseñanza y aprendizaje. En este artículo se describe la creación de un catálogo escultórico que contempla versiones digitales y tangibles de modelos tridimensionales de las esculturas a través de tecnologías innovadoras de bajo coste como la visualización e impresión 3D. La prueba piloto desarrollada con 15 alumnos de bachillerato recoge una alta valoración de los participantes sobre las tecnologías empleadas.

  3. Il MUDE Piemonte - modello unico digitale per l’edilizia: un progetto organizzativo

    Directory of Open Access Journals (Sweden)

    Livio Mandrile

    2012-12-01

    Full Text Available Le tecnologie dell’informazione e della comunicazione consentono di affrontare la reingegnerizzazione dei processi amministrativi attraverso servizi informatici definiti “di cooperazione applicativa”, aprendo nuove prospettive per semplificare il rapporto fra cittadino e Pubbliche Amministrazioni e agevolare lo scambio di documenti e informazioni. Il MUDE Piemonte – modello unico digitale per l’edilizia - è un sistema informativo realizzato attraverso la collaborazione di tutti i livelli di governo del territorio regionale, che crea un archivio digitale delle pratiche edilizie presentate allo Sportello per l’Edilizia, utilizzando il mezzo telematico per l’interazione fra professionista e Pubblica Amministrazione e l’interscambio informativo fra le banche dati amministrative. Il MUDE Piemonte è un sistema che realizza un ambiente operativo di fruizione / aggiornamento della base di dati territoriali ed amministrativi ad uso di più soggetti ed enti e in costante evoluzione in ragione dell’apporto progettuale offerto da tutti gli attori coinvolti nei procedimenti autorizzativi edilizi.

  4. FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

    Science.gov (United States)

    Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

    2017-06-01

    A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

  5. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  6. Intermediate Frequency Digital Receiver Based on Multi-FPGA System

    Directory of Open Access Journals (Sweden)

    Chengchang Zhang

    2016-01-01

    Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

  7. Architecture exploration of FPGA based accelerators for bioinformatics applications

    CERN Document Server

    Varma, B Sharat Chandra; Balakrishnan, M

    2016-01-01

    This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.

  8. A new FPGA architecture suitable for DSP applications

    International Nuclear Information System (INIS)

    Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan

    2011-01-01

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 x 4.5 mm 2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

  9. FPGA Implementation of a SAR Two-dimensional Autofocus Approach

    Directory of Open Access Journals (Sweden)

    Guo Jiangzhe

    2016-08-01

    Full Text Available For real-time autofocus of defocused images produced by Synthetic Aperture Radar (SAR, the twodimensional autofocus approach proposed in this study is used to correct the residual range cell migration and compensate for the phase error. Next, a block-wise Phase Gradient Autofocus (PGA is used to correct the space-variant phase error. The Field-Programmable Gate Array (FPGA design procedures, resource utilization, processing speed, accuracy, and autofocus are discussed in detail. The system is able to autofocus an 8K × 8K complex image with single precision within 5.7 s when the FPGA works at 200 MHz. The processing of the measured data verifies the effectiveness and real-time capability of the proposed method.

  10. FPGA-based network data transmission scheme for CSNS

    International Nuclear Information System (INIS)

    Wang Xiuku; Zhang Hongyu; Gu Minhao; Xiao Liang

    2012-01-01

    This paper presents the FPGA-based network data transmission solutions for the Data Acquisition System of China Spallation Neutron Source (CSNS). The board with FPGA as the core is used as the hardware platform to realize the transmission of network data. A SOPC system is built and an embedded Linux is transplanted on PowerPC Core. An application program based on Linux has been finished to realize the data transmission via embedded Gigabit Ethernet. The relationship between network transfer performance and packet size was obtained by a test program. In addition, the paper also tried to realize some other ways to transfer data: transplanting PetaLinux on Microblaze, transplanting Lwip protocol stack on PowerPC Core and Microblaze. Their advantages and disadvantages are analyzed and compared in this paper, so that different options and recommendations can be given to meet the actual needs of different projects in the future. (authors)

  11. FPGA-based digital convolution for wireless applications

    CERN Document Server

    Guan, Lei

    2017-01-01

    This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

  12. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Chalimbaud Pierre

    2007-01-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  13. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Pierre Chalimbaud

    2006-12-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  14. HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

    DEFF Research Database (Denmark)

    Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

    2015-01-01

    standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

  15. Teaching Computer Organization and Architecture Using Simulation and FPGA Applications

    OpenAIRE

    D. K.M. Al-Aubidy

    2007-01-01

    This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemente...

  16. FPGA based, modular, configurable controller with fast synchronous optical network

    Energy Technology Data Exchange (ETDEWEB)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

    2006-07-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  17. FPGA based, modular, configurable controller with fast synchronous optical network

    International Nuclear Information System (INIS)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S.

    2006-01-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  18. FPGA applications for single dish activity at Medicina radio telescopes

    Science.gov (United States)

    Bartolini, M.; Naldi, G.; Mattana, A.; Maccaferri, A.; De Biaggi, M.

    FPGA technologies are gaining major attention in the recent years in the field of radio astronomy. At Medicina radio telescopes, FPGAs have been used in the last ten years for a number of purposes and in this article we will take into exam the applications developed and installed for the Medicina Single Dish 32m Antenna: these range from high performance digital signal processing to instrument control developed on top of smaller FPGAs.

  19. Design of a synthesizer for magnetic resonance equipment using FPGA

    International Nuclear Information System (INIS)

    Sonora A

    2006-01-01

    This paper exposes the design of a direct digital synthesizer in FPGA. This desing can generate a sine wave output up to 4MHZ with 3,33 mHz of precision. The frequency is set by 32bit word of phase increment in 350ns. The desing was made for Magnetic Resonance scanners and uses a 97% of logic resources of device. Functions for the synthesizer control are implemented in the same chip

  20. FPGA based mixed-signal circuit novel testing techniques

    International Nuclear Information System (INIS)

    Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

    2013-01-01

    Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

  1. Implementation of Serial and Parallel Bubble Sort on Fpga

    OpenAIRE

    Purnomo, Dwi Marhaendro Jati; Arinaldi, Ahmad; Priyantini, Dwi Teguh; Wibisono, Ari; Febrian, Andreas

    2016-01-01

    Sorting is common process in computational world. Its utilization are on many fields from research to industry. There are many sorting algorithm in nowadays. One of the simplest yet powerful is bubble sort. In this study, bubble sort is implemented on FPGA. The implementation was taken on serial and parallel approach. Serial and parallel bubble sort then compared by means of its memory, execution time, and utility which comprises slices and LUTs. The experiments show that serial bubble sort r...

  2. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    OpenAIRE

    Zulfikar, Z

    2012-01-01

    A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared....

  3. VHDL resolved function based inner communication bus for FPGA

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2017-08-01

    This article discusses a method of building an internal, universal and parametric bus. The solution was designed for a variety of FPGA families and popular VHDL compilers. The algorithm of automatic configuration of address space and methods of receiving and sending addressed data are discussed. The basic solution realized in VHDL language in a behavioral form and chosen examples of practical use of the internal bus are presented in detail.

  4. Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research

    Directory of Open Access Journals (Sweden)

    Burgess Shane C

    2008-04-01

    Full Text Available Abstract Background This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences. Results This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs. Conclusion Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.

  5. DNA Assembly with De Bruijn Graphs Using an FPGA Platform.

    Science.gov (United States)

    Poirier, Carl; Gosselin, Benoit; Fortier, Paul

    2018-01-01

    This paper presents an FPGA implementation of a DNA assembly algorithm, called Ray, initially developed to run on parallel CPUs. The OpenCL language is used and the focus is placed on modifying and optimizing the original algorithm to better suit the new parallelization tool and the radically different hardware architecture. The results show that the execution time is roughly one fourth that of the CPU and factoring energy consumption yields a tenfold savings.

  6. Embedded active vision system based on an FPGA architecture

    OpenAIRE

    Chalimbaud , Pierre; Berry , François

    2006-01-01

    International audience; In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision) is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks,...

  7. Herramienta ALTER. Recursos educativos digitales en red y actividades con herramientas Web 2.0 para aulas hospitalarias

    OpenAIRE

    Serrano Sánchez, José Luis; Torres Soto, Ana

    2012-01-01

    Serrano, J.L. y Torres, A. (2012). Herramienta ALTER. Recursos educativos digitales en red y actividades con herramientas Web 2.0 para aulas hospitalarias. En M.P. Prendes y J.L. Serrano (Coords.), Las TIC en las aulas hospitalarias. Alicante: Marfil.

  8. The current state of FPGA technology in the nuclear domain

    Energy Technology Data Exchange (ETDEWEB)

    Ranta, J.

    2012-07-01

    Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

  9. The current state of FPGA technology in the nuclear domain

    International Nuclear Information System (INIS)

    Ranta, J.

    2012-01-01

    Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

  10. Desain Protokol Suara Sebagai Pengendali Dalam Smart Home Menggunakan FPGA

    Directory of Open Access Journals (Sweden)

    Barlian Henryranu Prasetio

    2017-05-01

    Smart home is a system that uses computers and information technology to control home-like equipment such as windows and lights. The system can be a simple control system to a complex system. Computer / microcontroller based on internet/ethernet network equipped with intelligent system and automation system so as to make home to work automatically. Many computer devices / microcontrollers that can be implemented as a controller in the smart home. Smart home control system in this study using Xilinx xpartan-3e that controls the equipment in the house through LAN (Local Area Networking. This control system communicates using broadcast voice on the local network. The Controller System is designed to be able to transmit a voice signal packet from the microphone input and then send it using the ethernet protocol in the home local network using the FPGA. The FPGA is programmed to transmit and encode data packets, converting digital data into analog data to be able to control the equipment in the home. From the simulation test results using ISIM, it is seen that the system works in realtime. Keywords: smart home, voice, fpga, control

  11. Estimation of channel impulse response and FPGA simulation

    Directory of Open Access Journals (Sweden)

    YU Longjie

    2015-02-01

    Full Text Available Wideband code division multiple access (WCDMA is a 3G wireless communication network.The common pilot channel in downlink of WCDMA provides an effective method to estimate the channel impulse response.In this paper,universal software radio peripheral (USRP is utilized to sample and process WCDMA signal which is emitted by China Unicom base station.Firstly,the received signal is pre-processed with filtering and down-sampling.Secondly,fast algorithm of WCDMA cell search is fulfilled.Thirdly,frequency shift caused by USRP′s crystal oscillator is checked and compensated.Eventually,channel impulse response is estimated.In this paper,MATLAB is used to describe the above algorithm and field programmable gate array (FPGA is used to simulate algorithm.In the process of simulation,pipeline and IP core multiplexing are introduced.In the case of 32 MHz clock frequency,FPGA simulation time is 80.861 ms.Simulation results show that FPGA is able to estimate the channel impulse response quickly and accurately with less hardware resources.

  12. Hardware and Software Integration in Project Development of Automated Controller System Using LABVIEW FPGA

    International Nuclear Information System (INIS)

    Mohd Khairulezwan Abd Manan; Mohd Sabri Minhat; Izhar Abu Hussin

    2014-01-01

    The Field-Programmable Gate Array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows user to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field, hence the name field-programmable. This project developed a control system using LabVIEW FPGA. LabVIEW FPGA is easier where it is programmed by using drag and drop icon. Then it will be integrated with the hardware input and output. (author)

  13. New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie D.; Label, Kenneth A.; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  14. New Developments in FPGA Devices: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  15. New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project

    CERN Document Server

    Mendez, Julian Maxime; Caratelli, Alessandro; Leitao, Pedro Vicente

    2018-01-01

    The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

  16. Registro de actividad eléctrica en la retina de una rata albina empleando una matriz de microelectrodos

    Directory of Open Access Journals (Sweden)

    Edwin Alexander Cerquera

    2015-09-01

    Full Text Available Las matrices de microelectrodos son dispositivos que permiten la detección de potenciales de acción o espigas en poblaciones de células excitables, ofreciendo varias aplicaciones en el campo de las neurociencias y la biología. Este trabajo muestra un protocolo para el registro de espigas en una población de células ganglionares retinales empleando una matriz de microelectrodos. La retina de una rata albina fue extraída y preparada para ser estimulada in vitro con luz led blanca, con el fin de registrar sus espigas evocadas ante estos estímulos. Cada microelectrodo puede registrar espigas de más de una célula ganglionar, razón por la cual se determinó a qué célula pertenece cada espiga aplicando un procedimiento conocido como “clasificación de espigas”. El trabajo permitió obtener el registro de un periodo de estimulación y otro de no estimulación, con el fin de representar los potenciales de acción evocados con luz y los espontáneos. Los registros fueron almacenados para visualizar las espigas de las células ganglionares y poder aplicar la herramienta de clasificación de espigas. De este modo, se almacenan los instantes de tiempo en los cuales cada célula ganglionar registrada generó potenciales de acción. Este trabajo conllevó al establecimiento de un protocolo de experimentación básico enfocado al uso de matrices MEA en el laboratorio de adquisición de potenciales extracelulares de la Universidad Antonio Nariño Sede Bogotá, no sólo para caracterizar los potenciales de acción de células ganglionares retinales, sino también para otro tipo de células que puedan ser estudiadas empleando matrices de microelectrodos.

  17. Economical Implementation of a Filter Engine in an FPGA

    Science.gov (United States)

    Kowalski, James E.

    2009-01-01

    A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be

  18. Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

    Science.gov (United States)

    Du, Hongtao; Qi, Hairong; Szu, Harold H.

    2005-03-01

    Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called jitter effect in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application

  19. Internet de los objetos empleando arduino para la gestión eléctrica domiciliaria

    Directory of Open Access Journals (Sweden)

    Adriana Marcela Vega E.

    2014-03-01

    Full Text Available Rev.esc.adm.neg El presente artículo muestra la importancia de la gestión eléctrica domiciliaria por medio del diseño, desarrollo e implementación de un prototipo de sistema domótico, que permite utilizar de manera remota una bombilla LED a través de las acciones de prender y apagar, según las necesidades del usuario, sin importar en donde se encuentre ubicado, es decir, que su localización geográfica no importa. Para su desarrollo se emplearon elementos de Hardware como el Arduino y de Software como los servicios en la nube de Windows Azure®; con esta aplicación, se pretende observar la interoperabilidad entre un dispositivo ubicado en el hogar y un servidor ubicado en el mundo virtual del Internet. Lo anterior permite hacer un acercamiento a las múltiples modalidades que se pueden desarrollar con el Internet de los objetos y que en un futuro próximo será empleando por las personas de manera permanente en sus residencias.

  20. Paralelización del Algoritmo Criptográfico GOST Empleando el Paradigma de Memoria Compartida

    Directory of Open Access Journals (Sweden)

    Marlis Fulgueira-Camilo

    2015-06-01

    Full Text Available El artículo refiere el proceso de paralelización del algoritmo criptográfico GOST. La investigación realizada persigue como objetivo, reducir el tiempo de ejecución del algoritmo. El estudio no se encuentra enfocado al análisis de fortaleza del algoritmo criptográfico, donde se hace énfasis es en el método empleado para disminuir el tiempo de ejecución de los procesos cifre y descifre. Para ello se realiza un diseño paralelo basado en la metodología de Ian Foster, el cual es aplicado a dos implementaciones usando técnicas como: OpenMP y CUDA. Las comparaciones realizadas teniendo en cuenta, tanto al algoritmo secuencial como las implementaciones paralelas, demuestran una significativa reducción de tiempo, sin importar la técnica empleada. El mejor resultado se logra empleando CUDA.

  1. Bayerische Staatsbibliothek Ludwig-Maximilian Universität München Historisches Seminar /Abteilung geschichtliche Wissenschaften, Projektbereich 'Digitale Tafelwerke Pilotprojekt Digitalisierung Sybel/Sickel: "Kaiserurkunden in Abbildungen"

    Directory of Open Access Journals (Sweden)

    Antonella Ghignoli

    2006-12-01

    Full Text Available Review of Bayerische Staatsbibliothek Ludwig-Maximilian Universität München Historisches Seminar /Abteilung geschichtliche Wissenschaften, Projektbereich 'Digitale Tafelwerke Pilotprojekt Digitalisierung Sybel/Sickel: "Kaiserurkunden in Abbildungen"

  2. Rezension: Digitale Körperinnenwelten. Endoskopische 3D-Animationen zwischen Medien und Populärkultur. von Sven Stollfuß

    Directory of Open Access Journals (Sweden)

    Petra Missomelius

    2015-09-01

    Full Text Available Sven Stollfuß’ Studie über die digitale Darstellung körperlicher Innenwelten bewegt sich zwischen medienwissenschaftlicher Theoriebildung, Bildtheorie und Science and Technology Studies. Petra Missomelius hat rezensiert ...

  3. Profesores, aprendan de los nativos digitales. Propuesta de utilización de sistemas colaborativos en la educación pública

    Directory of Open Access Journals (Sweden)

    Daniel Fajardo

    2012-03-01

    Full Text Available El texto propone cuatro claves primordiales para el uso y desarrollo de las TIC en comunidades educativas. Promueve el uso de plataformas libres como apoyo a todas las materias de bachillerato, a partir de algunas experiencias exitosas en Chile. El autor recomienda que los docentes secundarios se muevan en los mismos espacios digitales que sus alumnos (nativos digitales para promover la cooperación y creatividad lúdica de la enseñanza.

  4. Subjetividades juveniles, expresiones políticas y uso de tecnologías digitales

    Directory of Open Access Journals (Sweden)

    Mónica María Bermúdez Grajales

    2017-05-01

    Full Text Available El presente artículo da cuenta de algunos hallazgos derivados de una revisión documental que tuvo como fin indagar en la relación entre subjetividades juveniles, expresiones políticas y uso de tecnologías digitales. Fueron revisadas 150 investigaciones publicadas a partir del año 2000 hasta el 2014, tanto en el ámbito internacional —Europa y Estados Unidos— como en el nacional. Uno de los principales hallazgos plantea que con las actuales tecnologías digitales se están cultivando prácticas políticas de gran trascendencia, en tanto se produce una comunicación apasionada, multimodal e incidental que logra distanciarse de una política tradicional-representativa, para articularse a los deseos y pulsiones de la subjetividad juvenil contemporánea. Además se plantea que el uso de las tecnologías se integra a propuestas contrahegemónicas en las que la apropiación de lenguajes hipertextuales constituye la des-identificación con una lógica dominante. En tal sentido, los videos, las imágenes, la música, las animaciones, los enlaces y los mensajes de texto se convierten en la construcción de una sintaxis que contribuye a traducir con más convencimiento la emoción, el afecto y el malestar del presente.

  5. FiMAN: SISTEMA COMPUTARIZADO PARA ANÁLISIS DE MOVIMIENTOS DIGITALES

    Directory of Open Access Journals (Sweden)

    Miguel Carballo

    2016-07-01

    Full Text Available La reciente tecnología de dispositivos y sensores infrarrojos han abierto nuevas posibilidades para el desarrollo de software relacionado con el área de análisis de movimientos corporales. Esta tecnología puede ser utilizada en áreas como la salud, la enseñanza, la realidad virtual y aumentada, control de robots y entretenimiento. En este artículo presentamos el desarrollo de FiMAN, un sistema que permite visualizar los movimientos detallados de las manos en tiempo real y en 3D utilizando el dispositivo infrarrojo Leap Motion para la captura de datos, permitiendo la realización de grabaciones y reproducciones de movimientos para su posterior análisis. Para su desarrollo fue necesaria la división modular de los componentes visuales, estructurales, analíticos, estadísticos y de sonido, además de la captura y manipulación de datos. Gracias a su diseño modular, se obtuvo un entorno genérico de desarrollo para aplicaciones especializadas en movimientos digitales. Como Estudio de Caso, se utilizó el sistema al área de la educación musical, específicamente a la enseñanza de la técnica del piano, para lo cual se extendió FiMAN con un teclado virtual y manejo de sonido. El uso real de FiMAN en este escenario, demostró su modularidad y extensibilidad a diferentes áreas relacionadas al análisis de movimientos digitales.

  6. Det digitale imperativ: En epistemologisk bestræbelse [The Digital Imperative: An Epistemological Endeavour

    Directory of Open Access Journals (Sweden)

    Sisse Siggaard Jensen

    2014-12-01

    Full Text Available I denne artikel argumenteres der for, at forskning inden for feltet tredje-bølge digital humaniora er væsentlig for vores forståelse af, hvordan de sociale netværksmediers digitale infrastrukturer og datastrømme – status-opdateringer, selv-profilering, mikro-koordinering, mikro-blogging og vlogging – i stigende grad påvirker menneskelige relationer og ‘the structure of feeling’ (Berry, 2012. Som led i at underbygge dette synspunkt analyseres fire emergente temaer baseret på Facebook-data: Facebook-venner, Events, Self-profilering og Stalking. Analyserne tager afsæt i data, der er tilvejebragt gennem kondensering af design-konceptformuleringer fra 73 unge studerende (alder 20-24 som led i et universitetskursus inden for feltet digital humaniora (2013. To begrebspar er centrale for analyserne: ‘Forbundethed og forbindelser’ (van Dijck, 2013 og ‘synlighed og overvågning’ (Bucher, 2012. Der identificeres en række spændingsfelter mellem interpersonelle normer og påvirkningerne fra Facebook-datastrømme i forhold til: Venskab, troværdighed, ansvarlighed, prestige, selvpromovering og fælles interesser. Det konkluderes, at en væsentlig erkendelsesteoretiske bestræbelse for forskning inden for tredje-bølge digital humaniora må være at producere viden, der kan bidrage til vores individuelle såvel som kollektive forståelse af de mange spændingsfelter, der opstår i datastrømmenes og de menneskelige relationers gensidige påvirkning. Denne bestræbelse er sammenfattet i artiklens titel ‘det digitale imperativ’.

  7. Desarrollo de un cuestionario para estimar las habilidades digitales de estudiantes universitarios

    Directory of Open Access Journals (Sweden)

    Javier Organista-Sandoval

    2017-01-01

    Full Text Available El propósito del artículo es mostrar la ruta metodológica seguida para desarrollar un cuestionario para estimar las habilidades digitales con propósito educativo que tienen los estudiantes de una universidad pública mexicana. Se describe el desarrollo de un cuestionario basado en cuatro dimensiones: manejo de información, de comunicación, de organización y de tecnología portátil. Se recurre a la consulta de expertos para la delimitación de los factores, la elaboración de los reactivos y la estimación de un indicador de univocidad. Se aplica un análisis preliminar basado en modelado estructural de ecuaciones para obtener evidencias de validez de la escala desarrollada. El cuestionario se aplicó al azar a una muestra de 350 estudiantes. Se propuso un modelo conceptual para el constructo de habilidad digital, el cual tuvo la congruencia esperada entre las variables observadas y la estructura propuesta. Tras una primera aplicación se obtuvieron valores aceptables en tres de los índices de bondad de ajuste (RMSEA, GFI y AGFI, con excepción de Chi-cuadrada y se detectaron posibilidades de adecuar la escala con base en los índices de modificación derivados del programa AMOS. La información obtenida permitirá mejorar la escala propuesta. Determinar las habilidades digitales de los estudiantes es un punto de interés actual en la búsqueda de la innovación y eficiencia de las actividades educativas.

  8. Universitarios y redes sociales informativas: Escépticos totales, moderados duales o pro-digitales

    Directory of Open Access Journals (Sweden)

    2017-10-01

    Full Text Available El objetivo del presente trabajo es analizar el uso de las redes sociales informativas como herramienta de empoderamiento social por los universitarios españoles, y su percepción de la universidad como institución que contribuye a la formación de una ciudadanía crítica y activa, al tiempo que les proporciona las pertinentes competencias digitales. La revisión bibliográfica evidencia posibles discrepancias respecto al efecto que tienen las nuevas formas de comunicación digital en el empoderamiento de los jóvenes y en particular de los universitarios, así como la existencia de numerosas cuestiones por aclarar en este escenario digital. A continuación se presenta un análisis tipológico de la percepción de los estudiantes universitarios respecto a las redes sociales informativas, empoderamiento social y el papel de la universidad. A partir de los datos recogidos mediante un cuestionario estructurado de una muestra de 236 estudiantes de Grados de Ciencias Sociales, se realiza un análisis de tipologías con el algoritmo K Medias. Se identifican tres tipos –etiquetados como «escépticos totales», «moderados duales» y «pro-digitales»– significativamente diferentes. Se explica su prevalencia, y su caracterización: perfiles de creencias y conducta relacionadas con dichas creencias. El trabajo concluye con diversas recomendaciones para futuras investigaciones en cuanto a la percepción del universitario sobre el uso de las redes sociales como herramienta de transformación social y el papel de la universidad.

  9. Digitale metoder

    DEFF Research Database (Denmark)

    Birkbak, Andreas; Munk, Anders Kristian

    Digitaliseringen af sociale omgangsformer giver både nye muligheder og udfordringer for samfundsvidenskabelig og humanistisk forskning. Det er blevet relativt enkelt at høste meget store datamængder fra sociale medier og lignende internetteknologier, men det er et åbent spørgsmål, hvad man stille...

  10. Digitale forskydninger

    DEFF Research Database (Denmark)

    Christensen, Hans Dam

    2009-01-01

    En af tidens store kulturelle dagsordner drejer sig om digital tilgængeliggørelse af kulturarv. Fortidens spor dukker op i nye former på nettet - næsten alle kulturinstitutioner arbejder med, og befolkningen har fået helt nye muligheder for at se med og deltage. Digital formidling af kulturarv...

  11. Digitale Vertrauenskulturen

    Directory of Open Access Journals (Sweden)

    Jana Dittmann

    2017-08-01

    Full Text Available Wie sich die Transformation moderner Gesellschaften in den nächsten Jahren fortsetzt, hängt ganz zentral von der Entwicklung, Implementierung und sozialen Kontrolle der GNR-Technologien (der Kombination aus Gen-, Nano- und Robotertechnologie ab. Die Diskussion zur künstlichen Intelligenz, die im letzten Jahrzehnt geführt worden ist, hat mit dem Gebiet der Robotertechnologie gleichsam eine neue Arena gefunden und sich auf dieses Gebiet verlagert. Hier werden jetzt grundlegende, auch pädagogisch zentrale Fragen, wie z.B. die nach einem Personenkonzept, diskutiert (vgl. Richards u.a. 2002. Zentrale Bedenken, die sich auf die mit den neuen Technologien verbundenen Gefahren stützen, sind immer wieder vorgetragen worden (Joy 2000; Moravec 1999. Ohne diese verzweigte Debatte an dieser Stelle rekonstruieren zu wollen, kann doch ein Befund in verallgemeinernder Absicht hervorgehoben werden: In dem Maße, in dem Gesellschaften aufgrund des Einsatzes neuer Technologien einen Komplexitätsschub aufweisen, der sich bis in die Lebenswelten einzelner Menschen hinein auswirkt, rückt ein „Mechanismus“ von Sozialität immer stärker in das Zentrum der Aufmerksamkeit: Vertrauen. Nicht nur aus der hier herangezogenen Perspektive wird diese Ressource prekär. Vielmehr ist seit Beginn der neunzehnhundertneunziger Jahre ein Ansteigen der Publikationen zu dem Thema Vertrauen aus verschiedenen Perspektiven zu konstatieren, und zwar in Soziologie, Pädagogik, Philosophie, Politikwissenschaft und Ökonomie. Vertrauen wird als elementare Voraussetzung sozialer Prozesse gesehen. Wenn Vertrauen aber nicht mehr als selbstverständliche Voraussetzung sozialer Prozesse verstanden werden kann, häufen sich Maßnahmen zur Vertrauensbildung, gerät das Phänomen Vertrauen also in den Fokus der systematischen Reflexion.

  12. Digitale dagsordener

    DEFF Research Database (Denmark)

    Høyrup, Helene

    2009-01-01

    Artiklen indledes med en diskussion af digitaliseringens udfordringer til "bookspace", defineret som printkulturens moderne videnskompleks.  Op mod denne baggrund sætter artiklen diskussionen af aktuelle definitioner af New Literacy som et interdisciplinært felt.  Forbindelser mellem M.A.K. Halli...... primært fokuserer på henholdsvis et sociokulturelt og æstetisk videnssyn.  Afslutningsvis fremfører artiklen, at de to områder burde samarbejde i udviklingen af et transdisciplinært perspektiv omfattende teoretisk viden om medier, som kan kaste lys over begrebet multimodalitet....

  13. Digitale medier

    DEFF Research Database (Denmark)

    Sørensen, Birgitte Holm; Levinsen, Karin

    2013-01-01

    internetbrugere. Ifølge EU-Kids Online (2011) er børn i Danmark og Sverige syv år, når de har deres internetdebut. En rapport fra Medierådet i Sverige, fra 2010, omfattende svenske børn, Småungar & Medier – Fakta om små barns användning och upplevelser av medier, viser, at debutalderen er endnu lavere, nemlig...... brug af sociale medier, så viser en undersøgelse fra Medierådet for Børn og Unge i Danmark, at mere end hvert fjerde barn på 9-10 år har en profil på internettet, og at Facebook er det mest foretrukne (Medierådet for Børn og Unge 2009). Børnene finder det med andre ord vigtigt at omsætte deres læse- og...

  14. Design and demonstration of a multitechnology FPGA for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Hawk, Chris; Toshniwal, Kavita; Beyette, Fred R., Jr.

    2003-11-01

    We present here a novel architecture for a multi-technology field programmabler gate array (MT-FPGA). Implemented with a conventional CMOS VLSI technology the architecture is suitable for prototyping photonic information processing systems. We report here that this new FPGA architecture will enable the design of reconfigurable systems that incorporate technologies outside the traditional electronic domain.

  15. Implementation of a feed-forward artificial neural network in VHDL on FPGA

    NARCIS (Netherlands)

    Dondon, P.; Carvalho, J.; Gardere, R.; Lahalle, P.; Tsenov, G.; Mladenov, V.M.; Reljin, B.; Stankovic, S.

    2014-01-01

    Describing an Artificial Neural Network (ANN) using VHDL allows a further implementation of such a system on FPGA. Indeed, the principal point of using FPGA for ANNs is flexibility that gives it an advantage toward other systems like ASICS which are entirely dedicated to one unique architecture and

  16. Development of a multi-purpose logic module with the FPGA

    International Nuclear Information System (INIS)

    Nanbu, K.; Ishikawa, T.; Shimizu, H.

    2008-01-01

    We have developed a multi-purpose logic module (MPLM) with an FPGA. The internal circuit of this module can be modified easily with the FPGA. This kind of module enables trigger pulse processing for nuclear science. As a first step, the MPLM is used as an event tag generator in experiments with the FOREST detector system. (author)

  17. An FPGA bridge preserving traffing quality of service for on-chip network-based systems

    NARCIS (Netherlands)

    Nejad, A.B.; Escudero Martinez, M.; Goossens, K.G.W.

    2011-01-01

    FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into

  18. Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

    NARCIS (Netherlands)

    Becher, Andreas; Bauer, Florian; Ziener, Daniel; Teich, Jürgen

    2014-01-01

    In this paper, we propose an approach for energy-aware FPGA-based query acceleration for databases on embedded devices. After the analysis of an incoming query, a query-specific hardware accelerator is generated on-the-fly and loaded on the FPGA for subsequent query execution using partial dynamic

  19. Percepción de estudiantes con discapacidad visual sobre sus competencias digitales en una universidad pública del sureste de México

    Directory of Open Access Journals (Sweden)

    Silvia Patricia Aquino Zúñiga

    2016-04-01

    Full Text Available En este artículo nuestro objetivo fue indagar la percepción de estudiantes universitarios con discapacidad visual (ECDV acerca del desarrollo de sus competencias digitales. Participaron en el estudio los diez ECDV inscritos en programas de licenciatura en el ciclo 2014-02. Evaluamos el avance que perciben los estudiantes en competencias digitales relacionadas con el aprendizaje social y colaborativo, la búsqueda y tratamiento de la información, el desarrollo de relaciones interpersonales en el contexto universitario, y el uso de herramientas virtuales y de comunicación social de la universidad. Los resultados sugieren que, a excepción de aquellas referentes a las relaciones interpersonales, los ECDV perciben poco adelanto en sus competencias digitales. Con una prueba Anova de medidas repetidas, determinamos que la percepción de los ECDV sobre las competencias digitales concernientes a las relaciones interpersonales es significativamente mayor que la que reportan en las otras competencias. Concluimos que los ECDV no perciben una mejora en sus competencias digitales, en particular las de aprendizaje social y colaborativo, así como el uso de herramientas digitales.

  20. Multirate Digital Filters Based on FPGA and Its Applications

    International Nuclear Information System (INIS)

    Sharaf El-Din, R.M.A.

    2013-01-01

    Digital Signal Processing (DSP) is one of the fastest growing techniques in the electronics industry. It is used in a wide range of application fields such as, telecommunications, data communications, image enhancement and processing, video signals, digital TV broadcasting, and voice synthesis and recognition. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high performance DSP systems. The focus of this thesis is on one of the basic DSP functions, namely filtering signals to remove unwanted frequency bands. Multi rate Digital Filters (MDFs) are the main theme here. Theory and implementation of MDF, as a special class of digital filters, will be discussed. Multi rate digital filters represent a class of digital filters having a number of attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. This thesis introduces an efficient FPGA realization of a multi rate decimation filter with narrow pass-band and narrow transition band to reduce the frequency sample rate by factor of 64 for noise thermometer applications. The proposed multi rate decimation filter is composed of three stages; the first stage is a Cascaded Integrator Comb (CIC) decimation filter, the second stage is a two-coefficient Half-Band (HB) filter and the last stage is a sharper transition HB filter. The frequency responses of individual stages as well as the overall filter response have been demonstrated with full simulation using MATLAB. The design and implementation of the proposed MDF on FPGA (XILINX Virtex XCV800 BG432-4), using VHSIC Hardware Description Language (VHDL), has been introduced. The implementation areas of the proposed filter stages are compared. Using CIC-HB technique saves 18% of the design area, compared to using six stages HB decimation filters.

  1. Delay model and performance testing for FPGA carry chain TDC

    International Nuclear Information System (INIS)

    Kang Xiaowen; Liu Yaqiang; Cui Junjian Yang Zhangcan; Jin Yongjie

    2011-01-01

    Time-of-flight (TOF) information would improve the performance of PET (position emission tomography). TDC design is a key technique. It proposed Carry Chain TDC Delay model. Through changing the significant delay parameter of model, paper compared the difference of TDC performance, and finally realized Time-to-Digital Convertor (TDC) based on Carry Chain Method using FPGA EP2C20Q240C8N with 69 ps LSB, max error below 2 LSB. Such result could meet the TOF demand. It also proposed a Coaxial Cable Measuring method for TDC testing, without High-precision test equipment. (authors)

  2. IMPLEMENTATION OF SERIAL AND PARALLEL BUBBLE SORT ON FPGA

    Directory of Open Access Journals (Sweden)

    Dwi Marhaendro Jati Purnomo

    2016-06-01

    Full Text Available Sorting is common process in computational world. Its utilization are on many fields from research to industry. There are many sorting algorithm in nowadays. One of the simplest yet powerful is bubble sort. In this study, bubble sort is implemented on FPGA. The implementation was taken on serial and parallel approach. Serial and parallel bubble sort then compared by means of its memory, execution time, and utility which comprises slices and LUTs. The experiments show that serial bubble sort required smaller memory as well as utility compared to parallel bubble sort. Meanwhile, parallel bubble sort performed faster than serial bubble sort

  3. Enhanced Temperature Control Method Using ANFIS with FPGA

    Directory of Open Access Journals (Sweden)

    Chiung-Wei Huang

    2014-01-01

    Full Text Available Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS using a field-programmable gate array (FPGA to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV inductively-coupled plasma- (ICP- type etcher.

  4. Development of Integral Environment in Matlab/Simulink for FPGA

    Directory of Open Access Journals (Sweden)

    Dejan Jokic

    2014-01-01

    Full Text Available In this paper is presented realization of integral environment which consists of software and hardware components for the purpose of programming Altera DE boards. Software component is Toolbox FPGA Real Time which enables simple use of Matlab/Simulink with DSP Builder for the purpose of realization of control structures. Hardware component are Interface cards that make connection of DE board with object of control possible. Simulation and experimental results of DC motor control indicate the usefulness of the proposed concept.

  5. Energy Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Kenn Toft, Jakob; Nannarelli, Alberto

    2014-01-01

    Field Programmable Gate Arrays (FPGAs) based accelerators are very suitable to implement application-specific processors using uncommon operations or number systems. In this work, we design FPGA-based accelerators for two financial computations with different characteristics and we compare...... the accelerator performance and energy consumption to a software execution of the application. The experimental results show that significant speed-up and energy savings, can be obtained for large data sets by using the accelerator at expenses of a longer development time....

  6. FPGA curved track fitter with very low resource usage

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jin-Yuan; Wang, M.; Gottschalk, E.; Shi, Z.; /Fermilab

    2006-11-01

    Standard least-squares curved track fitting process is tailored for FPGA implementation. The coefficients in the fitting matrices are carefully chosen so that only shift and accumulation operations are used in the process. The divisions and full multiplications are eliminated. Comparison in an application example shows that the fitting errors of the low resource usage implementation are less than 4% bigger than the fitting errors of the exact least-squares algorithm. The implementation is suitable for low-cost, low-power applications such as high energy physics detector trigger systems.

  7. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    . Zulfikar

    2012-10-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  8. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    Zulfikar .

    2015-05-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  9. FPGA implementation of adaptive beamforming in hearing aids.

    Science.gov (United States)

    Samtani, Kartik; Thomas, Jobin; Varma, G Abhinav; Sumam, David S; Deepu, S P

    2017-07-01

    Beamforming is a spatial filtering technique used in hearing aids to improve target sound reception by reducing interference from other directions. In this paper we propose improvements in an existing architecture present for two omnidirectional microphone array based adaptive beamforming for hearing aid applications and implement the same on Xilinx Artix 7 FPGA using VHDL coding and Xilinx Vivado ® 2015.2. The nulls are introduced in particular directions by combination of two fixed polar patterns. This combination can be adaptively controlled to steer the null in the direction of noise. The beamform patterns and improvements in SNR values obtained from experiments in a conference room environment are analyzed.

  10. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  11. FPGA Implementation of Video Transmission System Based on LTE

    Directory of Open Access Journals (Sweden)

    Lu Yan

    2015-01-01

    Full Text Available In order to support high-definition video transmission, an implementation of video transmission system based on Long Term Evolution is designed. This system is developed on Xilinx Virtex-6 FPGA ML605 Evaluation Board. The paper elaborates the features of baseband link designed in Xilinx ISE and protocol stack designed in Xilinx SDK, and introduces the process of setting up hardware and software platform in Xilinx XPS. According to test, this system consumes less hardware resource and is able to transmit bidirectional video clearly and stably.

  12. LAPACKrc: Fast linear algebra kernels/solvers for FPGA accelerators

    International Nuclear Information System (INIS)

    Gonzalez, Juan; Nunez, Rafael C

    2009-01-01

    We present LAPACKrc, a family of FPGA-based linear algebra solvers able to achieve more than 100x speedup per commodity processor on certain problems. LAPACKrc subsumes some of the LAPACK and ScaLAPACK functionalities, and it also incorporates sparse direct and iterative matrix solvers. Current LAPACKrc prototypes demonstrate between 40x-150x speedup compared against top-of-the-line hardware/software systems. A technology roadmap is in place to validate current performance of LAPACKrc in HPC applications, and to increase the computational throughput by factors of hundreds within the next few years.

  13. SRF cavity testing using a FPGA Self Excited Loop

    Energy Technology Data Exchange (ETDEWEB)

    Ben-Zvi, I. [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2017-08-30

    Various authors have previously studied the theory and practice of cavity testing, notably an extensive treatment by Powers [1] and Padamsee [2]. The advent of the digital Low Level RF (LLRF) electronics based on Field Programmable Logic Arrays (FPGA) provides various improvements over the rather complex systems used in the past as well as enabling new measurement techniques.In this document we reintroduce a technique that seems to have fallen out of practice in recent times, that is obtaining the coupling constant β through measurements from just one port, the reflected power port, of the directional coupler placed in front of the cavity.

  14. SRF cavity testing using a FPGA Self Excited Loop

    CERN Document Server

    Ben-Zvi, Ilan

    2018-01-01

    This document provides a detailed description of procedures for very-high precision calibration and testing of superconducting RF cavities using digital Low-Level RF (LLRF) electronics based on Field Programmable Gate Arrays (FPGA). The use of a Self-Excited Loop with an innovative procedure for fast turn-on allows the measurement of the forward, reflected and transmitted power from a single port of the directional coupler in front of the cavity, thus eliminating certain measurement errors. Various procedures for measuring the quality factor as a function of cavity fields are described, including a single RF pulse technique. Errors are estimated for the measurements.

  15. Revistas nativas digitales en el ámbito del deporte en España: el caso de MARCA Plus

    Directory of Open Access Journals (Sweden)

    Ignacio LABARGA-ADÁN

    2018-01-01

    Full Text Available Desde su aparición en el verano de 2014, MARCA Plus se ha convertido en un referente para las publicaciones nativas digitales. Prueba de ello es el reconocimiento por parte de Apple como una de las mejores 'apps' para iPad y ganar los 'Digital Magazine Awards' en 2015 y 2016. Este artículo pretende abordar las características de este nuevo formato en el panorama actual de los medios: el de las revistas nativas digitales. La revista objeto de estudio es una de las apuestas de Unidad Editorial por las nuevas tecnologías, habiendo conseguido en tres años un posicionamiento excepcional en el mercado digital. MARCA Plus destaca por su diseño, creatividad, carácter innovador, interactividad y nuevas narrativas audiovisuales, a lo que se suma el ser un soporte ideal para las nuevas tendencias en publicidad.

  16. Diseño de Hardware y Software de Systems on Chip empleando tecnología Xilinx EDK

    Directory of Open Access Journals (Sweden)

    Julio Cadena

    2012-11-01

    Full Text Available El presente artículo resume el proceso empleado para obtener el primer System on Chip (SoC diseñado, desarrollado, y emulado en la Escuela Politécnica del Ejército (ESPE y en el Ecuador. Se demostrará que combinando las ventajas del diseño sobre Field Programable Gate Arrays (FPGAs empleando la reutilización de IP Cores y plataformas, junto al uso de la tecnología de desarrollo Xilinx EDK, se puede diseñar tanto el hardware como el software de un chip de manera rápida y económicamente fiable. Además, se detalla el uso de la metodología Platform Based Design (PBD y del concepto de co-diseño de hardware y software para diseñar las capas de hardware, sistema operativo y aplicación de un chip. La capa de hardware contiene una serie de IP Cores gobernados por un procesador MicroBlaze trabajando dentro de la arquitectura CoreConnect de IBM. Mientras que la capa de sistema operativo está conformada por drivers, librerías y el Sistema Operativo en Tiempo Real (RTOS Xilkernel. Por último, la capa de aplicación tiene la funcionalidad de controlar una planta de temperatura, mediante la selección de dos técnicas de control: ON-OFF o PID. Cabe destacar que el co-diseño se desarrolló considerando un adecuado enfoque conceptual, arquitectural, y metodológico1.

  17. La obtención y proyección de tablas de mortalidad empleando curvas. Spline

    Directory of Open Access Journals (Sweden)

    Alejandro MINA-VALDÉS

    2011-01-01

    Full Text Available Una de las herramientas del análisis numérico es el uso de polinomios de n-ésimo orden para interpolar entre n + 1 puntos, teniéndose casos en donde estas funciones polinómicas pueden llevar a resultados erróneos. Una alternativa es la de aplicar polinomios de orden inferior a subconjuntos de datos. Estos polinomios conectados se llaman funciones de interpolación segmentaria (spline functions. En este artículo se presenta la herramienta que el análisis numérico proporciona como instrumento técnico necesario para llevar a cabo todos los procedimientos matemáticos existentes con base a algoritmos que permitan su simulación o cálculo, en especial, las funciones splines definidas a trozos (por tramos, con interpolación mediante ellas, dando lugar a el ajuste de curvas spline con base en la serie de sobrevivientes lx de una tabla abreviada de mortalidad mexicana, con el fin de desagregarla por edad desplegada, respetando las concavidades que por el efecto de la mortalidad en las primeras edades y en las siguientes se tienen en la experiencia mexicana. También empleando las curvas splines se presentan las simulaciones que permiten obtener escenarios futuros de las series de sobrevivientes lx, que dan lugar a las proyecciones de la mortalidad mexicana para los años 2010-2050, las que generan las tablas completas de mortalidad para hombres y mujeres de dicho periodo, resaltando las diferencias entre sexos y edades de sus probabilidades de supervivencia y las ganancias en las esperanzas de vida.

  18. Rendimiento académico de los alumnos de secundaria que participan en el programa de aulas digitales

    Directory of Open Access Journals (Sweden)

    Jeckson Enrique Loza Arenas

    2017-07-01

    Full Text Available Este estudio analiza el impacto de las aulas digitales en el rendimiento académico en alumnos de educación secundaria de una institución educativa del sector público de Colombia. La metodología, de tipo cuantitativo, empleó un enfoque cuasi-experimental con dos tratamientos: un grupo experimental y uno de control, para establecer la diferencia del rendimiento académico de los alumnos participantes en el programa de aulas digitales con respecto a alumnos que no participan en el mismo. Los instrumentos empleados en este estudio fueron la aplicación de un pre-test y un post-test, una encuesta a los alumnos que integraron las aulas digitales y una encuesta al docente participante. Los resultados muestran que los alumnos participantes en el programa observan una mejora en el rendimiento académico en aspectos como la motivación, atención y participación con respecto a los alumnos que siguen un método de enseñanza tradicional; no ocurre igual en las calificaciones obtenidas ya que no se observa una mejora significativa en comparación con los alumnos no participantes. El uso de las aulas digitales mejora la disposición de los alumnos en el desarrollo de las clases, favoreciendo el trabajo colaborativo; facilitando la comprensión de los temas y dinamizando el desarrollo de las actividades de clase.

  19. Competencias digitales en docentes de la Carrera de Enfermería de la Universidad Técnica de Ambato

    Directory of Open Access Journals (Sweden)

    Diana Nancy Martínez García

    2017-03-01

    Full Text Available Introducción: El aprendizaje electrónico e-learning, incorporó la conectividad a través del Internet acercando el conocimiento y el desarrollo académico por medio de los espacios de aprendizaje virtuales. Del tradicional e-learning a la masificación de los cursos abiertos Massive Open Online Course, se ha revolucionado el mundo educativo en función de la oferta de formación académica abierta y de calidad. Objetivo: Evaluar las competencias digitales de los docentes de la Carrera de Enfermería de la Universidad Técnica de Ambato. Métodos: Se realizó un estudio observacional, descriptivo y retrospectivo con el objetivo de conocer las competencias digitales de los docentes de la Carrera de Enfermería. La población estuvo formada por 30 docentes, a los que se les aplicó un instrumento de evaluación para conocer las competencias digitales que poseían. Resultados: Los docentes estuvieron bien familiarizados con el uso de la Internet (n=19; 63%, y el uso de software educativos (n=8; 27%. El 37% de los docentes utilizó el Internet para el desarrollo de sus clases, el 33% lo utilizó a menudo, mientras que el 2,7% lo utilizó en determinadas ocasiones. Conclusiones: Las competencias digitales de los docentes estuvieron en un nivel medio de pericia, los docentes conocieron y manejaron las herramientas informáticas que integraron a su práctica docente, no obstante se evidenció la necesidad de acompañamiento por parte de personal especializado en el área de tecnologías de la información y la comunicación.

  20. A new FPGA architecture suitable for DSP applications

    Energy Technology Data Exchange (ETDEWEB)

    Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan, E-mail: 071021037@fudan.edu.cn [ASIC and System State Key Laboratory, Fudan University, Shanghai 201203 (China)

    2011-05-15

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 {mu}m CMOS technology successfully. The die size is 6.3 x 4.5 mm{sup 2} with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

  1. Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform

    Directory of Open Access Journals (Sweden)

    Vishwa Seneviratne

    2017-07-01

    Full Text Available Antenna array-based multi-dimensional infinite-impulse response (IIR digital beamformers are employed in a multitude of radio frequency (RF applications ranging from electronically-scanned radar, radio telescopes, long-range detection and target tracking. A method to design 3D IIR beam filters using 2D IIR beam filters is described. A cascaded 2D IIR beam filter architecture is proposed based on systolic array architecture as an alternative for an existing radar application. Differential-form transfer function and polyphase structures are employed in the design to gain an increase in the speed of operation to gigahertz range. The feasibility of practical implementation of a 4-phase polyphase 2D IIR beam filter is explored. A digital hardware prototype is designed, implemented and tested using a ROACH-2 Field Programmable Gate Array (FPGA platform fitted with a Xilinx Virtex-6 SX475T FPGA chip and multi-input analog-to-digital converters (ADC boards set to a maximum sampling rate of 960 MHz. The article describes a method to build a 3D IIR beamformer using polyphase structures. A comparison of technical specifications of an existing radar application based on phased-array and the proposed 3D IIR beamformer is also explained to illustrate the proposed method to be a better alternative for such applications.

  2. An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator.

    Science.gov (United States)

    Wang, Runchun M; Thakur, Chetan S; van Schaik, André

    2018-01-01

    This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF) neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons). This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

  3. An FPGA Implementation of Secured Steganography Communication System

    Directory of Open Access Journals (Sweden)

    Ahlam Fadhil Mahmood

    2013-04-01

    Full Text Available     Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.        In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.      This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secures data transmission applications

  4. An FPGA Implementation of Secured Steganography Communication System

    Directory of Open Access Journals (Sweden)

    Ahlam Mahmood

    2014-04-01

    Full Text Available Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.  In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.  This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secure data transmission applications

  5. FPGA platform for MEMS Disc Resonance Gyroscope (DRG) control

    Science.gov (United States)

    Keymeulen, Didier; Peay, Chris; Foor, David; Trung, Tran; Bakhshi, Alireza; Withington, Phil; Yee, Karl; Terrile, Rich

    2008-04-01

    Inertial navigation systems based upon optical gyroscopes tend to be expensive, large, power consumptive, and are not long lived. Micro-Electromechanical Systems (MEMS) based gyros do not have these shortcomings; however, until recently, the performance of MEMS based gyros had been below navigation grade. Boeing and JPL have been cooperating since 1997 to develop high performance MEMS gyroscopes for miniature, low power space Inertial Reference Unit applications. The efforts resulted in demonstration of a Post Resonator Gyroscope (PRG). This experience led to the more compact Disc Resonator Gyroscope (DRG) for further reduced size and power with potentially increased performance. Currently, the mass, volume and power of the DRG are dominated by the size of the electronics. This paper will detail the FPGA based digital electronics architecture and its implementation for the DRG which will allow reduction of size and power and will increase performance through a reduction in electronics noise. Using the digital control based on FPGA, we can program and modify in real-time the control loop to adapt to the specificity of each particular gyro and the change of the mechanical characteristic of the gyro during its life time.

  6. Optimizing latency in Xilinx FPGA implementations of the GBT

    International Nuclear Information System (INIS)

    Muschter, S; Bohm, C; Baron, S; Soos, C; Cachemiche, J-P

    2010-01-01

    The GigaBit Transceiver (GBT) system has been developed to replace the Timing, Trigger and Control (TTC) system, currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation. This code was optimized for resource utilization, as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

  7. FPGA based algorithms for data reduction at Belle II

    Energy Technology Data Exchange (ETDEWEB)

    Muenchow, David; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liu, Ming; Spruck, Bjoern [II. Physikalisches Institut, Universitaet Giessen (Germany)

    2011-07-01

    Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e{sup +}e{sup -} collider with a design luminosity of 8.10{sup 35}cm{sup -2}s{sup -1}. At Belle II the estimated event rate is {<=}30 kHz. The resulting data rate at the Pixel Detector (PXD) will be {<=}7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for buffering and storing the data. The status of the implementation and performance tests of the memory manager and data reduction algorithm is presented.

  8. FPGA Implementation of a Simple 3D Graphics Pipeline

    Directory of Open Access Journals (Sweden)

    Vladimir Kasik

    2015-01-01

    Full Text Available Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGA-based implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance Computing.

  9. Optimizing latency in Xilinx FPGA implementations of the GBT

    CERN Document Server

    Muschter, S; Bohm, C; Cachemiche, J-P; Baron, S

    2010-01-01

    The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation {[}3]. This code was optimized for resource utilization {[}4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The la...

  10. Optimizing latency in Xilinx FPGA implementations of the GBT

    Science.gov (United States)

    Muschter, S.; Baron, S.; Bohm, C.; Cachemiche, J.-P.; Soos, C.

    2010-12-01

    The GigaBit Transceiver (GBT) [1] system has been developed to replace the Timing, Trigger and Control (TTC) system [2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation [3]. This code was optimized for resource utilization [4], as the GBT protocol is very demanding. It was not, however, optimized for latency — which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board [5] equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

  11. A Sea-of-Gates Style FPGA Placement Algorithm

    Directory of Open Access Journals (Sweden)

    Kalapi Roy

    1996-01-01

    Full Text Available Field Programmable Gate Arrays (FPGAs have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool developed specifically for this architecture.

  12. FPGA Dynamic Power Minimization through Placement and Routing Constraints

    Directory of Open Access Journals (Sweden)

    Deepak Agarwal

    2006-08-01

    Full Text Available Field-programmable gate arrays (FPGAs are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits mapped into 0.12 μm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.

  13. Anti Theft Mechanism Through Face recognition Using FPGA

    Science.gov (United States)

    Sundari, Y. B. T.; Laxminarayana, G.; Laxmi, G. Vijaya

    2012-11-01

    The use of vehicle is must for everyone. At the same time, protection from theft is also very important. Prevention of vehicle theft can be done remotely by an authorized person. The location of the car can be found by using GPS and GSM controlled by FPGA. In this paper, face recognition is used to identify the persons and comparison is done with the preloaded faces for authorization. The vehicle will start only when the authorized personís face is identified. In the event of theft attempt or unauthorized personís trial to drive the vehicle, an MMS/SMS will be sent to the owner along with the location. Then the authorized person can alert the security personnel for tracking and catching the vehicle. For face recognition, a Principal Component Analysis (PCA) algorithm is developed using MATLAB. The control technique for GPS and GSM is developed using VHDL over SPTRAN 3E FPGA. The MMS sending method is written in VB6.0. The proposed application can be implemented with some modifications in the systems wherever the face recognition or detection is needed like, airports, international borders, banking applications etc.

  14. A shared synapse architecture for efficient FPGA implementation of autoencoders.

    Science.gov (United States)

    Suzuki, Akihiro; Morie, Takashi; Tamukoh, Hakaru

    2018-01-01

    This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers' units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.

  15. A Correctness Verification Technique for Commercial FPGA Synthesis Tools

    International Nuclear Information System (INIS)

    Kim, Eui Sub; Yoo, Jun Beom; Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo

    2014-01-01

    Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

  16. A Correctness Verification Technique for Commercial FPGA Synthesis Tools

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2014-10-15

    Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

  17. Sistem national de management al resurselor digitale în stiinta si tehnologie, bazat pe structuri GRID - SINRED

    CERN Document Server

    Banciu, D

    2007-01-01

    Proiectului CEEX, SINRED ?i-a propus s? defineasc? ?i s? realizeze un sistem na?ional unitar de management al resurselor digitale în ?tiin?? ?i tehnologie bazat pe structuri GRID. Partenerii din consor?iu sunt: Universitatea din Bucure?ti; Universitatea Politehnica Bucure?ti; Universitatea Tehnic? din Cluj-Napoca; Institutul National de Informare ?i Documentar; Universitatea de Vest din Timi?oara. Problematica propus? spre rezolvare se circumscrie urm?toarelor obiective specifice: definirea ?i fundamentarea solu?iilor privind constituirea unei biblioteci digitale bazate pe re?eaua bibliotecilor universitare, publice ?i academic;definirea metodelor ?i metodologiilor de creare a unui sistem unitar la nivel na?ional în domeniul info-documentar bazat pe documente digital; analiza ?i testarea modalit??ilor de valorificare a tehnologiilor GRID în domeniul info-documentar;definirea unor proceduri de construire a bazelor de date digitale în acord cu normele ?i reglement?rile na?ionale ?i interna?ionale în domeni...

  18. Un acercamiento a los servicios de información y colecciones de las bibliotecas digitales en México

    Directory of Open Access Journals (Sweden)

    Brenda Cabral Vargas

    2008-07-01

    Full Text Available Realiza un acercamiento a los servicios y colecciones de las bibliotecas digitales en México. A travésde una investigación bibliográfica y de campo, se brinda un panorama sobre la trayectoria que siguióla sociedad de la información con el surgimiento y desarrollo de la electrónica en los servicios deinformación. Se hace un recorrido por los sitios Web de servicios digitales, a través de la recopilaciónde información en cuestionarios y encuestas a los encargados de dichos sitios. El trabajo está estructuradoen tres apartados: en el primero se lleva a cabo la conceptualización teórica sobre la bibliotecadigital (BD; en el segundo se muestran las diferencias del trabajo virtual, tanto para los usuarios comopara sus bibliotecarios, y las interacciones entre ambos y los recursos; y en el tercero se exhibe lasituación de algunos servicios digitales en México, con especial énfasis en el servicio de referencia, asícomo el impacto de éstos en la profesión.

  19. Development of FPGA-based safety-related I and C systems

    Energy Technology Data Exchange (ETDEWEB)

    Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S. [08, Shinsugita-cho, Isogo-ku, Yokohama 235-8523 (Japan); 1, Toshiba-cho, Fuchu, Tokyo 183-8511 (Japan)

    2006-07-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  20. Development of FPGA-based safety-related instrumentation and control systems

    Energy Technology Data Exchange (ETDEWEB)

    Oda, N.; Tanaka, A.; Izumi, M.; Tarumi, T.; Sato, T. [Toshiba Corporation, Isogo Nuclear Engineering Center, Yokohama (Japan)

    2004-07-01

    Toshiba has developed systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related instrumentation and control systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  1. Verification of FPGA-based NPP I and C systems. General approach and techniques

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Reva, Lubov; Siora, Alexander

    2011-01-01

    This paper presents a general approach and techniques for design and verification of Field Programmable Gates Arrays (FPGA)-based Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP). Appropriate regulatory documents used for I and C systems design, development, verification and validation (V and V) are discussed considering the latest international standards and guidelines. Typical development and V and V processes of FPGA electronic design for FPGA-based NPP I and C systems are presented. Some safety-related features of implementation process are discussed. Corresponding development artifacts, related to design and implementation activities are outlined. An approach to test-based verification of FPGA electronic design algorithms, used in FPGA-based reactor trip systems is proposed. The results of application of test-based techniques for assessment of FPGA electronic design algorithms for reactor trip system (RTS) produced by Research and Production Corporation (RPC) 'Radiy' are presented. Some principles of invariant-oriented verification for FPGA-based safety-critical systems are outlined. (author)

  2. An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

    International Nuclear Information System (INIS)

    Jung, Sejin; Kim, Eui-Sub; Yoo, Junbeom; Kim, Jang-Yeol; Choi, Jong Gyun

    2016-01-01

    Highlights: • All direct/indirect COTS SW should be dedicated. • FPGA synthesis tools are important for the safety of new digital I&Cs. • No standards/reports are yet available to deal with the indirect SW – FPGA synthesis tools. • This paper proposes a new evaluation/acceptance process and criteria for indirect SW. - Abstract: FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

  3. Logic qualification of FPGA-based safety-related I and C systems

    International Nuclear Information System (INIS)

    Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

    2009-01-01

    We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

  4. Recursos digitales para el aprendizaje del dibujo tecnológico

    Directory of Open Access Journals (Sweden)

    Gavino, Sergio

    2012-01-01

    Full Text Available El presente trabajo sintetiza el proceso de diseño y creación de medios digitales en distintos formatos: animaciones en formato swf, modelos 3D interactivos en formato skp, java o pdf y la implementación de una aplicación on-line para el dibujo asistido por computadora. Las animaciones en formato swf se utilizan como apoyo para el aprendizaje presencial; en ellas, se modelizan los elementos que constituyen los fundamentos del dibujo tecnológico: el Sistema Monge o Sistema Diédrico, con el dinamismo que su organización implica, permitiendo la interacción del alumno con los elementos del sistema modelizado. Los modelos 3D interactivos pueden orientarse para la visualización de componentes de ingeniería, arquitectura, diseño industrial, etc., haciendo posible ampliar el repertorio de recursos morfológicos y así consolidar el aprendizaje del dibujo tecnológico. La actividad online para el dibujo asistido por computadora está basada en la aplicación Compass and Ruler, de código abierto bajo licencia GNU GPL; a través de esta aplicación los alumnos resuelven diversas ejercitaciones del concepto de isometría, otro contenido del dibujo tecnológico. Los recursos digitales presentados en el presente artículo son desarrollados por la Unidad de Investigación y Desarrollo Grupo de Ingeniería Gráfica Aplicada (UID-GIGA de la Facultad de Ingeniería de la UNLP para las asignaturas Gráfica para Ingeniería (de las especialidades Ingeniería Aeronáutica, Mecánica, Electromecánica y Materiales y Sistemas de Representación “C” (de las especialidades Ingeniería Química, Industrial y Computación.

  5. Big Data en humanidades digitales: de la escritura digital a la “lectura distante”

    Directory of Open Access Journals (Sweden)

    Ricardo Martínez-Gamboa

    2017-01-01

    Full Text Available El florecimiento de la escritura digital ha favorecido la irrupción no solo de las humanidades digitales desde el ámbito de la creación literaria, sino que también su análisis por medio de herramientas computacionales. Estas herramientas han permitido establecer tendencias, patrones, regularidades en los textos, a menudo de manera masiva, que han abierto un campo, el de la interpretación mediada por computadores, que ha generado importantes logros a lo largo de las últimas dos décadas, particularmente en lo que respecta a lo que Moretti denomina la “lectura distante”. En el presente artículo se exponen algunos de estos logros, a saber: estimaciones cuantitativas temáticas de los textos literarios, estimaciones cuantitativas de contenido de los textos literarios, clasificación de textos literarios según sus propiedades semántico-léxicas, determinación de patrones literarios por género y generación, establecimiento de similitudes entre textos literarios diversos, establecimiento de redes de autores contemporáneos. PALABRAS CLAVE: humanidades digitales, lingüística computacional, análisis mediado por computadores, patrones cuantitativos de la literatura. The development of digital writing has allowed not only the emergence of digital humanities from the field of literary creation, but also its analysis using computer tools. These tools have made it possible to establish trends, patterns, and regularities in the texts, often massively, which have opened a field, that of the interpretation mediated by computers, which has generated significant achievements over the past two decades, particularly in what Moretti has called “distant reading”. In this article some of these achievements are presented, namely, quantitative estimates of themes of literary texts, quantitative estimates of content of literary texts, classification of literary texts according to their semantic and lexical properties, the determining of literary

  6. Carry-chain propagation delay impacts on resolution of FPGA-based TDC

    International Nuclear Information System (INIS)

    Dong Lei; Yang Junfeng; Song Kezhu

    2014-01-01

    The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy. (authors)

  7. Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    International Nuclear Information System (INIS)

    Pappas, I; Kalenteridis, V; Vassiliadis, N; Pournara, H; Siozios, K; Koutroumpezis, G; Tatas, K; Nikolaidis, S; Siskos, S; Soudris, D J; Thanailakis, A

    2005-01-01

    A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 μm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools

  8. Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    Energy Technology Data Exchange (ETDEWEB)

    Pappas, I [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Kalenteridis, V [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Vassiliadis, N [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Pournara, H [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siozios, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Koutroumpezis, G [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Tatas, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Nikolaidis, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siskos, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Soudris, D J [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Thanailakis, A [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece)

    2005-01-01

    A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 {mu}m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

  9. High Performance and Energy Efficient Traffic Light Controller Design Using FPGA

    DEFF Research Database (Denmark)

    Pandey, Sujeet; Shrivastav, Vivek Kumar; Sharma, Rashmi

    2017-01-01

    and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER......In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA...

  10. Note: Design of FPGA based system identification module with application to atomic force microscopy

    Science.gov (United States)

    Ghosal, Sayan; Pradhan, Sourav; Salapaka, Murti

    2018-05-01

    The science of system identification is widely utilized in modeling input-output relationships of diverse systems. In this article, we report field programmable gate array (FPGA) based implementation of a real-time system identification algorithm which employs forgetting factors and bias compensation techniques. The FPGA module is employed to estimate the mechanical properties of surfaces of materials at the nano-scale with an atomic force microscope (AFM). The FPGA module is user friendly which can be interfaced with commercially available AFMs. Extensive simulation and experimental results validate the design.

  11. Development of an FPGA-Based Motion Control IC for Caving Machine

    Directory of Open Access Journals (Sweden)

    Chiu-Keng Lai

    2014-03-01

    Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

  12. Cómo una microempresa logró un desarrollo de productos ágil y generador de valor empleando Lean

    OpenAIRE

    Barón Maldonado, Diana Isabel; Rivera Cadavid, Leonardo

    2014-01-01

    El propósito del presente artículo es mostrar un ejemplo de cómo una microempresa puede hacer que su desarrollo de productos sea más ágil, flexible y generador de valor empleando Lean. Se tomaron como referentes el proceso genérico de desarrollo de productos, el proceso de desarrollo tradicional en el sector de confecciones, el sistema Toyota de desarrollo de productos y el antiguo sistema de desarrollo de la empresa. Se destacan el rol del lugar de reunión virtual y el papel del ingeniero je...

  13. Evaluación de la calidad de los registros empleando la auditoría odontológica en una clínica dental docente

    OpenAIRE

    Manrique Guzmán, Jorge A.; Manrique Chávez, Jorge E.; Chávez Reátegui, Beatriz; Manrique Chávez, Carolina B.

    2014-01-01

    Objetivo: Evaluar la calidad de registro o llenado de historias clínicas de pacientes nuevos atendidos en unaClínica Dental Docente durante el período de enero a julio de 2012 empleando la auditoría odontológica comoherramienta sistematizada. Material y métodos: Se tomaron como muestra 140 historias clínicas de pacientesnuevos de las cuales se evaluó la frecuencia y porcentaje de registro de los diferentes aspectos que componenla historia clínica. Resultados: Se encontró que el 78% de las his...

  14. Comportamiento de vigas de sección compuesta con perfiles de acero laminado y losa de concreto empleando conectores de cortante tipo tornillo grado dos (2)

    OpenAIRE

    García Zamora, Alejandro; Molina Herrera, Maritzabel

    2008-01-01

    En el presente artículo, partiendo de un análisis teórico-experimental, se determinan y caracterizan los parámetros de diseño que rigen el comportamiento de las vigas compuestas de perfiles de acero y losa de concreto empleando conectores de cortante tipo tornillo, dado que para esta clase de conector no existe un estudio específico de su comportamiento, además en la actualidad su diseño no está definido en las NSR-98, aunque es uno de los tipos de conectores más empleados en la construcción ...

  15. Comportamiento de vigas de sección compuesta con perfiles de acero laminado y losa de concreto empleando conectores de cortante tipo tornillo grado dos (2)

    OpenAIRE

    García Zamora, Alejandro; Molina Herrera, Maritzabel

    2010-01-01

    En el presente artículo, partiendo de un análisis teórico-experimental, se determinan y caracterizan los parámetros de diseño que rigen el comportamiento de las vigas compuestas de perfiles de acero y losa de concreto empleando conectores de cortante tipo tornillo, dado que para esta clase de conector no existe un estudio específico de su comportamiento, además en la actualidad su diseño no está definido en las NSR-98, aunque es uno de los tipos de conectores más empleados en la construcción ...

  16. Procedimiento para elaborar una lente intraocular monofocal asférica isoplanática y lente obtenida empleando dicho procedimiento

    OpenAIRE

    Barbero, Sergio; Marcos, Susana; Dorronsoro, Carlos; Montejo, Javier; Salazar Salegui, Pedro

    2010-01-01

    Procedimiento para elaborar una lente intraocular monofocal asférica isoplanática y lente obtenida empleando dicho procedimiento. Permite obtener lentes oftálmicas monofocales asféricas isoplanáticas en un rango visual de hasta 25º (preferentemente hasta 10º) de amplitud. El procedimiento comprende las etapas de: 1.- Definición matemática de un modelo de ojo afáquico; 2.- Definición matemática de un modelo de lente intraocular; 3.- Definición matemática de la implantac...

  17. Consideraciones de diseño para la eliminación biológica de fósforo empleando procesos biopelícula

    OpenAIRE

    Castillo de Castro, Pedro; Tejero Monzón, Iñaki

    1999-01-01

    El siguiente artículo es un resumen del estado del arte de la Eliminación Biológica de Fósforo (EBF) empleando procesos de biopelícula. En él se describen minuciosamente los mecanismos que intervienen en la eliminación biológica de este elemento, así como las teorías actualmente aceptadas. Se presentan los procesos biopelícula actualmente desarrollados, así como los consideraciones de diseño para reactores biopelícula, y la forma de trabajo necesaria para conseguir la EBF.

  18. Reconocimiento automático de locutor a través de aprendizaje automático mediante redes neuronales empleando el paquete de software libre Kaldi

    OpenAIRE

    Jiménez Andreu, Rubén

    2017-01-01

    El objetivo del presente Proyecto Fin de Máster es presentar algunas técnicas para reconocimiento de hablante empleando redes neuronales y deep learning. Como referencia se emplean vectors y un modelo universal basado en mezclas gaussianas (GMM-UBM) como método del estado del arte. El proceso de entrenamiento es realizado con la base de datos de audiolibros LibriSpeech. Esta base también se emplea para evaluar los modelos, junto con la de Speakers in the Wild, con locucion...

  19. Cómo una microempresa logró un desarrollo de productos ágil y generador de valor empleando Lean

    OpenAIRE

    Barón Maldonado, Diana Isabel; Rivera Cadavid, Leonardo

    2014-01-01

    El propósito del presente artículo es mostrar un ejemplo de cómo una microempresa puede hacer que su desarrollo de productos sea más ágil, flexible y generador de valor empleando Lean. Se tomaron como referentes el proceso genérico de desarrollo de productos, el proceso de desarrollo tradicional en el sector de confecciones, el sistema Toyota de desarrollo de productos y el antiguo sistema de desarrollo de la empresa. Se destacan el rol del lugar de reunión virtual y el papel del ...

  20. Controlador empotrado en FPGA para Sistema Inteligente de Transporte

    Directory of Open Access Journals (Sweden)

    Alejandro José Cabrera Sarmiento

    2011-11-01

    Full Text Available 1024x768 Normal 0 21 false false false ES X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;} En el presente trabajo se expone la concepción, desarrollo e implementación de un controlador empotrado en un FPGA de Xilinx para ser utilizado en un Sistema Inteligente de Transporte (SIT. La estructura hardware del controlador está basada en la utilización de diversos módulos de propiedad intelectual del sistema de procesamiento MicroBlaze y el soporte de software está basado en la utilización del sistema operativo Petalinux. El controlador empotrado dispone de interfaces Ethernet, USB, UART, SPI e I2C para la comunicación con los diferentes niveles jerárquicos del SIT. Ha sido implementado sobre una placa de desarrollo basada en un FPGA Spartan3E de 1.200 k compuertas, ocupando un 59% de sus recursos configurables. El resto de los recursos disponibles en el FPGA permite, además de la posible actualización del controlador, la implementación hardware de algoritmos que requieren una alta velocidad de procesamiento.

  1. Extending the BEAGLE library to a multi-FPGA platform.

    Science.gov (United States)

    Jin, Zheming; Bakos, Jason D

    2013-01-19

    Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein's pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein's pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple Field Programmable Gate Array (FPGA)-based platform called the Convey HC-1. The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform's peak memory bandwidth and the implementation's memory efficiency, as 2.03 × peak bandwidth × memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a ~40X speedup when compared with BEAGLE's CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE's GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design methodology that emphasizes high memory

  2. Key to Nature: Herramientas digitales para la enseñanza de biodiversidad

    Directory of Open Access Journals (Sweden)

    Castroviejo Bolíbar, Santiago

    2009-06-01

    Full Text Available Key to Nature is a European project that aims to implement digital tools for teaching biodiversity. It involves 14 public and private institutions from 11 European countries, performing different roles, like providing data (Botanical Garden of Madrid, Natural History Museum of London among others, and offering the latest innovations on e-learning (Centre for Usability Research, University of Leuven, Giunti Labs, Italy... The project, with a 4,8 millions budget half of which is financed by the European Community, lasts three years, the first one just through.Key to Nature es un proyecto europeo que tiene como objetivo la implementación de herramientas digitales para la enseñanza de la biodiversidad. Participan en él 14 instituciones públicas y privadas de 11 países europeos, representando diferentes roles, como proveer datos (Real Jardín Botánico de Madrid, Museo de Historia Natural de Londres entre otros, y ofrecer las últimas innovaciones en aprendizaje digital (Centro de Investigación de “Usabilidad” de la Universidad de Lovaina, Bélgica, Giunti Labs, Italia.... El proyecto, de 4,8 millones de presupuesto de los cuales la mitad los financia la Comunidad Europea, tiene una duración de tres años y se encuentra ahora concluyendo el primero.

  3. Mapeo cromático dental a partir de imágenes digitales

    Directory of Open Access Journals (Sweden)

    Josué González Sandoval

    2015-11-01

    Full Text Available El mapeo cromático dental es una técnica que consiste en la estimación de las características ópticas de la dentadura del paciente. Su objetivo es crear un mapa de tonalidades que facilite, al especialista, la elección de resinas o cerámicas a utilizar en la restauración de piezas dentales. Actualmente, el mapeo cromático se realiza comparando directamente la dentadura del paciente contra una guía de colores. Dicho procedimiento se ve afectado por diferentes factores como: condiciones ambientales, características del paciente, percepción del especialista, entre otras, lo que involucra un alto grado de subjetividad. En el presente trabajo se describe un método para el mapeo cromático dental a partir de imágenes digitales. El principal objetivo de esta propuesta es reducir la subjetividad en la selección de los materiales para la reconstrucción de piezas dentales, y en un futuro, desarrollar una herramienta que realice este trabajo automáticamente.

  4. Medienpädagogik und die Digitale Gesellschaft im Spannungsfeld von Regulierung und Teilhabe

    Directory of Open Access Journals (Sweden)

    Stefan Iske

    2014-12-01

    Full Text Available Vor 25 Jahren stellte Tim Berners-Lee sein Konzept eines World Wide Web (WWW vor und legte damit einen der bedeutendsten Grundsteine der digitalen Vernetzung. Was ursprünglich zum Austausch von Informationen und Daten unter Forschenden entworfen wurde, hat sich zu einem umfassenden Kultur- und Bildungsraum entwickelt und ist ein universaler und zentraler Dienst des Internet geworden. Dieser gegenwärtige Status des Internet und des World Wide Web ist der vorläufige Zwischenstand einer historischen Entwicklung, der sowohl Transformationen und Veränderungen als auch Konstanten zugrunde liegen. Nicht erst zum diesjährigen Geburtstag des World Wide Web wird deutlich, dass durch digitale und vernetzte Technologien zentrale Kategorien wie Bildung, Erziehung und Sozialisation berührt werden. Beispielhaft kann auf die aktuellen Debatten über Regulierungsmechanismen im Internet wie auch auf die Enthüllungen Edward Snowdens hingewiesen werden. Aus dem Vorangehenden lassen sich medienpädagogische Fragestellungen ableiten, die zum Beispiel die Handlungsautonomie von Subjekten sowie Möglichkeitsräume der Mitgestaltung von und Teilhabe an Gesellschaft (Winter 2012, Swertz 2014 thematisieren. Zudem sind es Fragen der Mediensozialisation und der Konstruktion von Identität in digital vernetzten Räumen (Jörissen/Marotzki 2008, die sowohl bei der Theoriebildung als auch im Rahmen medienpädagogischer Praxis eine hohe Relevanz besitzen.

  5. Time-delayed chameleon: Analysis, synchronization and FPGA implementation

    Science.gov (United States)

    Rajagopal, Karthikeyan; Jafari, Sajad; Laarem, Guessas

    2017-12-01

    In this paper we report a time-delayed chameleon-like chaotic system which can belong to different families of chaotic attractors depending on the choices of parameters. Such a characteristic of self-excited and hidden chaotic flows in a simple 3D system with time delay has not been reported earlier. Dynamic analysis of the proposed time-delayed systems are analysed in time-delay space and parameter space. A novel adaptive modified functional projective lag synchronization algorithm is derived for synchronizing identical time-delayed chameleon systems with uncertain parameters. The proposed time-delayed systems and the synchronization algorithm with controllers and parameter estimates are then implemented in FPGA using hardware-software co-simulation and the results are presented.

  6. improvement of digital image watermarking techniques based on FPGA implementation

    International Nuclear Information System (INIS)

    EL-Hadedy, M.E

    2006-01-01

    digital watermarking provides the ownership of a piece of digital data by marking the considered data invisibly or visibly. this can be used to protect several types of multimedia objects such as audio, text, image and video. this thesis demonstrates the different types of watermarking techniques such as (discrete cosine transform (DCT) and discrete wavelet transform (DWT) and their characteristics. then, it classifies these techniques declaring their advantages and disadvantages. an improved technique with distinguished features, such as peak signal to noise ratio ( PSNR) and similarity ratio (SR) has been introduced. the modified technique has been compared with the other techniques by measuring heir robustness against differ attacks. finally, field programmable gate arrays (FPGA) based implementation and comparison, for the proposed watermarking technique have been presented and discussed

  7. Fast FPGA Implementation of an Original Impedance Analyser

    Directory of Open Access Journals (Sweden)

    Abdulrahman HAMED

    2011-02-01

    Full Text Available This article describes in detail the design and rapid prototyping of an embedded impedance analyzer. The measurement principle is based on the feedback control of the excitation voltage VD during a fast frequency sweeping. This function is carried out by a high precision synthesizer whose output resistance RG is digitally adjustable. Real and imaginary parts of the dipole impedance are determined from RG and the phase of VD. The digital architecture design uses the hardware-in-the-loop simulation in which the dipole is modeled using an RLC parallel circuit and a Butterworth Van Dyke structure. All digital functions are implemented on a Stratix II FPGA board with a 100 MHz frequency clock. The parameters taken into account are the frequency range (0 to 5 MHz, speed and resolution of the analysis and the quality factor of the resonant dipole. To reduce the analysis duration, the frequency sweeping rate is adjusted in real time.

  8. Real-time particle image velocimetry based on FPGA technology

    International Nuclear Information System (INIS)

    Iriarte Munoz, Jose Miguel

    2008-01-01

    Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach. [es

  9. An FPGA-based rapid prototyping platform for wavelet coprocessors

    Science.gov (United States)

    Vera, Alonzo; Meyer-Baese, Uwe; Pattichis, Marios

    2007-04-01

    MatLab/Simulink-based design flows are being used by DSP designers to improve time-to-market of FPGA implementations. 1 Commonly, digital signal processing cores are integrated in an embedded system as coprocessors. Existing CAD tools do not fully address the integration of a DSP coprocessor into an embedded system design. This integration might prove to be time consuming and error prone. It also requires that the DSP designer has an excellent knowledge of embedded systems and computer architecture details. We present a prototyping platform and design flow that allows rapid integration of embedded systems with a wavelet coprocessor. The platform comprises of software and hardware modules that allow a DSP designer a painless integration of a coprocessor with a PowerPC-based embedded system. The platform has a wide range of applications, from industrial to educational environments.

  10. FPGA implementation of predictive degradation model for engine oil lifetime

    Science.gov (United States)

    Idros, M. F. M.; Razak, A. H. A.; Junid, S. A. M. Al; Suliman, S. I.; Halim, A. K.

    2018-03-01

    This paper presents the implementation of linear regression model for degradation prediction on Register Transfer Logic (RTL) using QuartusII. A stationary model had been identified in the degradation trend for the engine oil in a vehicle in time series method. As for RTL implementation, the degradation model is written in Verilog HDL and the data input are taken at a certain time. Clock divider had been designed to support the timing sequence of input data. At every five data, a regression analysis is adapted for slope variation determination and prediction calculation. Here, only the negative value are taken as the consideration for the prediction purposes for less number of logic gate. Least Square Method is adapted to get the best linear model based on the mean values of time series data. The coded algorithm has been implemented on FPGA for validation purposes. The result shows the prediction time to change the engine oil.

  11. FPGA implementation of advanced FEC schemes for intelligent aggregation networks

    Science.gov (United States)

    Zou, Ding; Djordjevic, Ivan B.

    2016-02-01

    In state-of-the-art fiber-optics communication systems the fixed forward error correction (FEC) and constellation size are employed. While it is important to closely approach the Shannon limit by using turbo product codes (TPC) and low-density parity-check (LDPC) codes with soft-decision decoding (SDD) algorithm; rate-adaptive techniques, which enable increased information rates over short links and reliable transmission over long links, are likely to become more important with ever-increasing network traffic demands. In this invited paper, we describe a rate adaptive non-binary LDPC coding technique, and demonstrate its flexibility and good performance exhibiting no error floor at BER down to 10-15 in entire code rate range, by FPGA-based emulation, making it a viable solution in the next-generation high-speed intelligent aggregation networks.

  12. A minimal SATA III Host Controller based on FPGA

    Science.gov (United States)

    Liu, Hailiang

    2018-03-01

    SATA (Serial Advanced Technology Attachment) is an advanced serial bus which has a outstanding performance in transmitting high speed real-time data applied in Personal Computers, Financial Industry, astronautics and aeronautics, etc. In this express, a minimal SATA III Host Controller based on Xilinx Kintex 7 serial FPGA is designed and implemented. Compared to the state-of-art, registers utilization are reduced 25.3% and LUTs utilization are reduced 65.9%. According to the experimental results, the controller works precisely and steady with the reading bandwidth of up to 536 MB per second and the writing bandwidth of up to 512 MB per second, both of which are close to the maximum bandwidth of the SSD(Solid State Disk) device. The host controller is very suitable for high speed data transmission and mass data storage.

  13. Implementace OFDM demodulátoru v obvodu FPGA

    OpenAIRE

    Solar, Pavel

    2010-01-01

    Diplomová práce stručně rozebírá princip OFDM modulace, možnosti synchronizace a odhadu frekvenční charakteristiky kanálu v OFDM. Je vytvořen jednoduchý model OFDM systému v programu MATLAB. Kombinací schématického popisu a popisu v jazyce VHDL je vytvořen ve vývojovém prostředí ISE behaviorální popis OFDM demodulátoru pro implementaci do FPGA. The master's thesis briefly analyses the principle of OFDM modulation, possibilities of the synchronization and channel estimation in OFDM. The sim...

  14. A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

    Directory of Open Access Journals (Sweden)

    Kevin R. Townsend

    2015-01-01

    Full Text Available On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

  15. Validation of a Real-time AVS Encoder on FPGA

    Directory of Open Access Journals (Sweden)

    Qun Fang Yuan

    2014-01-01

    Full Text Available A whole I frame AVS real-time video encoder is designed and implemented on FPGA platform in this paper. The system uses the structure of the flow calculation, coupled with a dual-port RAM memory between/among the various functional modules. Reusable design and pipeline design are used to optimize various encoding module and to ensure the efficient operation of the pipeline. Through the simulation of ISE software and the verification of Xilinx Vritex-4 pro platform, it can be seen that the highest working frequency can be up to 110 MHz, meeting the requirements of the whole I frame real- time encoding of AVS in CIF resolution.

  16. FPGA Implementation of Real-Time Ethernet for Motion Control

    Directory of Open Access Journals (Sweden)

    Chen Youdong

    2013-01-01

    Full Text Available This paper provides an applicable implementation of real-time Ethernet named CASNET, which modifies the Ethernet medium access control (MAC to achieve the real-time requirement for motion control. CASNET is the communication protocol used for motion control system. Verilog hardware description language (VHDL has been used in the MAC logic design. The designed MAC serves as one of the intellectual properties (IPs and is applicable to various industrial controllers. The interface of the physical layer is RJ45. The other layers have been implemented by using C programs. The real-time Ethernet has been implemented by using field programmable gate array (FPGA technology and the proposed solution has been tested through the cycle time, synchronization accuracy, and Wireshark testing.

  17. FPGA based compute nodes for high level triggering in PANDA

    International Nuclear Information System (INIS)

    Kuehn, W; Gilardi, C; Kirschner, D; Lang, J; Lange, S; Liu, M; Perez, T; Yang, S; Schmitt, L; Jin, D; Li, L; Liu, Z; Lu, Y; Wang, Q; Wei, S; Xu, H; Zhao, D; Korcyl, K; Otwinowski, J T; Salabura, P

    2008-01-01

    PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10 7 /s and data rates of several 100 Gb/s. FPGA based compute nodes with multi-Gb/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Data connectivity is provided via optical links as well as multiple Gb Ethernet ports. The boards will support trigger algorithms such us pattern recognition for RICH detectors, EM shower analysis, fast tracking algorithms and global event characterization. Besides VHDL, high level C-like hardware description languages will be considered to implement the firmware

  18. Implementation of a pulse coupled neural network in FPGA.

    Science.gov (United States)

    Waldemark, J; Millberg, M; Lindblad, T; Waldemark, K; Becanovic, V

    2000-06-01

    The Pulse Coupled neural network, PCNN, is a biologically inspired neural net and it can be used in various image analysis applications, e.g. time-critical applications in the field of image pre-processing like segmentation, filtering, etc. a VHDL implementation of the PCNN targeting FPGA was undertaken and the results presented here. The implementation contains many interesting features. By pipelining the PCNN structure a very high throughput of 55 million neuron iterations per second could be achieved. By making the coefficients re-configurable during operation, a complete recognition system could be implemented on one, or maybe two, chip(s). Reconsidering the ranges and resolutions of the constants may save a lot of hardware, since the higher resolution requires larger multipliers, adders, memories etc.

  19. Method to implement the CCD timing generator based on FPGA

    Science.gov (United States)

    Li, Binhua; Song, Qian; He, Chun; Jin, Jianhui; He, Lin

    2010-07-01

    With the advance of the PFPA technology, the design methodology of digital systems is changing. In recent years we develop a method to implement the CCD timing generator based on FPGA and VHDL. This paper presents the principles and implementation skills of the method. Taking a developed camera as an example, we introduce the structure, input and output clocks/signals of a timing generator implemented in the camera. The generator is composed of a top module and a bottom module. The bottom one is made up of 4 sub-modules which correspond to 4 different operation modes. The modules are implemented by 5 VHDL programs. Frame charts of the architecture of these programs are shown in the paper. We also describe implementation steps of the timing generator in Quartus II, and the interconnections between the generator and a Nios soft core processor which is the controller of this generator. Some test results are presented in the end.

  20. A FPGA Implementation of the CAR-FAC Cochlear Model

    Directory of Open Access Journals (Sweden)

    Ying Xu

    2018-04-01

    Full Text Available This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC cochlear model. The CAR part simulates the basilar membrane's (BM response to sound. The FAC part models the outer hair cell (OHC, the inner hair cell (IHC, and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  1. A FPGA Implementation of the CAR-FAC Cochlear Model.

    Science.gov (United States)

    Xu, Ying; Thakur, Chetan S; Singh, Ram K; Hamilton, Tara Julia; Wang, Runchun M; van Schaik, André

    2018-01-01

    This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  2. Hardware Implementation Of Line Clipping A lgorithm By Using FPGA

    Directory of Open Access Journals (Sweden)

    Amar Dawod

    2013-04-01

    Full Text Available The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance the clipping is still a bottleneck of any graphical system. So its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA. The designed hardware unit consists of two parts : the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the  designed unit is capable of clipping (232524 line segments per second.       

  3. Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping

    Energy Technology Data Exchange (ETDEWEB)

    Ceriani, Marco; Palermo, Gianluca; Secchi, Simone; Tumeo, Antonino; Villa, Oreste

    2013-04-29

    We present a prototype of a multi-core architecture implemented on FPGA, designed to enable efficient execution of irregular applications on distributed shared memory machines, while maintaining high performance on regular workloads. The architecture is composed of off-the-shelf soft-core cores, local interconnection and memory interface, integrated with custom components that optimize it for irregular applications. It relies on three key elements: a global address space, multithreading, and fine-grained synchronization. Global addresses are scrambled to reduce the formation of network hot-spots, while the latency of the transactions is covered by integrating an hardware scheduler within the custom load/store buffers to take advantage from the availability of multiple executions threads, increasing the efficiency in a transparent way to the application. We evaluated a dual node system irregular kernels showing scalability in the number of cores and threads.

  4. Implementation of FPGA-Based Diverse Protection System

    International Nuclear Information System (INIS)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

    2015-01-01

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

  5. Implementation of FPGA-Based Diverse Protection System

    Energy Technology Data Exchange (ETDEWEB)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

    2015-10-15

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

  6. An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator

    Directory of Open Access Journals (Sweden)

    Runchun M. Wang

    2018-04-01

    Full Text Available This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons. This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

  7. FPGA-based prototype of portable environmental radiation monitor

    Energy Technology Data Exchange (ETDEWEB)

    Benahmed, A.; Elkarch, H. [CNESTEN -Centre National de l' Energie des Sciences et Techniques Nucleaires (Morocco)

    2015-07-01

    This new portable radiological environmental monitor consists of 2 main components, Gamma ionization chamber and a FPGA-based electronic enclosure linked to convivial software for treatment and analyzing. The HPIC ion chamber is the heart of this radiation measurement system and is running in range from 0 to 100 mR/h, so that the sensitivity at the output is 20 mV/μR/h, with a nearly flat energy response from 0,07 to 10 MEV. This paper presents a contribution for developing a new nuclear measurement data acquisition system based on Cyclone III FPGA Starter Kit ALTERA, and a user-friendly software to run real-time control and data processing. It was developed to substitute the older radiation monitor RSS-112 PIC installed in CNESTEN's Laboratory in order to improve some of its functionalities related to acquisition time and data memory capacity. As for the associated acquisition software, it was conceived under the virtual LabView platform from National Instrument, and offers a variety of system setup for radiation environmental monitoring. It gives choice to display both the statistical data and the dose rate. Statistical data shows a summary of current data, current time/date and dose integrator values, and the dose rate displays the current dose rate in large numbers for viewing from a distance as well as the date and time. The prototype version of this new instrument and its data processing software has been successfully tested and validated for viewing and monitoring the environmental radiation of Moroccan nuclear center. (authors)

  8. FPGA-based RF spectrum merging and adaptive hopset selection

    Science.gov (United States)

    McLean, R. K.; Flatley, B. N.; Silvius, M. D.; Hopkinson, K. M.

    The radio frequency (RF) spectrum is a limited resource. Spectrum allotment disputes stem from this scarcity as many radio devices are confined to a fixed frequency or frequency sequence. One alternative is to incorporate cognition within a reconfigurable radio platform, therefore enabling the radio to adapt to dynamic RF spectrum environments. In this way, the radio is able to actively sense the RF spectrum, decide, and act accordingly, thereby sharing the spectrum and operating in more flexible manner. In this paper, we present a novel solution for merging many distributed RF spectrum maps into one map and for subsequently creating an adaptive hopset. We also provide an example of our system in operation, the result of which is a pseudorandom adaptive hopset. The paper then presents a novel hardware design for the frequency merger and adaptive hopset selector, both of which are written in VHDL and implemented as a custom IP core on an FPGA-based embedded system using the Xilinx Embedded Development Kit (EDK) software tool. The design of the custom IP core is optimized for area, and it can process a high-volume digital input via a low-latency circuit architecture. The complete embedded system includes the Xilinx PowerPC microprocessor, UART serial connection, and compact flash memory card IP cores, and our custom map merging/hopset selection IP core, all of which are targeted to the Virtex IV FPGA. This system is then incorporated into a cognitive radio prototype on a Rice University Wireless Open Access Research Platform (WARP) reconfigurable radio.

  9. Innovative approach to implementation of FPGA-based NPP instrumentation and control systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Siora, Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper. (author)

  10. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; SIORA Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper

  11. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    Energy Technology Data Exchange (ETDEWEB)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir [Centre for Safety Infrastructure-Oriented Research and Analysis, Kharkov (Ukraine); SIORA Alexander [Research and Production Corporation Radiy, Kirovograd (Ukraine)

    2011-08-15

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper.

  12. A natural-color mapping for single-band night-time image based on FPGA

    Science.gov (United States)

    Wang, Yilun; Qian, Yunsheng

    2018-01-01

    A natural-color mapping for single-band night-time image method based on FPGA can transmit the color of the reference image to single-band night-time image, which is consistent with human visual habits and can help observers identify the target. This paper introduces the processing of the natural-color mapping algorithm based on FPGA. Firstly, the image can be transformed based on histogram equalization, and the intensity features and standard deviation features of reference image are stored in SRAM. Then, the real-time digital images' intensity features and standard deviation features are calculated by FPGA. At last, FPGA completes the color mapping through matching pixels between images using the features in luminance channel.

  13. Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

    Directory of Open Access Journals (Sweden)

    He Chen

    2011-12-01

    Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

  14. Development of an FPGA-based controller for safety critical application

    International Nuclear Information System (INIS)

    Xing, A.; De Grosbois, J.; Sklyar, V.; Archer, P.; Awwal, A.

    2011-01-01

    In implementing safety functions, Field Programmable Gate Arrays (FPGA) technology offers a distinct combination of benefits and advantages over microprocessor-based systems. FPGAs can be designed such that the final product is purely hardware, without any overhead runtime software, bringing the design closer to a conventional hardware-based solution. On the other hand, FPGAs can implement more complex safety logic that would generally require microprocessor-based safety systems. There are now qualified FPGA-based platforms available on the market with a credible use history in safety applications in nuclear power plants. Atomic Energy of Canada (AECL), in collaboration with RPC Radiy, has initiated a development program to define a vigorous FPGA engineering process suitable for implementing safety critical functions at the application development level. This paper provides an update on the FPGA development program along with the proposed design model using function block diagrams for the development of safety controllers in CANDU applications. (author)

  15. A FPGA Approach in a Motorised Linear Stage Remote Controlled Experiment

    Directory of Open Access Journals (Sweden)

    Stamen Gadzhanov

    2013-04-01

    Full Text Available In recent years, an advanced motion control software for rapid development has been introduced by National Instruments, accompanied by innovative and improved FPGA-based hardware platforms. Compared to the well-known standard NI DAQ PCI/USB board solutions, this new approach offers robust stability in a deterministic real-time environment combined with the highest possible performance and re-configurability of the FPGA core. The NI Compact RIO (cRIO Real Time Controller utilises two distinctive interface modes of functionality: Scan and FPGA modes. This paper presents an application of a motion control flexible workbench based on the FPGA module, and analyses the advantages and disadvantages in comparison to another approach - the LabVIEW NI SoftMotion module run in scan interface mode. The workbench replicates real industrial applications and is very useful for experimentation with Brushless DC/ Permanent Magnet Synchronous motors and drives, and feedback devices.

  16. Timing measurements of some tracking algorithms and suitability of FPGA's to improve the execution speed

    CERN Document Server

    Khomich, A; Kugel, A; Männer, R; Müller, M; Baines, J T M

    2003-01-01

    Some of track reconstruction algorithms which are common to all B-physics channels and standard RoI processing have been tested for execution time and assessed for suitability for speed-up by using FPGA coprocessor. The studies presented in this note were performed in the C/C++ framework, CTrig, which was the fullest set of algorithms available at the time of study For investigation of possible speed-up of algorithms most time consuming parts of TRT-LUT was implemented in VHDL for running in FPGA coprocessor board MPRACE. MPRACE (Reconfigurable Accelerator / Computing Engine) is an FPGA-Coprocessor based on Xilinx Virtex-2 FPGA and made as 64Bit/66MHz PCI card developed at the University of Mannheim. Timing measurements results for a TRT Full Scan algorithm executed on the MPRACE are presented here as well. The measurement results show a speed-up factor of ~2 for this algorithm.

  17. Dynamic Reconfiguration Of FPGA Nodes In A Distributed Computing System: A Preliminary Investigation

    National Research Council Canada - National Science Library

    Nixon, Patrick

    2002-01-01

    This report results from a contract tasking Trinity College, Dublin to investigate a specialized portion of a heterogeneous information system, specifically, Field Programmable Gate Array (FPGA)-based nodes...

  18. Advanced Image Processing Package for FPGA-Based Re-Programmable Miniature Electronics

    National Research Council Canada - National Science Library

    Ovod, Vladimir I; Baxter, Christopher R; Massie, Mark A; McCarley, Paul L

    2005-01-01

    .... An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical background...

  19. Rad-Hard and ULP FPGA with "Full" Functionality, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

  20. A FPGA-based architecture for real-time image matching

    Science.gov (United States)

    Wang, Jianhui; Zhong, Sheng; Xu, Wenhui; Zhang, Weijun; Cao, Zhiguo

    2013-10-01

    Image matching is a fundamental task in computer vision. It is used to establish correspondence between two images taken at different viewpoint or different time from the same scene. However, its large computational complexity has been a challenge to most embedded systems. This paper proposes a single FPGA-based image matching system, which consists of SIFT feature detection, BRIEF descriptor extraction and BRIEF matching. It optimizes the FPGA architecture for the SIFT feature detection to reduce the FPGA resources utilization. Moreover, we implement BRIEF description and matching on FPGA also. The proposed system can implement image matching at 30fps (frame per second) for 1280x720 images. Its processing speed can meet the demand of most real-life computer vision applications.

  1. Fuzzy Controller Design Using FPGA for Photovoltaic Maximum Power Point Tracking

    OpenAIRE

    Basil M Hamed; Mohammed S. El-Moghany

    2012-01-01

    The cell has optimum operating point to be able to get maximum power. To obtain Maximum Power from photovoltaic array, photovoltaic power system usually requires Maximum Power Point Tracking (MPPT) controller. This paper provides a small power photovoltaic control system based on fuzzy control with FPGA technology design and implementation for MPPT. The system composed of photovoltaic module, buck converter and the fuzzy logic controller implemented on FPGA for controlling on/off time of MOSF...

  2. Direct Measurement of Power Dissipated by Monte Carlo Simulations on CPU and FPGA Platforms

    OpenAIRE

    Albicocco, Pietro; Papini, Davide; Nannarelli, Alberto

    2012-01-01

    In this technical report, we describe how power dissipation measurements on different computing platforms (a desktop computer and an FPGA board) are performed by using a Hall effectbased current sensor. The chosen application is a Monte Carlo simulation for European option pricing which is a popular algorithm used in financial computations. The Hall effect probe measurements complement the measurements performed on the core of the FPGA by a built-in Xilinxpower monitoring system.

  3. Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Jain, Vishal; Sharma, Rashmi

    2017-01-01

    In this work, we are going to analyze the effect of main supply voltage, auxiliary supply voltage, local voltage of different power bank, and supply voltage in GTX transceiver and BRAM on power dissipation of our FIR design using Verilog during implementation on 28nm FPGA. We have also taken three.......33%, 86%, 90.67%, 65.33%, 52%, and 48.67% reduction in IO power dissipation of FIR Filter design on CSG324 package of Artix-7 FPGA family....

  4. Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

    2012-01-01

    This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

  5. Investigation of Electromagnetic Signatures of a FPGA Using an APREL EM-ISIGHT System

    Science.gov (United States)

    2015-12-01

    shelf (COTS) field- programmable gate array (FPGA) at the optimized factor levels established from the DOE and varying the programmed signal. This...signature using APREL’s EM-ISight automated system is hypothesized to be a novel way to accomplish this task. Research Questions The research...a field programmable gate array (FPGA) is the circuit board utilized for testing the inherent electromagnetic signature. Every device produces an

  6. A Design Methodology for Efficient Implementation of Deconvolutional Neural Networks on an FPGA

    OpenAIRE

    Zhang, Xinyu; Das, Srinjoy; Neopane, Ojash; Kreutz-Delgado, Ken

    2017-01-01

    In recent years deep learning algorithms have shown extremely high performance on machine learning tasks such as image classification and speech recognition. In support of such applications, various FPGA accelerator architectures have been proposed for convolutional neural networks (CNNs) that enable high performance for classification tasks at lower power than CPU and GPU processors. However, to date, there has been little research on the use of FPGA implementations of deconvolutional neural...

  7. FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

    Directory of Open Access Journals (Sweden)

    Swapnil Mhaske

    2017-01-01

    Full Text Available We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

  8. FPGA hardware acceleration for high performance neutron transport computation based on agent methodology - 318

    International Nuclear Information System (INIS)

    Shanjie, Xiao; Tatjana, Jevremovic

    2010-01-01

    The accurate, detailed and 3D neutron transport analysis for Gen-IV reactors is still time-consuming regardless of advanced computational hardware available in developed countries. This paper introduces a new concept in addressing the computational time while persevering the detailed and accurate modeling; a specifically designed FPGA co-processor accelerates robust AGENT methodology for complex reactor geometries. For the first time this approach is applied to accelerate the neutronics analysis. The AGENT methodology solves neutron transport equation using the method of characteristics. The AGENT methodology performance was carefully analyzed before the hardware design based on the FPGA co-processor was adopted. The most time-consuming kernel part is then transplanted into the FPGA co-processor. The FPGA co-processor is designed with data flow-driven non von-Neumann architecture and has much higher efficiency than the conventional computer architecture. Details of the FPGA co-processor design are introduced and the design is benchmarked using two different examples. The advanced chip architecture helps the FPGA co-processor obtaining more than 20 times speed up with its working frequency much lower than the CPU frequency. (authors)

  9. Design Verification Enhancement of FPGA-based Plant Protection System Trip Logics for Nuclear Power Plant

    International Nuclear Information System (INIS)

    Ahmed, Ibrahim; Jung, Jae Cheon; Heo, Gyun Young

    2016-01-01

    As part of strengthening the application of FPGA technology and find solution to its challenges in NPPs, international atomic energy agency (IAEA) has indicated interest by joining sponsorship of Topical Group on FPGA Applications in NPPs (TG-FAN) that hold meetings up to 7th times until now, in form of workshop (International workshop on the application of FPGAs in NPPs) annually since 2008. The workshops attracted a significant interest and had a broad representation of stakeholders such as regulators, utilities, research organizations, system designers, and vendors, from various countries that converge to discuss the current issues regarding instrumentation and control (I and C) systems as well as FPGA applications. Two out of many technical issues identified by the group are lifecycle of FPGA-based platforms, systems, and applications; and methods and tools for V and V. Therefore, in this work, several design steps that involved the use of model-based systems engineering process as well as MATLAB/SIMULINK model which lead to the enhancement of design verification are employed. The verified and validated design output works correctly and effectively. Conclusively, the model-based systems engineering approach and the structural step-by-step design modeling techniques including SIMULINK model utilized in this work have shown how FPGA PPS trip logics design verification can be enhanced. If these design approaches are employ in the design of FPGA-based I and C systems, the design can be easily verified and validated

  10. A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

    Science.gov (United States)

    Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

    2015-10-01

    Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

  11. La construcción colaborativa de proyectos como metodología para adquirir competencias digitales

    Directory of Open Access Journals (Sweden)

    María Pérez Mateo

    2014-01-01

    Full Text Available Actualmente presenciamos una etapa de importantes cambios como consecuencia de la emergencia de las tecnologías de la información y la comunicación (TIC. La educación superior ejerce un papel clave para ayudar a los estudiantes a adquirir las competencias que les permitan desenvolverse en los entornos académico y profesional. Entre éstas, las vinculadas a las TIC y los procesos de colaboración se consideran claves. La finalidad del presente estudio es analizar la percepción de los estudiantes a fin de evidenciar cómo la construcción colaborativa de un proyecto digital facilita la adquisición de las competencias digitales. Para ello, se aborda el planteamiento metodológico de la asignatura «Competencias TIC» de la Universitat Oberta de Catalunya, la cual se desarrolla a través de un proyecto colaborativo en red organizado en cuatro fases: inicio, estructuración, desarrollo y conclusión y cierre. Mediante una investigación evaluativa se triangulan datos de naturaleza cuantitativa y cualitativa provenientes de un cuestionario. Los resultados muestran la evolución en la propuesta metodológica de la asignatura a la vez que ponen de manifiesto cómo el proyecto digital en equipo facilita la adquisición de las competencias digitales, destacando concretamente las vinculadas al trabajo en equipo en red y la actitud digital. Las conclusiones refuerzan la importancia de los procesos CSCL, la necesidad de trabajar propuestas pedagógicas para la adquisición de competencias digitales.

  12. Relatos digitales: activando las competencias comunicativa, narrativa y digital en la formación inicial del profesorado

    Directory of Open Access Journals (Sweden)

    María Esther del Moral

    2016-01-01

    Full Text Available Los relatos digitales constituyen una técnica narrativa con gran potencial educativo al adoptar fórmulas creativas que integran información multiformato e instrumentos tecnológicos para comunicar ideas. Esta investigación evalúa el nivel de competencia comunicativa, narrativa y digital ligado al diseño de relatos en entornos digitales, alcanzado por estudiantes del Grado de Maestro de Primaria (N=143 -tras participar en una experiencia de creación colaborativa-, utilizando una rúbrica integrada por 28 indicadores: 12 relacionados con la competencia comunicativa (comunicación escrita y oral, 6 con la narrativa, y otros 10 específicos con la digital. Los resultados evidencian que si bien presentan gran destreza con las tecnologías, casi un tercio registra niveles medio-bajos en la competencia comunicativa. Se detectan dificultades en la elaboración y adaptación del guión escrito de los relatos al registro elegido -pobre vocabulario y precaria puntuación-, junto a limitaciones en la dicción al locutar los diálogos, no logrando imprimir expresividad al relato. Respecto a la competencia narrativa, solo un 40% muestra originalidad al resolver las tramas y construir personajes. Sin duda, este tipo de experiencias innovadoras ofrece un escenario idóneo para desarrollar habilidades narrativas y creativas en contextos digitales, y brinda numerosas oportunidades para la formación de los futuros docentes.

  13. Uso de redes sociales digitales entre estudiantado universitario: Comunicación, socialización y colaboración

    OpenAIRE

    Marini Munguía, Verónica; Jácome Ávila, Nancy; López González, Rocío

    2017-01-01

    Este artículo describe resultados sobre el uso de redes sociales digitales en actividades de comunicación, socialización y colaboración. Es parte de una investigación en proceso, cuyo propósito es analizar el uso que le da el estudiantado universitario a los dispositivos digitales portátiles (DDP) –laptop, tableta y teléfono inteligente–. Para recolectar la información se aplicó un cuestionario diseñado en el marco del proyecto Brecha digital entre estudiantes y profesores de la Universidad V...

  14. Contenidos educativos digitales que promueven la integración efectiva de las tecnologías de la información y comunicación

    OpenAIRE

    Manso, Micaela; Garzón, Magdalena; Rodríguez, Cecilia; Pérez, Paula

    2011-01-01

    Este estudio cualitativo indagó la relación que existe entre la calidad de los contenidos educativos digitales y la calidad de la implementación que los docentes hacen de esos contenidos educativos. Se utilizaron 10 cualidades basadas en TPACK y el Marco de Enseñanza para la Comprensión (EpC) para analizar la calidad de ambos. Además, se seleccionaron 3 contenidos educativos digitales y se realizaron entrevistas a 6 docentes, 34 estudiantes secundarios y 3 diseñadores de proyectos TIC en Méx...

  15. Inclusión digital de los estudiantes adultos que acceden a la universidad: análisis de sus actitudes y competencias digitales

    OpenAIRE

    M. Teresa PADILLA-CARMONA; Magdalena SUÁREZ-ORTEGA; María Fe SÁNCHEZ-GARCÍA

    2016-01-01

    Esta investigación se propone identificar las actitudes y competencias de los estudiantes adultos en relación con el uso de las TIC, con especial atención al uso de plataformas digitales de aprendizaje y redes sociales (Web 2.0). Asimismo, evalúa la incidencia de algunas variables sociodemográficas (género y edad) en el uso estas herramientas y en la autopercepción de los estudiantes sobre sus competencias digitales. Se ha realizado un estudio tipo encuesta con una muestra de 3...

  16. Diseño de una estrategia para el análisis didáctico de contenidos digitales en anatomía osteo-muscular

    OpenAIRE

    Gamboa Latorre, Lina Fernanda

    2014-01-01

    Este artículo propone una estrategia fundamentada teóricamente en el aprendizaje significativo para orientar el análisis didáctico de los contenidos digitales en anatomía osteo-muscular, asignatura que es requisito curricular en las carreras de la salud. Para el estudio de la asignatura, docentes y estudiantes utilizan recursos tradicionales y emergentes. Parte de los recursos emergentes son los contenidos digitales, modalidades de tecnologías de la información y comunicaciones (TIC) disponib...

  17. Formación digital de profesores. Una revisión del tema con énfasis en los modelos de competencias/literacidades digitales

    Directory of Open Access Journals (Sweden)

    Gonzalo Abio

    2017-03-01

    Full Text Available En este trabajo de cuño teórico-reflexivo, se discuten algunos factores que influyen en el uso de las tecnologías en las escuelas y se focaliza en las competencias que necesita el profesor para un trabajo integrado y efectivo apoyado por las tecnologías digitales. Con ese objetivo, se lleva a cabo una revisión bibliográfica sobre algunos modelos de competencias/literacidades digitales con énfasis en el profesor. Por último, se brindan algunos comentarios sobre las necesidades de formación digital de los profesores.

  18. Toma de medidas usando fotografías digitales: Repaso experimental a procedimientos existentes, posibles fuentes de error, reproductividad del método y usos potenciales

    OpenAIRE

    Bustos-Pérez, Guillermo

    2016-01-01

    El uso de medios digitales para el análisis arqueológico está a la orden del día. Un ejemplo es el uso de fotografías digitales para la obtención de medidas en diferentes objetos. Se presenta aquí un repaso al procedimiento de medida de filos en lascas publicado por Eren et al., (2008), una experiencia de reproductividad del método, y una ampliación experimental de sus potenciales usos para el análisis de industria lítica. Los resultados muestran que se trata de un procedimient...

  19. Implementación de certificados y firmas digitales para sistemas de información transaccionales en una empresa gubernamental

    OpenAIRE

    Espol; Palomeque Avila, John Guillermo

    2015-01-01

    Esta tesis trata de un ámbito teórico, conceptos de organización, tipos de organizaciones y sus procesos, significado de sistemas de información en los cuales se involucra la firma digital; y permite conocer detalles de certificados digitales, firmas digitales, el uso, los organismos relacionados y leyes. Contiene el análisis de procesos diseñados de una organización de gobierno para implementar el procedimiento de legalización de documentos mediante el uso de firma digital. Guayaquil ...

  20. Tribus digitales en las aulas universitarias Digital Tribes in the University Classrooms

    Directory of Open Access Journals (Sweden)

    Andrés Palacios Picos

    2010-03-01

    Full Text Available Se ha extendido el discurso que afirma que los profundos cambios en las TIC experimentados en la última década han modificado también radicalmente el aprendizaje de nuestros estudiantes universitarios, considerados todos ellos nativos digitales. En este artículo se sostiene, sin embargo, que dichos cambios no son tan inmediatos, automáticos o beneficiosos como el discurso dominante sobre la bondad de las TIC pretende hacernos creer, y que dan lugar a múltiples y variadas situaciones intermedias que caracterizan la actual enseñanza universitaria. Utilizando las valoraciones de tres cuestionarios tipo Likert sobre los procesos de información y comunicación en tres entornos diferenciados (una plataforma virtual de enseñanza aprendizaje, Moodle, Tuenti, como ejemplo de red social, y las aulas presenciales y mediante técnicas multivariantes (análisis factorial y de conglomerados se encuentran cuatro segmentos de estudiantes: alumnado optimista o pro-TIC, alumnado pesimista o anti-TIC, alumnado apático y alumnado neutral. La presencia de dichos segmentos de estudiantes nos permite concluir que, aunque la presencia del ordenador en las aulas universitarias forma ya parte del imaginario colectivo, tal vez se esté sobrevalorando tanto el impacto de las TIC en la educación superior como las competencias digitales de los alumnos, y que esta falsa percepción de la realidad puede beneficiar a los vendedores de tecnología, pero no a la innovación metodológica, que sólo se podrá conseguir mediante la necesaria reflexión desde postulados educativos.The discourse stating that the profound changes in ICT of the last decade have also radically altered the way our students learn, and that they can all now be considered digital natives, is increasingly prevalent. However, this paper argues that these changes are not as immediate, automatic or beneficial as the dominant political and technological discourse on the benefits of ICT would have us

  1. Hacia el desarrollo y utilización de repositorios digitales de acceso abierto en el contexto educativo

    OpenAIRE

    Lafuente, Guillermo Javier; Filippi, José Luis; Lafuente, Gustavo

    2014-01-01

    El proyecto busca definir las bases teóricas, administrativas y técnicas para la creación, organización y desarrollo de un Repositorio Digital de Acceso Abierto en el Contexto Educativo. Por consiguiente, es de interés poder definir un marco conceptual para el desarrollo de Repositorios Digitales de contenido educativo, principalmente orientado al contexto universitario. Pero que dicho marco sirva para la construcción de repositorios de características similares. Se trata por lo tanto, de ...

  2. Estudio preliminar. Patologías digitales más frecuentes en el pie de la bailaora de flamencoe

    OpenAIRE

    José Manuel Castillo López; Joaquín Pérez Rendón; Cristina Algaba Guisado

    2010-01-01

    Este estudio tiene como objetivos, en primer lugar, dar a conocer las principales deformidades digitales de los pies, asociadas -por su alta incidencia- a la práctica profesional del baile flamenco femenino. Así como, poner de manifiesto la necesidad de llevar a cabo estudios de mayor magnitud para determinar si existe una relación estadísticamente significativa entre la práctica del baile flamenco con las deformidades y patologías podológicas descritas, y la importancia de la investigación e...

  3. Dispositivo de efectos digitales para guitarra eléctrica controlado por Arduino y mando a distancia

    OpenAIRE

    Pan Pérez-Vivancos, Luis Manuel

    2016-01-01

    El presente proyecto implementa el diseño, cálculo y la construcción de un equipo de efectos digitales para guitarra eléctrica, programados en una tarjeta de DSP controlada por un Arudino UNO y comandado por infrarrojos. Se estudian los diferentes tipos de efectos, se analizan diferentes configuraciones de hardware y sus limitaciones y se cons- truye físicamente un equipo plenamente funcional. Para ello se han empleado los siguientes programas de diseño: PsPice (Simular la adap- taci...

  4. Impacto de las tecnologías digitales en la descentralización del sistema escolar

    OpenAIRE

    San Martín Alonso, Ángel; Peirats Chacón, José

    2014-01-01

    Nuestro objetivo es indagar en la compleja relación entre las tecnologías digitales en los centros escolares y las políticas de descentralización, así como en las implicaciones del modelo pedagógico resultante. Los referentes teóricos se inscriben en el campo de la «nueva gestión pública» que pone el énfasis en la aplicación de indicadores, evaluaciones, regulaciones y aprendizajes autodirigidos como instrumentos del «management» de las organizaciones. ¿En qué medida estas políticas influyen ...

  5. Repositorios institucionales digitales: Análisis comparativo entre SEDICI (Argentina y Kérwá (Costa Rica

    Directory of Open Access Journals (Sweden)

    Juan Carlos Sandí Delgado

    2017-01-01

    Full Text Available Este trabajo tiene como objetivo comparar dos repositorios institucionales digitales a nivel internacional para encontrar convergencias y divergencias con respecto al manejo y la operación de los datos, información y contenidos. Además, contribuye a ampliar el panorama y conocimiento con respecto a la importancia e impacto de los repositorios digitales en las Instituciones de Educación Superior (IES. Los repositorios en estudio corresponden al Servicio de Difusión de la Creación Intelectual (SEDICI, repositorio institucional central de la Universidad Nacional de La Plata (UNLP, Argentina y Kérwá, repositorio institucional principal de la Universidad de Costa Rica (UCR, Costa Rica. Para responder al objetivo de investigación, se desarrolló un análisis metodológico cualitativo. La información se recolectó a través de la aplicación de un cuestionario a las personas responsables de la gestión administrativa de ambos repositorios y una exploración bibliográfica de documentos en formato electrónico, como artículos publicados en congresos, revistas internacionales, entre otros. El análisis se realizó acorde a los siguientes criterios y características: representación de recursos, interoperabilidad, normalización, visibilidad, preservación, entre otros. Se concluyó que los repositorios institucionales digitales se han convertido en una tendencia de innovación para las IES, ya que utilizan y promueven herramientas tecnológicas para producir cambios significativos con respecto al uso y manejo de la información. Asimismo, los repositorios digitales analizados convergen en aspectos como: software, metadatos, números normalizados, representación de recursos, accesibilidad, identificador, derechos de autor, depósito de contenidos, buscadores y preservación. Divergen en interoperabilidad, proceso de digitalización, depósito remoto, visibilidad, licenciamiento y divulgación.

  6. Desarrollo de competencias digitales a través del aprendizaje activo en contextos universitarios con ambientes m-learning

    OpenAIRE

    Agila Palacios, Martha Vanessa

    2015-01-01

    El objetivo de esta investigación es analizar el desarrollo de competencias digitales en estudiantes universitarios de modalidad abierta y a distancia, con experiencia en el uso de la tableta digital como herramienta de estudio, con la integración de aprendizaje activo en ambientes m-learning, con el fin de determinar el impacto del uso de las tecnologías móviles y la identificación de enfoques pedagógicos y didácticos de calidad para mejorar los aprendizajes.

  7. Catálogo hipertextual de traducciones anónimas al castellano (CHTAC). Un nuevo proyecto de Humanidades Digitales

    OpenAIRE

    Borsari, Elisa; Calvo Tello, José

    2013-01-01

    Son muchos los proyectos de Humanidades Digitales que en los últimos años se han llevado a cabo en el ámbito de la literatura y lengua españolas: sin embargo no se encuentra aún disponible en red un recurso en el ámbito de la traducción que quiera o pueda ofrecer una catalogación exhaustiva y unificada de todas las traducciones medievales al castellano. A partir de estas premisas y con el fin de paliar su falta, nace la idea de la creación de CHTAC. Catálogo Hipertextual de Traducciones Anóni...

  8. La lectura en formatos digitales en el Chile actual: nuevas prácticas y viejas desigualdades

    Directory of Open Access Journals (Sweden)

    Cristóbal Moya

    2017-01-01

    Full Text Available En el presente artículo se caracteriza la fisionomía de la lectura en formatos digitales, especialmente en comparación con los impresos. Para esto se analiza la lectura en formatos digitales de cuatro materiales de lectura en el Chile actual (libros, revistas, periódicos e historietas a partir del Estudio de Comportamiento Lector 2014. Las prácticas lectoras son analizadas en cuanto prácticas culturales más amplias, lo que permite dar cuenta de la afinidad existente entre prácticas lectoras y determinados grupos sociales. En particular, se examinan las implicancias de ser un “lector omnívoro” en términos de formatos digitales e impresos. Se encuentra que los “lectores omnívoros” corresponden a perfiles lectores de posiciones sociales aventajadas en términos de educación e ingresos del hogar. Además, los omnívoros son quienes exhiben una mayor disposición a leer distintos materiales y en distintos formatos. Finalmente, se evidencia que existe una reproducción intergeneracional de la desigual disposición a leer en formatos digitales a partir del análisis de la educación de los padres. PALABRAS CLAVE: lectura digital en Chile, prácticas lectoras en Chile, lectura y distinción social, omnivorismo lector. In this article the main features of the format of digital reading are presented, particularly in comparison with print. In order to carry out this aim, the reading in digital format of four reading materials in contemporary Chile (books, magazines, newspapers and comics is analyzed drawing on the Estudio de Comportamiento Lector 2014 (Study of Reading Behavior. Reading practices are analyzed as broader cultural practices, which allows to establish links between reading practices and certain social groups. Particularly, the implications of being an ‘omnivore reader’ are examined, considering digital and print formats. Results show that ‘omnivore readers’ correspond to reading profiles of advantaged social

  9. Competencias digitales en docentes de la Carrera de Enfermería de la Universidad Técnica de Ambato

    OpenAIRE

    Diana Nancy Martínez García

    2017-01-01

    Introducción: El aprendizaje electrónico e-learning, incorporó la conectividad a través del Internet acercando el conocimiento y el desarrollo académico por medio de los espacios de aprendizaje virtuales. Del tradicional e-learning a la masificación de los cursos abiertos Massive Open Online Course, se ha revolucionado el mundo educativo en función de la oferta de formación académica abierta y de calidad. Objetivo: Evaluar las competencias digitales de los docentes de la Carrera de Enferm...

  10. Enseñar con tecnologías digitales en la universidad

    Directory of Open Access Journals (Sweden)

    Carlos Marcelo García

    2015-07-01

    Full Text Available Esta investigación tiene por objetivo analizar el nivel de uso que de las tecnologías hace el profesorado universitario, interesándose tanto por la frecuencia de uso de ellas, como por el tipo de actividades de aprendizaje en las que se utilizan. Los problemas de investigación se centraron en: ¿qué tipos de actividades de aprendizaje con tecnologías diseñan los docentes universitarios?, ¿qué tipo de tecnologías utilizan los docentes en el diseño de su enseñanza?, ¿cuál es el nivel de uso de las tecnologías digitales en los diseños del aprendizaje del profesorado universitario? Hemos diseñado el Inventario de Actividades de Aprendizaje con Tecnologías en la Universidad que fue respondido por 941 docentes andaluces. A través de él hemos identificado el tipo y frecuencia de uso que de la tecnología hace el profesorado universitario en sus materias al tiempo que hemos estudiado las actividades de aprendizaje que predominan en sus diseños del aprendizaje. Los resultados revelan una pobre integración de tecnologías en los procesos de enseñanza-aprendizaje los cuales se constituyen, esencialmente, de actividades de aprendizaje centradas en el docente. Hemos identificado cuatro perfiles diferenciados de docentes en función del nivel de uso que hacen de las TIC. De los cuatro, el perfil que mayor número de docentes agrupa es el que hace referencia a un uso poco frecuente de la tecnología; son docentes que emplean escasamente la tecnología y esta es de una gama muy reducida.

  11. Los docentes de la Generación Z y sus competencias digitales

    Directory of Open Access Journals (Sweden)

    Francisco José Fernández Cruz

    2016-01-01

    Full Text Available La mera presencia de recursos tecnológicos en los centros y las altas capacidades de los alumnos de la «Generación Tecnológica» o «Generación Z», no son suficientes para desarrollar en los alumnos la competencia digital. La clave fundamental viene determinada por las competencias tecnológicas y pedagógicas de los docentes. En este trabajo, se pretende analizar el nivel de competencias en TIC de los profesores de Primaria y Secundaria estableciendo un marco competencial de referencia adaptado al ámbito educativo español, utilizando como base los estándares establecidos por la UNESCO en el año 2008 y reformulados en el año 2011. Para ello, se realizó un cuestionario que permitió establecer el perfil de formación docente en TIC del profesorado de la muestra (80 colegios y 1.433 profesores de la Comunidad de Madrid, para estudiar las características del profesorado mejor formado para el desarrollo de la competencia digital que establece el Ministerio de Educación de España. Los resultados muestran una alarmante diferencia entre las competencias que debieran tener los profesores para desarrollar la competencia digital en sus alumnos y la que verdaderamente tienen. Las competencias digitales del profesorado son muy relevantes en el desarrollo de procedimientos de aprendizaje que introduzcan las tecnologías como herramientas al servicio de la educación y este estudio nos permitirá tomar decisiones en política de formación inicial y a lo largo de la carrera profesional del profesorado.

  12. Vidas de aprendizaje conectadas: Jóvenes digitales en espacios escolares y comunitarios

    Directory of Open Access Journals (Sweden)

    Ola Erstad

    2013-03-01

    Full Text Available Aunque la mayoría de los estudios sobre el aprendizaje hablan de las experiencias intra-institucionales, nuestro interés se centra en el seguimiento de las trayectorias de aprendizaje individuales a través de distintos dominios. Las investigaciones sobre el uso de los diferentes medios por los jóvenes en el entorno extraescolar muestran cómo las prácticas aplicadas en el uso de medios digitales difieren de las prácticas en el entorno escolar, tanto en forma como en contenido. El reto principal actualmente consiste en encontrar formas de entender las interconexiones y la creación de redes entre estos dos mundos de la vida, tal y como las experimentan los jóvenes. Aquí los elementos importantes son los conceptos adaptados como contexto, trayectorias e identidad, relacionados con las redes de actividades. Presentamos datos del «proyecto sobre vidas de aprendizaje» actualmente en curso en una comunidad multicultural de Oslo. Nos centraremos especialmente en los alumnos de educación secundaria post obligatoria que cursan estudios de Medios y Comunicación. Con un enfoque etnográfico, nos centraremos en la forma en que se construyen y se negocian las identidades del alumno en distintos tipos de relaciones de aprendizaje. Los datos incluyen datos generados por los investigadores (entrevistas, observaciones a través de vídeos, anotaciones de campo y datos generados por los participantes (fotografías, diarios, mapas.

  13. Kundenfokus: Startpunkt für die digitale Transformation bei Stadtwerken

    Science.gov (United States)

    Fett, Perry; Küller, Philipp

    Big Data, Internet der Dinge, Mobile Computing und soziale Medien - die modernen Informationstechnologien durchdringen den Alltag der meisten Menschen und lösen hierdurch eine digitale Transformation aus. Im Unternehmenskontext manifestiert sich die Digitalisierung durch eine neue Qualität der wissensbasierten Entscheidungsunterstützung und der Automatisierung bzw. Autonomisierung der Geschäftsprozesse. Für Stadtwerke gilt es nun, die Chancen der Digitalisierung zu ihren Gunsten zu nutzen. Ein Startpunkt könnte hierbei sein, wie Stadtwerke zukünftig mit ihren Kunden interagieren. Ausgelöst durch die Liberalisierung der Märkte rückt der Kunde heute stärker in den Mittelpunkt - die Energiewirtschaft steht nun vor der Herausforderung, dem Wettbewerb einen Schritt voraus zu sein und dem Kunden ein absolut positives Kundenerlebnis (Customer Experience) sowohl als Maßnahme zur Kundenbindung als auch zum Kundenaufbau zu bieten. Das vorliegende Kapitel zeigt hierfür die Erfolgskriterien für die gelungene Etablierung des Kundenfokus im eigenen Unternehmen auf. Mit dem Customer-Focus-Cycle-Modell von Fujitsu, angelehnt an den Deming-Kreislauf, wird ein allgemeingültiger Ansatz für ein mögliches Vorgehen beim Aufbau des Kundenfokus vorgestellt. Die sechs Phasen werden dabei anhand praktischer Beispiele erläutert und geben zudem Hinweise zu Methoden und Tools. Aus dem vorgestellten "Werkzeugkasten" wird ferner die Customer-Journey-Methode im Detail erläutert. Weiter soll das präsentierte Reifegradmodell Unternehmen dabei unterstützen, den eigenen Status quo festzustellen und die persönlichen Ziele auf dem Weg zur kundenzentrierten Organisation festzulegen.

  14. Semivariogram Analysis of Bone Images Implemented on FPGA Architectures.

    Science.gov (United States)

    Shirvaikar, Mukul; Lagadapati, Yamuna; Dong, Xuanliang

    2017-03-01

    Osteoporotic fractures are a major concern for the healthcare of elderly and female populations. Early diagnosis of patients with a high risk of osteoporotic fractures can be enhanced by introducing second-order statistical analysis of bone image data using techniques such as variogram analysis. Such analysis is computationally intensive thereby creating an impediment for introduction into imaging machines found in common clinical settings. This paper investigates the fast implementation of the semivariogram algorithm, which has been proven to be effective in modeling bone strength, and should be of interest to readers in the areas of computer-aided diagnosis and quantitative image analysis. The semivariogram is a statistical measure of the spatial distribution of data, and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. A semi-variance, γ ( h ), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h . Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O ( n 2 ) Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current

  15. Spatial and color clustering on an FPGA-based computer system

    Science.gov (United States)

    Leeser, Miriam E.; Kitaryeva, Natalya V.; Crisman, Jill D.

    1998-10-01

    We are mapping an image clustering algorithm onto an FPGA- based computer system. Our approach processes raw pixel data in the red, green, blue color space and generates an output image where all pixels are assigned to classes. A class is a group of pixels with similar color and location. These classes are then used as the basis of further processing to generate tags. The tags, in turn, are used to generate queries for searching libraries of digital images. We run our image tagging approach on an FPGA-based computing machine. The image clustering algorithm is run on an FPGA board, and only the classified image is communicated to the host PC. Further processing is run on the host. Our experimental system consists of an Annapolis Wildforce board with four Xilinx XC4000 chips and a PCI connection to a host PC. Our implementation allows the raw image data to stay local to the FPGAs, and only the class image is communicated to the host PC. The classified pixels are then used to generate tags which can be used for searching a digital library. This approach allows us to parallelize the image processing on the FPGA board, and to minimize the data handled by the PC. FPGA platforms are ideally suited for this sort of initial processing of images. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures, keeping unnecessary data off the host processor. The result of our algorithm is a reduction by up to a factor of six in the number of bits required to represent each pixel. The output data is passed to the host PC, thus reducing the processing and memory resources needed compared to handling the raw data on the PC. The process of generating tags of images is simplified by first classifying pixels on an FPGA-based system, and digital library search is accelerated.

  16. An FPGA- Based General-Purpose Data Acquisition Controller

    Science.gov (United States)

    Robson, C. C. W.; Bousselham, A.; Bohm

    2006-08-01

    System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems

  17. Design and FPGA implementation for MAC layer of Ethernet PON

    Science.gov (United States)

    Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao

    2004-04-01

    Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.

  18. Electronic readout for THGEM detectors based on FPGA TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Koenigsmann, Kay; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany); Collaboration: COMPASS-II RICH upgrade Group

    2013-07-01

    In the framework of the RD51 programme the characteristics of a new detector design, called THGEM, which is based on multi-layer arrangements of printed circuit board material, is investigated. The THGEMs combine the advantages for covering gains up to 10{sup 6} in electron multiplication at large detector areas and low material budget. Studies are performed by extending the design to a hybrid gas detector by adding a Micromega layer, which significantly improves the ion back flow ratio of the chamber. With the upgrade of the COMPASS experiment at CERN a MWPC plane of the RICH-1 detector will be replaced by installing THGEM chambers. This summarizes to 40k channels of electronic readout, including amplification, discrimination and time-to-digital conversion of the anode signals. Due to the expected hit rate of the detector we design a cost-efficient TDC, based on Artix7 FPGA technology, with time resolution below 100 ps and sufficient hit buffer depth. To cover the large readout area the data is transferred via optical fibres to a central readout system which is part of the GANDALF framework.

  19. Cryogenic loss monitors with FPGA TDC signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Warner, A.; Wu, J.; /Fermilab

    2011-09-01

    Radiation hard helium gas ionization chambers capable of operating in vacuum at temperatures ranging from 5K to 350K have been designed, fabricated and tested and will be used inside the cryostats at Fermilab's Superconducting Radiofrequency beam test facility. The chamber vessels are made of stainless steel and all materials used including seals are known to be radiation hard and suitable for operation at 5K. The chambers are designed to measure radiation up to 30 kRad/hr with sensitivity of approximately 1.9 pA/(Rad/hr). The signal current is measured with a recycling integrator current-to-frequency converter to achieve a required measurement capability for low current and a wide dynamic range. A novel scheme of using an FPGA-based time-to-digital converter (TDC) to measure time intervals between pulses output from the recycling integrator is employed to ensure a fast beam loss response along with a current measurement resolution better than 10-bit. This paper will describe the results obtained and highlight the processing techniques used.

  20. Automation of FBTR fuel pin inspection using FPGA

    International Nuclear Information System (INIS)

    Khare, K.M.; Pai, Siddhesh; Pant, Brijesh; Sendhil Raja, S.; Gupta, P.K.

    2011-01-01

    A non-contact metrology system for inspection of FBTR fuel pins has been developed. The system consists of a stepper motors driven mechanism for orientation and positioning of FBTR fuel pin, a telecentric imaging system, absolute linear encoder with 0.1 μm resolution and a Field Programmable Gate Array (FPCA) based controller. The FBTR pin assembly is telecentrically illuminated from bottom by a red LED and its shadow graph is imaged using a CCD camera through telecentric imaging lens system. For system control and automation we have used a FPGA that has integrated soft picoblaze processor, X-θ axis motion controller, custom IPs for encoder data acquisition, synchronization circuit, RS485 interface along with other l/Os. Using the Graphical User Interface (GUI) on a PC the system is initialized at home position and the controller provides the trigger signal for start of data acquisition of CCD camera. CCD image of pin and the corresponding X-θ information is captured. After the acquisition of one set of images, the imaging module is moved with a step size pre-programmed to ensure proper stitching of acquired images. The GUI is programmed to analyze these X-θ Images to calculate the required parameters of the fuel pin like the diameter variation, pitch and bow. The details of the instrument and measurements made with it will be presented. (author)

  1. FPGA implementation of image dehazing algorithm for real time applications

    Science.gov (United States)

    Kumar, Rahul; Kaushik, Brajesh Kumar; Balasubramanian, R.

    2017-09-01

    Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K_BRAM, 97 DSP_48, 6508 FFs and 8159 LUTs.

  2. FPGA-accelerated algorithm for the regular expression matching system

    Science.gov (United States)

    Russek, P.; Wiatr, K.

    2015-01-01

    This article describes an algorithm to support a regular expressions matching system. The goal was to achieve an attractive performance system with low energy consumption. The basic idea of the algorithm comes from a concept of the Bloom filter. It starts from the extraction of static sub-strings for strings of regular expressions. The algorithm is devised to gain from its decomposition into parts which are intended to be executed by custom hardware and the central processing unit (CPU). The pipelined custom processor architecture is proposed and a software algorithm explained accordingly. The software part of the algorithm was coded in C and runs on a processor from the ARM family. The hardware architecture was described in VHDL and implemented in field programmable gate array (FPGA). The performance results and required resources of the above experiments are given. An example of target application for the presented solution is computer and network security systems. The idea was tested on nearly 100,000 body-based viruses from the ClamAV virus database. The solution is intended for the emerging technology of clusters of low-energy computing nodes.

  3. An FPGA computing demo core for space charge simulation

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Huang, Yifei

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  4. Functional verification of dynamically reconfigurable FPGA-based systems

    CERN Document Server

    Gong, Lingkan

    2015-01-01

    This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric.  Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an i...

  5. Implementation of Wireless Communications Systems on FPGA-Based Platforms

    Directory of Open Access Journals (Sweden)

    Voros NS

    2007-01-01

    Full Text Available Wireless communications are a very popular application domain. The efficient implementation of their components (access points and mobile terminals/network interface cards in terms of hardware cost and design time is of great importance. This paper describes the design and implementation of the HIPERLAN/2 WLAN system on a platform including general purpose microprocessors and FPGAs. Detailed implementation results (performance, code size, and FPGA resources utilization are presented. The main goal of the design case presented is to provide insight into the design aspects of a complex system based on FPGAs. The results prove that an implementation based on microprocessors and FPGAs is adequate for the access point part of the system where the expected volumes are rather small. At the same time, such an implementation serves as a prototyping of an integrated implementation (System-on-Chip, which is necessary for the mobile terminals of a HIPERLAN/2 system. Finally, firmware upgrades were developed allowing the implementation of an outdoor wireless communication system on the same platform.

  6. An FPGA computing demo core for space charge simulation

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; Huang, Yifei; /Fermilab

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  7. Fast neuromimetic object recognition using FPGA outperforms GPU implementations.

    Science.gov (United States)

    Orchard, Garrick; Martin, Jacob G; Vogelstein, R Jacob; Etienne-Cummings, Ralph

    2013-08-01

    Recognition of objects in still images has traditionally been regarded as a difficult computational problem. Although modern automated methods for visual object recognition have achieved steadily increasing recognition accuracy, even the most advanced computational vision approaches are unable to obtain performance equal to that of humans. This has led to the creation of many biologically inspired models of visual object recognition, among them the hierarchical model and X (HMAX) model. HMAX is traditionally known to achieve high accuracy in visual object recognition tasks at the expense of significant computational complexity. Increasing complexity, in turn, increases computation time, reducing the number of images that can be processed per unit time. In this paper we describe how the computationally intensive and biologically inspired HMAX model for visual object recognition can be modified for implementation on a commercial field-programmable aate Array, specifically the Xilinx Virtex 6 ML605 evaluation board with XC6VLX240T FPGA. We show that with minor modifications to the traditional HMAX model we can perform recognition on images of size 128 × 128 pixels at a rate of 190 images per second with a less than 1% loss in recognition accuracy in both binary and multiclass visual object recognition tasks.

  8. FPGA-based prototype storage system with phase change memory

    Science.gov (United States)

    Li, Gezi; Chen, Xiaogang; Chen, Bomy; Li, Shunfen; Zhou, Mi; Han, Wenbing; Song, Zhitang

    2016-10-01

    With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

  9. Neue Möglichkeiten in der archäologischen arbeit durch den Einsatz digitales Bildauswertung und photogrammetrischer Messtechniken

    Directory of Open Access Journals (Sweden)

    Jan Wesbuer

    2005-01-01

    Full Text Available Die digitale Bildbearbeitung und die digitale Photogrammetrie haben in den letzten Jahren, neben vielen anderen Gebieten, die Dokumentation von Ausgrabungsstätten beeinflusst. Die Photogrammetrie hat ihren Ursprung in der Vermessungskunde. Sie wird heutzutage in vielen Bereichen der Ingenieurwissenschaften eingesetzt und hat somit viele Schnittbereiche zu angrenzenden wissenschaftlichen Gebieten. In der Archäologie hat sie daher die Möglichkeit, in vielen Bereichen die herkömmliche Geodäsie zu erweitern bzw. neue Möglichkeiten der Visualisierung zu schaffen oder bei der Bildauswertung zu helfen.Durch die Bildbearbeitung ist es heutzutage möglich, schnell und vor Ort die Dokumentation vorzunehmen. Mit ihrer Hilfe können z.B. nicht orthogonale Aufnahmen perspektivisch entzerrt werden, so dass in ihnen wieder gemessen werden kann.Der Artikel unterteilt sich in 3 Bereiche:• als erstes werden die Möglichkeiten der digitalen Bildbearbeitung bzw. Auswertung von Photos dargestellt.• danach wird auf die photogrammetrische Auswertung und Vermessung von Ausgrabungsstätten eingegangen. • und zuletzt werden einige Visualisierungsmöglichkeiten gezeigt, die mit Hilfe der photogrammetrischen Auswertung und 3DModellerstellung realisiert werden können.

  10. Mercados municipales y tecnologías digitales: entre el e-comercio y nuevas formas de convivialidad

    Directory of Open Access Journals (Sweden)

    Juan Robles

    2014-01-01

    Full Text Available Los escaparates virtuales, la venta online y la puesta en valor de los circuitos de producción cortos y agroecológicos a través de eficaces políticas de comunicación en las redes sociales son ejemplos de lo que hoy están usando muchos pequeños comerciantes para poner en valor su expertise tradicional, paradójicamente basada en la cercanía y el trato directo. En este artículo analizamos el papel de las tecnologías digitales en la re-significación y re-activación del pequeño comercio y de los mercados de abastos tradicionales. El uso de tecnologías digitales pone en entredicho la visión de Internet como agente de desterritorialización y de creación de una cultura global, ante la presencia de nuevas formas de localización basadas en la emergencia de nuevas formas de convivialidad, agroecología y alimentación saludable.

  11. Mejoramiento de la productividad de la línea de extrusión de la empresa CEDAL, empleando la metodología "Six Sigma"

    OpenAIRE

    Garcés Muñoz, Luis Alfredo

    2016-01-01

    El presente trabajo tuvo como objetivo el mejoramiento de la productividad del proceso de extrusión en la empresa CEDAL, empleando la metodología “Six Sigma”. Para esto, se analizó la situación actual del proceso de extrusión por medio de 4 indicadores claves de desempeño o KPI. Se concluyó, que el KPI que mide la cantidad de rechazos de material no conforme, obtuvo una mejora en la productividad después de la implementación de las fases DMAMC, al tener una línea base del indicador en el mes ...

  12. Deshidratación de etanol empleando líquidos iónicos de naturaleza prótica

    OpenAIRE

    Acosta Cordero, L.; Pérez Ones, O.; Zumalacárregui de Cárdenas, L.

    2017-01-01

    En este trabajo se presenta el estudio experimental de la deshidratación de etanol empleando líquidos iónicos de naturaleza prótica, con el objetivo de determinar un líquido iónico prótico efectivo en este proceso de separación. Para ello se sintetizaron tres líquidos iónicos (formiato de 2-hidroxietilamonio, lactato de2-hidroxietilamonio y propionato de 2-hidroxietilamonio) y se determinaron sus propiedades críticas y densidad apartir de métodos de contribución de grupos. Además se confirmó ...

  13. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    Energy Technology Data Exchange (ETDEWEB)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I. [Research and Production Corporation Radiy, 29 Geroev Stalingrada Str., Kirovograd 25006 (Ukraine); Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A., E-mail: marketing@radiy.co [Center for Safety Infrastructure-Oriented Research and Analysis, 37 Astronomicheskaya Str., Kharkiv 61085 (Ukraine)

    2010-10-15

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY{sup TM} platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY{sup TM} platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY{sup TM} platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  14. Design for an IO block array in a tile-based FPGA

    International Nuclear Information System (INIS)

    Ding Guangxin; Chen Lingdou; Liu Zhongli

    2009-01-01

    A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 μm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process. (semiconductor integrated circuits)

  15. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    International Nuclear Information System (INIS)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I.; Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A.

    2010-10-01

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY TM platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY TM platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY TM platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  16. Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

    International Nuclear Information System (INIS)

    Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

    2016-01-01

    The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

  17. Motion camera based on a custom vision sensor and an FPGA architecture

    Science.gov (United States)

    Arias-Estrada, Miguel

    1998-09-01

    A digital camera for custom focal plane arrays was developed. The camera allows the test and development of analog or mixed-mode arrays for focal plane processing. The camera is used with a custom sensor for motion detection to implement a motion computation system. The custom focal plane sensor detects moving edges at the pixel level using analog VLSI techniques. The sensor communicates motion events using the event-address protocol associated to a temporal reference. In a second stage, a coprocessing architecture based on a field programmable gate array (FPGA) computes the time-of-travel between adjacent pixels. The FPGA allows rapid prototyping and flexible architecture development. Furthermore, the FPGA interfaces the sensor to a compact PC computer which is used for high level control and data communication to the local network. The camera could be used in applications such as self-guided vehicles, mobile robotics and smart surveillance systems. The programmability of the FPGA allows the exploration of further signal processing like spatial edge detection or image segmentation tasks. The article details the motion algorithm, the sensor architecture, the use of the event- address protocol for velocity vector computation and the FPGA architecture used in the motion camera system.

  18. 3° Jornadas de TIC e Innovación en el Aula: "Enlaces entre educación, conocimiento libre y tecnologías digitales"

    OpenAIRE

    González, Alejandro Héctor; Martin, María Mercedes

    2015-01-01

    Compilación de las ponencias presentadas en las III Jornadas de TIC e Innovación en el Aula: Enlaces entre educación, conocimiento libre y tecnologías digitales, durante los días 7 y 8 de septiembre de 2015.

  19. Habilidades digitales relacionadas con el medio y el contenido: la importancia del nivel educativo : Medium and content related Digital Skills: the importance of education level of attainment

    NARCIS (Netherlands)

    van Deursen, Alexander Johannes Aloysius Maria; van Dijk, Johannes A.G.M.; Peters, O

    2017-01-01

    Este artículo se centra en uno de los factores considerados cruciales para explicar la brecha digital: la posesión diferencial de las llamadas "habilidades digitales de Internet". En este artículo, se estudia el peso de las variables sexo, edad, nivel educativo, experiencia con Internet y frecuencia

  20. Publicidad dinámica y plataformas digitales: brand placement en espacios públicos y transmisiones deportivas en televisión

    OpenAIRE

    Ortiz Sobrino, Miguel Ángel; Montemayor Ruiz, Francisco Javier

    2014-01-01

    Las imágenes virtuales, la publicidad digital dinámica multimedia diseñada para espacios públicos y las plataformas digitales utilizadas en las transmisiones deportivas en televisión son hoy herramientas esenciales para la estrategia del emplazamiento de las marcas publicitarias.

  1. Tres miradas al mundo de los medios digitales y la comunicación

    Directory of Open Access Journals (Sweden)

    Oscar Coronado Jurado

    2005-01-01

    Full Text Available Este trabajo tiene como propósito abordar tres temas principales del binomio Medios Digitales y Educación: en primer lugar, los Mapas Conceptuales, luego la subjetividad y el aprendizaje en la interacción con el computador y, por último, Internet y su impacto en la educación y en la organización del trabajo. Usando como metodología la investigación bibliográfica, retoma el pensamiento de Novak y de Alberto Cañas, del cual se deriva que los Mapas Conceptuales, son una poderosa herramienta e instrumento, para la modelación rápida y precisa de simples y complejas relaciones causales-jerárquicas y cognitivas. Se aborda el estudio de Sherry Turkle con su libro “La vida en la pantalla. La construcción de la Identidad en la era de Internet”, en el que concluye que la interacción con el computador, después de examinar los llamados M.U.D. (Dominios de Múltiples Usuarios, los estilos de programación, las estéticas y culturas asociadas; en un lapso del desarrollo de la informática, en que el autor reseña -en ocasiones- sus propias experiencias tiene implicaciones fundamentales en la calidad del aprendizaje, la subjetividad y la conciencia colectiva y en comunidad, con importantes hallazgos culturales y psicológicos. Por último se caracteriza a Internet, red de redes, y su profundo impacto en todos los órdenes, especialmente en la forma de aprender y en la estructura reticular de las empresas, a partir del pensamiento de Manuel Castells en su libro “La Galaxia Internet”. Pero lo esencial, como un factor que determina y determinará, la inclusión o exclusión de las naciones, regiones o pueblos, a un desarrollo en que quepamos todos.

  2. Fuentes digitales y fuentes impresas. Prácticas letradas y plagio en el marco universitario

    Directory of Open Access Journals (Sweden)

    Aurora María Ruiz Bejarano

    2017-01-01

    Full Text Available Los estudios acerca de las prácticas de escritura deshonestas experimentaron un auge significativo con la expansión de las tecnologías de la información y de la comunicación. Una parte de estos estudios acepta la celeridad de las herramientas digitales y la accesibilidad de la información como las principales causas de la comisión del plagio digital. Sin embargo, es necesario realizar una aproximación al ciberplagio que lo sitúe dentro de los márgenes de las transformaciones operadas en las prácticas de escritura y que inciden también en las formas de comprender el conocimiento y de estimar el aprendizaje. Este artículo recoge algunos de los resultados preliminares de una investigación realizada en la Universidad de Cádiz1 con el fin de profundizar en la naturaleza de la percepción del plagio y del plagio digital entre el alumnado de los grados de Educación Infantil y Educación Primaria. PALABRAS CLAVE: ciberplagio, plagio, plagio académico, prácticas de escritura, educación superior. Studies on dishonest writing practices have experienced a significant growth with the spread of information and communication technologies. Some of these studies accept that the main cause of digital plagiarism is the speed of digital tools and the accessibilityof information. However, it is necessary to carry out an approach to cyber-plagiarism which placeswithin the marginsof the transformations carried out on writing practices and which have an impact on the way of understanding knowledge and of evaluating learning.This article includes some of the preliminary results of a research carried out in the University ofCádiz with the aim of deepening in the nature of the perception of plagiarism and of digital plagiarism among the students of the Degrees of Infant and Primary Education. Keywords: cyber-plagiarism; plagiarism; academic plagiarism, writing practices, higher education.

  3. Dauerhafter Zugriff auf digitale Publikationen – das DFG-Projekt NatHosting

    Directory of Open Access Journals (Sweden)

    Hildegard Schäffler

    2015-12-01

    Full Text Available Das Arbeiten mit digitalen Veröffentlichungen und Daten in Forschung, Lehre und Studium erfordert eine kontinuierliche und möglichst störungsfreie Verfügbarkeit dieser Inhalte. Bei Publikationen, die von wissenschaftlichen Fachverlagen lizenzpflichtig vertrieben werden, können verschiedene Typen von Störungsfällen wie temporäre oder längerfristige Ausfälle von Verlagsservern, der Transfer von Zeitschriftentiteln zu anderen Verlagen, das komplette Ausscheiden von Verlagen aus dem Markt oder die Abbestellung der elektronischen Ressourcen durch die lizenznehmende Einrichtung zu Zugriffsunterbrechungen führen. Das DFG-Projekt „Nationales Hosting elektronischer Ressourcen“ (NatHosting untersucht, wie unter Berücksichtigung bereits existierender Lösungsansätze eine nationale Strategie zur Absicherung des dauerhaften Zugriffs auf digitale Publikationen entwickelt werden kann. Das vom Projekt erarbeitete Lösungskonzept umfasst eine zweigleisige Strategie der Teilnahme eines nationalen Konsortiums bei Portico bei gleichzeitigem Aufbau eines „Private LOCKSS Networks“ für die durch Portico nicht abgedeckten Inhalte. Weitere Komponenten sind der Aufbau eines rechnergestützten Rechtemanagements und die Einrichtung einer „Hosting-Agentur“ mit Koordinationsaufgaben für das nationale Hosting. In order to work with digital publications and data in a reliable and sustainable way, researchers need to be sure that access to and immediate availability of the content is provided continuously and free of faults. An interruption of access to licensed content can occur for various reasons such as temporary or long-term breakdown of publishers’ servers, the transfer of journals to another publisher, the withdrawal of publishers from the market or the termination of electronic resource subscriptions by the licensee. Against the background of existing solutions, the project NatHosting (National Hosting of Electronic Resources aims at

  4. Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.

  5. Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

  6. Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

    DEFF Research Database (Denmark)

    Singh, Ritu; Kalia, Kartik; Minver, M. H.

    2016-01-01

    Abstract-In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobile...

  7. Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Rehman, M. Atiqur; Hussain, Dil muhammed Akbar

    2016-01-01

    , SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA......nm FPGA....

  8. Realization of manchester encoding and decoding and fast-speed communication for digital power supply based on FPGA

    International Nuclear Information System (INIS)

    Chen Huanguang; Xu Ruinian; Shen Tianjian; Li Deming

    2008-01-01

    A design and simulation to realize the process of Manchester encoding and decoding, to realize the process of SPI communication between FPGA and DSP, using Altera company's Quartus II IDE on FPGA is presented in this paper. And the application on the digital power supply controller with Manchester communication by optical fiber is introduced. (authors)

  9. Design of optical axis jitter control system for multi beam lasers based on FPGA

    Science.gov (United States)

    Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

    2018-02-01

    A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

  10. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    Millar James

    2006-01-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  11. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    James Millar

    2006-10-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  12. A low delay transmission method of multi-channel video based on FPGA

    Science.gov (United States)

    Fu, Weijian; Wei, Baozhi; Li, Xiaobin; Wang, Quan; Hu, Xiaofei

    2018-03-01

    In order to guarantee the fluency of multi-channel video transmission in video monitoring scenarios, we designed a kind of video format conversion method based on FPGA and its DMA scheduling for video data, reduces the overall video transmission delay.In order to sace the time in the conversion process, the parallel ability of FPGA is used to video format conversion. In order to improve the direct memory access (DMA) writing transmission rate of PCIe bus, a DMA scheduling method based on asynchronous command buffer is proposed. The experimental results show that this paper designs a low delay transmission method based on FPGA, which increases the DMA writing transmission rate by 34% compared with the existing method, and then the video overall delay is reduced to 23.6ms.

  13. FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool

    Directory of Open Access Journals (Sweden)

    Mohammed Bahoura

    2016-02-01

    Full Text Available In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA using Xilinx System Generator (XSG and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls.

  14. RADIOMETRIC CALIBRATION OF MARS HiRISE HIGH RESOLUTION IMAGERY BASED ON FPGA

    Directory of Open Access Journals (Sweden)

    Y. Hou

    2016-06-01

    Full Text Available Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

  15. Diversity for security: case assessment for FPGA-based safety-critical systems

    Directory of Open Access Journals (Sweden)

    Kharchenko Vyacheslav

    2016-01-01

    Full Text Available Industrial safety critical instrumentation and control systems (I&Cs are facing more with information (in general and cyber, in particular security threats and attacks. The application of programmable logic, first of all, field programmable gate arrays (FPGA in critical systems causes specific safety deficits. Security assessment techniques for such systems are based on heuristic knowledges and the expert judgment. Main challenge is how to take into account features of FPGA technology for safety critical I&Cs including systems in which are applied diversity approach to minimize risks of common cause failure. Such systems are called multi-version (MV systems. The goal of the paper is in description of the technique and tool for case-based security assessment of MV FPGA-based I&Cs.

  16. An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm

    Directory of Open Access Journals (Sweden)

    Peter Irgens

    2017-04-01

    Full Text Available We present an field programmable gate arrays (FPGA based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping.

  17. Implementation of 4-way Superscalar Hash MIPS Processor Using FPGA

    Science.gov (United States)

    Sahib Omran, Safaa; Fouad Jumma, Laith

    2018-05-01

    Due to the quick advancements in the personal communications systems and wireless communications, giving data security has turned into a more essential subject. This security idea turns into a more confounded subject when next-generation system requirements and constant calculation speed are considered in real-time. Hash functions are among the most essential cryptographic primitives and utilized as a part of the many fields of signature authentication and communication integrity. These functions are utilized to acquire a settled size unique fingerprint or hash value of an arbitrary length of message. In this paper, Secure Hash Algorithms (SHA) of types SHA-1, SHA-2 (SHA-224, SHA-256) and SHA-3 (BLAKE) are implemented on Field-Programmable Gate Array (FPGA) in a processor structure. The design is described and implemented using a hardware description language, namely VHSIC “Very High Speed Integrated Circuit” Hardware Description Language (VHDL). Since the logical operation of the hash types of (SHA-1, SHA-224, SHA-256 and SHA-3) are 32-bits, so a Superscalar Hash Microprocessor without Interlocked Pipelines (MIPS) processor are designed with only few instructions that were required in invoking the desired Hash algorithms, when the four types of hash algorithms executed sequentially using the designed processor, the total time required equal to approximately 342 us, with a throughput of 4.8 Mbps while the required to execute the same four hash algorithms using the designed four-way superscalar is reduced to 237 us with improved the throughput to 5.1 Mbps.

  18. STAR: FPGA-based software defined satellite transponder

    Science.gov (United States)

    Davalle, Daniele; Cassettari, Riccardo; Saponara, Sergio; Fanucci, Luca; Cucchi, Luca; Bigongiari, Franco; Errico, Walter

    2013-05-01

    This paper presents STAR, a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites, developed in collaboration with INTECS and SITAEL companies. With respect to state-of-the-art EO transponders, STAR includes the possibility of scientific data transfer thanks to the 40 Mbps downlink data-rate. This feature represents an important optimization in terms of hardware mass, which is important for EO small satellites. Furthermore, in-flight re-configurability of communication parameters via telecommand is important for in-orbit link optimization, which is especially useful for low orbit satellites where visibility can be as short as few hundreds of seconds. STAR exploits the principles of digital radio to minimize the analog section of the transceiver. 70MHz intermediate frequency (IF) is the interface with an external S/X band radio-frequency front-end. The system is composed of a dedicated configurable high-speed digital signal processing part, the Signal Processor (SP), described in technology-independent VHDL working with a clock frequency of 184.32MHz and a low speed control part, the Control Processor (CP), based on the 32-bit Gaisler LEON3 processor clocked at 32 MHz, with SpaceWire and CAN interfaces. The quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss which is less than 0.5 dB at BER = 10-5 for the RX chain. The IF ports require 8-bit precision. The system prototype is fitted on the Xilinx Virtex 6 VLX75T-FF484 FPGA of which a space-qualified version has been announced. The total device occupation is 82 %.

  19. Multichannel analyzer for nuclear spectrometry with FPGA using Vivado

    International Nuclear Information System (INIS)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Ibarra D, S.; Bravo M, I.

    2017-09-01

    The different applications of ionizing radiation have made this a very significant and useful tool, in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, cannot be perceived by the five senses, in such a way that in order to know the presence of it, radiation detectors and additional devices are required that allow to quantify and classify it. This is the case of the multichannel analyzer that is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The development or conditioning of nuclear technology has increased considerably due to the demand of the applications; therefore this allows developing systems that cover some commercial requirements, cost and volume in relation to the user needs. The objective of the work was to design and implement an intellectual property core (IP Core) which functions as a multichannel analyzer for nuclear spectrometry. For the IP Core design methodology, its components were created in VHDL hardware description language and packaged in the Vivado design suite, making use of resources such as the ARM processor cores that the Zynq chip contains. Likewise, for the first phase of the implementation, the hardware architecture was embedded in the FPGA and the application for the ARM processor was programmed in C language. For the second phase, the management, control and visualization of the results, a virtual instrument was developed in the LabView programming platform. The data obtained as a result of the development and implementation of the IP Core was observed graphically in a histogram that is part of the aforementioned virtual instrument. (Author)

  20. Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-06-01

    Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

  1. Optimization on fixed low latency implementation of the GBT core in FPGA

    Science.gov (United States)

    Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

    2017-07-01

    In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

  2. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

  3. Optimization on fixed low latency implementation of the GBT core in FPGA

    International Nuclear Information System (INIS)

    Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

    2017-01-01

    In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

  4. Application of the Information Encryption Technology in the Industrial Control Network Based on FPGA

    Directory of Open Access Journals (Sweden)

    Guo Yao-Hua

    2014-07-01

    Full Text Available With the rapid development of information technology industry, Information encryption is an effective means of information security. Data encryption system based on FPGA in the field of industry is elaborated in this paper, and the data acquisition module, the basic principle of 3DES algorithm, its implementation in FPGA and PMC bus interface module are introduced. Based on the function simulation, test and analysis of the design results, this scheme has the characteristics of high reliability, fast algorithm and less hardware resources, and it can be widely used in industrial networks.

  5. Data acquisition system for charge-division mechanism based on FPGA

    International Nuclear Information System (INIS)

    Yang Litao; Li Dongcang; Yang Lei; Wu Huaiyi; Qi Zhong

    2010-01-01

    Design a system of Peak value acquisition, data processing and data output for 4 channels nuclear signal at the same time by FPGA that base on the basic principle of position information readout for particle through Charger-division Mechanism. In view of the randomness of nuclear signal, so insert asynchronous FIFO in the system, which greatly improve the sampling rate of system. In the article has produced the conjunctive relation and inner circuit structure and give out simulation. From here, you can see the great power of FPGA which used in nuclear data acquisition and processing system. (authors)

  6. An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

    International Nuclear Information System (INIS)

    Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah; Choi, Jong Gyun

    2014-01-01

    NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity

  7. An Integrated Software Development Framework for PLC and FPGA based Digital I and Cs

    Energy Technology Data Exchange (ETDEWEB)

    Yoo, Jun Beom; Kim, Eui Sub; Lee, Dong Ah [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun [KAERI, Daejeon (Korea, Republic of)

    2014-08-15

    NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safety- critical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously from the same requirement or design specifications. The case study showed that the NuDE 2.0 can be adopted as an effective method of bridging the gap between the existing PLC and upcoming FPGA-based developments as well as a means of gaining diversity.

  8. SEU mitigation technique by Dynamic Reconfiguration method in FPGA based DSP application

    International Nuclear Information System (INIS)

    Dey, Madhusudan; Singh, Abhishek; Roy, Amitava

    2012-01-01

    Field Programmable Gate Array (FPGA), an SRAM based configurable devices meant for implementation of any digital circuits is susceptible to malfunction in the harsh radiation environment. It causes the corruption of the configuration memory of FPGA and the digital circuits starts malfunctioning. There is a need to restore the system as early as possible. This paper discusses about one such technique named dynamic partial reconfiguration (DPR) method. This paper also touches upon the signal processing by DPR method. The framework consisting of ADC, DAC and ICAP controllers designed using dedicated state machines to study the best possible downtime also for verifying the performance of digital filters for signal processing

  9. Implementació d'una Cache per a un processador MIPS d'una FPGA

    OpenAIRE

    Riera Villanueva, Marc

    2013-01-01

    [CATALÀ] Primer s'explicarà breument l'arquitectura d'un MIPS, la jerarquia de memòria i el funcionament de la cache. Posteriorment s'explicarà com s'ha dissenyat i implementat una jerarquia de memòria per a un MIPS implementat en VHDL en una FPGA. [ANGLÈS] First, the MIPS architecture, memory hierarchy and the functioning of the cache will be explained briefly. Then, the design and implementation of a memory hierarchy for a MIPS processor implemented in VHDL on an FPGA will be explained....

  10. GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

    International Nuclear Information System (INIS)

    Mitra, Jubin; Khan, Shuaib A.; Nayak, Tapan K.; Marin, Manoel Barros; Baron, Sophie; Kluge, Alex; Cachemiche, Jean-Pierre; Hachon, Frédéric; Rethore, Frédéric; David, Erno; Kiss, Tivadar

    2016-01-01

    The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA

  11. FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling.

    Science.gov (United States)

    Kim, Chang-Min; Park, Hyung-Min; Kim, Taesu; Choi, Yoon-Kyung; Lee, Soo-Young

    2003-01-01

    An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time.

  12. Radiation tolerance and mitigation strategies for FPGA:s in the ATLAS TileCal Demonstrator

    CERN Document Server

    Akerstedt, H; The ATLAS collaboration

    2013-01-01

    During 2014, demonstrator electronics will be installed in a Tile calorimeter "drawer" to get long term experience with the inherently redundant electronics proposed for a full upgrade scheduled for 2022. The new system, being FPGA-based, uses dense programmable logic which must be proven to be sufficently radiation tolerant. It must be protected against radiation induced single event upsets that corrupt memory and logic functions. Radiation induced errors need to be found and compensated for in time, to minimize data loss but also to avoid permanent damage. Strategies for detecting and correcting radiation induced errors in the Kintex-7 FPGA:s of the demonstrator are evaluated and discussed.

  13. Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

    Directory of Open Access Journals (Sweden)

    Alisson C. D. de Souza

    2014-09-01

    Full Text Available This paper proposes a parallel fixed point radial basis function (RBF artificial neural network (ANN, implemented in a field programmable gate array (FPGA trained online with a least mean square (LMS algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx, with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.

  14. Implementation of the 2-D Wavelet Transform into FPGA for Image

    Science.gov (United States)

    León, M.; Barba, L.; Vargas, L.; Torres, C. O.

    2011-01-01

    This paper presents a hardware system implementation of the of discrete wavelet transform algoritm in two dimensions for FPGA, using the Daubechies filter family of order 2 (db2). The decomposition algorithm of this transform is designed and simulated with the Hardware Description Language VHDL and is implemented in a programmable logic device (FPGA) XC3S1200E reference, Spartan IIIE family, by Xilinx, take advantage the parallels properties of these gives us and speeds processing that can reach them. The architecture is evaluated using images input of different sizes. This implementation is done with the aim of developing a future images encryption hardware system using wavelet transform for security information.

  15. Integration of multi-interface conversion channel using FPGA for modular photonic network

    Science.gov (United States)

    Janicki, Tomasz; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.

    2010-09-01

    The article discusses the integration of different types of interfaces with FPGA circuits using a reconfigurable communication platform. The solution has been implemented in practice in a single node of a distributed measurement system. Construction of communication platform has been presented with its selected hardware modules, described in VHDL and implemented in FPGA circuits. The graphical user interface (GUI) has been described that allows a user to control the operation of the system. In the final part of the article selected practical solutions have been introduced. The whole measurement system resides on multi-gigabit optical network. The optical network construction is highly modular, reconfigurable and scalable.

  16. FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG

    Science.gov (United States)

    2014-06-01

    is normalized to π. The proposed burst-mode architecture is written in VHDL and verified using Modelsim. The VHDL design is implemented on a Xilinx...Document Number: SET 2014-0043 412TW-PA-14298 FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG June 2014 Final Report Test...To) 9/11 -- 8/14 4. TITLE AND SUBTITLE FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG 5a. CONTRACT NUMBER: W900KK-11-C-0032 5b

  17. Implementation of the 2-D Wavelet Transform into FPGA for Image

    Energy Technology Data Exchange (ETDEWEB)

    Leon, M; Barba, L; Vargas, L; Torres, C O, E-mail: madeleineleon@unicesar.edu.co [Laboratorio de Optica e Informatica, Universidad Popular del Cesar, Sede balneario Hurtado, Valledupar, Cesar (Colombia)

    2011-01-01

    This paper presents a hardware system implementation of the of discrete wavelet transform algorithm in two dimensions for FPGA, using the Daubechies filter family of order 2 (db2). The decomposition algorithm of this transform is designed and simulated with the Hardware Description Language VHDL and is implemented in a programmable logic device (FPGA) XC3S1200E reference, Spartan IIIE family, by Xilinx, take advantage the parallels properties of these gives us and speeds processing that can reach them. The architecture is evaluated using images input of different sizes. This implementation is done with the aim of developing a future images encryption hardware system using wavelet transform for security information.

  18. Implementation of FPGA based PID Controller for DC Motor Speed Control System

    Directory of Open Access Journals (Sweden)

    Savita SONOLI

    2010-03-01

    Full Text Available In this paper, the implementation of software module using ‘VHDL’ for Xilinx FPGA (XC3S400 based PID controller for DC motor speed control system is presented. The tools used for building and testing the software modules are Xilinx ISE 9.2i and ModelSim XE III 6.3c. Before verifying the design on FPGA the complete design is simulated using Modelsim Simulation tool. A test bench is written where the set speed can be changed for the motor. It is observed that the motor speed gradually changes to the set speed and locks to the set speed.

  19. The FPGA realization of the general cellular automata based cryptographic hash functions: Performance and effectiveness

    Directory of Open Access Journals (Sweden)

    P. G. Klyucharev

    2014-01-01

    Full Text Available In the paper the author considers hardware implementation of the GRACE-H family general cellular automata based cryptographic hash functions. VHDL is used as a language and Altera FPGA as a platform for hardware implementation. Performance and effectiveness of the FPGA implementations of GRACE-H hash functions were compared with Keccak (SHA-3, SHA-256, BLAKE, Groestl, JH, Skein hash functions. According to the performed tests, performance of the hardware implementation of GRACE-H family hash functions significantly (up to 12 times exceeded performance of the hardware implementation of previously known hash functions, and effectiveness of that hardware implementation was also better (up to 4 times.

  20. A configurable FPGA FEC unit for Tb/s optical communication

    DEFF Research Database (Denmark)

    Andersen, Jakob Dahl; Larsen, Knud J.; Bering Bøgh, Christian

    2017-01-01

    Decoding of FEC (forward error correction) for optical communication beyond 1 Tb/s is investigated. A configurable single FPGA solution is presented having configurations supporting bit-rates in the range from 40 Gb/s to 1.6 Tb/s. The design allows for trade-offs of bit-rate, footprint, and latency...... within the resources of the FPGA. A proof-of-concept lab experiment at 40 Gb/s was conducted and pre-FEC — post-FEC performance validated with simulated results....