Interactive Digital Signal Processor
Mish, W. H.
1985-01-01
Interactive Digital Signal Processor, IDSP, consists of set of time series analysis "operators" based on various algorithms commonly used for digital signal analysis. Processing of digital signal time series to extract information usually achieved by applications of number of fairly standard operations. IDSP excellent teaching tool for demonstrating application for time series operators to artificially generated signals.
A Fast DCT Algorithm for Watermarking in Digital Signal Processor
S. E. Tsai
2017-01-01
Full Text Available Discrete cosine transform (DCT has been an international standard in Joint Photographic Experts Group (JPEG format to reduce the blocking effect in digital image compression. This paper proposes a fast discrete cosine transform (FDCT algorithm that utilizes the energy compactness and matrix sparseness properties in frequency domain to achieve higher computation performance. For a JPEG image of 8×8 block size in spatial domain, the algorithm decomposes the two-dimensional (2D DCT into one pair of one-dimensional (1D DCTs with transform computation in only 24 multiplications. The 2D spatial data is a linear combination of the base image obtained by the outer product of the column and row vectors of cosine functions so that inverse DCT is as efficient. Implementation of the FDCT algorithm shows that embedding a watermark image of 32 × 32 block pixel size in a 256 × 256 digital image can be completed in only 0.24 seconds and the extraction of watermark by inverse transform is within 0.21 seconds. The proposed FDCT algorithm is shown more efficient than many previous works in computation.
Morris, L R; Barszczewski, P
1989-06-01
Software and hardware have been developed to create a powerful, inexpensive, compact digital signal processing system which in real-time extracts a low-bit rate linear predictive coding (LPC) speech system model. The model parameters derived include accurate spectral envelope, formant, pitch, and amplitude information. The system is based on the Texas Instruments TMS320 family, and the most compact realization requires only three chips (TMS320E17, A/D-D/A, op-amp), consuming a total of less than 0.5 W. The processor is part of programmable cochlear implant system under development by a multiuniversity Canadian team, but also has other applications in aids to the hearing handicapped.
An Experimental Digital Image Processor
Cok, Ronald S.
1986-12-01
A prototype digital image processor for enhancing photographic images has been built in the Research Laboratories at Kodak. This image processor implements a particular version of each of the following algorithms: photographic grain and noise removal, edge sharpening, multidimensional image-segmentation, image-tone reproduction adjustment, and image-color saturation adjustment. All processing, except for segmentation and analysis, is performed by massively parallel and pipelined special-purpose hardware. This hardware runs at 10 MHz and can be adjusted to handle any size digital image. The segmentation circuits run at 30 MHz. The segmentation data are used by three single-board computers for calculating the tonescale adjustment curves. The system, as a whole, has the capability of completely processing 10 million three-color pixels per second. The grain removal and edge enhancement algorithms represent the largest part of the pipelined hardware, operating at over 8 billion integer operations per second. The edge enhancement is performed by unsharp masking, and the grain removal is done using a collapsed Walsh-hadamard transform filtering technique (U.S. Patent No. 4549212). These two algo-rithms can be realized using four basic processing elements, some of which have been imple-mented as VLSI semicustom integrated circuits. These circuits implement the algorithms with a high degree of efficiency, modularity, and testability. The digital processor is controlled by a Digital Equipment Corporation (DEC) PDP 11 minicomputer and can be interfaced to electronic printing and/or electronic scanning de-vices. The processor has been used to process over a thousand diagnostic images.
LIBS data analysis using a predictor-corrector based digital signal processor algorithm
Sanders, Alex; Griffin, Steven T.; Robinson, Aaron
2012-06-01
There are many accepted sensor technologies for generating spectra for material classification. Once the spectra are generated, communication bandwidth limitations favor local material classification with its attendant reduction in data transfer rates and power consumption. Transferring sensor technologies such as Cavity Ring-Down Spectroscopy (CRDS) and Laser Induced Breakdown Spectroscopy (LIBS) require effective material classifiers. A result of recent efforts has been emphasis on Partial Least Squares - Discriminant Analysis (PLS-DA) and Principle Component Analysis (PCA). Implementation of these via general purpose computers is difficult in small portable sensor configurations. This paper addresses the creation of a low mass, low power, robust hardware spectra classifier for a limited set of predetermined materials in an atmospheric matrix. Crucial to this is the incorporation of PCA or PLS-DA classifiers into a predictor-corrector style implementation. The system configuration guarantees rapid convergence. Software running on multi-core Digital Signal Processor (DSPs) simulates a stream-lined plasma physics model estimator, reducing Analog-to-Digital (ADC) power requirements. This paper presents the results of a predictorcorrector model implemented on a low power multi-core DSP to perform substance classification. This configuration emphasizes the hardware system and software design via a predictor corrector model that simultaneously decreases the sample rate while performing the classification.
IDSP- INTERACTIVE DIGITAL SIGNAL PROCESSOR
Mish, W. H.
1994-01-01
The Interactive Digital Signal Processor, IDSP, consists of a set of time series analysis "operators" based on the various algorithms commonly used for digital signal analysis work. The processing of a digital time series to extract information is usually achieved by the application of a number of fairly standard operations. However, it is often desirable to "experiment" with various operations and combinations of operations to explore their effect on the results. IDSP is designed to provide an interactive and easy-to-use system for this type of digital time series analysis. The IDSP operators can be applied in any sensible order (even recursively), and can be applied to single time series or to simultaneous time series. IDSP is being used extensively to process data obtained from scientific instruments onboard spacecraft. It is also an excellent teaching tool for demonstrating the application of time series operators to artificially-generated signals. IDSP currently includes over 43 standard operators. Processing operators provide for Fourier transformation operations, design and application of digital filters, and Eigenvalue analysis. Additional support operators provide for data editing, display of information, graphical output, and batch operation. User-developed operators can be easily interfaced with the system to provide for expansion and experimentation. Each operator application generates one or more output files from an input file. The processing of a file can involve many operators in a complex application. IDSP maintains historical information as an integral part of each file so that the user can display the operator history of the file at any time during an interactive analysis. IDSP is written in VAX FORTRAN 77 for interactive or batch execution and has been implemented on a DEC VAX-11/780 operating under VMS. The IDSP system generates graphics output for a variety of graphics systems. The program requires the use of Versaplot and Template plotting
Digital Signal Processor For GPS Receivers
Thomas, J. B.; Meehan, T. K.; Srinivasan, J. M.
1989-01-01
Three innovative components combined to produce all-digital signal processor with superior characteristics: outstanding accuracy, high-dynamics tracking, versatile integration times, lower loss-of-lock signal strengths, and infrequent cycle slips. Three components are digital chip advancer, digital carrier downconverter and code correlator, and digital tracking processor. All-digital signal processor intended for use in receivers of Global Positioning System (GPS) for geodesy, geodynamics, high-dynamics tracking, and ionospheric calibration.
Cluster Algorithm Special Purpose Processor
Talapov, A. L.; Shchur, L. N.; Andreichenko, V. B.; Dotsenko, Vl. S.
We describe a Special Purpose Processor, realizing the Wolff algorithm in hardware, which is fast enough to study the critical behaviour of 2D Ising-like systems containing more than one million spins. The processor has been checked to produce correct results for a pure Ising model and for Ising model with random bonds. Its data also agree with the Nishimori exact results for spin glass. Only minor changes of the SPP design are necessary to increase the dimensionality and to take into account more complex systems such as Potts models.
Cluster algorithm special purpose processor
Talapov, A.L.; Shchur, L.N.; Andreichenko, V.B.; Dotsenko, V.S. (Landau Inst. for Theoretical Physics, GSP-1 117940 Moscow V-334 (USSR))
1992-08-10
In this paper, the authors describe a Special Purpose Processor, realizing the Wolff algorithm in hardware, which is fast enough to study the critical behaviour of 2D Ising-like systems containing more than one million spins. The processor has been checked to produce correct results for a pure Ising model and for Ising model with random bonds. Its data also agree with the Nishimori exact results for spin glass. Only minor changes of the SPP design are necessary to increase the dimensionality and to take into account more complex systems such as Potts models.
Mahmud Benhamid
2009-01-01
Full Text Available Problem statement: Ultra Wide Band (UWB technology has attracted many researchers' attention due to its advantages and its great potential for future applications. The physical layer standard of Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM UWB system is defined by ECMA International. In this standard, the data sampling rate from the analog-to-digital converter to the physical layer is up to 528 M sample sec-1. Therefore, it is a challenge to realize the physical layer especially the components with high computational complexity in Very Large Scale Integration (VLSI implementation. Fast Fourier Transform (FFT block which plays an important role in MB-OFDM system is one of these components. Furthermore, the execution time of this module is only 312.5 ns. Therefore, if employing the traditional approach, high power consumption and hardware cost of the processor will be needed to meet the strict specifications of the UWB system. The objective of this study was to design an Application Specific Integrated Circuit (ASIC FFT processor for this system. The specification was defined from the system analysis and literature research. Approach: Based on the algorithm and architecture analysis, a novel Genetic Algorithm (GA based Canonical Signed Digit (CSD Multiplier less 128-point FFT processor and its inverse (IFFT for MB-OFDM UWB systems had been proposed. The proposed pipelined architecture was based on the modified Radix-22 algorithm that had same number of multipliers as that of the conventional Radix-22. However, the multiplication complexity and the ROM memory needed for storing twiddle factors coefficients could be eliminated by replacing the conventional complex multipliers with a newly proposed GA optimized CSD constant multipliers. The design had been coded in Verilog HDL and targeted Xilinx Virtex-II FPGA series. It was fully implemented and tested on real hardware using Virtex-II FG456 prototype board and logic analyzer
Distributed digital signal processors for multi-body structures
Lee, Gordon K.
1990-01-01
Several digital filter designs were investigated which may be used to process sensor data from large space structures and to design digital hardware to implement the distributed signal processing architecture. Several experimental tests articles are available at NASA Langley Research Center to evaluate these designs. A summary of some of the digital filter designs is presented, an evaluation of their characteristics relative to control design is discussed, and candidate hardware microcontroller/microcomputer components are given. Future activities include software evaluation of the digital filter designs and actual hardware inplementation of some of the signal processor algorithms on an experimental testbed at NASA Langley.
First Cluster Algorithm Special Purpose Processor
Talapov, A. L.; Andreichenko, V. B.; Dotsenko S., Vi.; Shchur, L. N.
We describe the architecture of the special purpose processor built to realize in hardware cluster Wolff algorithm, which is not hampered by a critical slowing down. The processor simulates two-dimensional Ising-like spin systems. With minor changes the same very effective architecture, which can be defined as a Memory Machine, can be used to study phase transitions in a wide range of models in two or three dimensions.
High-Speed General Purpose Genetic Algorithm Processor.
Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah
2016-07-01
In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.
Preliminary low temperature tests of a digital signal processor
Zebulum, Ricardo S.; Ramesham, Rajeshuni; Stoica, Adrian; Keymeulen, Didier; Daud, Taher; Sekanina, Lukas
2005-01-01
This paper describes an initial experiment performed to assess the electrical behavior of the Innovative Integration board containing a Digital Signal Processor (DSP) with its JTAG (Blackhawk) connector at low temperatures. The objective of the experiment is to determine the lowest temperature at which the DSP can operate. The DSP was tested at various low-temperatures and a Genetic Algorithm was used as the DSP test program.
Quantum Algorithm Processor For Finding Exact Divisors
Burger, John Robert
2005-01-01
Wiring diagrams are given for a quantum algorithm processor in CMOS to compute, in parallel, all divisors of an n-bit integer. Lines required in a wiring diagram are proportional to n. Execution time is proportional to the square of n.
Fault tolerant, radiation hard, high performance digital signal processor
Holmann, Edgar; Linscott, Ivan R.; Maurer, Michael J.; Tyler, G. L.; Libby, Vibeke
1990-01-01
An architecture has been developed for a high-performance VLSI digital signal processor that is highly reliable, fault-tolerant, and radiation-hard. The signal processor, part of a spacecraft receiver designed to support uplink radio science experiments at the outer planets, organizes the connections between redundant arithmetic resources, register files, and memory through a shuffle exchange communication network. The configuration of the network and the state of the processor resources are all under microprogram control, which both maps the resources according to algorithmic needs and reconfigures the processing should a failure occur. In addition, the microprogram is reloadable through the uplink to accommodate changes in the science objectives throughout the course of the mission. The processor will be implemented with silicon compiler tools, and its design will be verified through silicon compilation simulation at all levels from the resources to full functionality. By blending reconfiguration with redundancy the processor implementation is fault-tolerant and reliable, and possesses the long expected lifetime needed for a spacecraft mission to the outer planets.
Single-Scale Retinex Using Digital Signal Processors
Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn
2005-01-01
The Retinex is an image enhancement algorithm that improves the brightness, contrast and sharpness of an image. It performs a non-linear spatial/spectral transform that provides simultaneous dynamic range compression and color constancy. It has been used for a wide variety of applications ranging from aviation safety to general purpose photography. Many potential applications require the use of Retinex processing at video frame rates. This is difficult to achieve with general purpose processors because the algorithm contains a large number of complex computations and data transfers. In addition, many of these applications also constrain the potential architectures to embedded processors to save power, weight and cost. Thus we have focused on digital signal processors (DSPs) and field programmable gate arrays (FPGAs) as potential solutions for real-time Retinex processing. In previous efforts we attained a 21 (full) frame per second (fps) processing rate for the single-scale monochromatic Retinex with a TMS320C6711 DSP operating at 150 MHz. This was achieved after several significant code improvements and optimizations. Since then we have migrated our design to the slightly more powerful TMS320C6713 DSP and the fixed point TMS320DM642 DSP. In this paper we briefly discuss the Retinex algorithm, the performance of the algorithm executing on the TMS320C6713 and the TMS320DM642, and compare the results with the TMS320C6711.
Optical linear algebra processors - Architectures and algorithms
Casasent, David
1986-01-01
Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.
Optical linear algebra processors - Architectures and algorithms
Casasent, David
1986-01-01
Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.
DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor
Chuang, Chung-Lun; Shaffer, Scott; Smythe, Robert; Niamsuwan, Noppasin; Li, Samuel; Liao, Eric; Lim, Chester; Morfopolous, Arin; Veilleux, Louise
2013-01-01
The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.
DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor
Chuang, Chung-Lun; Shaffer, Scott; Smythe, Robert; Niamsuwan, Noppasin; Li, Samuel; Liao, Eric; Lim, Chester; Morfopolous, Arin; Veilleux, Louise
2013-01-01
The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.
An Efficient Graph-Coloring Algorithm for Processor Allocation
Mohammed Hasan Mahafzah
2013-06-01
Full Text Available This paper develops an efficient exact graph-coloring algorithm based on Maximum Independent Set (MIS for allocating processors in distributed systems. This technique represents the allocated processors in specific time in a fully connected graph and prevents each processor in multiprocessor system to be assigned to more than one process at a time. This research uses a sequential technique to distribute processes among processors. Moreover, the proposed method has been constructed by modifying the FMIS algorithm. The proposed algorithm has been programmed in Visual C++ and implemented on an Intel core i7. The experiments show that the proposed algorithm gets better performance in terms of CPU utilization, and minimum time for of graph coloring, comparing with the latest FMIS algorithm. The proposed algorithm can be developed to detect defected processor in the system.
NONE
2000-03-01
The digital audio signal processor (DSP) TC9446F series has been developed silicon audio playback devices with a memory medium of, e.g., flash memory, DVD players, and AV devices, e.g., TV sets. It corresponds to AAC (advanced audio coding) (2ch) and MP3 (MPEG1 Layer3), as the audio compressing techniques being used for transmitting music through an internet. It also corresponds to compressed types, e.g., Dolby Digital, DTS (digital theater system) and MPEG2 audio, being adopted for, e.g., DVDs. It can carry a built-in audio signal processing program, e.g., Dolby ProLogic, equalizer, sound field controlling, and 3D sound. TC9446XB has been lined up anew. It adopts an FBGA (fine pitch ball grid array) package for portable audio devices. (translated by NEDO)
Digital Signal Processor System for AC Power Drivers
Ovidiu Neamtu
2009-01-01
DSP (Digital Signal Processor) is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulation)circuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.
Digital Signal Processor System for AC Power Drivers
Ovidiu Neamtu
2009-10-01
Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.
Real-time adaptive filtering of dental drill noise using a digital signal processor
2006-01-01
The application of noise reduction methods requires the integration of acoustics engineering and digital signal processing, which is well served by a mechatronic approach as described in this paper. The Normalised Least Mean Square (NLMS) algorithm is implemented on the Texas Instruments TMS320C6713 DSK Digital Signal Processor (DSP) as an adaptive digital filter for dental drill noise. Blocks within the Matlab/Simulink Signal Processing Blockset and the Embedded Target for TI C6000 DSP famil...
Acoustooptic linear algebra processors - Architectures, algorithms, and applications
Casasent, D.
1984-01-01
Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.
Acoustooptic linear algebra processors - Architectures, algorithms, and applications
Casasent, D.
1984-01-01
Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.
Real time simulator with Ti floating point digital signal processor
Razazian, K.; Bobis, J.P.; Dieckman, S.L.; Raptis, A.C.
1994-08-01
This paper describes the design and operation of a Real Time Simulator using Texas Instruments TMS320C30 digital signal processor. This system operates with two banks of memory which provide the input data to digital signal processor chip. This feature enables the TMS320C30 to be utilized in variety of applications for which external connections to acquire input data is not needed. In addition, some practical applications of this Real Time Simulator are discussed.
An online emission spectral tomography system with digital signal processor.
Wan, Xiong; Xiong, Wenlin; Zhang, Zhimin; Chang, Fangfei
2009-03-30
Emission spectral tomography (EST) has been adopted to test the three-dimensional distribution parameters of fluid fields, such as burning gas, flame and plasma etc. In most cases, emission spectral data received by the video cameras are enormous so that the emission spectral tomography calculation is often time-consuming. Hence, accelerating calculation becomes the chief factor that one must consider for the practical application of EST. To solve the problem, a hardware implementation method was proposed in this paper, which adopted a digital signal processor (DSP) DM642 in an emission spectral tomography test system. The EST algorithm was fulfilled in the DSP, then calculation results were transmitted to the main computer via the user datagram protocol. Compared with purely VC++ software implementations, this new approach can decrease the calculation time significantly.
Digital signal processor and processing method for GPS receivers
Thomas, Jr., Jess B. (Inventor)
1989-01-01
A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.
A Digital Data Processor for Synthetic Aperture Radar
Vlothuizen, W.J.; Medenblik, H.J.W.
2007-01-01
This paper presents a Digital Data Processor (DDP) for Synthetic Aperture Radar (SAR). The DDP captures SAR data at a 1 GHz sample rate and processes data at 350 MB/s. Data reduction is performed by a digital down converter, programmable decimating filter and a fully programmable presummer. The tota
Fey, D; Kasche, B; Burkert, C; Tschäche, O
1998-01-10
A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.
Floating-point multiple data stream digital signal processor
Fortier, M.; Corinthios, M.J.
1982-01-01
A microprogrammed multiple data stream digital signal processor is introduced. This floating-point processor is capable of implementing optimum Wiener filtering of signals, in general, and images in particular. Generalised spectral analysis transforms such as Fourier, Walsh, Hadamard, and generalised Walsh are efficiently implemented in a bit-slice microprocessor-based architecture. In this architecture, a microprogrammed sequencing section directly controls a central floating-point signal processing unit. Throughout, computations are performed on pipelined multiple complex data streams. 12 references.
Digital optical cellular image processor (DOCIP) - Experimental implementation
Huang, K.-S.; Sawchuk, A. A.; Jenkins, B. K.; Chavel, P.; Wang, J.-M.; Weber, A. G.; Wang, C.-H.; Glaser, I.
1993-01-01
We demonstrate experimentally the concept of the digital optical cellular image processor architecture by implementing one processing element of a prototype optical computer that includes a 54-gate processor, an instruction decoder, and electronic input-output interfaces. The processor consists of a two-dimensional (2-D) array of 54 optical logic gates implemented by use of a liquid-crystal light valve and a 2-D array of 53 subholograms to provide interconnections between gates. The interconnection hologram is fabricated by a computer-controlled optical system.
Reconfigurable signal processor designs for advanced digital array radar systems
Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining
2017-05-01
The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.
Digital systems from logic gates to processors
Deschamps, Jean-Pierre; Terés, Lluís
2017-01-01
This textbook for a one-semester course in Digital Systems Design describes the basic methods used to develop “traditional” Digital Systems, based on the use of logic gates and flip flops, as well as more advanced techniques that enable the design of very large circuits, based on Hardware Description Languages and Synthesis tools. It was originally designed to accompany a MOOC (Massive Open Online Course) created at the Autonomous University of Barcelona (UAB), currently available on the Coursera platform. Readers will learn what a digital system is and how it can be developed, preparing them for steps toward other technical disciplines, such as Computer Architecture, Robotics, Bionics, Avionics and others. In particular, students will learn to design digital systems of medium complexity, describe digital systems using high level hardware description languages, and understand the operation of computers at their most basic level. All concepts introduced are reinforced by plentiful illustrations, examples, ...
Implementation Of A Prototype Digital Optical Cellular Image Processor (DOCIP)
Huang, K. S.; Sawchuk, A. A.; Jenkins, B. K.; Chavel, P.; Wang, J. M.; Weber, A. G.; Wang, C. H.; Glaser, I.
1989-02-01
A processing element of a prototype digital optical cellular image processor (DOCIP) is implemented to demonstrate a particular parallel computing and interconnection architecture. This experimental digital optical computing system consists of a 2-D array of 54 optical logic gates, a 2-D array of 53 subholograms to provide interconnections between gates, and electronic input/output interfaces. The multi-facet interconnection hologram used in this system is fabricated by a computer-controlled optical system to offer very flexible interconnections.
All-optical digital processor based on harmonic generation phenomena
Shcherbakov, Alexandre S.; Rakovsky, Vsevolod Y.
1990-07-01
Digital optical processors are designed to combine ultra- parallel data procesing capabilities of optical aystems cnd high accur&cy of performed computations. The ultimate limit of the processing rate can be anticipated from all-optical parcllel erchitecturea based on networks o logic gates using materials exibiting strong electronic nonlinearities with response times less than 1O seconds1.
Image processing algorithm acceleration using reconfigurable macro processor model
孙广富; 陈华明; 卢焕章
2004-01-01
The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of reconfigurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented.Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of "hardware" function that can be called by the DSP in high-level algorithm.It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.
The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units
Tavares Delgado, Ademar; The ATLAS collaboration
2016-01-01
The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units Type: Talk Abstract: We present the ATLAS Trigger algorithms developed to exploit General Purpose Graphics Processor Units. ATLAS is a particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system has two levels, hardware-based Level 1 and the High Level Trigger implemented in software running on a farm of commodity CPU. Performing the trigger event selection within the available farm resources presents a significant challenge that will increase future LHC upgrades. are being evaluated as a potential solution for trigger algorithms acceleration. Key factors determining the potential benefit of this new technology are the relative execution speedup, the number of GPUs required and the relative financial cost of the selected GPU. We have developed a trigger demonstrator which includes algorithms for reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Cal...
VLSI digital demodulator co-processor
Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.
A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.
CERN Technical Training: Digital Signal Processors
HR Department
2009-01-01
A new training is going to be held at CERN on the ADSP SHARC Family. The “System Development and Programming with the Analog Devices' SHARC Family” course is a 3.5-day hands-on training on Analog Devices SHARC DSPs, focusing on the latest ‘368/9 and 37x families. General DSP architecture, peripherals available, booting up process and DSP code development will be covered. Hardware tools, debugging and hardware design guidelines will be introduced as well. The course id designed for System Designers needing to make informed decisions on design tradeoffs, Hardware Designers needing to develop external interfaces, and Code Developers needing to know how to get the highest performance from their algorithms. The course will take place, in English, from 31 March to 4 April in the CERN Technical Training Center. Few places are still available. Registrations are opened on the Technical Training page. More information on our catalogue: http://cta.cern.ch/cta2/f?p=110:9 or conta...
High performance deformable image registration algorithms for manycore processors
Shackleford, James; Sharp, Gregory
2013-01-01
High Performance Deformable Image Registration Algorithms for Manycore Processors develops highly data-parallel image registration algorithms suitable for use on modern multi-core architectures, including graphics processing units (GPUs). Focusing on deformable registration, we show how to develop data-parallel versions of the registration algorithm suitable for execution on the GPU. Image registration is the process of aligning two or more images into a common coordinate frame and is a fundamental step to be able to compare or fuse data obtained from different sensor measurements. E
Digital signal processor-based real-time optical Doppler tomography system.
Yan, Shikui; Piao, Daqing; Chen, Yueli; Zhu, Quing
2004-01-01
We present a real-time data-processing and display unit based on a custom-designed digital signal processor (DSP) module for imaging tissue structure and Doppler blood flow. The DSP module is incorporated into a conventional optical coherence tomography system. We also demonstrate the flexibility of embedding advanced Doppler processing algorithms in the DSP module. Two advanced velocity estimation algorithms previously introduced by us are incorporated in this DSP module. Experiments on Intralipid flow demonstrate that a pulsatile flow of several hundred pulses per minute can be faithfully captured in M-scan mode by this DSP system. In vivo imaging of a rat's abdominal blood flow is also presented.
Abdul Aziz Mohammed Al Buaijan,
2014-08-01
Full Text Available Presenting in his paper, Digital signal processor (DSP-based implementation of a single phase unified power flow controller (UPFC. For shunt side and series side An efficient UPFC control algorithm is achieved. Discussing the laboratory experimental results using DC source are taken as an UPFC linked by two ll-bridge PWM voltage source converters.
Digital Guided Weapons Technology. Volume 1. Digital Processor System Studies
1976-11-01
Subsystem 4. 1. 3 LORAN Subsystem 4. 1.4 E-O Data Link Subsystem 4. 1. 5 TERCOM Subsystem 4.1.6 DME Subsystem 4. 1.7 Global Positioning System...Subsystem Block Diagram 16 Electro-Optical Data Link Subsystem Block Diagram 17 TERCOM Subsystem Block Diagram 18 GPS Subsystem Functional Flow...Processing Requirements — EO Data Link 6 Processing Requirements - TERCOM Subsystem 7 GPS Guidance Subsystem Digital Processing Requirements 8
Image data compression using a new floating-point digital signal processor.
Siegel, E L; Templeton, A W; Hensley, K L; McFadden, M A; Baxter, K G; Murphey, M D; Cronin, P E; Gesell, R G; Dwyer, S J
1991-08-01
A new dual-ported, floating-point, digital signal processor has been evaluated for compressing 512 and 1,024 digital radiographic images using a full-frame, two-dimensional, discrete cosine transform (2D-DCT). The floating point digital signal processor operates at 49.5 million floating point instructions per second (MFLOPS). The level of compression can be changed by varying four parameters in the lossy compression algorithm. Throughput times were measured for both 2D-DCT compression and decompression. For a 1,024 x 1,024 x 10-bit image with a compression ratio of 316:1, the throughput was 75.73 seconds (compression plus decompression throughput). For a digital fluorography 1,024 x 1,024 x 8-bit image and a compression ratio of 26:1, the total throughput time was 63.23 seconds. For a computed tomography image of 512 x 512 x 12 bits and a compression ratio of 10:1 the throughput time was 19.65 seconds.
The Trigger Processor and Trigger Processor Algorithms for the ATLAS New Small Wheel Upgrade
Lazovich, Tomo; The ATLAS collaboration
2015-01-01
The ATLAS New Small Wheel (NSW) is an upgrade to the ATLAS muon endcap detectors that will be installed during the next long shutdown of the LHC. Comprising both MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), this system will drastically improve the performance of the muon system in a high cavern background environment. The NSW trigger, in particular, will significantly reduce the rate of fake triggers coming from track segments in the endcap not originating from the interaction point. We will present an overview of the trigger, the proposed sTGC and MM trigger algorithms, and the hardware implementation of the trigger. In particular, we will discuss both the heart of the trigger, an ATCA system with FPGA-based trigger processors (using the same hardware platform for both MM and sTGC triggers), as well as the full trigger electronics chain, including dedicated cards for transmission of data via GBT optical links. Finally, we will detail the challenges of ensuring that the trigger electronics can ...
Digital GPS-Signal Processor With P-Code/No-P-Code Option
Thomas, J. Brooks; Srinivasan, Jeffrey M.
1994-01-01
Size, power, and cost reduced by exploiting commonality. Digital signal processor for Global Positioning System (GPS) receiver set to operate in "code" mode when P code known, or in "codeless" mode when P code not known. In codeless mode, processor performs full-quadrature processing, resulting in signal-to-noise ratio (SNR) 6 dB greater than SNR's of processors not performing at full quadrature.
Analyzing and Seeking Minimum Test Instruction Set of Digital Signal Processor for Motor Control
严伟; 曹家麟; 龚幼民
2005-01-01
The relativity of instructions of motor control digital signal processor (MCDSP) in the design is analyzed. A method for obtaining a minimum instruction set in place of the complete instruction set during generation of testing procedures is given in terms of the processor presentation matrix between micro-operators and instructions of MCDSP.
Qin, Jianhuan; Huang, Zhiming; Ge, Yujian; Hou, Yun; Chu, Junhao
2009-03-01
Dual-modulated spectroscopy is one of the most powerful methods in the measurement of modulation spectroscopy. Here we develop a tandem lock-in amplifier (LIA) based on digital signal processor to implement a novel algorithm of tandem demodulation. The theoretical analysis of demodulation algorithm is presented, and the implementation of this tandem LIA is described in detail. Compared to the traditional demodulating way with two LIAs in cascade, this tandem LIA eliminates the extra quantization error of redundant analog-to-digital and digital-to-analog conversions and removes the limitation to the time constant in the commercial LIA, hence lowers the requirement of frequency ratio in dual-modulated spectroscopy. The applications are given as examples in the photoreflectance (PR) measurements of GaAs (100) thin film and GaSb bulk material, respectively, at the different optical energy regions. The experimental results indicate that this tandem is well capable of PR spectra measurement with good PR lineshapes and reasonable signal noise ratio. A brief comparison of GaAs PR results between tandem LIA and two LIAs is made to prove the efficiency and advantages of the tandem LIA.
Implementation of comprehensive address generator for digital signal processor
Kini, Ramesh M.; David, Sumam S.
2013-03-01
The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log 2 N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.
Murakami, T.; Ohira, H. (Mitsubishi Electric Corp., Tokyo (Japan))
1991-12-20
A description is given on the internationally standardized animation coding system, and existing and next generation type image processing digital signal processor (DSP) architectures. The internationally standardized animation coding system stratifies images into segments of picture element, frame, and block, with each stratum given exclusive processing. A TV conference and a TV telephone conversation require a huge amount of animation image data. To process these data on a real-time basis, the current video image processing system takes a multi DSP configuration. Methods to split the loads and allocate each load fixedly to each DSP are classified into splitting the loads in the units of coding processing function, the object images, and the loads according to amounts of loads to be calculated. These splitting methods are applied to each stratum processing. The process and splitting corresponding to each stratum processing improved the efficiency. Since the method is a software-based processing, it can be applied not only to the irternationally standardized system, but also to the vector quantization system. Although the present LSI technology is not sufficiently capable to mount the architectures meeting the stratified configuration on one chip, an architecture that specializes the functions in each stratum has a possibility to serve as one chip DSP. 14 refs., 5 figs., 4 tabs.
Digital Radar-Signal Processors Implemented in FPGAs
Berkun, Andrew; Andraka, Ray
2004-01-01
High-performance digital electronic circuits for onboard processing of return signals in an airborne precipitation- measuring radar system have been implemented in commercially available field-programmable gate arrays (FPGAs). Previously, it was standard practice to downlink the radar-return data to a ground station for postprocessing a costly practice that prevents the nearly-real-time use of the data for automated targeting. In principle, the onboard processing could be performed by a system of about 20 personal- computer-type microprocessors; relative to such a system, the present FPGA-based processor is much smaller and consumes much less power. Alternatively, the onboard processing could be performed by an application-specific integrated circuit (ASIC), but in comparison with an ASIC implementation, the present FPGA implementation offers the advantages of (1) greater flexibility for research applications like the present one and (2) lower cost in the small production volumes typical of research applications. The generation and processing of signals in the airborne precipitation measuring radar system in question involves the following especially notable steps: The system utilizes a total of four channels two carrier frequencies and two polarizations at each frequency. The system uses pulse compression: that is, the transmitted pulse is spread out in time and the received echo of the pulse is processed with a matched filter to despread it. The return signal is band-limited and digitally demodulated to a complex baseband signal that, for each pulse, comprises a large number of samples. Each complex pair of samples (denoted a range gate in radar terminology) is associated with a numerical index that corresponds to a specific time offset from the beginning of the radar pulse, so that each such pair represents the energy reflected from a specific range. This energy and the average echo power are computed. The phase of each range bin is compared to the previous echo
Optimal Parallel Algorithms for Two Processor Scheduling with Tree Precedence Constraints
Ernst W. Mayr; Hans Stadtherr
2016-01-01
Consider the problem of finding a minimum length schedule for an unit execution time tasks on m processors with tree-like precedence constraints. A sequential algorithm can solve this problem in linear time. The fastest known parallel algorithm needs O(log n) time using n^2 processors. For the case m=2 we present two work optimal parallel algorithms that produce greedy optimal schedules for intrees and outtrees. Both run in O(log n) time using n/(log n) processors of an EREW PRAM.
Liang, Xiao; Binghe, Sun; Yueping, Ma; Ruyan, Zhao
2013-05-01
A digital spectrometer for low-field magnetic resonance imaging is described. A digital signal processor (DSP) is utilized as the pulse programmer on which a pulse sequence is executed as a subroutine. Field programmable gate array (FPGA) devices that are logically mapped into the external addressing space of the DSP work as auxiliary controllers of gradient control, radio frequency (rf) generation, and rf receiving separately. The pulse programmer triggers an event by setting the 32-bit control register of the corresponding FPGA, and then the FPGA automatically carries out the event function according to preset configurations in cooperation with other devices; accordingly, event control of the spectrometer is flexible and efficient. Digital techniques are in widespread use: gradient control is implemented in real-time by a FPGA; rf source is constructed using direct digital synthesis technique, and rf receiver is constructed using digital quadrature detection technique. Well-designed performance is achieved, including 1 μs time resolution of the gradient waveform, 1 μs time resolution of the soft pulse, and 2 MHz signal receiving bandwidth. Both rf synthesis and rf digitalization operate at the same 60 MHz clock, therefore, the frequency range of transmitting and receiving is from DC to ~27 MHz. A majority of pulse sequences have been developed, and the imaging performance of the spectrometer has been validated through a large number of experiments. Furthermore, the spectrometer is also suitable for relaxation measurement in nuclear magnetic resonance field.
Liang, Xiao; Binghe, Sun; Yueping, Ma; Ruyan, Zhao
2013-05-01
A digital spectrometer for low-field magnetic resonance imaging is described. A digital signal processor (DSP) is utilized as the pulse programmer on which a pulse sequence is executed as a subroutine. Field programmable gate array (FPGA) devices that are logically mapped into the external addressing space of the DSP work as auxiliary controllers of gradient control, radio frequency (rf) generation, and rf receiving separately. The pulse programmer triggers an event by setting the 32-bit control register of the corresponding FPGA, and then the FPGA automatically carries out the event function according to preset configurations in cooperation with other devices; accordingly, event control of the spectrometer is flexible and efficient. Digital techniques are in widespread use: gradient control is implemented in real-time by a FPGA; rf source is constructed using direct digital synthesis technique, and rf receiver is constructed using digital quadrature detection technique. Well-designed performance is achieved, including 1 μs time resolution of the gradient waveform, 1 μs time resolution of the soft pulse, and 2 MHz signal receiving bandwidth. Both rf synthesis and rf digitalization operate at the same 60 MHz clock, therefore, the frequency range of transmitting and receiving is from DC to ˜27 MHz. A majority of pulse sequences have been developed, and the imaging performance of the spectrometer has been validated through a large number of experiments. Furthermore, the spectrometer is also suitable for relaxation measurement in nuclear magnetic resonance field.
Low-power, real-time digital video stabilization using the HyperX parallel processor
Hunt, Martin A.; Tong, Lin; Bindloss, Keith; Zhong, Shang; Lim, Steve; Schmid, Benjamin J.; Tidwell, J. D.; Willson, Paul D.
2011-06-01
Coherent Logix has implemented a digital video stabilization algorithm for use in soldier systems and small unmanned air / ground vehicles that focuses on significantly reducing the size, weight, and power as compared to current implementations. The stabilization application was implemented on the HyperX architecture using a dataflow programming methodology and the ANSI C programming language. The initial implementation is capable of stabilizing an 800 x 600, 30 fps, full color video stream with a 53ms frame latency using a single 100 DSP core HyperX hx3100TM processor running at less than 3 W power draw. By comparison an Intel Core2 Duo processor running the same base algorithm on a 320x240, 15 fps stream consumes on the order of 18W. The HyperX implementation is an overall 100x improvement in performance (processing bandwidth increase times power improvement) over the GPP based platform. In addition the implementation only requires a minimal number of components to interface directly to the imaging sensor and helmet mounted display or the same computing architecture can be used to generate software defined radio waveforms for communications links. In this application, the global motion due to the camera is measured using a feature based algorithm (11 x 11 Difference of Gaussian filter and Features from Accelerated Segment Test) and model fitting (Random Sample Consensus). Features are matched in consecutive frames and a control system determines the affine transform to apply to the captured frame that will remove or dampen the camera / platform motion on a frame-by-frame basis.
Yang, Yuxing; Yin, Dongyuan; Freyer, Richard
2002-07-01
This paper presents a digital signal processor (DSP)-based new multichannel electrocardiogram (ECG) system for 12-lead synchronization ECG automatic analysis in real-time with high sampling rate at 1000 Hz and 12-bits precision. Using the hardware structure of double-CPU based on Microprocessor (MPU) 89C55 and DSP TMS320F206 combines the powerful control ability of MPU with DSPs fast computation ability. Fully utilizing the double-CPUs resource, the system can distribute the reasonable CPU-time for the real-time tasks of multichannel synchronization ECG sampling, digital filter, data storing, waveform automatic analysis and print at high sampling rate. The digital ECG system has the advantages of simple structure, sampling with high speed and precision, powerful real-time processing ability and good quality. The paper discusses the system's principle and the skilful hardware design, also gives the ECG processing using the fast simple integer-coefficient filter method and the automatic calculation algorithms of the ECG parameters such as heart rate, P-R interval, Q-T interval and deflexion angle of ECG-axis etc. The system had been successfully tested and used in the ECG automatic analysis instrument.
FPGA implementation of digital down converter using CORDIC algorithm
Agarwal, Ashok; Lakshmi, Boppana
2013-01-01
In radio receivers, Digital Down Converters (DDC) are used to translate the signal from Intermediate Frequency level to baseband. It also decimates the oversampled signal to a lower sample rate, eliminating the need of a high end digital signal processors. In this paper we have implemented architecture for DDC employing CORDIC algorithm, which down converts an IF signal of 70MHz (3G) to 200 KHz baseband GSM signal, with an SFDR greater than 100dB. The implemented architecture reduces the hardware resource requirements by 15 percent when compared with other architecture available in the literature due to elimination of explicit multipliers and a quadrature phase shifter for mixing.
Implementation of Low-Memory Reference FFT on Digital Signal Processor
Yi-Pin Hsu
2008-01-01
Full Text Available Problem statement: In order to improve and implement Fast Fourier Transform (FFT, in general, an efficient parallel form in digital signal processor is necessary. The butterfly structure is an important role in FFT, because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even though recent research which calls as Novel Memory Reference Reduction Methods (NMRRM for FFT focus on reduce memory reference in twiddle factor, the data-dependent property still exists. Approach:In this study, we propose an approach for FFT implementation on DSP from analog device company (ADI which is based on data-independent property and still hold the property of low-memory reference. We have applied the proposed method of radix-2 FFT algorithm in low-memory reference on ADI BlackFin561 DSP. Results: Experimental results show the method can reduce 44.36% clock cycles comparing with the NMRRM FFT implementation and keep the low-memory reference property. Conclusions/Recommendations: From our algorithm, the results can be accepted and realized for DSP-based embedded system. In further, we will try to implement on different DSP-based system in order to improve the algorithm values.
Neural network surface acoustic wave RF signal processor for digital modulation recognition.
Kavalov, Dimitar; Kalinin, Victor
2002-09-01
An architecture of a surface acoustic wave (SAW) processor based on an artificial neural network is proposed for an automatic recognition of different types of digital passband modulation. Three feed-forward networks are trained to recognize filtered and unfiltered binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK) signals, as well as unfiltered BPSK, QPSK, and 16 quadrature amplitude (16QAM) signals. Performance of the processor in the presence of additive white Gaussian noise (AWGN) is simulated. The influence of second-order effects in SAW devices, phase, and amplitude errors on the performance of the processor also is studied.
Roundoff noise analysis for digital signal power processors using Welch's power spectrum estimation
Chi, Chong-Yung; Long, David; Li, Fuk-Kwok
1987-01-01
The noise due to finite-word-length effects is analyzed for digital-signal power processors using Welch's power-spectrum estimation technique to measure the power of Gaussian random signals over a frequency band of interest. The input of the digital signal processor contains a finite-length time interval in which the true Gaussian signal is contaminated by Gaussian noise. The roundoff noise-to-signal ratio in the measurement of the signal power is derived, and computer simulations which validate the analytical results are presented. These results can be used in tradeoff studies of hardware design, such as the number of bits required at each processing stage. The results presented in this paper are currently being used in the design of a digital Doppler processor (Chi et al., 1986) for a radar scatterometer.
Portable laser speckle perfusion imaging system based on digital signal processor.
Tang, Xuejun; Feng, Nengyun; Sun, Xiaoli; Li, Pengcheng; Luo, Qingming
2010-12-01
The ability to monitor blood flow in vivo is of major importance in clinical diagnosis and in basic researches of life science. As a noninvasive full-field technique without the need of scanning, laser speckle contrast imaging (LSCI) is widely used to study blood flow with high spatial and temporal resolution. Current LSCI systems are based on personal computers for image processing with large size, which potentially limit the widespread clinical utility. The need for portable laser speckle contrast imaging system that does not compromise processing efficiency is crucial in clinical diagnosis. However, the processing of laser speckle contrast images is time-consuming due to the heavy calculation for enormous high-resolution image data. To address this problem, a portable laser speckle perfusion imaging system based on digital signal processor (DSP) and the algorithm which is suitable for DSP is described. With highly integrated DSP and the algorithm, we have markedly reduced the size and weight of the system as well as its energy consumption while preserving the high processing speed. In vivo experiments demonstrate that our portable laser speckle perfusion imaging system can obtain blood flow images at 25 frames per second with the resolution of 640 × 480 pixels. The portable and lightweight features make it capable of being adapted to a wide variety of application areas such as research laboratory, operating room, ambulance, and even disaster site.
Dillier, N; Bögli, H; Spillmann, T
1993-01-01
The following processing strategies have been implemented on an experimental laboratory system of a cochlear implant digital speech processor (CIDSP) for the Nucleus 22-channel cochlear prosthesis. The first approach (PES, Pitch Excited Sampler) is based on the maximum peak channel vocoder concept whereby the time-varying spectral energy of a number of frequency bands is transformed into electrical stimulation parameters for up to 22 electrodes. The pulse rate at any electrode is controlled by the voice pitch of the input speech signal. The second approach (CIS, Continuous Interleaved Sampler) uses a stimulation pulse rate which is independent of the input signal. The algorithm continuously scans all specified frequency bands (typically between four and 22) and samples their energy levels. As only one electrode can be stimulated at any instance of time, the maximally achievable rate of stimulation is limited by the required stimulus pulse widths (determined individually for each subject) and some additional constraints and parameters. A number of variations of the CIS approach have, therefore, been implemented which either maximize the number of quasi-simultaneous stimulation channels or the pulse rate on a reduced number of electrodes. Evaluation experiments with five experienced cochlear implant users showed significantly better performance in consonant identification tests with the new processing strategies than with the subjects' own wearable speech processors; improvements in vowel identification tasks were rarely observed. Modifications of the basic PES- and CIS strategies resulted in large variations of identification scores. Information transmission analysis of confusion matrices revealed a rather complex pattern across conditions and speech features. Optimization and fine-tuning of processing parameters for these coding strategies will require more data both from speech identification and discrimination evaluations and from psychophysical experiments.
Implementation of directional Doppler techniques using a digital signal processor.
Aydin, N; Evans, D H
1994-07-01
Three methods of deriving directional signals from phase quadrature Doppler signals, using digital techniques, are described. These are the phasing-filter technique, the Weaver receiver technique and the complex FFT. The basic theory behind the three methods is presented, together with the results of digital simulations. Each of the methods has been implemented in real time using a commercially available digital signal-processing board, and their relative processing times are compared. All the methods work well, and the decision to implement one or other in a specific application is likely to rest on secondary factors, such as the need to tape-record the time domain output.
The risk of utilizing SEE sensitive COTS digital signal processor (DSP) devices in space
Koga, R.; Crawford, K.B.; Hansel, S.J.; Crain, W.R.; Penzin, S.H. [Aerospace Corp., Los Angeles, CA (United States); Miller, S.W. [OSC, Dulles, VA (United States)
1996-12-01
Digital signal processors (DSPs) sensitive to SEE may be utilized in some space-borne systems, in which the effects of cosmic-rays and trapped protons are limited. Thorough ground testing for SEE is essential in designing an SEE tolerant system, with a minimized risk factor.
Low-Energy Real-Time OS Using Voltage Scheduling Algorithm for Variable Voltage Processors
Okuma, Takanori; Yasuura, Hiroto
2001-01-01
This paper presents a real-time OS based on $ mu $ITRON using proposed voltage scheduling algorithm for variable voltage processors which can vary supply voltage dynamically. The proposed voltage scheduling algorithms assign voltage level for each task dynamically in order to minimize energy consumption under timing constraints. Using the presented real-time OS, running tasks with low supply voltage leads to drastic energy reduction. In addition, the presented voltage scheduling algorithm is ...
DFT algorithms for bit-serial GaAs array processor architectures
Mcmillan, Gary B.
1988-01-01
Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.
Littlefield, R.J.; Maschhoff, K.J.
1991-04-01
Many linear algebra algorithms utilize an array of processors across which matrices are distributed. Given a particular matrix size and a maximum number of processors, what configuration of processors, i.e., what size and shape array, will execute the fastest The answer to this question depends on tradeoffs between load balancing, communication startup and transfer costs, and computational overhead. In this paper we analyze in detail one algorithm: the blocked factored Jacobi method for solving dense eigensystems. A performance model is developed to predict execution time as a function of the processor array and matrix sizes, plus the basic computation and communication speeds of the underlying computer system. In experiments on a large hypercube (up to 512 processors), this model has been found to be highly accurate (mean error {approximately} 2%) over a wide range of matrix sizes (10 {times} 10 through 200 {times} 200) and processor counts (1 to 512). The model reveals, and direct experiment confirms, that the tradeoffs mentioned above can be surprisingly complex and counterintuitive. We propose decision procedures based directly on the performance model to choose configurations for fastest execution. The model-based decision procedures are compared to a heuristic strategy and shown to be significantly better. 7 refs., 8 figs., 1 tab.
Riza, Nabeel A; Reza, Syed Azer
2008-06-01
For the first time, to the best of our knowledge, the design and demonstration of a programmable spectral filtering processor is presented that simultaneously engages the power of an analog-mode optical device such as an acousto-optic tunable filter and a digital-mode optical device such as the digital micromirror device. The demonstrated processor allows a high 50 dB attenuation dynamic range across the chosen 1530-1565 nm (~C band). The hybrid analog-digital spectral control mechanism enables the processor to operate with greater versatility when compared to analog- or digital-only processor designs. Such a processor can be useful both as a test instrument in biomedical applications and as an equalizer in fiber communication networks.
Processor for high-density digital tape-recorded signals
Ashlock, J. C.
1973-01-01
Linear filter and detection theory can bear on problem of reconstructing recorded bit stream. Problem can be taken from realm of nonlinear problems even though basic record process is still recognized as highly nonlinear. Digital tape recorder can be modeled as particular type of linear communication channel with intersymbol interference.
Kriegler, F. J.; Gordon, M. F.; Mclaughlin, R. H.; Marshall, R. E.
1975-01-01
The MIDAS (Multivariate Interactive Digital Analysis System) processor is a high-speed processor designed to process multispectral scanner data (from Landsat, EOS, aircraft, etc.) quickly and cost-effectively to meet the requirements of users of remote sensor data, especially from very large areas. MIDAS consists of a fast multipipeline preprocessor and classifier, an interactive color display and color printer, and a medium scale computer system for analysis and control. The system is designed to process data having as many as 16 spectral bands per picture element at rates of 200,000 picture elements per second into as many as 17 classes using a maximum likelihood decision rule.
Quantization analysis of the real-time SAR digital image formation processor
Magotra, N.
1988-12-01
This report presents a quantization analysis of the digital image formation processor (IFP) of a linear-FM synthetic aperture radar (SAR). The IFP is configured as a patch processor and forms the final image by performing a two dimensional Fast Fourier Transform (FFT). The quantization analysis examines the effects of using fixed precision arithmetic in the image formation process. Theoretical bounds for the worst-case errors introduced by using fixed point arithmetic and experimental results verifying the theoretical bounds are presented. 34 refs., 23 figs., 7 tabs.
Julián Cote
2011-12-01
Full Text Available En este artículo se presentan los principales resultados de la evaluación que se llevó a cabo relacionada con la implementación del método de optimización PSO de convergencia garantizada en topología alternante con el método simplex, en un procesador digital de señales (DSP. Se comparó desempeño con funciones de prueba convencionalmente utilizadas en la evaluación de algoritmos de optimización. Se hizo la programación en el DSP confirmando la viabilidad de su implementación en este tipo de dispositivo caracterizado por ser transportable, de reducido tamaño, flexibilidad y bajo costo. No obstante este logro, se encontró que su mayor tiempo de cómputo sigue siendo aún su principal debilidad, al menos con el tipo de funciones probadas.This article shows the main results of an evaluation related to the implementation of the convergence PSO method assured in alternating topology with the simplex method, in a Digital Signal Processor (DSP. Comparisons on the performance of testing functions conventionally used for the evaluation of optimization algorithms were made. A programming was executed on the DSP confirming the feasibility of its implementation in this kind of device characterized by its small size, low cost, and portable feature. Despite this achievement, it was found that its longest computation time is still its main weakness, at least with the kind of functions tested.
Distributed digital signal processors for multi-body flexible structures
Lee, Gordon K. F.
1992-01-01
Multi-body flexible structures, such as those currently under investigation in spacecraft design, are large scale (high-order) dimensional systems. Controlling and filtering such structures is a computationally complex problem. This is particularly important when many sensors and actuators are located along the structure and need to be processed in real time. This report summarizes research activity focused on solving the signal processing (that is, information processing) issues of multi-body structures. A distributed architecture is developed in which single loop processors are employed for local filtering and control. By implementing such a philosophy with an embedded controller configuration, a supervising controller may be used to process global data and make global decisions as the local devices are processing local information. A hardware testbed, a position controller system for a servo motor, is employed to illustrate the capabilities of the embedded controller structure. Several filtering and control structures which can be modeled as rational functions can be implemented on the system developed in this research effort. Thus the results of the study provide a support tool for many Control/Structure Interaction (CSI) NASA testbeds such as the Evolutionary model and the nine-bay truss structure.
Impact of device level faults in a digital avionic processor
Suk, Ho Kim
1989-01-01
This study describes an experimental analysis of the impact of gate and device-level faults in the processor of a Bendix BDX-930 flight control system. Via mixed mode simulation, faults were injected at the gate (stuck-at) and at the transistor levels and, their propagation through the chip to the output pins was measured. The results show that there is little correspondence between a stuck-at and a device-level fault model, as far as error activity or detection within a functional unit is concerned. In so far as error activity outside the injected unit and at the output pins are concerned, the stuck-at and device models track each other. The stuck-at model, however, overestimates, by over 100 percent, the probability of fault propagation to the output pins. An evaluation of the Mean Error Durations and the Mean Time Between Errors at the output pins shows that the stuck-at model significantly underestimates (by 62 percent) the impact of an internal chip fault on the output pins. Finally, the study also quantifies the impact of device fault by location, both internally and at the output pins.
A full parallel radix sorting algorithm for multicore processors
Maus, Arne
2011-01-01
The problem addressed in this paper is that we want to sort an integer array a [] of length n on a multi core machine with k cores. Amdahl’s law tells us that the inherent sequential part of any algorithm will in the end dominate and limit the speedup we get from parallelisation of that algorithm. This paper introduces PARL, a parallel left radix sorting algorithm for use on ordinary shared memory multi core machines, that has just one simple statement in its sequential part. It can be seen a...
付航; 章秀华; 贺武
2015-01-01
To rea1ize fast running of the mu1ti-view deb1urring a1gorithm in sma11 devices, apara11e1 optimiza-tion a1gorithm was proposed.TMS320C6657 dua1-core digita1 signa1 processor (DSP) was used as the primary computing chip, and the CCSv5.2 was used as the software deve1opment environment. To so1ve the prob1em of time consume of the sing1e core, the time of each sub-function in the a1gorithm was ana1yzed by using the time stamp counter. Then the a1gorithm of matrix mu1tip1ication that consumes the 1ongest time in the sub-function was optimized by dividing into two parts using a dividing point, and the amount of ca1cu1ation was assigned to the two cores of DSP equa11y to ensure the a1gorithm run in para11e1. The resu1ts show that the so1ving method of the dividing point is correct and effective; the running time of the DSP is reduced signifi-cantly by the optimized a1gorithm of mu1ti-view deb1urring and the operation efficiency is improved.%为了实现多视点去模糊算法在小型设备上快速运行,提出了一种并行优化的方法.采用TMS320C6657双核数字信号处理器(DSP,Digita1 signa1 processor)作为主要运算芯片,使用CCSv5.2作为软件开发环境.为了解决算法在单核上运行时间长的问题,首先使用时间戳计数器对算法中各部分功能函数的运行时间进行了详细的统计和分析；然后将运行时间最长的子函数中矩阵相乘部分的算法进行了优化,采用一个分界点将矩阵相乘部分算法划分为两块,将计算量均等的分配到DSP的两个核心上,使这部分算法能够同时在两个核心上并行运算.结果表明对分界点的求解是正确有效的；优化后的图像去模糊算法极大的缩短了DSP上的运算时间,提高了运算效率.
A unified approach to VLSI layout automation and algorithm mapping on processor arrays
Venkateswaran, N.; Pattabiraman, S.; Srinivasan, Vinoo N.
1993-01-01
Development of software tools for designing supercomputing systems is highly complex and cost ineffective. To tackle this a special purpose PAcube silicon compiler which integrates different design levels from cell to processor arrays has been proposed. As a part of this, we present in this paper a novel methodology which unifies the problems of Layout Automation and Algorithm Mapping.
Demonstration of two-qubit algorithms with a superconducting quantum processor.
DiCarlo, L; Chow, J M; Gambetta, J M; Bishop, Lev S; Johnson, B R; Schuster, D I; Majer, J; Blais, A; Frunzio, L; Girvin, S M; Schoelkopf, R J
2009-07-09
Quantum computers, which harness the superposition and entanglement of physical states, could outperform their classical counterparts in solving problems with technological impact-such as factoring large numbers and searching databases. A quantum processor executes algorithms by applying a programmable sequence of gates to an initialized register of qubits, which coherently evolves into a final state containing the result of the computation. Building a quantum processor is challenging because of the need to meet simultaneously requirements that are in conflict: state preparation, long coherence times, universal gate operations and qubit readout. Processors based on a few qubits have been demonstrated using nuclear magnetic resonance, cold ion trap and optical systems, but a solid-state realization has remained an outstanding challenge. Here we demonstrate a two-qubit superconducting processor and the implementation of the Grover search and Deutsch-Jozsa quantum algorithms. We use a two-qubit interaction, tunable in strength by two orders of magnitude on nanosecond timescales, which is mediated by a cavity bus in a circuit quantum electrodynamics architecture. This interaction allows the generation of highly entangled states with concurrence up to 94 per cent. Although this processor constitutes an important step in quantum computing with integrated circuits, continuing efforts to increase qubit coherence times, gate performance and register size will be required to fulfil the promise of a scalable technology.
Performance of parallel linear algebra algorithms on an interleaved array processor
Wolf, G.
1986-01-01
This thesis investigates the performance of numerical algorithms that take advantage of the unique properties of a new type of array processor. This processor, called an Interleaved Array Processor (IAP), is characterized by its ability to use multiple Programmable Functional Units (PFU's) with local data and instruction memories. Unlike conventional array processors, which can only execute simple arithmetic vector operations such as addition and multiplication, the IAP can execute complex vector operations defined by the user. These operations are specified by small programs that can contain conditional branching as well as arithmetic and data movement instructions in each processor. The author calls these programs High-Level Vector Operations (HLVO's). Ways to partition the algorithms and the data among the processing units in the system are presented so that in such a way that the computation time in every processing unit is increased, and at the same time the data movement on the system bus, is reduced. In this way the bus can be timeshared among several functional units, allowing several operations on different vector components to be executed simultaneously and overlapped with the transfer of operands and results.
Burst digital correlator as laser-Doppler velocimetry signal processor.
Ikeda, Y; Nakajima, T
1996-06-20
A burst digital correlator (BDC) has been developed to obtain flow-velocity information at high data rates from wideband laser-Doppler signals of low signal-to-noise ratio (below 0 dB). Results with artificial signals show that, over a signal bandwidth of 5-120 MHz, the BDC has a measurement accuracy of less than 0.4% at a maximum data rate (number of measurements per second) of 208 kHz when 64 signal samples are correlated. The accuracy is better than 0.05% with a sample size of 512. The performance of the BDC was also evaluated in practical measurements of near-wall and strongly oscillatory recirculating flows.
Design of an ultra-low-power digital processor for passive UHF RFID tags
Shi Wanggen; Zhuang Yiqi; Li Xiaoming; Wang Xianghua; Jin Zhao; Wang Dan
2009-01-01
A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed.This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption.By applying methods like system-level power management,global clock gating and low voltage implementation,the total power of the design is reduced to a few microwatts.In addition,an innovative way for the design of a true RNG is presented,which contributes to both low power and secure data transaction.The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows.The design fits different CMOS technologies and has been taped out using the 2P4M 0.35μm process of Chartered Semiconductor.
PMSM Control System Based on Digital Signal Processor
Zhu Jun
2013-04-01
Full Text Available For the high power density of PMSM, designed the corresponding drive controller to improve the servo efficiency of PMSM servo system. According to the theory of math model of PMSM under the dq coordinate system, applied id = 0 vector control method as a PMSM control strategy, established PMSM controller model based on vector control. Taking DSP TMS320F2812 as controller core, built a power-driven circuit, control circuit and the main detection protection circuit. The algorithm of control program was completed on the hardware platform to present its software processes. The simulation results show that: the control system response is fast, can track the given speed and position quickly and accurately. The speed fluctuation, overshoot and steady state error are very small. The designed controller is reasonable, which has better dynamic and static characteristics, and be benefit to improve the efficiency of PMSM servo system.
Floating-to-Fixed-Point Conversion for Digital Signal Processors
Menard Daniel
2006-01-01
Full Text Available Digital signal processing applications are specified with floating-point data types but they are usually implemented in embedded systems with fixed-point arithmetic to minimise cost and power consumption. Thus, methodologies which establish automatically the fixed-point specification are required to reduce the application time-to-market. In this paper, a new methodology for the floating-to-fixed point conversion is proposed for software implementations. The aim of our approach is to determine the fixed-point specification which minimises the code execution time for a given accuracy constraint. Compared to previous methodologies, our approach takes into account the DSP architecture to optimise the fixed-point formats and the floating-to-fixed-point conversion process is coupled with the code generation process. The fixed-point data types and the position of the scaling operations are optimised to reduce the code execution time. To evaluate the fixed-point computation accuracy, an analytical approach is used to reduce the optimisation time compared to the existing methods based on simulation. The methodology stages are described and several experiment results are presented to underline the efficiency of this approach.
Characterization of three digital signal processor systems used in gamma ray spectrometry.
Reguigui, N; Morel, J; Kraiem, H Ben; Mahjoub, A
2002-01-01
Various manufacturers have recently introduced digital signal processing systems that allow data acquisition in gamma spectrometry at high-input counting rates (several thousand pulses per second). In these systems, the signal digitization is performed immediately following the preamplification stage. This allows digital shaping and filtering of the signal which increases the number of possible combinations in signal shaping and as a consequence, optimizes the resolution as a function of the detector characteristics and the counting rate. Basic characteristic parameters of three digital signal processors that were recently introduced in the market have been studied and compared to those of an analog system. This study is carried out using a hyper-pure coaxial type germanium detector and 57Co, 60Co and 137Cs radioactive sources. Performance parameters such as energy resolution, system throughput, and counting losses that are due to dead time and pile-up effects are presented and discussed.
Ghosh, A
1988-08-01
Lanczos and conjugate gradient algorithms are important in computational linear algebra. In this paper, a parallel pipelined realization of these algorithms on a ring of optical linear algebra processors is described. The flow of data is designed to minimize the idle times of the optical multiprocessor and the redundancy of computations. The effects of optical round-off errors on the solutions obtained by the optical Lanczos and conjugate gradient algorithms are analyzed, and it is shown that optical preconditioning can improve the accuracy of these algorithms substantially. Algorithms for optical preconditioning and results of numerical experiments on solving linear systems of equations arising from partial differential equations are discussed. Since the Lanczos algorithm is used mostly with sparse matrices, a folded storage scheme to represent sparse matrices on spatial light modulators is also described.
McWilliams, T.; Widdoes, Jr., L. C.; Wood, L.
1976-09-30
The design of an extremely high performance programmable digital filter of novel architecture, the LLL Programmable Digital Filter, is described. The digital filter is a high-performance multiprocessor having general purpose applicability and high programmability; it is extremely cost effective either in a uniprocessor or a multiprocessor configuration. The architecture and instruction set of the individual processor was optimized with regard to the multiple processor configuration. The optimal structure of a parallel processing system was determined for addressing the specific Navy application centering on the advanced digital filtering of passive acoustic ASW data of the type obtained from the SOSUS net. 148 figures. (RWR)
Ressler, Johann; Dirscherl, Andreas; Grothe, Helmut; Wolf, Bernhard
2007-02-01
In many cases of bioanalytical measurement, calculation of large amounts of data, analysis of complex signal waveforms or signal speed can overwhelm the performance of microcontrollers, analog electronic circuits or even PCs. One method to obtain results in real time is to apply a digital signal processor (DSP) for the analysis or processing of measurement data. In this paper we show how DSP-supported multiplying and accumulating (MAC) operations, such as time/frequency transformation, pattern recognition by correlation, convolution or filter algorithms, can optimize the processing of bioanalytical data. Discrete integral calculations are applied to the acquisition of impedance values as part of multi-parametric sensor chips, to pH monitoring using light-addressable potentiometric sensors (LAPS) and to the analysis of rapidly changing signal shapes, such as action potentials of cultured neuronal networks, as examples of DSP capability.
Genetic Algorithms for Digital Quantum Simulations.
Las Heras, U; Alvarez-Rodriguez, U; Solano, E; Sanz, M
2016-06-10
We propose genetic algorithms, which are robust optimization techniques inspired by natural selection, to enhance the versatility of digital quantum simulations. In this sense, we show that genetic algorithms can be employed to increase the fidelity and optimize the resource requirements of digital quantum simulation protocols while adapting naturally to the experimental constraints. Furthermore, this method allows us to reduce not only digital errors but also experimental errors in quantum gates. Indeed, by adding ancillary qubits, we design a modular gate made out of imperfect gates, whose fidelity is larger than the fidelity of any of the constituent gates. Finally, we prove that the proposed modular gates are resilient against different gate errors.
Genetic Algorithms for Digital Quantum Simulations
Las Heras, U.; Alvarez-Rodriguez, U.; Solano, E.; Sanz, M.
2016-06-01
We propose genetic algorithms, which are robust optimization techniques inspired by natural selection, to enhance the versatility of digital quantum simulations. In this sense, we show that genetic algorithms can be employed to increase the fidelity and optimize the resource requirements of digital quantum simulation protocols while adapting naturally to the experimental constraints. Furthermore, this method allows us to reduce not only digital errors but also experimental errors in quantum gates. Indeed, by adding ancillary qubits, we design a modular gate made out of imperfect gates, whose fidelity is larger than the fidelity of any of the constituent gates. Finally, we prove that the proposed modular gates are resilient against different gate errors.
MATLAB fitting for overcurrent relay and a new digital algorithm study
ZHANG Xiao-ming
2005-01-01
The overcurrent (OC) protection limit is set usually accorging to a OC protection setting table on digital integrated protection equipment in mine explode isolation high voltage (HV) vacuum switch. For digital integrated protection equipment, OC protection setting table must be converted to be a microcomputer algorithm. This paper first introduced a method of the fitting OC protection setting table to be OC relay inverse time characteristics equations using MATLAB least square fitting. On the basis of analyzing these fitting equations, a notion, "integral limit rate" was put forward initially and a OC inverse time digital algorithm was developed. MATLAB simulation results and a digital signal processor (DSP) based digital integrated protection equipment running test indicate that this algorithm has less calculation amount, less taking up memory, high control accuracy,implements the no-grade setting of OC delay values, suits for all kinds of low-middle microcomputer system implementation.
Parallel Algorithms for Medical Informatics on Data-Parallel Many-Core Processors
Moazeni, Maryam
2013-01-01
The extensive use of medical monitoring devices has resulted in the generation of tremendous amounts of data. Storage, retrieval, and analysis of such data require platforms that can scale with data growth and adapt to the various behavior of the analysis and processing algorithms. In recent years, many-core processors and more specifically many-core Graphical Processing Units (GPUs) have become one of the most promising platforms for high performance processing of data, due to the massive pa...
INTELLIGENT CONTROL SYSTEM OF PULSED MAG WELDING INVERTER BASED ON DIGITAL SIGNAL PROCESSOR
无
2008-01-01
A fuzzy logic intelligent control system of pulsed MAG welding inverter based on digital signal processor (DSP) is proposed to obtain the consistency of arc length in pulsed MAG welding. The proposed control system combines the merits of intelligent control with DSP digital control. The fuzzy logic intelligent control system designed is a typical two-input-single-output structure, and regards the error and the change in error of peak arc voltage as two inputs and the background time as single output. The fuzzy logic intelligent control system is realized in a look-up table (LUT) method by using MATLAB based fuzzy logic toolbox, and the implement of LUT method based on DSP is also discussed. The pulsed MAG welding experimental results demonstrate that the developed fuzzy logic intelligent control system based on DSP has strong arc length controlling ability to accomplish the stable pulsed MAG welding process and controls pulsed MAG welding inverter digitally and intelligently.
Scheduling Algorithm: Tasks Scheduling Algorithm for Multiple Processors with Dynamic Reassignment
Pradeep Kumar Yadav
2008-01-01
Full Text Available Distributed computing systems [DCSs] offer the potential for improved performance and resource sharing. To make the best use of the computational power available, it is essential to assign the tasks dynamically to that processor whose characteristics are most appropriate for the execution of the tasks in distributed processing system. We have developed a mathematical model for allocating “M” tasks of distributed program to “N” multiple processors (M>N that minimizes the total cost of the program. Relocating the tasks from one processor to another at certain points during the course of execution of the program that contributes to the total cost of the running program has been taken into account. Phasewise execution cost [EC], intertask communication cost [ITCT], residence cost [RC] of each task on different processors, and relocation cost [REC] for each task have been considered while preparing a dynamic tasks allocation model. The present model is suitable for arbitrary number of phases and processors with random program structure.
Development of moving target detection algorithm using ADSP TS201 DSP Processor
Babu rao Kodavati
2010-08-01
Full Text Available This paper presents detect the presence of a target within a specified range(2 to 30m. The present work generally relates to a radar system and more particularly, to improve range resolution (3 m and minimum detection time (2 msec. Speed and accuracy are two important evaluation indicators in target detecting system. The challenges in developing the algorithm is finding the Doppler frequency and give caution signal to chief at an optimum instant of time to cause target kill. Time management serves to maintain a priority queue of all the tasks. In this work we have taken up issue of developing an algorithm using ADSP TS 201 DSP Processor.
Digital-signal-processor-based dynamic imaging system for optical tomography.
Lasker, Joseph M; Masciotti, James M; Schoenecker, Matthew; Schmitz, Christoph H; Hielscher, Andreas H
2007-08-01
In this article, we introduce a dynamic optical tomography system that is, unlike currently available analog instrumentation, based on digital data acquisition and filtering techniques. At the core of this continuous wave instrument is a digital signal processor (DSP) that collects, collates, processes, and filters the digitized data set. The processor is also responsible for managing system timing and the imaging routines which can acquire real-time data at rates as high as 150 Hz. Many of the synchronously timed processes are controlled by a complex programmable logic device that is also used in conjunction with the DSP to orchestrate data flow. The operation of the system is implemented through a comprehensive graphical user interface designed with LABVIEW software which integrates automated calibration, data acquisition, data organization, and signal postprocessing. Performance analysis demonstrates very low system noise (approximately 1 pW rms noise equivalent power), excellent signal precision (<0.04%-0.2%) and long term system stability (<1% over 40 min). A large dynamic range (approximately 190 dB) accommodates a wide scope of measurement geometries and tissue types. First experiments on tissue phantoms show that dynamic behavior is accurately captured and spatial location can be correctly tracked using this system.
Control of a PWM Rectifier with Extended Functions in a Signal Digital Processor
C. Núñez–Gutiérrez
2009-01-01
Full Text Available This work presents the application of a digital signal processor (DSP for the control of a three–phase PWM rectifier for industrial applications, to which are extended their functions to have capacity to compensate voltage sags. The study stands out the advantages that the DSP offers to control, based on the system transformation from fix reference frame to synchronous reference frame (D–Q theory and classical controllers. The analysis of the system is presented, as well as simulation and experimental results to validate the operation of the DSP as system element controller.
A novel algorithm combining oversampling and digital lock-in amplifier of high speed and precision.
Li, Gang; Zhou, Mei; He, Feng; Lin, Ling
2011-09-01
Because of a large amount of arithmetic in the standard digital lock-in detection, a high performance processor is needed to implement the algorithm in real time. This paper presents a novel algorithm that integrates oversampling and high-speed lock-in detection. The algorithm sets the sampling frequency as a whole-number multiple of four of the input signal frequency, and then uses the common downsampling technology to lower the sampling frequency to four times of the input signal frequency. It could effectively remove the noise interference and improve the detection accuracy. After that the phase sensitive detector is implemented. It simply does the addition and subtraction on four points in the period of same phase and replaces almost all the multiplication operations to speed up digital lock-in detection calculation substantially. Furthermore, the correction factor is introduced to improve the calculation accuracy of the amplitude, and an error caused by the algorithm in theory can be eliminated completely. The results of the simulation and actual experiments show that the novel algorithm combining digital lock-in detection and oversampling not only has the high precision, but also has the unprecedented speed. In our work, the new algorithm is suitable for the real-time weak signal detection in the general microprocessor not just digital signal processor.
Meghana Hasamnis
2012-06-01
Full Text Available Embedded system design is becoming complex day by day, combined with reduced time-to-market deadlines. Due to the constraints and complexity in the design of embedded systems, it incorporates hardware / software co-design methodology. An embedded system is a combination of hardware and software parts integrated together on a common platform. A soft-core processor which is a hardware description language (HDL model of a specific processor (CPU can be customized for any application and can be synthesized for FPGA target. This paper gives a comparative analysis of the development environment for embedded systems using LEON 3 and NIOS II Processor, both soft core processors. LEON3 is an open source processor and NIOS II is a commercial processor. Case study under consideration is Rijindael’s Encryption Algorithm (AES. It is a standard encryption algorithm used to encrypt huge bulk of data and for security. Using the co-design methodology the algorithm is implemented on two different platforms. One using the open source and other using the commercial processor and the comparative results of the two different platforms is stated in terms of its performance parameters. The algorithm is partitioned in hardware and software parts and integrated on a common platform.
Comparison between Two Text Digital Watermarking Algorithms
TANG Sheng; XUE Xu-ce
2011-01-01
In this paper,two text digital watermarking methods are compared in the context of their robustness performances.A nonlinear watermarking algorithm embeds the watermark into the reordered DCT coefficients of a text image,and utilizes a nonlinear detector to detect the watermark in some attacks.Compared with the classical watermarking algorithm,experimental results show that this nonlinear watennarking nlgorithm has some potential merits.
Generic-type hierarchical multi digital signal processor system for hard-field tomography.
Garcia Castillo, Sergio; Ozanyan, Krikor B
2007-05-01
This article introduces the design and implementation of a hierarchical multi digital signal processor system aimed to perform parallel multichannel measurements and data processing of the type widely used in hard-field tomography. Details are presented of a complete tomography system with modular and expandable architecture, capable of accommodating a variety of data processing modalities, configured by software. The configuration of the acquisition and processing circuits and the management of the data flow allow a data frame rate of up to 250 kHz. Results of a case study, guided path tomography for temperature mapping, are shown as a direct demonstration of the system's capabilities. Digital lock-in detection is employed for data processing to extract the information from ac measurements of the temperature-induced resistance changes in an array of 32 noninteracting transducers, which is further exported for visualization.
Generic-type hierarchical multi digital signal processor system for hard-field tomography
Garcia Castillo, Sergio; Ozanyan, Krikor B.
2007-05-01
This article introduces the design and implementation of a hierarchical multi digital signal processor system aimed to perform parallel multichannel measurements and data processing of the type widely used in hard-field tomography. Details are presented of a complete tomography system with modular and expandable architecture, capable of accommodating a variety of data processing modalities, configured by software. The configuration of the acquisition and processing circuits and the management of the data flow allow a data frame rate of up to 250kHz. Results of a case study, guided path tomography for temperature mapping, are shown as a direct demonstration of the system's capabilities. Digital lock-in detection is employed for data processing to extract the information from ac measurements of the temperature-induced resistance changes in an array of 32 noninteracting transducers, which is further exported for visualization.
Real Time Phase Noise Meter Based on a Digital Signal Processor
Angrisani, Leopoldo; D'Arco, Mauro; Greenhall, Charles A.; Schiano Lo Morille, Rosario
2006-01-01
A digital signal-processing meter for phase noise measurement on sinusoidal signals is dealt with. It enlists a special hardware architecture, made up of a core digital signal processor connected to a data acquisition board, and takes advantage of a quadrature demodulation-based measurement scheme, already proposed by the authors. Thanks to an efficient measurement process and an optimized implementation of its fundamental stages, the proposed meter succeeds in exploiting all hardware resources in such an effective way as to gain high performance and real-time operation. For input frequencies up to some hundreds of kilohertz, the meter is capable both of updating phase noise power spectrum while seamlessly capturing the analyzed signal into its memory, and granting as good frequency resolution as few units of hertz.
Mitra, Avik; Ghosh, Arindam; Das, Ranabir; Patel, Apoorva; Kumar, Anil
2005-12-01
Quantum adiabatic algorithm is a method of solving computational problems by evolving the ground state of a slowly varying Hamiltonian. The technique uses evolution of the ground state of a slowly varying Hamiltonian to reach the required output state. In some cases, such as the adiabatic versions of Grover's search algorithm and Deutsch-Jozsa algorithm, applying the global adiabatic evolution yields a complexity similar to their classical algorithms. However, using the local adiabatic evolution, the algorithms given by J. Roland and N.J. Cerf for Grover's search [J. Roland, N.J. Cerf, Quantum search by local adiabatic evolution, Phys. Rev. A 65 (2002) 042308] and by Saurya Das, Randy Kobes, and Gabor Kunstatter for the Deutsch-Jozsa algorithm [S. Das, R. Kobes, G. Kunstatter, Adiabatic quantum computation and Deutsh's algorithm, Phys. Rev. A 65 (2002) 062301], yield a complexity of order N (where N=2(n) and n is the number of qubits). In this paper, we report the experimental implementation of these local adiabatic evolution algorithms on a 2-qubit quantum information processor, by Nuclear Magnetic Resonance.
Sato, T. [Max Co. Ltd., Tokyo (Japan)
1999-03-15
A digital control development effort is introduced, citing a case of DSP (digital signal processor)-aided DC servo motor control for the flat head type pen plotter. In a real plotter, a complicated nonlinear problem will arise because the natural frequency varies dependent upon the pen position. For the inhibition of such vibration which occurs during acceleration and deceleration, nonlinear elements have to be taken into consideration at the designing stage. In this report, the effort is focused on motor axis control only, and the DC servo control problem is solved as a linear problem. A DSP board type DS1102 of the dSPACE Corporation is named for this work. Using this board, the C code is automatically generated out of a control block constructed through SIMULINK, and a real-time test is conducted after downloading the code to the DSP processor. Since the quantity of DC servo motor rotation is quantized in an encoder, the result would contain much error and cause instability in the control if the quantity as obtained was subjected to differential calculus. Such being the case, velocity data for the control in this report are acquired by use of an observer. (NEDO)
IMAGEP - A FORTRAN ALGORITHM FOR DIGITAL IMAGE PROCESSING
Roth, D. J.
1994-01-01
IMAGEP is a FORTRAN computer algorithm containing various image processing, analysis, and enhancement functions. It is a keyboard-driven program organized into nine subroutines. Within the subroutines are other routines, also, selected via keyboard. Some of the functions performed by IMAGEP include digitization, storage and retrieval of images; image enhancement by contrast expansion, addition and subtraction, magnification, inversion, and bit shifting; display and movement of cursor; display of grey level histogram of image; and display of the variation of grey level intensity as a function of image position. This algorithm has possible scientific, industrial, and biomedical applications in material flaw studies, steel and ore analysis, and pathology, respectively. IMAGEP is written in VAX FORTRAN for DEC VAX series computers running VMS. The program requires the use of a Grinnell 274 image processor which can be obtained from Mark McCloud Associates, Campbell, CA. An object library of the required GMR series software is included on the distribution media. IMAGEP requires 1Mb of RAM for execution. The standard distribution medium for this program is a 1600 BPI 9track magnetic tape in VAX FILES-11 format. It is also available on a TK50 tape cartridge in VAX FILES-11 format. This program was developed in 1991. DEC, VAX, VMS, and TK50 are trademarks of Digital Equipment Corporation.
Implementation Issues for Algorithmic VLSI (Very Large Scale Integration) Processor Arrays.
1984-10-01
analysis of the various algorithms are described in Appendiccs 5.A, 5.B and 5.C. A note on notation: Following Ottmann ei aL [40], the variable n is used...redundant operations OK. Ottmann log i I log 1 up to n wasted processors. X-tree topology. Atallah log n I 1 redundant operations OK. up to n wasted...for Computing Machinery 14(2):203-241, April, 1967. 40] Thomas A. Ottmann , Arnold L. Rosenberg and Larry J. Stockmeyer. A dictionary machine (for VLSI
Kim, W E; Ahn, J M; Choi, S W; Min, B G
1997-01-01
An intelligent Li Ion battery management (ILBM) system was developed based on a digital signal processor (DSP). Instead of using relatively complicated hardware charging control, a DSP algorithm was used, and favorable characteristics in volume, mass, and temperature increase of the implantable battery were achieved. In vitro tests were performed to evaluate the DSP based algorithm for Li Ion charging control (24 V dc motor input power 16 W, 5 L/min, 100 mmHg afterload). In this article, the first improvement was volume reduction using a Li Ion battery (3.6 V/Cell, 900 mA, seven cells: 25.2 V, 22.7 W). Its volume and mass were decreased by 40% and 50% respectively (40*55*75 mm, 189 g), compared to previously reported results, with total energy capacity increased by 110% (more than 60 min vs 25 min run time in the other battery). The second improvement includes the ILBM, which can control the performance detection for each unit cell and has a low temperature rise. The ILBM's unit cell energy detection was important because the low performance of one cell dropped to 50% of the total performance along with a 20% increase in surface temperature. All electronics for a transcutaneous energy transmission (TET), battery, and telemetry were finalized for hybridization and used for total artificial heat (TAH) implantation.
Kessel, Alexander R.; Yakovleva, Natalia M.
2002-01-01
Schemes of experimental realization of the main two qubit processors for quantum computers and Deutsch-Jozsa algorithm are derived in virtual spin representation. The results are applicable for every four quantum states allowing the required properties for quantum processor implementation if for qubit encoding virtual spin representation is used. Four dimensional Hilbert space of nuclear spin 3/2 is considered in details for this aim
Chadha, Aman; Bhatia, M G
2011-01-01
This paper describes the design and simulation of an 8-bit dedicated processor for calculating the Sine and Cosine of an Angle using CORDIC Algorithm (COordinate Rotation DIgital Computer), a simple and efficient algorithm to calculate hyperbolic and trigonometric functions. We have proposed a dedicated processor system, modeled by writing appropriate programs in VHDL, for calculating the Sine and Cosine of an angle. System simulation was carried out using ModelSim 6.3f and Xilinx ISE Design Suite 12.3. A maximum frequency of 81.353 MHz was reached with a minimum period of 12.292 ns. 126 (3%) slices were used. This paper attempts to survey the existing CORDIC algorithm with an eye towards implementation in Field Programmable Gate Arrays (FPGAs). A brief description of the theory behind the algorithm and the derivation of the Sine and Cosine of an angle using the CORDIC algorithm has been presented. The system can be implemented using Spartan3 XC3S400 with Xilinx ISE 12.3 and VHDL.
Digital and discrete geometry theory and algorithms
Chen, Li
2014-01-01
This book provides comprehensive coverage of the modern methods for geometric problems in the computing sciences. It also covers concurrent topics in data sciences including geometric processing, manifold learning, Google search, cloud data, and R-tree for wireless networks and BigData.The author investigates digital geometry and its related constructive methods in discrete geometry, offering detailed methods and algorithms. The book is divided into five sections: basic geometry; digital curves, surfaces and manifolds; discretely represented objects; geometric computation and processing; and a
QuickProbs--a fast multiple sequence alignment algorithm designed for graphics processors.
Gudyś, Adam; Deorowicz, Sebastian
2014-01-01
Multiple sequence alignment is a crucial task in a number of biological analyses like secondary structure prediction, domain searching, phylogeny, etc. MSAProbs is currently the most accurate alignment algorithm, but its effectiveness is obtained at the expense of computational time. In the paper we present QuickProbs, the variant of MSAProbs customised for graphics processors. We selected the two most time consuming stages of MSAProbs to be redesigned for GPU execution: the posterior matrices calculation and the consistency transformation. Experiments on three popular benchmarks (BAliBASE, PREFAB, OXBench-X) on quad-core PC equipped with high-end graphics card show QuickProbs to be 5.7 to 9.7 times faster than original CPU-parallel MSAProbs. Additional tests performed on several protein families from Pfam database give overall speed-up of 6.7. Compared to other algorithms like MAFFT, MUSCLE, or ClustalW, QuickProbs proved to be much more accurate at similar speed. Additionally we introduce a tuned variant of QuickProbs which is significantly more accurate on sets of distantly related sequences than MSAProbs without exceeding its computation time. The GPU part of QuickProbs was implemented in OpenCL, thus the package is suitable for graphics processors produced by all major vendors.
QuickProbs—A Fast Multiple Sequence Alignment Algorithm Designed for Graphics Processors
Gudyś, Adam; Deorowicz, Sebastian
2014-01-01
Multiple sequence alignment is a crucial task in a number of biological analyses like secondary structure prediction, domain searching, phylogeny, etc. MSAProbs is currently the most accurate alignment algorithm, but its effectiveness is obtained at the expense of computational time. In the paper we present QuickProbs, the variant of MSAProbs customised for graphics processors. We selected the two most time consuming stages of MSAProbs to be redesigned for GPU execution: the posterior matrices calculation and the consistency transformation. Experiments on three popular benchmarks (BAliBASE, PREFAB, OXBench-X) on quad-core PC equipped with high-end graphics card show QuickProbs to be 5.7 to 9.7 times faster than original CPU-parallel MSAProbs. Additional tests performed on several protein families from Pfam database give overall speed-up of 6.7. Compared to other algorithms like MAFFT, MUSCLE, or ClustalW, QuickProbs proved to be much more accurate at similar speed. Additionally we introduce a tuned variant of QuickProbs which is significantly more accurate on sets of distantly related sequences than MSAProbs without exceeding its computation time. The GPU part of QuickProbs was implemented in OpenCL, thus the package is suitable for graphics processors produced by all major vendors. PMID:24586435
QuickProbs--a fast multiple sequence alignment algorithm designed for graphics processors.
Adam Gudyś
Full Text Available Multiple sequence alignment is a crucial task in a number of biological analyses like secondary structure prediction, domain searching, phylogeny, etc. MSAProbs is currently the most accurate alignment algorithm, but its effectiveness is obtained at the expense of computational time. In the paper we present QuickProbs, the variant of MSAProbs customised for graphics processors. We selected the two most time consuming stages of MSAProbs to be redesigned for GPU execution: the posterior matrices calculation and the consistency transformation. Experiments on three popular benchmarks (BAliBASE, PREFAB, OXBench-X on quad-core PC equipped with high-end graphics card show QuickProbs to be 5.7 to 9.7 times faster than original CPU-parallel MSAProbs. Additional tests performed on several protein families from Pfam database give overall speed-up of 6.7. Compared to other algorithms like MAFFT, MUSCLE, or ClustalW, QuickProbs proved to be much more accurate at similar speed. Additionally we introduce a tuned variant of QuickProbs which is significantly more accurate on sets of distantly related sequences than MSAProbs without exceeding its computation time. The GPU part of QuickProbs was implemented in OpenCL, thus the package is suitable for graphics processors produced by all major vendors.
Texas Instruments-Digital Signal Processor(TI-DSP)SMJ320F20 SEL Testing
Sanders, Anthony B.; Poivey, C.; Kim, H. S.; Gee, George B.
2006-01-01
This viewgraph presentation reviews the testing of the Texas Instrument Digital Signal Processor(TI-DSP)SMJ320F20. Tests were performed to screen for susceptibility to Single Event Latchup (SEL) and measure sensitivity as a function of Linear Energy Transfer (LET) for an application specific test setup. The Heavy Ion Testing of two TI-DSP SMJ320F240 devices experienced Single Event Latchup (SEL) conditions at an LET of 1.8 MeV/(mg/square cm) The devices were exposed from a fluence of 1.76 x l0(exp 3) to 5.00 x 10(exp 6) particles/square cm of the Neon, Argon and Krypton ion beams. For DI(sub DD) an average latchup current occurred at about 700mA, which is a magnitude of 10 over the nominal current of 700mA.
Real time measurement of RR intervals using a digital signal processor.
Buttfield, A C; Bolton, M P
2005-01-01
The accurate measurement of beat to beat intervals is essential for subsequent heart rate variability analysis. Where the ECG is used to derive the intervals, timing can be affected by artefacts such as muscle noise, electrode instability and also shape changes in the QRS complex. Identifying the QRS time by correlation methods can minimize the uncertainty but the method is computationally intensive. We have developed a real time RR interval measurement system using a correlation technique running on a low cost digital signal processor (TMS320C31). Sampling rate is 1 KHz. Timing resolution is +/- 1 ms. The correlation process uses an averaged complex from the actual ECG and has an adaptive noise threshold. The high processing speed of a DSP has proved ideal for accurate RR interval measurement. The system is described and test results with various signal to noise ratios and different types of noise are presented.
Demonstrations of analog-to-digital conversion using a frequency domain stretched processor.
Reibel, Randy Ray; Harrington, Calvin; Dahl, Jason; Ostrander, Charles; Roos, Peter Aaron; Berg, Trenton; Mohan, R Krishna; Neifeld, Mark A; Babbitt, Wm R
2009-07-06
The first proof-of-concept demonstrations are presented for a broadband photonic-assisted analog-to-digital converter (ADC) based on spatial spectral holography (SSH). The SSH-ADC acts as a frequency-domain stretch processor converting high bandwidth input signals to low bandwidth output signals, allowing the system to take advantage of high performance, low bandwidth electronic ADCs. Demonstrations with 50 MHz effective bandwidth are shown to highlight basic performance with approximately 5 effective bits of vertical resolution. Signal capture with 1600 MHz effective bandwidth is also shown. Because some SSH materials span over 100 GHz and have large time apertures (approximately 10 micros), this technique holds promise as a candidate for the next generation of ADCs.
Passive all-optical polarization switch, binary logic gates, and digital processor.
Zaghloul, Y A; Zaghloul, A R M; Adibi, A
2011-10-10
We introduce the passive all-optical polarization switch, which modulates light with light. That switch is used to construct all the binary logic gates of two or more inputs. We discuss the design concepts and the operation of the AND, OR, NAND, and NOR gates as examples. The rest of the 16 logic gates are similarly designed. Cascading of such gates is straightforward as we show and discuss. Cascading in itself does not require a power source, but feedback at this stage of development does. The design and operation of an SR Latch is presented as one of the popular basic sequential devices used for memory cells. That completes the essential components of an all-optical polarization digital processor. The speed of such devices is well above 10 GHz for bulk implementations and is much higher for chip-size implementations. In addition, the presented devices do have the four essential characteristics previously thought unique to the microelectronic ones.
Implementation of the SITAN algorithm in the digital terrain management and display system
Cambron, T.M.; Snyder, F.B.; Fellerhoff, J.R.
1985-01-01
This paper describes the functional methodologies and development processes used to integrate the SITAN autonomous navigation algorithm with the Digital Terrain Management and Display System (DTMDS) for real-time demonstrations aboard the AFTI/F-16 aircraft. Heretofore, the SITAN algorithm has not been implemented for real-time operation aboard a military aircraft. The paper describes the implementation design of the DTMDS and how the elevation data base supported by the digital map generator subsystem is made available to the SITAN algorithm. The effects of aircraft motion as related to SITAN algorithm timing and processor loading are evaluated. The closed-loop implementation with the AFTI aircraft inertial navigation system (INS) was specifically selected for the initial demonstration.
Cosmo-SkyMed Di Seconda Generazione Innovative Algorithms and High Performance SAR Data Processors
Mari, S.; Porfilio, M.; Valentini, G.; Serva, S.; Fiorentino, C. A. M.
2016-08-01
In the frame of COSMO-SkyMed di Seconda Generazione (CSG) programme, extensive research activities have been conducted on SAR data processing, with particular emphasis on high resolution processors, wide field products noise and coregistration algorithms.As regards the high resolution, it is essential to create a model for the management of all those elements that are usually considered as negligible but alter the target phase responses when it is "integrated" for several seconds. Concerning the SAR wide-field products noise removal, one of the major problems is the ability compensate all the phenomena that affect the received signal intensity. Research activities are aimed at developing adaptive- iterative techniques for the compensation of inaccuracies on the knowledge of radar antenna pointing, up to achieve compensation of the order of thousandths of degree. Moreover, several modifications of the image coregistration algortithm have been studied aimed at improving the performences and reduce the computational effort.
Suarez, R; Aalseth, C E; Hossbach, T W; Miley, H S
2007-01-01
Pulse-shape analysis of the ionization signals from germanium gamma-ray spectrometers is a method for obtaining information that can characterize an event beyond just the total energy deposited in the crystal. However, as typically employed, this method is data-intensive requiring the digitization, transfer, and recording of electronic signals from the spectrometer. A hardware realization of a real-time digital signal processor for implementing a parametric pulse shape is presented. Specifically, a previously developed method for distinguishing between single-site and multi-site gamma-ray interactions is demonstrated in an on-line digital signal processor, compared with the original off-line pulse-shape analysis routine, and shown to have no significant difference. Reduction of the amount of the recorded information per event is shown to translate into higher duty-cycle data acquisition rates while retaining the benefits of additional event characterization from pulse-shape analysis.
Digital Readout System for Micromachined Gyroscope and Analysis for its Demodulation Algorithm
ZHOU Bin; GAO Zhong-yu; CHEN Huai; ZHANG Rong; CHEN Zhi-yong
2006-01-01
A new digital readout system for micromachined gyroscope has been proposed to implement flexible parameter adiustment,improve the control performance of gyroscope,and make error compensation.By digitalizing the output of the gyroscope,this system uses a floatingtype digital signal processor(DSP)to process the signal demodulation and achieve the feedback conffol of the gyroscope.Therefore.the small change of capacitance in the micromachined gyroscope Can be detected.A new demodulation algorithm of least mean square demodulation(LMSD)has been developed inside DSP Simulation and measurement results show that LMSD Can improve 29%of the noise performance compared with the typical multiplication method.In air pressure.a kind ofvibration-wheel micmmachined over the 100-Hz bandwidth by using this digital readout technology.
DATA BYPASSING ARCHITECTURE AND CIRCUIT DESIGN FOR 32-BIT DIGITAL SIGNAL PROCESSOR
Chen Xiaoyi; Yao Qingdong; Liu Peng
2005-01-01
This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.
Efficient Implementation of Elliptic Curve Cryptography Using Low-power Digital Signal Processor
Malik, Muhammad Yasir
2011-01-01
RSA(Rivest, Shamir and Adleman)is being used as a public key exchange and key agreement tool for many years. Due to large numbers involved in RSA, there is need for more efficient methods in implementation for public key cryptosystems. Elliptic Curve Cryptography(ECC) is based on elliptic curves defined over a finite field. Elliptic curve cryptosystems(ECC) were discovered by Victor Miller and Neal Koblitz in 1985.This paper comprises of five sections. Section I is introduction to ECC and its components. Section II describes advantages of ECC schemes and its comparison with RSA. Section III is about some of the applications of ECC. Section IV gives some embedded implementations of ECC. Section V contains ECC implementation on fixed point Digital Signal Processor(TMS320VC5416). ECC was implemented using general purpose microcontrollers and Field Programmable Gate Arrays (FPGA) before this work. DSP is more powerful than microcontrollers and much economical than FPGA. So this implementation can be efficiently u...
数字化X线医学图像增强处理器研究%Research on digital X-ray medical images enhancement processor
林创鲁; 程韬波; 周松斌; 黄可嘉
2011-01-01
Many digital medical images suffer from lack of contrast and sharpness, and hard to differentiate original dark object from low illumination area. In order to improve the accuracy of clinical diagnosis, Multi-Scales Retinex (MSR) algorithm based on human perception theory is used for images enhancement. Development of a Digital Signal Processor (DSP) implementation X-ray medical images enhancement is designed. Experimetal result shows that the processor can meet clinical diagnosis need preliminary.%针对x线医学图像存在的对比度低、暗部细节模糊、视觉效果不佳而难以提高临床诊断准确率等问题,采用基于人眼视觉理论的多尺度Retinex算法的X线医学图像增强方法,设计了基于高性能DM643芯片的X线医学图像增强处理器.实验结果表明,该处理器能有效压缩图像动态范围、提高对比度和暗部区域的可视度,初步满足临床诊断应用的要求.
Chen, Ming-Chih; Hsiao, Shen-Fu
In this paper, we propose an area-efficient design of Advanced Encryption Standard (AES) processor by applying a new common-expression-elimination (CSE) method to the sub-functions of various transformations required in AES. The proposed method reduces the area cost of realizing the sub-functions by extracting the common factors in the bit-level XOR/AND-based sum-of-product expressions of these sub-functions using a new CSE algorithm. Cell-based implementation results show that the AES processor with our proposed CSE method has significant area improvement compared with previous designs.
The Introduction and Use of Digital Audio Processor%数字声频处理器及使用
熊坚
2015-01-01
在分析数字声频处理器的特点、功能、基本结构、性能指标的基础上，介绍目前国内外常用的数字声频处理器品牌的功能和适用范围，特别提示针对不同应用场合、不同使用方式的使用技巧。%This paper introduced the function and applicable scope of the digital audio processor which were commonly used brands at home and abroad, on the basis of analysing the characteristics, function, basic structure and performance index of the digital audio processor, especially for the use skills in different applications and different usage modes.
New efficient algorithm for recognizing handwritten Hindi digits
El-Sonbaty, Yasser; Ismail, Mohammed A.; Karoui, Kamal
2001-12-01
In this paper a new algorithm for recognizing handwritten Hindi digits is proposed. The proposed algorithm is based on using the topological characteristics combined with statistical properties of the given digits in order to extract a set of features that can be used in the process of digit classification. 10,000 handwritten digits are used in the experimental results. 1100 digits are used for training and another 5500 unseen digits are used for testing. The recognition rate has reached 97.56%, a substitution rate of 1.822%, and a rejection rate of 0.618%.
A digital-signal-processor-based optical tomographic system for dynamic imaging of joint diseases
Lasker, Joseph M.
Over the last decade, optical tomography (OT) has emerged as viable biomedical imaging modality. Various imaging systems have been developed that are employed in preclinical as well as clinical studies, mostly targeting breast imaging, brain imaging, and cancer related studies. Of particular interest are so-called dynamic imaging studies where one attempts to image changes in optical properties and/or physiological parameters as they occur during a system perturbation. To successfully perform dynamic imaging studies, great effort is put towards system development that offers increasingly enhanced signal-to-noise performance at ever shorter data acquisition times, thus capturing high fidelity tomographic data within narrower time periods. Towards this goal, I have developed in this thesis a dynamic optical tomography system that is, unlike currently available analog instrumentation, based on digital data acquisition and filtering techniques. At the core of this instrument is a digital signal processor (DSP) that collects, collates, and processes the digitized data set. Complementary protocols between the DSP and a complex programmable logic device synchronizes the sampling process and organizes data flow. Instrument control is implemented through a comprehensive graphical user interface which integrates automated calibration, data acquisition, and signal post-processing. Real-time data is generated at frame rates as high as 140 Hz. An extensive dynamic range (˜190 dB) accommodates a wide scope of measurement geometries and tissue types. Performance analysis demonstrates very low system noise (˜1 pW rms noise equivalent power), excellent signal precision (˜0.04%--0.2%) and long term system stability (˜1% over 40 min). Experiments on tissue phantoms validate spatial and temporal accuracy of the system. As a potential new application of dynamic optical imaging I present the first application of this method to use vascular hemodynamics as a means of characterizing
Chakrabartty, Shantanu; Shaga, Ravi K; Aono, Kenji
2013-04-01
Analog circuits that are calibrated using digital-to-analog converters (DACs) use a digital signal processor-based algorithm for real-time adaptation and programming of system parameters. In this paper, we first show that this conventional framework for adaptation yields suboptimal calibration properties because of artifacts introduced by quantization noise. We then propose a novel online stochastic optimization algorithm called noise-shaping or ΣΔ gradient descent, which can shape the quantization noise out of the frequency regions spanning the parameter adaptation trajectories. As a result, the proposed algorithms demonstrate superior parameter search properties compared to floating-point gradient methods and better convergence properties than conventional quantized gradient-methods. In the second part of this paper, we apply the ΣΔ gradient descent algorithm to two examples of real-time digital calibration: 1) balancing and tracking of bias currents, and 2) frequency calibration of a band-pass Gm-C biquad filter biased in weak inversion. For each of these examples, the circuits have been prototyped in a 0.5-μm complementary metal-oxide-semiconductor process, and we demonstrate that the proposed algorithm is able to find the optimal solution even in the presence of spurious local minima, which are introduced by the nonlinear and non-monotonic response of calibration DACs.
A microprogrammable versatile processor (MVP) for digital signal and data processing
Tsou, H. E.; Nix, W. C.; Weir, E. M.; Smith, J. J.; Kushner, M. L.
A simple, functionally partitioned, data bus-oriented, horizontally-microprogrammed processor architecture has been developed which is ideal for low cost signal processing, emulation, and data processing applications. Due to its functional modularity and bus oriented architecture, new technologies can be inserted without perturbing the design and the support software. The processor has separate RALUs for data processing and address generation and is the first signal processor to use the TRW 16 x 16-bit multiplier and the AMD RALUs. It allows for growth by adding attached arithmetic processors, microprocessors, etc. Support software includes register transfer-level HOL, assembler, loader, linker, diagnostics, library, executive and I/O drivers. Applications include speech processing, coding/decoding, modulation/demodulation, signal processing and emulation.
Clarençon, D; Renaudin, M; Gourmelon, P; Kerckhoeve, A; Catérini, R; Boivin, E; Ellis, P; Hille, B; Fatôme, M
1996-12-01
This paper describes a complete real-time system for EEG signal analysis. Specific software and hardware have been designed to provide biologists with an efficient tool, which allows a complete study of the different states of vigilance as well as the paroxysmal activities. The analysis method which is based on the wavelet transform is first presented and compared to the standard spectral approach. The dedicated digital signal processor card, based on the Motorola 96002 processor chip, that has been designed to support real-time acquisition and real-time processing of EEG signals is then presented. We finally illustrate the proposed method by processing real EEG signals of rats, and show that it opens up new prospects in the domain of EEG-based diagnosis. We propose a new representation, called globalization, that provides a global view and better detection of paroxysmal activities.
Digital Detection and feedback Fluxgate Magnetometer
Piil-Henriksen, J.; Merayo, José M.G.; Nielsen, Otto V;
1996-01-01
A new full Earth's field dynamic feedback fluxgate magnetometer is described. It is based entirely on digital signal processing and digital feedback control, thereby replacing the classical second harmonic tuned analogue electronics by processor algorithms. Discrete mathematical cross...
Mathijssen, R W; Leliveld, W H
1989-01-01
An experimental system for a tactile hearing aid using a digital signal processor (DSP) is being developed. This system can be used to test and evaluate not only the familiar techniques for a tactile hearing aid, such as energy level display, filterbank analysis, etc., but also novel techniques. The system is being developed especially to try out new recognition strategies, because the currently available strategies are not satisfactory. A portable tactile hearing aid that can recognize certain environmental sounds (alarm sounds) and certain features from the speech signal (such as pitch, voiced/voiceless, or even complete phonemes), being a good support for lipreading, should be the final result of the experiments.
A high-speed digital signal processor for atmospheric radar, part 7.3A
Brosnahan, J. W.; Woodard, D. M.
1984-01-01
The Model SP-320 device is a monolithic realization of a complex general purpose signal processor, incorporating such features as a 32-bit ALU, a 16-bit x 16-bit combinatorial multiplier, and a 16-bit barrel shifter. The SP-320 is designed to operate as a slave processor to a host general purpose computer in applications such as coherent integration of a radar return signal in multiple ranges, or dedicated FFT processing. Presently available is an I/O module conforming to the Intel Multichannel interface standard; other I/O modules will be designed to meet specific user requirements. The main processor board includes input and output FIFO (First In First Out) memories, both with depths of 4096 W, to permit asynchronous operation between the source of data and the host computer. This design permits burst data rates in excess of 5 MW/s.
Svetek, A.; Blake, M.; Cepeda Hermida, M.; Dasu, S.; Dodd, L.; Fobes, R.; Gomber, B.; Gorski, T.; Guo, Z.; Klabbers, P.; Levine, A.; Ojalvo, I.; Ruggles, T.; Smith, N.; Smith, W. H.; Tikalsky, J.; Vicente, M.; Woods, N.
2016-02-01
The CMS Level-1 upgraded calorimeter trigger requires a powerful, flexible and compact processing card. The Calorimeter Trigger Processor Card (CTP7) uses the Virtex-7 FPGA as its primary data processor and is the first FPGA based processing card in CMS to employ the ZYNQ System-on-Chip (SoC) running embedded Linux to provide TCP/IP communication and board support functions. The CTP7 was built from the ground up to support AXI infrastructure to provide flexible and modular designs with minimal time from project conception to final implementation.
Xu, Lijun; Liu, Chang; Zheng, Deyan; Cao, Zhang; Cai, Weiwei
2014-12-01
To realize on-line high-accuracy measurement in direct absorption spectroscopy (DAS), a system-on-chip, high-precision digital signal processor-based on-line Voigt lineshape fitting implementation is introduced in this paper. Given that the Voigt lineshape is determined by the Gauss full width at half maximum (FWHM) and Lorentz FWHM, a look-up table, which covers a range of combinations of both, is first built to achieve rapid and accurate calculation of Voigt lineshape. With the look-up table and raw absorbance data in hand, Gauss-Newton nonlinear fitting module is implemented to obtain the parameters including both the Gauss and Lorentz FWHMs, which can be used to calculate the integrated absorbance. To realize the proposed method in hardware, a digital signal processor (DSP) is adopted to fit the Voigt lineshape in a real-time DAS measurement system. In experiment, temperature and H2O concentration of a flat flame are recovered from the transitions of 7444.36 cm(-1) and 7185.6 cm(-1) by the DSP-based on-line Voigt lineshape fitting and on-line integral of the raw absorbance, respectively. The results show that the proposed method can not only fit the Voigt lineshape on-line but also improve the measurement accuracy compared with those obtained from the direct integral of the raw absorbance.
The MATPHOT Algorithm for Digital Point Spread Function CCD Stellar Photometry
Mighell, Kenneth J.
Most CCD stellar photometric reduction packages use analytical functions to represent the stellar Point Spread Function (PSF). These PSF-fitting programs generally compute all the major partial derivatives of the observational model by differentiating the volume integral of the PSF over a pixel. Real-world PSFs are frequently very complicated and may not be exactly representable with any combination of analytical functions. Deviations of the real-world PSF from the analytical PSF are then generally stored in a residual matrix. Diffraction rings and spikes can provide a great deal of information about the position of a star, yet information about such common observational effects generally resides only in the residual matrix. Such useful information is generally not used in the PSF-fitting process except for the final step involving the determination of the chi-square goodness-of-fit between the CCD observation and the model where the intensity-scaled residual matrix is added to the mathematical model of the observation just before the goodness-of-fit is computed. I describe some of the key features of my MATPHOT algorithm for digital PSF-fitting CCD stellar photometry where the PSF is represented by a matrix of numbers. The mathematics of determining the partial derivatives of the observational model with respect to the x and y direction vectors is exactly the same with analytical or digital PSFs. The implementation methodology, however, is quite different. In the case of digital PSFs, the partial derivatives can be determined using numerical differentiation techniques on the digital PSFs. I compare the advantages and disadvantages with respect to traditional PSF-fitting algorithms based on analytical representations of the PSF. The MATPHOT algorithm is an ideal candidate for parallel processing. Instead of operating in the traditional single-processor mode of analyzing one pixel at a time, the MATPHOT algorithm can be written to operate on an image-plane basis
Barnes, Richard; Lehman, Clarence; Mulla, David
2014-01-01
Depressions (or pits) are areas within a digital elevation model that are surrounded by higher terrain, with no outlet to lower areas. Filling them so they are level, as fluid would fill them if the terrain was impermeable, is often necessary in preprocessing DEMs. The depression-filling algorithm presented here - called Priority-Flood - unifies and improves the work of a number of previous authors who have published similar algorithms. The algorithm operates by flooding DEMs inwards from their edges using a priority queue to determine the next cell to be flooded. The resultant DEM has no depressions or digital dams: every cell is guaranteed to drain. The algorithm is optimal for both integer and floating-point data, working in O(n) and O(n log2 n) time, respectively. It is shown that by using a plain queue to fill depressions once they have been found, an O(m log2 m) time-complexity can be achieved, where m does not exceed the number of cells n. This is the lowest time complexity of any known floating-point depression-filling algorithm. In testing, this improved variation of the algorithm performed up to 37% faster than the original. Additionally, a parallel version of an older, but widely used, depression-filling algorithm required six parallel processors to achieve a run-time on par with what the newer algorithm's improved variation took on a single processor. The Priority-Flood Algorithm is simple to understand and implement: the included pseudocode is only 20 lines and the included C++ reference implementation is under a hundred lines. The algorithm can work on irregular meshes as well as 4-, 6-, 8-, and n-connected grids. It can also be adapted to label watersheds and determine flow directions through either incremental elevation changes or depression carving. In the case of incremental elevation changes, the algorithm includes safety checks not present in prior works.
Levesque, Philippe; Sawan, Mohamad
2009-08-01
A fully hardware-based real-time digital wideband quadrature demodulation processor based on the Hilbert transform is proposed to process ultrasound radio frequency signals. The presented architecture combines 2 finite impulse response (FIR) filters to process in-phase and quadrature signals and includes a piecewise linear approximation architecture that performs the required square root operations. The proposed implementation enables flexibility to support different transducers with its ability to load on-the-fly different FIR filter coefficient sets. The complexity and accuracy of the demodulator processor are analyzed with simulated RF data; a normalized residual sum-of-squares cost function is used for comparison with the Matlab Hilbert function. Three implementations are integrated into a hand-held ultrasound system for experimental accuracy and performance evaluation. Real-time images were acquired from a reference phantom, demonstrating the feasibility of using the presented architecture to perform real-time digital quadrature demodulation of ultrasonic signal echoes. Experimental results show that the implementation, using only 2942 slices and 3 dedicated digital multipliers of a low-cost and low-power field-programmable gate array (FPGA) is accurate relative to a comparable software- based system; axial and lateral resolution of 1 mm and 2 mm, respectively, were obtained with a 12-mm piezoelectric transducer without postprocessing. Because the processing and sampling rates are the same, high-frequency ultrasound signals can be processed as well. For a 15-frame-per-second display, the hand-held ultrasonic imaging-processing core (FPGA, memory) requires only 45 mW (dynamic) when using a 5-MHz single-element piezoelectric transducer.
Digital Geometry Algorithms Theoretical Foundations and Applications to Computational Imaging
Barneva, Reneta
2012-01-01
Digital geometry emerged as an independent discipline in the second half of the last century. It deals with geometric properties of digital objects and is developed with the unambiguous goal to provide rigorous theoretical foundations for devising new advanced approaches and algorithms for various problems of visual computing. Different aspects of digital geometry have been addressed in the literature. This book is the first one that explicitly focuses on the presentation of the most important digital geometry algorithms. Each chapter provides a brief survey on a major research area related to the general volume theme, description and analysis of related fundamental algorithms, as well as new original contributions by the authors. Every chapter contains a section in which interesting open problems are addressed.
Digital Media Processing DSP Algorithms Using C
Malepati, Hazarathaiah
2010-01-01
Multimedia processing demands efficient programming in order to optimize functionality. Data, image, audio, and video processing, some or all of which are present in all electronic devices today, are complex programming environments. Optimized algorithms (step-by-step directions) are difficult to create but can make all the difference when developing a new application.This book discusses the most current algorithms available that will maximize your programming keeping in mind the memory and real-time constraints of the architecture with which you are working. A wide range of algorithms is cove
A blind digital signature scheme using elliptic curve digital signature algorithm
BÜTÜN, İsmail; DEMİRER, Mehmet
2013-01-01
In this study, we propose a blind digital signature (BDS) scheme based on the elliptic curve digital signature algorithm that increases the performance significantly. The security of our scheme is based on the difficulty of the elliptic curve discrete algorithm problem. Therefore, it offers much smaller key lengths for the desired security levels, along with much faster cryptographic processes, leading to fewer hardware and software requirements. According to our simulation results, ...
Digital image processing an algorithmic approach with Matlab
Qidwai, Uvais
2009-01-01
Introduction to Image Processing and the MATLAB EnvironmentIntroduction Digital Image Definitions: Theoretical Account Image Properties MATLAB Algorithmic Account MATLAB CodeImage Acquisition, Types, and File I/OImage Acquisition Image Types and File I/O Basics of Color Images Other Color Spaces Algorithmic Account MATLAB CodeImage ArithmeticIntroduction Operator Basics Theoretical TreatmentAlgorithmic Treatment Coding ExamplesAffine and Logical Operations, Distortions, and Noise in ImagesIntroduction Affine Operations Logical Operators Noise in Images Distortions in ImagesAlgorithmic Account
A JPEG-based enhanced compression algorithm of digital holograms
Yu, Hanming; Zhang, Zibang; Zhong, Jingang
2012-11-01
We present a modified version of the general JPEG encoder for digital holograms. Since digital holograms are characterized by most of their information concentrated at first-order term, to compress digital holograms only with their first-order term is available. The proposed algorithm performs 2D-DCT (discrete cosine transform) on digital holograms as the general JPEG, then quantizes and encodes the low-frequency section extracted with an adaptive mask. Compatible with the general JPEG, the compressed holograms can be directly decoded by the general decoders. Our simulation and experimental results show that this algorithm has higher compression ratio than the general JPEG and more accurate retrieved phase while the compression is equal.
Digital Signal Processing Filtering Algorithm : Audio Equalization Using Matlab
Chaguaro Aldaz, Daniel
2015-01-01
The contemporary domain of Digital Signal Processing is in constant influx and trying to find new applications that will benefit the everyday life of ordinary people. In modern technology, most of the electronic processes use DSP algorithms in order to collect analogue information that is continually present all around us and convert it into a digital form. The need of understanding the basics of how these processes occur, has inspired to implement a DSP application for educational and testin...
Genovese, Mariangela; Napoli, Ettore
2013-05-01
The identification of moving objects is a fundamental step in computer vision processing chains. The development of low cost and lightweight smart cameras steadily increases the request of efficient and high performance circuits able to process high definition video in real time. The paper proposes two processor cores aimed to perform the real time background identification on High Definition (HD, 1920 1080 pixel) video streams. The implemented algorithm is the OpenCV version of the Gaussian Mixture Model (GMM), an high performance probabilistic algorithm for the segmentation of the background that is however computationally intensive and impossible to implement on general purpose CPU with the constraint of real time processing. In the proposed paper, the equations of the OpenCV GMM algorithm are optimized in such a way that a lightweight and low power implementation of the algorithm is obtained. The reported performances are also the result of the use of state of the art truncated binary multipliers and ROM compression techniques for the implementation of the non-linear functions. The first circuit has commercial FPGA devices as a target and provides speed and logic resource occupation that overcome previously proposed implementations. The second circuit is oriented to an ASIC (UMC-90nm) standard cell implementation. Both implementations are able to process more than 60 frames per second in 1080p format, a frame rate compatible with HD television.
[Image processing system of visual prostheses based on digital signal processor DM642].
Xie, Chengcheng; Lu, Yanyu; Gu, Yun; Wang, Jing; Chai, Xinyu
2011-09-01
This paper employed a DSP platform to create the real-time and portable image processing system, and introduced a series of commonly used algorithms for visual prostheses. The results of performance evaluation revealed that this platform could afford image processing algorithms to be executed in real time.
Comparative Study of Image Denoising Algorithms in Digital Image Processing
Aarti
2014-05-01
Full Text Available This paper proposes a basic scheme for understanding the fundamentals of digital image processing and the image denising algorithm. There are three basic operation categorized on during image processing i.e. image rectification and restoration, enhancement and information extraction. Image denoising is the basic problem in digital image processing. The main task is to make the image free from Noise. Salt & pepper (Impulse noise and the additive white Gaussian noise and blurredness are the types of noise that occur during transmission and capturing. For denoising the image there are some algorithms which denoise the image.
Comparative Study of Image Denoising Algorithms in Digital Image Processing
Aarti Kumari
2015-11-01
Full Text Available This paper proposes a basic scheme for understanding the fundamentals of digital image processing and the image denising algorithm. There are three basic operation categorized on during image processing i.e. image rectification and restoration, enhancement and information extraction. Image denoising is the basic problem in digital image processing. The main task is to make the image free from Noise. Salt & pepper (Impulse noise and the additive white Gaussian noise and blurredness are the types of noise that occur during transmission and capturing. For denoising the image there are some algorithms which denoise the image.
基于CORDIC算法的FFT处理器设计%Design of FFT Processor Based on CORDIC Algorithm
彭清兵; 李方军
2011-01-01
采用CORDIC算法和无乘法器的蝶形运算操作,建立Matlab函数模型.合理选择迭代级数和运算数据位宽,设计一种新的高信噪比快速傅里叶变换(FFT)处理器.在最优化设计中,信噪比可以达到88 dB,在加入溢出保护设计后,硬件实现的信噪比可以达到80 dB,功耗减少20.63％.仿真结果表明,该处理器具有芯片面积较小、精度高、功耗低、信噪比高等优点.%A Matlab function model is built through using CORDIC algorithm and butterfly operation without multiplier. By choosing reasonable iterative series and the operation data bit width, a novel Fast Fourier Transform(FFT) processor with high Signal Noise Ratio(SNR) is designed. In the Matlab simulation, the SNR can reach 88 dB. After adding the overflow protection, the SNR realized by hardware can reach 80 dB, and the power consumption can be reduced by 20.63%. The designed FFT processor has many advantages such as smaller chip area, high accuracy, lower power consumption and high SNR.
Dombrowski, M. P.; LaBelle, J.; McGaw, D. G.; Broughton, M. C.
2016-07-01
The programmable combined receiver/digital signal processor platform presented in this article is designed for digital downsampling and processing of general waveform inputs with a 66 MHz initial sampling rate and multi-input synchronized sampling. Systems based on this platform are capable of fully autonomous low-power operation, can be programmed to preprocess and filter the data for preselection and reduction, and may output to a diverse array of transmission or telemetry media. We describe three versions of this system, one for deployment on sounding rockets and two for ground-based applications. The rocket system was flown on the Correlation of High-Frequency and Auroral Roar Measurements (CHARM)-II mission launched from Poker Flat Research Range, Alaska, in 2010. It measured auroral "roar" signals at 2.60 MHz. The ground-based systems have been deployed at Sondrestrom, Greenland, and South Pole Station, Antarctica. The Greenland system synchronously samples signals from three spaced antennas providing direction finding of 0-5 MHz waves. It has successfully measured auroral signals and man-made broadcast signals. The South Pole system synchronously samples signals from two crossed antennas, providing polarization information. It has successfully measured the polarization of auroral kilometric radiation-like signals as well as auroral hiss. Further systems are in development for future rocket missions and for installation in Antarctic Automatic Geophysical Observatories.
Rerucha, Simon; Sarbort, Martin; Hola, Miroslava; Cizek, Martin; Hucl, Vaclav; Cip, Ondrej; Lazar, Josef
2016-12-01
The homodyne detection with only a single detector represents a promising approach in the interferometric application which enables a significant reduction of the optical system complexity while preserving the fundamental resolution and dynamic range of the single frequency laser interferometers. We present the design, implementation and analysis of algorithmic methods for computational processing of the single-detector interference signal based on parallel pipelined processing suitable for real time implementation on a programmable hardware platform (e.g. the FPGA - Field Programmable Gate Arrays or the SoC - System on Chip). The algorithmic methods incorporate (a) the single detector signal (sine) scaling, filtering, demodulations and mixing necessary for the second (cosine) quadrature signal reconstruction followed by a conic section projection in Cartesian plane as well as (a) the phase unwrapping together with the goniometric and linear transformations needed for the scale linearization and periodic error correction. The digital computing scheme was designed for bandwidths up to tens of megahertz which would allow to measure the displacements at the velocities around half metre per second. The algorithmic methods were tested in real-time operation with a PC-based reference implementation that employed the advantage pipelined processing by balancing the computational load among multiple processor cores. The results indicate that the algorithmic methods are suitable for a wide range of applications [3] and that they are bringing the fringe counting interferometry closer to the industrial applications due to their optical setup simplicity and robustness, computational stability, scalability and also a cost-effectiveness.
Olariu, S.; Schwing, J.; Zhang, J.
1991-01-01
A bus system that can change dynamically to suit computational needs is referred to as reconfigurable. We present a fast adaptive convex hull algorithm on a two-dimensional processor array with a reconfigurable bus system (2-D PARBS, for short). Specifically, we show that computing the convex hull of a planar set of n points taken O(log n/log m) time on a 2-D PARBS of size mn x n with 3 less than or equal to m less than or equal to n. Our result implies that the convex hull of n points in the plane can be computed in O(1) time in a 2-D PARBS of size n(exp 1.5) x n.
Lennartsson, Per; Nordlander, Lars
2002-01-01
This Master thesis describes the benchmarking of a DSP processor. Benchmarking means measuring the performance in some way. In this report, we have focused on the number of instruction cycles needed to execute certain algorithms. The algorithms we have used in the benchmark are all very common in signal processing today. The results we have reached in this thesis have been compared to benchmarks for other processors, performed by Berkeley Design Technology, Inc. The algorithms were programm...
Lipinski, Piotr
This paper concerns the quadratic three-dimensional assignment problem (Q3AP), an extension of the quadratic assignment problem (QAP), and proposes an efficient hybrid evolutionary algorithm combining stochastic optimization and local search with a number of crossover operators, a number of mutation operators and an auto-adaptation mechanism. Auto-adaptation manages the pool of evolutionary operators applying different operators in different computation phases to better explore the search space and to avoid premature convergence. Local search additionally optimizes populations of candidate solutions and accelerates evolutionary search. It uses a many-core graphics processor to optimize a number of solutions in parallel, which enables its incorporation into the evolutionary algorithm without excessive increases in the computation time. Experiments performed on benchmark Q3AP instances derived from the classic QAP instances proposed by Nugent et al. confirmed that the proposed algorithm is able to find optimal solutions to Q3AP in a reasonable time and outperforms best known results found in the literature.
Wael A. Murtada
2011-01-01
Full Text Available Problem statement: The Software Communications Architecture (SCA was developed to improve software reuse and interoperability in Software Defined Radios (SDR. However, there have been performance concerns since its conception. Arguably, the majority of the problems and inefficiencies associated with the SCA can be attributed to the assumption of modular distributed platforms relying on General Purpose Processors (GPPs to perform all signal processing. Approach: Significant improvements in cost and power consumption can be obtained by utilizing specialized and more efficient platforms. Digital Signal Processors (DSPs present such a platform and have been widely used in the communications industry. Improvements in development tools and middleware technology opened the possibility of fully integrating DSPs into the SCA. This approach takes advantage of the exceptional power, cost and performance characteristics of DSPs, while still enjoying the flexibility and portability of the SCA. Results: This study presents the design and implementation of an SCA Core Framework (CF for a TI TMS320C6416 DSP. The framework is deployed on a C6416 Device Cycle Accurate Simulator and TI C6416 Development board. The SCA CF is implemented by leveraging OSSIE, an open-source implementation of the SCA, to support the DSP platform. OISs ORBExpress DSP and DSP/BIOS are used as the middleware and operating system, respectively. A sample waveform was developed to demonstrate the frameworks functionality. Benchmark results for the framework and sample applications are provided. Conclusion: Benchmark results show that, using OIS ORBExpress DSP ORB middleware has an impact for decreasing the Software Memory Footprint and increasing the System Performance compared with PrismTech's e*ORB middleware.
Foundations of digital signal processing theory, algorithms and hardware design
Gaydecki, Patrick
2005-01-01
An excellent introductory text, this book covers the basic theoretical, algorithmic and real-time aspects of digital signal processing (DSP). Detailed information is provided on off-line, real-time and DSP programming and the reader is effortlessly guided through advanced topics such as DSP hardware design, FIR and IIR filter design and difference equation manipulation.
Algorithms for digital image processing in diabetic retinopathy.
Winder, R J; Morrow, P J; McRitchie, I N; Bailie, J R; Hart, P M
2009-12-01
This work examined recent literature on digital image processing in the field of diabetic retinopathy. Algorithms were categorized into 5 steps (preprocessing; localization and segmentation of the optic disk; segmentation of the retinal vasculature; localization of the macula and fovea; localization and segmentation of retinopathy). The variety of outcome measures, use of a gold standard or ground truth, data sample sizes and the use of image databases is discussed. It is intended that our classification of algorithms into a small number of categories, definition of terms and discussion of evolving techniques will provide guidance to algorithm designers for diabetic retinopathy.
Ge, Shuang-Chao; Deng, Ming; Chen, Kai; Li, Bin; Li, Yuan
2016-12-01
Time-domain induced polarization (TDIP) measurement is seriously affected by power line interference and other field noise. Moreover, existing TDIP instruments generally output only the apparent chargeability, without providing complete secondary field information. To increase the robustness of TDIP method against interference and obtain more detailed secondary field information, an improved dataprocessing algorithm is proposed here. This method includes an efficient digital notch filter which can effectively eliminate all the main components of the power line interference. Hardware model of this filter was constructed and Vhsic Hardware Description Language code for it was generated using Digital Signal Processor Builder. In addition, a time-location method was proposed to extract secondary field information in case of unexpected data loss or failure of the synchronous technologies. Finally, the validity and accuracy of the method and the notch filter were verified by using the Cole-Cole model implemented by SIMULINK software. Moreover, indoor and field tests confirmed the application effect of the algorithm in the fieldwork.
T. von Sydow
2003-01-01
Full Text Available Various reasons like technology progress, flexibility demands, shortened product cycle time and shortened time to market have brought up the possibility and necessity to integrate different architecture blocks on one heterogeneous System-on-Chip (SoC. Architecture blocks like programmable processor cores (DSP- and GPP-kernels, embedded FPGAs as well as dedicated macros will be integral parts of such a SoC. Especially programmable architecture blocks and associated optimization techniques are discussed in this contribution. Design space exploration and thus the choice which architecture blocks should be integrated in a SoC is a challenging task. Crucial to this exploration is the evaluation of the application domain characteristics and the costs caused by individual architecture blocks integrated on a SoC. An ATE-cost function has been applied to examine the performance of the aforementioned programmable architecture blocks. Therefore, representative discrete devices have been analyzed. Furthermore, several architecture dependent optimization steps and their effects on the cost ratios are presented.
Jimenez, Edward Steven,
2013-09-01
The goal of this work is to develop a fast computed tomography (CT) reconstruction algorithm based on graphics processing units (GPU) that achieves significant improvement over traditional central processing unit (CPU) based implementations. The main challenge in developing a CT algorithm that is capable of handling very large datasets is parallelizing the algorithm in such a way that data transfer does not hinder performance of the reconstruction algorithm. General Purpose Graphics Processing (GPGPU) is a new technology that the Science and Technology (S&T) community is starting to adopt in many fields where CPU-based computing is the norm. GPGPU programming requires a new approach to algorithm development that utilizes massively multi-threaded environments. Multi-threaded algorithms in general are difficult to optimize since performance bottlenecks occur that are non-existent in single-threaded algorithms such as memory latencies. If an efficient GPU-based CT reconstruction algorithm can be developed; computational times could be improved by a factor of 20. Additionally, cost benefits will be realized as commodity graphics hardware could potentially replace expensive supercomputers and high-end workstations. This project will take advantage of the CUDA programming environment and attempt to parallelize the task in such a way that multiple slices of the reconstruction volume are computed simultaneously. This work will also take advantage of the GPU memory by utilizing asynchronous memory transfers, GPU texture memory, and (when possible) pinned host memory so that the memory transfer bottleneck inherent to GPGPU is amortized. Additionally, this work will take advantage of GPU-specific hardware (i.e. fast texture memory, pixel-pipelines, hardware interpolators, and varying memory hierarchy) that will allow for additional performance improvements.
Development of a ground signal processor for digital synthetic array radar data
Griffin, C. R.; Estes, J. M.
1981-01-01
A modified APQ-102 sidelooking array radar (SLAR) in a B-57 aircraft test bed is used, with other optical and infrared sensors, in remote sensing of Earth surface features for various users at NASA Johnson Space Center. The video from the radar is normally recorded on photographic film and subsequently processed photographically into high resolution radar images. Using a high speed sampling (digitizing) system, the two receiver channels of cross-and co-polarized video are recorded on wideband magnetic tape along with radar and platform parameters. These data are subsequently reformatted and processed into digital synthetic aperture radar images with the image data available on magnetic tape for subsequent analysis by investigators. The system design and results obtained are described.
A Novel Digital Signature Algorithm based on Biometric Hash
Shivangi Saxena
2017-01-01
Full Text Available Digital Signature protects the document`s integrity and binds the authenticity of the user who have signed. Present Digital Signature algorithm confirms authenticity but it does not ensure secrecy of the data. Techniques like encryption and decryption are needed to be used for this purpose. Biometric security has been a useful way for authentication and security as it provides a unique identity of the user. In this paper we have discussed the user authentication process and development of digital signatures. Authentication was based on hash functions which uses biometric features. Hash codes are being used to maintain the integrity of the document which is digitally signed. For security purpose, Encryption and Decryption techniques are used to develop a bio -cryptosystem. User information when gets concatenated with feature vector of biometric data, which actually justifies the sense of authentication. Various online or offline transaction where authenticity and integrity is the top most priority can make use of this development.
Implementation of Hash Algorithm in Network Processor%Hash算法在网络处理器中的实现
付仲满; 张辉; 李苗; 刘涛
2014-01-01
提出一种应用于网络处理器的Hash算法,通过建立新型查找表的结构和构造两级Hash函数,能够有效地解决Hash冲突的问题。描述Hash表的软件建立流程和硬件查找过程,在Hash查找的基础上,给出硬件表项的学习过程和老化方法,简化表项的更新操作。针对不同的应用,建立不同类型的Hash表,合理地利用内外部存储资源,兼顾了存储资源和处理速度的平衡。实验结果表明,该算法对各种查找表中不同的表项数目和关键词长度均具有较好的兼容性,成功查找的平均长度为2,减少了存储器的访存次数,其单个微引擎的查找速度高达25 Mb/s,能够满足网络处理器接口处理带宽20 Gb/s的要求。%A novel Hash algorithm is proposed in this paper for network processor application. It resolves Hash collision problem by constructing new look up table and new two-level Hash function. The software processing and hardware lookup flow of Hash table are descripted, and the learning process and ageing machine for entry of table are designed for simplifying the entry updating operation. For different engineering applications,the algorithm sets up different Hash table, which makes the efficience of memory utilization improved and the tradeoff between memory and processing speed optimized. Simulation results show the algorithm works well despite of the number of table entry and the size of keyword. The average length of look up’ s success is 2 and the memory access times is reduced dramaticlly. The look up speed of micro-engine is improved to 25 Mb/s,satisfing the requinrement of 20 Gb/s bandwidth performance of network processor.
数字 BPM 信号处理器的研制进展%Progress of Digital BPM Signal Processor
赖龙伟; 冷用斌; 阎映炳; 周伟民
2015-01-01
A digital BPM signal processor prototype has been developed in Shanghai Synchrotron Radiation Facility (SSRF) ,which is based on FPGA and ARM .In this paper ,the processor progress was introduced ,including the processor structure ,key innovation ,performance evaluation and future plan .It is the first BPM signal processor developed in China .Some essential technical breakthroughs were made during the devel‐opment ,and it can reach sub‐micrometer position resolution ,w hich is the same level of international product . The second version processor prototype was developed , and further system optimization is in progress .%介绍了上海光源束测组自行研制的基于FPGA和ARM的一体化数字BPM 信号处理器的进展，包括系统结构、关键技术创新、性能评估和下一步研究计划。该处理器是国内首台研制成功的BPM 信号处理器，在研制过程中取得多项关键技术的突破，逐圈位置分辨率达到亚微米，与国际同类产品处于相同水平。目前，该处理器已完成第2版样机的研制，正进行进一步系统优化。
Analysis algorithm for digital data used in nuclear spectroscopy
AUTHOR|(CDS)2085950; Sin, Mihaela
Data obtained from digital acquisition systems used in nuclear spectroscopy experiments must be converted by a dedicated algorithm in or- der to extract the physical quantities of interest. I will report here the de- velopment of an algorithm capable to read digital data, discriminate between random and true signals and convert the results into a format readable by a special data analysis program package used to interpret nuclear spectra and to create coincident matrices. The algorithm can be used in any nuclear spectroscopy experimental setup provided that digital acquisition modules are involved. In particular it was used to treat data obtained from the IS441 experiment at ISOLDE where the beta decay of 80Zn was investigated as part of ultra-fast timing studies of neutron rich Zn nuclei. The results obtained for the half-lives of 80Zn and 80Ga were in very good agreement with previous measurements. This fact proved unquestionably that the conversion algorithm works. Another remarkable result was the improve...
Qin, R.
2016-06-01
Large-scale Digital Surface Models (DSM) are very useful for many geoscience and urban applications. Recently developed dense image matching methods have popularized the use of image-based very high resolution DSM. Many commercial/public tools that implement matching methods are available for perspective images, but there are rare handy tools for satellite stereo images. In this paper, a software package, RPC (rational polynomial coefficient) stereo processor (RSP), is introduced for this purpose. RSP implements a full pipeline of DSM and orthophoto generation based on RPC modelled satellite imagery (level 1+), including level 2 rectification, geo-referencing, point cloud generation, pan-sharpen, DSM resampling and ortho-rectification. A modified hierarchical semi-global matching method is used as the current matching strategy. Due to its high memory efficiency and optimized implementation, RSP can be used in normal PC to produce large format DSM and orthophotos. This tool was developed for internal use, and may be acquired by researchers for academic and non-commercial purpose to promote the 3D remote sensing applications.
Real-time, auto-focusing digital holographic microscope using graphics processors.
Doğar, Mert; İlhan, Hazar A; Özcan, Meriç
2013-08-01
The most significant advantage of holographic imaging is that one does not need to do focusing alignment for the scene or objects while capturing their images. To focus on a particular object recorded in a digital hologram, a post-processing on the recorded image must be performed. This post-processing, so called the reconstruction, is essentially the calculation of wave propagation in free space. If the object's optical distance to the recording plane is not known a priori, focusing methods are used to estimate this distance. However, these operations can be quite time consuming as the hologram sizes increase. When there is a time constraint on these procedures and the image resolution is high, traditional central processing units (CPUs) can no longer satisfy the desired reconstruction speeds. Then, especially for real-time operations, additional hardware accelerators are required for reconstructing high resolution holograms. To this extend, today's commercial graphic cards offer a viable solution, as the holograms can be reconstructed tens of times faster with a graphics processing unit than with the state-of-the-art CPUs. Here we present an auto-focusing megapixel-resolution digital holographic microscope (DHM) that uses a graphics processing unit (GPU) as the calculation engine. The computational power of the GPU allows the DHM to work in real-time such that the reconstruction distance is estimated unsupervised, and the post-processing of the holograms are made completely transparent to the user. We compare DHM with GPU and CPU and present experimental results showing a maximum of 70 focused reconstructions per second (frps) with 1024 × 1024 pixel holograms.
Zhang, Chenxin; Öwall, Viktor
2016-01-01
This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G. •Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfigur...
Parallel Performance of MPI Sorting Algorithms on Dual-Core Processor Windows-Based Systems
Elnashar, Alaa Ismail
2011-01-01
Message Passing Interface (MPI) is widely used to implement parallel programs. Although Windowsbased architectures provide the facilities of parallel execution and multi-threading, little attention has been focused on using MPI on these platforms. In this paper we use the dual core Window-based platform to study the effect of parallel processes number and also the number of cores on the performance of three MPI parallel implementations for some sorting algorithms.
Optimizing ion channel models using a parallel genetic algorithm on graphical processors.
Ben-Shalom, Roy; Aviv, Amit; Razon, Benjamin; Korngreen, Alon
2012-01-01
We have recently shown that we can semi-automatically constrain models of voltage-gated ion channels by combining a stochastic search algorithm with ionic currents measured using multiple voltage-clamp protocols. Although numerically successful, this approach is highly demanding computationally, with optimization on a high performance Linux cluster typically lasting several days. To solve this computational bottleneck we converted our optimization algorithm for work on a graphical processing unit (GPU) using NVIDIA's CUDA. Parallelizing the process on a Fermi graphic computing engine from NVIDIA increased the speed ∼180 times over an application running on an 80 node Linux cluster, considerably reducing simulation times. This application allows users to optimize models for ion channel kinetics on a single, inexpensive, desktop "super computer," greatly reducing the time and cost of building models relevant to neuronal physiology. We also demonstrate that the point of algorithm parallelization is crucial to its performance. We substantially reduced computing time by solving the ODEs (Ordinary Differential Equations) so as to massively reduce memory transfers to and from the GPU. This approach may be applied to speed up other data intensive applications requiring iterative solutions of ODEs.
严伟; 曹家麟; 龚幼民
2005-01-01
The relativity of instructions of motor control digital signal processor (MCDSP) in the design is analyzed. A method for obtaining a minimum instruction set in place of the complete instruction set during generation of testing procedures is given in terms of the processor presentation matrix between micro-operators and instructions of MCDSP.
Digital zoom algorithm with context derived basis functions
Schau, H. C.
2011-06-01
One of the goals of superresultion has been to achieve interpolation in excess of some externally imposed physical constraint. Initially it was the optical diffraction limit while the Nyquist Limit of sampled data systems has also become a more recent issue. Regardless of the setting, the limitations are the same; there generally is not enough available degrees of freedom to perform an interpolation without severe loss of information. While some success has been achieved in superresolution, magnification is generally limited to less than 2. In this paper we present a method where context based basis functions are developed for digital zoom where the magnifications were assumed to be greater that 2. The number of degrees of freedom are still less than the number formally required, because the basis functions are developed for scenes similar to scenes presented for interpolation, they are more efficient than those developed without regard to context. The technique is presented together with several still images and video examples of digital zoom for a magnification of 5 and 10. Results are compared with conventional B-Cubic Spline interpolation. Parallelization of the technique with graphic processors is discussed toward its real time implementation.
Applications of Digital Signal Processors in Software Radio%数字信号处理器在软件无线电中的应用
单月晖
2001-01-01
首先介绍了软件无线电(Software Radio)的思想、结构、特性及其对数字信号处理能力的要求,然后着重讨论了数字信号处理器(Digital Signal Processor,简称DSP,包括A/D、DDC、DUC、DDS、高速并行DSP)在软件无线电中的应用.
Digital Watermarking Algorithm Based on Wavelet Transform and Neural Network
WANG Zhenfei; ZHAI Guangqun; WANG Nengchao
2006-01-01
An effective blind digital watermarking algorithm based on neural networks in the wavelet domain is presented. Firstly, the host image is decomposed through wavelet transform. The significant coefficients of wavelet are selected according to the human visual system (HVS) characteristics. Watermark bits are added to them. And then effectively cooperates neural networks to learn the characteristics of the embedded watermark related to them. Because of the learning and adaptive capabilities of neural networks, the trained neural networks almost exactly recover the watermark from the watermarked image. Experimental results and comparisons with other techniques prove the effectiveness of the new algorithm.
A novel digital watermark algorithm based on chaotic maps
Wu Xianyong [Department of Control Science and Engineering, Huazhong University of Science and Technology, Wuhan, Hubei 430074 (China) and School of Electronics and Information, Yangtze University, Jingzhou, Hubei 434023 (China)]. E-mail: wu_xianyong@163.com; Guan Zhihong [Department of Control Science and Engineering, Huazhong University of Science and Technology, Wuhan, Hubei 430074 (China)
2007-06-11
In this Letter, a new digital watermarking algorithm is proposed. Different from most of existing chaotic watermarking schemes, two chaotic maps are employed in our scheme to improve the security, one map is used to encrypt the embedding position of the host image, and another map is used to determine the pixel bit of host image for watermark embedding. Simulation results demonstrate that the watermark generated with the proposed algorithm is invisible and the watermarking scheme is robust against common image processing operations, such as JPEG compression, filtering, Gaussian noise pollution, cropping and rotation and so on.
Convergence of iterative image reconstruction algorithms for Digital Breast Tomosynthesis
Sidky, Emil; Jørgensen, Jakob Heide; Pan, Xiaochuan
2012-01-01
solutions can aid in iterative image reconstruction algorithm design. This issue is particularly acute for iterative image reconstruction in Digital Breast Tomosynthesis (DBT), where the corresponding data model IS particularly poorly conditioned. The impact of this poor conditioning is that iterative......Most iterative image reconstruction algorithms are based on some form of optimization, such as minimization of a data-fidelity term plus an image regularizing penalty term. While achieving the solution of these optimization problems may not directly be clinically relevant, accurate optimization....... Math. Imag. Vol. 40, pgs 120-145) and apply it to iterative image reconstruction in DBT....
Algorithmically specialized parallel computers
Snyder, Lawrence; Gannon, Dennis B
1985-01-01
Algorithmically Specialized Parallel Computers focuses on the concept and characteristics of an algorithmically specialized computer.This book discusses the algorithmically specialized computers, algorithmic specialization using VLSI, and innovative architectures. The architectures and algorithms for digital signal, speech, and image processing and specialized architectures for numerical computations are also elaborated. Other topics include the model for analyzing generalized inter-processor, pipelined architecture for search tree maintenance, and specialized computer organization for raster
A robust chaotic algorithm for digital image steganography
Ghebleh, M.; Kanso, A.
2014-06-01
This paper proposes a new robust chaotic algorithm for digital image steganography based on a 3-dimensional chaotic cat map and lifted discrete wavelet transforms. The irregular outputs of the cat map are used to embed a secret message in a digital cover image. Discrete wavelet transforms are used to provide robustness. Sweldens' lifting scheme is applied to ensure integer-to-integer transforms, thus improving the robustness of the algorithm. The suggested scheme is fast, efficient and flexible. Empirical results are presented to showcase the satisfactory performance of our proposed steganographic scheme in terms of its effectiveness (imperceptibility and security) and feasibility. Comparison with some existing transform domain steganographic schemes is also presented.
HIPSR: A Digital Signal Processor for the Parkes 21-cm Multibeam Receiver
Price, D. C.; Staveley-Smith, L.; Bailes, M.; Carretti, E.; Jameson, A.; Jones, M. E.; van Straten, W.; Schediwy, S. W.
2016-11-01
HIPSR (HI-Pulsar) is a digital signal processing system for the Parkes 21-cm Multibeam Receiver that provides larger instantaneous bandwidth, increased dynamic range, and more signal processing power than the previous systems in use at Parkes. The additional computational capacity enables finer spectral resolution in wideband HI observations and real-time detection of Fast Radio Bursts during pulsar surveys. HIPSR uses a heterogeneous architecture, consisting of FPGA-based signal processing boards connected via high-speed Ethernet to high performance compute nodes. Low-level signal processing is conducted on the FPGA-based boards, and more complex signal processing routines are conducted on the GPU-based compute nodes. The development of HIPSR was driven by two main science goals: to provide large bandwidth, high-resolution spectra suitable for 21-cm stacking and intensity mapping experiments; and to upgrade the Berkeley-Parkes-Swinburne Recorder (BPSR), the signal processing system used for the High Time Resolution Universe (HTRU) Survey and the Survey for Pulsars and Extragalactic Radio Bursts (SUPERB).
软件无线电数字信号处理器体系结构研究%Software Defined Radio Digital Signal Processor Architecture Research
刘衡竹; 莫方政; 张波涛; 赵恒; 刘冬培; 陈艇; 周理
2009-01-01
Software defined radio (SDR) has won much interest for being considered to be in line with the trend of wireless communication developrnent. Now the digital signal processor (DSP) is the bottleneck of software defined radio. The advantages and disadvantages of diverse architecture of software defined radio digital signal processor are summarized, and then the trends of software defined radio digital signal processor are discussed.%软件无线电因被认为是无线通信技术未来的发展趋势而受到广泛关注.目前数字信号处理器是软件无线电发展的瓶颈.通过分析、比较目前几种较为典型的软件无线电数字信号处理器结构,归纳总结各种结构各自设计出发点和优缺点,并对软件无线电数字信号处理器的发展趋势做了展望.
Digital VLSI algorithms and architectures for support vector machines.
Anguita, D; Boni, A; Ridella, S
2000-06-01
In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.
Implementation of real-time SAR systems with a high-performance digital signal processor
Kloos, Helge; Wittenburg, Jens P.; Hinrichs, Willm; Lieske, Hanno; Pirsch, Peter
1999-12-01
Real-time Synthetic Aperture Radar (SAR) image synthesis is one of the major problems to solve in the future. To achieve a fully synthesized SAR image, the raw signal must be filtered with a 2-dimensional function representing the system transfer function. These filtering operations are usually processed by multiplication in frequency domain. Therefore, the Fast Fourier Transform (FFT) used for transformation to/from frequency domain is the predominant algorithm in terms of processing power for SAR image synthesis. The presented HiPAR- DSP is a programmable architecture, which is optimized for FFT-dominated applications like SAR image processing. To provide the high requested processing power for these task, the HiPAR-DSP has an array of 4 (HiPAR-DSP4) respectively 16 (HiPAR-DSP16) parallel processing units (datapaths) which is controlled by a single RISC Controller. For data exchange between the processing units there is a shared memory which allows the concurrent access from all processing units in a single clock cycle. So the HiPAR-DSP16 performs a complex FFT with 1024 Samples in 32microsecond(s) . For the implemented SAR- Processing task, the Range Compression with 4096 complex samples per line we achieve a real-time performance of nearly 1500 rangelines/s.
Niederhauser, Thomas; Wyss-Balmer, Thomas; Haeberlin, Andreas; Marisa, Thanks; Wildhaber, Reto A; Goette, Josef; Jacomet, Marcel; Vogel, Rolf
2015-06-01
Long-term electrocardiogram (ECG) often suffers from relevant noise. Baseline wander in particular is pronounced in ECG recordings using dry or esophageal electrodes, which are dedicated for prolonged registration. While analog high-pass filters introduce phase distortions, reliable offline filtering of the baseline wander implies a computational burden that has to be put in relation to the increase in signal-to-baseline ratio (SBR). Here, we present a graphics processor unit (GPU)-based parallelization method to speed up offline baseline wander filter algorithms, namely the wavelet, finite, and infinite impulse response, moving mean, and moving median filter. Individual filter parameters were optimized with respect to the SBR increase based on ECGs from the Physionet database superimposed to autoregressive modeled, real baseline wander. A Monte-Carlo simulation showed that for low input SBR the moving median filter outperforms any other method but negatively affects ECG wave detection. In contrast, the infinite impulse response filter is preferred in case of high input SBR. However, the parallelized wavelet filter is processed 500 and four times faster than these two algorithms on the GPU, respectively, and offers superior baseline wander suppression in low SBR situations. Using a signal segment of 64 mega samples that is filtered as entire unit, wavelet filtering of a seven-day high-resolution ECG is computed within less than 3 s. Taking the high filtering speed into account, the GPU wavelet filter is the most efficient method to remove baseline wander present in long-term ECGs, with which computational burden can be strongly reduced.
Practical contour segmentation algorithm for small animal digital radiography image
Zheng, Fang; Hui, Gong
2008-12-01
In this paper a practical, automated contour segmentation technique for digital radiography image is described. Digital radiography is an imaging mode based on the penetrability of x-ray. Unlike reflection imaging mode such as visible light camera, the pixel brightness represents the summation of the attenuations on the photon thoroughfare. It is not chromophotograph but gray scale picture. Contour extraction is of great importance in medical applications, especially in non-destructive inspection. Manual segmentation techniques include pixel selection, geometrical boundary selection and tracing. But it relies heavily on the experience of the operators, and is time-consuming. Some researchers try to find contours from the intensity jumping characters around them. However these characters also exist in the juncture of bone and soft tissue. The practical way is back to the primordial threshold algorithm. This research emphasizes on how to find the optimal threshold. A high resolution digital radiography system is used to provide the oriental gray scale image. A mouse is applied as the sample of this paper to show the feasibility of the algorithm.
A content-based digital audio watermarking algorithm
Zhang, Liping; Zhao, Yi; Xu, Wen Li
2015-12-01
Digital audio watermarking embeds inaudible information into digital audio data for the purposes of copyright protection, ownership verification, covert communication, and/or auxiliary data carrying. In this paper, we present a novel watermarking scheme to embed a meaningful gray image into digital audio by quantizing the wavelet coefficients (using integer lifting wavelet transform) of audio samples. Our audio-dependent watermarking procedure directly exploits temporal and frequency perceptual masking of the human auditory system (HAS) to guarantee that the embedded watermark image is inaudible and robust. The watermark is constructed by utilizing still image compression technique, breaking each audio clip into smaller segments, selecting the perceptually significant audio segments to wavelet transform, and quantizing the perceptually significant wavelet coefficients. The proposed watermarking algorithm can extract the watermark image without the help from the original digital audio signals. We also demonstrate the robustness of that watermarking procedure to audio degradations and distortions, e.g., those that result from noise adding, MPEG compression, low pass filtering, resampling, and requantization.
Recognition of digital characteristics based new improved genetic algorithm
Wang, Meng; Xu, Guoqiang; Lin, Zihao
2017-08-01
In the field of digital signal processing, Estimating the characteristics of signal modulation parameters is an significant research direction. The paper determines the set of eigenvalue which can show the difference of the digital signal modulation based on the deep research of the new improved genetic algorithm. Firstly take them as the best gene pool; secondly, The best gene pool will be changed in the genetic evolvement by selecting, overlapping and eliminating each other; Finally, Adapting the strategy of futher enhance competition and punishment to more optimizer the gene pool and ensure each generation are of high quality gene. The simulation results show that this method not only has the global convergence, stability and faster convergence speed.
CANDID: Comparison algorithm for navigating digital image databases
Kelly, P.M.; Cannon, T.M.
1994-02-21
In this paper, we propose a method for calculating the similarity between two digital images. A global signature describing the texture, shape, or color content is first computed for every image stored in a database, and a normalized distance between probability density functions of feature vectors is used to match signatures. This method can be used to retrieve images from a database that are similar to an example target image. This algorithm is applied to the problem of search and retrieval for database containing pulmonary CT imagery, and experimental results are provided.
Experience with CANDID: Comparison algorithm for navigating digital image databases
Kelly, P.; Cannon, M.
1994-10-01
This paper presents results from the authors experience with CANDID (Comparison Algorithm for Navigating Digital Image Databases), which was designed to facilitate image retrieval by content using a query-by-example methodology. A global signature describing the texture, shape, or color content is first computed for every image stored in a database, and a normalized similarity measure between probability density functions of feature vectors is used to match signatures. This method can be used to retrieve images from a database that are similar to a user-provided example image. Results for three test applications are included.
Preliminary Study of Image Reconstruction Algorithm on a Digital Signal Processor
2014-03-01
solutions are examined for performance. Accelerators promise the potential to augment a system with only Intel or AMD central processing units...and AMD central processing units (CPUs) has hampered x86 dominance in performance, especially for inherently parallel applications. In this new era... disables all optimizations. The compiler generates unoptimized, linear assembly language code. 2. Optimization Level 1: The compiler performs all target
Design and Realization of Array Signal Processor VLSI Architecture for Phased Array System
D. Govind Rao
2016-08-01
Full Text Available A method for implementing an array signal processor for phased array radars. The array signal processor can receive planar array antenna inputs and can process it. It is based on the application of Adaptive Digital beam formers using FPGAs. Adaptive filter algorithm used here is Inverse Q-R Decomposition based Recursive Least Squares (IQRD-RLS [1] algorithm. Array signal processor based on FPGAs is suitable in the areas of Phased Array Radar receiver, where speed, accuracy and numerical stability are of utmost important. Using IQRD-RLS algorithm, optimal weights are calculated in much less time compared to conventional QRD-RLS algorithm. A customized multiple FPGA board comprising three Kintex-7 FPGAs is employed to implement array signal processor. The proposed architecture can form multiple beams from planar array antenna elements
Model of computation for Fourier optical processors
Naughton, Thomas J.
2000-05-01
We present a novel and simple theoretical model of computation that captures what we believe are the most important characteristics of an optical Fourier transform processor. We use this abstract model to reason about the computational properties of the physical systems it describes. We define a grammar for our model's instruction language, and use it to write algorithms for well-known filtering and correlation techniques. We also suggest suitable computational complexity measures that could be used to analyze any coherent optical information processing technique, described with the language, for efficiency. Our choice of instruction language allows us to argue that algorithms describable with this model should have optical implementations that do not require a digital electronic computer to act as a master unit. Through simulation of a well known model of computation from computer theory we investigate the general-purpose capabilities of analog optical processors.
Parallel algorithms for interactive manipulation of digital terrain models
Davis, E. W.; Mcallister, D. F.; Nagaraj, V.
1988-01-01
Interactive three-dimensional graphics applications, such as terrain data representation and manipulation, require extensive arithmetic processing. Massively parallel machines are attractive for this application since they offer high computational rates, and grid connected architectures provide a natural mapping for grid based terrain models. Presented here are algorithms for data movement on the massive parallel processor (MPP) in support of pan and zoom functions over large data grids. It is an extension of earlier work that demonstrated real-time performance of graphics functions on grids that were equal in size to the physical dimensions of the MPP. When the dimensions of a data grid exceed the processing array size, data is packed in the array memory. Windows of the total data grid are interactively selected for processing. Movement of packed data is needed to distribute items across the array for efficient parallel processing. Execution time for data movement was found to exceed that for arithmetic aspects of graphics functions. Performance figures are given for routines written in MPP Pascal.
Optimal Polygonal Approximation of Digital Planar Curves Using Genetic Algorithm and Tabu Search
无
2000-01-01
Three heuristic algorithms for optimal polygonal approximation of digital planar curves is presented.With Genetic Algorithm (GA), improved Genetic Algorithm (IGA) based on Pareto optimal solution and Tabu Search (TS), a near optimal polygonal approximation was obtained.Compared to the famous Teh-chin algorithm, our algorithms have obtained the approximated polygons with less number of vertices and less approximation error.Compared to the dynamic programming algorithm, the processing time of our algorithms are much less expensive.
窦维蓓; 阳学仕; 董在望
1999-01-01
MPEG音频层III压缩算法,是由ISO11172-3标准规定的一种高效、高保真的压缩编码算法.由于层III压缩算法的复杂度高,运算量大,为此提出了在实时应用中,基于数字信号处理器(Digital Signal Processor,以下简称DSP)实现层III压缩算法的关键运算的加速措施.
Evaluation of clinical image processing algorithms used in digital mammography.
Zanca, Federica; Jacobs, Jurgen; Van Ongeval, Chantal; Claus, Filip; Celis, Valerie; Geniets, Catherine; Provost, Veerle; Pauwels, Herman; Marchal, Guy; Bosmans, Hilde
2009-03-01
Screening is the only proven approach to reduce the mortality of breast cancer, but significant numbers of breast cancers remain undetected even when all quality assurance guidelines are implemented. With the increasing adoption of digital mammography systems, image processing may be a key factor in the imaging chain. Although to our knowledge statistically significant effects of manufacturer-recommended image processings have not been previously demonstrated, the subjective experience of our radiologists, that the apparent image quality can vary considerably between different algorithms, motivated this study. This article addresses the impact of five such algorithms on the detection of clusters of microcalcifications. A database of unprocessed (raw) images of 200 normal digital mammograms, acquired with the Siemens Novation DR, was collected retrospectively. Realistic simulated microcalcification clusters were inserted in half of the unprocessed images. All unprocessed images were subsequently processed with five manufacturer-recommended image processing algorithms (Agfa Musica 1, IMS Raffaello Mammo 1.2, Sectra Mamea AB Sigmoid, Siemens OPVIEW v2, and Siemens OPVIEW v1). Four breast imaging radiologists were asked to locate and score the clusters in each image on a five point rating scale. The free-response data were analyzed by the jackknife free-response receiver operating characteristic (JAFROC) method and, for comparison, also with the receiver operating characteristic (ROC) method. JAFROC analysis revealed highly significant differences between the image processings (F = 8.51, p < 0.0001), suggesting that image processing strongly impacts the detectability of clusters. Siemens OPVIEW2 and Siemens OPVIEW1 yielded the highest and lowest performances, respectively. ROC analysis of the data also revealed significant differences between the processing but at lower significance (F = 3.47, p = 0.0305) than JAFROC. Both statistical analysis methods revealed that the
Kimura, N; The ATLAS collaboration; Beretta, M; Gatta, M; Gkaitatzis, S; Iizawa, T; Kordas, K; Korikawa, T; Nikolaidis, N; Petridou, P; Sotiropoulou, C-L; Yorita, K; Volpi, G
2014-01-01
The highly parallel 2D-clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors read out drivers (RODs) at 760Gbps, the full rate of level 1 triggers. Clustering serves two purposes. The first is to reduce the high rate of the received data before further processing. The second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The implementation is fully generic, therefore the detection window size can be optimized for the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility ma...
Evaluation of hybrids algorithms for mass detection in digitalized mammograms
Cordero, Jose; Garzon Reyes, Johnson, E-mail: josecorderog@hotmail.com [Grupo de Optica y Espectroscopia GOE, Centro de Ciencia Basica, Universidad Pontifica Bolivariana de Medellin (Colombia)
2011-01-01
The breast cancer remains being a significant public health problem, the early detection of the lesions can increase the success possibilities of the medical treatments. The mammography is an image modality effective to early diagnosis of abnormalities, where the medical image is obtained of the mammary gland with X-rays of low radiation, this allows detect a tumor or circumscribed mass between two to three years before that it was clinically palpable, and is the only method that until now achieved reducing the mortality by breast cancer. In this paper three hybrids algorithms for circumscribed mass detection on digitalized mammograms are evaluated. In the first stage correspond to a review of the enhancement and segmentation techniques used in the processing of the mammographic images. After a shape filtering was applied to the resulting regions. By mean of a Bayesian filter the survivors regions were processed, where the characteristics vector for the classifier was constructed with few measurements. Later, the implemented algorithms were evaluated by ROC curves, where 40 images were taken for the test, 20 normal images and 20 images with circumscribed lesions. Finally, the advantages and disadvantages in the correct detection of a lesion of every algorithm are discussed.
Su, Jianping; Zhang, Jun; Yu, Lingfeng; G Colt, Henri; Brenner, Matthew; Chen, Zhongping
2008-01-01
A fast-scan-rate swept laser for optical coherence tomography (OCT) is suitable to record and analyze a 3-D image volume. However, the whole OCT system speed is limited by data streaming, processing, and storage. In this case, postprocessing is a common technique. Endoscopic clinical applications prefer onsite diagnosis, which requires a real-time technique. Parallel digital signal processors were applied to stream and process data directly from a data digitizer. A real-time system with 20-kHz axial line speed, which was limited only by our swept laser scan rate, was implemented. To couple with the system speed, an endoscope based on an improved 3-D microelectromechanical motor (diameter 1.5 mm, length 9.4 mm) was developed. In vivo 3-D imaging of the human airway was demonstrated.
The Application Research of MD5 Encryption Algorithm in DCT Digital Watermarking
Xijin, Wang; Linxiu, Fan
This article did the preliminary study of the application of algorithm for MD5 in the digital watermark. It proposed that copyright information will be encrypted using an algorithm MD5, and made rules for the second value image watermarks, through DCT algorithm that embeds an image by the carrier. The extraction algorithms can pick up the watermark and restore MD5 code.
Automatic Synthesis of CMOS Algorithmic Analog To-Digital Converter.
Jusuf, Gani
The steady decrease in technological feature size is allowing increasing levels of integration in analog/digital interface functions. These functions consist of analog as well as digital circuits. While the turn around time for an all digital IC chip is very short due to the maturity of digital IC computer-aided design (CAD) tools over the last ten years, most analog circuits have to be designed manually due to the lack of analog IC CAD tools. As a result, analog circuit design becomes the bottleneck in the design of mixed signal processing chips. One common analog function in a mixed signal processing chip is an analog-to-digital conversion (ADC) function. This function recurs frequently but with varying performance requirements. The objective of this research is to study the design methodology of a compilation program capable of synthesizing ADC's with a broad range of sampling rates and resolution, and silicon area and performance comparable with the manual approach. The automatic compilation of the ADC function is a difficult problem mainly because ADC techniques span such a wide spectrum of performance, with radically different implementations being optimum for different ranges of conversion range, resolution, and power dissipation. We will show that a proper choice of the ADC architectures and the incorporation of many analog circuit design techniques will simplify the synthesis procedure tremendously. Moreover, in order to speed up the device sizing, hierarchical optimization procedure and behavioral simulation are implemented into the ADC module generation steps. As a result of this study, a new improved algorithmic ADC without the need of high precision comparators has been developed. This type of ADC lends itself to automatic generation due to its modularity, simplicity, small area consumption, moderate speed, low power dissipation, and single parameter trim capability that can be added at high resolution. Furthermore, a performance-driven CMOS ADC module
DIGITAL SPECKLE CORRELATION METHOD IMPROVED BY GENETIC ALGORITHM
MaShaopeng; JillGuanchang
2003-01-01
The digital speckle correlation method is an important optical metrology for surface displacement and strain measurement. With this technique, the whole field deformation information can be obtained by tracking the geometric points on the speckle images based on a correlation-matching search technique. However, general search techniques suffer from great computational complexity in the processing of speckle images with large deformation and the large random errors in the processing of images of bad quality. In this paper, an advanced approach based on genetic algorithms (GA) for correlation-matching search is developed. Benefiting from the abilities of global optimum and parallelism searching of GA, this new approach can complete the correlation-matching search with less computational consumption and at high accuracy. Two experimental results from the simulated speckle images have proved the efficiency of the new approach.
A Systolic Array RLS Processor
Asai, T.; Matsumoto, T.
2000-01-01
This paper presents the outline of the systolic array recursive least-squares (RLS) processor prototyped primarily with the aim of broadband mobile communication applications. To execute the RLS algorithm effectively, this processor uses an orthogonal triangularization technique known in matrix algebra as QR decomposition for parallel pipelined processing. The processor board comprises 19 application-specific integrated circuit chips, each with approximately one million gates. Thirty-two bit ...
Chaotic CDMA watermarking algorithm for digital image in FRFT domain
Liu, Weizhong; Yang, Wentao; Feng, Zhuoming; Zou, Xuecheng
2007-11-01
A digital image-watermarking algorithm based on fractional Fourier transform (FRFT) domain is presented by utilizing chaotic CDMA technique in this paper. As a popular and typical transmission technique, CDMA has many advantages such as privacy, anti-jamming and low power spectral density, which can provide robustness against image distortions and malicious attempts to remove or tamper with the watermark. A super-hybrid chaotic map, with good auto-correlation and cross-correlation characteristics, is adopted to produce many quasi-orthogonal codes (QOC) that can replace the periodic PN-code used in traditional CDAM system. The watermarking data is divided into a lot of segments that correspond to different chaotic QOC respectively and are modulated into the CDMA watermarking data embedded into low-frequency amplitude coefficients of FRFT domain of the cover image. During watermark detection, each chaotic QOC extracts its corresponding watermarking segment by calculating correlation coefficients between chaotic QOC and watermarked data of the detected image. The CDMA technique not only can enhance the robustness of watermark but also can compress the data of the modulated watermark. Experimental results show that the watermarking algorithm has good performances in three aspects: better imperceptibility, anti-attack robustness and security.
The use of variable-step delta modulation in digital filtering and correlation analysis
Pogribnoi, V. A.
1985-11-01
General expressions are obtained for convolutions and correlation functions using variable-quantization-step DM in conjunction with PCM, making it possible to realize low-cost processor circuits. Algorithms for the operation of processors for digital filtering and correlation analysis on the basis of this type of modulation are proposed. In addition, they are compared with algorithms for the operation of processors with linear PCM, DM, and delta-sigma modulation.
Fan, Desheng; Meng, Xiangfeng; Wang, Yurong; Yang, Xiulun; Peng, Xiang; He, Wenqi; Dong, Guoyan; Chen, Hongyi
2013-08-10
An optical identity authentication scheme based on the elliptic curve digital signature algorithm (ECDSA) and phase retrieval algorithm (PRA) is proposed. In this scheme, a user's certification image and the quick response code of the user identity's keyed-hash message authentication code (HMAC) with added noise, serving as the amplitude and phase restriction, respectively, are digitally encoded into two phase keys using a PRA in the Fresnel domain. During the authentication process, when the two phase keys are presented to the system and illuminated by a plane wave of correct wavelength, an output image is generated in the output plane. By identifying whether there is a match between the amplitude of the output image and all the certification images pre-stored in the database, the system can thus accomplish a first-level verification. After the confirmation of first-level verification, the ECDSA signature is decoded from the phase part of the output image and verified to allege whether the user's identity is legal or not. Moreover, the introduction of HMAC makes it almost impossible to forge the signature and hence the phase keys thanks to the HMAC's irreversible property. Theoretical analysis and numerical simulations both validate the feasibility of our proposed scheme.
Aalto, S.; Ayesta, U.; Borst, S.C.; Misra, V.; Núñez Queija, R.
2007-01-01
While the (Egalitarian) Processor-Sharing (PS) discipline offers crucial insights in the performance of fair resource allocation mechanisms, it is inherently limited in analyzing and designing differentiated scheduling algorithms such as Weighted Fair Queueing and Weighted Round-Robin. The Discrimin
Sheng, Hui; Gao, Yesheng; Zhu, Bingqi; Wang, Kaizhi; Liu, Xingzhao
2015-01-01
With the high programmability of a spatial light modulator (SLM), a newly developed synthetic aperture radar (SAR) optronic processor is capable of focusing SAR data with different parameters. The embedded SLM, encoding SAR data into light signal in the processor, has a limited loading resolution of 1920×1080. When the dimension of processed SAR data increases to tens of thousands in either range or azimuth direction, SAR data should be input and focused block by block. And then, part of the imaging results is mosaicked to offer a full-scene SAR image. In squint mode, however, Doppler centroid will shift signal spectrum in the azimuth direction and make phase filters, loaded by another SLM, unable to cover the entire signal spectrum. It brings about a poor imaging result. Meanwhile, the imaging result, shifted away from the center of light output, will cause difficulties in subsequent image mosaic. We present an SAR image formation algorithm designed to solve these problems when processing SAR data of a large volume in low-squint case. It could not only obtain high-quality imaging results, but also optimize the subsequent process of image mosaic with optimal system cost and efficiency. Experimental results validate the performance of this proposed algorithm in optical full-scene SAR imaging.
Peng, Xinhua; Zhu, Xiwen; Fang, Ximing; Feng, Mang; Liu, Maili; Gao, Kelin
2004-02-22
A quantum circuit is introduced to describe the preparation of a labeled pseudo-pure state by multiplet-component excitation scheme which has been experimentally implemented on a 4-qubit nuclear magnetic resonance quantum processor. Meanwhile, we theoretically analyze and numerically investigate the low-power selective single-pulse implementation of a controlled-rotation gate, which manifests its validity in our experiment. Based on the labeled pseudo-pure state prepared, a 3-qubit Bernstein-Vazirani algorithm has been experimentally demonstrated by spectral implementation. The "answers" of the computations are identified from the split peak positions in the spectra of the observer spin, which are equivalent to projective measurements required by the algorithms.
Kimura, N; The ATLAS collaboration; Beretta, M; Gatta, M; Gkaitatzis, S; Iizawa, T; Kordas, K; Korikawa, T; Nikolaidis, S; Petridou, C; Sotiropoulou, C-L; Yorita, K; Volpi, G
2014-01-01
The highly parallel 2D-clustering FPGA implementation used for the input system of Fast TracKer (FTK) processor for the ATLAS experiment at Large Hadron Collider (LHC) at CERN is presented. The LHC after the 2013-2014 shutdown periods is expected to increase the luminosity, which will make more difficult to have efficient online selection of rare events due to the increasing of the overlapping collisions. FTK is highly-parallelized hardware system that allows improving online selection by real time track finding using silicon inner detector information. FTK system require Fast and robust clustering of hits position from silicon detector on FPGA. We show the development of original input boards and implemented clustering algorithm. For the complicated 2D-clustering, moving window technique is used to minimize the limited FPGA resources. Developed boards and implementation of the clustering algorithm has sufficient processing power to meet the specification for silicon inner detector of ATLAS for the maximum LH...
New approach to the design of digital algorithms for electric power measurements
Kezunovic, M. (Texas A and M Univ., TX (US)); Perunicic, B. (Univ. of Sarajevo (YU))
1991-04-01
This paper introduces a new approach to the design of digital algorithms for electric power measurements. Digital algorithms for electric power measurements are represented as 2D digital FIR filters applied on voltage and current samples. Based on this approach, a new technique for algorithm design is developed. As the main advantage, the technique provides a convenient way to design new algorithms for measuring the electric power components according to various definitions in both sinusoidal and non-sinusoidal conditions. Several new algorithms are derived by using the proposed design technique. The existing algorithms for power measurements are also derived by using the new approach. The algorithm performance is tested using actual signal recordings.
A programmable sound processor for advanced hearing aid research.
McDermott, H
1998-03-01
A portable sound processor has been developed to facilitate research on advanced hearing aids. Because it is based on a digital signal processing integrated circuit (Motorola DSP56001), it can readily be programmed to execute novel algorithms. Furthermore, the parameters of these algorithms can be adjusted quickly and easily to suit the specific hearing characteristics of users. In the processor, microphone signals are digitized to a precision of 12 bits at a sampling rate of approximately 12 kHz for input to the DSP device. Subsequently, processed samples are delivered to the earphone by a novel, fully-digital class-D driver. This driver provides the advantages of a conventional class-D amplifier (high maximum output, low power consumption, low distortion) without some of the disadvantages (such as the need for precise analog circuitry). In addition, a cochlear implant driver is provided so that the processor is suitable for hearing-impaired people who use an implant and an acoustic hearing aid together. To reduce the computational demands on the DSP device, and therefore the power consumption, a running spectral analysis of incoming signals is provided by a custom-designed switched-capacitor integrated circuit incorporating 20 bandpass filters. The complete processor is pocket-sized and powered by batteries. An example is described of its use in providing frequency-shaped amplification for aid users with severe hearing impairment. Speech perception tests confirmed that the processor performed significantly better than the subjects' own hearing aids, probably because the digital filter provided a frequency response generally closer to the optimum for each user than the simpler analog aids.
Siy, P.F.; Carter, J.T.; D' Addario, L.R.; Loeber, D.A.
1991-08-01
The MITRE Corporation has performed in-flux radiation testing of the Texas Instruments TMS320C30 32-bit floating point digital signal processor in both total dose and dose rate radiation environments. This test effort has provided data relating to the applicability of the TMS320C30 in systems with total dose and/or dose rate survivability requirements. In order to accomplish these tests, the MITRE Corporation developed custom hardware and software for in-flux radiation testing. This paper summarizes the effort by providing an overview of the TMS320C30, MITRE's test methodology, test facilities, statistical analysis, and full coverage of the test results. (Author)
Development of Automatic Cluster Algorithm for Microcalcification in Digital Mammography
Choi, Seok Yoon [Dept. of Medical Engineering, Korea University, Seoul (Korea, Republic of); Kim, Chang Soo [Dept. of Radiological Science, College of Health Sciences, Catholic University of Pusan, Pusan (Korea, Republic of)
2009-03-15
Digital Mammography is an efficient imaging technique for the detection and diagnosis of breast pathological disorders. Six mammographic criteria such as number of cluster, number, size, extent and morphologic shape of microcalcification, and presence of mass, were reviewed and correlation with pathologic diagnosis were evaluated. It is very important to find breast cancer early when treatment can reduce deaths from breast cancer and breast incision. In screening breast cancer, mammography is typically used to view the internal organization. Clusterig microcalcifications on mammography represent an important feature of breast mass, especially that of intraductal carcinoma. Because microcalcification has high correlation with breast cancer, a cluster of a microcalcification can be very helpful for the clinical doctor to predict breast cancer. For this study, three steps of quantitative evaluation are proposed : DoG filter, adaptive thresholding, Expectation maximization. Through the proposed algorithm, each cluster in the distribution of microcalcification was able to measure the number calcification and length of cluster also can be used to automatically diagnose breast cancer as indicators of the primary diagnosis.
A robust digital watermarking algorithm based on framelet and SVD
Xiao, Moyan; He, Zhibiao; Quan, Tingwei
2015-12-01
Compared with wavelet, framelet has good time frequency analysis ability and redundant characteristic. SVD (Singular Value Decomposition) can obtain stable feature of images which is not easily destroyed. To further improve the watermarking technique, a robust digital watermarking algorithm based on framelet and SVD is proposed. Firstly, Arnold transform is implemented to the grayscale watermark image. Secondly perform framelet transform to each host block which is divided according to the size of the watermark. Then embed the scrambled watermark into the biggest singular values produced in SVD transform to each coarse band gained from framelet transform to host image block. At last inverse framelet transform after inverse SVD transform to obtain embedded coarse band. Experimental results show that the proposed method gains good performance in robustness and security compared with traditional image processing including noise attack, cropping, filtering and JPEG compression etc. Moreover, the watermark imperceptibility of our method is better than that of wavelet and has stronger robustness than pure framelet without SVD.
Digital neuromorphic processing for a simplified algorithm of ultrasonic reception
Qiang, Lin; Clarke, Chris
2001-05-01
Previously, most mammalian auditory systems research has concentrated on human sensory perception whose frequencies are lower than 20 kHz. The implementations almost always used analog VLSI design. Due to the complexity of the model, it is difficult to implement these algorithms using current digital technology. This paper introduces a simplified model of biosonic reception system in bats and its implementation in the ``Chiroptera Inspired Robotic CEphaloid'' (CIRCE) project. This model consists of bandpass filters, a half-wave rectifier, low-pass filters, automatic gain control, and spike generation with thresholds. Due to the real-time requirements of the system, the system employs Butterworth filters and advanced field programmable gate array (FPGA) architectures to provide a viable solution. The ultrasonic signal processing is implemented on a Xilinx FPGA Virtex II device in real time. In the system, 12-bit input echo signals from receivers are sampled at 1 M samples per second for a signal frequency range from 20 to 200 kHz. The system performs a 704-channel per ear auditory pipeline operating in real time. The output of the system is a coded time series of threshold crossing points. Comparing hardware implementation with fixed-point software, the system shows significant performance gains with no loss of accuracy.
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
Lang, Tomas; Nannarelli, Alberto
2007-01-01
In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm. The previous decimal division designs do not include recent developments in the theory and practice of this type of algorithm, which were developed for radix-2^k dividers. In addition...... to the adaptation of these features, the radix-10 quotient digit is decomposed into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required in the recurrence. Moreover, the most significant slice of the recurrence, which includes the selection function, is implemented...
Multidimensional Systolic Arrays of LMS AlgorithmAdaptive (FIR Digital Filters
Bakir A. R. Al-Hashemy
2009-01-01
Full Text Available A multidimensional systolic arrays realization of LMS algorithm by a method of mapping regular algorithm onto processor array, are designed. They are based on appropriately selected 1-D systolic array filter that depends on the inner product sum systolic implementation. Various arrays may be derived that exhibit a regular arrangement of the cells (processors and local interconnection pattern, which are important for VLSI implementation. It reduces latency time and increases the throughput rate in comparison to classical 1-D systolic arrays. The 3-D multilayered array consists of 2-D layers, which are connected with each other only by edges. Such arrays for LMS-based adaptive (FIR filter may be opposed the fundamental requirements of fast convergence rate in most adaptive filter applications.
An online algorithm for generating fractal hash chains applied to digital chains of custody
Bradford, Phillip G
2007-01-01
This paper gives an online algorithm for generating Jakobsson's fractal hash chains. Our new algorithm compliments Jakobsson's fractal hash chain algorithm for preimage traversal since his algorithm assumes the entire hash chain is precomputed and a particular list of Ceiling(log n) hash elements or pebbles are saved. Our online algorithm for hash chain traversal incrementally generates a hash chain of n hash elements without knowledge of n before it starts. For any n, our algorithm stores only the Ceiling(log n) pebbles which are precisely the inputs for Jakobsson's amortized hash chain preimage traversal algorithm. This compact representation is useful to generate, traverse, and store a number of large digital hash chains on a small and constrained device. We also give an application using both Jakobsson's and our new algorithm applied to digital chains of custody for validating dynamically changing forensics data.
Computer Arithmetic Algorithms for Mega-Digit Floating Point Numbers' Precision
Musbah J. Aqel
2007-01-01
Full Text Available IEEE standard 754 floating point is the most common representation used for floating point numbers, and many computer arithmetic algorithms are developed for basic operations on this standard. In this study, new computer algorithms are proposed to increase the precision range and to solve some problems that are available while using these algorithms. However, these algorithms provide an optional range of required accuracy (Mega-Digit precision to meet new computer's applications.
WACODI: A generic algorithm to derive the intrinsic color of natural waters from digital images
Novoa, S.; Wernand, M.; van der Woerd, H.J.
2015-01-01
This document presents the WAter COlor from Digital Images (WACODI) algorithm, which extracts the color of natural waters from images collected by low-cost digital cameras, in the context of participatory science and water quality monitoring. SRGB images are converted to the CIE XYZ color space, und
Negative base encoding in optical linear algebra processors
Perlee, C.; Casasent, D.
1986-01-01
In the digital multiplication by analog convolution algorithm, the bits of two encoded numbers are convolved to form the product of the two numbers in mixed binary representation; this output can be easily converted to binary. Attention is presently given to negative base encoding, treating base -2 initially, and then showing that the negative base system can be readily extended to any radix. In general, negative base encoding in optical linear algebra processors represents a more efficient technique than either sign magnitude or 2's complement encoding, when the additions of digitally encoded products are performed in parallel.
Embedded Processor Oriented Compiler Infrastructure
DJUKIC, M.
2014-08-01
Full Text Available In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture.
Flaxer, Eli
2014-08-01
We present a new design of a compact, ultra fast, high resolution and high-powered, pulse generator for inductive load, using power MOSFET, dedicated gate driver and a digital signal controller. This design is an improved circuit of our old version controller. We demonstrate the performance of this pulse generator as a driver for a new generation of high-pressure supersonic pulsed valves.
A WAVELET TRANSFORM BASED WATERMARKING ALGORITHM FOR PROTECTING COPYRIGHTS OF DIGITAL IMAGES
Divya A
2013-08-01
Full Text Available This paper proposes an algorithm of Digital Watermarking based on Biorthogonal Wavelet Transform. Digital Watermarking is a technique to protect the copyright of the multimedia data. The position of the watermark can be detected without using the original image by utilizing the correlation between the neighbours of wave co-efficient. The strength of Digital watermark is obtained according to the edge intensities resulting in good robust and Imperceptible. Results show that the proposed watermark algorithm is invisible and has good robustness against common image processing operations.
Poster: Comparison of two global digital algorithms for Minkowski tensor estimation
Christensen, Sabrina Tang
We present a comparison of two global digital algorithms for estimation of Minkowski tensors of sets in dimension two with positive reach given only a digitisation of the set. We give recommendations for the choice of variables utilised by the algorithms and examine accuracy of the latter...
Mishra, Kumar Vijay
The recent spate in the use of solid-state transmitters for weather radar systems has unexceptionably revolutionized the research in meteorology. The solid-state transmitters allow transmission of low peak powers without losing the radar range resolution by allowing the use of pulse compression waveforms. In this research, a novel frequency-diversity wideband waveform is proposed and realized to extenuate the low sensitivity of solid-state radars and mitigate the blind range problem tied with the longer pulse compression waveforms. The latest developments in the computing landscape have permitted the design of wideband digital receivers which can process this novel waveform on Field Programmable Gate Array (FPGA) chips. In terms of signal processing, wideband systems are generally characterized by the fact that the bandwidth of the signal of interest is comparable to the sampled bandwidth; that is, a band of frequencies must be selected and filtered out from a comparable spectral window in which the signal might occur. The development of such a wideband digital receiver opens a window for exciting research opportunities for improved estimation of precipitation measurements for higher frequency systems such as X, Ku and Ka bands, satellite-borne radars and other solid-state ground-based radars. This research describes various unique challenges associated with the design of a multi-channel wideband receiver. The receiver consists of twelve channels which simultaneously downconvert and filter the digitized intermediate-frequency (IF) signal for radar data processing. The product processing for the multi-channel digital receiver mandates a software and network architecture which provides for generating and archiving a single meteorological product profile culled from multi-pulse profiles at an increased data date. The multi-channel digital receiver also continuously samples the transmit pulse for calibration of radar receiver gain and transmit power. The multi
Conde Mui\\~no, Patricia; The ATLAS collaboration
2016-01-01
General purpose Graphics Processor Units (GPGPU) are being evaluated for possible future inclusion in an upgraded ATLAS High Level Trigger farm. We have developed a demonstrator including GPGPU implementations of Inner Detector and Muon tracking and Calorimeter clustering within the ATLAS software framework. ATLAS is a general purpose particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system consists of two levels, with level 1 implemented in hardware and the High Level Trigger implemented in software running on a farm of commodity CPU. The High Level Trigger reduces the trigger rate from the 100 kHz level 1 acceptance rate to 1 kHz for recording, requiring an average per-event processing time of ~250 ms for this task. The selection in the high level trigger is based on reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Calorimeter. Performing this reconstruction within the available farm resources presents a significant ...
A personification heuristic Genetic Algorithm for Digital Microfluidics-based Biochips Placement
Jingsong Yang
2013-06-01
Full Text Available A personification heuristic Genetic Algorithm is established for the placement of digital microfluidics-based biochips, in which, the personification heuristic algorithm is used to control the packing process, while the genetic algorithm is designed to be used in multi-objective placement results optimizing. As an example, the process of microfluidic module physical placement in multiplexed in-vitro diagnostics on human physiological fluids is simulated. The experiment results show that personification heuristic genetic algorithm can achieve better results in multi-objective optimization, compare to the parallel recombinative simulated annealing algorithm.
Automatic digital document processing and management problems, algorithms and techniques
Ferilli, Stefano
2011-01-01
This text reviews the issues involved in handling and processing digital documents. Examining the full range of a document's lifetime, this book covers acquisition, representation, security, pre-processing, layout analysis, understanding, analysis of single components, information extraction, filing, indexing and retrieval. This title: provides a list of acronyms and a glossary of technical terms; contains appendices covering key concepts in machine learning, and providing a case study on building an intelligent system for digital document and library management; discusses issues of security,
AN ITERATIVE ALGORITHM FOR OPTIMAL DESIGN OF NON-FREQUENCY-SELECTIVE FIR DIGITAL FILTERS
Duan Miyi; Sun Chunlai; Liu Xin; Tian Xinguang
2008-01-01
This paper proposes a novel iterative algorithm for optimal design of non-frequency-se-lective Finite Impulse Response (FIR) digital filters based on the windowing method. Different from the traditional optimization concept of adjusting the window or the filter order in the windowing design of an FIR digital filter,the key idea of the algorithm is minimizing the approximation error by succes-sively modifying the design result through an iterative procedure under the condition of a fixed window length. In the iterative procedure,the known deviation of the designed frequency response in each iteration from the ideal frequency response is used as a reference for the next iteration. Because the approximation error can be specified variably,the algorithm is applicable for the design of FIR digital filters with different technical requirements in the frequency domain. A design example is employed to illustrate the efficiency of the algorithm.
Real-Time Implementation of an Efficient Speech Enhancement Algorithm for Digital Hearing Aids
GAO Jie; ZHANG Hui; HU Guangshu
2006-01-01
In order to remove background noise and improve the quality of speech for digital hearing aids, a single-channel speech enhancement algorithm is proposed. The algorithm is implemented and assessed on a digital hearing aid platform based on the TI DSP TMS320VC5502 chip. Assuming that background noise is stationary or varies slowly, an energy-based voice activity detection algorithm is adopted by adaptively tracking the minima and maxima of the power envelope in noisy speech. The target speech is then enhanced by using a Wiener filter, on the basis of a short-term power spectral estimation. To deal with the distracting musical noise of the processed speech, phase randomization, along with adjacent spectral averaging, is adopted. Objective measures and an informal hearing test both show an improved performance as well as obvious attenuation of residual noise. The low power consumption and high efficiency render the whole algorithm very applicable for use in digital hearing aids.
RT-A100 High-Speed Digital Signal Processor and Application%高速数字信号处理器RT—A100及其应用
李明; 伊锐; 蔡文彬
2001-01-01
RT-A100 is a cascadable high speed digital signal processor with autonomous intelligence copyright,developed by Nanjing Research Institute of Electronics Technology.The processor can be compatible with IMSA100 processor in pin distribution manufactured by famous INMOS company,RT-A100 processor has the same function as IMSA100,meanwhile.Through the corresponding improvement,RT-A100 processor has better performance.This paper has presented the function,performance and application of RT-A100 in details.%RT-A100可级联高速数字信号处理器是南京电子技术研究所开发的具有自主知识产权的数字信号处理器。该信号处理器与著名的INMOS公司的IMSA100在引脚分配上完全兼容，功能上也完全含盖了IMSA100，并有针对性地进行了改进，在性能上完全超过了IMSA100。本文详细地描述了RT-A100的功能、性能及应用。
Bamatraf, Abdullah; Salleh, Mohd Najib Mohd
2011-01-01
In this paper, we introduce a new digital watermarking algorithm using least significant bit (LSB). LSB is used because of its little effect on the image. This new algorithm is using LSB by inversing the binary values of the watermark text and shifting the watermark according to the odd or even number of pixel coordinates of image before embedding the watermark. The proposed algorithm is flexible depending on the length of the watermark text. If the length of the watermark text is more than ((MxN)/8)-2 the proposed algorithm will also embed the extra of the watermark text in the second LSB. We compare our proposed algorithm with the 1-LSB algorithm and Lee's algorithm using Peak signal-to-noise ratio (PSNR). This new algorithm improved its quality of the watermarked image. We also attack the watermarked image by using cropping and adding noise and we got good results as well.
Dunham, Mark Edward [Los Alamos National Laboratory; Baker, Zachary K [Los Alamos National Laboratory; Stettler, Matthew W [Los Alamos National Laboratory; Pigue, Michael J [Los Alamos National Laboratory; Schmierer, Eric N [Los Alamos National Laboratory; Power, John F [Los Alamos National Laboratory; Graham, Paul S [Los Alamos National Laboratory
2009-01-01
Los Alamos has recently completed the latest in a series of Reconfigurable Software Radios, which incorporates several key innovations in both hardware design and algorithms. Due to our focus on satellite applications, each design must extract the best size, weight, and power performance possible from the ensemble of Commodity Off-the-Shelf (COTS) parts available at the time of design. In this case we have achieved 1 TeraOps/second signal processing on a 1920 Megabit/second datastream, while using only 53 Watts mains power, 5.5 kg, and 3 liters. This processing capability enables very advanced algorithms such as our wideband RF compression scheme to operate remotely, allowing network bandwidth constrained applications to deliver previously unattainable performance.
Comparison of two global digital algorithms for Minkowski tensor estimation
The geometry of real world objects can be described by Minkowski tensors. Algorithms have been suggested to approximate Minkowski tensors if only a binary image of the object is available. This paper presents implementations of two such algorithms. The theoretical convergence properties are confi...... are confirmed by simulations on test sets, and recommendations for input arguments of the algorithms are given. For increasing resolutions, we obtain more accurate estimators for the Minkowski tensors. Digitisations of more complicated objects are shown to require higher resolutions....
李鹏
2004-01-01
介绍同步突发静态RAM的特点及结构,并就其与DSP(digital signal processor)的接口信号、控制寄存器、读写操作、时序设计,数据访问时的等待状态等进行讨论.最后给出一个SBSRAM在信号处理系统中的应用实例.
New Generation Digital Signal Processor TMS320055X & CPU Structure%新一代数字号处理器TMS320C55X及其CPU结构
邓勇; 施文康; 刘琪
2001-01-01
TMS320C55X is a low-power, general purpose digital signal processor. This paper describes the CPU architecture.%TMS320C55X是一种低功耗高性能的数字信号处理器，本文介绍了其主要特性，并详细分析了TMS320C55X的CPU结构。
Digital Image Encryption Algorithm Design Based on Genetic Hyperchaos
Jian Wang
2016-01-01
Full Text Available In view of the present chaotic image encryption algorithm based on scrambling (diffusion is vulnerable to choosing plaintext (ciphertext attack in the process of pixel position scrambling, we put forward a image encryption algorithm based on genetic super chaotic system. The algorithm, by introducing clear feedback to the process of scrambling, makes the scrambling effect related to the initial chaos sequence and the clear text itself; it has realized the image features and the organic fusion of encryption algorithm. By introduction in the process of diffusion to encrypt plaintext feedback mechanism, it improves sensitivity of plaintext, algorithm selection plaintext, and ciphertext attack resistance. At the same time, it also makes full use of the characteristics of image information. Finally, experimental simulation and theoretical analysis show that our proposed algorithm can not only effectively resist plaintext (ciphertext attack, statistical attack, and information entropy attack but also effectively improve the efficiency of image encryption, which is a relatively secure and effective way of image communication.
An algorithm for approximate rectification of digital aerial images
High-resolution aerial photography is one of the most valuable tools available for managing extensive landscapes. With recent advances in digital camera technology, computer hardware, and software, aerial photography is easier to collect, store, and transfer than ever before. Images can be automa...
Algorithmic information theory mathematics of digital information processing
Seibt, Peter
2007-01-01
Treats the Mathematics of many important areas in digital information processing. This book covers, in a unified presentation, five topics: Data Compression, Cryptography, Sampling (Signal Theory), Error Control Codes, Data Reduction. It is useful for teachers, students and practitioners in Electronic Engineering, Computer Science and Mathematics.
AN ADAPTIVE DIGITAL IMAGE WATERMARK ALGORITHM BASED ON GRAY-SCALE MORPHOLOGY
Tong Ming; Hu Jia; Ji Hongbing
2009-01-01
An adaptive digital image watermark algorithm with strong robustness based on gray-scale morphology is proposed in this paper.The embedded strategies include:The algorithm seeks and extracts adaptively the image strong texture regions.The algorithm maps the image strong texture region to the wavelet tree structures,and embeds adaptively watermark into the wavelet coefficients corresponding to the image's strong texture regions.According to the visual masking features,the algorithm adjusts adaptively the watermark-embedding intensity.Experimental results show the algorithm is robust to compression,filtering,noise as well as strong shear attacks.The algorithm is blind watermark scheme.The image strong texture region extraction method based on morphology in this algorithm is simple and effective and adaptive to various images.
A DIGITAL CALIBRATION ALGORITHM WITH VARIABLE-AMPLITUDE DITHERING FOR DOMAIN-EXTENDED PIPELINE ADCS
Ting Li
2014-02-01
Full Text Available The pseudorandom noise dither (PN dither technique is used to measure domain-extended pipeline analog-to-digital converter (ADC gain errors and to calibrate them digitally, while the digital error correction technique is used to correct the comparator offsets through the use of redundancy bits. However, both these techniques suffer from three disadvantages: slow convergence speed, deduction of the amplitude of the transmitting signal, and deduction of the redundancy space. A digital calibration algorithm with variable-amplitude dithering for domain-extended pipeline ADCs is used in this research to overcome these disadvantages. The proposed algorithm is implemented in a 12-bit, 100 MS/s sample-rate pipeline ADC. The simulation results illustrate both static and dynamic performance improvement after calibration. Moreover, the convergence speed is much faster.
BACKPROPAGATION TRAINING ALGORITHM WITH ADAPTIVE PARAMETERS TO SOLVE DIGITAL PROBLEMS
R. Saraswathi
2011-01-01
Full Text Available An efficient technique namely Backpropagation training with adaptive parameters using Lyapunov Stability Theory for training single hidden layer feed forward network is proposed. A three-layered Feedforward neural network architecture is used to solve the selected problems. Sequential Training Mode is used to train the network. Lyapunov stability theory is employed to ensure the faster and steady state error convergence and to construct and energy surface with a single global minimum point through the adaptive adjustment of the weights and the adaptive parameter ß. To avoid local minima entrapment, an adaptive backpropagation algorithm based on Lyapunov stability theory is used. Lyapunov stability theory gives the algorithm, the efficiency of attaining a single global minimum point. The learning parameters used in this algorithm is responsible for the faster error convergence. The adaptive learning parameter used in this algorithm is chosen properly for faster error convergence. The error obtained has been asymptotically converged to zero according to Lyapunov Stability theory. The performance of the adaptive Backpropagation algorithm is measured by solving parity problem, half adder and full adder problems.
Abhishek Banerjee
2015-01-01
Full Text Available The technological progress in the digitalization of a complete histological glass slide has opened a new door in the tissue based diagnosis. Automated slide diagnosis can be made possible by the use of mathematical algorithms which are formulated by binary codes or values. These algorithms (diagnostic algorithms include both object based (object features, structures and pixel based (texture measures. The intra- and inter-observer errors inherent in the visual diagnosis of a histopathological slide are largely replaced by the use of diagnostic algorithms leading to a standardized and reproducible diagnosis. The present paper reviews the advances in digital histopathology especially related to the use of mathematical algorithms (diagnostic algorithms in the field of oral histopathology. The literature was reviewed for data relating to the use of algorithms utilized in the construction of computational software with special applications in oral histopathological diagnosis. The data were analyzed, and the types and end targets of the algorithms were tabulated. The advantages, specificities and reproducibility of the software, its shortcomings and its comparison with traditional methods of histopathological diagnosis were evaluated. Algorithms help in automated slide diagnosis by creating software with possible reduced errors and bias with a high degree of specificity, sensitivity, and reproducibility. Akin to the identification of thumbprints and faces, software for histopathological diagnosis will in the near future be an important part of the histopathological diagnosis.
Robust message authentication code algorithm for digital audio recordings
Zmudzinski, Sascha; Steinebach, Martin
2007-02-01
Current systems and protocols for integrity and authenticity verification of media data do not distinguish between legitimate signal transformation and malicious tampering that manipulates the content. Furthermore, they usually provide no localization or assessment of the relevance of such manipulations with respect to human perception or semantics. We present an algorithm for a robust message authentication code (RMAC) to verify the integrity of audio recodings by means of robust audio fingerprinting and robust perceptual hashing. Experimental results show that the proposed algorithm provides both a high level of distinction between perceptually different audio data and a high robustness against signal transformations that do not change the perceived information.
Algorithm for Design of Digital Notch Filter Using Simulation
Amit Verma
2013-08-01
Full Text Available A smooth waveform is generated of low frequency signal can be achieved through the Digital Notch Filter. Noise can be easily eliminated from a speech signal by using a Notch filter. In this paper the design of notch filter using MATLAB has been designed and implemented. The performance and characteristics of the filter has been shown in the waveform in the conclusion part of the paper.
Jaraíz-Simón, María D; Gómez-Pulido, Juan A; Vega-Rodríguez, Miguel A; Sánchez-Pérez, Juan M
2012-01-01
When a mobile wireless sensor is moving along heterogeneous wireless sensor networks, it can be under the coverage of more than one network many times. In these situations, the Vertical Handoff process can happen, where the mobile sensor decides to change its connection from a network to the best network among the available ones according to their quality of service characteristics. A fitness function is used for the handoff decision, being desirable to minimize it. This is an optimization problem which consists of the adjustment of a set of weights for the quality of service. Solving this problem efficiently is relevant to heterogeneous wireless sensor networks in many advanced applications. Numerous works can be found in the literature dealing with the vertical handoff decision, although they all suffer from the same shortfall: a non-comparable efficiency. Therefore, the aim of this work is twofold: first, to develop a fast decision algorithm that explores the entire space of possible combinations of weights, searching that one that minimizes the fitness function; and second, to design and implement a system on chip architecture based on reconfigurable hardware and embedded processors to achieve several goals necessary for competitive mobile terminals: good performance, low power consumption, low economic cost, and small area integration.
Juan M. Sánchez-Pérez
2012-02-01
Full Text Available When a mobile wireless sensor is moving along heterogeneous wireless sensor networks, it can be under the coverage of more than one network many times. In these situations, the Vertical Handoff process can happen, where the mobile sensor decides to change its connection from a network to the best network among the available ones according to their quality of service characteristics. A fitness function is used for the handoff decision, being desirable to minimize it. This is an optimization problem which consists of the adjustment of a set of weights for the quality of service. Solving this problem efficiently is relevant to heterogeneous wireless sensor networks in many advanced applications. Numerous works can be found in the literature dealing with the vertical handoff decision, although they all suffer from the same shortfall: a non-comparable efficiency. Therefore, the aim of this work is twofold: first, to develop a fast decision algorithm that explores the entire space of possible combinations of weights, searching that one that minimizes the fitness function; and second, to design and implement a system on chip architecture based on reconfigurable hardware and embedded processors to achieve several goals necessary for competitive mobile terminals: good performance, low power consumption, low economic cost, and small area integration.
Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture
Antelo, Elisardo; Lang, Tomas; Montuschi, Paolo
2005-01-01
The reciprocal and square-root reciprocal operations are important in several applications. For these operations, we present algorithms that combine a digit-by-digit module and one iteration of a quadratic-convergence approximation. The latter is implemented by a digit-recurrence, which uses......-up of about 2 and, because of the approximation part, the area factor is also about 2. We also show a combined implementation for both operations that has essentially the same complexity as that for square-root reciprocal alone....
ShearLab: A Rational Design of a Digital Parabolic Scaling Algorithm
Kutyniok, Gitta; Zhuang, Xiaosheng
2011-01-01
Multivariate problems are typically governed by anisotropic features such as edges in images. A common bracket of most of the various directional representation systems which have been proposed to deliver sparse approximations of such features is the utilization of parabolic scaling. One prominent example is the shearlet system. Our objective in this paper is three-fold: We firstly develop a digital shearlet theory which is rationally designed in the sense that it is the digitization of the existing shearlet theory for continuous data. This implicates that shearlet theory provides a unified treatment of both the continuum and digital realm. Secondly, we analyze the utilization of pseudo-polar grids and the pseudo-polar Fourier transform for digital implementations of parabolic scaling algorithms. We derive an isometric pseudo-polar Fourier transform by careful weighting of the pseudo-polar grid, allowing exploitation of its adjoint for the inverse transform. This leads to a digital implementation of the shear...
1981-07-01
1p^^i-J\\\\^3^\\\\^. TECHNICAL LIBRARY AD^y^.q ijg. TECHNICAL REPORT ARBRL-TR-02346 COMPUTER ALGORITHMS FOR THE DESIGN AND IMPLEMENTATION OF LINEAR...INSTRUCTIONS BEFORE COMPLETI?>G FORM 1. REPORT NUMBER TECHNICAL REPORT ARBRL-TR-n2.^46 i. GOVT ACCESSION NO. *. TITLE fand Sijfam;»; COMPUTER ... ALGORITHMS FOR THE DESIGN AND IMPLEMENTATION OF LINEAR PHASE FINPTE IMPULSE RESPONSE DIGITAL FILTERS 7. AUTHORf*; James N. Walbert 9
A novel blinding digital watermark algorithm based on lab color space
Dong, Bing-feng; Qiu, Yun-jie; Lu, Hong-tao
2010-02-01
It is necessary for blinding digital image watermark algorithm to extract watermark information without any extra information except the watermarked image itself. But most of the current blinding watermark algorithms have the same disadvantage: besides the watermarked image, they also need the size and other information about the original image when extracting the watermark. This paper presents an innovative blinding color image watermark algorithm based on Lab color space, which does not have the disadvantages mentioned above. This algorithm first marks the watermark region size and position through embedding some regular blocks called anchor points in image spatial domain, and then embeds the watermark into the image. In doing so, the watermark information can be easily extracted after doing cropping and scale change to the image. Experimental results show that the algorithm is particularly robust against the color adjusting and geometry transformation. This algorithm has already been used in a copyright protecting project and works very well.
Kim, Ye-seul; Park, Hye-suk; Lee, Haeng-Hwa; Choi, Young-Wook; Choi, Jae-Gu; Kim, Hak Hee; Kim, Hee-Joung
2016-02-01
Digital breast tomosynthesis (DBT) is a recently developed system for three-dimensional imaging that offers the potential to reduce the false positives of mammography by preventing tissue overlap. Many qualitative evaluations of digital breast tomosynthesis were previously performed by using a phantom with an unrealistic model and with heterogeneous background and noise, which is not representative of real breasts. The purpose of the present work was to compare reconstruction algorithms for DBT by using various breast phantoms; validation was also performed by using patient images. DBT was performed by using a prototype unit that was optimized for very low exposures and rapid readout. Three algorithms were compared: a back-projection (BP) algorithm, a filtered BP (FBP) algorithm, and an iterative expectation maximization (EM) algorithm. To compare the algorithms, three types of breast phantoms (homogeneous background phantom, heterogeneous background phantom, and anthropomorphic breast phantom) were evaluated, and clinical images were also reconstructed by using the different reconstruction algorithms. The in-plane image quality was evaluated based on the line profile and the contrast-to-noise ratio (CNR), and out-of-plane artifacts were evaluated by means of the artifact spread function (ASF). Parenchymal texture features of contrast and homogeneity were computed based on reconstructed images of an anthropomorphic breast phantom. The clinical images were studied to validate the effect of reconstruction algorithms. The results showed that the CNRs of masses reconstructed by using the EM algorithm were slightly higher than those obtained by using the BP algorithm, whereas the FBP algorithm yielded much lower CNR due to its high fluctuations of background noise. The FBP algorithm provides the best conspicuity for larger calcifications by enhancing their contrast and sharpness more than the other algorithms; however, in the case of small-size and low
HYBRID CHRIPTOGRAPHY STREAM CIPHER AND RSA ALGORITHM WITH DIGITAL SIGNATURE AS A KEY
Grace Lamudur Arta Sihombing
2017-03-01
Full Text Available Confidentiality of data is very important in communication. Many cyber crimes that exploit security holes for entry and manipulation. To ensure the security and confidentiality of the data, required a certain technique to encrypt data or information called cryptography. It is one of the components that can not be ignored in building security. And this research aimed to analyze the hybrid cryptography with symmetric key by using a stream cipher algorithm and asymmetric key by using RSA (Rivest Shamir Adleman algorithm. The advantages of hybrid cryptography is the speed in processing data using a symmetric algorithm and easy transfer of key using asymmetric algorithm. This can increase the speed of transaction processing data. Stream Cipher Algorithm using the image digital signature as a keys, that will be secured by the RSA algorithm. So, the key for encryption and decryption are different. Blum Blum Shub methods used to generate keys for the value p, q on the RSA algorithm. It will be very difficult for a cryptanalyst to break the key. Analysis of hybrid cryptography stream cipher and RSA algorithms with digital signatures as a key, indicates that the size of the encrypted file is equal to the size of the plaintext, not to be larger or smaller so that the time required for encryption and decryption process is relatively fast.
Vedivision – A Fast Bcd Division Algorithm Facilitated by Vedic Mathematics
Diganta Sengupta
2013-08-01
Full Text Available Of the four elementary operations, division is the most time consuming and expensive operation in modern day processors. This paper uses the tricks based on Ancient Indian Vedic Mathematics System to achieve a generalized algorithm for BCD division in a much time efficient and optimised manner than the conventional algorithms in literature. It has also been observed that the algorithm in concern exhibits remarkable results when executed on traditional mid range processors with numbers having size up to 15 digits (50 bits. The present form of the algorithm can divide numbers having 38 digits (127 bits which can be further enhanced by simple modifications.
A Multiresolution Image Completion Algorithm for Compressing Digital Color Images
R. Gomathi
2014-01-01
Full Text Available This paper introduces a new framework for image coding that uses image inpainting method. In the proposed algorithm, the input image is subjected to image analysis to remove some of the portions purposefully. At the same time, edges are extracted from the input image and they are passed to the decoder in the compressed manner. The edges which are transmitted to decoder act as assistant information and they help inpainting process fill the missing regions at the decoder. Textural synthesis and a new shearlet inpainting scheme based on the theory of p-Laplacian operator are proposed for image restoration at the decoder. Shearlets have been mathematically proven to represent distributed discontinuities such as edges better than traditional wavelets and are a suitable tool for edge characterization. This novel shearlet p-Laplacian inpainting model can effectively reduce the staircase effect in Total Variation (TV inpainting model whereas it can still keep edges as well as TV model. In the proposed scheme, neural network is employed to enhance the value of compression ratio for image coding. Test results are compared with JPEG 2000 and H.264 Intracoding algorithms. The results show that the proposed algorithm works well.
Design of Digital IIR Filter with Conflicting Objectives Using Hybrid Gravitational Search Algorithm
D. S. Sidhu
2015-01-01
Full Text Available In the recent years, the digital IIR filter design as a single objective optimization problem using evolutionary algorithms has gained much attention. In this paper, the digital IIR filter design is treated as a multiobjective problem by minimizing the magnitude response error, linear phase response error and optimal order simultaneously along with meeting the stability criterion. Hybrid gravitational search algorithm (HGSA has been applied to design the digital IIR filter. GSA technique is hybridized with binary successive approximation (BSA based evolutionary search method for exploring the search space locally. The relative performance of GSA and hybrid GSA has been evaluated by applying these techniques to standard mathematical test functions. The above proposed hybrid search techniques have been applied effectively to solve the multiparameter and multiobjective optimization problem of low-pass (LP, high-pass (HP, band-pass (BP, and band-stop (BS digital IIR filter design. The obtained results reveal that the proposed technique performs better than other algorithms applied by other researchers for the design of digital IIR filter with conflicting objectives.
Multi-Rate Digital Control Systems with Simulation Applications. Volume II. Computer Algorithms
1980-09-01
34 ~AFWAL-TR-80-31 01 • • Volume II L IL MULTI-RATE DIGITAL CONTROL SYSTEMS WITH SIMULATiON APPLICATIONS Volume II: Computer Algorithms DENNIS G. J...29 Ma -8 - Volume II. Computer Algorithms ~ / ’+ 44MWLxkQT N Uwe ~~ 4 ~jjskYIF336l5-79-C-369~ 9. PER~rORMING ORGANIZATION NAME AND ADDRESS IPROG AMEL...additional options. The analytical basis for the computer algorithms is discussed in Ref. 12. However, to provide a complete description of the program, some
An Effective Digital Watermarking Algorithm for Binary Text Image
HU Zhihua; QIN Zhongping
2006-01-01
Aiming at the binary text image's characteristics of simple pixel, complex texture and bad immunity of information concealment, a digital watermarking embedment location choosing method has been put forward based upon compatible roughness set. The method divides binary text image into different equivalent classes. Equivalent classes are further divided into different subclasses according to each pixel's degree and texture changes between blocks. Through properties' combination, the embedment block and location which are fit for watermarking are found out. At last, different binary text images are chosen for emulation experiment. After being embedded, the image is compressed in JPIG-2. Gaussian noise, salt & pepper noise are added and cutting is employed to imitate the actual environment in which images may suffer from various attacks and interferences. The result shows that the detector has a sound testing effect under various conditions.
Implementing a Vector Controller Using 68k Processors
Mohammad Bagher
2009-01-01
Full Text Available Problem statement: This study described the design of a 3-phase AC Induction Motor (ACIM vector control drive with position encoder coupled to the motor shaft. Approach: It was based on free scale's (Motorola's 68k micro processor devices. Although the free scale 56F80x (56800 core and 56F8300 (56800E core families were well-suited for digital motor control and offer all things was needed, but we decided to realize a complete vector controller with a powerful 68k processor. Results: Obviously all 680X0 and many 683XX can overcome this task very easily, but we decided 68332 for time consuming because it combines high-performance data manipulation capabilities with powerful peripheral subsystems. All software and hardware was based on Peter J. Pinewski's nice research from Motorola. Conclusion: In this study the overall software algorithm and in two fellow papers the hardware schematics and performance will be described respectively.
YIN Hong; CHEN Zeng-qiang; YUAN Zhu-zhi
2006-01-01
@@ A hyperchaos-based watermarking algorithm is developed in the wavelet domain for images.The algorithm is based on discrete wavelet transform and combines the communication model with side information.We utilize a suitable scale factor to scale host image,then construct cosets for embedding digital watermarking according to scale version of the host image.Our scheme makes a tradeoff between imperceptibility and robustness,and achieves security.The extraction algorithm is a blind detection algorithm which retrieves the watermark without the original host image.In addition,we propose a new method for watermark encryption with hyperchaotic sequence.This method overcomes the drawback of small key space of chaotic sequence and improves the watermark security.Simulation results indicate that the algorithm is a well-balanced watermarking method that offers good robustness and imperceptibility.
A Total Variation Regularization Based Super-Resolution Reconstruction Algorithm for Digital Video
Zhang Liangpei
2007-01-01
Full Text Available Super-resolution (SR reconstruction technique is capable of producing a high-resolution image from a sequence of low-resolution images. In this paper, we study an efficient SR algorithm for digital video. To effectively deal with the intractable problems in SR video reconstruction, such as inevitable motion estimation errors, noise, blurring, missing regions, and compression artifacts, the total variation (TV regularization is employed in the reconstruction model. We use the fixed-point iteration method and preconditioning techniques to efficiently solve the associated nonlinear Euler-Lagrange equations of the corresponding variational problem in SR. The proposed algorithm has been tested in several cases of motion and degradation. It is also compared with the Laplacian regularization-based SR algorithm and other TV-based SR algorithms. Experimental results are presented to illustrate the effectiveness of the proposed algorithm.
Reconfigurable FFT Processor – A Broader Perspective Survey
V.Sarada
2013-04-01
Full Text Available The FFT(Fast Fourier Transform processing is one of the key procedure in the popular orthogonal frequency division multiplexing(OFDM based communication system such as Digital AudioBroadcasting(DAB,Digital Video Broadcasting Terrestrial(DVB- T,Asymmetric Digital Subscriber Loop(ADSL etc.These application domain require performing FFT in various size from 64 to 8192 point. Implementing each FFT on a dedicated IP presents a great overhead in silicon area of the chip. By supporting the different sizes of FFT for new wireless telecommunication standard may increase the time to market it. This consideration make FFT ideal candidate for reconfigurable implementation. Efficient implementation of the FFT processor with small area, low power and speed is very important. This survey paper aims at a study on efficient algorithm and architecture for reconfigurable FFT design and observes common traits of the good contribution.
Šaponjić Đorđe
2009-01-01
Full Text Available By applying the well known dualism: mean count rate - mean time between successive pulses - the equivalence between an IIR digital filter and a preset count digital rate meter has been demonstrated. By using a bank of four second order IIR filters and an optimized automated algorithm for filter selection, a practical realization of a preset count rate meter giving good tradeoff between statistical fluctuations and speed of response, particularly at low count rates such as background monitoring, is presented. The presented solution is suitable for designing portable count rate meters. The designed prototype is capable of operating up to 3600 pulses per second with an accuracy of over 4% in steady-state and response times of 1 second for the rising edge and 2 seconds for the falling edge of the mean count rate step-change.
Vladimir A. Batura
2014-11-01
Full Text Available The efficiency of orthogonal transformations application in the frequency algorithms of the digital watermarking of still images is examined. Discrete Hadamard transform, discrete cosine transform and discrete Haar transform are selected. Their effectiveness is determined by the invisibility of embedded in digital image watermark and its resistance to the most common image processing operations: JPEG-compression, noising, changing of the brightness and image size, histogram equalization. The algorithm for digital watermarking and its embedding parameters remain unchanged at these orthogonal transformations. Imperceptibility of embedding is defined by the peak signal to noise ratio, watermark stability– by Pearson's correlation coefficient. Embedding is considered to be invisible, if the value of the peak signal to noise ratio is not less than 43 dB. Embedded watermark is considered to be resistant to a specific attack, if the Pearson’s correlation coefficient is not less than 0.5. Elham algorithm based on the image entropy is chosen for computing experiment. Computing experiment is carried out according to the following algorithm: embedding of a digital watermark in low-frequency area of the image (container by Elham algorithm, exposure to a harmful influence on the protected image (cover image, extraction of a digital watermark. These actions are followed by quality assessment of cover image and watermark on the basis of which efficiency of orthogonal transformation is defined. As a result of computing experiment it was determined that the choice of the specified orthogonal transformations at identical algorithm and parameters of embedding doesn't influence the degree of imperceptibility for a watermark. Efficiency of discrete Hadamard transform and discrete cosine transformation in relation to the attacks chosen for experiment was established based on the correlation indicators. Application of discrete Hadamard transform increases
Ari Muzakir
2017-05-01
Full Text Available Ease of deployment of digital image through the internet has positive and negative sides, especially for owners of the original digital image. The positive side of the ease of rapid deployment is the owner of that image deploys digital image files to various sites in the world address. While the downside is that if there is no copyright that serves as protector of the image it will be very easily recognized ownership by other parties. Watermarking is one solution to protect the copyright and know the results of the digital image. With Digital Image Watermarking, copyright resulting digital image will be protected through the insertion of additional information such as owner information and the authenticity of the digital image. The least significant bit (LSB is one of the algorithm is simple and easy to understand. The results of the simulations carried out using android smartphone shows that the LSB watermarking technique is not able to be seen by naked human eye, meaning there is no significant difference in the image of the original files with images that have been inserted watermarking. The resulting image has dimensions of 640x480 with a bit depth of 32 bits. In addition, to determine the function of the ability of the device (smartphone in processing the image using this application used black box testing.
Automatic Rotation Recovery Algorithm for Accurate Digital Image and Video Watermarks Extraction
Nasr addin Ahmed Salem Al-maweri
2016-11-01
Full Text Available Research in digital watermarking has evolved rapidly in the current decade. This evolution brought various different methods and algorithms for watermarking digital images and videos. Introduced methods in the field varies from weak to robust according to how tolerant the method is implemented to keep the existence of the watermark in the presence of attacks. Rotation attacks applied to the watermarked media is one of the serious attacks which many, if not most, algorithms cannot survive. In this paper, a new automatic rotation recovery algorithm is proposed. This algorithm can be plugged to any image or video watermarking algorithm extraction component. The main job for this method is to detect the geometrical distortion happens to the watermarked image/images sequence; recover the distorted scene to its original state in a blind and automatic way and then send it to be used by the extraction procedure. The work is limited to have a recovery process to zero padded rotations for now, cropped images after rotation is left as future work. The proposed algorithm is tested on top of extraction component. Both recovery accuracy and the extracted watermarks accuracy showed high performance level.
Libera Electron Beam Position Processor
Ursic, Rok
2005-01-01
Libera is a product family delivering unprecedented possibilities for either building powerful single station solutions or architecting complex feedback systems in the field of accelerator instrumentation and controls. This paper presents functionality and field performance of its first member, the electron beam position processor. It offers superior performance with multiple measurement channels delivering simultaneously position measurements in digital format with MHz kHz and Hz bandwidths. This all-in-one product, facilitating pulsed and CW measurements, is much more than simply a high performance beam position measuring device delivering micrometer level reproducibility with sub-micrometer resolution. Rich connectivity options and innate processing power make it a powerful feedback building block. By interconnecting multiple Libera electron beam position processors one can build a low-latency high throughput orbit feedback system without adding additional hardware. Libera electron beam position processor ...
1982-01-01
well as to business, industry , science, and government in general. In these applications it serves as an aid to complex reasoning, e.g., in the...propositional calculus in a fundamental way. More well-known are its applications to the design of industrial process-control machines, digital computers...Dpto. Electricidad y Electronica , Facultad de Ciencias, Universidad de Granada, Spain, 1977. 27. Matney, R. M. and C. H. Roth, "Associative computing
Video rate morphological processor based on a redundant number representation
Kuczborski, Wojciech; Attikiouzel, Yianni; Crebbin, Gregory A.
1992-03-01
This paper presents a video rate morphological processor for automated visual inspection of printed circuit boards, integrated circuit masks, and other complex objects. Inspection algorithms are based on gray-scale mathematical morphology. Hardware complexity of the known methods of real-time implementation of gray-scale morphology--the umbra transform and the threshold decomposition--has prompted us to propose a novel technique which applied an arithmetic system without carrying propagation. After considering several arithmetic systems, a redundant number representation has been selected for implementation. Two options are analyzed here. The first is a pure signed digit number representation (SDNR) with the base of 4. The second option is a combination of the base-2 SDNR (to represent gray levels of images) and the conventional twos complement code (to represent gray levels of structuring elements). Operation principle of the morphological processor is based on the concept of the digit level systolic array. Individual processing units and small memory elements create a pipeline. The memory elements store current image windows (kernels). All operation primitives of processing units apply a unified direction of digit processing: most significant digit first (MSDF). The implementation technology is based on the field programmable gate arrays by Xilinx. This paper justified the rationality of a new approach to logic design, which is the decomposition of Boolean functions instead of Boolean minimization.
Optimal design study of high order FIR digital filters based on neural network algorithm
王小华; 何怡刚
2004-01-01
An optimal design approach of high order FIR digital filter is developed based on the algorithm of neural networks with cosine basis function . The main idea is to minimize the sum of the square errors between the amplitude response of the desired FIR filter and that of the designed by training the weights of neural networks, then obtains the impulse response of FIR digital filter . The convergence theorem of the neural networks algorithm is presented and proved,and the optimal design method is introduced by designing four kinds of FIR digital filters , i.e., low-pass, high-pass,bandpass , and band-stop FIR digital filter. The results of the amplitude responses show that attenuation in stop-bands is more than 60 dB with no ripple and pulse existing in pass-bands, and cutoff frequency of passband and stop-band is easily controlled precisely . The presented optimal design approach of high order FIR digital filter is significantly effective.
A Digital Control Algorithm for Magnetic Suspension Systems
Britton, Thomas C.
1996-01-01
An ongoing program exists to investigate and develop magnetic suspension technologies and modelling techniques at NASA Langley Research Center. Presently, there is a laboratory-scale large air-gap suspension system capable of five degree-of-freedom (DOF) control that is operational and a six DOF system that is under development. Those systems levitate a cylindrical element containing a permanent magnet core above a planar array of electromagnets, which are used for levitation and control purposes. In order to evaluate various control approaches with those systems, the Generic Real-Time State-Space Controller (GRTSSC) software package was developed. That control software package allows the user to implement multiple control methods and allows for varied input/output commands. The development of the control algorithm is presented. The desired functionality of the software is discussed, including the ability to inject noise on sensor inputs and/or actuator outputs. Various limitations, common issues, and trade-offs are discussed including data format precision; the drawbacks of using either Direct Memory Access (DMA), interrupts, or program control techniques for data acquisition; and platform dependent concerns related to the portability of the software, such as memory addressing formats. Efforts to minimize overall controller loop-rate and a comparison of achievable controller sample rates are discussed. The implementation of a modular code structure is presented. The format for the controller input data file and the noise information file is presented. Controller input vector information is available for post-processing by mathematical analysis software such as MATLAB1.
Oris Krianto Sulaiman
2016-09-01
Full Text Available Keamanan dan kerahasiaan informasi merupakan hal yang sangat penting, banyak hal yang telah dilakukan agar keamanan dan kerahasiaan informasi ini terjaga dengan utuh , salah satunya dengan menggunakan teknik kriptografi, kriptografi berperan untuk menjaga kemanan informasi dengan menyandikan informasi tersebut, salah satu algoritma kriptografi untuk penyandian yaitu DES, dimana DES akan melakukan pengacakan berdasarkan s-box hingga 16 putaran, selain menjaga kemanan dan kerahasiaan diperlukan juga nirpenyangkalan dengan menggunakan digital signature algorithm (DSA atau tanda tangan digital yang mana bertujuan untuk melakukan verifikasi apakah pesan atau informasi tersebut diterima dalam keadaan asli dari pengiriman atau telah dimodifikasi sehingga pesan atau informasi tersebut tidaklah asli.
Malte Baesler
2013-01-01
and decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carry-propagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.
A Hashing-Based Search Algorithm for Coding Digital Images by Vector Quantization
Chu, Chen-Chau
1989-11-01
This paper describes a fast algorithm to compress digital images by vector quantization. Vector quantization relies heavily on searching to build codebooks and to classify blocks of pixels into code indices. The proposed algorithm uses hashing, localized search, and multi-stage search to accelerate the searching process. The average of pixel values in a block is used as the feature for hashing and intermediate screening. Experimental results using monochrome images are presented. This algorithm compares favorably with other methods with regard to processing time, and has comparable or better mean square error measurements than some of them. The major advantages of the proposed algorithm are its speed, good quality of the reconstructed images, and flexibility.
Tsai Chi-Yi
2011-01-01
Full Text Available Abstract This article addresses the problem of low dynamic range image enhancement for commercial digital cameras. A novel simultaneous dynamic range compression and local contrast enhancement algorithm (SDRCLCE is presented to resolve this problem in a single-stage procedure. The proposed SDRCLCE algorithm is able to combine with many existent intensity transfer functions, which greatly increases the applicability of the proposed method. An adaptive intensity transfer function is also proposed to combine with SDRCLCE algorithm that provides the capability to adjustably control the level of overall lightness and contrast achieved at the enhanced output. Moreover, the proposed method is amenable to parallel processing implementation that allows us to improve the processing speed of SDRCLCE algorithm. Experimental results show that the performance of the proposed method outperforms three state-of-the-art methods in terms of dynamic range compression and local contrast enhancement.
An image based auto-focusing algorithm for digital fundus photography.
Moscaritolo, Michele; Jampel, Henry; Knezevich, Frederick; Zeimer, Ran
2009-11-01
In fundus photography, the task of fine focusing the image is demanding and lack of focus is quite often the cause of suboptimal photographs. The introduction of digital cameras has provided an opportunity to automate the task of focusing. We have developed a software algorithm capable of identifying best focus. The auto-focus (AF) method is based on an algorithm we developed to assess the sharpness of an image. The AF algorithm was tested in the prototype of a semi-automated nonmydriatic fundus camera designed to screen in the primary care environment for major eye diseases. A series of images was acquired in volunteers while focusing the camera on the fundus. The image with the best focus was determined by the AF algorithm and compared to the assessment of two masked readers. A set of fundus images was obtained in 26 eyes of 20 normal subjects and 42 eyes of 28 glaucoma patients. The 95% limits of agreement between the readers and the AF algorithm were -2.56 to 2.93 and -3.7 to 3.84 diopter and the bias was 0.09 and 0.71 diopter, for the two readers respectively. On average, the readers agreed with the AF algorithm on the best correction within less than 3/4 diopter. The intraobserver repeatability was 0.94 and 1.87 diopter, for the two readers respectively, indicating that the limit of agreement with the AF algorithm was determined predominantly by the repeatability of each reader. An auto-focus algorithm for digital fundus photography can identify the best focus reliably and objectively. It may improve the quality of fundus images by easing the task of the photographer.
Experiences on developing digital down conversion algorithms using Xilinx system generator
Xu, Chengfa; Yuan, Yuan; Zhao, Lizhi
2013-07-01
The Digital Down Conversion (DDC) algorithm is a classical signal processing method which is widely used in radar and communication systems. In this paper, the DDC function is implemented by Xilinx System Generator tool on FPGA. System Generator is an FPGA design tool provided by Xilinx Inc and MathWorks Inc. It is very convenient for programmers to manipulate the design and debug the function, especially for the complex algorithm. Through the developing process of DDC function based on System Generator, the results show that System Generator is a very fast and efficient tool for FPGA design.
A wearable real-time image processor for a vision prosthesis.
Tsai, D; Morley, J W; Suaning, G J; Lovell, N H
2009-09-01
Rapid progress in recent years has made implantable retinal prostheses a promising therapeutic option in the near future for patients with macular degeneration or retinitis pigmentosa. Yet little work on devices that encode visual images into electrical stimuli have been reported to date. This paper presents a wearable image processor for use as the external module of a vision prosthesis. It is based on a dual-core microprocessor architecture and runs the Linux operating system. A set of image-processing algorithms executes on the digital signal processor of the device, which may be controlled remotely via a standard desktop computer. The results indicate that a highly flexible and configurable image processor can be built with the dual-core architecture. Depending on the image-processing requirements, general-purpose embedded microprocessors alone may be inadequate for implementing image-processing strategies required by retinal prostheses.
Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems
Downie, John D.
1990-01-01
A ground-based adaptive optics imaging telescope system attempts to improve image quality by detecting and correcting for atmospherically induced wavefront aberrations. The required control computations during each cycle will take a finite amount of time. Longer time delays result in larger values of residual wavefront error variance since the atmosphere continues to change during that time. Thus an optical processor may be well-suited for this task. This paper presents a study of the accuracy requirements in a general optical processor that will make it competitive with, or superior to, a conventional digital computer for the adaptive optics application. An optimization of the adaptive optics correction algorithm with respect to an optical processor's degree of accuracy is also briefly discussed.
Implementing kinematics computation in FPGA co-processor for a 6-DOF space manipulator
Zheng Yili; Sun Hanxu; Jia Qingxuan; Shi Guozhen
2009-01-01
Based on the coordinate rotation digital computer (CORDIC) algorithm, the high-speed kinematics calculation for a six degree of freedom (DOF) space manipulator is implemented in a field programmable gate array (FPGA) co-processor. A pipeline architecture is adopted to reduce the complexity and time-consumption of the kinematics calculation. The CORDIC soft-core and the CORDIC-based pipelined kinematics calculation co-processor are described with the very-high-speed integrated circuit hardware description language (VHDL) language and realized in the FPGA. Finally, the feasibility of the design is validated in the Spartan-3 FPGA of Xilinx Inc., and the performance specifications of FPGA co-processor are discussed. The results show that time-consumption of the kinematics calculation is greatly reduced.
Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems
Downie, John D.
1990-01-01
A ground-based adaptive optics imaging telescope system attempts to improve image quality by detecting and correcting for atmospherically induced wavefront aberrations. The required control computations during each cycle will take a finite amount of time. Longer time delays result in larger values of residual wavefront error variance since the atmosphere continues to change during that time. Thus an optical processor may be well-suited for this task. This paper presents a study of the accuracy requirements in a general optical processor that will make it competitive with, or superior to, a conventional digital computer for the adaptive optics application. An optimization of the adaptive optics correction algorithm with respect to an optical processor's degree of accuracy is also briefly discussed.
Neo, Atsushi; Kakue, Takashi; Shimobaba, Tomoyoshi; Masuda, Nobuyuki; Ito, Tomoyoshi
2017-04-01
Digital holography is expected to be useful in the analysis of moving three-dimensional (3D) image measurement. In this technique, a two-dimensional interference fringe recorded using a 3D image is captured with an image sensor, and the 3D image is reproduced on a computer. To obtain the reproduced 3D images with high spatial resolution, a high-performance image sensor is required, which increases the system cost. We propose an algorithm for super-resolution processing in digital holography that does not require a high-performance image sensor. The proposed algorithm wherein 3D images are considered as the aggregation of object points improves spatial resolution by performing a light-intensity search of the reproduced image and the object points.
Аndriy V. Sadchenko
2015-12-01
Full Text Available Digital television systems need to ensure that all digital signals processing operations are performed simultaneously and consistently. Frame synchronization dictated by the need to match phases of transmitter and receiver so that it would be possible to identify the start of a frame. As a frame synchronization signals are often used long length binary sequence with good aperiodic autocorrelation function. Aim: This work is dedicated to the development of the algorithm of random length sequences synthesis. Materials and Methods: The paper provides a comparative analysis of the known sequences, which can be used at present as synchronization ones, revealed their advantages and disadvantages. This work proposes the algorithm for the synthesis of binary synchronization sequences of random length with good autocorrelation properties based on noise generator with a uniform distribution law of probabilities. A "white noise" semiconductor generator is proposed to use as the initial material for the synthesis of binary sequences with desired properties. Results: The statistical analysis of the initial implementations of the "white noise" and synthesized sequences for frame synchronization of digital television is conducted. The comparative analysis of the synthesized sequences with known ones was carried out. The results show the benefits of obtained sequences in compare with known ones. The performed simulations confirm the obtained results. Conclusions: Thus, the search algorithm of binary synchronization sequences with desired autocorrelation properties received. According to this algorithm, the sequence can be longer in length and without length limitations. The received sync sequence can be used for frame synchronization in modern digital communication systems that will increase their efficiency and noise immunity.
Design of Low Pass Digital FIR Filter Using Cuckoo Search Algorithm
Taranjit Singh; Harvinder Singh Josan
2014-01-01
This paper presents a novel approach of designing linear phase FIR low pass filter using cuckoo Search Algorithm (CSA). FIR filter design is a multi-modal optimization problem. The conventional optimization techniques are not efficient for digital filter design. An iterative method is introduced to find the best solution of FIR filter design problem.Flat passband and high stopband attenuation are the major characteristics required in FIR filter design. To achieve these charact...
Algorithm for Extracting Digital Terrain Models under Forest Canopy from Airborne LiDAR Data
Almasi S. Maguya
2014-07-01
Full Text Available Extracting digital elevationmodels (DTMs from LiDAR data under forest canopy is a challenging task. This is because the forest canopy tends to block a portion of the LiDAR pulses from reaching the ground, hence introducing gaps in the data. This paper presents an algorithm for DTM extraction from LiDAR data under forest canopy. The algorithm copes with the challenge of low data density by generating a series of coarse DTMs by using the few ground points available and using trend surfaces to interpolate missing elevation values in the vicinity of the available points. This process generates a cloud of ground points from which the final DTM is generated. The algorithm has been compared to two other algorithms proposed in the literature in three different test sites with varying degrees of difficulty. Results show that the algorithm presented in this paper is more tolerant to low data density compared to the other two algorithms. The results further show that with decreasing point density, the differences between the three algorithms dramatically increased from about 0.5m to over 10m.
Array processors based on Gaussian fraction-free method
Peng, S.; Sedukhin, S. [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I.
1998-03-01
The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)
Zhu, Wu; Fang, Jian-an; Tang, Yang; Zhang, Wenbing; Du, Wei
2012-01-01
Design of a digital infinite-impulse-response (IIR) filter is the process of synthesizing and implementing a recursive filter network so that a set of prescribed excitations results a set of desired responses. However, the error surface of IIR filters is usually non-linear and multi-modal. In order to find the global minimum indeed, an improved differential evolution (DE) is proposed for digital IIR filter design in this paper. The suggested algorithm is a kind of DE variants with a controllable probabilistic (CPDE) population size. It considers the convergence speed and the computational cost simultaneously by nonperiodic partial increasing or declining individuals according to fitness diversities. In addition, we discuss as well some important aspects for IIR filter design, such as the cost function value, the influence of (noise) perturbations, the convergence rate and successful percentage, the parameter measurement, etc. As to the simulation result, it shows that the presented algorithm is viable and comparable. Compared with six existing State-of-the-Art algorithms-based digital IIR filter design methods obtained by numerical experiments, CPDE is relatively more promising and competitive.
Practical Constraint K-Segment Principal Curve Algorithms for Generating Railway GPS Digital Map
Dewang Chen
2013-01-01
Full Text Available In order to obtain a decent trade-off between the low-cost, low-accuracy Global Positioning System (GPS receivers and the requirements of high-precision digital maps for modern railways, using the concept of constraint K-segment principal curves (CKPCS and the expert knowledge on railways, we propose three practical CKPCS generation algorithms with reduced computational complexity, and thereafter more suitable for engineering applications. The three algorithms are named ALLopt, MPMopt, and DCopt, in which ALLopt exploits global optimization and MPMopt and DCopt apply local optimization with different initial solutions. We compare the three practical algorithms according to their performance on average projection error, stability, and the fitness for simple and complex simulated trajectories with noise data. It is found that ALLopt only works well for simple curves and small data sets. The other two algorithms can work better for complex curves and large data sets. Moreover, MPMopt runs faster than DCopt, but DCopt can work better for some curves with cross points. The three algorithms are also applied in generating GPS digital maps for two railway GPS data sets measured in Qinghai-Tibet Railway (QTR. Similar results like the ones in synthetic data are obtained. Because the trajectory of a railway is relatively simple and straight, we conclude that MPMopt works best according to the comprehensive considerations on the speed of computation and the quality of generated CKPCS. MPMopt can be used to obtain some key points to represent a large amount of GPS data. Hence, it can greatly reduce the data storage requirements and increase the positioning speed for real-time digital map applications.
Diaz, Claudia C.
2007-11-01
I present some results of contrast enhancement and segmentation of microcalcifications in digital mammograms. These mammograms were obtained from MIAS-minidatabase and using a CR to digitize images. White-top-hat and black-top-hat transformations were used to improve the contrast of images, while reconstruction-by-dilation algorithm was used to emphasize the microcalcifications over the tissues. Segmentation was done using different gradient matrices. These algorithms intended to show some details which were not evident in original images.
Digitalized accurate modeling of SPCB with multi-spiral surface based on CPC algorithm
Huang, Yanhua; Gu, Lizhi
2015-09-01
The main methods of the existing multi-spiral surface geometry modeling include spatial analytic geometry algorithms, graphical method, interpolation and approximation algorithms. However, there are some shortcomings in these modeling methods, such as large amount of calculation, complex process, visible errors, and so on. The above methods have, to some extent, restricted the design and manufacture of the premium and high-precision products with spiral surface considerably. This paper introduces the concepts of the spatially parallel coupling with multi-spiral surface and spatially parallel coupling body. The typical geometry and topological features of each spiral surface forming the multi-spiral surface body are determined, by using the extraction principle of datum point cluster, the algorithm of coupling point cluster by removing singular point, and the "spatially parallel coupling" principle based on the non-uniform B-spline for each spiral surface. The orientation and quantitative relationships of datum point cluster and coupling point cluster in Euclidean space are determined accurately and in digital description and expression, coupling coalescence of the surfaces with multi-coupling point clusters under the Pro/E environment. The digitally accurate modeling of spatially parallel coupling body with multi-spiral surface is realized. The smooth and fairing processing is done to the three-blade end-milling cutter's end section area by applying the principle of spatially parallel coupling with multi-spiral surface, and the alternative entity model is processed in the four axis machining center after the end mill is disposed. And the algorithm is verified and then applied effectively to the transition area among the multi-spiral surface. The proposed model and algorithms may be used in design and manufacture of the multi-spiral surface body products, as well as in solving essentially the problems of considerable modeling errors in computer graphics and
A CNN-Specific Integrated Processor
Suleyman Malki
2009-01-01
Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.
A CNN-Specific Integrated Processor
Malki, Suleyman; Spaanenburg, Lambert
2009-12-01
Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.
A dynamic material discrimination algorithm for dual MV energy X-ray digital radiography.
Li, Liang; Li, Ruizhe; Zhang, Siyuan; Zhao, Tiao; Chen, Zhiqiang
2016-08-01
Dual-energy X-ray radiography has become a well-established technique in medical, industrial, and security applications, because of its material or tissue discrimination capability. The main difficulty of this technique is dealing with the materials overlapping problem. When there are two or more materials along the X-ray beam path, its material discrimination performance will be affected. In order to solve this problem, a new dynamic material discrimination algorithm is proposed for dual-energy X-ray digital radiography, which can also be extended to multi-energy X-ray situations. The algorithm has three steps: α-curve-based pre-classification, decomposition of overlapped materials, and the final material recognition. The key of the algorithm is to establish a dual-energy radiograph database of both pure basis materials and pair combinations of them. After the pre-classification results, original dual-energy projections of overlapped materials can be dynamically decomposed into two sets of dual-energy radiographs of each pure material by the algorithm. Thus, more accurate discrimination results can be provided even with the existence of the overlapping problem. Both numerical and experimental results that prove the validity and effectiveness of the algorithm are presented.
Williamson, Ben
2015-01-01
The emergence of digitized health and physical education, or "eHPE", embeds software algorithms in the organization of health and physical education pedagogies. Particularly with the emergence of wearable and mobile activity trackers, biosensors and personal analytics apps, algorithmic processes have an increasingly powerful part to play…
Land-cover classification with an expert classification algorithm using digital aerial photographs
José L. de la Cruz
2010-05-01
Full Text Available The purpose of this study was to evaluate the usefulness of the spectral information of digital aerial sensors in determining land-cover classification using new digital techniques. The land covers that have been evaluated are the following, (1 bare soil, (2 cereals, including maize (Zea mays L., oats (Avena sativa L., rye (Secale cereale L., wheat (Triticum aestivum L. and barley (Hordeun vulgare L., (3 high protein crops, such as peas (Pisum sativum L. and beans (Vicia faba L., (4 alfalfa (Medicago sativa L., (5 woodlands and scrublands, including holly oak (Quercus ilex L. and common retama (Retama sphaerocarpa L., (6 urban soil, (7 olive groves (Olea europaea L. and (8 burnt crop stubble. The best result was obtained using an expert classification algorithm, achieving a reliability rate of 95%. This result showed that the images of digital airborne sensors hold considerable promise for the future in the field of digital classifications because these images contain valuable information that takes advantage of the geometric viewpoint. Moreover, new classification techniques reduce problems encountered using high-resolution images; while reliabilities are achieved that are better than those achieved with traditional methods.
Indra Kanta Maitra
2011-06-01
Full Text Available Many image processing techniques have been developed over the past two decades to help radiologists in diagnosing breast cancer. At the same time, many studies proven that an early diagnosis of breastcancer can increase the survival rate, thus making screening programmes a mandatory step for females.Radiologists have to examine a large number of images. Digital Mammogram has emerged as the most popular screening technique for early detection of Breast Cancer and other abnormalities. Raw digital mammograms are medical images that are difficult to interpret so we need to develop Computer Aided Diagnosis (CAD systems that will improve detection of abnormalities in mammogram images. Extraction of the breast region by delineation of the breast contour and pectoral muscle allows the search for abnormalities to be limited to the region of the breast without undue influence from the background of the mammogram. We need to performessential pre-processing steps to suppress artifacts, enhance the breast region and then extract breast region by the process of segmentation. In this paper we present a fully automated scheme for detection of abnormal masses by anatomical segmentation of Breast Region of Interest (ROI. We are using medio-lateral oblique (MLO view of mammograms. We have proposed a new homogeneity enhancement process namely Binary Homogeneity Enhancement Algorithm (BHEA, followed by an innovative approach for edge detection (EDA. Then obtain the breast boundary by using our proposed Breast Boundary Detection Algorithm (BBDA. After we use our proposed Pectoral Muscle Detection Algorithm (PMDA to suppress the pectoral muscle thus obtaining the breast ROI, we use our proposed Anatomical Segmentation of Breast ROI (ASB algorithm to differentiate various regions within the breast. After segregating the different breast regions we use our proposed Seeded Region Growing Algorithm (SRGA to isolate normal and abnormal regions in the breast tissue. If any
Optimizing Live Digital Evidence Mining Using Structural Subroutines of Apriori Algorithm
Akshay Zadgaonkar,
2011-04-01
Full Text Available The Scope and Complexity of the Internet has grown exponentially. This growth hasmade digital forensic investigation a very challenging task. Even the modest intra-organizationalnetworks have sufficient network traffic to pose a problem for digital crime investigators topolice and collect evidences. Another problem in Network based Crime Investigation is thatOffline Mining Techniques do not yield pervasive evidence. At the same time due to voluminoustraffic, live evidence mining becomes a challenge. This paper presents a technique to optimize thelive evidence mining by using the principles of apriori algorithm to trigger the evidence collectionmechanism at right and opportune moment. The crux of this technique is answering “When &What Information” to Collect about a subject of investigation or Data.
Secure Digital Certificate Design Based on the Public Key Cryptography Algorithm
Zhang Qi ming
2013-07-01
Full Text Available With the popularity of the Internet, more and more people choose online shopping, however, in the case of lacking security measures, there is a great deal of risk on the Internet. to this situation,In response to this situation, this paper presents a digital certificate based on the X.509 standard. This paper uses the C language generation public key algorithm (RSA,Realization of the digital certificate registration, verification and certificate generation process,the identity of certification users can be verified and provide proof of identity on the Internet transactions ,reducing the transaction risks greatly , ensuring the user's property and interests are not infringed.
Grayer, G H
1981-01-01
Experiment UA1 is a large multipurpose spectrometer at the CERN proton-antiproton collider. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead-time losses due to the bunched nature of the beam. To achieve this fast 8-bit charge to digital converters have been built followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, and to transverse energy in the other. Each processor forms four sums from a chosen combination of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in...
Berends, Constantijn J.; van de Wal, Roderik S. W.
2016-12-01
Many processes govern the deglaciation of ice sheets. One of the processes that is usually ignored is the calving of ice in lakes that temporarily surround the ice sheet. In order to capture this process a "flood-fill algorithm" is needed. Here we present and evaluate several optimizations to a standard flood-fill algorithm in terms of computational efficiency. As an example, we determine the land-ocean mask for a 1 km resolution digital elevation model (DEM) of North America and Greenland, a geographical area of roughly 7000 by 5000 km (roughly 35 million elements), about half of which is covered by ocean. Determining the land-ocean mask with our improved flood-fill algorithm reduces computation time by 90 % relative to using a standard stack-based flood-fill algorithm. This implies that it is now feasible to include the calving of ice in lakes as a dynamical process inside an ice-sheet model. We demonstrate this by using bedrock elevation, ice thickness and geoid perturbation fields from the output of a coupled ice-sheet-sea-level equation model at 30 000 years before present and determine the extent of Lake Agassiz, using both the standard and improved versions of the flood-fill algorithm. We show that several optimizations to the flood-fill algorithm used for filling a depression up to a water level, which is not defined beforehand, decrease the computation time by up to 99 %. The resulting reduction in computation time allows determination of the extent and volume of depressions in a DEM over large geographical grids or repeatedly over long periods of time, where computation time might otherwise be a limiting factor. The algorithm can be used for all glaciological and hydrological models, which need to trace the evolution over time of lakes or drainage basins in general.
A New Echeloned Poisson Series Processor (EPSP)
Ivanova, Tamara
2001-07-01
A specialized Echeloned Poisson Series Processor (EPSP) is proposed. It is a typical software for the implementation of analytical algorithms of Celestial Mechanics. EPSP is designed for manipulating long polynomial-trigonometric series with literal divisors. The coefficients of these echeloned series are the rational or floating-point numbers. The Keplerian processor and analytical generator of special celestial mechanics functions based on the EPSP are also developed.
Practical algorithms for simulation and reconstruction of digital in-line holograms
Latychevskaia, Tatiana
2014-01-01
Here, we present practical methods for simulation and reconstruction of in-line digital holograms recorded with plane and spherical waves. The algorithms described here are applicable to holographic imaging of an object exhibiting absorption as well as phase shifting properties. Optimal parameters, related to distances, sampling rate, and other factors for successful simulation and reconstruction of holograms are evaluated and criteria for the achievable resolution are worked out. Moreover, we show that the numerical procedures for the reconstruction of holograms recorded with plane and spherical waves are identical under certain conditions. Experimental examples of holograms and their reconstructions are also discussed.
An Efficient 16-Bit Multiplier based on Booth Algorithm
Khan, M. Zamin Ali; Saleem, Hussain; Afzal, Shiraz; Naseem, Jawed
2012-11-01
Multipliers are key components of many high performance systems such as microprocessors, digital signal processors, etc. Optimizing the speed and area of the multiplier is major design issue which is usually conflicting constraint so that improving speed results mostly in bigger areas. A VHDL designed architecture based on booth multiplication algorithm is proposed which not only optimize speed but also efficient on energy use.
An effective detection algorithm for region duplication forgery in digital images
Yavuz, Fatih; Bal, Abdullah; Cukur, Huseyin
2016-04-01
Powerful image editing tools are very common and easy to use these days. This situation may cause some forgeries by adding or removing some information on the digital images. In order to detect these types of forgeries such as region duplication, we present an effective algorithm based on fixed-size block computation and discrete wavelet transform (DWT). In this approach, the original image is divided into fixed-size blocks, and then wavelet transform is applied for dimension reduction. Each block is processed by Fourier Transform and represented by circle regions. Four features are extracted from each block. Finally, the feature vectors are lexicographically sorted, and duplicated image blocks are detected according to comparison metric results. The experimental results show that the proposed algorithm presents computational efficiency due to fixed-size circle block architecture.
Simple digital phase-measuring algorithm for low-noise heterodyne interferometry
Kokuyama, Wataru; Ohta, Akihiro; Hattori, Koichiro
2016-01-01
We present a digital algorithm for measuring the phase difference between two sinusoidal signals that combines the modified fringe-counting method with two-sample zero crossing to enable sequential signal processing. This technique can be applied to a phase meter for measuring dynamic phase differences with high resolution, particularly for heterodyne interferometry. The floor noise obtained from a demonstration with an electrical apparatus is $5\\times10^{-8} \\mathrm{rad/\\sqrt{Hz}}$ at frequencies above approximately 0.1 Hz. In addition, by applying this method to a commercial heterodyne interferometer, the floor-noise level is confirmed to be $7\\times10^{-14} \\mathrm{m/\\sqrt{Hz}}$ from 4 kHz to 1 MHz. We also confirm the validity of the algorithm by comparing its results with those from a standard homodyne interferometer for measuring shock-motion peak acceleration greater than 5000 m/s^2 and a 10 mm stroke.
Research on adaptive acoustic echo cancellation algorithm in digital hearing aids
Ma, Min; Wang, Mingjiang; Hu, Jiebin
2017-08-01
At present, the study of acoustic echo cancellation (AEC) is mainly based on the adaptive acoustic echo cancellation algorithm. It is proved that the echo signal of the near-end microphone must be compensated by the time delay to achieve the purpose of echo cancellation, and the accuracy of the delay estimation affecting the final effect of echo cancellation. This paper proposes a combination of the normalized minimum mean square algorithm (NLMS) and the time delay estimation model to solve the echo problem in hearing aids. In this paper, using generalized cross correlation (GCC) to estimate time delay. In addition, using the energy, Teager-Kaiser Energy Operator (TKEO) and the signal correlation coefficient as the threshold value to detect the howling signal in digital hearing aids. Finally, the simulation and experimental results are given. The experiment proves that the method has good effect.
Jaeger, Markus, E-mail: jaeger@informatik.uni-leipzig.de [Faculty of Mathematics and Computer Science, University of Leipzig, PF 100920, 04009 Leipzig (Germany); Butz, Tilman, E-mail: butz@physik.uni-leipzig.de [Faculty of Physics and Earth Sciences, University of Leipzig, Linnestr. 5, 04103 Leipzig (Germany)
2012-05-11
In a recent development of a fully digital spectrometer for time differential perturbed angular correlations a true constant fraction trigger (CFT) algorithm was implemented that, however, allowed for integer delays, i.e. integer multiples of the sampling interval, only. With a sampling rate of 1 GS/s and BaF{sub 2} scintillators this turned out to be insufficient. Here, we present an extension of the algorithm to fractional delays implemented in field programmable gate arrays (FPGAs). Furthermore, we derive a criterion for the delay for optimum timing based on the steepest slope of the CFT signal. Experimental data are given for LaBr{sub 3}(Ce) scintillators and 511 keV-511 keV prompt coincidences that corroborate the theoretical result.
Design of Low Pass Digital FIR Filter Using Cuckoo Search Algorithm
Taranjit Singh
2014-08-01
Full Text Available This paper presents a novel approach of designing linear phase FIR low pass filter using cuckoo Search Algorithm (CSA. FIR filter design is a multi-modal optimization problem. The conventional optimization techniques are not efficient for digital filter design. An iterative method is introduced to find the best solution of FIR filter design problem.Flat passband and high stopband attenuation are the major characteristics required in FIR filter design. To achieve these characteristics, a Cuckoo Search algorithm (CSA is proposed in this paper. CSA have been used here for the design of linear phase finite impulse response (FIR filters. Results are presented in this paper that seems to be promising tool for FIR filter design
Error Analysis for a Navigation Algorithm based on Optical-Flow and a Digital Terrain Map
Kupervasser, Oleg; Rivlin, Ehud; 10.1109/PLANS.2008.4570040
2011-01-01
The paper deals with the error analysis of a navigation algorithm that uses as input a sequence of images acquired by a moving camera and a Digital Terrain Map (DTM) of the region been imaged by the camera during the motion. The main sources of error are more or less straightforward to identify: camera resolution, structure of the observed terrain and DTM accuracy, field of view and camera trajectory. After characterizing and modeling these error sources in the framework of the CDTM algorithm, a closed form expression for their effect on the pose and motion errors of the camera can be found. The analytic expression provides a priori measurements for the accuracy in terms of the parameters mentioned above.
Power estimation on functional level for programmable processors
M. Schneider
2004-01-01
the input parameters of the Correspondence to: H. Blume (blume@eecs.rwth-aachen.de arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. This approach is exemplarily demonstrated and evaluated applying two modern digital signal processors and a variety of basic algorithms of digital signal processing. The resulting estimation values for the inspected algorithms are compared to physically measured values. A resulting maximum estimation error of 3% is achieved.
Evaluation of the algorithms for recovering reflectance from virtual digital camera response
Ana Gebejes
2012-10-01
Full Text Available In the recent years many new methods for quality control in graphic industry are proposed. All of these methodshave one in common – using digital camera as a capturing device and appropriate image processing method/algorithmto obtain desired information. With the development of new, more accurate sensors, digital cameras becameeven more dominant and the use of cameras as measuring device became more emphasized. The idea of using cameraas spectrophotometer is interesting because this kind of measurement would be more economical, faster, widelyavailable and it would provide a possibility of multiple colour capture with a single shot. This can be very usefulfor capturing colour targets for characterization of different properties of a print device. A lot of effort is put into enablingcommercial colour CCD cameras (3 acquisition channels to obtain enough of the information for reflectancerecovery. Unfortunately, RGB camera was not made with the idea of performing colour measurements but ratherfor producing an image that is visually pleasant for the observer. This somewhat complicates the task and seeks fora development of different algorithms that will estimate the reflectance information from the available RGB cameraresponses with minimal possible error. In this paper three different reflectance estimation algorithms are evaluated(Orthogonal projection,Wiener and optimized Wiener estimation, together with the method for reflectance approximationbased on principal component analysis (PCA. The aim was to perform reflectance estimation pixelwise and analyze the performance of some reflectance estimation algorithms locally, at some specific pixels in theimage, and globally, on the whole image. Performances of each algorithm were evaluated visually and numericallyby obtaining pixel wise colour difference and pixel wise difference of estimated reflectance to the original values. Itwas concluded that Wiener method gives the best reflectance estimation
Dorai, Kavita; Arvind; Kumar, Anil
2001-01-01
We describe the experimental implementation of a recently proposed quantum algorithm involving quantum entanglement at the level of two qubits using NMR. The algorithm solves a generalisation of the Deutsch problem and distinguishes between even and odd functions using fewer function calls than is possible classically. The manipulation of entangled states of the two qubits is essential here, unlike the Deutsch-Jozsa algorithm and the Grover's search algorithm for two bits.
Ueno, A; Manabe, S; Uchikawa, Y
2005-01-01
A new system has been developed to assess human alertness and to alert the subject with acoustic stimulation in accordance with the assessed level of alertness. Dynamic characteristics of saccadic eye movement (saccade: SC) were used to calculate an alertness index. Digital signal processor was adopted for the calculation. The system was tested through eye tracking tasks. The results indicated that the developed system could awaken the subject by feeding sound back to the subject. Also, arousal reaction induced by the sound was visualized quantitatively by analyzing values of the alertness index after the stimulation. These results indicate applicability of the system not only to awakening device for accident prevention, but also to a tool for investigating effects of the stimulation.
Processor-Dependent Malware... and codes
Desnos, Anthony; Filiol, Eric
2010-01-01
Malware usually target computers according to their operating system. Thus we have Windows malwares, Linux malwares and so on ... In this paper, we consider a different approach and show on a technical basis how easily malware can recognize and target systems selectively, according to the onboard processor chip. This technology is very easy to build since it does not rely on deep analysis of chip logical gates architecture. Floating Point Arithmetic (FPA) looks promising to define a set of tests to identify the processor or, more precisely, a subset of possible processors. We give results for different families of processors: AMD, Intel (Dual Core, Atom), Sparc, Digital Alpha, Cell, Atom ... As a conclusion, we propose two {\\it open problems} that are new, to the authors' knowledge.
Yahya AL-Nabhani
2015-10-01
Full Text Available Digital watermarking, which has been proven effective for protecting digital data, has recently gained considerable research interest. This study aims to develop an enhanced technique for producing watermarked images with high invisibility. During extraction, watermarks can be successfully extracted without the need for the original image. We have developed discrete wavelet transform with a Haar filter to embed a binary watermark image in selected coefficient blocks. A probabilistic neural network is used to extract the watermark image. To evaluate the efficiency of the algorithm and the quality of the extracted watermark images, we used widely known image quality function measurements, such as peak signal-to-noise ratio (PSNR and normalized cross correlation (NCC. Results indicate the excellent invisibility of the extracted watermark image (PSNR = 68.27 dB, as well as exceptional watermark extraction (NCC = 0.9779. Experimental results reveal that the proposed watermarking algorithm yields watermarked images with superior imperceptibility and robustness to common attacks, such as JPEG compression, rotation, Gaussian noise, cropping, and median filter.
Simple digital phase-measuring algorithm for low-noise heterodyne interferometry
Kokuyama, Wataru; Nozato, Hideaki; Ohta, Akihiro; Hattori, Koichiro
2016-08-01
We present a digital algorithm for measuring the phase of a sinusoidal signal that combines the modified digital fringe-counting method with two-sample zero crossing to enable sequential signal processing. This technique can be applied to a phase meter for measuring dynamic phase differences between two sinusoidal signals with high resolution, particularly for heterodyne interferometry. The floor noise obtained from a demonstration with an electrical apparatus is 5× {{10}-8} \\text{rad}\\text{/}{{\\sqrt{\\text{Hz}}}{}} at frequencies above approximately 0.1 Hz for 80 kHz signal frequency. In addition, by applying this method to a commercial heterodyne interferometer with a modulation frequency of 80 MHz, the floor-noise level is confirmed to be 7× {{10}-14}\\text{m}\\text{/}{{\\sqrt{\\text{Hz}}}{}} from 4 kHz to 1 MHz. We also confirm the validity of the algorithm by comparing its results with those from a standard homodyne interferometer for measuring shock-motion peak acceleration greater than 5000 \\text{m} {{\\text{s}}-2} and a 10 mm stroke.
Sasaki, Makoto; Kudo, Kohsuke; Uwano, Ikuko; Goodwin, Jonathan; Higuchi, Satomi; Ito, Kenji; Yamashita, Fumio [Iwate Medical University, Division of Ultrahigh Field MRI, Institute for Biomedical Sciences, Yahaba (Japan); Boutelier, Timothe; Pautot, Fabrice [Olea Medical, Department of Research and Innovation, La Ciotat (France); Christensen, Soren [University of Melbourne, Department of Neurology and Radiology, Royal Melbourne Hospital, Victoria (Australia)
2013-10-15
A new deconvolution algorithm, the Bayesian estimation algorithm, was reported to improve the precision of parametric maps created using perfusion computed tomography. However, it remains unclear whether quantitative values generated by this method are more accurate than those generated using optimized deconvolution algorithms of other software packages. Hence, we compared the accuracy of the Bayesian and deconvolution algorithms by using a digital phantom. The digital phantom data, in which concentration-time curves reflecting various known values for cerebral blood flow (CBF), cerebral blood volume (CBV), mean transit time (MTT), and tracer delays were embedded, were analyzed using the Bayesian estimation algorithm as well as delay-insensitive singular value decomposition (SVD) algorithms of two software packages that were the best benchmarks in a previous cross-validation study. Correlation and agreement of quantitative values of these algorithms with true values were examined. CBF, CBV, and MTT values estimated by all the algorithms showed strong correlations with the true values (r = 0.91-0.92, 0.97-0.99, and 0.91-0.96, respectively). In addition, the values generated by the Bayesian estimation algorithm for all of these parameters showed good agreement with the true values [intraclass correlation coefficient (ICC) = 0.90, 0.99, and 0.96, respectively], while MTT values from the SVD algorithms were suboptimal (ICC = 0.81-0.82). Quantitative analysis using a digital phantom revealed that the Bayesian estimation algorithm yielded CBF, CBV, and MTT maps strongly correlated with the true values and MTT maps with better agreement than those produced by delay-insensitive SVD algorithms. (orig.)
High Throughput Bent-Pipe Processor Demonstrator
Tabacco, P.; Vernucci, A.; Russo, L.; Cangini, P.; Botticchio, T.; Angeletti, P.
2008-08-01
The work associated to this article is a study initiative sponsored by ESA/ESTEC that responds to the crucial need of developing new Satellite payload aimed at making rapid progresses in handling large amounts of data at a competitive price with respect to terrestrial one in the telecommunication field. Considering the quite limited band allowed to space communications at Ka band, reusing the same band in a large number of beams is mandatory: therefore beam-forming is the right technological answer. Technological progresses - mainly in the digital domain - also help greatly in increasing the satellite capacity. Next Satellite payload target are set in throughput range of 50Gbps. Despite the fact that the implementation of a wideband transparent processor for a high capacity communication payload is a very challenging task, Space Engineering team in the frame of this ESA study proposed an intermediate step of development for a scalable unit able to demonstrate both the capacity and flexibility objectives for different type of Wideband Beamforming antennas designs. To this aim the article describes the features of Wideband HW (analog and digital) platform purposely developed by Space Engineering in the frame of this ESA/ESTEC contract ("WDBFN" contract) with some preliminary system test results. The same platform and part of the associated SW will be used in the development and demonstration of the real payload digital front end Mux and Demux algorithms as well as the Beam Forming and on Board channel switching in frequency domain. At the time of this article writing, despite new FPGA and new ADC and DAC converters have become available as choices for wideband system implementation, the two HW platforms developed by Space Engineering, namely WDBFN ADC and DAC Boards, represent still the most performing units in terms of analog bandwidth, processing capability (in terms of FPGA module density), SERDES (SERiliazer DESerializers) external links density, integration form
Digital Sound Synthesis Algorithms: a Tutorial Introduction and Comparison of Methods
Lee, J. Robert
The objectives of the dissertation are to provide both a compendium of sound-synthesis methods with detailed descriptions and sound examples, as well as a comparison of the relative merits of each method based on ease of use, observed sound quality, execution time, and data storage requirements. The methods are classified under the general headings of wavetable-lookup synthesis, additive synthesis, subtractive synthesis, nonlinear methods, and physical modelling. The nonlinear methods comprise a large group that ranges from the well-known frequency-modulation synthesis to waveshaping. The final category explores computer modelling of real musical instruments and includes numerical and analytical solutions to the classical wave equation of motion, along with some of the more sophisticated time -domain models that are possible through the prudent combination of simpler synthesis techniques. The dissertation is intended to be understandable by a musician who is mathematically literate but who does not necessarily have a background in digital signal processing. With this limitation in mind, a brief and somewhat intuitive description of digital sampling theory is provided in the introduction. Other topics such as filter theory are discussed as the need arises. By employing each of the synthesis methods to produce the same type of sound, interesting comparisons can be made. For example, a struck string sound, such as that typical of a piano, can be produced by algorithms in each of the synthesis classifications. Many sounds, however, are peculiar to a single algorithm and must be examined independently. Psychoacoustic studies were conducted as an aid in the comparison of the sound quality of several implementations of the synthesis algorithms. Other psychoacoustic experiments were conducted to supplement the established notions of which timbral issues are important in the re -synthesis of the sounds of acoustic musical instruments.
P. Raspollini
2013-09-01
Full Text Available The MIPAS (Michelson Interferometer for Passive Atmospheric Sounding instrument on the Envisat (Environmental satellite satellite has provided vertical profiles of the atmospheric composition on a global scale for almost ten years. The MIPAS mission is divided in two phases: the full resolution phase, from 2002 to 2004, and the optimized resolution phase, from 2005 to 2012, which is characterized by a finer vertical and horizontal sampling attained through a reduction of the spectral resolution. While the description and characterization of the products of the ESA processor for the full resolution phase has been already described in previous papers, in this paper we focus on the performances of the latest version of the ESA (European Space Agency processor, named ML2PP V6 (MIPAS Level 2 Prototype Processor, which has been used for reprocessing the entire mission. The ESA processor had to perform the operational near real time analysis of the observations and its products needed to be available for data assimilation. Therefore, it has been designed for fast, continuous and automated analysis of observations made in quite different atmospheric conditions and for a minimum use of external constraints in order to avoid biases in the products. The dense vertical sampling of the measurements adopted in the second phase of the MIPAS mission resulted in sampling intervals finer than the instantaneous field of view of the instrument. Together with the choice of a retrieval grid aligned with the vertical sampling of the measurements, this made ill-conditioned the retrieval problem of the MIPAS operational processor. This problem has been handled with minimal changes to the original retrieval approach but with significant improvements nonetheless. The Levenberg–Marquardt method, already present in the retrieval scheme for its capability to provide fast convergence for nonlinear problems, is now also exploited for the reduction of the ill-conditioning of
Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...
EARLY EXPERIENCE WITH A HYBRID PROCESSOR: K-MEANS CLUSTERING
M. GOKHALE; ET AL
2001-02-01
We discuss hardware/software coprocessing on a hybrid processor for a compute- and data-intensive hyper-spectral imaging algorithm, K-Means Clustering. The experiments are performed on the Altera Excalibur board using the soft IP core 32-bit NIOS RISC processor. In our experiments, we compare performance of the sequential algorithm with two different accelerated versions. We consider granularity and synchronization issues when mapping an algorithm to a hybrid processor. Our results show that on the Excalibur NIOS, a 15% speedup can be achieved over the sequential algorithm on images with 8 spectral bands where the pixels are divided into 8 categories. Speedup is limited by the communication cost of transferring data from external memory through the NIOS processor to the customized circuits. Our results indicate that future hybrid processors must either (1) have a clock rate 10X the speed of the configurable logic circuits or (2) include dual port memories that both the processor and configurable logic can access. If either of these conditions is met, the hybrid processor will show a factor of 10 speedup over the sequential algorithm. Such systems will combine the convenience of conventional processors with the speed of configurable logic.
Siregar, H.; Junaeti, E.; Hayatno, T.
2017-03-01
Activities correspondence is often used by agencies or companies, so that institutions or companies set up a special division to handle issues related to the letter management. Most of the distribution of letters using electronic media, then the letter should be kept confidential in order to avoid things that are not desirable. Techniques that can be done to meet the security aspect is by using cryptography or by giving a digital signature. The addition of asymmetric and symmetric algorithms, i.e. RSA and AES algorithms, on the digital signature had been done in this study to maintain data security. The RSA algorithm was used during the process of giving digital signature, while the AES algorithm was used during the process of encoding a message that will be sent to the receiver. Based on the research can be concluded that the additions of AES and RSA algorithms on the digital signature meet four objectives of cryptography: Secrecy, Data Integrity, Authentication and Non-repudiation.
赵丽; 高新
2012-01-01
应用数字信号处理器设计了一个基于想象动作电位的脑-机接口系统,通过模拟滤波与数字信号器处理相结合的方法,实现了对想象动作电位信息的有效采集和处理.系统在硬件上设计了脑电信号放大器,DSP开发板；对脑电信号放大、AD转换后,通过分类特征提取处理后,完成动作识别与控制命令的输出.将数字信号处理器应用在脑-机接口中,利用数字信号处理器优异的处理能力和丰富的外设资源,实现了一个嵌入式、微型化的脑-机接口构建,实现了脑-机接口实时处理与微型化.%This paper presents motor-imaginary-potential-based brain-computer interface (BCI) interface by using digital signal processor (DSP). Combining analog filtering and digital processing; realize the motor imaginary potential information acquisition effectively and processing. A EEG amplifier and DSP development board were designed in system for hardware. Motor imaginary potential information through EEG-amplifier and AD converted, after classification and feature extraction,gesture recognition will be completed and control command will be output to control peripherals. In this paper, digital signal processor (DSP) is used in brain-computer interface (BCI), using the DSP achieved a brain-computer interface real-time processing and miniaturization with its excellent processing power and rich resources of the peripheral. A on embedded technology Based, Miniaturization of brain-computer interface was built.
Development of Learning Board for the Digital Relay Using DSP
Ahn, Yong Jin; Choi, Young Woo [Youho Elec. Ind. Co., LTD. (Korea)
2002-07-01
A relaying board is developed for the study of digital relay, which is based on digital Signal Processor(DSP). The present development is capable of understanding and application for digital relay hardware. To support the design of relaying hardware, first A/D convertor, MMI and serial port for communication are embedded, and next a booting cables of three types are supplied. More particularly the relaying board that is convenient to test digital relaying algorithm. This paper concludes by into a relaying board. The hardware test results show practically high performance. (author). 35 refs., 10 figs.
Wilkins, L. C.; Wintz, P. A.
1975-01-01
Many redundancy removal algorithms employ some sort of run length code. Blocks of timing words are coded with synchronization words inserted between blocks. The probability of incorrectly reconstructing a sample because of a channel error in the timing data is a monotonically nondecreasing function of time since the last synchronization word. In this paper we compute the 'probability that the accumulated magnitude of timing errors equal zero' as a function of time since the last synchronization word for a zero-order predictor (ZOP). The result is valid for any data source that can be modeled by a first-order Markov chain and any digital channel that can be modeled by a channel transition matrix. An example is presented.
Ostlund, N.S.
1980-01-01
The field of attached scientific processors (''array processors'') is surveyed, and an attempt is made to indicate their present and possible future use in computational chemistry. The current commercial products from Floating Point Systems, Inc., Datawest Corporation, and CSP, Inc. are discussed.
Pentaris, Fragkiskos P.; Makris, John P.
2013-04-01
In Structural Health Monitoring (SHM) is of great importance to reveal valuable information from the recorded SHM data that could be used to predict or indicate structural fault or damage in a building. In this work a combination of digital signal processing methods, namely FFT along with Wavelet Transform is applied, together with a proposed algorithm to study frequency dispersion, in order to depict non-linear characteristics of SHM data collected in two university buildings under natural or anthropogenic excitation. The selected buildings are of great importance from civil protection point of view, as there are the premises of a public higher education institute, undergoing high use, stress, visit from academic staff and students. The SHM data are collected from two neighboring buildings that have different age (4 and 18 years old respectively). Proposed digital signal processing methods are applied to the data, presenting a comparison of the structural behavior of both buildings in response to seismic activity, weather conditions and man-made activity. Acknowledgments This work was supported in part by the Archimedes III Program of the Ministry of Education of Greece, through the Operational Program "Educational and Lifelong Learning", in the framework of the project entitled «Interdisciplinary Multi-Scale Research of Earthquake Physics and Seismotectonics at the front of the Hellenic Arc (IMPACT-ARC) » and is co-financed by the European Union (European Social Fund) and Greek National Fund.
Tiwari, Saumya; Bhargava, Rohit
2015-06-01
Fourier transform infrared (FTIR) spectroscopic imaging is an emerging microscopy modality for clinical histopathologic diagnoses as well as for biomedical research. Spectral data recorded in this modality are indicative of the underlying, spatially resolved biochemical composition but need computerized algorithms to digitally recognize and transform this information to a diagnostic tool to identify cancer or other physiologic conditions. Statistical pattern recognition forms the backbone of these recognition protocols and can be used for highly accurate results. Aided by biochemical correlations with normal and diseased states and the power of modern computer-aided pattern recognition, this approach is capable of combating many standing questions of traditional histology-based diagnosis models. For example, a simple diagnostic test can be developed to determine cell types in tissue. As a more advanced application, IR spectral data can be integrated with patient information to predict risk of cancer, providing a potential road to precision medicine and personalized care in cancer treatment. The IR imaging approach can be implemented to complement conventional diagnoses, as the samples remain unperturbed and are not destroyed. Despite high potential and utility of this approach, clinical implementation has not yet been achieved due to practical hurdles like speed of data acquisition and lack of optimized computational procedures for extracting clinically actionable information rapidly. The latter problem has been addressed by developing highly efficient ways to process IR imaging data but remains one that has considerable scope for progress. Here, we summarize the major issues and provide practical considerations in implementing a modified Bayesian classification protocol for digital molecular pathology. We hope to familiarize readers with analysis methods in IR imaging data and enable researchers to develop methods that can lead to the use of this promising
Venkateswaran, Vijay; Pivit, Florian; Guan, Lei
2016-07-01
Modern wireless communication networks, particularly cellular networks utilize multiple antennas to improve the capacity and signal coverage. In these systems, typically an active transceiver is connected to each antenna. However, this one-to-one mapping between transceivers and antennas will dramatically increase the cost and complexity of a large phased antenna array system. In this paper, firstly we propose a \\emph{partially adaptive} beamformer architecture where a reduced number of transceivers with a digital beamformer (DBF) is connected to an increased number of antennas through an RF beamforming network (RFBN). Then, based on the proposed architecture, we present a methodology to derive the minimum number of transceivers that are required for marco-cell and small-cell base stations, respectively. Subsequently, in order to achieve optimal beampatterns with given cellular standard requirements and RF operational constraints, we propose efficient algorithms to jointly design DBF and RFBN. Starting from the proposed algorithms, we specify generic microwave RFBNs for optimal marco-cell and small-cell networks. In order to verify the proposed approaches, we compare the performance of RFBN using simulations and anechoic chamber measurements. Experimental measurement results confirm the robustness and performance of the proposed hybrid DBF-RFBN concept eventually ensuring that theoretical multi-antenna capacity and coverage are achieved at a little incremental cost.
Digital Image Analysis Algorithm For Determination of Particle Size Distributions In Diesel Engines
Armas, O.; Ballesteros, R.; Gomez, A.
One of the most serious problems associated to Diesel engines is pollutant emissions, standing out nitrogen oxides and particulate matter. However, although current emis- sions standards in Europe and America with regard to light vehicles and heavy duty engines refer the particulate limit in mass units, concern for knowing size and number of particles emitted by engines is being increased recently. This interest is promoted by last studies about particle harmful effects on health and is enhanced by recent changes in internal combustion engines technology. This study is focused on the implementation of a method to determine the particle size distribution made up in current methodology for vehicles certification in Europe. It will use an automated Digital Image Analysis Algorithm (DIAA) to determine particle size trends from Scanning Electron Microscope (SEM) images of filters charged in a dilution system used for measuring specific particulate emissions. The experimental work was performed on a steady state direct injection Diesel en- gine with 0.5 MW rated power, being considered as a typical engine in middle power industries. Particulate size distributions obtained using DIAA and a Scanning Mobil- ity Particle Sizer (SMPS), nowadays considered as the most reliable technique, were compared. Although number concentration detected by this method does not repre- sent real flowing particle concentration, this algorithm fairly reproduces the trends observed with SMPS when the engine load is varied.
Bibliographic Pattern Matching Using the ICL Distributed Array Processor.
Carroll, David M.; And Others
1988-01-01
Describes the use of a highly parallel array processor for pattern matching operations in a bibliographic retrieval system. The discussion covers the hardware and software features of the processor, the pattern matching algorithm used, and the results of experimental tests of the system. (37 references) (Author/CLB)
Xu, Beijie; Recker, Mimi; Qi, Xiaojun; Flann, Nicholas; Ye, Lei
2013-01-01
This article examines clustering as an educational data mining method. In particular, two clustering algorithms, the widely used K-means and the model-based Latent Class Analysis, are compared, using usage data from an educational digital library service, the Instructional Architect (IA.usu.edu). Using a multi-faceted approach and multiple data…
Xu, Beijie; Recker, Mimi; Qi, Xiaojun; Flann, Nicholas; Ye, Lei
2013-01-01
This article examines clustering as an educational data mining method. In particular, two clustering algorithms, the widely used K-means and the model-based Latent Class Analysis, are compared, using usage data from an educational digital library service, the Instructional Architect (IA.usu.edu). Using a multi-faceted approach and multiple data…
Bosca, Ryan J; Jackson, Edward F
2016-01-21
Assessing and mitigating the various sources of bias and variance associated with image quantification algorithms is essential to the use of such algorithms in clinical research and practice. Assessment is usually accomplished with grid-based digital reference objects (DRO) or, more recently, digital anthropomorphic phantoms based on normal human anatomy. Publicly available digital anthropomorphic phantoms can provide a basis for generating realistic model-based DROs that incorporate the heterogeneity commonly found in pathology. Using a publicly available vascular input function (VIF) and digital anthropomorphic phantom of a normal human brain, a methodology was developed to generate a DRO based on the general kinetic model (GKM) that represented realistic and heterogeneously enhancing pathology. GKM parameters were estimated from a deidentified clinical dynamic contrast-enhanced (DCE) MRI exam. This clinical imaging volume was co-registered with a discrete tissue model, and model parameters estimated from clinical images were used to synthesize a DCE-MRI exam that consisted of normal brain tissues and a heterogeneously enhancing brain tumor. An example application of spatial smoothing was used to illustrate potential applications in assessing quantitative imaging algorithms. A voxel-wise Bland-Altman analysis demonstrated negligible differences between the parameters estimated with and without spatial smoothing (using a small radius Gaussian kernel). In this work, we reported an extensible methodology for generating model-based anthropomorphic DROs containing normal and pathological tissue that can be used to assess quantitative imaging algorithms.
Bosca, Ryan J.; Jackson, Edward F.
2016-01-01
Assessing and mitigating the various sources of bias and variance associated with image quantification algorithms is essential to the use of such algorithms in clinical research and practice. Assessment is usually accomplished with grid-based digital reference objects (DRO) or, more recently, digital anthropomorphic phantoms based on normal human anatomy. Publicly available digital anthropomorphic phantoms can provide a basis for generating realistic model-based DROs that incorporate the heterogeneity commonly found in pathology. Using a publicly available vascular input function (VIF) and digital anthropomorphic phantom of a normal human brain, a methodology was developed to generate a DRO based on the general kinetic model (GKM) that represented realistic and heterogeneously enhancing pathology. GKM parameters were estimated from a deidentified clinical dynamic contrast-enhanced (DCE) MRI exam. This clinical imaging volume was co-registered with a discrete tissue model, and model parameters estimated from clinical images were used to synthesize a DCE-MRI exam that consisted of normal brain tissues and a heterogeneously enhancing brain tumor. An example application of spatial smoothing was used to illustrate potential applications in assessing quantitative imaging algorithms. A voxel-wise Bland-Altman analysis demonstrated negligible differences between the parameters estimated with and without spatial smoothing (using a small radius Gaussian kernel). In this work, we reported an extensible methodology for generating model-based anthropomorphic DROs containing normal and pathological tissue that can be used to assess quantitative imaging algorithms.
SPROC: A multiple-processor DSP IC
Davis, R.
1991-01-01
A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.
Characterization of the effects of the FineView algorithm for full field digital mammography
Urbanczyk, H.; McDonagh, E.; Marshall, N. W.; Castellano, I.
2012-04-01
The aim of this study was to characterize the effect of an image processing algorithm (FineView) on both quantitative image quality parameters and the threshold contrast detail response of the GE Senographe DS full-field digital mammography system. The system was characterized using signal transfer property, pre-sampling modulation transfer function (MTF), normalized noise power spectrum (NNPS) and detective quantum efficiency (DQE) of the system. An algorithmic modulation transfer function (MTFa) was calculated from images acquired at a reduced detector air kerma (DAK) and with the FineView algorithm enabled. Two sets of beam conditions were used: Mo/Mo/28 kV and Rh/Rh/29 kV, both with 2 mm added Al filtration at the x-ray tube. Images were acquired with and without FineView at four DAK levels from 14 to 378 µGy. The threshold contrast detail response was assessed using the CDMAM contrast-detail test object which was imaged under standard clinical conditions with and without FineView at three DAK levels from 24 to 243 µGy. The images were scored by both human observers and by automated scoring software. Results indicated an improvement of up to 125% at 5 mm-1 in MTFa when FineView was activated, particularly at high DAK levels. A corresponding increase of up to 425% at 5 mm-1 was also seen in the NNPS, again with the same DAK dependence. FineView did not influence DQE, an indication that the signal to noise ratio transfer of the system remained unchanged. FineView did not affect the threshold contrast detectability of the system, a result that is consistent with the DQE results.
A new wavelet-based reconstruction algorithm for twin image removal in digital in-line holography
Hattay, Jamel; Belaid, Samir; Aguili, Taoufik; Lebrun, Denis
2016-07-01
Two original methods are proposed here for digital in-line hologram processing. Firstly, we propose an entropy-based method to retrieve the focus plane which is very useful for digital hologram reconstruction. Secondly, we introduce a new approach to remove the so-called twin images reconstructed by holograms. This is achieved owing to the Blind Source Separation (BSS) technique. The proposed method is made up of two steps: an Adaptive Quincunx Lifting Scheme (AQLS) and a statistical unmixing algorithm. The AQLS tool is based on wavelet packet transform, whose role is to maximize the sparseness of the input holograms. The unmixing algorithm uses the Independent Component Analysis (ICA) tool. Experimental results confirm the ability of convolutive blind source separation to discard the unwanted twin image from in-line digital holograms.
Onboard Interferometric SAR Processor for the Ka-Band Radar Interferometer (KaRIn)
Esteban-Fernandez, Daniel; Rodriquez, Ernesto; Peral, Eva; Clark, Duane I.; Wu, Xiaoqing
2011-01-01
An interferometric synthetic aperture radar (SAR) onboard processor concept and algorithm has been developed for the Ka-band radar interferometer (KaRIn) instrument on the Surface and Ocean Topography (SWOT) mission. This is a mission- critical subsystem that will perform interferometric SAR processing and multi-look averaging over the oceans to decrease the data rate by three orders of magnitude, and therefore enable the downlink of the radar data to the ground. The onboard processor performs demodulation, range compression, coregistration, and re-sampling, and forms nine azimuth squinted beams. For each of them, an interferogram is generated, including common-band spectral filtering to improve correlation, followed by averaging to the final 1 1-km ground resolution pixel. The onboard processor has been prototyped on a custom FPGA-based cPCI board, which will be part of the radar s digital subsystem. The level of complexity of this technology, dictated by the implementation of interferometric SAR processing at high resolution, the extremely tight level of accuracy required, and its implementation on FPGAs are unprecedented at the time of this reporting for an onboard processor for flight applications.
Continuous history variable for programmable quantum processors
Vlasov, Alexander Yu
2010-01-01
In this brief note is discussed application of continuous quantum history ("trash") variable for simplification of scheme of programmable quantum processor. Similar scheme may be tested also in other models of the theory of quantum algorithms and complexity, because provides modification of a standard operation: quantum function evaluation.
Jaime Repollés Llauradó
2014-12-01
Full Text Available Los artistas digitales recurren a los algoritmos para generar sistemas lineales y vectoriales que se conforman como paisajes y figuras que frecuentemente evocan imaginarios acuáticos. En estos escenarios virtuales se multiplican y reverberan los atributos de las ninfas clásicas. Tanto el cibernauta posmoderno como el espectador del cine de animación pueden contemplar estas aguas digitales con la misma mirada evocadora que permitió a los poetas clásicos advertir la emergencia de las nereidas de las fuentes míticas. Aquella ninfomanía que agitó el imaginario artístico fin de siècle revive cuando advertimos ondinas posmodernas surgidas de curvas algorítmicas, emanando del mismo manantial mítico que el imaginario de la ninfa moderna, desde los objetos art nouveau hasta el cine de la era digital. AbstractDigital artists use algorithms to generate linear and vector systems which take the shape of landscapes and human figures and often evoke water imaginaria. Inside this virtual setting the attributes of classic Nymphs resonate and multiply. Both the Postmodern Internet user and the audience of animation cinema can contemplate these digital waters with the same evocative gaze that allowed classic poets to notice the emergence of Nereids from the mythical springs. The same “nymphomania” that stirred the fin de siècle artistic imaginarium revives when we notice the presence of Postmodern Undines, emerged from algorithm curves, emanating from the same mythical spring as the imaginarium of the Modern Nymph, from the Art Nouveau objects to the digital age cinema.
Kriegler, F.; Marshall, R.; Lampert, S.; Gordon, M.; Cornell, C.; Kistler, R.
1973-01-01
The MIDAS system is a prototype, multiple-pipeline digital processor mechanizing the multivariate-Gaussian, maximum-likelihood decision algorithm operating at 200,000 pixels/second. It incorporates displays and film printer equipment under control of a general purpose midi-computer and possesses sufficient flexibility that operational versions of the equipment may be subsequently specified as subsets of the system.
TC9447F, single-chip DSP (digital signal processor) for audio; 1 chip audio yo DSP LSI TC9447F
NONE
1999-03-01
TC9447F is a single-chip DSP for audio which builds in 2-channel AD converter/4-channel DA converter. It can build various application programs such as the sound field control like hall simulation, digital filter like equalizer, and dynamic range control, in the program memory (ROM). Further, it builds in {+-}10dB trim use electronic volume for two channels. It also builds data delay use RAM (64K-bit) in, so no RAM to be separately attached is necessary. (translated by NEDO)
Processor Allocation for Optimistic Parallelization of Irregular Programs
Versaci, Francesco
2012-01-01
Optimistic parallelization is a promising approach for the parallelization of irregular algorithms: potentially interfering tasks are launched dynamically, and the runtime system detects conflicts between concurrent activities, aborting and rolling back conflicting tasks. However, parallelism in irregular algorithms is very complex. In a regular algorithm like dense matrix multiplication, the amount of parallelism can usually be expressed as a function of the problem size, so it is reasonably straightforward to determine how many processors should be allocated to execute a regular algorithm of a certain size (this is called the processor allocation problem). In contrast, parallelism in irregular algorithms can be a function of input parameters, and the amount of parallelism can vary dramatically during the execution of the irregular algorithm. Therefore, the processor allocation problem for irregular algorithms is very difficult. In this paper, we describe the first systematic strategy for addressing this pro...
A Method for Analog Implementation of Centroid Tracking Algorithm in a Video Signal
Payman Moallem
2007-06-01
Full Text Available The main goal of a video tracking algorithm is finding the location of a predefined target in successive video frames. Centroid pointing is one of the most efficient methods in the target tracking. This method can be simply implemented by a digital video processing system that includes a video memory and a powerful digital processor. Usually, the cost and the complexity of the digital video processor is high and in some applications, using analog video processor that includes only electronic devices like OPAMP, diodes, transistors, resistors and capacitors has lower cost, more efficient and more reliable. Implementing of the centroid in an analog video processor is not as simple as digital one, therefore in this paper, we introduce a novel formulation of the centroid that can be implemented in an analog video processor. We simulate the proposed method by MatLab simulink and compare the results with the area-based tracking that is usually used in analog video processors. The simulation results show that the proposed method is more reliable and accurate.
基于STM32的动漫游戏系统设计%Design of digital Anime game system based on STM32 processor
李勇; 程铁栋; 周乃军
2014-01-01
A animation-game system based on embedded system was proposed in this paper.The system consists of hardware and software.The hardware was cored as the ARM microprocessor of STM32103,and Amazon-LF was used to execute processing of multimedia,the two processors cooperated with peripheral circuits formed the hardware conifguration. The software system consists of drive of hardware,real-time operating system uC/OS-II and applied program in which multilayer mechanism were used in image display.The multilayer mechanism can decrease the processing load and improve the stability of the animation-game system.A system of animation-game was completed successful y in this study through optimization of hardware and software design.%提出了一种基于嵌入式系统的动漫游戏系统设计方案，系统包括硬件电路设计和软件设计。硬件电路以ARM微控制器STM32F103作为主控制器，并采用Amazon-LF芯片进行多媒体处理，以上两种处理器和外设电路一起组成了系统的硬件架构。软件系统则由硬件驱动程序、uC/OS-II实时操作系统、游戏系统应用程序等部分组成。在应用程序设计中，图像显示部分采用了多图层机制显示方法，从而减少了Amazon-LF芯片处理负荷并提高了整个游戏软件系统的稳定性。最终通过对软件和硬件的优化设计，成功实现了动漫游戏系统的设计。
CERN. Geneva; PUNZI, Giovanni
2015-01-01
Charge particle reconstruction is one of the most demanding computational tasks found in HEP, and it becomes increasingly important to perform it in real time. We envision that HEP would greatly benefit from achieving a long-term goal of making track reconstruction happen transparently as part of the detector readout ("detector-embedded tracking"). We describe here a track-reconstruction approach based on a massively parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain as it happens in nature ('RETINA algorithm'). It turns out that high-quality tracking in large HEP detectors is possible with very small latencies, when this algorithm is implemented in specialized processors, based on current state-of-the-art, high-speed/high-bandwidth digital devices.
基于STM32处理器的数字PDA系统设计%Design of digital PDA system based on STM32 processor
胡锦霖; 曾上游; 王亮; 戴伟
2012-01-01
The digital PDA system contains hardware circuit and software system. The hardware circuit is composed of the peripheral circuits of PDA controlled by the low power ARM microcontroller STM32ZET6. The software system is composed of hardware drive program, real-time operating system , file system FATFS and GUI. The digital PDA system integrates the software system, and provides a method based on the page, which is a thread, and utilize the semaphore and mailbox mechanism to switch tasks between multiple threads. The design of the page mechanism is adopted in the PDA system to reduce the amount of the code modification when the PDA system adds application program, and improve the stability of PDA software system and the development speed of application program.%数字PDA系统整体由硬件电路和软件系统2部分组成,硬件电路由低功耗ARM微控制器STM32ZET6控制的PDA外围电路组成,软件系统则由硬件驱动程序、μC/OS-Ⅱ实时操作系统、FATFS文件系统、GUI等部分组成.数字PDA系统将整个软件系统进行了整合,提供一种基于页的机制方法,即每页都是一个线程,利用μC/OS-Ⅱ的信号量、邮箱机制实现多线程之间的任务切换.PDA系统采用页机制的设计,旨在减少增加应用程序时代码的修改量和提高整个PDA软件系统的稳定性,以及提高应用程序的开发速度.
Design of Digital Thermocouple Sensors Based on Single Chip Processors%基于单片机的数字式热电偶传感器设计
于剑超; 董恩生; 李清亮
2014-01-01
A conventional thermocouple has some disadvantages: its output signal is weak, making it difficult for a long distance signal transmission;it needs temperature compensation at cold junctions, making the application inconvenient;and its output signal is an analog signal, making it complex for doing a digital measurement. As to these problems, this paper introduced a measuring circuit based on a computer, which can directly measure the output signals of thermocouples and automatically make the cold-junction temperature compensation. The measuring re-sults from the circuit are turned into RS232 serial signals to output. The thermocouple equipped with the circuit will be able to output digital sig-nals corresponding to the measured temperature. So the design is of high practical value.%针对热电偶传感器存在的输出热电势信号小、不便于远距离传输，需要进行冷端温度补偿、不便于使用，输出的是模拟信号、不便于实现数字式测量等问题，提出一种基于单片机的测量电路，该电路可对热电偶输出的信号进行测量，并能够自动进行冷端温度补偿，测量结果转换为RS232串行信号向外输出。热电偶传感器配备上该测量电路，便可实现所测温度的数字输出，具有较高的实用性。
Byung-eun LEE; Thanh-binh NGUYEN; Sun-tae CHUNG
2010-01-01
Foreground moving object detection is an important pocess in various computer vision applicatipons such as intelligent visual sur-veillance,HCI,object-based video compression,etc.One of the most successful moving object detection algorithms is based on Adaptive Gaussian Mixture Model (AGMM).Although AGMM-based object detection shows very good performance with respect to object detection accuracy,AGMM is very complex model requiring lots of floating-point arithmetic so that it should pay for expensive computational cost.Thus,direa implementation of the AGMM-based object detec-tion for embedded DSPs without floating-point arithmetic HW support cannot satisfy the real-time processing requirement.This paper pre-sents a navel real-time implementation of adaptive Gaussian mixture model-based moving object detection algorithm for fixed-point DSPs.In the proposed implementation,in addition to changes of data types into fixed- point ones,magnification of the Gaussian distribution tech nique is introduced so that the integer and fixed-point arithmetic can be easily and consistently utilized instead of real number and floating-point arithmetic in processing of AGMM algorithm.Experimental re-sults shows that the proposed implementation have a high potential in real-time applications.
APRON: A Cellular Processor Array Simulation and Hardware Design Tool
David R. W. Barr
2009-01-01
Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.
Time-Stretch Accelerated Processor for Real-time, In-service, Signal Analysis
Lonappan, Cejo K.; Buckley, Brandon W.; Adam, Jost
2014-01-01
We demonstrate real-time, in-service, digital signal analysis of 10 Gbit/s data using a 1.2 Tbit/s burst-mode digital processor. The processor comprises a time-stretch front-end and a custom data acquisition and real-time signal processing back- end. Experimental demonstration of real-time, in...
Seltzer, S. M.
1976-01-01
The problem discussed is to design a digital controller for a typical satellite. The controlled plant is considered to be a rigid body acting in a plane. The controller is assumed to be a digital computer which, when combined with the proposed control algorithm, can be represented as a sampled-data system. The objective is to present a design strategy and technique for selecting numerical values for the control gains (assuming position, integral, and derivative feedback) and the sample rate. The technique is based on the parameter plane method and requires that the system be amenable to z-transform analysis.
基于任务图的多处理器负载均衡调度算法%Multi-processor Load Balance Scheduling Algorithm Based on Task Graph
芦奉良; 刘羽; 张军
2011-01-01
针对共享存储多处理机系统中各处理机负载不均衡的问题,提出一种新的任务调度算法--多重波前法.在任务图划分的基础上,采用分层调度方式对原波前法进行改进,通过对任务序列进行多重遍历和重组以降低各处理器的分配误差,利用循环调度算法提高任务调度结果的精度,并给出该算法的并行实现.实验结果证明,该算法具有较低的任务分配误差和较高的系统并行效率.%Aiming at the processors load imbalance problem in shared memory multiprocessor system, this paper provides a new task scheduling algorithm——Multiple Wave Front Method(MWFM).MWFM improves the original Wave Front Method(WFM) by the way of hierarchical scheduling based on dividing the task graphs.It traverses and reallocates task sequences to reduce the error, improves the accuracy of the results of task scheduling by cyclic scheduling algorithm, and gives the implementation of the parallel algorithm.Experimental results prove that the algorithm can significantly reduce errors and improve the efficiency of the parallel systems.
Jiangyi Qin
Full Text Available A novel blind recognition algorithm of frame synchronization words is proposed to recognize the frame synchronization words parameters in digital communication systems. In this paper, a blind recognition method of frame synchronization words based on the hard-decision is deduced in detail. And the standards of parameter recognition are given. Comparing with the blind recognition based on the hard-decision, utilizing the soft-decision can improve the accuracy of blind recognition. Therefore, combining with the characteristics of Quadrature Phase Shift Keying (QPSK signal, an improved blind recognition algorithm based on the soft-decision is proposed. Meanwhile, the improved algorithm can be extended to other signal modulation forms. Then, the complete blind recognition steps of the hard-decision algorithm and the soft-decision algorithm are given in detail. Finally, the simulation results show that both the hard-decision algorithm and the soft-decision algorithm can recognize the parameters of frame synchronization words blindly. What's more, the improved algorithm can enhance the accuracy of blind recognition obviously.
Qin, Jiangyi; Huang, Zhiping; Liu, Chunwu; Su, Shaojing; Zhou, Jing
2015-01-01
A novel blind recognition algorithm of frame synchronization words is proposed to recognize the frame synchronization words parameters in digital communication systems. In this paper, a blind recognition method of frame synchronization words based on the hard-decision is deduced in detail. And the standards of parameter recognition are given. Comparing with the blind recognition based on the hard-decision, utilizing the soft-decision can improve the accuracy of blind recognition. Therefore, combining with the characteristics of Quadrature Phase Shift Keying (QPSK) signal, an improved blind recognition algorithm based on the soft-decision is proposed. Meanwhile, the improved algorithm can be extended to other signal modulation forms. Then, the complete blind recognition steps of the hard-decision algorithm and the soft-decision algorithm are given in detail. Finally, the simulation results show that both the hard-decision algorithm and the soft-decision algorithm can recognize the parameters of frame synchronization words blindly. What's more, the improved algorithm can enhance the accuracy of blind recognition obviously.
Fast 2D-DCT implementations for VLIW processors
Sohm, OP; Canagarajah, CN; Bull, DR
1999-01-01
This paper analyzes various fast 2D-DCT algorithms regarding their suitability for VLIW processors. Operations for truncation or rounding which are usually neglected in proposals for fast algorithms have also been taken into consideration. Loeffler's algorithm with parallel multiplications was found to be most suitable due to its parallel structure
The sloan digital sky Survey-II supernova survey: search algorithm and follow-up observations
Sako, Masao [Department of Physics and Astronomy, University of Pennsylvania, 209 South 33rd Street, Philadelphia, PA 19104 (United States); Bassett, Bruce [Department of Mathematics and Applied Mathematics, University of Cape Town, Rondebosch 7701 (South Africa); Becker, Andrew; Hogan, Craig J. [Department of Astronomy, University of Washington, Box 351580, Seattle, WA 98195 (United States); Cinabro, David [Department of Physics, Wayne State University, Detroit, MI 48202 (United States); DeJongh, Fritz; Frieman, Joshua A.; Marriner, John; Miknaitis, Gajus [Center for Particle Astrophysics, Fermi National Accelerator Laboratory, P.O. Box 500, Batavia, IL 60510 (United States); Depoy, D. L.; Prieto, Jose Luis [Department of Astronomy, Ohio State University, 140 West 18th Avenue, Columbus, OH 43210-1173 (United States); Dilday, Ben; Kessler, Richard [Kavli Institute for Cosmological Physics, The University of Chicago, 5640 South Ellis Avenue Chicago, IL 60637 (United States); Doi, Mamoru [Institute of Astronomy, Graduate School of Science, University of Tokyo 2-21-1, Osawa, Mitaka, Tokyo 181-0015 (Japan); Garnavich, Peter M. [University of Notre Dame, 225 Nieuwland Science, Notre Dame, IN 46556-5670 (United States); Holtzman, Jon [Department of Astronomy, MSC 4500, New Mexico State University, P.O. Box 30001, Las Cruces, NM 88003 (United States); Jha, Saurabh [Kavli Institute for Particle Astrophysics and Cosmology, Stanford University, P.O. Box 20450, MS29, Stanford, CA 94309 (United States); Konishi, Kohki [Institute for Cosmic Ray Research, University of Tokyo, 5-1-5, Kashiwanoha, Kashiwa, Chiba, 277-8582 (Japan); Lampeitl, Hubert [Space Telescope Science Institute, 3700 San Martin Drive, Baltimore, MD 21218 (United States); Nichol, Robert C. [Institute of Cosmology and Gravitation, Mercantile House, Hampshire Terrace, University of Portsmouth, Portsmouth PO1 2EG (United Kingdom); and others
2008-01-01
The Sloan Digital Sky Survey-II Supernova Survey has identified a large number of new transient sources in a 300 deg{sup 2} region along the celestial equator during its first two seasons of a three-season campaign. Multi-band (ugriz) light curves were measured for most of the sources, which include solar system objects, galactic variable stars, active galactic nuclei, supernovae (SNe), and other astronomical transients. The imaging survey is augmented by an extensive spectroscopic follow-up program to identify SNe, measure their redshifts, and study the physical conditions of the explosions and their environment through spectroscopic diagnostics. During the survey, light curves are rapidly evaluated to provide an initial photometric type of the SNe, and a selected sample of sources are targeted for spectroscopic observations. In the first two seasons, 476 sources were selected for spectroscopic observations, of which 403 were identified as SNe. For the type Ia SNe, the main driver for the survey, our photometric typing and targeting efficiency is 90%. Only 6% of the photometric SN Ia candidates were spectroscopically classified as non-SN Ia instead, and the remaining 4% resulted in low signal-to-noise, unclassified spectra. This paper describes the search algorithm and the software, and the real-time processing of the SDSS imaging data. We also present the details of the supernova candidate selection procedures and strategies for follow-up spectroscopic and imaging observations of the discovered sources.
First Results of an "Artificial Retina" Processor Prototype
Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John
2016-11-01
We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called "artificial retina algorithm", inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate.
The C4 clustering algorithm: Clusters of galaxies in the Sloan Digital Sky Survey
Miller, Christopher J.; Nichol, Robert; Reichart, Dan; Wechsler, Risa H.; Evrard, August; Annis, James; McKay, Timothy; Bahcall, Neta; Bernardi, Mariangela; Boehringer,; Connolly, Andrew; Goto, Tomo; Kniazev, Alexie; Lamb, Donald; Postman, Marc; Schneider, Donald; Sheth, Ravi; Voges, Wolfgang; /Cerro-Tololo InterAmerican Obs. /Portsmouth U.,
2005-03-01
We present the ''C4 Cluster Catalog'', a new sample of 748 clusters of galaxies identified in the spectroscopic sample of the Second Data Release (DR2) of the Sloan Digital Sky Survey (SDSS). The C4 cluster-finding algorithm identifies clusters as overdensities in a seven-dimensional position and color space, thus minimizing projection effects that have plagued previous optical cluster selection. The present C4 catalog covers {approx}2600 square degrees of sky and ranges in redshift from z = 0.02 to z = 0.17. The mean cluster membership is 36 galaxies (with redshifts) brighter than r = 17.7, but the catalog includes a range of systems, from groups containing 10 members to massive clusters with over 200 cluster members with redshifts. The catalog provides a large number of measured cluster properties including sky location, mean redshift, galaxy membership, summed r-band optical luminosity (L{sub r}), velocity dispersion, as well as quantitative measures of substructure and the surrounding large-scale environment. We use new, multi-color mock SDSS galaxy catalogs, empirically constructed from the {Lambda}CDM Hubble Volume (HV) Sky Survey output, to investigate the sensitivity of the C4 catalog to the various algorithm parameters (detection threshold, choice of passbands and search aperture), as well as to quantify the purity and completeness of the C4 cluster catalog. These mock catalogs indicate that the C4 catalog is {approx_equal}90% complete and 95% pure above M{sub 200} = 1 x 10{sup 14} h{sup -1}M{sub {circle_dot}} and within 0.03 {le} z {le} 0.12. Using the SDSS DR2 data, we show that the C4 algorithm finds 98% of X-ray identified clusters and 90% of Abell clusters within 0.03 {le} z {le} 0.12. Using the mock galaxy catalogs and the full HV dark matter simulations, we show that the L{sub r} of a cluster is a more robust estimator of the halo mass (M{sub 200}) than the galaxy line-of-sight velocity dispersion or the richness of the cluster
Zeloufi, Mohamed; The ATLAS collaboration; Rarbi, Fatah-ellah
2015-01-01
This paper presents a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy allows also a digital background calibration, based on a code density analysis, to compensate the capacitors mismatching effects. The total of capacitors used in this architecture is limited to a half of the one in a classical SAR design. Only 211 unit capacitors were necessary to reach 12bit resolution, and the switching algorithm is intrinsically monotonic. The design is fully differential featuring 12-bit 40MS/s in a CMOS 130nm 1P8M process.
Zeloufi, Mohamed; The ATLAS collaboration; Rarbi, Fatah-ellah
2015-01-01
We present a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy allows also a digital background calibration, based on a code density analysis, to compensate the capacitors mismatching effects. The total of capacitors used in this architecture is limited to a half of the one in a classical SAR design. Only 2^11 unit capacitors were necessary to reach 12bits resolution, and the switching algorithm is intrinsically monotonic. The design is fully differential featuring 12-bit 40MS/s in a CMOS 130nm 1P8M process.
Jian Zhao,Na Zhang,Jian Jia,; Huanwei Wang
2015-01-01
Contraposing the need of the robust digital watermark for the copyright protection field, a new digital watermarking algo-rithm in the non-subsampled contourlet transform (NSCT) domain is proposed. The largest energy sub-band after NSCT is selected to embed watermark. The watermark is embedded into scale-invariant feature transform (SIFT) regions. During embedding, the initial region is divided into some cirque sub-regions with the same area, and each watermark bit is embedded into one sub-region. Extensive simulation results and comparisons show that the algo-rithm gets a good trade-off of invisibility, robustness and capacity, thus obtaining good quality of the image while being able to effec-tively resist common image processing, and geometric and combo attacks, and normalized similarity is almost al reached.
Pierce, Paul E.
1986-01-01
A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.
Signal processor packaging design
McCarley, Paul L.; Phipps, Mickie A.
1993-10-01
The Signal Processor Packaging Design (SPPD) program was a technology development effort to demonstrate that a miniaturized, high throughput programmable processor could be fabricated to meet the stringent environment imposed by high speed kinetic energy guided interceptor and missile applications. This successful program culminated with the delivery of two very small processors, each about the size of a large pin grid array package. Rockwell International's Tactical Systems Division in Anaheim, California developed one of the processors, and the other was developed by Texas Instruments' (TI) Defense Systems and Electronics Group (DSEG) of Dallas, Texas. The SPPD program was sponsored by the Guided Interceptor Technology Branch of the Air Force Wright Laboratory's Armament Directorate (WL/MNSI) at Eglin AFB, Florida and funded by SDIO's Interceptor Technology Directorate (SDIO/TNC). These prototype processors were subjected to rigorous tests of their image processing capabilities, and both successfully demonstrated the ability to process 128 X 128 infrared images at a frame rate of over 100 Hz.
Maiti, Abhik; Chakravarty, Debashish
2016-01-01
3D reconstruction of geo-objects from their digital images is a time-efficient and convenient way of studying the structural features of the object being modelled. This paper presents a 3D reconstruction methodology which can be used to generate photo-realistic 3D watertight surface of different irregular shaped objects, from digital image sequences of the objects. The 3D reconstruction approach described here is robust, simplistic and can be readily used in reconstructing watertight 3D surface of any object from its digital image sequence. Here, digital images of different objects are used to build sparse, followed by dense 3D point clouds of the objects. These image-obtained point clouds are then used for generation of photo-realistic 3D surfaces, using different surface reconstruction algorithms such as Poisson reconstruction and Ball-pivoting algorithm. Different control parameters of these algorithms are identified, which affect the quality and computation time of the reconstructed 3D surface. The effects of these control parameters in generation of 3D surface from point clouds of different density are studied. It is shown that the reconstructed surface quality of Poisson reconstruction depends on Samples per node (SN) significantly, greater SN values resulting in better quality surfaces. Also, the quality of the 3D surface generated using Ball-Pivoting algorithm is found to be highly depend upon Clustering radius and Angle threshold values. The results obtained from this study give the readers of the article a valuable insight into the effects of different control parameters on determining the reconstructed surface quality.
Real time continuous wavelet transform implementation on a DSP processor.
Patil, S; Abel, E W
2009-01-01
The continuous wavelet transform (CWT) is an effective tool when the emphasis is on the analysis of non-stationary signals and on localization and characterization of singularities in signals. We have used the B-spline based CWT, the Lipschitz Exponent (LE) and measures derived from it to detect and quantify the singularity characteristics of biomedical signals. In this article, a real-time implementation of a B-spline based CWT on a digital signal processor is presented, with the aim of providing quantitative information about the signal to a clinician as it is being recorded. A recursive algorithm implementation was shown to be too slow for real-time implementation so a parallel algorithm was considered. The use of a parallel algorithm involves redundancy in calculations at the boundary points. An optimization of numerical computation to remove redundancy in calculation was carried out. A formula has been derived to give an exact operation count for any integer scale m and any B-spline of order n (for the case where n is odd) to calculate the CWT for both the original and the optimized parallel methods. Experimental results show that the optimized method is 20-28% faster than the original method. As an example of applying this optimized method, a real-time implementation of the CWT with LE postprocessing has been achieved for an EMG Interference Pattern signal sampled at 50 kHz.
Finnemann, Niels Ole
2014-01-01
Processes of digitization have for years represented a major trend in the developments of modern society but have only recently been related to processes of mediatization. The purpose of this article is to look into the relation between the concepts of mediatization and digitization and to clarify...... what a concept of digital media might add to the understanding of processes of mediatization and what the concept of mediatization might add to the understanding of digital media. It is argued that digital media open an array of new trajectories in human communication, trajectories which were...... not anticipated in previous conceptualizations of media and mediatization. If digital media are to be included, the concept of mediatization has to be revised and new parameters are to be built into the concept of media. At the same time it is argued that the concept of mediatization still provides a variety...
Digital Signal Controller Based Digital Control of Brushless DC Motor
Anjana Elizabeth Thomas
2013-07-01
Full Text Available This paper presents the digital control of a brushless dc (BLDC motor using TMS320F2812 DSP controller and an EPROM. The real-time control of electrical motors is an application area that is not usually the domain of Digital Signal Processors. The TMS320F2812 has got dedicated modules for digital motor control. Control algorithms used for the control has been in TMS320F2812 DSP controller. The output of the driver is 6 independent PWM pulses that have to be given to the corresponding gates of the six MOSFETs power switches used in the three-phase bridge driving circuit whose output is given to the stator of the Brushless DC Motor. The commutation technique used in this work is the trapezoidal commutation owing to its excellent speed and current control and it has been implemented using an EPROM
Connor, Joseph P; Cunningham, Ashley M; Raife, Thomas; Rose, William N; Medow, Joshua E
2017-06-01
Prospective clinical trials support restrictive thresholds for red blood cell (RBC) transfusion. Nonsurvivable donors are a major source of organs for transplantation. The Digital Intern (DI) is a computer algorithm to standardize donor care that includes a more restrictive transfusion threshold. The impact of standardized and restrictive RBC transfusion in organ donors, as determined by the DI, has not been reported. We conducted a retrospective cohort study to compare the transfusion practice of the DI (n = 100) to a historic group of physician-managed donors (n = 90). Transfusion rates, the number of units transfused, and pretransfusion laboratory values were compared between groups. The variability of these parameters was also compared between groups. Finally, the number of transplanted organs per donor in each group was compared. The mean time as a donor was 25.9 ± 15.2 hours and was not different between the groups. In the DI group 19% were transfused compared to 26% in the control group (p = 0.3). The number of units transfused was less in the DI group (1 unit vs. 2 units per transfusion, p = 0.03) and the pretransfusion hematocrit was lower in the DI group (23% vs. 27%, p = 0.01). The variability in the latter two parameters was significantly lower in the DI group. The number of transplanted organs per donor was similar in both groups (3.24 [DI] vs. 3.03 [control], p = 0.37). The DI provides a more standardization transfusion practice in organ donors and reduces blood use without compromising transplantable organs. © 2017 AABB.
Schuldhaus, D; Spiegel, M; Polyanskaya, M; Hornegger, J [Pattern Recognition Lab, University Erlangen-Nuremberg (Germany); Redel, T [Siemens AG Healthcare Sector, Forchheim (Germany); Struffert, T; Doerfler, A, E-mail: martin.spiegel@informatik.uni-erlangen.de [Department of Neuroradiology, University Erlangen-Nuremberg (Germany)
2011-03-21
X-ray-based 2D digital subtraction angiography (DSA) plays a major role in the diagnosis, treatment planning and assessment of cerebrovascular disease, i.e. aneurysms, arteriovenous malformations and intracranial stenosis. DSA information is increasingly used for secondary image post-processing such as vessel segmentation, registration and comparison to hemodynamic calculation using computational fluid dynamics. Depending on the amount of injected contrast agent and the duration of injection, these DSA series may not exhibit one single DSA image showing the entire vessel tree. The interesting information for these algorithms, however, is usually depicted within a few images. If these images would be combined into one image the complexity of segmentation or registration methods using DSA series would drastically decrease. In this paper, we propose a novel method automatically splitting a DSA series into three parts, i.e. mask, arterial and parenchymal phase, to provide one final image showing all important vessels with less noise and moving artifacts. This final image covers all arterial phase images, either by image summation or by taking the minimum intensities. The phase classification is done by a two-step approach. The mask/arterial phase border is determined by a Perceptron-based method trained from a set of DSA series. The arterial/parenchymal phase border is specified by a threshold-based method. The evaluation of the proposed method is two-sided: (1) comparison between automatic and medical expert-based phase selection and (2) the quality of the final image is measured by gradient magnitudes inside the vessels and signal-to-noise (SNR) outside. Experimental results show a match between expert and automatic phase separation of 93%/50% and an average SNR increase of up to 182% compared to summing up the entire series.
Schuldhaus, D.; Spiegel, M.; Redel, T.; Polyanskaya, M.; Struffert, T.; Hornegger, J.; Doerfler, A.
2011-03-01
X-ray-based 2D digital subtraction angiography (DSA) plays a major role in the diagnosis, treatment planning and assessment of cerebrovascular disease, i.e. aneurysms, arteriovenous malformations and intracranial stenosis. DSA information is increasingly used for secondary image post-processing such as vessel segmentation, registration and comparison to hemodynamic calculation using computational fluid dynamics. Depending on the amount of injected contrast agent and the duration of injection, these DSA series may not exhibit one single DSA image showing the entire vessel tree. The interesting information for these algorithms, however, is usually depicted within a few images. If these images would be combined into one image the complexity of segmentation or registration methods using DSA series would drastically decrease. In this paper, we propose a novel method automatically splitting a DSA series into three parts, i.e. mask, arterial and parenchymal phase, to provide one final image showing all important vessels with less noise and moving artifacts. This final image covers all arterial phase images, either by image summation or by taking the minimum intensities. The phase classification is done by a two-step approach. The mask/arterial phase border is determined by a Perceptron-based method trained from a set of DSA series. The arterial/parenchymal phase border is specified by a threshold-based method. The evaluation of the proposed method is two-sided: (1) comparison between automatic and medical expert-based phase selection and (2) the quality of the final image is measured by gradient magnitudes inside the vessels and signal-to-noise (SNR) outside. Experimental results show a match between expert and automatic phase separation of 93%/50% and an average SNR increase of up to 182% compared to summing up the entire series.
Schuldhaus, D; Spiegel, M; Redel, T; Polyanskaya, M; Struffert, T; Hornegger, J; Doerfler, A
2011-03-21
X-ray-based 2D digital subtraction angiography (DSA) plays a major role in the diagnosis, treatment planning and assessment of cerebrovascular disease, i.e. aneurysms, arteriovenous malformations and intracranial stenosis. DSA information is increasingly used for secondary image post-processing such as vessel segmentation, registration and comparison to hemodynamic calculation using computational fluid dynamics. Depending on the amount of injected contrast agent and the duration of injection, these DSA series may not exhibit one single DSA image showing the entire vessel tree. The interesting information for these algorithms, however, is usually depicted within a few images. If these images would be combined into one image the complexity of segmentation or registration methods using DSA series would drastically decrease. In this paper, we propose a novel method automatically splitting a DSA series into three parts, i.e. mask, arterial and parenchymal phase, to provide one final image showing all important vessels with less noise and moving artifacts. This final image covers all arterial phase images, either by image summation or by taking the minimum intensities. The phase classification is done by a two-step approach. The mask/arterial phase border is determined by a Perceptron-based method trained from a set of DSA series. The arterial/parenchymal phase border is specified by a threshold-based method. The evaluation of the proposed method is two-sided: (1) comparison between automatic and medical expert-based phase selection and (2) the quality of the final image is measured by gradient magnitudes inside the vessels and signal-to-noise (SNR) outside. Experimental results show a match between expert and automatic phase separation of 93%/50% and an average SNR increase of up to 182% compared to summing up the entire series.
A task-based comparison of two reconstruction algorithms for digital breast tomosynthesis
Mahadevan, Ravi; Ikejimba, Lynda C.; Lin, Yuan; Samei, Ehsan; Lo, Joseph Y.
2014-03-01
Digital breast tomosynthesis (DBT) generates 3-D reconstructions of the breast by taking X-Ray projections at various angles around the breast. DBT improves cancer detection as it minimizes tissue overlap that is present in traditional 2-D mammography. In this work, two methods of reconstruction, filtered backprojection (FBP) and the Newton-Raphson iterative reconstruction were used to create 3-D reconstructions from phantom images acquired on a breast tomosynthesis system. The task based image analysis method was used to compare the performance of each reconstruction technique. The task simulated a 10mm lesion within the breast containing iodine concentrations between 0.0mg/ml and 8.6mg/ml. The TTF was calculated using the reconstruction of an edge phantom, and the NPS was measured with a structured breast phantom (CIRS 020) over different exposure levels. The detectability index d' was calculated to assess image quality of the reconstructed phantom images. Image quality was assessed for both conventional, single energy and dual energy subtracted reconstructions. Dose allocation between the high and low energy scans was also examined. Over the full range of dose allocations, the iterative reconstruction yielded a higher detectability index than the FBP for single energy reconstructions. For dual energy subtraction, detectability index was maximized when most of the dose was allocated to the high energy image. With that dose allocation, the performance trend for reconstruction algorithms reversed; FBP performed better than the corresponding iterative reconstruction. However, FBP performance varied very erratically with changing dose allocation. Therefore, iterative reconstruction is preferred for both imaging modalities despite underperforming dual energy FBP, as it provides stable results.
The Milstar Advanced Processor
Tjia, Khiem-Hian; Heely, Stephen D.; Morphet, John P.; Wirick, Kevin S.
The Milstar Advanced Processor (MAP) is a 'drop-in' replacement for its predecessor which preserves existing interfaces with other Milstar satellite processors and minimizes the impact of such upgrading to already-developed application software. In addition to flight software development, and hardware development that involves the application of VHSIC technology to the electrical design, the MAP project is developing two sophisticated and similar test environments. High density RAM and ROM are employed by the MAP memory array. Attention is given to the fine-pitch VHSIC design techniques and lead designs used, as well as the tole of TQM and concurrent engineering in the development of the MAP manufacturing process.
数字信号处理器分布式寄存器的写回设计%Write-Back Strategy for Distributed Register in Digital Signal Processor
2013-01-01
We present a design of write back strategy for distributed register file in VLIW digital signal processor to solve the synchronization problem of branch pipeline and write back signals . The design includes generating execution cycles ,write back signal register and write back control unit .We assess the area and power of the design . The proposed strategy can fully implement the advantage of distributed register file , will save 50% in power compared with central register file ,and will save 70% in area compared with traditional write back control method .% 针对分布式寄存器文件应用于高性能超长指令字（VLIW）数字信号处理器而造成的分支流水线与写回控制信号的同步问题，提出了一种面向分布式本地寄存器文件的写回策略。其中包括指令执行周期的产生，写回信号缓存以及写回控制单元。采用了面积功耗性能评估方法，结果证明了该策略能充分发挥分布式寄存器文件在功耗方面的优势，相对于运用集中式寄存器文件可以减少50％的功耗，同时对于传统流水线写回控制方法可以节省60％的面积开销。
Pelgrom, Marcel J M
2010-01-01
The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for...
Peterson, A.; Narasimha, M.; Narayan, S.
1980-01-01
The system design of a wideband (8 MHz) million-channel digital spectrum analyzer for use with a SETI receiver is presented. The analyzer makes use of a digital bandpass filter bank for transforming the wideband input signal into a specified number (120) of uniform narrowband output channels by the use of a Fourier transform digital processor combined with a prototype digital weighting network (finite impulse response filter). The output is then processed separately by 120 microprocessor-based discrete Fourier transform computers, each producing 8190 output channels of approximately 8 Hz bandwidth by the use of an 8190-point prime factor algorithm.
Architectures/Algorithms/Tools for Ultra-Low Power, Compact EVA Digital Radio Project
National Aeronautics and Space Administration — The EVA digital radio imposes tight constraints on power consumption, latency, throughput, form factor, reconfigurability, single event upset and fault tolerance,...
Algorithms for Digital Micro-Wave Receivers and Optimal System Identification.
1994-02-28
estimation, Frequency estimation, Digital receiver design, Improved AR and ARMA modeling, Electronic Warfare (EW) signal detection, Optimal system identification from input/output and frequency domain data.
Optimization of image processing algorithms on mobile platforms
Poudel, Pramod; Shirvaikar, Mukul
2011-03-01
This work presents a technique to optimize popular image processing algorithms on mobile platforms such as cell phones, net-books and personal digital assistants (PDAs). The increasing demand for video applications like context-aware computing on mobile embedded systems requires the use of computationally intensive image processing algorithms. The system engineer has a mandate to optimize them so as to meet real-time deadlines. A methodology to take advantage of the asymmetric dual-core processor, which includes an ARM and a DSP core supported by shared memory, is presented with implementation details. The target platform chosen is the popular OMAP 3530 processor for embedded media systems. It has an asymmetric dual-core architecture with an ARM Cortex-A8 and a TMS320C64x Digital Signal Processor (DSP). The development platform was the BeagleBoard with 256 MB of NAND RAM and 256 MB SDRAM memory. The basic image correlation algorithm is chosen for benchmarking as it finds widespread application for various template matching tasks such as face-recognition. The basic algorithm prototypes conform to OpenCV, a popular computer vision library. OpenCV algorithms can be easily ported to the ARM core which runs a popular operating system such as Linux or Windows CE. However, the DSP is architecturally more efficient at handling DFT algorithms. The algorithms are tested on a variety of images and performance results are presented measuring the speedup obtained due to dual-core implementation. A major advantage of this approach is that it allows the ARM processor to perform important real-time tasks, while the DSP addresses performance-hungry algorithms.
The Central Trigger Processor (CTP)
Franchini, Matteo
2016-01-01
The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.
Advanced signal separation and recovery algorithms for digital x-ray spectroscopy
Mahmoud, Imbaby I.; El Tokhy, Mohamed S.
2015-02-01
X-ray spectroscopy is widely used for in-situ applications for samples analysis. Therefore, spectrum drawing and assessment of x-ray spectroscopy with high accuracy is the main scope of this paper. A Silicon Lithium Si(Li) detector that cooled with a nitrogen is used for signal extraction. The resolution of the ADC is 12 bits. Also, the sampling rate of ADC is 5 MHz. Hence, different algorithms are implemented. These algorithms were run on a personal computer with Intel core TM i5-3470 CPU and 3.20 GHz. These algorithms are signal preprocessing, signal separation and recovery algorithms, and spectrum drawing algorithm. Moreover, statistical measurements are used for evaluation of these algorithms. Signal preprocessing based on DC-offset correction and signal de-noising is performed. DC-offset correction was done by using minimum value of radiation signal. However, signal de-noising was implemented using fourth order finite impulse response (FIR) filter, linear phase least-square FIR filter, complex wavelet transforms (CWT) and Kalman filter methods. We noticed that Kalman filter achieves large peak signal to noise ratio (PSNR) and lower error than other methods. However, CWT takes much longer execution time. Moreover, three different algorithms that allow correction of x-ray signal overlapping are presented. These algorithms are 1D non-derivative peak search algorithm, second derivative peak search algorithm and extrema algorithm. Additionally, the effect of signal separation and recovery algorithms on spectrum drawing is measured. Comparison between these algorithms is introduced. The obtained results confirm that second derivative peak search algorithm as well as extrema algorithm have very small error in comparison with 1D non-derivative peak search algorithm. However, the second derivative peak search algorithm takes much longer execution time. Therefore, extrema algorithm introduces better results over other algorithms. It has the advantage of recovering and
A Domain Specific DSP Processor
Tell, Eric
2001-01-01
This thesis describes the design of a domain specific DSP processor. The thesis is divided into two parts. The first part gives some theoretical background, describes the different steps of the design process (both for DSP processors in general and for this project) and motivates the design decisions made for this processor. The second part is a nearly complete design specification. The intended use of the processor is as a platform for hardware acceleration units. Support for this has howe...
Processor register error correction management
Bose, Pradip; Cher, Chen-Yong; Gupta, Meeta S.
2016-12-27
Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.
The Digital Regime of Truth: From the Algorithmic Governmentality to a New Rule of Law
Antoinette Rouvroy
2016-11-01
Full Text Available This text is a transcription of Rouvroy’s presentation on 7th October 2014 at the “Digital Studies” seminar series at the Centre Georges Pompidou. This seminar series, organised by the French philosopher Bernard Stiegler, question the influence of digital technologies on knowledge from an epistemological point of view and from the way they alter academic disciplines.
Modules for Pipelined Mixed Radix FFT Processors
Anatolij Sergiyenko
2016-01-01
Full Text Available A set of soft IP cores for the Winograd r-point fast Fourier transform (FFT is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by r times. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.
Leidi, Tiziano; Scocchi, Giulio; Grossi, Loris; Pusterla, Simone; D'Angelo, Claudio; Thiran, Jean-Philippe; Ortona, Alberto
2012-11-01
In recent decades, finite element (FE) techniques have been extensively used for predicting effective properties of random heterogeneous materials. In the case of very complex microstructures, the choice of numerical methods for the solution of this problem can offer some advantages over classical analytical approaches, and it allows the use of digital images obtained from real material samples (e.g., using computed tomography). On the other hand, having a large number of elements is often necessary for properly describing complex microstructures, ultimately leading to extremely time-consuming computations and high memory requirements. With the final objective of reducing these limitations, we improved an existing freely available FE code for the computation of effective conductivity (electrical and thermal) of microstructure digital models. To allow execution on hardware combining multi-core CPUs and a GPU, we first translated the original algorithm from Fortran to C, and we subdivided it into software components. Then, we enhanced the C version of the algorithm for parallel processing with heterogeneous processors. With the goal of maximizing the obtained performances and limiting resource consumption, we utilized a software architecture based on stream processing, event-driven scheduling, and dynamic load balancing. The parallel processing version of the algorithm has been validated using a simple microstructure consisting of a single sphere located at the centre of a cubic box, yielding consistent results. Finally, the code was used for the calculation of the effective thermal conductivity of a digital model of a real sample (a ceramic foam obtained using X-ray computed tomography). On a computer equipped with dual hexa-core Intel Xeon X5670 processors and an NVIDIA Tesla C2050, the parallel application version features near to linear speed-up progression when using only the CPU cores. It executes more than 20 times faster when additionally using the GPU.
2006-01-01
Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.
Chen, Limin; Liang, Yin; Wan, Guojin
2012-04-01
An regularization approach is introduced into the online identification of inverse model for predistortion. It is based on a modified backpropagation Levenberg-Marquardt algorithm with sliding window. Adaptive predistorter with feedback was identified respectively based on direct learning and indirect learning architectures. Length of the sliding window was discussed. Compared with the Recursive Prediction Error Method (RPEM) algorithm and Nonlinear Filtered Least-Mean-Square (NFxLMS) algorithm, the algorithm is tested by identification of infinite impulse response Wiener predistorter. It is found that the proposed algorithm is much more efficient than either of the other techniques. The values of the parameters are also smaller than those extracted by the ordinary least-squares algorithm since the proposed algorithm constrains the L2-norm of the parameters.
Speed Scaling on Parallel Processors with Migration
Angel, Eric; Kacem, Fadi; Letsios, Dimitrios
2011-01-01
We study the problem of scheduling a set of jobs with release dates, deadlines and processing requirements (or works), on parallel speed-scaled processors so as to minimize the total energy consumption. We consider that both preemption and migration of jobs are allowed. An exact polynomial-time algorithm has been proposed for this problem, which is based on the Ellipsoid algorithm. Here, we formulate the problem as a convex program and we propose a simpler polynomial-time combinatorial algorithm which is based on a reduction to the maximum flow problem. Our algorithm runs in $O(nf(n)logP)$ time, where $n$ is the number of jobs, $P$ is the range of all possible values of processors' speeds divided by the desired accuracy and $f(n)$ is the complexity of computing a maximum flow in a layered graph with O(n) vertices. Independently, Albers et al. \\cite{AAG11} proposed an $O(n^2f(n))$-time algorithm exploiting the same relation with the maximum flow problem. We extend our algorithm to the multiprocessor speed scal...
Kim, Ye-Seul; Park, Hye-Suk; Kim, Hee-Joung [Yonsei University, Wonju (Korea, Republic of); Choi, Young-Wook; Choi, Jae-Gu [Korea Electrotechnology Research Institute, Ansan (Korea, Republic of)
2014-12-15
Digital breast tomosynthesis (DBT) is a technique that was developed to overcome the limitations of conventional digital mammography by reconstructing slices through the breast from projections acquired at different angles. In developing and optimizing DBT, The x-ray scatter reduction technique remains a significant challenge due to projection geometry and radiation dose limitations. The most common approach to scatter reduction is a beam-stop-array (BSA) algorithm; however, this method raises concerns regarding the additional exposure involved in acquiring the scatter distribution. The compressed breast is roughly symmetric, and the scatter profiles from projections acquired at axially opposite angles are similar to mirror images. The purpose of this study was to apply the BSA algorithm with only two scans with a beam stop array, which estimates the scatter distribution with minimum additional exposure. The results of the scatter correction with angular interpolation were comparable to those of the scatter correction with all scatter distributions at each angle. The exposure increase was less than 13%. This study demonstrated the influence of the scatter correction obtained by using the BSA algorithm with minimum exposure, which indicates its potential for practical applications.
带限数字信号多分辨率逼近的计算%THE MULTIRESOLUTION REPRESENTATION ALGORITHM OF THE DIGITAL SIGNAL
谢宏; 牛东晓; 陈志业
2001-01-01
In the wavelet analysis of a signal,if we represent a digital signal in some resolution sampling space,we can use Mallet's algorithm to decompose the digital signal into wavelet components of varingresolution and a vague lowpass spectrum component.In this paper,we discuss a general algorithm of the digital signal representation in some resolution sampling space based on Shannon's sampling theorem,and give the method of how to control the approximating error by choosing the sampling rate.At the end of the paper we offer two computing examples.
Matrix preconditioning: a robust operation for optical linear algebra processors.
Ghosh, A; Paparao, P
1987-07-15
Analog electrooptical processors are best suited for applications demanding high computational throughput with tolerance for inaccuracies. Matrix preconditioning is one such application. Matrix preconditioning is a preprocessing step for reducing the condition number of a matrix and is used extensively with gradient algorithms for increasing the rate of convergence and improving the accuracy of the solution. In this paper, we describe a simple parallel algorithm for matrix preconditioning, which can be implemented efficiently on a pipelined optical linear algebra processor. From the results of our numerical experiments we show that the efficacy of the preconditioning algorithm is affected very little by the errors of the optical system.
Software-Reconfigurable Processors for Spacecraft
Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey
2005-01-01
A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).
Research on Digital Conversion Difference Fast Algorithm%关于《数字换位差值速算法》的研讨
高庆胜
2015-01-01
In order to better understand the fast algorithm skills, Digital Conversion Difference Fast Algorithm is further researched.%为了更好地掌握速算的技巧，将《数字换位差值速算法》做进一步研讨。
New Generation Processor Architecture Research
Chen Hongsong(陈红松); Hu Mingzeng; Ji Zhenzhou
2003-01-01
With the rapid development of microelectronics and hardware,the use of ever faster micro-processors and new architecture must be continued to meet tomorrow′s computing needs. New processor microarchitectures are needed to push performance further and to use higher transistor counts effectively.At the same time,aiming at different usages,the processor has been optimized in different aspects,such as high performace,low power consumption,small chip area and high security. SOC (System on chip)and SCMP (Single Chip Multi Processor) constitute the main processor system architecture.
Research on Superscalar Digital Signal Processor
Deng Zhenghong; Zheng Wei; Deng Lei; Hu Zhengguo
2004-01-01
Under the direction of design space theory,in this paper we discuss the design of a superscalar pipelining using the way of multiple issues,and the implement of a superscalar-based RISC DSP architecture,SDSP.Furthermore,in this paper we discuss the validity of instruction prefetch,the branch prediction,the depth of instruction window and other issues that can affect the performance of superscalar DSP.
A vector DSP for digital media processors
Bersack, Bret; Redford, John; Moniz, Matt; Goldman, Michael
2003-05-01
A new chip using a DSP with a novel vector architecture is described. It uses a Very Dense Instruction Word (rather than a VLIW) and exploits the parallelism and narrow data typical of image processing to gain high performance at low cost and power. It contains eight 32-bit datapaths all working off a single instruction, and can do sixteen 16-bit MACs per cycle or four 32-bit memory accesses per cycle to 128 KB of on-chip memory. It also contains a serial datapath for handling low-performance code and OS functions. The chip includes memory, video and IO interfaces on an industry-standard bus. It also includes camera-specific IO such as videos DACs for NTSC/PAL and analog LCDs, an I2S audio interface, and USB 1.1. It is built in 0.18 um CMOS, runs at 233 MHz, and draws 300 mW. It uses no fixed-function blocks, microcode, or coprocessors, but can capture and compress video at 30 fps at VGA resolution using JPEG, or at CIF resolution using MPEG-4.
MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY
Barhen, Jacob [ORNL; Kerekes, Ryan A [ORNL; ST Charles, Jesse Lee [ORNL; Buckner, Mark A [ORNL
2008-01-01
High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core
Synthesis of optimal digital shapers with arbitrary noise using a genetic algorithm
Regadío, Alberto, E-mail: regadioca@inta.es [Department of Computer Engineering, Space Research Group, Universidad de Alcalá, 28805 Alcalá de Henares (Spain); Electronic Technology Area, Instituto Nacional de Técnica Aeroespacial, 28850 Torrejón de Ardoz (Spain); Sánchez-Prieto, Sebastián, E-mail: sebastian.sanchez@uah.es [Department of Computer Engineering, Space Research Group, Universidad de Alcalá, 28805 Alcalá de Henares (Spain); Tabero, Jesús, E-mail: taberogj@inta.es [Electronic Technology Area, Instituto Nacional de Técnica Aeroespacial, 28850 Torrejón de Ardoz (Spain); González-Castaño, Diego M., E-mail: diego.gonzalez@usc.es [Radiation Physics Laboratory, Universidad de Santiago, 15782 Santiago de Compostela (Spain)
2015-09-21
This paper presents structure, design and implementation of a novel technique for determining the optimal shaping, in time-domain, for spectrometers by means of a Genetic Algorithm (GA) specifically designed for this purpose. The proposed algorithm is able to adjust automatically the coefficients for shaping an input signal. Results of this experiment have been compared to a previous simulated annealing algorithm. Finally, its performance and capabilities were tested using simulation data and a real particle detector, as a scintillator.
Stereoscopic Optical Signal Processor
Graig, Glenn D.
1988-01-01
Optical signal processor produces two-dimensional cross correlation of images from steroscopic video camera in real time. Cross correlation used to identify object, determines distance, or measures movement. Left and right cameras modulate beams from light source for correlation in video detector. Switch in position 1 produces information about range of object viewed by cameras. Position 2 gives information about movement. Position 3 helps to identify object.
Taylor, Michael B.; Lee, Walter; Miller, Jason E.; Wentzlaff, David; Bratt, Ian; Greenwald, Ben; Hoffmann, Henry; Johnson, Paul R.; Kim, Jason S.; Psota, James; Saraf, Arvind; Shnidman, Nathan; Strumpen, Volker; Frank, Matthew I.; Amarasinghe, Saman; Agarwal, Anant
For the last few decades Moore’s Law has continually provided exponential growth in the number of transistors on a single chip. This chapter describes a class of architectures, called tiled multicore architectures, that are designed to exploit massive quantities of on-chip resources in an efficient, scalable manner. Tiled multicore architectures combine each processor core with a switch to create a modular element called a tile. Tiles are replicated on a chip as needed to create multicores with any number of tiles. The Raw processor, a pioneering example of a tiled multicore processor, is examined in detail to explain the philosophy, design, and strengths of such architectures. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance. Central to achieving this goal is Raw’s ability to exploit all forms of parallelism, including ILP, DLP, TLP, and Stream parallelism. Raw approaches this challenge by implementing plenty of on-chip resources - including logic, wires, and pins - in a tiled arrangement, and exposing them through a new ISA, so that the software can take advantage of these resources for parallel applications. Compared to a traditional superscalar processor, Raw performs within a factor of 2x for sequential applications with a very low degree of ILP, about 2x-9x better for higher levels of ILP, and 10x-100x better when highly parallel applications are coded in a stream language or optimized by hand.
Digital elevation model (DEM) data are essential to hydrological applications and have been widely used to calculate a variety of useful topographic characteristics, e.g., slope, flow direction, flow accumulation area, stream channel network, topographic index, and others. Excep...
A novel VLSI processor architecture for supercomputing arrays
Venkateswaran, N.; Pattabiraman, S.; Devanathan, R.; Ahmed, Ashaf; Venkataraman, S.; Ganesh, N.
1993-01-01
Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.
TAN WeiXian; HONG Wen; WANG YanPing; LIN Yun; WU YiRong
2009-01-01
Based on the general geometric model of multi-baseline Synthetic Aperture Radar Tomography (TomoSAR), the three-dimensional (3-D) sampling criteria, the analytic expression of the 3-D Point Spread Function (PSF) and the 3-D resolution are derived in the 3-D wavenumber domain in this paper. Considering the relationship between the observation geometry and the size of illuminated scenario, a 3-D Range Migration Algorithm with Elevation Digital Spotlighting (RMA-EDS) is proposed. With this algorithm 3-D images of the area of interest can be directly and accurately reconstructed in the 3-D space avoiding the complex operations of 3-D geometric correction. Finally, theoretical analyses and simulation results are presented to demonstrate the shift-varying property of the 3-D PSF and the spatialvarying property of the 3-D resolution and to demonstrate the validity of the 3-D RMA-EDS.
宋晓瑞; 王元钦; 郑海昕; 闫冬
2015-01-01
Because azimuth and elevation difference channels are not orthogonal in monopulse angle tracking system, this paper presents a new digital phase calibration method by using two NCOs to compensate the azimuth and elevation phase differences to reduce the error of angle estimation with in-depth study of the angle error extraction principle in I/Q processor.With an analysis of the precision of angle tracking under different calibration methods,the feasibility of the new method can be validated.As a simulation result,the precision of dual-channel monopulse angle tracking system can be improved.%针对双通道单脉冲角跟踪系统中存在的方位、俯仰差通道不正交的问题，在对基于正交处理的角误差提取原理进行深入研究分析的基础上，通过利用数字振荡器生成本振信号的初相进行相位补偿以及将方位、俯仰差通道分置的方法，进而提出了一种基于正交处理的数字校相方法。通过对采用不同校相方法时角误差提取精度的分析，从理论推导和仿真实验两方面验证了新方法的可行性。仿真结果表明该新方法可以减小方位、俯仰差通道不正交这一因素给角误差提取所带来的误差，从而提高双通道单脉冲角跟踪系统的角误差提取精度。
Two Normal Basis Multiplication Algorithms for GF(2n)
FAN Haining; LIU Duo; DAI Yiqi
2006-01-01
For software implementations, word-level normal basis multiplication algorithms utilize the full data-path of the processor, and hence are more efficient than the bit-level multiplication algorithm presented in the IEEE standard P1363-2000. In this paper, two word-level normal basis multiplication algorithms are proposed for GF(2n). The first algorithm is suitable for high complexity normal bases, while the second algorithm is fast for type-Ⅰ optimal normal bases and low complexity normal bases. Theoretical analyses and experimental results both indicate that the presented algorithms are efficient in GF(2233), GF(2283), GF(2409),and GF(2571), which are four of the five binary fields recommended by the National Institute of Standards and Technology (NIST) for the elliptic curve digital signature algorithm (ECDSA) applications.
Soliman, Hammam Abdelaal Hammam; Wang, Huai; Blaabjerg, Frede
2016-01-01
of the aforementioned challenges and shortcomings. In this paper, a pure software condition monitoring method based on Artificial Neural Network (ANN) algorithm is proposed. The implemented ANN estimates the capacitance of the dc-link capacitor in a back-to-back converter. The error analysis of the estimated results...... is also studied. The developed ANN algorithm has been implemented in a Digital Signal Processor (DSP) in order to have a proof of concept of the proposed method....
Forchhammer, Søren; Kim, Chul E
1988-01-01
Digital squares are defined and their geometric properties characterized. A linear time algorithm is presented that considers a convex digital region and determines whether or not it is a digital square. The algorithm also determines the range of the values of the parameter set of its preimages....... The analysis involves transforming the boundary of a digital region into parameter space of slope and y-intercept...
胡秀寒; 周田华; 贺岩; 朱小磊; 陈卫标
2013-01-01
A high speed and high reliable underwater optical communication transceiver system based on digital signal processor (DSP) is proposed, and the modulation timing sequence and signal processing procedure is analyzed. In the transmitter, the DSP accomplishes Reed-Solomon codes encoding of the information need to be sent and filtering, threshold decision, the decoding and demodulation of the received information. The field-programmable gate array (FPGA) accomplishes the modulation of the information encoded in the DSP. Under the condition that the pulse width after underwater propagation is less than 100 ns and the frequency deviation from the mean is less than 15% , the dependence of the pulse position modulation (PPM) modulation rate on the chosen Galois field is discussed and the signal processing speed as well as the interfaces communication speed are analyzed. The analytical results show that the designed transmitter system can accomplish full-duplex and real time communication with a speed as high as 73 kbit/s. which can be used for real-time communication of multi-media information, such as voice and images. The pulse shape of laser after a propagation of 100 m in case Ⅱ water is simulated through Matlab as well as the timing sequence of a frame of data transmitted through FPGA and sampled sequence of a frame of data obtained through analog-to-digital converter (ADC). The structure of the designed transceiver provides a certain reference to the design and accomplishment of underwater optical communication system in the future.%设计了一种基于数字信号处理机(DSP)的高速高可靠性水下光通信收发系统,并分析了调制时序和信号处理过程.在收发机中,DSP完成待发送信息的里德-所罗门码编码和接收信息的滤波、门限判决、解调解码,现场可编程门阵列(FPGA)完成编码后信息的脉冲位置调制(PPM).针对激光脉冲水下传输后脉宽展宽小于100 ns,激光重复频率偏离均值小于15
Pedretti, Kevin
2008-11-18
A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.
A novel algorithm for fractional resizing of digital image in DCT domain
Wang Ci; Zhang Wenjun; Zheng Meng
2005-01-01
Fractional resizing of digital images is needed in various applications, such as displaying at different resolution depending on that of display device, building image index for an image database, and changing resolution according to the transmission channel bandwidth. With the wide use of JPEG and MPEG, almost all digital images are stored and transferred in DCT compressed format. Inorder to save the computation and memory cost, it is desirable to do resizing in DCT domain directly. This paper presents a fast and efficient method, which possesses the capability of fractional resizing in DCT domain. Experimental results confirm that this scheme can achieve significant computation cost reduction while maintain better quality.
Hoare Raymond R
2006-01-01
Full Text Available This paper presents an architecture that combines VLIW (very long instruction word processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1 a 4-way VLIW processor implemented in an FPGA, (2 large speedups through hardware functions, (3 a hardware/software interface with zero overhead, (4 a design methodology for implementing signal processing applications on this architecture, (5 tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to times that of software with an average times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.
MAP3D: a media processor approach for high-end 3D graphics
Darsa, Lucia; Stadnicki, Steven; Basoglu, Chris
1999-12-01
Equator Technologies, Inc. has used a software-first approach to produce several programmable and advanced VLIW processor architectures that have the flexibility to run both traditional systems tasks and an array of media-rich applications. For example, Equator's MAP1000A is the world's fastest single-chip programmable signal and image processor targeted for digital consumer and office automation markets. The Equator MAP3D is a proposal for the architecture of the next generation of the Equator MAP family. The MAP3D is designed to achieve high-end 3D performance and a variety of customizable special effects by combining special graphics features with high performance floating-point and media processor architecture. As a programmable media processor, it offers the advantages of a completely configurable 3D pipeline--allowing developers to experiment with different algorithms and to tailor their pipeline to achieve the highest performance for a particular application. With the support of Equator's advanced C compiler and toolkit, MAP3D programs can be written in a high-level language. This allows the compiler to successfully find and exploit any parallelism in a programmer's code, thus decreasing the time to market of a given applications. The ability to run an operating system makes it possible to run concurrent applications in the MAP3D chip, such as video decoding while executing the 3D pipelines, so that integration of applications is easily achieved--using real-time decoded imagery for texturing 3D objects, for instance. This novel architecture enables an affordable, integrated solution for high performance 3D graphics.
Maximilien Brice
2003-01-01
This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.
数字化核测系统通信数据传输算法应用%Transmission Algorithm of Digital Communicating Data for Digital NDIS
刘瑞; 李艳丽
2014-01-01
Taking the advantages of good stability and high reliability , digital communication are becoming a more critical component of instrument and control ( I&C) systems in nuclear plant power ( NPP) , especially for the next generation .With China's rapid development of NPP I&C of third generation AP 1000 technology , most of Nuclear Detecting Instrument System ( NDIS) are supplied by foreign manufacturer and digital NDIS is una-vailable in China .In the digital control system design customized for field nuclear instrument , all parts need to be taken into account for signal acquisition , processing , threshold comparison and control .Fast and intelligent communication data processing is often of concern and needs research .Transmission algorithm of digital commu-nicating data for NDIS is designed to solve the real -time-control problems in the amount of time and equip-ment limitation which caused by physical characteristics of RS 485 high-speed data bus .The algorithms in-clude data link establishment and link management , data subcontracting computing , and data test .In the case of limited system scan cycle time and multi -exchanged data of digital NDIS , it can guarantee the normal trans-mission of sufficient data for information of all devices .%数字化通信具有稳定性好、可靠性高的优点，越来越广泛应用于仪控系统，特别是新一代核电厂仪控系统。现在我国核电建设事业快速发展，引进了三代AP1000技术，但是大部分核测系统还是由国外厂商供货，尤其是数字化核测系统更是空白。在与现场核测仪表配套定制的数字化仪控系统设计中，需要考虑作为信号采集、处理、阈值比较和控制的各个环节，其中如何快速、智能地处理通信数据也是大家经常关注和研究的重点。数字化通信数据传输算法针对数字化核测系统的快速可靠的循环数据交互任务而设计，目的是解决系统采用的RS485高速数据总线
An algorithm for radiometric and geometric correction of digital SLAR data
Hoogeboom, P.; Binnenkade, P.; Veugen, L.M.M.
1983-01-01
In The Netherlands an accurate SLAR system with digital data recording is used for measurements within the framework of the national microwave remote sensing research program. However, the images are disturbed by unwanted platform motions due to, e.g., turbulence at the low operating height
An algorithm for radiometric and geometric correction of digital SLAR data
Hoogeboom, P.; Binnenkade, P.; Veugen, L.M.M.
1983-01-01
In The Netherlands an accurate SLAR system with digital data recording is used for measurements within the framework of the national microwave remote sensing research program. However, the images are disturbed by unwanted platform motions due to, e.g., turbulence at the low operating height (300–300
On the Adoption of the Elliptic Curve Digital Signature Algorithm (ECDSA) in DNSSEC
van Rijswijk, Roland M.; Jonker, Mattijs; Sperotto, Anna
2016-01-01
The Domain Name System Security Extensions (DNSSEC) are steadily being deployed across the Internet. DNSSEC extends the DNS protocol with two vital security properties, authenticity and integrity, using digital signatures. While DNSSEC is meant to solve security issues in the DNS, it also introduces
On the Adoption of the Elliptic Curve Digital Signature Algorithm (ECDSA) in DNSSEC
Rijswijk-Deij, van Roland; Jonker, Mattijs; Sperotto, Anna
2016-01-01
The Domain Name System Security Extensions (DNSSEC) are steadily being deployed across the Internet. DNSSEC extends the DNS protocol with two vital security properties, authenticity and integrity, using digital signatures. While DNSSEC is meant to solve security issues in the DNS, it also introduces
Low-Light Image Enhancement Using Adaptive Digital Pixel Binning
Yoonjong Yoo
2015-06-01
Full Text Available This paper presents an image enhancement algorithm for low-light scenes in an environment with insufficient illumination. Simple amplification of intensity exhibits various undesired artifacts: noise amplification, intensity saturation, and loss of resolution. In order to enhance low-light images without undesired artifacts, a novel digital binning algorithm is proposed that considers brightness, context, noise level, and anti-saturation of a local region in the image. The proposed algorithm does not require any modification of the image sensor or additional frame-memory; it needs only two line-memories in the image signal processor (ISP. Since the proposed algorithm does not use an iterative computation, it can be easily embedded in an existing digital camera ISP pipeline containing a high-resolution image sensor.
M. Schämann
2008-05-01
Full Text Available High data rates combined with high mobility represent a challenge for the design of cellular devices. Advanced algorithms are required which result in higher complexity, more chip area and increased power consumption. However, this contrasts to the limited power supply of mobile devices.
This presentation discusses the application of an HSDPA receiver which has been optimized regarding power consumption with the focus on the algorithmic and architectural level. On algorithmic level the Rake combiner, Prefilter-Rake equalizer and MMSE equalizer are compared regarding their BER performance. Both equalizer approaches provide a significant increase of performance for high data rates compared to the Rake combiner which is commonly used for lower data rates. For both equalizer approaches several adaptive algorithms are available which differ in complexity and convergence properties. To identify the algorithm which achieves the required performance with the lowest power consumption the algorithms have been investigated using SystemC models regarding their performance and arithmetic complexity. Additionally, for the Prefilter Rake equalizer the power estimations of a modified Griffith (LMS and a Levinson (RLS algorithm have been compared with the tool ORINOCO supplied by ChipVision. The accuracy of this tool has been verified with a scalable architecture of the UMTS channel estimation described both in SystemC and VHDL targeting a 130 nm CMOS standard cell library.
An architecture combining all three approaches combined with an adaptive control unit is presented. The control unit monitors the current condition of the propagation channel and adjusts parameters for the receiver like filter size and oversampling ratio to minimize the power consumption while maintaining the required performance. The optimization strategies result in a reduction of the number of arithmetic operations up to 70% for single components which leads to an
AMD's 64-bit Opteron processor
CERN. Geneva
2003-01-01
This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...
Emerging Trends in Embedded Processors
Gurvinder Singh
2014-05-01
Full Text Available An Embedded Processors is simply a µProcessors that has been “Embedded” into a device. Embedded systems are important part of human life. For illustration, one cannot visualize life without mobile phones for personal communication. Embedded systems are used in many places like healthcare, automotive, daily life, and in different offices and industries.Embedded Processors develop new research area in the field of hardware designing.
Optical linear algebra processors: noise and error-source modeling.
Casasent, D; Ghosh, A
1985-06-01
The modeling of system and component noise and error sources in optical linear algebra processors (OLAP's) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.
Optical linear algebra processors - Noise and error-source modeling
Casasent, D.; Ghosh, A.
1985-01-01
The modeling of system and component noise and error sources in optical linear algebra processors (OLAPs) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.
Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas
2008-01-01
A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.
Choudhari, Khoobaram S; Jidesh, Pacheeripadikkal; Sudheendra, Parampalli; Kulkarni, Suresh D
2013-08-01
A new mathematical algorithm is reported for the accurate and efficient analysis of pore properties of nanoporous anodic alumina (NAA) membranes using scanning electron microscope (SEM) images. NAA membranes of the desired pore size were fabricated using a two-step anodic oxidation process. Surface morphology of the NAA membranes with different pore properties was studied using SEM images along with computerized image processing and analysis. The main objective was to analyze the SEM images of NAA membranes quantitatively, systematically, and quickly. The method uses a regularized shock filter for contrast enhancement, mathematical morphological operators, and a segmentation process for efficient determination of pore properties. The algorithm is executed using MATLAB, which generates a statistical report on the morphology of NAA membrane surfaces and performs accurate quantification of the parameters such as average pore-size distribution, porous area fraction, and average interpore distances. A good comparison between the pore property measurements was obtained using our algorithm and ImageJ software. This algorithm, with little manual intervention, is useful for optimizing the experimental process parameters during the fabrication of such nanostructures. Further, the algorithm is capable of analyzing SEM images of similar or asymmetrically porous nanostructures where sample and background have distinguishable contrast.
Intelligent trigger processor for the crystal box
Sanders, G H; Cooper, M D; Hart, G W; Hoffman, C M; Hogan, G E; Hughes, E B; Matis, H S; Rolfe, J; Sandberg, V D; Williams, R A; Wilson, S; Zeman, H
1981-01-01
A large solid angle angular modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor-changing decays of the muon. A beam of up to 10/sup 6/ muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor. Further reduction to <1 Hz is achieved by a microprocessor-based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic logic. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex ...
DSP algorithms in FPGA: proposition of a new architecture
Kolasinski, Piotr; Zabolotny, Wojciech
2008-01-01
This paper presents a new reconfigurable architecture created in FPGA which is optimized for DSP algorithms like digital filters or digital transforms. The architecture tries to combine advantages of typical architectures like DSP processors and datapath architecture, while avoiding their drawbacks. The architecture is built from blocks called Operational Units (OU). Each Operational Unit contains the Control Unit (CU), which controls its operation. The Operational Units may operate in parallel, which shortens the processing time. This structure is also highly flexible, because all OUs may operate independently, executing their own programs. User may customize connections between units and modify architecture by adding new modules.
Ahmad Audi
2017-07-01
Full Text Available Images acquired with a long exposure time using a camera embedded on UAVs (Unmanned Aerial Vehicles exhibit motion blur due to the erratic movements of the UAV. The aim of the present work is to be able to acquire several images with a short exposure time and use an image processing algorithm to produce a stacked image with an equivalent long exposure time. Our method is based on the feature point image registration technique. The algorithm is implemented on the light-weight IGN (Institut national de l’information géographique camera, which has an IMU (Inertial Measurement Unit sensor and an SoC (System on Chip/FPGA (Field-Programmable Gate Array. To obtain the correct parameters for the resampling of the images, the proposed method accurately estimates the geometrical transformation between the first and the N-th images. Feature points are detected in the first image using the FAST (Features from Accelerated Segment Test detector, then homologous points on other images are obtained by template matching using an initial position benefiting greatly from the presence of the IMU sensor. The SoC/FPGA in the camera is used to speed up some parts of the algorithm in order to achieve real-time performance as our ultimate objective is to exclusively write the resulting image to save bandwidth on the storage device. The paper includes a detailed description of the implemented algorithm, resource usage summary, resulting processing time, resulting images and block diagrams of the described architecture. The resulting stacked image obtained for real surveys does not seem visually impaired. An interesting by-product of this algorithm is the 3D rotation estimated by a photogrammetric method between poses, which can be used to recalibrate in real time the gyrometers of the IMU. Timing results demonstrate that the image resampling part of this algorithm is the most demanding processing task and should also be accelerated in the FPGA in future work.
Audi, Ahmad; Pierrot-Deseilligny, Marc; Meynard, Christophe; Thom, Christian
2017-07-18
Images acquired with a long exposure time using a camera embedded on UAVs (Unmanned Aerial Vehicles) exhibit motion blur due to the erratic movements of the UAV. The aim of the present work is to be able to acquire several images with a short exposure time and use an image processing algorithm to produce a stacked image with an equivalent long exposure time. Our method is based on the feature point image registration technique. The algorithm is implemented on the light-weight IGN (Institut national de l'information géographique) camera, which has an IMU (Inertial Measurement Unit) sensor and an SoC (System on Chip)/FPGA (Field-Programmable Gate Array). To obtain the correct parameters for the resampling of the images, the proposed method accurately estimates the geometrical transformation between the first and the N-th images. Feature points are detected in the first image using the FAST (Features from Accelerated Segment Test) detector, then homologous points on other images are obtained by template matching using an initial position benefiting greatly from the presence of the IMU sensor. The SoC/FPGA in the camera is used to speed up some parts of the algorithm in order to achieve real-time performance as our ultimate objective is to exclusively write the resulting image to save bandwidth on the storage device. The paper includes a detailed description of the implemented algorithm, resource usage summary, resulting processing time, resulting images and block diagrams of the described architecture. The resulting stacked image obtained for real surveys does not seem visually impaired. An interesting by-product of this algorithm is the 3D rotation estimated by a photogrammetric method between poses, which can be used to recalibrate in real time the gyrometers of the IMU. Timing results demonstrate that the image resampling part of this algorithm is the most demanding processing task and should also be accelerated in the FPGA in future work.
A Novel Scrambling Digital Image Watermark Algorithm Based on Double Transform Domains
Taiyue Wang
2015-01-01
Full Text Available Digital watermark technology is a very good method for protecting copyright. In this paper, in terms of requisition of imperceptibility and robustness of watermarking, the multidirectional, multiscale, and band-pass coefficient features of Curvelet transform are introduced and a novel image watermark scheme based on Curvelet and human visual system is proposed. Digital watermark information is embedded into the first 16 directions with larger energy in the fourth layer. Experimental results indicate that the proposed watermark scheme is feasible and simple. Simultaneously, the embedded watermark images just have tiny difference with the original images and the extracted watermark is accurate. Moreover, it is imperceptible and robust against various methods of signals processing such as cropping, noise adding, and rotating and altering.
Digital Demodulation Algorithm for Multi-Tone FM Signal in New Type Track Circuit
ZHU Lin-xiao; WU Si-liang
2006-01-01
The multi-tone frequency modulation (FM) signal transferred through track circuit in automatic train control (ATC) system is analyzed. A digital filter with ideal sloping shape in frequency domain is designed for frequency discrimination. With this filter, the FM signal is converted into AM-FM signal by frequency-to-amplitude conversion. The modulating signal is finally extracted from the envelope of the AM-FM signal. Simulations show that the digital demodulation method could accurately recover the modulating signal in low signal noise ratio (SNR) circumstance, and has good performance in suppressing interference of harmonics of traction current frequency. The feasibility of the proposed method is proved in a hardware system based on SHARC DSP.
Adaptive Motion Estimation Processor for Autonomous Video Devices
T. Dias
2007-05-01
Full Text Available Motion estimation is the most demanding operation of a video encoder, corresponding to at least 80% of the overall computational cost. As a consequence, with the proliferation of autonomous and portable handheld devices that support digital video coding, data-adaptive motion estimation algorithms have been required to dynamically configure the search pattern not only to avoid unnecessary computations and memory accesses but also to save energy. This paper proposes an application-specific instruction set processor (ASIP to implement data-adaptive motion estimation algorithms that is characterized by a specialized datapath and a minimum and optimized instruction set. Due to its low-power nature, this architecture is highly suitable to develop motion estimators for portable, mobile, and battery-supplied devices. Based on the proposed architecture and the considered adaptive algorithms, several motion estimators were synthesized both for a Virtex-II Pro XC2VP30 FPGA from Xilinx, integrated within an ML310 development platform, and using a StdCell library based on a 0.18 ÃŽÂ¼m CMOS process. Experimental results show that the proposed architecture is able to estimate motion vectors in real time for QCIF and CIF video sequences with a very low-power consumption. Moreover, it is also able to adapt the operation to the available energy level in runtime. By adjusting the search pattern and setting up a more convenient operating frequency, it can change the power consumption in the interval between 1.6 mW and 15 mW.
Adaptive Motion Estimation Processor for Autonomous Video Devices
Dias T
2007-01-01
Full Text Available Motion estimation is the most demanding operation of a video encoder, corresponding to at least 80% of the overall computational cost. As a consequence, with the proliferation of autonomous and portable handheld devices that support digital video coding, data-adaptive motion estimation algorithms have been required to dynamically configure the search pattern not only to avoid unnecessary computations and memory accesses but also to save energy. This paper proposes an application-specific instruction set processor (ASIP to implement data-adaptive motion estimation algorithms that is characterized by a specialized datapath and a minimum and optimized instruction set. Due to its low-power nature, this architecture is highly suitable to develop motion estimators for portable, mobile, and battery-supplied devices. Based on the proposed architecture and the considered adaptive algorithms, several motion estimators were synthesized both for a Virtex-II Pro XC2VP30 FPGA from Xilinx, integrated within an ML310 development platform, and using a StdCell library based on a 0.18 μm CMOS process. Experimental results show that the proposed architecture is able to estimate motion vectors in real time for QCIF and CIF video sequences with a very low-power consumption. Moreover, it is also able to adapt the operation to the available energy level in runtime. By adjusting the search pattern and setting up a more convenient operating frequency, it can change the power consumption in the interval between 1.6 mW and 15 mW.
Jin-Young Lee
2015-01-01
Full Text Available This paper presents a study to analyze and modify the Islamic star pattern using digital algorithm, introducing a method to efficiently modify and control classical geometric patterns through experiments and applications of computer algorithms. This will help to overcome the gap between the closeness of classical geometric patterns and the influx of design by digital technology and to lay out a foundation for efficiency and flexibility in developing future designs and material fabrication by promoting better understanding of the various methods for controlling geometric patterns.
Time-Stretch Accelerated Processor for Real-time, In-service, Signal Analysis
Lonappan, Cejo K.; Buckley, Brandon W.; Adam, Jost
2014-01-01
We demonstrate real-time, in-service, digital signal analysis of 10 Gbit/s data using a 1.2 Tbit/s burst-mode digital processor. The processor comprises a time-stretch front-end and a custom data acquisition and real-time signal processing back- end. Experimental demonstration of real-time, in-service......, signal integrity analysis of streaming video packets at 10 Gbit/s is presented....
Performance Case study of Grigoryan FFT over Cooley-Tukey FFT using TMS DSP Processors
Narayanam Ranganadh , Muni Guravaiah P
2012-12-01
Full Text Available Frequency analysis plays vital role in the applications like cryptanalysis, steganalysis [6], system identification, controller tuning, speech recognition, noise filters, etc. Discrete Fourier Transform (DFT is a principal mathematical method for the frequency analysis. The way of splitting the DFT gives out various fast algorithms. In this paper, we present the implementation of two fast algorithms for the DFT for evaluating their performance. One of them is the popular radix-2 Cooley-Tukey fast Fourier transform algorithm (FFT [1] and the other one is the Grigoryan FFT based on the splitting by the paired transform [2]. We evaluate the performance of these algorithms by implementing them on the TMS320C6748 and TMS320C5416 DSPs. We developed C programming for these DSP processors. Finally we show that the paired-transform based algorithm of the FFT is faster than the radix-2 FFT, consequently it is useful for higher sampling rates. Working at higher data rates is a challenge in the applications of Digital Signal Processing.
Devaprakash, Daniel; Weir, Gillian J; Dunne, James J; Alderson, Jacqueline A; Donnelly, Cyril J
2016-12-01
There is a large and growing body of surface electromyography (sEMG) research using laboratory-specific signal processing procedures (i.e., digital filter type and amplitude normalisation protocols) and data analyses methods (i.e., co-contraction algorithms) to acquire practically meaningful information from these data. As a result, the ability to compare sEMG results between studies is, and continues to be challenging. The aim of this study was to determine if digital filter type, amplitude normalisation method, and co-contraction algorithm could influence the practical or clinical interpretation of processed sEMG data. Sixteen elite female athletes were recruited. During data collection, sEMG data was recorded from nine lower limb muscles while completing a series of calibration and clinical movement assessment trials (running and sidestepping). Three analyses were conducted: (1) signal processing with two different digital filter types (Butterworth or critically damped), (2) three amplitude normalisation methods, and (3) three co-contraction ratio algorithms. Results showed the choice of digital filter did not influence the clinical interpretation of sEMG; however, choice of amplitude normalisation method and co-contraction algorithm did influence the clinical interpretation of the running and sidestepping task. Care is recommended when choosing amplitude normalisation method and co-contraction algorithms if researchers/clinicians are interested in comparing sEMG data between studies.
Manuel Rosa-Zurera
2009-01-01
Full Text Available The feasible implementation of signal processing techniques on hearing aids is constrained by the finite precision required to represent numbers and by the limited number of instructions per second to implement the algorithms on the digital signal processor the hearing aid is based on. This adversely limits the design of a neural network-based classifier embedded in the hearing aid. Aiming at helping the processor achieve accurate enough results, and in the effort of reducing the number of instructions per second, this paper focuses on exploring (1 the most appropriate quantization scheme and (2 the most adequate approximations for the activation function. The experimental work proves that the quantized, approximated, neural network-based classifier achieves the same efficiency as that reached by “exact” networks (without these approximations, but, this is the crucial point, with the added advantage of extremely reducing the computational cost on the digital signal processor.
Breadboard Signal Processor for Arraying DSN Antennas
Jongeling, Andre; Sigman, Elliott; Chandra, Kumar; Trinh, Joseph; Soriano, Melissa; Navarro, Robert; Rogstad, Stephen; Goodhart, Charles; Proctor, Robert; Jourdan, Michael;
2008-01-01
A recently developed breadboard version of an advanced signal processor for arraying many antennas in NASA s Deep Space Network (DSN) can accept inputs in a 500-MHz-wide frequency band from six antennas. The next breadboard version is expected to accept inputs from 16 antennas, and a following developed version is expected to be designed according to an architecture that will be scalable to accept inputs from as many as 400 antennas. These and similar signal processors could also be used for combining multiple wide-band signals in non-DSN applications, including very-long-baseline interferometry and telecommunications. This signal processor performs functions of a wide-band FX correlator and a beam-forming signal combiner. [The term "FX" signifies that the digital samples of two given signals are fast Fourier transformed (F), then the fast Fourier transforms of the two signals are multiplied (X) prior to accumulation.] In this processor, the signals from the various antennas are broken up into channels in the frequency domain (see figure). In each frequency channel, the data from each antenna are correlated against the data from each other antenna; this is done for all antenna baselines (that is, for all antenna pairs). The results of the correlations are used to obtain calibration data to align the antenna signals in both phase and delay. Data from the various antenna frequency channels are also combined and calibration corrections are applied. The frequency-domain data thus combined are then synthesized back to the time domain for passing on to a telemetry receiver
Design And Implementation of Low Area/Power Elliptic Curve Digital Signature Hardware Core
Anissa Sghaier
2017-06-01
Full Text Available The Elliptic Curve Digital Signature Algorithm(ECDSA is the analog to the Digital Signature Algorithm(DSA. Based on the elliptic curve, which uses a small key compared to the others public-key algorithms, ECDSA is the most suitable scheme for environments where processor power and storage are limited. This paper focuses on the hardware implementation of the ECDSA over elliptic curveswith the 163-bit key length recommended by the NIST (National Institute of Standards and Technology. It offers two services: signature generation and signature verification. The proposed processor integrates an ECC IP, a Secure Hash Standard 2 IP (SHA-2 Ip and Random Number Generator IP (RNG IP. Thus, all IPs will be optimized, and different types of RNG will be implemented in order to choose the most appropriate one. A co-simulation was done to verify the ECDSA processor using MATLAB Software. All modules were implemented on a Xilinx Virtex 5 ML 50 FPGA platform; they require respectively 9670 slices, 2530 slices and 18,504 slices. FPGA implementations represent generally the first step for obtaining faster ASIC implementations. Further, the proposed design was also implemented on an ASIC CMOS 45-nm technology; it requires a 0.257 mm2 area cell achieving a maximum frequency of 532 MHz and consumes 63.444 (mW. Furthermore, in this paper, we analyze the security of our proposed ECDSA processor against the no correctness check for input points and restart attacks.
Local digital algorithms for estimating the mean integrated curvature of r-regular sets
Svane, Anne Marie
Consider the design based situation where an r-regular set is sampled on a random lattice. A fast algorithm for estimating the integrated mean curvature based on this observation is to use a weighted sum of 2×⋯×2 configuration counts. We show that for a randomly translated lattice, no asymptotica......-or-miss transforms of r-regular sets....
Casson, Alexander J; Rodriguez-Villegas, Esther
2008-01-01
This paper quantifies the performance difference between custom and generic hardware algorithm implementations, illustrating the challenges that are involved in Body Area Network signal processing implementations. The potential use of analogue signal processing to improve the power performance is also demonstrated.
Berends, Constantijn J.; Van De Wal, Roderik S W
2016-01-01
Many processes govern the deglaciation of ice sheets. One of the processes that is usually ignored is the calving of ice in lakes that temporarily surround the ice sheet. In order to capture this process a "flood-fill algorithm" is needed. Here we present and evaluate several optimizations to a stan
Evtushenko Vladimir
2016-01-01
Full Text Available The aim of the study was the development and clinical application of patient selection algorithm for surgical treatment of longlasting persistent atrial fibrillation. The study included 235 patients with acquired heart disease and coronary artery disease, which in the period from 1999 to 2015 performed surgical treatment of long-term persistent atrial fibrillation (RF “MAZE III” procedure in conjunction with the correction of the underlying heart disease. The patients were divided into 2 groups according to the method of operation: the group 1 – 135 patients (76 women and 59 men who have applied an integrated approach to surgery for atrial fibrillation, including penetrating method of RF effects on atrial myocardium and the study of the function of the sinus node before and after the operation (these patients were operated on from 2008 to 2015. The group 2 – 100 patients (62 women and 38 men with a “classical” method of monopolar RF “MAZE III”, which the sinus node function was not studied. We used the combined (epi- and endocardial method of RF «MAZE». This algorithm is decreasing of possible permanent pacemaker postoperatively. The initial sinus node function in these patients, measured using the original method, the basic line of this algorithm was taken. The results showed that use this algorithm for selection of patients allows significantly reduce the possibility of pacemaker implantation in the postoperative period.
Noureddine Aloui
2015-02-01
Full Text Available This paper presents an optimized speech compression algorithm using discrete wavelet transform, and its real time implementation on fixed-point digital signal processor (DSP. The optimized speech compression algorithm presents the advantages to ensure low complexity, low bit rate and achieve high speech coding efficiency, and this by adding a voice activity detector (VAD module before the application of the discrete wavelet transform. The VAD module avoids the computation of the discrete wavelet coefficients during the inactive voice signal. In addition, a real-time implementation of the optimized speech compression algorithm is performed using fixed-point processor. The optimized and the original algorithms are evaluated and compared in terms of CPU time (sec, Cycle count (MCPS, Memory consumption (Ko, Compression Ratio (CR, Signal to Noise Ratio (SNR, Peak Signal to Noise Ratio (PSNR and Normalized Root Mean Square Error (NRMSE.
SMART AS A CRYPTOGRAPHIC PROCESSOR
Saroja Kanchi
2016-05-01
Full Text Available SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algorithm on the HC12, a same-size but CISC-type off-the-shelf microcontroller, Our results show that compared to HC12, SMaRT code is only 14% longer in terms of the static number of instructions but about 10 times faster in terms of the number of clock cycles, and 7% smaller in terms of code size. Our results also show that 2.5- address instructions, a SMaRT selling point, amount to 45% of the whole R-type instructions resulting in significant improvement in static number of instructions hence code size as well as performance. Additionally, we see that the SMaRT short-branch range is sufficiently wide in 90% of cases in the SMaRT code. Our results also reveal that the SMaRT novel concept of locality of reference in using the MSBs of the registers in non-subroutine branch instructions stays valid with a remarkable hit rate of 95%!
DSPSR: Digital Signal Processing Software for Pulsar Astronomy
van Straten, W
2010-01-01
DSPSR is a high-performance, open-source, object-oriented, digital signal processing software library and application suite for use in radio pulsar astronomy. Written primarily in C++, the library implements an extensive range of modular algorithms that can optionally exploit both multiple-core processors and general-purpose graphics processing units. After over a decade of research and development, DSPSR is now stable and in widespread use in the community. This paper presents a detailed description of its functionality, justification of major design decisions, analysis of phase-coherent dispersion removal algorithms, and demonstration of performance on some contemporary microprocessor architectures.
Energy Efficiency of a Multi-Core Processor by Tag Reduction
Long Zheng; Mian-Xiong Dong; Kaoru Ota; Hai Jin; Song Guo; Jun Ma
2011-01-01
We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This paper extends the tag reduction technique on a single-core processor to a multi-core processor and investigates the potential of energy saving for multi-core processors. We formulate our approach as an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. We provide convincing experimental results by collecting experimental data from a real operating system instead of the traditional way using a processor simulator that cannot simulate operating system functions and the full memory hierarchy. Experimental results show that our proposed algorithms can save total energy up to 83.93% on an 8-core processor and 76.16% on a 4-core processor in average compared to the one that the tag-reduction is not used for. They also significantly outperform the tag reduction based algorithm on a single-core processor.
IMPLEMENTATION OF A REAL-TIME STACKING ALGORITHM IN A PHOTOGRAMMETRIC DIGITAL CAMERA FOR UAVS
A. Audi
2017-08-01
Full Text Available In the recent years, unmanned aerial vehicles (UAVs have become an interesting tool in aerial photography and photogrammetry activities. In this context, some applications (like cloudy sky surveys, narrow-spectral imagery and night-vision imagery need a longexposure time where one of the main problems is the motion blur caused by the erratic camera movements during image acquisition. This paper describes an automatic real-time stacking algorithm which produces a high photogrammetric quality final composite image with an equivalent long-exposure time using several images acquired with short-exposure times. Our method is inspired by feature-based image registration technique. The algorithm is implemented on the light-weight IGN camera, which has an IMU sensor and a SoC/FPGA. To obtain the correct parameters for the resampling of images, the presented method accurately estimates the geometrical relation between the first and the Nth image, taking into account the internal parameters and the distortion of the camera. Features are detected in the first image by the FAST detector, than homologous points on other images are obtained by template matching aided by the IMU sensors. The SoC/FPGA in the camera is used to speed up time-consuming parts of the algorithm such as features detection and images resampling in order to achieve a real-time performance as we want to write only the resulting final image to save bandwidth on the storage device. The paper includes a detailed description of the implemented algorithm, resource usage summary, resulting processing time, resulting images, as well as block diagrams of the described architecture. The resulting stacked image obtained on real surveys doesn’t seem visually impaired. Timing results demonstrate that our algorithm can be used in real-time since its processing time is less than the writing time of an image in the storage device. An interesting by-product of this algorithm is the 3D rotation
Cache Energy Optimization Techniques For Modern Processors
Mittal, Sparsh [ORNL
2013-01-01
newcomers and veterans in the field of cache power management. It will help graduate students, CAD tool developers and designers in understanding the need of energy efficiency in modern computing systems. Further, it will be useful for researchers in gaining insights into algorithms and techniques for micro-architectural and system-level energy optimization using dynamic cache reconfiguration. We sincerely believe that the ``food for thought'' presented in this book will inspire the readers to develop even better ideas for designing ``green'' processors of tomorrow.
Big Bang–Big Crunch Optimization Algorithm for Linear Phase Fir Digital Filter Design
Ms. Rashmi Singh Dr. H. K. Verma
2012-02-01
Full Text Available The Big Bang–Big Crunch (BB–BC optimization algorithm is a new optimization method that relies on the Big Bang and Big Crunch theory, one of the theories of the evolution of the universe. In this paper, a Big Bang–Big Crunch algorithm has been used here for the design of linear phase finite impulse response (FIR filters. Here the experimented fitness function based on the mean squared error between the actual and the ideal filter response. This paper presents the plot of magnitude response of FIR filters and error graph. The BB-BC seems to be promising tool for FIR filter design especially in a dynamic environment where filter coefficients have to be adapted and fast convergence is of importance.
Zeng, Rongping; Badano, Aldo; Myers, Kyle J.
2017-04-01
We showed in our earlier work that the choice of reconstruction methods does not affect the optimization of DBT acquisition parameters (angular span and number of views) using simulated breast phantom images in detecting lesions with a channelized Hotelling observer (CHO). In this work we investigate whether the model-observer based conclusion is valid when using humans to interpret images. We used previously generated DBT breast phantom images and recruited human readers to find the optimal geometry settings associated with two reconstruction algorithms, filtered back projection (FBP) and simultaneous algebraic reconstruction technique (SART). The human reader results show that image quality trends as a function of the acquisition parameters are consistent between FBP and SART reconstructions. The consistent trends confirm that the optimization of DBT system geometry is insensitive to the choice of reconstruction algorithm. The results also show that humans perform better in SART reconstructed images than in FBP reconstructed images. In addition, we applied CHOs with three commonly used channel models, Laguerre-Gauss (LG) channels, square (SQR) channels and sparse difference-of-Gaussian (sDOG) channels. We found that LG channels predict human performance trends better than SQR and sDOG channel models for the task of detecting lesions in tomosynthesis backgrounds. Overall, this work confirms that the choice of reconstruction algorithm is not critical for optimizing DBT system acquisition parameters.
Wavelength-encoded OCDMA system using opto-VLSI processors.
Aljada, Muhsen; Alameh, Kamal
2007-07-01
We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.
Communication Efficient Multi-processor FFT
Lennart Johnsson, S.; Jacquemin, Michel; Krawitz, Robert L.
1992-10-01
Computing the fast Fourier transform on a distributed memory architecture by a direct pipelined radix-2, a bi-section, or a multisection algorithm, all yield the same communications requirement, if communication for all FFT stages can be performed concurrently, the input data is in normal order, and the data allocation is consecutive. With a cyclic data allocation, or bit-reversed input data and a consecutive allocation, multi-sectioning offers a reduced communications requirement by approximately a factor of two. For a consecutive data allocation, normal input order, a decimation-in-time FFT requires that P/ N + d-2 twiddle factors be stored for P elements distributed evenly over N processors, and the axis that is subject to transformation be distributed over 2 d processors. No communication of twiddle factors is required. The same storage requirements hold for a decimation-in-frequency FFT, bit-reversed input order, and consecutive data allocation. The opposite combination of FFT type and data ordering requires a factor of log 2N more storage for N processors. The peak performance for a Connection Machine system CM-200 implementation is 12.9 Gflops/s in 32-bit precision, and 10.7 Gflops/s in 64-bit precision for unordered transforms local to each processor. The corresponding execution rates for ordered transforms are 11.1 Gflops/s and 8.5 Gflops/s, respectively. For distributed one- and two-dimensional transforms the peak performance for unordered transforms exceeds 5 Gflops/s in 32-bit precision and 3 Gflops/s in 64-bit precision. Three-dimensional transforms execute at a slightly lower rate. Distributed ordered transforms execute at a rate of about {1}/{2}to {2}/{3} of the unordered transforms.
Woonki Na
2017-03-01
Full Text Available This paper presents an improved maximum power point tracking (MPPT algorithm using a fuzzy logic controller (FLC in order to extract potential maximum power from photovoltaic cells. The objectives of the proposed algorithm are to improve the tracking speed, and to simultaneously solve the inherent drawbacks such as slow tracking in the conventional perturb and observe (P and O algorithm. The performances of the conventional P and O algorithm and the proposed algorithm are compared by using MATLAB/Simulink in terms of the tracking speed and steady-state oscillations. Additionally, both algorithms were experimentally validated through a digital signal processor (DSP-based controlled-boost DC-DC converter. The experimental results show that the proposed algorithm performs with a shorter tracking time, smaller output power oscillation, and higher efficiency, compared with the conventional P and O algorithm.
Kim, R S J; Postman, M; Strauss, M A; Bahcall, Neta A; Gunn, J E; Lupton, R H; Annis, J; Nichol, R C; Castander, F J; Brinkmann, J; Brunner, R J; Connolly, A; Csabai, I; Hindsley, R B; Ivezic, Z; Vogeley, M S; York, D G; Kim, Rita S. J.; Kepner, Jeremy V.; Postman, Marc; Strauss, Michael A.; Bahcall, Neta A.; Gunn, James E.; Lupton, Robert H.; Annis, James; Nichol, Robert C.; Castander, Francisco J.; Brunner, Robert J.; Connolly, Andrew; Csabai, Istvan; Hindsley, Robert B.; Ivezic, Zeljko; Vogeley, Michael S.; York, Donald G.
2002-01-01
We present a comparison of three cluster finding algorithms from imaging data using Monte Carlo simulations of clusters embedded in a 25 deg^2 region of Sloan Digital Sky Survey (SDSS) imaging data: the Matched Filter (MF; Postman et al. 1996), the Adaptive Matched Filter (AMF; Kepner et al. 1999) and a color-magnitude filtered Voronoi Tessellation Technique (VTT). Among the two matched filters, we find that the MF is more efficient in detecting faint clusters, whereas the AMF evaluates the redshifts and richnesses more accurately, therefore suggesting a hybrid method (HMF) that combines the two. The HMF outperforms the VTT when using a background that is uniform, but it is more sensitive to the presence of a non-uniform galaxy background than is the VTT; this is due to the assumption of a uniform background in the HMF model. We thus find that for the detection thresholds we determine to be appropriate for the SDSS data, the performance of both algorithms are similar; we present the selection function for eac...
数字全息技术中散斑噪声滤波算法比较%Comparison of algorithms for filtering speckle noise in digital holography
潘云; 潘卫清; 晁明举
2011-01-01
In the recording process of digital holographic measurement, the hologram is easily polluted by speckle noise, which may decrease the resolution of the hologram. In addition, the reconstructed effect is seriously affected by speckle noise in digital reconstruction. Thus it is important to study the filtering speckle algorithms for digital hologram. The median filtering algorithm, Lee filtering algorithm, Kuan filtering algorithm and SUSAN filtering algorithm were introduced to filter the speckle noise in hologram and reconstructed image. Then these algorithms were compared. The results showed that the SUSAN filtering algorithm was better in digital holographic technology. The speckle noises were suppressed significantly and the information of reconstructed images were well maintained.%在数字全息测量记录过程中,其所记录的全息图易受到散斑噪声的污染造成分辨率下降,同时也严重影响数字全息再现的效果,因此研究适用于数字全息技术中散斑滤波的算法具有重要的实用价值.介绍了中值滤波、Lee滤波、Kuan滤波和SUSAN滤波这四种常用的散斑滤波算法,并将它们运用于数字全息实验所记录图像和数字再现图像的散斑噪声滤波处理中,然后对这四种算法的处理结果进行评价.结果表明,在数字全息技术中使用SUSAN滤波算法进行处理,既明显抑制了散斑噪声,又有效保证了再现图像信息的完整性.
Benitez R, J.S.; Perez C, B. [Instituto Nacional de Investigaciones Nucleares, Km. 36.5 Carretera Mexico-Toluca, Municipio de Ocoyoacac, 52045 Estado de Mexico (Mexico)
2002-07-01
The first stage of the development of a digital system based on a DSP is presented which forms part of an hybrid simulator for the power regulation in am model of the punctual kinetics of a TRIGA reactor type. The DSP performs the regulation, using a Mandami type algorithm of diffuse control. In the algorithm, the universe of the output variable is discretized for performing in an unique stage the aggregation functions and dis-diffusization. (Author)
Lu, Lee-Jane W.; Nishino, Thomas K.; Johnson, Raleigh F.; Nayeem, Fatima; Brunder, Donald G.; Ju, Hyunsu; Leonard, Morton H., Jr.; Grady, James J.; Khamapirad, Tuenchit
2012-11-01
Women with mostly mammographically dense fibroglandular tissue (breast density, BD) have a four- to six-fold increased risk for breast cancer compared to women with little BD. BD is most frequently estimated from two-dimensional (2D) views of mammograms by a histogram segmentation approach (HSM) and more recently by a mathematical algorithm consisting of mammographic imaging parameters (MATH). Two non-invasive clinical magnetic resonance imaging (MRI) protocols: 3D gradient-echo (3DGRE) and short tau inversion recovery (STIR) were modified for 3D volumetric reconstruction of the breast for measuring fatty and fibroglandular tissue volumes by a Gaussian-distribution curve-fitting algorithm. Replicate breast exams (N = 2 to 7 replicates in six women) by 3DGRE and STIR were highly reproducible for all tissue-volume estimates (coefficients of variation tissue, (2) 0.72-0.82, 0.64-0.96, and 0.77-0.91, for glandular volume, (3) 0.87-0.98, 0.94-1.07, and 0.89-0.99, for fat volume, and (4) 0.89-0.98, 0.94-1.00, and 0.89-0.98, for total breast volume. For all values estimated, the correlation was stronger for comparisons between the two MRI than between each MRI versus mammography, and between each MRI versus MATH data than between each MRI versus HSM data. All ICC values were >0.75 indicating that all four methods were reliable for measuring BD and that the mathematical algorithm and the two complimentary non-invasive MRI protocols could objectively and reliably estimate different types of breast tissues.
A New Algorithm for Creating Digital Certificate’s Private Key from Iris
Farrokh Koropi
2010-06-01
Full Text Available Enterprises are now global, virtual and dependent on dynamic information access. Naturally, digital information is constant throughout its lifecycle. In this shifting landscape, the battlefront in security is rapidly changing from securing the perimeter to protecting the information itself. The primary advantage of public-key cryptography is increased security and convenience: private keys never need to be transmitted or revealed to anyone, but loss of a private key may cause the loss of valuable data. In this paper, we proposed a new method of using iris biometric instead of private keys, so that the iris cannot be lost, stolen or even misused. The two first stages of iris recognition are implemented as the preliminary result. Our approach is feasible to produce an iris template for using as a private key in identity identification and biometric watermarking applications.
Ray, R. J.; Myers, L. P.
1986-01-01
The highly integrated digital electronic control (HIDEC) program will demonstrate and evaluate the improvements in performance and mission effectiveness that result from integrated engine-airframe control systems. Performance improvements will result from an adaptive engine stall margin mode, a highly integrated mode that uses the airplane flight conditions and the resulting inlet distortion to continuously compute engine stall margin. When there is excessive stall margin, the engine is uptrimmed for more thrust by increasing engine pressure ratio (EPR). The EPR uptrim logic has been evaluated and implemente into computer simulations. Thrust improvements over 10 percent are predicted for subsonic flight conditions. The EPR uptrim was successfully demonstrated during engine ground tests. Test results verify model predictions at the conditions tested.
Alag, G. S.; Kaufman, H.
1974-01-01
Simple mechanical linkages are often unable to cope with the many control problems associated with high performance aircraft maneuvering over a wide flight envelope. One procedure for retaining uniform handling qualities over such an envelope is to implement a digital adaptive controller. Towards such an implementation an explicit adaptive controller, which makes direct use of online parameter identification, has been developed and applied to the linearized equations of motion for a typical fighter aircraft. The system is composed of an online weighted least squares identifier, a Kalman state filter, and a single stage real model following control law. The corresponding control gains are readily adjustable in accordance with parameter changes to ensure asymptotic stability if the conditions for perfect model following are satisfied and stability in the sense of boundedness otherwise.
The LOGO Processor; A Guide for System Programmers.
Weiner, Walter B.; And Others
A detailed specification of the LOGO programing system is given. The level of description is intended to enable system programers to design LOGO processors of their own. The discussion of storage allocation and garbage collection algorithms is virtually complete. An annotated LOGO system listing for the PDP-10 computer system may be obtained on…
Implementation of Genetic Algorithm in Control Structure of Induction Motor A.C. Drive
BRANDSTETTER, P.
2014-11-01
Full Text Available Modern concepts of control systems with digital signal processors allow the implementation of time-consuming control algorithms in real-time, for example soft computing methods. The paper deals with the design and technical implementation of a genetic algorithm for setting proportional and integral gain of the speed controller of the A.C. drive with the vector-controlled induction motor. Important simulations and experimental measurements have been realized that confirm the correctness of the proposed speed controller tuned by the genetic algorithm and the quality speed response of the A.C. drive with changing parameters and disturbance variables, such as changes in load torque.
H~ Estimation Approach to Active Noise Control: Theory, Algorithm and Real-Time Implementation
Bambang Riyanto
2003-11-01
Full Text Available This paper presents an H¥ estimation approach to active control of acoustic noise inside an enclosure. It is shown how H¥ filter theory and algorithm can be effectively applied to active noise control to provide important robustness property. Real-time implementation of the algorithm is performed on Digital Signal Processor. Experimental comparison to conventional FxLMS algorithm for active noise control is presented for both single channel and multichannel cases. While providing some new results, this paper also serves as a brief review on H¥ filter theory and on active noise control.
Digital Image Encryption Scheme Based on Multiple Chaotic Systems
Abd El-Latif, Ahmed A.; Li, Li; Zhang, Tiejun; Wang, Ning; Song, Xianhua; Niu, Xiamu
2012-06-01
Image encryption is a challenging task due to the significant level of sophistication achieved by forgerers and other cybercriminals. Advanced encryption methods for secure transmission, storage, and retrieval of digital images are increasingly needed for a number of military, medical, homeland security, and other applications. In this paper, we introduce a new digital image encryption algorithm. The new algorithm employs multiple chaotic systems and cryptographic primitive operations within the encryption process, which are efficiently implemented on modern processors, and adopts round keys for encryption using a chaotic map. Experiments conducted show that the proposed algorithm possesses robust security features such as fairly uniform distribution, high sensitivity to both keys and plainimages, almost ideal entropy, and the ability to highly de-correlate adjacent pixels in the cipherimages. Furthermore, it has a large key space, which greatly increases its security for image encryption applications.
Momeni, Saba; Pourghassem, Hossein
2014-08-01
Recently image fusion has prominent role in medical image processing and is useful to diagnose and treat many diseases. Digital subtraction angiography is one of the most applicable imaging to diagnose brain vascular diseases and radiosurgery of brain. This paper proposes an automatic fuzzy-based multi-temporal fusion algorithm for 2-D digital subtraction angiography images. In this algorithm, for blood vessel map extraction, the valuable frames of brain angiography video are automatically determined to form the digital subtraction angiography images based on a novel definition of vessel dispersion generated by injected contrast material. Our proposed fusion scheme contains different fusion methods for high and low frequency contents based on the coefficient characteristic of wrapping second generation of curvelet transform and a novel content selection strategy. Our proposed content selection strategy is defined based on sample correlation of the curvelet transform coefficients. In our proposed fuzzy-based fusion scheme, the selection of curvelet coefficients are optimized by applying weighted averaging and maximum selection rules for the high frequency coefficients. For low frequency coefficients, the maximum selection rule based on local energy criterion is applied to better visual perception. Our proposed fusion algorithm is evaluated on a perfect brain angiography image dataset consisting of one hundred 2-D internal carotid rotational angiography videos. The obtained results demonstrate the effectiveness and efficiency of our proposed fusion algorithm in comparison with common and basic fusion algorithms.
A high-accuracy optical linear algebra processor for finite element applications
Casasent, D.; Taylor, B. K.
1984-01-01
Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.
Pani, Danilo; Barabino, Gianluca; Citi, Luca; Meloni, Paolo; Raspopovic, Stanisa; Micera, Silvestro; Raffo, Luigi
2016-09-01
The control of upper limb neuroprostheses through the peripheral nervous system (PNS) can allow restoring motor functions in amputees. At present, the important aspect of the real-time implementation of neural decoding algorithms on embedded systems has been often overlooked, notwithstanding the impact that limited hardware resources have on the efficiency/effectiveness of any given algorithm. Present study is addressing the optimization of a template matching based algorithm for PNS signals decoding that is a milestone for its real-time, full implementation onto a floating-point digital signal processor (DSP). The proposed optimized real-time algorithm achieves up to 96% of correct classification on real PNS signals acquired through LIFE electrodes on animals, and can correctly sort spikes of a synthetic cortical dataset with sufficiently uncorrelated spike morphologies (93% average correct classification) comparably to the results obtained with top spike sorter (94% on average on the same dataset). The power consumption enables more than 24 h processing at the maximum load, and latency model has been derived to enable a fair performance assessment. The final embodiment demonstrates the real-time performance onto a low-power off-the-shelf DSP, opening to experiments exploiting the efferent signals to control a motor neuroprosthesis.
Real-time image processing of TOF range images using a reconfigurable processor system
Hussmann, S.; Knoll, F.; Edeler, T.
2011-07-01
During the last years, Time-of-Flight sensors achieved a significant impact onto research fields in machine vision. In comparison to stereo vision system and laser range scanners they combine the advantages of active sensors providing accurate distance measurements and camera-based systems recording a 2D matrix at a high frame rate. Moreover low cost 3D imaging has the potential to open a wide field of additional applications and solutions in markets like consumer electronics, multimedia, digital photography, robotics and medical technologies. This paper focuses on the currently implemented 4-phase-shift algorithm in this type of sensors. The most time critical operation of the phase-shift algorithm is the arctangent function. In this paper a novel hardware implementation of the arctangent function using a reconfigurable processor system is presented and benchmarked against the state-of-the-art CORDIC arctangent algorithm. Experimental results show that the proposed algorithm is well suited for real-time processing of the range images of TOF cameras.
Modal Processor Effects Inspired by Hammond Tonewheel Organs
Kurt James Werner
2016-06-01
Full Text Available In this design study, we introduce a novel class of digital audio effects that extend the recently introduced modal processor approach to artificial reverberation and effects processing. These pitch and distortion processing effects mimic the design and sonics of a classic additive-synthesis-based electromechanical musical instrument, the Hammond tonewheel organ. As a reverb effect, the modal processor simulates a room response as the sum of resonant filter responses. This architecture provides precise, interactive control over the frequency, damping, and complex amplitude of each mode. Into this framework, we introduce two types of processing effects: pitch effects inspired by the Hammond organ’s equal tempered “tonewheels”, “drawbar” tone controls, vibrato/chorus circuit, and distortion effects inspired by the pseudo-sinusoidal shape of its tonewheels and electromagnetic pickup distortion. The result is an effects processor that imprints the Hammond organ’s sonics onto any audio input.
Cheng, Beato T.
2010-04-01
With the advances in focal plane, electronics and memory storage technologies, wide area and persistence surveillance capabilities have become a reality in airborne ISR. A WAS system offers many benefits in comparison with the traditional airborne image capturing systems that provide little data overlap, both in terms of space and time. Unlike a fix-mount surveillance camera, a persistence WAS system can be deployed anywhere as desired, although the platform typically has to be in motion, say circling above an area of interest. Therefore, WAS is a perfect choice for surveillance that can provide near real time capabilities such as change detection and target tracking. However, the performance of a WAS system is still limited by the available technologies: the optics that control the field-of-view, the electronics and mechanical subsystems that control the scanning, the focal plane data throughput, and the dynamics of the platform all play key roles in the success of the system. It is therefore beneficial to develop a simulated version that can capture the essence of the system, in order to help provide insights into the design of an optimized system. We describe an approach to the simulation of a generic WAS system that allows focal plane layouts, scanning patterns, flight paths and platform dynamics to be defined by a user. The system generates simulated image data of the area ground coverage from reference databases (e.g. aerial imagery, and elevation data), based on the sensor model. The simulated data provides a basis for further algorithm development, such as image stitching/mosaic, registration, and geolocation. We also discuss an algorithm to extract the terrain elevation from the simulated data, and to compare that with the original DEM data.
Mirosław-Świątek, Dorota; Szporak-Wasilewska, Sylwia; Michałowski, Robert; Kardel, Ignacy; Grygoruk, Mateusz
2016-07-01
Airborne laser scanning survey data were conducted with a scanning density of 4 points/m2 to accurately map the surface of a unique central European complex of wetlands: the lower Biebrza River valley (Poland). A method to correct a degrading effect of vegetation (so-called "vegetation effect") on digital terrain models (DTMs) was applied utilizing remotely sensed images, real-time kinematic global positioning system elevation measurements, topographical surveys, and vegetation height measurements. Geographic object-based image analysis (GEOBIA) was performed to map vegetation within the study area that was used as categories from which vegetation height information was derived for the DTM correction. The final DTM was compared with a model obtained, where additional correction of the "vegetation effect" was neglected. A comparison between corrected and uncorrected DTMs demonstrated the importance of accurate topography through a simple presentation of the discrepancies arising in features of the flood using various DTM products. An overall map classification accuracy of 80% was attained with the use of GEOBIA. Correction factors developed for various types of the vegetation reached values from 0.08 up to 0.92 m and were dependent on the vegetation type.
A Distributed Spanning Tree Algorithm
Johansen, Karl Erik; Jørgensen, Ulla Lundin; Nielsen, Sven Hauge
We present a distributed algorithm for constructing a spanning tree for connected undirected graphs. Nodes correspond to processors and edges correspond to two-way channels. Each processor has initially a distinct identity and all processors perform the same algorithm. Computation as well...... as communication is asynchronous. The total number of messages sent during a construction of a spanning tree is at most 2E+3NlogN. The maximal message size is loglogN+log(maxid)+3, where maxid is the maximal processor identity....
A distributed spanning tree algorithm
Johansen, Karl Erik; Jørgensen, Ulla Lundin; Nielsen, Svend Hauge
1988-01-01
We present a distributed algorithm for constructing a spanning tree for connected undirected graphs. Nodes correspond to processors and edges correspond to two way channels. Each processor has initially a distinct identity and all processors perform the same algorithm. Computation as well...... as communication is asyncronous. The total number of messages sent during a construction of a spanning tree is at most 2E+3NlogN. The maximal message size is loglogN+log(maxid)+3, where maxid is the maximal processor identity....
A Distributed Spanning Tree Algorithm
Johansen, Karl Erik; Jørgensen, Ulla Lundin; Nielsen, Sven Hauge
We present a distributed algorithm for constructing a spanning tree for connected undirected graphs. Nodes correspond to processors and edges correspond to two-way channels. Each processor has initially a distinct identity and all processors perform the same algorithm. Computation as well...... as communication is asynchronous. The total number of messages sent during a construction of a spanning tree is at most 2E+3NlogN. The maximal message size is loglogN+log(maxid)+3, where maxid is the maximal processor identity....
Fast Forwarding with Network Processors
Lefèvre, Laurent; Lemoine, E.; Pham, C; Tourancheau, B.
2003-01-01
Forwarding is a mechanism found in many network operations. Although a regular workstation is able to perform forwarding operations it still suffers from poor performances when compared to dedicated hardware machines. In this paper we study the possibility of using Network Processors (NPs) to improve the capability of regular workstations to forward data. We present a simple model and an experimental study demonstrating that even though NPs are less powerful than Host Processors (HPs) they ca...
Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA
Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei
2013-03-01
With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.
A 2D driven 3D vessel segmentation algorithm for 3D digital subtraction angiography data
Spiegel, M; Hornegger, J [Pattern Recognition Lab, University Erlangen-Nuremberg, Erlangen (Germany); Redel, T [Siemens AG Healthcare Sector, Forchheim (Germany); Struffert, T; Doerfler, A, E-mail: martin.spiegel@informatik.uni-erlangen.de [Department of Neuroradiology, University Erlangen-Nuremberg, Erlangen (Germany)
2011-10-07
Cerebrovascular disease is among the leading causes of death in western industrial nations. 3D rotational angiography delivers indispensable information on vessel morphology and pathology. Physicians make use of this to analyze vessel geometry in detail, i.e. vessel diameters, location and size of aneurysms, to come up with a clinical decision. 3D segmentation is a crucial step in this pipeline. Although a lot of different methods are available nowadays, all of them lack a method to validate the results for the individual patient. Therefore, we propose a novel 2D digital subtraction angiography (DSA)-driven 3D vessel segmentation and validation framework. 2D DSA projections are clinically considered as gold standard when it comes to measurements of vessel diameter or the neck size of aneurysms. An ellipsoid vessel model is applied to deliver the initial 3D segmentation. To assess the accuracy of the 3D vessel segmentation, its forward projections are iteratively overlaid with the corresponding 2D DSA projections. Local vessel discrepancies are modeled by a global 2D/3D optimization function to adjust the 3D vessel segmentation toward the 2D vessel contours. Our framework has been evaluated on phantom data as well as on ten patient datasets. Three 2D DSA projections from varying viewing angles have been used for each dataset. The novel 2D driven 3D vessel segmentation approach shows superior results against state-of-the-art segmentations like region growing, i.e. an improvement of 7.2% points in precision and 5.8% points for the Dice coefficient. This method opens up future clinical applications requiring the greatest vessel accuracy, e.g. computational fluid dynamic modeling.
The associative memory system for the FTK processor at ATLAS
Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M
2014-01-01
In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.
A programmable systolic trigger processor for FERA-bus data
Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.
1992-09-01
A generic CAMAC based trigger processor module for fast processing of large amounts of Analog to Digital Converter (ADC) data was designed. This module was realized using complex programmable gate arrays. The gate arrays were connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter is used for set up and control but may also be used for data output. Large numbers of ADC's can be served by a hierarchical arrangement of trigger processor modules which process ADC data with pipeline arithmetics and produce the final result at the apex of the pyramid. The trigger decision is transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was developed for the proposed neutral particle search. It was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data, and calculate the particle mass. A suitable mass cut would then deliver the trigger decision.
McDonnell, Mark D; Tissera, Migel D; Vladusich, Tony; van Schaik, André; Tapson, Jonathan
2015-01-01
Recent advances in training deep (multi-layer) architectures have inspired a renaissance in neural network use. For example, deep convolutional networks are becoming the default option for difficult tasks on large datasets, such as image and speech recognition. However, here we show that error rates below 1% on the MNIST handwritten digit benchmark can be replicated with shallow non-convolutional neural networks. This is achieved by training such networks using the 'Extreme Learning Machine' (ELM) approach, which also enables a very rapid training time (∼ 10 minutes). Adding distortions, as is common practise for MNIST, reduces error rates even further. Our methods are also shown to be capable of achieving less than 5.5% error rates on the NORB image database. To achieve these results, we introduce several enhancements to the standard ELM algorithm, which individually and in combination can significantly improve performance. The main innovation is to ensure each hidden-unit operates only on a randomly sized and positioned patch of each image. This form of random 'receptive field' sampling of the input ensures the input weight matrix is sparse, with about 90% of weights equal to zero. Furthermore, combining our methods with a small number of iterations of a single-batch backpropagation method can significantly reduce the number of hidden-units required to achieve a particular performance. Our close to state-of-the-art results for MNIST and NORB suggest that the ease of use and accuracy of the ELM algorithm for designing a single-hidden-layer neural network classifier should cause it to be given greater consideration either as a standalone method for simpler problems, or as the final classification stage in deep neural networks applied to more difficult problems.
Mark D McDonnell
Full Text Available Recent advances in training deep (multi-layer architectures have inspired a renaissance in neural network use. For example, deep convolutional networks are becoming the default option for difficult tasks on large datasets, such as image and speech recognition. However, here we show that error rates below 1% on the MNIST handwritten digit benchmark can be replicated with shallow non-convolutional neural networks. This is achieved by training such networks using the 'Extreme Learning Machine' (ELM approach, which also enables a very rapid training time (∼ 10 minutes. Adding distortions, as is common practise for MNIST, reduces error rates even further. Our methods are also shown to be capable of achieving less than 5.5% error rates on the NORB image database. To achieve these results, we introduce several enhancements to the standard ELM algorithm, which individually and in combination can significantly improve performance. The main innovation is to ensure each hidden-unit operates only on a randomly sized and positioned patch of each image. This form of random 'receptive field' sampling of the input ensures the input weight matrix is sparse, with about 90% of weights equal to zero. Furthermore, combining our methods with a small number of iterations of a single-batch backpropagation method can significantly reduce the number of hidden-units required to achieve a particular performance. Our close to state-of-the-art results for MNIST and NORB suggest that the ease of use and accuracy of the ELM algorithm for designing a single-hidden-layer neural network classifier should cause it to be given greater consideration either as a standalone method for simpler problems, or as the final classification stage in deep neural networks applied to more difficult problems.
Hu, Jiaqi; Li, Qi; Cui, Shanshan
2014-10-20
In terahertz inline digital holography, zero-order diffraction light and conjugate images can cause the reconstructed image to be blurred. In this paper, three phase retrieval algorithms are applied to conduct reconstruction based on the same near-field diffraction propagation conditions and image-plane constraints. The impact of different object-plane constraints on CW terahertz inline digital holographic reconstruction is studied. The results show that in the phase retrieval algorithm it is not suitable to impose restriction on the phase when the object is not isolated in the transmission-type CW terahertz inline digital holography. In addition, the effects of zero-padding expansion, boundary replication expansion, and apodization operation on reconstructed images are studied. The results indicate that the conjugate image can be eliminated, and a better reconstructed image can be obtained by adopting an appropriate phase retrieval algorithm after the normalized hologram extending to the minimum area, which meets the applicable range of the angular spectrum reconstruction algorithm by means of boundary replication.
Performance evaluation of H.264 decoder on different processors
H.S.Prasantha
2010-08-01
Full Text Available H.264/AVC (Advanced Video Coding is the newest video coding standard of the moving video coding experts group. The decoder is standardized by imposing restrictions on the bit stream and syntax, and defining the process of decoding syntax elements such that every decoder conforming to the standard will produce similar output when encoded bit stream is provided as input. It uses state of art coding tools and provides enhanced coding efficiency for a wide range of applications, including video telephony, real-time video conferencing, direct-broadcast TV (television, blue-ray disc, DVB (Digital video broadcast broadcast, streaming video and others. The paper proposes to port the H.264/AVC decoder on the various processors such as TI DSP (Digital signal processor, ARM (Advanced risk machines and P4 (Pentium processors. The paper also proposesto analyze and compare Video Quality Metrics for different encoded video sequences. The paper proposes to investigate the decoder performance on different processors with and without deblocking filter and compare the performance based on different video quality measures.
Demonstrating quantum speed-up in a superconducting two-qubit processor
Dewes, A; Ong, F R; Schmitt, V; Milman, P; Bertet, P; Vion, D; Esteve, D
2011-01-01
We operate a superconducting quantum processor consisting of two tunable transmon qubits coupled by a swapping interaction, and equipped with non destructive single-shot readout of the two qubits. With this processor, we run the Grover search algorithm among four objects and find that the correct answer is retrieved after a single run with a success probability between 0.52 and 0.67, significantly larger than the 0.25 achieved with a classical algorithm. This constitutes a proof-of-concept for the quantum speed-up of electrical quantum processors.
Guerrero Gonzalez, Neil; Zibar, Darko; Caballero Jambrina, Antonio;
2010-01-01
Highest reported bit rate of 2.5 Gb/s for optically phase modulated radio-over-fiber (RoF) link, employing digital coherent detection, is demonstrated. Demodulation of 3$,times,$ 2.5 Gb/s quadrature phase-shift keying modulated wavelength-division-multiplexed RoF channels is achieved after 79 km ...... of transmission through deployed fiber. Error-free performance (bit-error rate corresponding to $10^{{-}4}$) is achieved using a digital coherent receiver in combination with a $K$-means algorithm for radio-frequency phase recovery....
Guerrero Gonzalez, Neil; Zibar, Darko; Caballero Jambrina, Antonio
2010-01-01
Highest reported bit rate of 2.5 Gb/s for optically phase modulated radio-over-fiber (RoF) link, employing digital coherent detection, is demonstrated. Demodulation of 3$,times,$ 2.5 Gb/s quadrature phase-shift keying modulated wavelength-division-multiplexed RoF channels is achieved after 79 km...... of transmission through deployed fiber. Error-free performance (bit-error rate corresponding to $10^{{-}4}$) is achieved using a digital coherent receiver in combination with a $K$-means algorithm for radio-frequency phase recovery....
Low Power Complex Multiplier based FFT Processor
V.Sarada
2015-08-01
Full Text Available High speed processing of signals has led to the requirement of very high speed conversion of signals from time domain to frequency domain. Recent years there has been increasing demand for low power designs in the field of Digital signal processing. Power consumption is the most important aspect while considering the system performance. In order to design high performance Fast Fourier Transform (FFT and realization, efficient internal structure is required. In this paper we present FFT Single Path Delay feedback (SDF pipeline architecture using radix -24 algorithm .The complex multiplier is realized by using Digit Slicing Concept multiplier less architecture. To reduce computation complexity radix 24 algorithms is used. The proposed design has been coded in Verilog HDL and synthesizes by Cadence tool. The result demonstrates that the power is reduced compared with complex multiplication used CSD (Canonic Signed Digit multiplier.