Cost-effective bidirectional digitized radio-over-fiber systems employing sigma delta modulation

Science.gov (United States)

Lee, Kyung Woon; Jung, HyunDo; Park, Jung Ho

2016-11-01

We propose a cost effective digitized radio-over-fiber (D-RoF) system employing a sigma delta modulation (SDM) and a bidirectional transmission technique using phase modulated downlink and intensity modulated uplink. SDM is transparent to different radio access technologies and modulation formats, and more suitable for a downlink of wireless system because a digital to analog converter (DAC) can be avoided at the base station (BS). Also, Central station and BS share the same light source by using a phase modulation for the downlink and an intensity modulation for the uplink transmission. Avoiding DACs and light sources have advantages in terms of cost reduction, power consumption, and compatibility with conventional wireless network structure. We have designed a cost effective bidirectional D-RoF system using a low pass SDM and measured the downlink and uplink transmission performance in terms of error vector magnitude, signal spectra, and constellations, which are based on the 10MHz LTE 64-QAM standard.

A 155µW 88-dB DR discrete-time delta-sigma modulator for digital hearing aids exploiting a summing SAR ADC Quantizer

NARCIS (Netherlands)

Porrazzo, S.; Morgado, A.; San Segundo Bello, D.; Cannillo, F.; Van Hoof, C.; Yazicioglu, R.F.; Roermund, van Arthur; Cantatore, Eugenio

2013-01-01

This paper presents a low-power switched-capacitor $Delta Sigma$ modulator for digital hearing-aid applications that features a novel summing successive approximation (SAR). The summing SAR performs multi-bit quantization together with the analog addition required in feed-forward (FF) $Delta Sigma$

Sigma-Delta Voltage to Frequency Converter With Phase Modulation Possibility

OpenAIRE

STORK, Milan

2014-01-01

Voltage to frequency converter (VFC) is an oscillator whose frequency is linearly proportional to control voltage. There are two common VFC architectures: the current steering multivibrator and the charge-balance VFC. For higher linearity, the charge-balancing method is preferred. The charge balanced VFC may be made in asynchronous or synchronous (clocked) forms. The synchronous charge balanced VFC or "sigma delta" (S-D) VFC is used when output pulses are synchroni...

Reference-Free CMOS Pipeline Analog-to-Digital Converters

CERN Document Server

Figueiredo, Michael; Evans, Guiomar

2013-01-01

This book shows that digitally assisted analog-to-digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low ...

Low Power Continuous-Time Delta-Sigma ADC with Current Output DAC

DEFF Research Database (Denmark)

Marker-Villumsen, Niels; Jørgensen, Ivan Harald Holger; Bruun, Erik

2015-01-01

The paper presents a continuous-time (CT) DeltaSigma (∆Σ) analog-to-digital converter (ADC) using a current output digital-to-analog converter (DAC) for the feedback. From circuit analysis it is shown that using a current output DAC makes it possible to relax the noise requirements of the 1st...... integrator of the loopfilter, and thereby reduce the current consumption. Furthermore, the noise of the current output DAC being dependent on the ADC input signal level, enabling a dynamic range that is larger than the peak signal-to-noise ratio (SNR). The current output DAC is used in a 3rd order multibit...... CT ∆Σ ADC for audio applications, designed in a 0.18 µm CMOS process, with active-RC integrators, a 7-level Flash ADC quantizer and current output DAC for the feedback. From simulations the ADC achieves a dynamic range of 95.0 dB in the audio band, with a current consumption of 284 µA for a 1.7 V...

Real time event selection and flash analog-to-digital converters

International Nuclear Information System (INIS)

Imori, Masatosi

1983-01-01

In high-energy particle experiments, high-speed analog logic is employed to select events on a real-time basis. Flash analog-to-digital converters replace the high-speed analog logic with digital logic. The digital logic gives great flexibility to the scheme for real-time event selection. This paper proposes the use of flash A/D converters for the logic used to obtain the total sum of the energy deposited in individual counters in a shower detector. (author)

Optimization of Modulator and Circuits for Low Power Continuous-Time Delta-Sigma ADC

DEFF Research Database (Denmark)

Marker-Villumsen, Niels; Bruun, Erik

2014-01-01

This paper presents a new optimization method for achieving a minimum current consumption in a continuous-time Delta-Sigma analog-to-digital converter (ADC). The method is applied to a continuous-time modulator realised with active-RC integrators and with a folded-cascode operational transconduc...... levels are swept. Based on the results of the circuit analysis, for each modulator combination the summed current consumption of the 1st integrator and quantizer of the ADC is determined. By also sweeping the partitioning of the noise power for the different circuit parts, the optimum modulator...

Combined analog-to-digital converter

International Nuclear Information System (INIS)

Zhukov, A.V.; Rzhendinskaya, S.N.

1983-01-01

A 10-bit analog-to-digital converter (ADC) designed for operating in spectrometers with time-dependent filters is described. The ADC operation is based on combining the parallel reading and sequential counting methods. At maximum conversion time of 12 μs, timing series frequency of 25 MHz and foUr reference levels the differential nonlinearity withoUt statistical smoothing (maximum relative channel width deviation from average value) is not more than 4%

A simple encoding method for Sigma-Delta ADC based biopotential acquisition systems.

Science.gov (United States)

Guerrero, Federico N; Spinelli, Enrique M

2017-10-01

Sigma Delta analogue-to-digital converters allow acquiring the full dynamic range of biomedical signals at the electrodes, resulting in less complex hardware and increased measurement robustness. However, the increased data size per sample (typically 24 bits) demands the transmission of extremely large volumes of data across the isolation barrier, thus increasing power consumption on the patient side. This problem is accentuated when a large number of channels is used as in current 128-256 electrodes biopotential acquisition systems, that usually opt for an optic fibre link to the computer. An analogous problem occurs for simpler low-power acquisition platforms that transmit data through a wireless link to a computing platform. In this paper, a low-complexity encoding method is presented to decrease sample data size without losses, while preserving the full DC-coupled signal. The method achieved a 2.3 average compression ratio evaluated over an ECG and EMG signal bank acquired with equipment based on Sigma-Delta converters. It demands a very low processing load: a C language implementation is presented that resulted in an 110 clock cycles average execution on an 8-bit microcontroller.

Energy savings assessment for digital-to-analog converter boxes

International Nuclear Information System (INIS)

Cheung, Hoi Ying; Meier, Alan; Brown, Richard

2011-01-01

The Digital Television (DTV) Converter Box Coupon Program was administered by the U.S. government to subsidize purchases of digital-to-analog converter boxes, with up to two $40 coupons for each eligible household. In order to qualify as Coupon Eligible Converter Boxes (CECBs), these devices had to meet a number of minimum performance specifications, including energy efficiency standards. The Energy Star Program also established voluntary energy efficiency specifications that are more stringent than the CECB requirements. In this study, we measured the power and energy consumptions for a sample of 12 CECBs (including 6 Energy Star labeled models) in-use in homes and estimated aggregate energy savings produced by the energy efficiency policies. Based on the 35 million coupons redeemed through the end of the program, our analysis indicates that between 2500 and 3700 GWh per year are saved as a result of the energy efficiency policies implemented on digital-to-analog converter boxes. The energy savings generated are equivalent to the annual electricity use of 280,000 average US homes. - Research highlights: → We examined energy efficiency policies on digital-to-analog converter boxes in US. → The government assistance program resulted in high participation. → 35 million coupons were redeemed for the purchases of energy efficient DTAs. → Between 2500 and 3700 GWh per year are saved as a result of the policies. → Savings are equivalent to the annual electricity use of 280,000 average US homes.

Analog-to-digital conversion

CERN Document Server

Pelgrom, Marcel J M

2010-01-01

The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for...

Designed cell consortia as fragrance-programmable analog-to-digital converters.

Science.gov (United States)

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

Energy Technology Data Exchange (ETDEWEB)

Li Di; Yang Yintang; Zhu Zhangming; Shi Lichun; Wu Xiaofeng; Wang Jiangan, E-mail: lidi2004@126.co [School of Microelectronics, Xidian University, Xi' an 710071 (China)

2010-02-15

An improved low distortion sigma-delta ADC (analog-to-digital converter) for wireless local area network standards is presented. A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however, this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR (signal to noise and distortion ratio), using 4-bit ADCs in both stages to minimize the quantization noise. Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs, which improves the SFDR (spurious free dynamic range) of the ADC. The modulator has been implemented by a 0.18 {mu}m CMOS process and operates at a single 1.8 V supply voltage. Experimental results show that for a 1.25 MHz - -6 dBFS input signal at 160 MHz sampling frequency, the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB, and the effective number of bits is 13.15 bits. (semiconductor integrated circuits)

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

OpenAIRE

Zhang, Dai

2014-01-01

Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultralow- power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent A...

System-Level Power Optimization for a ΣΔ D/A Converter for Hearing-Aid Application

DEFF Research Database (Denmark)

Pracný, Peter; Jørgensen, Ivan Harald Holger; Bruun, Erik

2013-01-01

This paper deals with a system-level optimization of a back-end of audio signal processing chain for hearing-aids, including a sigma-delta modulator digital-to-analog converter (DAC) and a Class D power amplifier. Compared to other stateof-the-art designs dealing with sigma-delta modulator design...... hearing-aid audio back-end system resulting in less hardware and power consumption in the interpolation filter, in the sigma-delta modulator and reduced switching rate of the Class D output stage....

A study of analog-to digital sliding scale. Converter utilization

Energy Technology Data Exchange (ETDEWEB)

Maddaleno, F; Rossi, M

1996-12-31

The well-known Sliding Scale technique provides a statistical linearization of the Analog to Digital Converter, obtaining a high differential linearity. This technique sums at each conversion a known and uncorrelated variable signal (offset) to the analog input signal, and then subs tract numerically the offset from the conversion result. 2 refs.

Analysis and characterization of cyclic-scale compensated analog-to-digital converters

International Nuclear Information System (INIS)

Gatti, E.; Manfredi, P.F.; Marino, D.

1979-01-01

The authors discuss characteristics and limitations of cyclic-scale compensated analog-to-digital converters. After summarizing the behaviour of the method implemented in an ideal way, they show how the inaccuracies in the auxillary analog levels affect the real design. Having stated under what approximations and with what cares a cyclic-scale compensated converter approaches the ideal case of channels having equal profiles, the consequences of this property, are studied. (Auth.)

A 13-Bits wilkinson analog-digital converter for NIM acquisition system

International Nuclear Information System (INIS)

Acosta Toledo, R.; Osorio Deliz, J.; Arista Romeu, E.; Fernandez, J.

1994-01-01

A new 13-bits Wilkinson analog-digital converter is described. The aim of this work is to describe the circuits of sample and hold, memory condensator loading and releasing PROM based control memory logic, zero level detection and correction. The converter is designed for the digital measurement of the peak amplitudes of pulses with statistical or periodical time distribution. The analog-digital converter may be used in spectrometric systems, multi-channel analysers or any similar PC based system

Diamond-Shaped Semiconductor Ring Lasers for Analog to Digital Photonic Converters

National Research Council Canada - National Science Library

Green, Malcolm

2004-01-01

Photonic/ optoelectronic analog to digital converters (ADCs) have advantages in areas such as precise sampling times, narrow sampling apertures, and the ability to sample without contaminating the incident signal...

Very High-Performance Advanced Filter Bank Analog-to-Digital Converter (AFB ADC) Project

National Research Council Canada - National Science Library

Velazquez, Scott

1999-01-01

... of the art by using a parallel array of individual commercial off the shelf converters. The significant performance improvements afforded by the Advanced Filter Bank Analog to Digital Converter (AFB ADC...

Analog electronics for radiation detection

CERN Document Server

2016-01-01

Analog Electronics for Radiation Detection showcases the latest advances in readout electronics for particle, or radiation, detectors. Featuring chapters written by international experts in their respective fields, this authoritative text: Defines the main design parameters of front-end circuitry developed in microelectronics technologies Explains the basis for the use of complementary metal oxide semiconductor (CMOS) image sensors for the detection of charged particles and other non-consumer applications Delivers an in-depth review of analog-to-digital converters (ADCs), evaluating the pros and cons of ADCs integrated at the pixel, column, and per-chip levels Describes incremental sigma delta ADCs, time-to-digital converter (TDC) architectures, and digital pulse-processing techniques complementary to analog processing Examines the fundamental parameters and front-end types associated with silicon photomultipliers used for single visible-light photon detection Discusses pixel sensors ...

Design and assessment of a 6 ps-resolution time-to-digital converter with 5 MGy gamma-dose tolerance for nuclear instrumentation

Energy Technology Data Exchange (ETDEWEB)

Cao, Y. [ESAT-MICAS Div., Katholieke Universiteit Leuven, B-3001 Heverlee (Belgium); SCK.CEN, Belgian Nuclear Research Centre, B-2400 Mol (Belgium); Leroux, P. [ESAT-MICAS Div., Katholieke Universiteit Leuven, B-3001 Heverlee (Belgium); ICT-RELIC Div., Katholieke Hogeschool Kempen, B-2440 Geel (Belgium); De Cock, W. [SCK.CEN, Belgian Nuclear Research Centre, B-2400 Mol (Belgium); Steyaert, M. [ESAT-MICAS Div., Katholieke Universiteit Leuven, B-3001 Heverlee (Belgium)

2011-07-01

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. In order to realize a TDC with picosecond time resolution as well as multi MGy gamma-dose radiation tolerance, a novel multi-stage noise-shaping (MASH) delta-sigma ({Delta}{Sigma}) TDC structure is proposed. The converter, implemented in 0.13 {mu}m, achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the over sampling ratio (OSR) is 250. The TDC core consumes only 1.7 mW, and occupies an area of 0.11 mm{sup 2}. Owing to the usage of circuit level radiation hardened-by-design techniques, such as passive RC oscillators and constant-g{sub m} biasing, the TDC exhibits enhanced radiation tolerance. At a low dose rate of 1.2 kGy/h, the frequency of the counting clock in the TDC remains constant up to at least 160 kGy. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the TDC still achieves a time resolution of 10.5 ps with an OSR of 250. (authors)

New technologies for radiation-hardening analog to digital converters

International Nuclear Information System (INIS)

Gauthier, M.K.

1982-12-01

Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years

New technologies for radiation-hardening analog to digital converters

Science.gov (United States)

Gauthier, M. K.

1982-01-01

Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years.

Nonlinearities in SC Delta-Sigma A/D Converters

DEFF Research Database (Denmark)

Steensgaard-Madsen, Jesper

1998-01-01

The effects of using nonlinear low-gain opamps in switched-capacitor delta-sigma modulators are analyzed. Using unconventional topologies, the state variables are made essentially uncorrelated with the input signal, hence opamp nonlinearity will cause very little harmonic distortion. Nonlinearity...

Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

CERN Document Server

Morgado, Alonso; Rosa, José M

2012-01-01

This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called multistandard transceiver chipsets, integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.   This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview...

Large-scale digitizer system, analog converters

International Nuclear Information System (INIS)

Althaus, R.F.; Lee, K.L.; Kirsten, F.A.; Wagner, L.J.

1976-10-01

Analog to digital converter circuits that are based on the sharing of common resources, including those which are critical to the linearity and stability of the individual channels, are described. Simplicity of circuit composition is valued over other more costly approaches. These are intended to be applied in a large-scale processing and digitizing system for use with high-energy physics detectors such as drift-chambers or phototube-scintillator arrays. Signal distribution techniques are of paramount importance in maintaining adequate signal-to-noise ratio. Noise in both amplitude and time-jitter senses is held sufficiently low so that conversions with 10-bit charge resolution and 12-bit time resolution are achieved

The RHIC general purpose multiplexed analog to digital converter system

International Nuclear Information System (INIS)

Michnoff, R.

1995-01-01

A general purpose multiplexed analog to digital converter system is currently under development to support acquisition of analog signals for the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory. The system consists of a custom intelligent VME based controller module (V113) and a 14-bit 64 channel multiplexed A/D converter module (V114). The design features two independent scan groups, where one scan group is capable of acquiring 64 channels at 60 Hz, concurrently with the second scan group acquiring data at an aggregate rate of up to 80 k samples/second. An interface to the RHIC serially encoded event line is used to synchronize acquisition. Data is stored in a circular static RAM buffer on the controller module, then transferred to a commercial VMEbus CPU board and higher level workstations for plotting, report Generation, analysis and storage

Superconducting bandpass delta-sigma modulator

International Nuclear Information System (INIS)

Bulzacchelli, J.F.; Lee, H.-S.; Misewich, J.A.; Ketchen, M.B.

1999-01-01

Bandpass delta-sigma modulators digitize narrowband signals with high dynamic range and linearity. The required sampling rate is only a few times higher than the centre frequency of the input. This paper presents a superconducting bandpass delta-sigma modulator for direct analogue-to-digital conversion of RF signals in the GHz range. The input signal is capacitively coupled to one end of a microstrip transmission line, and a single flux quantum balanced comparator quantizes the current flowing out of the other end. Quantization noise is suppressed at the quarter-wave resonance of the transmission line (about 2 GHz in our design). Circuit performance at a 20 GHz sampling rate has been studied with several long JSIM simulations. Full-scale (FS) input sensitivity is 20 mV (rms), and in-band noise is -53 dBFS and -57 dBFS over bandwidths of 39 MHz and 19.5 MHz, respectively. In-band intermodulation distortion is better than -69 dBFS. (author)

Time-Interleaved Analog to Digital Converters

NARCIS (Netherlands)

Louwsma, S.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

2010-01-01

This book describes the research carried out by our PhD student Simon Louwsma at the University of Twente, The Netherlands in the field of high-speed Analogto- Digital (AD) converters. AD converters are crucial circuits for modern systems where information is stored or processed in digital form. Due

Resonant Tunneling Analog-To-Digital Converter

Science.gov (United States)

Broekaert, T. P. E.; Seabaugh, A. C.; Hellums, J.; Taddiken, A.; Tang, H.; Teng, J.; vanderWagt, J. P. A.

1995-01-01

As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.

All-optical analog-to-digital converter based on Kerr effect in photonic crystal

Science.gov (United States)

Jafari, Dariush; Nurmohammadi, Tofiq; Asadi, Mohammad Javad; Abbasian, Karim

2018-05-01

In this paper, a novel all-optical analog-to-digital converter (AOADC) is proposed and simulated for proof of principle. This AOADC is designed to operate in the range of telecom wavelength (1550 nm). A cavity made of nonlinear Kerr material in photonic crystal (PhC), is designed to achieve an optical analog-to-digital conversion with 1 Tera sample per second (TS/s) and the total footprint of 42 μm2 . The simulation is done using finite-difference time domain (FDTD) method.

8-bit serial-parallel analog-to-digital converter for fast transient recorder

International Nuclear Information System (INIS)

Kulka, Z.; Nadachowski, M.; Zimek, Z.

1990-08-01

An 8-bit serial-parallel analog-to-digital converter with a sampling frequency 5 MHz is described. The most important circuits of the device are described and parameters are given. The converter is a central part of a transient recorder type TR-1 designed for recording pulse waveforms in measurements of the kinetics of chemical reactions which are radiation-induced using an electron linear accelerator. 9 refs., 9 figs. (author)

Circuit with a successive approximation analog to digital converter

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2011-01-01

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and

Circuit with a successive approximation analog to digital converter

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2010-01-01

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and

A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters

DEFF Research Database (Denmark)

Nielsen, Jannik Hammel; Bruun, Erik

2003-01-01

In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power...... bits performance. Expected power consumption for the prototype is approx. 170 μW....

17 bit 4.35 mW 1 kHz Delta Sigma ADC and 256-to-1 multiplexer for remote handling instrumentation equipment

Energy Technology Data Exchange (ETDEWEB)

Verbeeck, Jens, E-mail: jens.verbeeck@esat.kuleuven.be [KU Leuven, Department ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); KH Kempen University College, IBW-RELIC, Kleinhoefstraat 4, 2440 Geel (Belgium); Van Uffelen, Marco [Fusion for Energy, c/Josep, n° 2, Torres Diagonal Litoral, Ed. B3, 08019 Barcelona (Spain); Steyaert, Michiel [KU Leuven, Department ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Leroux, Paul [KU Leuven, Department ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); KH Kempen University College, IBW-RELIC, Kleinhoefstraat 4, 2440 Geel (Belgium)

2013-10-15

Highlights: ► We present a radiation hard 17 bit-1 kHz 4.35 mW Delta Sigma ADC. ► A radiation tolerant 256-to-1 multiplexer is shown. ► We propose a generic radiation tolerant ASIC for use in an instrumentation link. ► The ASIC can interface more than hundred pressure or resistive sensors. ► All building blocks have a simulated radiation tolerance of more than 1 MGy. -- Abstract: A radiation tolerant Delta-Sigma Analog-to-Digital Converter (ADC) and multiplexer is presented. The design features a 1.5 V, 17 bit ADC consuming 4.35 mW at a sample frequency of 1 MHz. The ADC features a bandwidth of 1 kHz and utilizes a Correlated Double Sampling technique (CDS) to remove offset and 1/f noise. The circuit maintains its 17 bit resolution upon a simulated radiation dose exceeding 1 MGy and varying temperatures between 0 °C and 85 °C. Next a multiplexer is presented. It can multiplex 256 channels at a clock frequency of 128 MHz or has a data throughput of 256 MSample/s. In addition the bit period of the multiplexer varies less then 1.5% due to the influence of temperature or radiation, which proves the temperature and radiation tolerance.

Real-time compression of analog-to-digital converter outputs

International Nuclear Information System (INIS)

Okumura, Haruhiko

1997-01-01

We describe a fast lossless data compression algorithm suitable for digitized data taken at regular time intervals, such as outputs from analog-to-digital converters (ADCs). It is designed on the assumptions that the present value can be predicted approximately from the past values, and that the distribution of the prediction error is approximately Gaussian with zero mean and small and slowly changing standard deviation. Unlike many offline compression tools such as LHA and gzip, our algorithm does not need future values to encode the present value. This property is important for real-time transmission of compressed data on the network. The algorithm is to be integrated into our data acquisition system for the Large Helical Device (LHD) experiments at the National Institute for Fusion Science (NIFS). (author)

Time-to-digital converters

CERN Document Server

Henzler, Stephan

2010-01-01

This text covers the fundamentals of time-to-digital converters on analog and digital conversion principles. It includes a theoretical investigation into quantization, linearity, noise and variability, and it details a range of advanced TDC architectures.

FPGA implementation of a single-input fuzzy logic controller for boost converter with the absence of an external analog-to-digital converter

DEFF Research Database (Denmark)

Taeed, Fazel; Salam, Z.; Ayob, S.

2012-01-01

converter (ADC). Instead, a simple analog-to-digital conversion scheme is implemented using the FPGA itself. Due to the simplicity of the SIFLC algorithm and the absence of an external ADC, the overall implementation requires only 408 logic elements and five input-output pins of the FPGA.......) and applied on a 50-W boost converter. The SIFLC is compared to the proportional-integral controller; the simulation and practical results indicate that SIFLC exhibits excellent performance for step load and input reference changes. Another feature of this work is the absence of an external analog-to-digital...

Radiation-hard analog-to-digital converters for space and strategic applications

Science.gov (United States)

Gauthier, M. K.; Dantas, A. R. V.

1985-01-01

During the course of the Jet Propulsion Laboratory's program to study radiation-hardened analog-to-digital converters (ADCs), numerous milestones have been reached in manufacturers' awareness and technology development and transfer, as well as in user awareness of these developments. The testing of ADCs has also continued with twenty different ADCs from seven manufacturers, all tested for total radiation dose and three tested for neutron effects. Results from these tests are reported.

Design of a 12-bit 80MS/s pipeline analog-to-digital converter for PLC-VDSL applications

Science.gov (United States)

Ruiz-Amaya, Jesus; Delgado-Restituto, Manuel; Fernandez-Bootello, Juan F.; de la Rosa, Jose M.

2005-06-01

This paper describes the design of a 12-bit 80MS/s pipeline Analog-to-Digital converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation, synthesis and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is based on a 10-stage pipeline preceded by a sample/hold with bootstrapping technique. Each stage gives 1.5 effective bits, except for the first one which provides 2.5 effective bits to improve linearity. The Analog-to-Digital architecture uses redundant bits for digital correction, it is planned to be implemented without using calibration and employs a subranging pipeline look-ahead technique to increase speed. Substrate biased MOSFETs in the depletion region are used as capacitors, linearized by a series compensation. Simulation results show that the Multi-Tone Power Ratio is higher than 56dB for several DMT test signals and the estimated Signal-to-Noise Ratio yield is supposed to be better than 62 dB from DC to Nyquist frequency. The converter dissipates less than 150mW from a 3.3V supply and occupies less than 4 mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.

Multisensor transducer based on a parallel fiber optic digital-to-analog converter

Directory of Open Access Journals (Sweden)

Grechishnikov Vladimir

2017-01-01

Full Text Available Considered possibility of creating a multisensory information converter (MSPI based on new fiber-optic functional element-digital-to-analog (DAC fiber optic converter. The use of DAC fiber-optic provides jamming immunity combined with low weight and cost of indicators .Because of that MSPI scheme was developed based on parallel DAC fiber-optic (Russian Federation Patent 157416. We came up with an equation for parallel DAC fiber-optic. An eleborate general mathematical model of the proposed converter. Developed a method for reducing conversion errors by placing the DAC transfer function between i and i + 1 ADC quantization levels. By using this model it allows you to obtain reliable information about the technical capabilities of a converter without the need for costly experiments.

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-{mu}m CMOS technology

Energy Technology Data Exchange (ETDEWEB)

Yu Jinshan; Zhang Ruitao; Zhang Zhengping; Wang Yonglu; Zhu Can; Zhang Lei; Yu Zhou; Han Yong, E-mail: yujinshan@yeah.net [National Laboratory of Analog IC' s, Chongqing 400060 (China)

2011-01-15

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-{mu}m CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input. (semiconductor integrated circuits)

Process and circuiting arrangement for the conversion of analog signals to digital signals and digital signals to analog signals

International Nuclear Information System (INIS)

Wintzer, K.

1977-01-01

Process for analog-to-digital and digital-to-analog conversion in telecommunication systems whose outstations each have an analog transmitter and an analog receiver. The invention illustrates a method of reducing the power demand of the converters at times when no conversion processes take place. (RW) [de

Effects of Analog-to-Digital Converter Nonlinearities on Radar Range-Doppler Maps

Energy Technology Data Exchange (ETDEWEB)

Doerry, Armin Walter [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Dubbert, Dale F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Tise, Bertice L. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2014-07-01

Radar operation, particularly Ground Moving Target Indicator (GMTI) radar modes, are very sensitive to anomalous effects of system nonlinearities. These throw off harmonic spurs that are sometimes detected as false alarms. One significant source of nonlinear behavior is the Analog to Digital Converter (ADC). One measure of its undesired nonlinearity is its Integral Nonlinearity (INL) specification. We examine in this report the relationship of INL to GMTI performance.

A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

International Nuclear Information System (INIS)

Yang Weidong; Pu Jie; Zhang Ruitao; Chen Chao; Zang Jiandong; Li Tiehu; Luo Pu

2015-01-01

This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18 μm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB and INL less than ±4.3 LSB after the chip is calibrated. (paper)

Adaptive Reference Levels in a Level-Crossing Analog-to-Digital Converter

Directory of Open Access Journals (Sweden)

Andrew C. Singer

2008-11-01

Full Text Available Level-crossing analog-to-digital converters (LC ADCs have been considered in the literature and have been shown to efficiently sample certain classes of signals. One important aspect of their implementation is the placement of reference levels in the converter. The levels need to be appropriately located within the input dynamic range, in order to obtain samples efficiently. In this paper, we study optimization of the performance of such an LC ADC by providing several sequential algorithms that adaptively update the ADC reference levels. The accompanying performance analysis and simulation results show that as the signal length grows, the performance of the sequential algorithms asymptotically approaches that of the best choice that could only have been chosen in hindsight within a family of possible schemes.

High-Performance Data Converters

DEFF Research Database (Denmark)

Steensgaard-Madsen, Jesper

-resolution internal D/A converters are required. Unit-element mismatch-shaping D/A converters are analyzed, and the concept of mismatch-shaping is generalized to include scaled-element D/A converters. Several types of scaled-element mismatch-shaping D/A converters are proposed. Simulations show that, when implemented...... in a standard CMOS technology, they can be designed to yield 100 dB performance at 10 times oversampling. The proposed scaled-element mismatch-shaping D/A converters are well suited for use as the feedback stage in oversampled delta-sigma quantizers. It is, however, not easy to make full use of their potential......-order difference of the output signal from the loop filter's first integrator stage. This technique avoids the need for accurate matching of analog and digital filters that characterizes the MASH topology, and it preserves the signal-band suppression of quantization errors. Simulations show that quantizers...

SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

Science.gov (United States)

Gauthier, M. K.; Perret, J.; Evans, K. C.

1981-01-01

The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

High Performance Ultra Low-Power ADCs and DACs, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The objective of the Phase-I research is to design a multi-GHz high bandwidth Delta Sigma Analog-to-Digital and Digital-to-Analog converter using a deep sub-micron...

Connect high speed analog-digital converter with EPICS based on LabVIEW

International Nuclear Information System (INIS)

Wang Wei; Chi Yunlong

2008-01-01

This paper introduce a method to connect high speed analog-digital converter (ADC212/100) with EPICS on Windows platform using LabVIEW. We use labVIEW to communicate with the converter, then use interface sub-VIs between LabVIEW and EPICS to access the EPICS IOC by Channel Access (CA). For the easy use graph programming language of LabVIEW, this method could shorten the develop period and reduce manpower cost. (authors)

Modified Polar Sigma-Delta Transmitter for Multiradio Applications

Directory of Open Access Journals (Sweden)

Maršálek Roman

2010-01-01

Full Text Available Radio transmitters capable of transforming variable envelope signals into constant envelope signals can be associated with high-efficiency switched mode power amplifiers. One of the techniques providing this conversion is Polar Sigma-Delta ( architecture. This approach provides efficient solution for high-dynamic signals, and, moreover, it offers flexibility in a multiradio environment. The overall concept of the polar transmitter is presented here along with novel modifications and improvements. Namely, when recombining the envelope and the phase signals, it is suggested to replace the analog mixing by a digital mixing. The impact of a frequency synthesizer with a switched loop bandwidth and its imperfections on the overall polar architecture is investigated as well. The Mobile WiMAX standard has been chosen for validation due to very high requirements in terms of power dynamics and the variable channel bandwidth. Simulation results are presented in this paper, and advantages and drawbacks of this novel approach are pointed here as well.

Design of a 12-bit 80-MS/s CMOS digital-to-analog converter for PLC-VDSL applications

Science.gov (United States)

Ruiz-Amaya, Jesus; Delgado-Restituto, Manuel; Fernandez-Bootello, J. Francisco; de la Rosa, Jose M.

2005-06-01

This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is segmented in a unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distribute in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and it is supposed to be better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.

A new 12-bit spectroscopy analog-to-digital converter type SAA intended for CAMAC acquisition systems

International Nuclear Information System (INIS)

Borsuk, S.; Kulka, Z.

1989-12-01

A new 12-bit spectroscopy analog-to-digital converter (ADC) type SAA (Successive Approximation type with channel width Averaging) intended for CAMAC acquisition systems is decsribed. ADC type SAA initiates new series of spectroscopy ADC's based on a binary-approximation method in which differential nonlinearity is corrected by a statistical channel width averaging method. The structure and principle of operation, as well as some circuit realizations and specifications of the new converter are described. 41 refs., 5 figs. (author)

Data Converter for Multistandard Mobile Phones

DEFF Research Database (Denmark)

Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

2004-01-01

This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...... Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures....... The entire ADC consumes about 5.5 mW and occupies an active area of about 0.36 mm(2). A test circuit has been developed and fabricated and measurements show that both the required programmability and the required performance can be obtained using the proposed configurations....

Mismatch-Shaping Serial Digital-to-Analog Converter

DEFF Research Database (Denmark)

Steensgaard-Madsen, Jesper; Moon, Un-Ku; Temes, Gabor C.

1999-01-01

A simple but accurate pseudo-passive mismatch-shaping D/A converter is described. A digital state machine is used to control the switching sequence of a symmetric two-capacitor network that performs the D/A conversion. The error caused by capacitor mismatch is uncorrelated with the input signal...

Design and assessment of a 6 ps-resolution time-to-digital converter with 5 MGy gamma-dose tolerance for nuclear instrumentation

International Nuclear Information System (INIS)

Cao, Y.; Leroux, P.; De Cock, W.; Steyaert, M.

2011-01-01

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. In order to realize a TDC with picosecond time resolution as well as multi MGy gamma-dose radiation tolerance, a novel multi-stage noise-shaping (MASH) delta-sigma (ΔΣ) TDC structure is proposed. The converter, implemented in 0.13 μm, achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the over sampling ratio (OSR) is 250. The TDC core consumes only 1.7 mW, and occupies an area of 0.11 mm 2 . Owing to the usage of circuit level radiation hardened-by-design techniques, such as passive RC oscillators and constant-g m biasing, the TDC exhibits enhanced radiation tolerance. At a low dose rate of 1.2 kGy/h, the frequency of the counting clock in the TDC remains constant up to at least 160 kGy. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the TDC still achieves a time resolution of 10.5 ps with an OSR of 250. (authors)

A Calibration Method for Nonlinear Mismatches in M-Channel Time-Interleaved Analog-to-Digital Converters Based on Hadamard Sequences

Directory of Open Access Journals (Sweden)

Husheng Liu

2016-11-01

Full Text Available The time-interleaved analog-to-digital converter (TIADC is an architecture used to achieve a high sampling rate and high dynamic performance. However, estimation and compensation methods are required to maintain the dynamic performance of the constituent analog-to-digital converters (ADCs due to channel mismatches. This paper proposes a blind adaptive method to calibrate the nonlinear mismatches in M-channel TIADCs (M-TIADCs. The nonlinearity-induced error signal is reconstructed by the proposed multiplier Hadamard transform (MHT structure, and the nonlinear parameters are estimated by the filtered-X least-mean square (FxLMS algorithm. The performance of cascade calibration is also analyzed. The numerical simulation results show that the proposed method consumes much less hardware resources while maintaining the calibration performance.

Proposition of a scheme for adaptive/intelligent analog-to-digital converters

International Nuclear Information System (INIS)

Vaidya, P.P.; Kataria, S.K.

2001-01-01

The paper proposes design of a new class of Analog to Digital Converters (ADC's) which we call as Intelligent ADC's with moving resolution. Unlike presently available ADC's which are designed for specific range of applications and give fixed resolution and conversion time, the intelligent ADC's described here can adjust their resolution during the process of conversion, depending upon nature of input signal to make optimum use of the hard-ware. It is possible to use an intelligent ADC to give resolution ranging from 8 bit to 16 bit and conversion time ranging from few nano sec. to few micro secs. These ADC's have significant advantages over conventional ones when used for nuclear pulse spectroscopy as well as for process control applications. (author)

Efficiency and hardware comparison of analog control-based and digital control-based 70 W two-stage power factor corrector and DC-DC converters

DEFF Research Database (Denmark)

Török, Lajos; Munk-Nielsen, Stig

2011-01-01

A comparison of an analog and a digital controller driven 70 W two-stage power factor corrector converter is presented. Both controllers are operated in average current-mode-control for the PFC and peak current control for the DC-DC converter. Digital controller design and converter modeling...... is described. Results show that digital control can compete with the analog one in efficiency, PFC and THD....

Data input from an analog-to-digital converter into the M-6000 computer

International Nuclear Information System (INIS)

Kalashnikov, A.M.; Sheremet'ev, A.K.

1978-01-01

A device for spectrometric data input from the ADC-4096 into the M-6000 computer memory operating in the information storage regime is described. The input device made on integrated circuits coordinates signal levels of the fast response analog-to-digital converter and computer with the help of resistors and inverters. Besides, the input forms a strobe to trigger an increment channel used to record information into the computer memory. The use of the input device permits to get rid of the intermediate information storage in the analyzer memory and ensures fast response of the devices

Inverter-based successive approximation capacitance-to-digital converter

KAUST Repository

Omran, Hesham

2017-03-23

An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog- to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter- based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.

A 1.2-V 165-μW 0.29-mm² Multibit Sigma-Delta ADC for Hearing Aids Using Nonlinear DACs and With Over 91 dB Dynamic-Range

DEFF Research Database (Denmark)

Custódio, José R.; Goes, João; Paulino, Nuno

2013-01-01

This paper describes the design and experimental evaluation of a multibit Sigma-Delta (ΣΔ) modulator (ΣΔM) with enhanced dynamic range (DR) through the use of nonlinear digital-to-analog converters (DACs) in the feedback paths. This nonlinearity imposes a trade-off between DR and distortion, which...... in a 130 nm digital CMOS technology, which includes the proposed modulator with nonlinear DACs and a modulator with conventional linear DACs, for comparison purposes. The measured results show that the ΣΔM using nonlinear DACs achieves an enhancement of the DR around 8.4 dB (to 91.4 dB). Power dissipation...... and silicon area are about the same for the two cases. The performance achieved is comparable to that of the best reported multibit ΣΔ ADCs, with the advantage of occupying less silicon area (7.5 times lower area when compared with the most energy efficient ΣΔM)....

A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS

Directory of Open Access Journals (Sweden)

Koh Jinseok

2006-01-01

Full Text Available We present a discrete-time second-order multibit sigma-delta ADC that filters and decimates by two the input data samples. At the same time it provides gain control function in its input sampling stage. A 4-tap FIR switched capacitor (SC architecture was chosen for antialiasing filtering. The decimation-by-two function is realized using divided-by-two clock signals in the antialiasing filter. Antialiasing, gain control, and sampling functions are merged in the sampling network using SC techniques. This compact architecture allows operating the preceding blocks at twice the ADC's clock frequency, thus improving the noise performance of the wireless receiver channel and relaxing settling requirements of the analog building blocks. The presented approach has been validated and incorporated in a commercial single-chip Bluetooth radio realized in a 1.5 V 130 nm digital CMOS process. The measured antialiasing filtering shows better than 75 dB suppression at the folding frequency band edge. A 67 dB dynamic range was measured with a sampling frequency of 37.5MHz.

PIC microcontroller based external fast analog to digital converter to acquire wide-lined solid NMR spectra by BRUKER DRX and Avance-I spectrometers.

Science.gov (United States)

Koczor, Bálint; Rohonczy, János

2015-01-01

Concerning many former liquid or hybrid liquid/solid NMR consoles, the built in Analog-to-Digital Converters (ADCs) are incapable of digitizing the fids at sampling rates in the MHz range. Regarding both strong anisotropic interactions in the solid state and wide chemical shift dispersion nuclei in solution phase such as (195)Pt, (119)Sn, (207)Pb etc., the spectrum range of interest might be in the MHz range. As determining the informative tensor components of anisotropic NMR interactions requires nonlinear fitting over the whole spectrum including the asymptotic baseline, it is prohibited by low sampling rates of the ADCs. Wide spectrum width is also useful in solution NMR, since windowing of wide chemical shift ranges is avoidable. We built an external analog to digital converter with 10 MHz maximal sampling rate, which can work simultaneously with the built in ADC of the spectrometer. The ADC was tested on both Bruker DRX and Avance-I NMR consoles. In addition to the analog channels it only requires three external digital lines of the NMR console. The ADC sends data to PC via USB. The whole process is controlled by software written in JAVA which is implemented under TopSpin. Copyright © 2015 Elsevier Inc. All rights reserved.

Mixed Linear/Square-Root Encoded Single Slope Ramp Provides a Fast, Low Noise Analog to Digital Converter with Very High Linearity for Focal Plane Arrays

Science.gov (United States)

Wrigley, Christopher James (Inventor); Hancock, Bruce R. (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor)

2014-01-01

An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.

Delta-Sigma AD-Converters Practical Design for Communication Systems

CERN Document Server

Gaggl, Richard

2013-01-01

The emphasis of this book is on practical design aspects for broadband A/D converters for communication systems. The embedded designs are employed for transceivers in the field of ADSL solutions and WLAN applications. An area- and power-efficient realization of a converter is mandatory to remain competitive in the market. The right choice for the converter topology and architecture needs to be done very carefully to result in a competitive FOM. The book begins with a brief overview of basic concepts about ADSL and WLAN to understand the ADC requirements. At architectural level, issues on different modulator topologies are discussed employing the provided technology node. The design issues are pointed out in detail for modern digital CMOS technologies, beginning with 180nm followed by 130nm and going down to 65nm feature size. Beside practical aspects, challenges to mixed-signal design level are addressed to optimize the converters in terms of consumed chip area, power consumption and design for high yield in ...

Analogue demonstration of a high temperature superconducting sigma-delta modulator with 27 GHz sampling

Energy Technology Data Exchange (ETDEWEB)

Forrester, M.G.; Hunt, B.D.; Miller, D.L.; Talvacchio, J.; Young, R.M. [Northrop Grumman Science and Technology Center, Pittsburgh, PA 15235-5098 (United States)

1999-11-01

We have successfully fabricated and tested a high temperature superconducting (HTS) sigma-delta modulator for analogue-to-digital conversion. This is the first demonstration of a GHz sampling A-to-D in HTS. The 15-junction single-flux-quantum (SFQ) circuit, fabricated using an epitaxial multilayer HTS process with YBCO/Co-YBCO/YBCO edge junctions, was internally clocked at 27 GHz and used to convert a 5.01 MHz signal. The modulator demonstrated a spur-free dynamic range of more than 75 dB. Two-tone measurements with 5.01 MHz and 5.51 MHz signals demonstrated third-order intermodulation products to be lower than -59 dBc. Demonstration of a functional HTS modulator represents a significant milestone in the development of high dynamic range ADCs suitable for such applications as surveillance radar. (author)

Digitalization of highly precise fluxgate magnetometers

DEFF Research Database (Denmark)

Cerman, Ales; Kuna, A.; Ripka, P.

2005-01-01

This paper describes the theory behind all three known ways of digitalizing the fluxgate magnetometers: analogue magnetometers with digitalized output using high resolution ADC, application of the delta-sigma modulation to the sensor feedback loop and fully digital signal detection. At present time...... the Delta-Sigma ADCs are mostly used for the digitalization of the highly precise fluxgate magnetorneters. The relevant part of the paper demonstrates some pitfalls of their application studied during the design of the magnetometer for the new Czech scientific satellite MIMOSA. The part discussing...... the application of the A-E modulation to the sensor feedback loop theoretically derives the main advantage of this method-increasing of the modulation order and shows its real potential compared to the analog magnetometer with consequential digitalization. The comparison is realized on the modular magnetometer...

Low-power low-noise analog circuits for on-focal-plane signal processing of infrared sensors

Science.gov (United States)

Pain, Bedabrata; Mendis, Sunetra K.; Schober, Robert C.; Nixon, Robert H.; Fossum, Eric R.

1993-10-01

On-focal-plane signal processing circuits for enhancement of IR imager performance are presented. To enable the detection of high background IR images, an in-pixel current-mode background suppression scheme is presented. The background suppression circuit consists of a current memory placed in the feedback loop of a CTIA and is designed for a thousand-fold suppression of the background flux, thereby easing circuit design constraints, and assuring BLIP operation even with detectors having large response non-uniformities. For improving the performance of low-background IR imagers, an on-chip column-parallel analog-to-digital converter (ADC) is presented. The design of a 10-bit ADC with 50 micrometers pitch and based on sigma-delta ((Sigma) -(Delta) ) modulation is presented. A novel IR imager readout technique featuring photoelectron counting in the unit cell is presented for ultra-low background applications. The output of the unit cell is a digital word corresponding to the incident flux density and the readout is noise free. The design of low-power (noise, high-gain (> 100,000), small real estate (60 micrometers pitch) self-biased CMOS amplifiers required for photon counting are presented.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

Science.gov (United States)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Analog-to-digital conversion using custom CMOS analog memory for the EOS time projection chamber

International Nuclear Information System (INIS)

Lee, K.L.; Arthur, A.A.; Jones, R.W.; Matis, H.S.; Nakamura, M.; Kleinfelder, S.A.; Ritter, H.G.; Wienman, H.H.

1990-01-01

This paper describes the multiplexing scheme of custom CMOS analog memory integrated circuits, 16 channels x 256 cells, into analog to digital converters (ADC's) to handle 15,360 signal channels of a time projection, chamber detector system. Primary requirements of this system are high density, low power and large dynamic range. The analog memory device multiplexing scheme was designed to digitize the information stored in the memory cells. The digitization time of the ADC's and the settling times for the memory unit were carefully interleaved to optimize the performance and timing during the multiplexing operation. This kept the total number of ADC's, a costly and power dissipative component, to an acceptable minimum

10-bit rapid single flux quantum digital-to-analog converter for ac voltage standard

International Nuclear Information System (INIS)

Maezawa, M; Hirayama, F

2008-01-01

Digital-to-analog (D/A) converters based on rapid single flux quantum (RSFQ) technology are under development for ac voltage standard applications. We present design and test results on a prototype 10-bit version integrated on a single chip. The 10-bit chip includes over 6000 Josephson junctions and consumes a bias current exceeding 1 A. To reduce the effects of the high bias current on circuit operation, a custom design method was employed in part and large circuit blocks were divided into smaller ones. The 10-bit chips were fabricated and tested at low speed. The test results suggested that our design approach could manage large bias currents on the order of 1 A per chip

Fast collimated neutron flux measurement using stilbene scintillator and flashy analog-to-digital converter in JT-60U

International Nuclear Information System (INIS)

Ishikawa, M.; Itoga, T.; Okuji, T.; Nakhostin, M.; Shinohara, K.; Hayashi, T.; Sukegawa, A.; Baba, M.; Nishitani, T.

2006-01-01

A line-integrated neutron emission profile is routinely measured using the radial neutron collimator system in JT-60U tokamak. Stilbene neuron detectors (SNDs), which combine a stilbene organic crystal scintillation detector (SD) with an analog neutron-gamma pulse shape discrimination (PSD) circuit, have been used to measure collimated neutron flux. Although the SND has many advantages as a neutron detector, the maximum count rate is limited up to ∼1x10 5 counts/s due to the analog PSD circuit. To overcome this issue, a digital signal processing system (DSPS) using a flash analog-to-digital converter (Acqiris DC252, 8 GHz, 10 bits) has been developed at Cyclotron and Radioisotope Center in Tohoku University. In this system anode signals from photomultiplier of the SD are directory stored and digitized. Then, the PSD between neutrons and gamma rays is performed using software. The DSPS has been installed in the vertical neutron collimator system in JT-60U and applied to deuterium experiments. It is confirmed that the PSD is sufficiently performed and collimated neutron flux is successfully measured with count rate up to ∼5x10 5 counts/s without the effect of pileup of detected pulses. The performance of the DSPS as a neutron detector, which supersedes the SND, is demonstrated

Continuous time sigma delta ADC design and non-idealities analysis

International Nuclear Information System (INIS)

Yuan Jun; Chen Zhenhai; Yang Yintang; Zhang Zhaofeng; Wu Jun; Wang Chao; Qian Wenrong

2011-01-01

A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed non-idealities analysis (excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch) is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. Athird-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply. (semiconductor integrated circuits)

Design of integrated all optical digital to analog converter (DAC) using 2D photonic crystals

Science.gov (United States)

Moniem, Tamer A.; El-Din, Eman S.

2017-11-01

A novel design of all optical 3 bit digital to analog (DAC) converter will be presented in this paper based on 2 Dimension photonic crystals (PhC). The proposed structure is based on the photonic crystal ring resonators (PCRR) with combining the nonlinear Kerr effect on the PCRR. The total size of the proposed optical 3 bit DAC is equal to 44 μm × 37 μm of 2D square lattice photonic crystals of silicon rods with refractive index equal to 3.4. The finite different time domain (FDTD) and Plane Wave Expansion (PWE) methods are used to back the overall operation of the proposed optical DAC.

Sigma-delta modulator modeling analysis and design

International Nuclear Information System (INIS)

Ge Binjie; Wang Xin'an; Zhang Xing; Feng Xiaoxing; Wang Qingqin

2010-01-01

This paper introduces a new method for SC sigma-delta modulator modeling. It studies the integrator's different equivalent circuits in the integrating and sampling phases. This model uses the OP-AMP input pair's tail current (I 0 ) and overdrive voltage (v on ) as variables. The modulator's static and dynamic errors are analyzed. A group of optimized I 0 and v on for maximum SNR and power x area ratio can be obtained through this model. As examples, a MASH21 modulator for digital audio and a second order modulator for RFID baseband are implemented and tested, and they can achieve 91 dB and 72 dB respectively, which verifies the modeling and design criteria. (semiconductor integrated circuits)

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

Directory of Open Access Journals (Sweden)

Mostafa Chakir

2017-01-01

Full Text Available The CMOS Monolithic Active Pixel Sensor (MAPS for the International Linear Collider (ILC vertex detector (VXD expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC. This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor.

Science.gov (United States)

Chakir, Mostafa; Akhamal, Hicham; Qjidaa, Hassan

2017-01-01

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18  μ m CMOS process with a pixel pitch of 35  μ m. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76  μ m 2 . The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/-0.0787 LSB and 0.0811/-0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

LDRD final report: photonic analog-to-digital converter (ADC) technology; TOPICAL

International Nuclear Information System (INIS)

Bowers, M; Deri, B; Haigh, R; Lowry, M; Sargis, P; Stafford, R; Tong, T

1999-01-01

We report on an LDRD seed program of novel technology development (started by an FY98 Engineering Tech-base project) that will enable extremely high-fidelity analog-to-digital converters for a variety of national security missions. High speed (l0+ GS/s ), high precision (l0+ bits) ADC technology requires extremely short aperture times ((approx)1ps ) with very low jitter requirements (sub 10fs ). These fundamental requirements, along with other technological barriers, are difficult to realize with electronics: However, we outline here, a way to achieve these timing apertures using a novel multi-wavelength optoelectronic short-pulse optical source. Our approach uses an optoelectronic feedback scheme with high optical Q to produce an optical pulse train with ultra-low jitter ( sub 5fs) and high amplitude stability ( and lt;10(sup 10)). This approach requires low power and can be integrated into an optoelectronic integrated circuit to minimize the size. Under this seed program we have demonstrated that the optical feedback mechanism can be used to generate a high Q resonator. This has reduced the technical risk for further development, making it an attractive candidate for outside funding

A digital silicon photomultiplier with multiple time-to-digital converters

Energy Technology Data Exchange (ETDEWEB)

Garutti, Erika [University Hamburg (Germany); Silenzi, Alessandro [DESY, Hamburg (Germany); Xu, Chen [DESY, Hamburg (Germany); University Hamburg (Germany)

2013-07-01

A silicon photomultiplier (SiPM) with pixel level signal digitization and column-wise connected time-to-digital converters (TDCs) has been developed for an endoscopic Positron Emission Tomography (PET) detector. A digital SiPM has pixels consist of a single photon avalanche diode (SPAD) and circuit elements to optimize overall dark counts and temporal response. Compared with conventional analog SiPM, digital SiPM's direct signal route from SPAD to TDC improves single photon time resolution. In addition, using multiple TDCs can perform the statistical estimation of the time-of-arrival in multiple photon detection case such as readout of scintillation crystals. Characterization measurements of the prototype digital SiPM and a Monte-Carlo simulation to predict the timing performance of the PET detector are shown.

Rad-Hard Sigma-Delta 3-channel ADC for Fluxgate Magnetometers, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The proposed project aims to develop a multi-channel analog to digital converter (ADC) required for a fluxgate magnetometer (EPD) employed on NASA's planetary...

Design rules for superconducting analog-digital transducers; Entwurfsregeln fuer Supraleitende Analog-Digital-Wandler

Energy Technology Data Exchange (ETDEWEB)

Haddad, Taghrid

2015-05-29

This Thesis is a contribution for dimensioning aspects of circuits designs in superconductor electronics. Mainly superconductor comparators inclusive Josephson comparators as well as QOJS-Comparators are investigated. Both types were investigated in terms of speed and sensitivity. The influence of the thermal noise on the decision process of the comparators represent in so called gray zone, which is analysed in this thesis. Thereby, different relations between design parameters were derived. A circuit model of the Josephson comparator was verified by experiments. Concepts of superconductor analog-to-digital converters, which are based on above called comparators, were investigated in detail. From the comparator design rules, new rules for AD-converters were derived. Because of the reduced switching energy, the signal to noise ratio (SNR) of the circuits is affected and therefore the reliability of the decision-process is affected. For special applications with very demanding requirements in terms of the speed and accuracy superconductor analog-to-digital converters offer an excellent performance. This thesis provides relations between different design paramenters and shows resulting trade-offs, This method is transparent and easy to transfer to other circuit topologies. As a main result, a highly predictive tool for dimensioning of superconducting ADC's is proved.

Broadband analog to digital conversion with spatial-spectral holography

International Nuclear Information System (INIS)

Babbitt, W. Randall; Neifeld, Mark A.; Merkel, Kristian D.

2007-01-01

A new approach to broadband photonic-assisted analog-to-digital converter (ADC) technology is proposed and analyzed. The core of the device is a spatial spectral holographic (SSH) material, which can directly record the signals of interest in the frequency domain. An SSH-ADC acts as a frequency-domain stretch processor, which leverages the high performance of conventional ADCs by converting high bandwidth input signals to low bandwidth output signals without loss of information. Analysis of a 10 GHz bandwidth SSH-ADC predicts that 10-bit performance can be achieved with currently available materials and components. SSH-ADC technology is scalable to bandwidths over 100 GHz with recently developed SSH materials. While the SSH-ADC is a transient digitizer, the spatial parallelism of SSH materials can be utilized to enable continuous digitization

Broadband analog to digital conversion with spatial-spectral holography

Energy Technology Data Exchange (ETDEWEB)

Babbitt, W. Randall [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States)]. E-mail: babbitt@physics.montana.edu; Neifeld, Mark A. [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States); Merkel, Kristian D. [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States)

2007-11-15

A new approach to broadband photonic-assisted analog-to-digital converter (ADC) technology is proposed and analyzed. The core of the device is a spatial spectral holographic (SSH) material, which can directly record the signals of interest in the frequency domain. An SSH-ADC acts as a frequency-domain stretch processor, which leverages the high performance of conventional ADCs by converting high bandwidth input signals to low bandwidth output signals without loss of information. Analysis of a 10 GHz bandwidth SSH-ADC predicts that 10-bit performance can be achieved with currently available materials and components. SSH-ADC technology is scalable to bandwidths over 100 GHz with recently developed SSH materials. While the SSH-ADC is a transient digitizer, the spatial parallelism of SSH materials can be utilized to enable continuous digitization.

Sigma-delta modulator modeling analysis and design

Energy Technology Data Exchange (ETDEWEB)

Ge Binjie; Wang Xin' an; Zhang Xing; Feng Xiaoxing; Wang Qingqin, E-mail: wangxa@szpku.edu.c [Key Laboratory of Integrated Microsystem Science and Engineering Applications, Shenzhen Graduate School of Peking University, Shenzhen 518055 (China)

2010-09-15

This paper introduces a new method for SC sigma-delta modulator modeling. It studies the integrator's different equivalent circuits in the integrating and sampling phases. This model uses the OP-AMP input pair's tail current (I{sub 0}) and overdrive voltage (v{sub on}) as variables. The modulator's static and dynamic errors are analyzed. A group of optimized I{sub 0} and v{sub on} for maximum SNR and power x area ratio can be obtained through this model. As examples, a MASH21 modulator for digital audio and a second order modulator for RFID baseband are implemented and tested, and they can achieve 91 dB and 72 dB respectively, which verifies the modeling and design criteria. (semiconductor integrated circuits)

Assessment of an Average Controller for a DC/DC Converter via Either a PWM or a Sigma-Delta-Modulator

Directory of Open Access Journals (Sweden)

R. Silva-Ortigoza

2014-01-01

Full Text Available Sliding mode control is a discontinuous control technique that is, by its nature, appropriate for controlling variable structure systems, such as the switch regulated systems employed in power electronics. However, when designing control laws based on the average models of these systems a modulator is necessary for their experimental implementation. Among the most widely used modulators in power electronics are the pulse width modulation (PWM and, more recently, the sigma-delta-modulator (Σ-Δ-modulator. Based on the importance of achieving an appropriate implementation of average control laws and the relevance of the trajectory tracking task in DC/DC power converters, for the first time, this research presents the assessment of the experimental results obtained when one of these controllers is implemented through either a PWM or a Σ-Δ-modulator to perform such a task. A comparative assessment based on the integral square error (ISE index shows that, at frequencies with similar efficiency, the Σ-Δ-modulator provides a better tracking performance for the DC/DC Buck converter. In this paper, an average control based on differential flatness was used to perform the experiments. It is worth mentioning that a different trajectory tracking controller could have been selected for this research.

Digital to Analog Converter Description

NARCIS (Netherlands)

van Tuijl, Adrianus Johannes Maria

2002-01-01

A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources (40-1, 40-2, 40-n), where n is the resolution required of the conversion. Preferably more than 2n current sources (40-1, 40-2, 40-n) are used. The order in which the sources (40-1,

Design and Simulation of Seido Buffer for Analog to Digital Converter (ADC) on Multichannel Analyzer (MCA) Application

International Nuclear Information System (INIS)

Harzawadi Hasim; Maslina Ibrahim; Nolida Yusop; Mohd Ashhar Khalid

2011-01-01

Most of our electronic equipment has buffer, thus this make buffer as one of importance in electronic gadget. This paper introduced Single Ended Input Differential Output (SEIDO) buffer to predict the bias at approximately 2.5 V. For this purpose, the input range between -1 mV to 4 V was implemented. The software used to cascade SEIDO buffer is called LTspice IV; an open source software developed by Linear Technology Incorporation. The component involve in this development was Operational Amplifier (OP AMP) AD826 from Analog Devices Incorporation, capacitor and resistor. Kirchhoffs Current Law and Kirchhoffs Voltage Law was applied to calculated voltage gain and biasing voltage. All design has been verified by LTspice IV. The result produced from simulation was between -0.3 V to 6.3 V with bias roughly at 2.5 V. These results prove that it was capable to drive Analog Digital Converter (ADC) that can subsequently apply for Multichannel Analyzer (MCA). (author)

Design of the 12-bit Delta-Sigma Modulator using SC Technique for Vibration Sensor Output Processing

Directory of Open Access Journals (Sweden)

M. Pavlik

2012-04-01

Full Text Available The work deals with the design of the 12-bit Delta-Sigma modulator using switched capacitors (SC technique. The modulator serves to vibration sensor output processing. The first part describes the Delta-Sigma modulator parameters definition. Results of the proposed topology ideal model were presented as well. Next, the Delta-Sigma modulator circuitry on the transistor level was done. The ONSemiconductor I2T100 0.7 um CMOS technology was used for design. Then, the Delta-Sigma modulator nonidealities were simulated and implemented into the MATLAB ideal model of the modulator. The model of real Delta-Sigma modulator was derived. Consequently, modulator coefficients were optimized. Finally, the corner analysis of the Delta-Sigma modulator with the optimized coefficients was simulated. The value of SNDR = 82.2 dB (ENOB = 13.4 bits was achieved.

Deep Cryogenic Low Power 24 Bits Analog to Digital Converter with Active Reverse Cryostat

Science.gov (United States)

Turqueti, Marcos; Prestemon, Soren; Albright, Robert

LBNL is developing an innovative data acquisition module for superconductive magnets where the front-end electronics and digitizer resides inside the cryostat. This electronic package allows conventional electronic technologies such as enhanced metal-oxide-semiconductor to work inside cryostats at temperatures as low as 4.2 K. This is achieved by careful management of heat inside the module that keeps the electronic envelop at approximately 85 K. This approach avoids all the difficulties that arise from changes in carrier mobility that occur in semiconductors at deep cryogenic temperatures. There are several advantages in utilizing this system. A significant reduction in electrical noise from signals captured inside the cryostat occurs due to the low temperature that the electronics is immersed in, reducing the thermal noise. The shorter distance that signals are transmitted before digitalization reduces pickup and cross-talk between channels. This improved performance in signal-to-noise rate by itself is a significant advantage. Another important advantage is the simplification of the feedthrough interface on the cryostat head. Data coming out of the cryostat is digital and serial, dramatically reducing the number of lines going through the cryostat feedthrough interface. It is important to notice that all lines coming out of the cryostat are digital and low voltage, reducing the possibility of electric breakdown inside the cryostat. This paper will explain in details the architecture and inner workings of this data acquisition system. It will also provide the performance of the analog to digital converter when the system is immersed in liquid helium, and in liquid nitrogen. Parameters such as power dissipation, integral non-linearity, effective number of bits, signal-to-noise and distortion, will be presented for both temperatures.

4-bit digital to analog converter using R-2R ladder and binary weighted resistors

Science.gov (United States)

Diosanto, J.; Batac, M. L.; Pereda, K. J.; Caldo, R.

2017-06-01

The use of a 4-bit digital-to-analog converter using two methods; Binary Weighted Resistors and R-2R Ladder is designed and presented in this paper. The main components that were used in constructing both circuits were different resistor values, operational amplifier (LM741) and single pole double throw switches. Both circuits were designed using MULTISIM software to be able to test the circuit for its ideal application and FRITZING software for the layout designing and fabrication to the printed circuit board. The implementation of both systems in an actual circuit benefits in determining and comparing the advantages and disadvantages of each. It was realized that the binary weighted circuit is more efficient DAC, having lower percentage error of 0.267% compared to R-2R ladder circuit which has a minimum of percentage error of 4.16%.

Adjustable Nyquist-rate System for Single-Bit Sigma-Delta ADC with Alternative FIR Architecture

Science.gov (United States)

Frick, Vincent; Dadouche, Foudil; Berviller, Hervé

2016-09-01

This paper presents a new smart and compact system dedicated to control the output sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma-delta (ΣΔ) modulator. This system dramatically improves the spectral analysis capabilities of power network analysers (power meters) by adjusting the ADC's sampling frequency to the input signal's fundamental frequency with a few parts per million accuracy. The trade-off between straightforwardness and performance that motivated the choice of the ADC's architecture are preliminary discussed. It particularly comes along with design considerations of an ultra-steep direct-form FIR that is optimised in terms of size and operating speed. Thanks to compact standard VHDL language description, the architecture of the proposed system is particularly suitable for application-specific integrated circuit (ASIC) implementation-oriented low-power and low-cost power meter applications. Field programmable gate array (FPGA) prototyping and experimental results validate the adjustable sampling frequency concept. They also show that the system can perform better in terms of implementation and power capabilities compared to dedicated IP resources.

Segmented correlation measurements on superconducting bandpass delta-sigma modulator with and without input tone

International Nuclear Information System (INIS)

Bulzacchelli, John F; Lee, Hae-Seung; Hong, Merit Y; Misewich, James A; Ketchen, Mark B

2003-01-01

Segmented correlation is a useful technique for testing a superconducting analogue-to-digital converter, as it allows the output spectrum to be estimated with fine frequency resolution even when data record lengths are limited by small on-chip acquisition memories. Previously, we presented segmented correlation measurements on a superconducting bandpass delta-sigma modulator sampling at 40.2 GHz under idle channel (no input) conditions. This paper compares the modulator output spectra measured by segmented correlation with and without an input tone. Important practical considerations of calculating segmented correlations are discussed in detail. Resolution enhancement by segmented correlation does reduce the spectral width of the input tone in the desired manner, but the signal power due to the input increases the variance of the spectral estimate near the input frequency, hindering accurate calculation of the in-band noise. This increased variance, which is predicted by theory, must be considered carefully in the application of segmented correlation. Methods for obtaining more accurate estimates of the quantization noise spectrum which are closer to those measured with no input are described

Digitalization and networking of analog simulators and portal images.

Science.gov (United States)

Pesznyák, Csilla; Zaránd, Pál; Mayer, Arpád

2007-03-01

Many departments have analog simulators and irradiation facilities (especially cobalt units) without electronic portal imaging. Import of the images into the R&V (Record & Verify) system is required. Simulator images are grabbed while portal films scanned by using a laser scanner and both converted into DICOM RT (Digital Imaging and Communications in Medicine Radiotherapy) images. Image intensifier output of a simulator and portal films are converted to DICOM RT images and used in clinical practice. The simulator software was developed in cooperation at the authors' hospital. The digitalization of analog simulators is a valuable updating in clinical use replacing screen-film technique. Film scanning and digitalization permit the electronic archiving of films. Conversion into DICOM RT images is a precondition of importing to the R&V system.

Doubling-resolution analog-to-digital conversion based on PIC18F45K80

Directory of Open Access Journals (Sweden)

Yueyang Yuan

2014-08-01

Full Text Available Aiming at the analog signal being converted into the digital with a higher precision, a method to improve the analog-to-digital converter (ADC resolution is proposed and described. Based on the microcomputer PIC18F45K80 in which the internal ADC modules are embedded, a circuit is designed for doubling the resolution of ADC. According to the circuit diagram, the mathematical formula for calculating this resolution is derived. The corresponding software and print circuit board assembly is also prepared. With the experiment, a 13 bit ADC is achieved based on the 12 bit ADC module predesigned in the PIC18F45K80.

Casscf/ci Calculations for First Row Transition Metal Hydrides - the TIH(4-PHI), VH(5-DELTA), CRH(6-SIGMA-PLUS), MNH(7-SIGMA-PLUS), FEH(4,6-DELTA) and NIH(2-DELTA) States

Science.gov (United States)

Walch, S. P.; Bauschlicher, C. W., Jr.

1983-04-01

Calculations are performed for the predicted ground states of TiH(4-phi), VH(5-delta), CrH(6-sigma-plus), MnH(7-sigma-plus), Fett(4,6-delta) and NiH(2-delta). For FeH both the 6-delta and 4-delta states are studied, since both are likely candidates for the ground state. The ground state symmetries are predicted based on a combination of atomic coupling arguments and coupling of 4s(2)3d(n) and 4s(1)3d(n+1) terms in the molecular system. Electron correlation is included by a CASSCF/CI (SD) treatment. The CASSCF includes near-degeneracy effects, while correlation of the 3d electrons in included at the CI level.

Double Modulation Scheme for Switching Mixers Controlled by Sigma-Delta Modulators

DEFF Research Database (Denmark)

Nielsen, Per Asbeck; Fallesen, Carsten

1998-01-01

. This modification can be carried out on a large variety of mixers including the above mentioned. Although the principle was meant to be used to down convert analog signals, the principle is general and can be used in digital circuits too. This paper verifies the new mixing scheme and compares it to the traditional...

Nyquist AD Converters, Sensor Interfaces, and Robustness Advances in Analog Circuit Design, 2012

CERN Document Server

Baschirotto, Andrea; Steyaert, Michiel

2013-01-01

This book is based on the presentations during the 21st workshop on Advances in Analog Circuit Design.  Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity.  This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.  Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format; Includes coverage of Nyquist A/D converters, capacitive sensor interfaces, reliability, variability, and connectivity.

Analog to digital conversion for nuclear spectrometry

International Nuclear Information System (INIS)

Carvalho, P.V.R. de.

1982-04-01

A study of the analog to digital conversion techniques for nuclear spectrometry is presented and the main design philosophies of nuclear ADC's are compared. Among them, the most suitable for the current Brazilian conditions, concerning the specifications and components avaiability is the one that employs a statistical correction of successive approximation converters. This technique is described in full detail. A prototype has been developed an tested for the practical demonstration of the theoretical conclusions. These tests was carried on nuclear spectrometry data aquisition system whose implementation is also described. (Author) [pt

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

Science.gov (United States)

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

Application of digital control techniques for satellite medium power DC-DC converters

Science.gov (United States)

Skup, Konrad R.; Grudzinski, Pawel; Nowosielski, Witold; Orleanski, Piotr; Wawrzaszek, Roman

2010-09-01

The objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter bases on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage mode stabilization that was implemented using VHDL. The described controllers are a classical digital PID controller and a bang-bang controller. The used converter for testing is a simple model of 5-20 W, 200 kHz buck power converter. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.

Digitalization and networking of analog simulators and portal images

Energy Technology Data Exchange (ETDEWEB)

Pesznyak, C.; Zarand, P.; Mayer, A. [Uzsoki Hospital, Budapest (Hungary). Inst. of Oncoradiology

2007-03-15

Background: Many departments have analog simulators and irradiation facilities (especially cobalt units) without electronic portal imaging. Import of the images into the R and V (Record and Verify) system is required. Material and Methods: Simulator images are grabbed while portal films scanned by using a laser scanner and both converted into DICOM RT (Digital Imaging and Communications in Medicine Radiotherapy) images. Results: Image intensifier output of a simulator and portal films are converted to DICOM RT images and used in clinical practice. The simulator software was developed in cooperation at the authors' hospital. Conclusion: The digitalization of analog simulators is a valuable updating in clinical use replacing screen-film technique. Film scanning and digitalization permit the electronic archiving of films. Conversion into DICOM RT images is a precondition of importing to the R and V system. (orig.)

Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

Directory of Open Access Journals (Sweden)

Al Al

2015-01-01

Full Text Available Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ-comparator, the encoder and the parallel input serial output (PISO register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

Detection of delta-ferrite to sigma transformation using metallographic techniques involving ferromagnetic colloid, color etching, and microprobe analysis

International Nuclear Information System (INIS)

Gray, R.J.; Sikka, V.K.; King, R.T.

1976-01-01

The mechanical properties of ferrite-containing austenitic stainless steel base metal and weldments are usually adversely affected by prolonged exposure to temperatures in the 482 to 900 0 C (900 to 1652 0 F) range. One cause of the property alteration is related to the transformation of relatively ductile delta-ferrite to less ductile sigma-phase. Attempts to identify sigma and delta-ferrite phases by color staining techniques alone are well documented; however, the results are often questionable due to the difficulty in maintaining consistent color identifications. This investigation is concerned with the microstructural responses of the ferromagnetic delta-ferrite phase and the paramagnetic sigma-phase to a ferromagnetic iron colloid in a magnetic field. Such positive or negative responses of the two phases to the colloid offer a more definitive identification. With this technique, the identification of small amounts of these phases in the microstructure is limited only by the highest magnification and resolution of the optical microscope. The procedure is substantiated in this metallographic study with microprobe analysis and color metallography. Several examples of the correlative use of these three techniques in identifying varying amounts of delta-ferrite → sigma transformation are presented

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

Directory of Open Access Journals (Sweden)

M. Rezvanyvardom

2015-09-01

Full Text Available This paper investigates a novel cyclic time-to-digital converter (TDC which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop. The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. Also, this converter improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM. In this converter, the integral nonlinearity (INL and differential nonlinearity (DNL errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

106-17 Telemetry Standards Digitized Audio Telemetry Standard Chapter 5

Science.gov (United States)

2017-07-01

Digitized Audio Telemetry Standard 5.1 General This chapter defines continuously variable slope delta (CVSD) modulation as the standard for digitizing...audio signal. The CVSD modulator is, in essence , a 1-bit analog-to-digital converter. The output of this 1-bit encoder is a serial bit stream, where

A 12-bit spectroscopy analog-to-digital converter type SAA (Successive Approximation type with channel width Averaging) intended for multichannel pulse height analyzer SWAN-1 based on IBM PC/XT/AT

International Nuclear Information System (INIS)

Borsuk, S.; Kulka, Z.

1989-12-01

A 12-bit spectroscopy analog-to-digital converter (ADC) type SAA (Successive Approximation type with channel width Averaging) intended for multichannel pulse height analyzer SWAN-1 based on IBM PC/XT/AT has been described. Design principles, specifications and measurements of a fundamental SAA-2 converter version are reported. Finally, two next versions of the converter with introduced modifications are discussed. 6 refs., 7 figs. (author)

Configurable Analog-Digital Conversion Using the Neural EngineeringFramework

Directory of Open Access Journals (Sweden)

Christian G Mayr

2014-07-01

Full Text Available Efficient Analog-Digital Converters (ADC are one of the mainstays of mixed-signal integrated circuit design. Besides the conventional ADCs used in mainstream ICs, there have been various attempts in the past to utilize neuromorphic networks to accomplish an efficient crossing between analog and digital domains, i.e. to build neurally inspired ADCs. Generally, these have suffered from the same problems as conventional ADCs, that is they require high-precision, handcrafted analog circuits and are thus not technology portable. In this paper, we present an ADC based on the Neural Engineering Framework (NEF. It carries out a large fraction of the overall ADC process in the digital domain, i.e. it is easily portable across technologies. The analog-digital conversion takes full advantage of the high degree of parallelism inherent in neuromorphic networks, making for a very scalable ADC. In addition, it has a number of features not commonly found in conventional ADCs, such as a runtime reconfigurability of the ADC sampling rate, resolution and transfer characteristic.

Design rules for superconducting analog-digital transducers

International Nuclear Information System (INIS)

Haddad, Taghrid

2015-01-01

This Thesis is a contribution for dimensioning aspects of circuits designs in superconductor electronics. Mainly superconductor comparators inclusive Josephson comparators as well as QOJS-Comparators are investigated. Both types were investigated in terms of speed and sensitivity. The influence of the thermal noise on the decision process of the comparators represent in so called gray zone, which is analysed in this thesis. Thereby, different relations between design parameters were derived. A circuit model of the Josephson comparator was verified by experiments. Concepts of superconductor analog-to-digital converters, which are based on above called comparators, were investigated in detail. From the comparator design rules, new rules for AD-converters were derived. Because of the reduced switching energy, the signal to noise ratio (SNR) of the circuits is affected and therefore the reliability of the decision-process is affected. For special applications with very demanding requirements in terms of the speed and accuracy superconductor analog-to-digital converters offer an excellent performance. This thesis provides relations between different design paramenters and shows resulting trade-offs, This method is transparent and easy to transfer to other circuit topologies. As a main result, a highly predictive tool for dimensioning of superconducting ADC's is proved.

A 1 MHz BW 34.2 fJ/step Continuous Time Delta Sigma Modulator With an Integrated Mixer for Cardiac Ultrasound.

Science.gov (United States)

Kaald, Rune; Eggen, Trym; Ytterdal, Trond

2017-02-01

Fully digitized 2D ultrasound transducer arrays require one ADC per channel with a beamforming architecture consuming low power. We give design considerations for per-channel digitization and beamforming, and present the design and measurements of a continuous time delta-sigma modulator (CTDSM) for cardiac ultrasound applications. By integrating a mixer into the modulator frontend, the phase and frequency of the input signal can be shifted, thereby enabling both improved conversion efficiency and narrowband beamforming. To minimize the power consumption, we propose an optimization methodology using a simulated annealing framework combined with a C++ simulator solving linear electrical networks. The 3rd order single-bit feedback type modulator, implemented in a 65 nm CMOS process, achieves an SNR/SNDR of 67.8/67.4 dB across 1 MHz bandwidth consuming 131 [Formula: see text] of power. The achieved figure of merit of 34.2 fJ/step is comparable with state-of-the-art feedforward type multi-bit designs. We further demonstrate the influence to the dynamic range when performing dynamic receive beamforming on recorded delta-sigma modulated bit-stream sequences.

Iterative Signal Processing for Mitigation of Analog-to-Digital Converter Clipping Distortion in Multiband OFDMA Receivers

Directory of Open Access Journals (Sweden)

Markus Allén

2012-01-01

Full Text Available In modern wideband communication receivers, the large input-signal dynamics is a fundamental problem. Unintentional signal clipping occurs, if the receiver front-end with the analog-to-digital interface cannot respond to rapidly varying conditions. This paper discusses digital postprocessing compensation of such unintentional clipping in multiband OFDMA receivers. The proposed method iteratively mitigates the clipping distortion by exploiting the symbol decisions. The performance of the proposed method is illustrated with various computer simulations and also verified by concrete laboratory measurements with commercially available analog-to-digital hardware. It is shown that the clipping compensation algorithm implemented in a turbo decoding OFDM receiver is able to remove almost all the clipping distortion even under significant clipping in fading channel circumstances. That is to say, it is possible to nearly recover the receiver performance to the level, which would be achieved in the equivalent nonclipped situation.

An ultra-low-power CMOS temperature sensor for RFID applications

Energy Technology Data Exchange (ETDEWEB)

Xu Conghui; Gao Peijun; Che Wenyi; Tan Xi; Yan Na; Min Hao, E-mail: yanna@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

2009-04-15

An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-mum CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 muA and 1.8 V for continuous operation and achieves an accuracy of +-0.65 deg. C from -20 to 120 deg. C after calibration at one temperature.

An ultra-low-power CMOS temperature sensor for RFID applications

International Nuclear Information System (INIS)

Xu Conghui; Gao Peijun; Che Wenyi; Tan Xi; Yan Na; Min Hao

2009-01-01

An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-μm CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 μA and 1.8 V for continuous operation and achieves an accuracy of ±0.65 deg. C from -20 to 120 deg. C after calibration at one temperature.

CMOS circuit design, layout and simulation

CERN Document Server

Baker, R Jacob

2010-01-01

The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

Practical Design of Delta-Sigma Multiple Description Audio Coding

DEFF Research Database (Denmark)

Leegaard, Jack Højholt; Østergaard, Jan; Jensen, Søren Holdt

2014-01-01

It was recently shown that delta-sigma quantization (DSQ) can be used for optimal multiple description (MD) coding of Gaussian sources. The DSQ scheme combined oversampling, prediction, and noise-shaping in order to trade off side distortion for central distortion in MD coding. It was shown that ...

A CAMAC unit for charge measuring and pulse shape recording based on a fast, 8-bit parallel analog-to-digital converter

International Nuclear Information System (INIS)

Kulka, Z.; Kreciejewski, M.; Nadachowski, M.

1990-08-01

A device designed mainly for measuring systems for testing parameters of some type of detectors used in the high energy physics is described. The device is one-module CAMAC unit. It is equipped in a fast, 8-bit parallel analog-to-digital converter ''flash''type with a gated integrator at the input and a static RAM (4096 x 8 bit) at the output. The device enables measurements of the charge in pulses from detectors or registration of the shape of these pulses. The construction, operation and parameters of the circuits of the device are described and the way of programming functions using CAMAC dataway is given. 8 refs., 9 figs. (author)

A Continuous-Time Delta-Sigma ADC for Portable Ultrasound Scanners

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Jørgensen, Ivan Harald Holger; Bruun, Erik

2017-01-01

A fully differential fourth-order 1-bit continuous-time delta-sigma ADC designed in a 65nm process for portable ultrasound scanners is presented in this paper. The circuit design, implementation and measurements on the fabricated die are shown. The loop filter consists of RC-integrators, programmable...... capacitor arrays, resistors and voltage feedback DACs. The quantizer contains a pulse generator, a high-speed clocked comparator and a pull-down clocked latch to ensure constant delay in the feedback loop. Using this implementation, a small and low-power solution required for portable ultrasound scanner...... applications is achieved. The converter has a supply voltage of 1.2V, a bandwidth of 10MHz and an oversampling ratio of 16 leading to an operating frequency of 320MHz. The design occupies a die area of 0.0175mm2. Simulations with extracted parasitics show a SNR of 45.2dB and a current consumption of 489 µ...

Digitized self-oscillating loop for piezoelectric transformer-based power converters

DEFF Research Database (Denmark)

Ekhtiari, Marzieh; Andersen, Thomas; Zhang, Zhe

2016-01-01

A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitized delay, or digitized phase shift through the self-oscillating loop results in a very precise...... frequency control and ensures an optimum operation of the piezoelectric transformer in terms of voltage gain and efficiency. In this work, additional time delay is implemented digitally for the first time through 16 bit digital-to-analog converter to the self-oscillating loop. Delay control setpoints...... updates at a rate of 417 kHz. This allows the control loop to dynamically follow frequency changes of the transformer in each resonant cycle. The operation principle behind self-oscillating is discussed in this paper. Moreover, experimental results are reported....

Study and analysis of coefficient mismatch in a MASH21 sigma-delta modulator

Energy Technology Data Exchange (ETDEWEB)

Ge Binjie; Wang Xin' an; Zhang Xing; Feng Xiaoxing; Wang Qingqin, E-mail: wangxa@szpku.edu.c [Key Laboratory of Integrated Microsystem Science and Engineering Applications, Shenzhen Graduate School of Peking University, Shenzhen 518055 (China)

2010-01-15

The quantization noise leakage of the first stage in a MASH21 sigma-delta modulator is analyzed. The results show that the finite DC gain of the opamp is the main reason for noise leakage, and finite GBW and SR only generate harmonic distortion. The relationship between DC gain and leakage is modeled and conclusions on design criteria are reached. As an example, a MASH21 modulator for a digital audio application is realized. This modulator, fabricated in an 0.18 {mu}m mixed signal process, achieves an SNDR of 91 dB with 1.8 V supply, which verifies the analysis and design criteria. (semiconductor integrated circuits)

A standardized way to select, evaluate, and test an analog-to-digital converter for ultrawide bandwidth radiofrequency signals based on user's needs, ideal, published,and actual specifications

Science.gov (United States)

Chang, Daniel Y.; Rowe, Neil C.

2012-06-01

The most important adverse impact on the Electronic Warfare (EW) simulation is that the number of signal sources that can be tested simultaneously is relatively small. When the number of signal sources increases, the analog hardware, complexity and costs grow by the order of N2, since the number of connections among N components is O(N*N) and the signal communication is bi-directional. To solve this problem, digitization of the signal is suggested. In digitizing a radiofrequency signal, an Analog-to-Digital Converter (ADC) is widely used. Most research studies on ADCs are conducted from designer/test engineers' perspective. Some research studies are conducted from market's perspective. This paper presents a generic way to select, evaluate and test ultra high bandwidth COTS ADCs and generate requirements for digitizing continuous time signals from the perspective of user's needs. Based on user's needs, as well as vendor's published, ideal and actual specifications, a decision can be made in selecting a proper ADC for an application. To support our arguments and illustrate the methodology, we evaluate a Tektronix TADC-1000, an 8-bit and 12 gigasamples per second ADC. This project is funded by JEWEL lab, NAWCWD at Point Mugu, CA.

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

Science.gov (United States)

Ge, Binjie; Li, Yan; Yu, Hang; Feng, Xiaoxing

2018-05-01

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator. A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator. The proposed modulator uses sampling capacitor sharing switched capacitor integrator, and achieves a very small feedback coefficient by a series capacitor network, and those two techniques can dramatically reduce capacitor area. Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation. This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and -1 MHz IF with 48 MHz clock. The chip is fabricated with SMIC 0.18 μm CMOS technology, it achieves a total power current of 2.1 mA, and the chip area is 0.48 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61471245, U1201256), the Guangdong Province Foundation (No. 2014B090901031), and the Shenzhen Foundation (Nos. JCYJ20160308095019383, JSGG20150529160945187).

New system for digital to analog transformation and reconstruction of 12-lead ECGs.

Science.gov (United States)

Kothadia, Roshni; Kulecz, Walter B; Kofman, Igor S; Black, Adam J; Grier, James W; Schlegel, Todd T

2013-01-01

We describe initial validation of a new system for digital to analog conversion (DAC) and reconstruction of 12-lead ECGs. The system utilizes an open and optimized software format with a commensurately optimized DAC hardware configuration to accurately reproduce, from digital files, the original analog electrocardiographic signals of previously instrumented patients. By doing so, the system also ultimately allows for transmission of data collected on one manufacturer's 12-lead ECG hardware/software into that of any other. To initially validate the system, we compared original and post-DAC re-digitized 12-lead ECG data files (∼5-minutes long) in two types of validation studies in 10 patients. The first type quantitatively compared the total waveform voltage differences between the original and re-digitized data while the second type qualitatively compared the automated electrocardiographic diagnostic statements generated by the original versus re-digitized data. The grand-averaged difference in root mean squared voltage between the original and re-digitized data was 20.8 µV per channel when re-digitization involved the same manufacturer's analog to digital converter (ADC) as the original digitization, and 28.4 µV per channel when it involved a different manufacturer's ADC. Automated diagnostic statements generated by the original versus reconstructed data did not differ when using the diagnostic algorithm from the same manufacturer on whose device the original data were collected, and differed only slightly for just 1 of 10 patients when using a third-party diagnostic algorithm throughout. Original analog 12-lead ECG signals can be reconstructed from digital data files with accuracy sufficient for clinical use. Such reconstructions can readily enable automated second opinions for difficult-to-interpret 12-lead ECGs, either locally or remotely through the use of dedicated or cloud-based servers.

New system for digital to analog transformation and reconstruction of 12-lead ECGs.

Directory of Open Access Journals (Sweden)

Roshni Kothadia

Full Text Available INTRODUCTION: We describe initial validation of a new system for digital to analog conversion (DAC and reconstruction of 12-lead ECGs. The system utilizes an open and optimized software format with a commensurately optimized DAC hardware configuration to accurately reproduce, from digital files, the original analog electrocardiographic signals of previously instrumented patients. By doing so, the system also ultimately allows for transmission of data collected on one manufacturer's 12-lead ECG hardware/software into that of any other. MATERIALS AND METHODS: To initially validate the system, we compared original and post-DAC re-digitized 12-lead ECG data files (∼5-minutes long in two types of validation studies in 10 patients. The first type quantitatively compared the total waveform voltage differences between the original and re-digitized data while the second type qualitatively compared the automated electrocardiographic diagnostic statements generated by the original versus re-digitized data. RESULTS: The grand-averaged difference in root mean squared voltage between the original and re-digitized data was 20.8 µV per channel when re-digitization involved the same manufacturer's analog to digital converter (ADC as the original digitization, and 28.4 µV per channel when it involved a different manufacturer's ADC. Automated diagnostic statements generated by the original versus reconstructed data did not differ when using the diagnostic algorithm from the same manufacturer on whose device the original data were collected, and differed only slightly for just 1 of 10 patients when using a third-party diagnostic algorithm throughout. CONCLUSION: Original analog 12-lead ECG signals can be reconstructed from digital data files with accuracy sufficient for clinical use. Such reconstructions can readily enable automated second opinions for difficult-to-interpret 12-lead ECGs, either locally or remotely through the use of dedicated or cloud

Capacitive digital-to-analogue converters with least significant bit down in differential successive approximation register ADCs

Directory of Open Access Journals (Sweden)

Lei Sun

2014-01-01

Full Text Available This Letter proposes a least significant bit-down switching scheme in the capacitive digital-to-analogue converters (CDACs of successive approximation register analog-to-digital converter (ADC. Under the same unit capacitor, the chip area and the switching energy are halved without increasing the complexity of logic circuits. Compared with conventional CDAC, when it is applied to one of the most efficient switching schemes, V(cm-based structure, it achieves 93% less switching energy and 75% less chip area with the same differential non linearity (DNL/integral non linearity (INL performance.

Ultra-fast analog-to-digital converter based on a nonlinear triplexer and an optical coder with a photonic crystal structure.

Science.gov (United States)

Mehdizadeh, Farhad; Soroosh, Mohammad; Alipour-Banaei, Hamed; Farshidi, Ebrahim

2017-03-01

In this paper, we propose what we believe is a novel all-optical analog-to-digital converter (ADC) based on photonic crystals. The proposed structure is composed of a nonlinear triplexer and an optical coder. The nonlinear triplexer is for creating discrete levels in the continuous optical input signal, and the optical coder is for generating a 2-bit standard binary code out of the discrete levels coming from the nonlinear triplexer. Controlling the resonant mode of the resonant rings through optical intensity is the main objective and working mechanism of the proposed structure. The maximum delay time obtained for the proposed structure was about 5 ps and the total footprint is about 1520  μm2.

Digital and analog communication systems

Science.gov (United States)

Shanmugam, K. S.

1979-01-01

The book presents an introductory treatment of digital and analog communication systems with emphasis on digital systems. Attention is given to the following topics: systems and signal analysis, random signal theory, information and channel capacity, baseband data transmission, analog signal transmission, noise in analog communication systems, digital carrier modulation schemes, error control coding, and the digital transmission of analog signals.

Improved stability and performance from sigma-delta modulators using 1-bit vector quantization

DEFF Research Database (Denmark)

Risbo, Lars

1993-01-01

A novel class of sigma-delta modulators is presented. The usual scalar 1-b quantizer in a sigma-delta modulator is replaced by a 1-b vector quantizer with a N-dimensional input state-vector from the linear feedback filter. Generally, the vector quantizer changes the nonlinear dynamics...... of the modulator, and a proper choice of vector quantizer can improve both system stability and coding performance. It is shown how to construct the vector quantizer in order to limit the excursions in state-space. The proposed method is demonstrated graphically for a simple second-order modulator...

Digitally controlled analog proportional-integral-derivative (PID) controller for high-speed scanning probe microscopy

Science.gov (United States)

Dukic, Maja; Todorov, Vencislav; Andany, Santiago; Nievergelt, Adrian P.; Yang, Chen; Hosseini, Nahid; Fantner, Georg E.

2017-12-01

Nearly all scanning probe microscopes (SPMs) contain a feedback controller, which is used to move the scanner in the direction of the z-axis in order to maintain a constant setpoint based on the tip-sample interaction. The most frequently used feedback controller in SPMs is the proportional-integral (PI) controller. The bandwidth of the PI controller presents one of the speed limiting factors in high-speed SPMs, where higher bandwidths enable faster scanning speeds and higher imaging resolution. Most SPM systems use digital signal processor-based PI feedback controllers, which require analog-to-digital and digital-to-analog converters. These converters introduce additional feedback delays which limit the achievable imaging speed and resolution. In this paper, we present a digitally controlled analog proportional-integral-derivative (PID) controller. The controller implementation allows tunability of the PID gains over a large amplification and frequency range, while also providing precise control of the system and reproducibility of the gain parameters. By using the analog PID controller, we were able to perform successful atomic force microscopy imaging of a standard silicon calibration grating at line rates up to several kHz.

A bulk-controlled ring-VCO with 1/f-noise reduction for frequency ΔΣ modulator

DEFF Research Database (Denmark)

Tuan Vu, CAO; Wisland, Dag T.; Lande, Tor Sverre

The paper introduces a bulk-controlled ring-VCO with a tail transistor utilizing flicker-noise (1/f-noise) reduction techniques for a frequency-based DeltaSigma modulator (FDSM). This VCO converts an analog input voltage to phase information under various bias conditions ranging from sub-threshol......The paper introduces a bulk-controlled ring-VCO with a tail transistor utilizing flicker-noise (1/f-noise) reduction techniques for a frequency-based DeltaSigma modulator (FDSM). This VCO converts an analog input voltage to phase information under various bias conditions ranging from sub...

A CMOS analog front-end chip for amperometric electrochemical sensors

International Nuclear Information System (INIS)

Li Zhichao; Chen Min; Xiao Jingbo; Chen Jie; Liu Yuntao

2015-01-01

This paper reports a complimentary metal–oxide–semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I 2 C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma–delta analog to digital converter (Σ–Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm 2 . Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. (paper)

Measurement of the total cross section difference {Delta}{sigma}{sub L} in np transmission at 1.19, 2.49 and 3.65 GeV

Energy Technology Data Exchange (ETDEWEB)

Averichev, S.A. [Joint Inst. for Nuclear Research, Dubna (Russian Federation). Lab. of High Energy; Azhgirey, L.S. [Joint Inst. for Nuclear Research, Dubna (Russian Federation). Lab. of Nuclear Problems; Benda, B. [CEA Centre d`Etudes de Saclay, 91 - Gif-sur-Yvette (France). Dept. d`Astrophysique, de la Physique des Particules, de la Physique Nucleaire et de l`Instrumentation Associee; Adiasevich, B.P. [Russian Research Centre Kurchatov Inst., Moscow (Russian Federation); Ball, J. [Laboratoire National Saturne - Centre d`Etudes Nucleaires de Saclay, 91 - Gif-sur-Yvette (France); Bazhanov, N.A. [AN SSSR, Leningrad (Russian Federation). Inst. Yadernoj Fiziki; Dzyubak, A.P. [AN Ukrainskoj SSR, Kharkov (Ukraine). Fiziko-Tekhnicheskij Inst.; Fedorov, A.N. [Joint Inst. for Nuclear Research, Dubna (Russian Federation). Lab. of Particle Physics; Grosnick, D.P. [Argonne National Lab., IL (United States). High Energy Physics Div.; Gurevich, G.M. [AN SSSR, Moscow (Russian Federation). Inst. Yadernykh Issledovanij] [and others

1996-01-01

Results of the total cross section difference {Delta}{sigma}{sub L} in a np transmission experiment are presented. Results were obtained with a polarized beam of free quasi-monochromatic neutrons passing through the new Dubna frozen spin proton target. The beam and target polarizations were oriented longitudinally. The new results are compared with {Delta}{sigma}{sub L}(pn) data determined as a difference between {Delta}{sigma}{sub L}(pd) and {Delta}{sigma}{sub L}(pp) ANL-ZGS measurements. The values of {Delta}{sigma}{sub L} for the isospin state I=0 were deduced using known pp data. (author). Submitted to Zeitschrift fuer Physik, C (DE); 51 refs.

Methodology for the digital calibration of analog circuits and systems with case studies

CERN Document Server

Pastre, Marc

2006-01-01

Methodology for the Digital Calibration of Analog Circuits and Systems shows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components. A complete methodology is proposed, and three applications are detailed. To start with, an in-depth analysis of existing compensation techniques for analog circuit imperfections is carried out. The M/2+M sub-binary digital-to-analog converter is thoroughly studied, and the use of this very low-area circuit in conjunction with a successive approximations algorithm for digital compensation is described. A complete methodology based on this compensation circuit and algorithm is then proposed. The detection and correction of analog circuit imperfections is studied, and a simulation tool allowing the transparent simulation of analog circuits with automatic compensation blocks is introduced. The first application shows how the sub-binary M/2+M structure can be employed as a conventional di...

Converting analog interpretive data to digital formats for use in database and GIS applications

Science.gov (United States)

Flocks, James G.

2004-01-01

There is a growing need by researchers and managers for comprehensive and unified nationwide datasets of scientific data. These datasets must be in a digital format that is easily accessible using database and GIS applications, providing the user with access to a wide variety of current and historical information. Although most data currently being collected by scientists are already in a digital format, there is still a large repository of information in the literature and paper archive. Converting this information into a format accessible by computer applications is typically very difficult and can result in loss of data. However, since scientific data are commonly collected in a repetitious, concise matter (i.e., forms, tables, graphs, etc.), these data can be recovered digitally by using a conversion process that relates the position of an attribute in two-dimensional space to the information that the attribute signifies. For example, if a table contains a certain piece of information in a specific row and column, then the space that the row and column occupies becomes an index of that information. An index key is used to identify the relation between the physical location of the attribute and the information the attribute contains. The conversion process can be achieved rapidly, easily and inexpensively using widely available digitizing and spreadsheet software, and simple programming code. In the geological sciences, sedimentary character is commonly interpreted from geophysical profiles and descriptions of sediment cores. In the field and laboratory, these interpretations were typically transcribed to paper. The information from these paper archives is still relevant and increasingly important to scientists, engineers and managers to understand geologic processes affecting our environment. Direct scanning of this information produces a raster facsimile of the data, which allows it to be linked to the electronic world. But true integration of the content with

Interpolation by a prime factor other than 2 in low-voltage low-power ΣΔ DAC

DEFF Research Database (Denmark)

Pracný, Peter; Jørgensen, Ivan Harald Holger; Chen, Liang

2013-01-01

This paper presents power optimization of a sigma-delta (ΣΔ) modulator based digital-to-analog converter (DAC) for hearing-aid audio back-end application. In a number of state-of-the-art publications the oversampling ratio (OSR) of the ΣΔ modulator is chosen as a factor of integer power of two...... optimization approach can be used for other low voltage low power portable audio applications (mobile phones, notebook computers etc.)....

Sub-picosecond Resolution Time-to-Digital Converter

Energy Technology Data Exchange (ETDEWEB)

Bratov, Vladimir [Advanced Science and Novel Technology Company, Rancho Palos Verdes, CA (United States); Katzman, Vladimir [Advanced Science and Novel Technology Company, Rancho Palos Verdes, CA (United States); Binkley, Jeb [Advanced Science and Novel Technology Company, Rancho Palos Verdes, CA (United States)

2006-03-30

Time-to-digital converters with sub-picosecond resolutions are needed to satisfy the requirements of time-on-flight measurements of the next generation of high energy and nuclear physics experiments. The converters must be highly integrated, power effective, low cost, and feature plug-and-play capabilities to handle the increasing number of channels (up to hundreds of millions) in future Department of Energy experiments. Current state-off-the-art time-to-digital converter integrated circuits do not have the sufficient degree of integration and flexibility to fulfill all the described requirements. During Phase I, the Advanced Science and Novel Technology Company in cooperation with the nuclear physics division of the Oak Ridge National Laboratory has developed the architecture of a novel time-to-digital converter with multiple channels connected to an external processor through a special interfacing block and synchronized by clock signals generated by an internal phase-locked loop. The critical blocks of the system including signal delay lines and delay-locked loops with proprietary differential delay cells, as well as the required digital code converter and the clock period counter have been designed and simulated using the advanced SiGe120 BiCMOS technological process. The results of investigations demonstrate a possibility to achieve the digitization accuracy within 1ps. ADSANTEC has demonstrated the feasibility of the proposed concept in computer simulations. The proposed system will be a critical component for the next generation of NEP experiments.

Demonstrations of analog-to-digital conversion using a frequency domain stretched processor.

Science.gov (United States)

Reibel, Randy Ray; Harrington, Calvin; Dahl, Jason; Ostrander, Charles; Roos, Peter Aaron; Berg, Trenton; Mohan, R Krishna; Neifeld, Mark A; Babbitt, Wm R

2009-07-06

The first proof-of-concept demonstrations are presented for a broadband photonic-assisted analog-to-digital converter (ADC) based on spatial spectral holography (SSH). The SSH-ADC acts as a frequency-domain stretch processor converting high bandwidth input signals to low bandwidth output signals, allowing the system to take advantage of high performance, low bandwidth electronic ADCs. Demonstrations with 50 MHz effective bandwidth are shown to highlight basic performance with approximately 5 effective bits of vertical resolution. Signal capture with 1600 MHz effective bandwidth is also shown. Because some SSH materials span over 100 GHz and have large time apertures (approximately 10 micros), this technique holds promise as a candidate for the next generation of ADCs.

Analog-to-digital conversion to accommodate the dynamics of live music in hearing instruments.

Science.gov (United States)

Hockley, Neil S; Bahlmann, Frauke; Fulton, Bernadette

2012-09-01

Hearing instrument design focuses on the amplification of speech to reduce the negative effects of hearing loss. Many amateur and professional musicians, along with music enthusiasts, also require their hearing instruments to perform well when listening to the frequent, high amplitude peaks of live music. One limitation, in most current digital hearing instruments with 16-bit analog-to-digital (A/D) converters, is that the compressor before the A/D conversion is limited to 95 dB (SPL) or less at the input. This is more than adequate for the dynamic range of speech; however, this does not accommodate the amplitude peaks present in live music. The hearing instrument input compression system can be adjusted to accommodate for the amplitudes present in music that would otherwise be compressed before the A/D converter in the hearing instrument. The methodology behind this technological approach will be presented along with measurements to demonstrate its effectiveness.

Efficient high-performance ultrasound beamforming using oversampling

Science.gov (United States)

Freeman, Steven R.; Quick, Marshall K.; Morin, Marc A.; Anderson, R. C.; Desilets, Charles S.; Linnenbrink, Thomas E.; O'Donnell, Matthew

1998-05-01

High-performance and efficient beamforming circuitry is very important in large channel count clinical ultrasound systems. Current state-of-the-art digital systems using multi-bit analog to digital converters (A/Ds) have matured to provide exquisite image quality with moderate levels of integration. A simplified oversampling beamforming architecture has been proposed that may a low integration of delta-sigma A/Ds onto the same chip as digital delay and processing circuitry to form a monolithic ultrasound beamformer. Such a beamformer may enable low-power handheld scanners for high-end systems with very large channel count arrays. This paper presents an oversampling beamformer architecture that generates high-quality images using very simple; digitization, delay, and summing circuits. Additional performance may be obtained with this oversampled system for narrow bandwidth excitations by mixing the RF signal down in frequency to a range where the electronic signal to nose ratio of the delta-sigma A/D is optimized. An oversampled transmit beamformer uses the same delay circuits as receive and eliminates the need for separate transmit function generators.

Calculation of comparators of analog-to-digital converters with account of electric regime of transistor operation and ionizing radiation effect; Raschet komparatov analogo-tsifrovykh preobrazovatelej s uchetom ehlektricheskogo rezhima raboty tranzistorov i vozdejstviya ioniziruyushchego izlucheniya

Energy Technology Data Exchange (ETDEWEB)

Ragozin, A Yu

1994-12-31

Zero shift voltage in comparators of analog-to-digital converters under gamma irradiation with regard to electric mode effect on bipolar transistor degradation is calculated. It is shown that the input range of comparators such weak units are represented by comparators of bipolar and lower grades.

An Open-Source Tool Set Enabling Analog-Digital-Software Co-Design

Directory of Open Access Journals (Sweden)

Michelle Collins

2016-02-01

Full Text Available This paper presents an analog-digital hardware-software co-design environment for simulating and programming reconfigurable systems. The tool simulates, designs, as well as enables experimental measurements after compiling to configurable systems in the same integrated design tool framework. High level software in Scilab/Xcos (open-source programs similar to MATLAB/Simulink that converts the high-level block description by the user to blif format (sci2blif, which acts as an input to the modified VPR tool, including the code v p r 2 s w c s , encoding the specific platform through specific architecture files, resulting in a targetable switch list on the resulting configurable analog–digital system. The resulting tool uses an analog and mixed-signal library of components, enabling users and future researchers access to the basic analog operations/computations that are possible.

A time to voltage converter and analog memory unit for straw tracking detectors

International Nuclear Information System (INIS)

Callewaert, L.; Eyckmans, W.; Sansen, W.; Stevens, A.; Van der Spiegel, J.; Van Berg, R.; Williams, H.H.; Yau, T.Y.

1990-01-01

In a high precision drift tube or straw tracking system, one measures the time of arrival of the first electron at the anode. While many possible schemes exist, the authors initial judgment was that an analog time measurement would offer both lower power and greater resolution than an equally complex digital system. In addition, they believe that it will be necessary to incorporate all of the system features such as connection to the trigger and DAQ systems in any usable design in order to keep the power, mass and complexity of the final system under control. A low power, sub-nanosecond accuracy, quick recovery, data-driven, multiple sample Time to Voltage Converter suitable for use on high rate straw tracking detectors is described. The described TVC includes virtual storage of analog data in both Level 1 and Level 2 queues and an on board ADC with first order correction for capacitance variations and non-linearities

Method and apparatus for analog signal conditioner for high speed, digital x-ray spectrometer

International Nuclear Information System (INIS)

Warburton, W.K.; Hubbard, B.

1999-01-01

A signal processing system which accepts input from an x-ray detector-preamplifier and produces a signal of reduced dynamic range for subsequent analog-to-digital conversion is disclosed. The system conditions the input signal to reduce the number of bits required in the analog-to-digital converter by removing that part of the input signal which varies only slowly in time and retaining the amplitude of the pulses which carry information about the x-rays absorbed by the detector. The parameters controlling the signal conditioner's operation can be readily supplied in digital form, allowing it to be integrated into a feedback loop as part of a larger digital x-ray spectroscopy system. 13 figs

Multirate Formulation for Mismatch Sensitivity Analysis of Analog-to-Digital Converters That Utilize Parallel ΣΔ-Modulators

Directory of Open Access Journals (Sweden)

Per Löwenborg

2008-02-01

Full Text Available A general formulation based on multirate filterbank theory for analog-to-digital converters using parallel sigmadelta modulators in conjunction with modulation sequences is presented. The time-interleaved modulators (TIMs, Hadamard modulators (HMs, and frequency-band decomposition modulators (FBDMs can be viewed as special cases of the proposed description. The usefulness of the formulation stems from its ability to analyze a system's sensitivity to aliasing due to channel mismatch and modulation sequence level errors. Both Nyquist-rate and oversampled systems are considered, and it is shown how the matching requirements between channels can be reduced for oversampled systems. The new formulation is useful also for the derivation of new modulation schemes, and an example is given of how it can be used in this context.

Simulation of continuously logical base cells (CL BC) with advanced functions for analog-to-digital converters and image processors

Science.gov (United States)

Krasilenko, Vladimir G.; Lazarev, Alexander A.; Nikitovich, Diana V.

2017-10-01

The paper considers results of design and modeling of continuously logical base cells (CL BC) based on current mirrors (CM) with functions of preliminary analogue and subsequent analogue-digital processing for creating sensor multichannel analog-to-digital converters (SMC ADCs) and image processors (IP). For such with vector or matrix parallel inputs-outputs IP and SMC ADCs it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such basic cells and ADCs based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the CL BC and ADC of photocurrents and their various possible implementations and its simulations. We consider CL BC for methods of selection and rank preprocessing and linear array of ADCs with conversion to binary codes and Gray codes. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of simple nodes based on current mirrors extends the range of functions performed by the image processor. Each channel of the structure consists of several digital-analog cells (DC) on 15-35 CMOS. The amount of DC does not exceed the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC-(G) and SHD, and it has only 35 CMOS transistors. In such ADCs easily parallel code can be realized and also serial-parallel output code. The circuits and simulation results of their design with OrCAD are shown. The supply voltage of the DC is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the transformation time is 20÷30nS at 6-8 bit binary or Gray codes. The general power consumption of the ADC with iteration is only 50÷100μW, if the

Analog to digital workflow improvement: a quantitative study.

Science.gov (United States)

Wideman, Catherine; Gallet, Jacqueline

2006-01-01

This study tracked a radiology department's conversion from utilization of a Kodak Amber analog system to a Kodak DirectView DR 5100 digital system. Through the use of ProModel Optimization Suite, a workflow simulation software package, significant quantitative information was derived from workflow process data measured before and after the change to a digital system. Once the digital room was fully operational and the radiology staff comfortable with the new system, average patient examination time was reduced from 9.24 to 5.28 min, indicating that a higher patient throughput could be achieved. Compared to the analog system, chest examination time for modality specific activities was reduced by 43%. The percentage of repeat examinations experienced with the digital system also decreased to 8% vs. the level of 9.5% experienced with the analog system. The study indicated that it is possible to quantitatively study clinical workflow and productivity by using commercially available software.

A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

KAUST Repository

Omran, Hesham

2016-11-16

A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.

A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

KAUST Repository

Omran, Hesham; Alhoshany, Abdulaziz; Alahmadi, Hamzah; Salama, Khaled N.

2016-01-01

A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.

Noise-shaping all-digital phase-locked loops modeling, simulation, analysis and design

CERN Document Server

Brandonisio, Francesco

2014-01-01

This book presents a novel approach to the analysis and design of all-digital phase-locked loops (ADPLLs), technology widely used in wireless communication devices. The authors provide an overview of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. Realistic examples illustrate how to analyze and simulate phase noise in the presence of sigma-delta modulation and time-to-digital conversion. Readers will gain a deep understanding of ADPLLs and the central role played by noise-shaping. A range of ADPLL and TDC architectures are presented in unified manner. Analytical and simulation tools are discussed in detail. Matlab code is included that can be reused to design, simulate and analyze the ADPLL architectures that are presented in the book.   • Discusses in detail a wide range of all-digital phase-locked loops architectures; • Presents a unified framework in which to model time-to-digital converters for ADPLLs; • Explains a procedure to predict and simulate phase noise in oscil...

Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA

Directory of Open Access Journals (Sweden)

Khalid Khaleel Mohammed

2016-10-01

Full Text Available A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool.  The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR of 256 with a sampling frequency of 20.48 MHz. The proposed decimation filter design is consists of a second order Cascaded Integrator Comb filter (CIC followed by two finite impulse response (FIR filters. This architecture reduces the need for multiplication which is need very large area. This architecture implements a decimation ratio of 256 and allows a maximum resolution of 13  bits in the output of the filter. The decimation filter was designed  and  tested  in  Xilinx  system  generator  tool  which  reduces  the  design  cycle  by  directly generating efficient VHDL code. The results obtained show that the overall Sigma-Delta ADC is able to achieve an ENOB (Effective Number Of Bit of 13.71 bits and SNR of 84.3 dB

Design and implementation of sigma–delta digital to analog converter

Indian Academy of Sciences (India)

Sonika

2018-06-01

Jun 1, 2018 ... Simulation results verify the superiority of the proposed modulator. Sampling rate ..... A MATLAB system level simulation is performed; fig- .... model and implement the design on to the FPGA. The .... J. Signal Process. Syst.

Direct digital conversion detector technology

Science.gov (United States)

Mandl, William J.; Fedors, Richard

1995-06-01

Future imaging sensors for the aerospace and commercial video markets will depend on low cost, high speed analog-to-digital (A/D) conversion to efficiently process optical detector signals. Current A/D methods place a heavy burden on system resources, increase noise, and limit the throughput. This paper describes a unique method for incorporating A/D conversion right on the focal plane array. This concept is based on Sigma-Delta sampling, and makes optimum use of the active detector real estate. Combined with modern digital signal processors, such devices will significantly increase data rates off the focal plane. Early conversion to digital format will also decrease the signal susceptibility to noise, lowering the communications bit error rate. Computer modeling of this concept is described, along with results from several simulation runs. A potential application for direct digital conversion is also reviewed. Future uses for this technology could range from scientific instruments to remote sensors, telecommunications gear, medical diagnostic tools, and consumer products.

Analog and digital signal analysis from basics to applications

CERN Document Server

Cohen Tenoudji, Frédéric

2016-01-01

This book provides comprehensive, graduate-level treatment of analog and digital signal analysis suitable for course use and self-guided learning. This expert text guides the reader from the basics of signal theory through a range of application tools for use in acoustic analysis, geophysics, and data compression. Each concept is introduced and explained step by step, and the necessary mathematical formulae are integrated in an accessible and intuitive way. The first part of the book explores how analog systems and signals form the basics of signal analysis. This section covers Fourier series and integral transforms of analog signals, Laplace and Hilbert transforms, the main analog filter classes, and signal modulations. Part II covers digital signals, demonstrating their key advantages. It presents z and Fourier transforms, digital filtering, inverse filters, deconvolution, and parametric modeling for deterministic signals. Wavelet decomposition and reconstruction of non-stationary signals are also discussed...

7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

KAUST Repository

Omran, Hesham

2014-08-01

In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.

7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

KAUST Repository

Omran, Hesham; Arsalan, Muhammad; Salama, Khaled N.

2014-01-01

In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.

25th workshop on Advances in Analog Circuit Design

CERN Document Server

Harpe, Pieter; Makinwa, Kofi

2017-01-01

This book is based on the 18 tutorials presented during the 25th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of continuous-time sigma-delta modulators, automotive electronics, and power management. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

Fast digital recorders of signal shaping

International Nuclear Information System (INIS)

Meleshko, E.A.

1997-01-01

Methodology of fast digital registration and pulse signals through fast-action analog-to-digital converters is considered. Systems of digital recorders: sampling and storage devices and operational memory units are described. Main attention is paid to developing parallel analog-to-digital converters, making it possible to bring the conversion frequencies up to several gigahertzes are described. Parallel-sequential analog-to-digital converters, combining high action with increased accuracy are also considered. Concrete examples of designing universal and specialized digital signal recorders, applied in experimental physics, are presented. 44 refs., 12 figs

A simple method of digitizing analog scintigrams for quantification and digital archiving

International Nuclear Information System (INIS)

Schramm, M.; Kaempfer, B.; Wolf, H.; Clausen, M.; Wendhausen, H.; Henze, E.

1993-01-01

This study was undertaken to evaluate a quick, reliable and cheap method of digitizing analog scintigrams. 40 whole-body bone scintigrams were obtained simultaneously in analog and genuine digital format. The analog scans on X-ray film were then digitized seecondarily by three different methods: 300 dpi flatbed scanning, high-resolution camera scanning and camcorder recording. A simple exposure approach using a light box, a cheap camcorder, a PC and image grabber hard- and software proved to be optimal. Visual interpretation showed no differences in clinical findings when comparing the analog images with their secondarily digitized counterparts. To test the possibility of quantification, 126 equivalent ROIs were drawn both in the genuine digital and the secondarily digitized images. Comparing the ROI count to whole-body count percentage of the corresponding ROIs showed the correlation to be linear. The evaluation of phantom studies showed the linear correlation to be true within a wide activity range. Thus, secondary digitalization of analog scintigrams is an easy, cheap and reliable method of archiving images and allows secondary digital quantification. (orig.) [de

[A simple method of digitizing analog scintigrams for quantification and digital archiving].

Science.gov (United States)

Schramm, M; Kämpfer, B; Wolf, H; Clausen, M; Wendhausen, H; Henze, E

1993-02-01

This study was undertaken to evaluate a quick, reliable and cheap method of digitizing analog scintigrams. 40 whole-body bone scintigrams were obtained simultaneously in analog and genuine digital format. The analog scans on x-ray film were then digitized secondarily by three different methods: 300 dpi flat-bed scanning, high-resolution camera scanning and camcorder recording. A simple exposure approach using a light box, a cheap camcorder, a PC and image grabber hard- and software proved to be optimal. Visual interpretation showed no differences in clinical findings when comparing the analog images with their secondarily digitized counterparts. To test the possibility of quantification, 126 equivalent ROIs were drawn both in the genuine digital and the secondarily digitized images. Comparing the ROI count to whole-body count percentage of the corresponding ROIs showed the correlation to be linear. The evaluation of phantom studies showed the linear correlation to be true within a wide activity range. Thus, secondary digitalization of analog scintigrams is an easy, cheap and reliable method of archiving images and allows secondary digital quantification.

Full-Circle Resolver-to-Linear-Analog Converter

Science.gov (United States)

Alhorn, Dean C.; Smith, Dennis A.; Howard, David E.

2005-01-01

A circuit generates sinusoidal excitation signals for a shaft-angle resolver and, like the arctangent circuit described in the preceding article, generates an analog voltage proportional to the shaft angle. The disadvantages of the circuit described in the preceding article arise from the fact that it must be made from precise analog subcircuits, including a functional block capable of implementing some trigonometric identities; this circuitry tends to be expensive, sensitive to noise, and susceptible to errors caused by temperature-induced drifts and imprecise matching of gains and phases. These disadvantages are overcome by the design of the present circuit. The present circuit (see figure) includes an excitation circuit, which generates signals Ksin(Omega(t)) and Kcos(Omega(t)) [where K is an amplitude, Omega denotes 2(pi)x a carrier frequency (the design value of which is 10 kHz), and t denotes time]. These signals are applied to the excitation terminals of a shaft-angle resolver, causing the resolver to put out signals C sin(Omega(t)-Theta) and C cos(Omega(t)-Theta). The cosine excitation signal and the cosine resolver output signal are processed through inverting comparator circuits, which are configured to function as inverting squarers, to obtain logic-level or square-wave signals .-LL[cos(Omega(t)] and -LL[cos(Omega(t)-Theta)], respectively. These signals are fed as inputs to a block containing digital logic circuits that effectively measure the phase difference (which equals Theta between the two logic-level signals). The output of this block is a pulse-width-modulated signal, PWM(Theta), the time-averaged value of which ranges from 0 to 5 VDC as Theta ranges from .180 to +180deg. PWM(Theta) is fed to a block of amplifying and level-shifting circuitry, which converts the input PWM waveform to an output waveform that switches between precise reference voltage levels of +10 and -10 V. This waveform is processed by a two-pole, low-pass filter, which removes

Amplitude-to-frequency converter of radioisotope instruments

International Nuclear Information System (INIS)

Demchenkov, V.P.; Korobkov, I.N.

1988-01-01

An amplitude-to-frequency converter designed for signal processing of radioisotope relay devices is descibed. The basic elements of the converter are a scaling amplifier, an analog-to-digital converter, a code-to-frequency converter, a null-organ, a delay unit and a clock-pulse generator. The designed amplitude-to-frequency converter takes into account a prior information about the signal shape of the energy spectrum. The converter processes input pulses of 0.10 V amplitude and duration more than 2μs. The energy channel number is 64

A high speed digital-to-analogue converter

International Nuclear Information System (INIS)

Hallgren, B.I.

1974-02-01

An 8-bit Digital-to-Analogue converter of the current-weighting type has been constructed using 8 monolithic integrated circuit transistor arrays -one for each bit. The D/A-converter has a voltage output within the range 0 to -2V. The settling time to within half of the least significant bit is about 50 nsec. The temperature dependence and transient response of the converter has been analysed using computer aided design techniques. A comparison is made between the experimental and simulated transient performance. (Auth.)

Benefit of Analog, Programmable and Digital Hearing Aids

Directory of Open Access Journals (Sweden)

Jamileh Fatahi

2006-12-01

Full Text Available Background and Aims: As the hearing aid technology progressively promotes toward replacing analog hearing aids with digital and programmable ones, comparison of the patient satisfaction of those kinds of hearing aids by means of a valuable tool seems so necessary. So, the aim of this study was to compare self-reported benefit of analog, digitally controlled programmable and digital hearing aids for reducing disability caused by hearing impairment in mild to severe sensorineural hearing impaired persons. Materials and Methods: This cross-sectional study was performed on 90 persons with mild to severe sensorineural hearing loss dividing into three groups: 43 subjects were fitted with digital, 15 with programmable, 32 with analog hearing aids. After pure tone audiometry, Abbreviated profile of hearing aid benefit (APHAB was completed before and one month after using hearing aids to determine the benefit of them. Results: Global APHAB mean scores for digital, programmable and analog hearing aids were 49.05, 33.19 and 39.53, respectively. Ease of Communication subscale mean scores were 53.46 for digitals, 37.66 for programmables and 39.09 for analogs. Background noise subscale mean scores for digital programmable and analog hearing aids were 46.36, 25.53 and 35.31, respectively. Global and also both subscale mean scores showed significant difference between digital hearing aids and programmable and analog ones. There was no significant difference between reverberation subscale mean scores of three groups. Conclusion: It seems digital hearing aids may be more beneficial to reduce disability caused by hearing loss than analog and programmable hearing aids are.

A continuous-time/discrete-time mixed audio-band sigma delta ADC

International Nuclear Information System (INIS)

Liu Yan; Hua Siliang; Wang Donghui; Hou Chaohuan

2011-01-01

This paper introduces a mixed continuous-time/discrete-time, single-loop, fourth-order, 4-bit audio-band sigma delta ADC that combines the benefits of continuous-time and discrete-time circuits, while mitigating the challenges associated with continuous-time design. Measurement results show that the peak SNR of this ADC reaches 100 dB and the total power consumption is less than 30 mW. (semiconductor integrated circuits)

Frequency to Voltage Converter Analog Front-End Prototype

Science.gov (United States)

Mata, Carlos; Raines, Matthew

2012-01-01

The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

A continuous-time sigma delta ADC with increased immunity to wide-band interferers

NARCIS (Netherlands)

Philips, K.J.P.; Nuijten, P.A.C.M.; Roovers, R.L.J.; Roermund, van A.H.M.; Munoz Chavero, F.; Tejero Pallarés, M.; Torralba, A.

2004-01-01

Receivers are being digitized in a quest for flexibility. Analog filters and programmable gain stages are being exchanged for digital processing at the price of a very challenging ADC. This paper presents an alternative solution where the filter and programmable gain functionality is integrated into

Modules of the SUMMA system for data readout to the oscillograph, digital display devices and digital printing

International Nuclear Information System (INIS)

Bushnin, Yu.B.; Denisenko, A.A.; Dunajtsev, A.F.; Rybakov, V.G.; Sytin, A.N.

1975-01-01

The modules of the ''Summa'' system are described which allow outputting of information to an oscilloscope, a digital tableau, and a digital printing mechanism; they are: a digital-analog converter, a converter that converts a binary code to a binary-decimal code, a digital display module, a block for outputting to a digital printing mechanism, and a block for stipulating the programs during information outputting. The block diagrams of the modules and the block diagram of the information-outputting programs are presented

Delta sup(14)C, sigma CO sub(2) salinity of the western Indian Ocean deep waters: Spatial and temporal variations

Digital Repository Service at National Institute of Oceanography (India)

Somayajulu, B.L.K.; Bhushan, R.; Narvekar, P.V.

ppt, as revealed by the GEOSECS data (1977-78). The delta sup(14)C-sigma CO sub(2)-salinity relationships show better correlation in the western sector. High biological productivity induced changes and corrosive deepwaters could account for sigma CO...

A measurement of. Delta. sigma. sub L (np), the difference between neutron-proton total cross sections in pure longitudinal spin states

Energy Technology Data Exchange (ETDEWEB)

Beddo, M.E.

1990-10-01

A measurement off {Delta}{sigma}{sub L}(np), the difference between neutron-proton total cross sections in pure longitudinal spin states, is described. The results will help determine the isospin-zero (I = 0) scattering amplitudes, which are not well known above laboratory energies of 500 MeV, whereas the isospin-one (I = 1) amplitudes are fairly well-determined to 1 GeV. Data points were taken at the Los Alamos Meson Physics Facility (LAMPF) at Los Alamos, New Mexico, for five neutron beam energies: 484, 568, 634,720 and 788 MeV; they are the first in this energy range. Polarized neutrons were produced by charge-exchange of polarized protons on a liquid deuterium target (LD{sub 2}). Large-volume neutron counters detected the neutrons that passed through a polarized proton target. The counters subtended a range of solid angles large enough to allow extrapolation of the scattered neutrons to 0{degree}. Two modifications to the LAMPF accelerator system which were made for this work are described. They included a beam buncher,'' which modified the normal rf-time structure of the proton beam and allowed for the selection of peak-energy neutrons by time-of-flight means, and a computerized beam steering program, which reduced systematic effects due to beam motion at the LD{sub 2} target. The experimental values of {Delta}{sigma}{sub L}(np) are found to be consistent with other np data, including preliminary data from SIN and Saclay, but not with some results from Argonne which used a polarized proton beam and a polarized deuteron target. The I = 0 component was extracted from {Delta}{sigma}{sub L}(np) using existing pp data (I = 1), with the unexpected result that {Delta}{sigma}{sub L}(I = 0) was found to be essentially identical in shape to {Delta}{sigma}{sub L}(I = 1). The significance of this is not yet understood.

As Film Goes Byte: The Change From Analog to Digital Film Perception

OpenAIRE

Loertscher, Miriam Laura; Weibel, David; Spiegel, Simon; Flueckiger, Barbara; Mennel, Pierre; Mast, Fred; Iseli, Christian

2016-01-01

The digital revolution changed film production in many ways. Until the end of the 20th century, most film professionals and critics preferred celluloid film. However, no previous empirical study compared complete narrative films recorded with analog and digital cinematography. Three short narrative films were produced with an analog and a digital camera attached to a 3D rig in order to control all optical parameters. In postproduction, a third version of a digital film was created to mimic th...

As Film Goes Byte: The Change From Analog to Digital Film Perception.

OpenAIRE

Loertscher M. L. Weibel D. Spiegel S. Flueckiger B. Mennel P. Mast F. W. & Iseli C.

2016-01-01

The digital revolution changed film production in many ways. Until the end of the 20th century most film professionals and critics preferred celluloid film. However no previous empirical study compared complete narrative films recorded with analog and digital cinematography. Three short narrative films were produced with an analog and a digital camera attached to a 3D rig in order to control all optical parameters. In postproduction a third version of a digital film was created to mimic the a...

Making the Switch to Digital Audio

Directory of Open Access Journals (Sweden)

Shannon Gwin Mitchell

2004-12-01

Full Text Available In this article, the authors describe the process of converting from analog to digital audio data. They address the step-by-step decisions that they made in selecting hardware and software for recording and converting digital audio, issues of system integration, and cost considerations. The authors present a brief description of how digital audio is being used in their current research project and how it has enhanced the “quality” of their qualitative research.

Digital-Analog Hybrid Scheme and Its Application to Chaotic Random Number Generators

Science.gov (United States)

Yuan, Zeshi; Li, Hongtao; Miao, Yunchi; Hu, Wen; Zhu, Xiaohua

2017-12-01

Practical random number generation (RNG) circuits are typically achieved with analog devices or digital approaches. Digital-based techniques, which use field programmable gate array (FPGA) and graphics processing units (GPU) etc. usually have better performances than analog methods as they are programmable, efficient and robust. However, digital realizations suffer from the effect of finite precision. Accordingly, the generated random numbers (RNs) are actually periodic instead of being real random. To tackle this limitation, in this paper we propose a novel digital-analog hybrid scheme that employs the digital unit as the main body, and minimum analog devices to generate physical RNs. Moreover, the possibility of realizing the proposed scheme with only one memory element is discussed. Without loss of generality, we use the capacitor and the memristor along with FPGA to construct the proposed hybrid system, and a chaotic true random number generator (TRNG) circuit is realized, producing physical RNs at a throughput of Gbit/s scale. These RNs successfully pass all the tests in the NIST SP800-22 package, confirming the significance of the scheme in practical applications. In addition, the use of this new scheme is not restricted to RNGs, and it also provides a strategy to solve the effect of finite precision in other digital systems.

Advances in analog and RF IC design for wireless communication systems

CERN Document Server

Manganaro, Gabriele

2013-01-01

Advances in Analog and RF IC Design for Wireless Communication Systems gives technical introductions to the latest and most significant topics in the area of circuit design of analog/RF ICs for wireless communication systems, emphasizing wireless infrastructure rather than handsets. The book ranges from very high performance circuits for complex wireless infrastructure systems to selected highly integrated systems for handsets and mobile devices. Coverage includes power amplifiers, low-noise amplifiers, modulators, analog-to-digital converters (ADCs) and digital-to-analog converters

Time-interleaved high-speed D/A converters

NARCIS (Netherlands)

Olieman, E.

2016-01-01

This thesis is on power efficient very high-speed digital-to-analog converters (DACs) in CMOS technology, intended to generate signals from DC to RF. Components in RF signal chains are nowadays often moved from the analog domain to the digital domain. This allows for more flexibility and better

Method and apparatus for clockless analog-to-digital conversion and peak detection

Science.gov (United States)

DeGeronimo, Gianluigi

2007-03-06

An apparatus and method for analog-to-digital conversion and peak detection includes at least one stage, which includes a first switch, second switch, current source or capacitor, and discriminator. The discriminator changes state in response to a current or charge associated with the input signal exceeding a threshold, thereby indicating whether the current or charge associated with the input signal is greater than the threshold. The input signal includes a peak or a charge, and the converter includes a peak or charge detect mode in which a state of the switch is retained in response to a decrease in the current or charge associated with the input signal. The state of the switch represents at least a portion of a value of the peak or of the charge.

Conception and realization of a multichannel amplitude converter

International Nuclear Information System (INIS)

Bendebiche, L.

1992-11-01

A compact Analog to Digital Converter system suitable for high resolution γ-ray analysers has been developed based on the ADADC84 12-bit converter from Analog Devices. The converter was equipped with a peak detector and a stretcher, and with a memory card providing the sliding scale circuits, the lower threshold, the channel number identification and the zero suppression. The conversion time is 10 μs and the differential non linearity is less than ±1% for a 12-bit resolution. The converter consists of a 12-bit spectroscopy analog-to-digital converter (ADC) while the memory card includes a 8K 24-bit buffer memory. The two cards are plugged into a slot of an IBM PC AT and using an emulation software converts the micro-computer into a full-featured pulse height analyser. In data acquisition mode, the cards can operate independently, making the computer free for other tasks. The software offers acquisition control, visualization, data handling functions and various types of result presentation

Delta-Connected Cascaded H-Bridge Multilevel Converters for Large-Scale Photovoltaic Grid Integration

DEFF Research Database (Denmark)

Yu, Yifan; Konstantinou, Georgios; Townsend, Christopher D.

2017-01-01

The cascaded H-bridge (CHB) converter is becoming a promising candidate for use in next generation large-scale photovoltaic (PV) power plants. However, solar power generation in the three converter phase-legs can be significantly unbalanced, especially in a large geographically-dispersed plant....... The power imbalance between the three phases defines a limit for the injection of balanced three-phase currents to the grid. This paper quantifies the performance of, and experimentally confirms, the recently proposed delta-connected CHB converter for PV applications as an alternative configuration...... for large-scale PV power plants. The required voltage and current overrating for the converter is analytically developed and compared against the star-connected counterpart. It is shown that the delta-connected CHB converter extends the balancing capabilities of the star-connected CHB and can accommodate...

A Three-Step Resolution-Reconfigurable Hazardous Multi-Gas Sensor Interface for Wireless Air-Quality Monitoring Applications.

Science.gov (United States)

Choi, Subin; Park, Kyeonghwan; Lee, Seungwook; Lim, Yeongjin; Oh, Byungjoo; Chae, Hee Young; Park, Chan Sam; Shin, Heugjoo; Kim, Jae Joon

2018-03-02

This paper presents a resolution-reconfigurable wide-range resistive sensor readout interface for wireless multi-gas monitoring applications that displays results on a smartphone. Three types of sensing resolutions were selected to minimize processing power consumption, and a dual-mode front-end structure was proposed to support the detection of a variety of hazardous gases with wide range of characteristic resistance. The readout integrated circuit (ROIC) was fabricated in a 0.18 μm CMOS process to provide three reconfigurable data conversions that correspond to a low-power resistance-to-digital converter (RDC), a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC), and a 16-bit delta-sigma modulator. For functional feasibility, a wireless sensor system prototype that included in-house microelectromechanical (MEMS) sensing devices and commercial device products was manufactured and experimentally verified to detect a variety of hazardous gases.

Global orbit feedback utilizing analog and digital technologies

International Nuclear Information System (INIS)

Singh, O.; Tang, Y.; Ramamoorthy, S.; Krinsky, S.; Yu, L.H.

1997-01-01

At the NSLS, an analog global orbit feedback system is used in regular operations, and a digital global orbit feedback system is available in machine physics studies on the X-Ray Ring. Here, the authors discuss the relative merits of utilizing analog and digital technology in orbit feedback. Results of experiments are reported characterizing the performance of the analog and digital systems when operated individually or together. They give their thoughts on plans for future development of the orbit feedback systems at the NSLS

Total cost of performing analog-to-digital upgrades

International Nuclear Information System (INIS)

Albrigo, T.

1993-01-01

The financial well-being of nuclear power plants in the United States is dependent on reducing costs. Rapid advances in industrial technology have created a conundrum for utility executives and their engineering staffs. Digital technology is being touted as beneficial in many ways; however, a number of significant issues have been raised regarding the adequacy and financial viability of digital systems in nuclear power plants. Actual or perceived problems with digital system design, development, and installation have caused significant financial losses for nuclear utilities. This paper provides a list of problems that must be considered in performing an analog-to-digital conversion or for doing a large digital upgrade. It is desirable that the full financial risks associated with these types of upgrades are considered. Specific problems encountered at Palo Verde nuclear generating station are reviewed to emphasize some of the problem areas

A Novel High-Precision Digital Tunneling Magnetic Resistance-Type Sensor for the Nanosatellites’ Space Application

Directory of Open Access Journals (Sweden)

Xiangyu Li

2018-03-01

Full Text Available Micro-electromechanical system (MEMS magnetic sensors are widely used in the nanosatellites field. We proposed a novel high-precision miniaturized three-axis digital tunneling magnetic resistance-type (TMR sensor. The design of the three-axis digital magnetic sensor includes a low-noise sensitive element and high-performance interface circuit. The TMR sensor element can achieve a background noise of 150 pT/Hz1/2 by the vertical modulation film at a modulation frequency of 5 kHz. The interface circuit is mainly composed of an analog front-end current feedback instrumentation amplifier (CFIA with chopper structure and a fully differential 4th-order Sigma-Delta (ΣΔ analog to digital converter (ADC. The low-frequency 1/f noise of the TMR magnetic sensor are reduced by the input-stage and system-stage chopper. The dynamic element matching (DEM is applied to average out the mismatch between the input and feedback transconductor so as to improve the gain accuracy and gain drift. The digital output is achieved by a switched-capacitor ΣΔ ADC. The interface circuit is implemented by a 0.35 μm CMOS technology. The performance test of the TMR magnetic sensor system shows that: at a 5 V operating voltage, the sensor can achieve a power consumption of 120 mW, a full scale of ±1 Guass, a bias error of 0.01% full scale (FS, a nonlinearity of x-axis 0.13% FS, y-axis 0.11% FS, z-axis 0.15% FS and a noise density of x-axis 250 pT/Hz1/2 (at 1 Hz, y-axis 240 pT/Hz1/2 (at 1 Hz, z-axis 250 pT/Hz1/2 (at 1 Hz, respectively. This work has a less power consumption, a smaller size, and higher resolution than other miniaturized magnetometers by comparison.

Fast transient digitizer

International Nuclear Information System (INIS)

Villa, F.

1982-01-01

Method and apparatus for sequentially scanning a plurality of target elements with an electron scanning beam modulated in accordance with variations in a high-frequency analog signal to provide discrete analog signal samples representative of successive portions of the analog signal; coupling the discrete analog signal samples from each of the target elements to a different one of a plurality of high speed storage devices; converting the discrete analog signal samples to equivalent digital signals; and storing the digital signals in a digital memory unit for subsequent measurement or display

Analog Organic Electronics Building Blocks for Organic Smart Sensor Systems on Foil

CERN Document Server

Marien, Hagen; Heremans, Paul

2013-01-01

 This book provides insight into organic electronics technology and in analog circuit techniques that can be used to increase the performance of both analog and digital organic circuits. It explores the domain of organic electronics technology for analog circuit applications, specifically smart sensor systems.  It focuses on all the building blocks in the data path of an organic sensor system between the sensor and the digital processing block. Sensors, amplifiers, analog-to-digital converters and DC-DC converters are discussed in detail. Coverage includes circuit techniques, circuit implementation, design decisions and measurement results of the building blocks described. Offers readers the first book to focus on analog organic circuit design; Discusses organic electronics technology for analog circuit applications in the context of smart sensor systems; Describes all building blocks necessary for an organic sensor system between the sensor and the digital processing block; Includes circuit techniques, cir...

A new time-digital convert circuit based on digital delay line

International Nuclear Information System (INIS)

Liu Haifeng; Guo Ying; Zhang Zhi

2004-01-01

An introduction of a new method of time-digital convert circuit based on digital delay line is given. High precision and good reliability can be realized when it is combined with traditional counting convert method in the measurement of large scale pulse width and low frequency self-excitation oscillator. (authors)

A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

Directory of Open Access Journals (Sweden)

Sergio Saponara

2010-01-01

Full Text Available The design of a 10-bit resistor-string digital-to-analog converter (DAC for MOEMS micromirror interfacing is addressed in this paper. The proposed DAC, realized in a 0.18-μm BCD technology, features a folded resistor-string stage with a switch matrix and address decoders plus an output voltage buffer stage. The proposed DAC and buffer circuitry are key elements of an innovative scanning micromirror actuator, characterized by direct digital input, full differential driving, and linear response. With respect to the the state-of-the-art resistor-string converters in similar technologies, the proposed DAC has comparable nonlinearity (INL, DNL performances while it has the advantage of a smaller area occupation, 0.17 mm2, including output buffer, and relatively low-power consumption, 200 μW at 500 kSPS and few μW in idle mode.

An introduction to analog and digital communications

CERN Document Server

Haykin, Simon

2012-01-01

The second edition of this accessible book provides readers with an introductory treatment of communication theory as applied to the transmission of information-bearing signals. While it covers analog communications, the emphasis is placed on digital technology. It begins by presenting the functional blocks that constitute the transmitter and receiver of a communication system. Readers will next learn about electrical noise and then progress to multiplexing and multiple access techniques.

Digital redesign of anti-wind-up controller for cascaded analog system.

Science.gov (United States)

Chen, Y S; Tsai, J S H; Shieh, L S; Moussighi, M M

2003-01-01

The cascaded conventional anti-wind-up (CAW) design method for integral controller is discussed. Then, the prediction-based digital redesign methodology is utilized to find the new pulse amplitude modulated (PAM) digital controller for effective digital control of the analog plant with input saturation constraint. The desired digital controller is determined from existing or pre-designed CAW analog controller. The proposed method provides a novel methodology for indirect digital design of a continuous-time unity output-feedback system with a cascaded analog controller as in the case of PID controllers for industrial control processes with the presence of actuator saturations. It enables us to implement an existing or pre-designed cascaded CAW analog controller via a digital controller effectively.

Electronic circuit for rapid digital NMR signal imaging

International Nuclear Information System (INIS)

Jurak, P.; Krejci, I.; Belusa, J.

1992-01-01

The circuit is made up of two analog-to-digital converters whose outputs are connected to a process computer and the synchronization inputs to the clock terminal. The one analog-to-digital converter is connected, via the signal input, to the terminal of the nuclear magnetic resonance locking signal. The signal input of the other analog-to-digital converter is connected to the time base generator, which can be switched off, and to the magnetic field sweep circuit. The assets of this citcuit include easy computerized processing of the digitized information independently of the time base generation, and prevention of interfering signals from penetrating into the magnetic field sweep circuits. (Z.S.). 1 fig

A Novel Analog-to-digital conversion Technique using nonlinear duty-cycle modulation

OpenAIRE

Jean Mbihi; François Ndjali Beng; Martin Kom; Léandre Nneme Nneme

2012-01-01

A new type of analog-to-digital conversion technique is presented in this paper. The interfacing hardware is a very simple nonlinear circuit with 1-bit modulated output. As a implication, behind the hardware simplicity retained is hidden a dreadful nonlinear duty-cycle modulation ratio. However, the overall nonlinear behavior embeds a sufficiently wide linear range, for a rigorous digital reconstitution of the analog input signal using a standard linear filter. Simulation and experimental r...

A 45.8fJ/Step, energy-efficient, differential SAR capacitance-to-digital converter for capacitive pressure sensing

KAUST Repository

Alhoshany, Abdulaziz

2016-05-03

An energy-efficient readout circuit for a capacitive sensor is presented. The capacitive sensor is digitized by a 12-bit energy efficient capacitance-to-digital converter (CDC) that is based on a differential successive-approximation architecture. This CDC meets extremely low power requirements by using an operational transconductance amplifier (OTA) that is based on a current-starved inverter. It uses a charge-redistribution DAC that involves coarse-fine architecture. We split the DAC into a coarse-DAC and a fine-DAC to allow a wide capacitance range in a compact area. It covers a wide range of capacitance of 16.14 pF with a 4.5 fF absolute resolution. An analog comparator is implemented by cross-coupling two 3-input NAND gates to enable power and area efficient operation. The prototype CDC was fabricated using a standard 180 nm CMOS technology. The 12-bit CDC has a measurement time of 42.5 μs, and consumes 3.54 μW and 0.29 μW from analog and digital supplies, respectively. This corresponds to a state-of-the-art figure-of-merit (FoM) of 45.8 fJ/conversion-step. © 2016 Elsevier B.V. All rights reserved.

A 45.8fJ/Step, energy-efficient, differential SAR capacitance-to-digital converter for capacitive pressure sensing

KAUST Repository

Alhoshany, Abdulaziz; Omran, Hesham; Salama, Khaled N.

2016-01-01

An energy-efficient readout circuit for a capacitive sensor is presented. The capacitive sensor is digitized by a 12-bit energy efficient capacitance-to-digital converter (CDC) that is based on a differential successive-approximation architecture. This CDC meets extremely low power requirements by using an operational transconductance amplifier (OTA) that is based on a current-starved inverter. It uses a charge-redistribution DAC that involves coarse-fine architecture. We split the DAC into a coarse-DAC and a fine-DAC to allow a wide capacitance range in a compact area. It covers a wide range of capacitance of 16.14 pF with a 4.5 fF absolute resolution. An analog comparator is implemented by cross-coupling two 3-input NAND gates to enable power and area efficient operation. The prototype CDC was fabricated using a standard 180 nm CMOS technology. The 12-bit CDC has a measurement time of 42.5 μs, and consumes 3.54 μW and 0.29 μW from analog and digital supplies, respectively. This corresponds to a state-of-the-art figure-of-merit (FoM) of 45.8 fJ/conversion-step. © 2016 Elsevier B.V. All rights reserved.

Design, Simulation and Characteristics Research of the Interface Circuit based on nano-polysilicon thin films pressure sensor

Science.gov (United States)

Zhao, Xiaosong; Zhao, Xiaofeng; Yin, Liang

2018-03-01

This paper presents a interface circuit for nano-polysilicon thin films pressure sensor. The interface circuit includes consist of instrument amplifier and Analog-to-Digital converter (ADC). The instrumentation amplifier with a high common mode rejection ratio (CMRR) is implemented by three stages current feedback structure. At the same time, in order to satisfy the high precision requirements of pressure sensor measure system, the 1/f noise corner of 26.5 mHz can be achieved through chopping technology at a noise density of 38.2 nV/sqrt(Hz).Ripple introduced by chopping technology adopt continuous ripple reduce circuit (RRL), which achieves the output ripple level is lower than noise. The ADC achieves 16 bits significant digit by adopting sigma-delta modulator with fourth-order single-bit structure and digital decimation filter, and finally achieves high precision integrated pressure sensor interface circuit.

Monolitic integrated circuit for the strobed charge-to-time converter

International Nuclear Information System (INIS)

Bel'skij, V.I.; Bushnin, Yu.B.; Zimin, S.A.; Punzhin, Yu.N.; Sen'ko, V.A.; Soldatov, M.M.; Tokarchuk, V.P.

1985-01-01

The developed and comercially produced semiconducting circuit - gating charge-to-time converter KR1101PD1 is described. The considered integrated circuit is a short pulse charge-to-time converter with integration of input current. The circuit is designed for construction of time-to-pulse analog-to-digital converters utilized in multichannel detection systems when studying complex topology processes. Input resistance of the circuit is 0.1 Ω permissible input current is 50 mA, maximum measured charge is 300-1000 pC

Design and debugging of multi-step analog to digital converters

NARCIS (Netherlands)

Zjajo, A.

2010-01-01

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has

A High Resolution Switched Capacitor 1bit Sigma-Delta Modulator for Low-Voltage/Low-Power Applications

DEFF Research Database (Denmark)

Furst, Claus Efdmann

1996-01-01

A high resolution 1bit Sigma-Delta modulator for low power/low voltage applications is presented. The modulator operates at a supply of 1-1.5V, the current drain is 0.1mA. The maximum resolution is 87dB equivalent to 14 bits of resolution. This is achieved with a signal-band of 5kHz, over-samplin...

MASMA: a versatile multifunctional unit (gated window amplifier, analog memory, and height-to-time converter)

International Nuclear Information System (INIS)

Goursky, V.; Thenes, P.

1969-01-01

This multipurpose unit is designed to accomplish one of the following functions: - gated window amplifier, - Analog memory and - Amplitude-to-time converter. The first function is mainly devoted to improve the poor resolution of pulse-height analyzers with a small number of channels. The analog memory, a new function in the standard range of plug-in modules, is capable of performing a number of operations: 1) fixed delay, or variable delay dependent on an external parameter (application to the analog processing of non-coincident pulses), 2) de-randomiser to increase the efficiency of the pulse height analysis in a spectrometry experiment, 3) linear multiplexer to allow an analyser to serve as many spectrometry devices as memory elements that it possesses. Associated with a coding scaler, this unit, if used as a amplitude-to-time converter, constitutes a Wilkinson A.D.C with a capability of 10 bits (or more) and with a 100 MHz clock frequency. (authors) [fr

Digital control of high-frequency switched-mode power converters

CERN Document Server

Corradini, Luca; Mattavelli, Paolo; Zane, Regan

This book is focused on the fundamental aspects of analysis, modeling and design of digital control loops around high-frequency switched-mode power converters in a systematic and rigorous manner Comprehensive treatment of digital control theory for power converters Verilog and VHDL sample codes are provided Enables readers to successfully analyze, model, design, and implement voltage, current, or multi-loop digital feedback loops around switched-mode power converters Practical examples are used throughout the book to illustrate applications of the techniques developed Matlab examples are also

CMOS based capacitance to digital converter circuit for MEMS sensor

Science.gov (United States)

Rotake, D. R.; Darji, A. D.

2018-02-01

Most of the MEMS cantilever based system required costly instruments for characterization, processing and also has large experimental setups which led to non-portable device. So there is a need of low cost, highly sensitive, high speed and portable digital system. The proposed Capacitance to Digital Converter (CDC) interfacing circuit converts capacitance to digital domain which can be easily processed. Recent demand microcantilever deflection is part per trillion ranges which change the capacitance in 1-10 femto farad (fF) range. The entire CDC circuit is designed using CMOS 250nm technology. Design of CDC circuit consists of a D-latch and two oscillators, namely Sensor controlled oscillator (SCO) and digitally controlled oscillator (DCO). The D-latch is designed using transmission gate based MUX for power optimization. A CDC design of 7-stage, 9-stage and 11-stage tested for 1-18 fF and simulated using mentor graphics Eldo tool with parasitic. Since the proposed design does not use resistance component, the total power dissipation is reduced to 2.3621 mW for CDC designed using 9-stage SCO and DCO.

Cryocooled wideband digital channelizing radio-frequency receiver based on low-pass ADC

International Nuclear Information System (INIS)

Vernik, Igor V; Kirichenko, Dmitri E; Dotsenko, Vladimir V; Miller, Robert; Webber, Robert J; Shevchenko, Pavel; Talalaevskii, Andrei; Gupta, Deepnarayan; Mukhanov, Oleg A

2007-01-01

We have demonstrated a digital receiver performing direct digitization of radio-frequency signals over a wide frequency range from kilohertz to gigahertz. The complete system, consisting of a cryopackaged superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field programmable gate array (FPGA) based post-processing module, has been developed. The ADR chip comprises a low-pass analog-to-digital converter (ADC) delta modulator with phase modulation-demodulation architecture together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chip is fabricated using a 4.5 kA cm -2 process and is cryopackaged using a commercial-off-the-shelf cryocooler. Experimental results in HF, VHF, UHF and L bands and their analysis, proving consistent operation of the cryopackaged ADR chip up to 24.32 GHz clock frequency, are presented and discussed

A Capacitance-To-Digital Converter for MEMS Sensors for Smart Applications.

Science.gov (United States)

Pérez Sanjurjo, Javier; Prefasi, Enrique; Buffa, Cesare; Gaggl, Richard

2017-06-07

The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 µm CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm², which means a pressure resolution of 1 Pa, while consuming 146 µA from a 1.5 V power supply.

From Analog to Digital Medias in Early Childhood Education

DEFF Research Database (Denmark)

Brandt, Erika Zimmer

2015-01-01

Research aims: The aim of the study is to explore how the encounters between children and their educators alter when the media changes from analog to digital. Relationship to previous research works Tablets and other handheld, electronic devices has become part of everyday life in kindergartens....... Research shows that there are both potential pedagogical difficulties and possibilities connected to using digital media (ex. Thestrup 2015, Tække and Paulsen 2014) Theoretical and conceptual framework: The study is a single case study of an educational experiment (Flyvbjerg 2006). It is carried out...

Current-Mode CMOS A/D Converter for Pico Ampere-Range with a Potentiostatic Input

DEFF Research Database (Denmark)

Breten, Madalina

1999-01-01

amount of a certain gas in a solution, such as oxygen in blood, can be determined by measuring the concentration-dependent current. The circuit that maintains the electrochemical stability in the sensor, as well as buffering the current output is called potentiostat.The DC current at the output....... In this context conversion techniques of the integration-type are preferred, such as dual-slope, multi-slope, or sigma-delta modulation. The performances of the comparator, clock-feedthrough effect, and the offset compensation are the main problems. Furthermore, if an analog circuit is designed as a building......-out. The influence and methods to reduce the nonlinearities of the A/D converter are discussed. At the input of the integrator was implemented a bridge of 4-switches in order to measure the low current with minimum charge injection, and to overcome the drift problems.A new conversion technique is proposed: folded-dual-slope...

High quality digital holographic reconstruction on analog film

Science.gov (United States)

Nelsen, B.; Hartmann, P.

2017-05-01

High quality real-time digital holographic reconstruction, i.e. at 30 Hz frame rates, has been at the forefront of research and has been hailed as the holy grail of display systems. While these efforts have produced a fascinating array of computer algorithms and technology, many applications of reconstructing high quality digital holograms do not require such high frame rates. In fact, applications such as 3D holographic lithography even require a stationary mask. Typical devices used for digital hologram reconstruction are based on spatial-light-modulator technology and this technology is great for reconstructing arbitrary holograms on the fly; however, it lacks the high spatial resolution achievable by its analog counterpart, holographic film. Analog holographic film is therefore the method of choice for reconstructing highquality static holograms. The challenge lies in taking a static, high-quality digitally calculated hologram and effectively writing it to holographic film. We have developed a theoretical system based on a tunable phase plate, an intensity adjustable high-coherence laser and a slip-stick based piezo rotation stage to effectively produce a digitally calculated hologram on analog film. The configuration reproduces the individual components, both the amplitude and phase, of the hologram in the Fourier domain. These Fourier components are then individually written on the holographic film after interfering with a reference beam. The system is analogous to writing angularly multiplexed plane waves with individual component phase control.

Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update

CERN Document Server

Pickering, J.

2015-06-15

This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and implementing it in a design have not changed. Analogue to digital and digital to analogue converters are crucial components in the continued drive to replace analogue circuitry with more controllable and less costly digital processing. This paper discusses the technologies available to perform in the likely measurement and control applications that arise within accelerators. It covers much of the terminology and 'specmanship' together with an application-oriented analysis of the realisable performance of the various types. Finally, some hints and warnings on system integration problems are given.

A 10 MHz Bandwidth Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Jørgensen, Ivan Harald Holger; Bruun, Erik

2016-01-01

comparator and a pull-down clocked latch. The feedback signal is generated with voltage DACs based on transmission gates. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The modulator has a bandwidth of 10 MHz with an oversampling......A fourth-order 1-bit continuous-time delta-sigma modulator designed in a 65 nm process for portable ultrasound scanners is presented in this paper. The loop filter consists of RCintegrators, with programmable capacitor arrays and resistors, and the quantizer is implemented with a high-speed clocked...

Thermal isomerizations of ketenimines to nitriles: evaluations of sigma-Dot (sigma(*)) constants for spin-delocalizations

Science.gov (United States)

Kim; Zhu; Lee

2000-05-19

Rate constants (k(Y)) of the isomerizations of 11 diphenyl N-(substituted benzyl) ketenimines were measured at 40, 50, 60, and 70 degrees C. Activation parameters DeltaH()(Y) and DeltaS()(Y) were obtained using the Eyring equation. The relative rates (k(Y)/k(H)) were fitted into Hammett single correlations (log k(Y)/k(H) = rhosigma and log k(Y)/k(H) = rho(*)sigma(*)). The single correlations have been compared with Hammett dual correlations (log k(Y)/k(H) = rhosigma + rho(*)sigma(*) ). Separate treatments of para and meta substituents yielded even better correlations. Para substituents control the rates through spin-delocalizations and inductive effects. The former outweighs the latter when the latter exerts a modest but distinct influence on the rates. On the other hand, inductive effects are the "major" or the sole interactions triggered by meta substituents.

Toward a 62.5 MHz analog virtual pipeline integrated data acquisition system

International Nuclear Information System (INIS)

Kleinfelder, S.A.; Levi, M.; Milgrome, O.

1991-01-01

Requirements of analog pipeline memories at the SSC are reviewed and the concept of virtual pipelines is introduced. Design details and test results of several new custom analog and digital integrated circuits implementing sections of the virtual multiple pipeline (VMP) scheme are provied. These include serial, random access and simultaneous read and write random access analog storage and retrieval circuits, a 100 MHz systolic variable depth digital pipeline, and a prototye 32 μs, 12 bit serial analog to digital converter. (orig.)

A High Performance Delta-Sigma Modulator for Neurosensing.

Science.gov (United States)

Xu, Jian; Zhao, Menglian; Wu, Xiaobo; Islam, Md Kafiul; Yang, Zhi

2015-08-07

Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-µm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 µW, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.

The influence of the analog-to-digital conversion error on the JT-60 plasma position/shape feedback control system

International Nuclear Information System (INIS)

Yoshida, Michiharu; Kurihara, Kenichi

1995-12-01

In the plasma feedback control system (PFCS) and the direct digital controller (DDC) for the poloidal field coil power supply in the JT-60 tokamak, it is necessary to observe signals of all the poloidal field coil currents. Each of the signals, originally measured by a single sensor, is distributed to the PFCS and DDC through different cable routes and different analog-to-digital converters from each other. This produces the conversion error to the amount of several bits. Consequently, proper voltage from feedback calculation cannot be applied to the coil, and hence the control performance is possibly supposed to deteriorate to a certain extent. This paper describes how this error makes an influence on the plasma horizontal position control and how to improve the deteriorated control performance. (author)

Design and characterization of a mixed-signal PCB for digital-to-analog conversion in a modular and scalable infrared scene projector

Science.gov (United States)

Benedict, Jacob

Infra-red (IR) sensors have proven instrumental in a wide variety of fields from military to industrial applications. The proliferation of IR sensors has spawned an intense push for technologies that can test and calibrate the multitudes of IR sensors. One such technology, IR scene projection (IRSP), provides an inexpensive and safe method for the testing of IR sensor devices. Previous efforts have been conducted to develop IRSPs based on super-lattice light emitting diodes (SLEDS). A single-color 512x512 SLEDs system has been developed, produced, and tested as documented in Corey Lange's Master's thesis, and a GOMAC paper by Rodney McGee [1][2]. Current efforts are being undergone to develop a two-color 512x512 SLEDs system designated (TCSA). The following thesis discusses the design and implementation of a custom printed circuit board (PCB), known as the FMC 4DAC, that contains both analog and digital signals. Utilizing two 16-bit digital-to-analog converters (DAC) the purpose of the board is to provide four analog current output channels for driving the TCSA system to a maximum frame rate of 1 kHz. In addition, the board supports a scalable TCSA system architecture. Several copies of the board can be run in parallel to achieve a range of analog channels between 4 and 32.

Emergent Explorations: Analog and Digital Scripting

OpenAIRE

Worden, Alexander

2011-01-01

This book documents an exploration of emergent and linear modes of defining space, form, and structure. The thesis highlights a dialog between analog and digital modeling techniques, in concept and project development. It identifies that analog modeling techniques, coupled with judgment, can be used to develop complex forms. The thesis project employs critical judgment and the textile techniques of crochet as a vehicle generate form. Crochet lends itself to this investigation because it ...

Time-to-code converter with selection of time intervals on duration

International Nuclear Information System (INIS)

Atanasov, I.Kh.; Rusanov, I.R.; )

2001-01-01

Identification of elementary particles on the basis of time-of-flight represents the important approach of the preliminary selection procedure. Paper describes a time-to-code converter with preliminary selection of the measured time intervals as to duration. It consists of a time-to-amplitude converter, an analog-to-digital converter, a unit of selection of time intervals as to duration, a unit of total reset and CAMAC command decoder. The time-to-code converter enables to measure time intervals with 100 ns accuracy within 0-100 ns range. Output code capacity is of 10. Selection time constitutes 50 ns [ru

Digital positron lifetime: the influence of noise

International Nuclear Information System (INIS)

Krille, Arnold; Krause-Rehberg, Reinhard; Anwand, Wolfgang

2011-01-01

In contrast to the world around where everything seems to go digital as soon as possible, positron lifetime spectrometers are kind of a 'last sanctuary' for analog measurements. Only a few of the newer spectrometers use the analog-digital-converters directly after the photomultipliers and extract the timing information via computer. Judging from their results it seems as if the current available converters and the timing mathematics are only as good as the conventional analog setup in the timing resolution. As it is decided that EPOS [1] will use digital positron lifetime, we try to find some reasons for limited timing resolution by simulating anode pulses from the photomultipliers and measuring the FWHM. We create pulses similar to current state-of-the-art 4GS/s digitizers but can control the level of noise and the bit-depth independently. We found that especially the noise (that would come from the analog electronics in/before the converters) has a great influence on the timing resolution. Also we try to use lowpass filtering to reduce that influence with great success.

Digital positron lifetime: the influence of noise

Energy Technology Data Exchange (ETDEWEB)

Krille, Arnold; Krause-Rehberg, Reinhard [Department of Physics, Martin-Luther-University Halle-Wittenberg, 06099 Halle (Germany); Anwand, Wolfgang, E-mail: arnold.krille@physik.uni-halle.de [Institute of Ion Beam Physics, Research Center Dresden-Rossendorf, 01314 Dresden (Germany)

2011-01-10

In contrast to the world around where everything seems to go digital as soon as possible, positron lifetime spectrometers are kind of a 'last sanctuary' for analog measurements. Only a few of the newer spectrometers use the analog-digital-converters directly after the photomultipliers and extract the timing information via computer. Judging from their results it seems as if the current available converters and the timing mathematics are only as good as the conventional analog setup in the timing resolution. As it is decided that EPOS [1] will use digital positron lifetime, we try to find some reasons for limited timing resolution by simulating anode pulses from the photomultipliers and measuring the FWHM. We create pulses similar to current state-of-the-art 4GS/s digitizers but can control the level of noise and the bit-depth independently. We found that especially the noise (that would come from the analog electronics in/before the converters) has a great influence on the timing resolution. Also we try to use lowpass filtering to reduce that influence with great success.

Digital circuit for the introduction and later removal of dither from an analog signal

Science.gov (United States)

Borgen, Gary S.

1994-05-01

An electronics circuit is presented for accurately digitizing an analog audio or like data signal into a digital equivalent signal by introducing dither into the analog signal and then subsequently removing the dither from the digitized signal prior to its conversion to an analog signal which is a substantial replica of the incoming analog audio or like data signal. The electronics circuit of the present invention is characterized by a first pseudo-random number generator which generates digital random noise signals or dither for addition to the digital equivalent signal and a second pseudo-random number generator which generates subtractive digital random noise signals for the subsequent removal of dither from the digital equivalent signal prior its conversion to the analog replica signal.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

Science.gov (United States)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Auxiliary controller for time-to-digital converter module readout

International Nuclear Information System (INIS)

Ermolin, Yu.V.

1992-01-01

The KD-225 auxiliary controller for time-to-digital converter module readout in the SUMMA crate is described. After readout and preliminary processing the data are written in the P-140 buffer memory module. The controller is used in the FODS-2 experimental setup data acquisition system. 12 refs.; 1 fig

Quality assessment of the digitalization process of analog x-ray images

International Nuclear Information System (INIS)

Georgieva, D.

2014-01-01

Computer-assisted diagnosis enabled doctors for a second point-of-view on the test results. This improves the diseases' early detection and significantly reduces the chance of errors. These methods very nicely complemented the possibilities of digital medical imaging apparatus, but in analog images their applicability and results entirely depend on the quality of analog images digitalisation. Today many standards and remarks for good practices discuss the digital apparatus image quality but the digitalisation process of analog medical images is not a part of them. Medical imaging apparatus have become digital, but within an entirely digital medical environment is necessary for their ability to blend with the old analog medical imaging carriers. The life of patients doesn't start with the beginning of digital era and for the aim of tracking diseases it is necessary to use the new digital images as well as older analog ones. For the generation of 40-50 years a large archive of images is piled up, which should be accounted of in the diagnosis process. This article is the author's study of the digitalized image quality problem. It offers a new approach to the x-ray image digitalisation - getting the HDR-image by optical sensor. After the HDR-image generation method offers to be used a digital signal processing to improve the quality of the final 16 bit gray scale medical image. The new method for medical image enhancement is proposed - it improves the image contrast, it increases or preserves the dynamic range and it doesn't lead to the loss of small low contrast structures in the image. Key words: Quality of Digital X-Rays Images

Development and evaluation of a novel radioiodinated vesamicol analog as a sigma receptor imaging agent.

Science.gov (United States)

Ogawa, Kazuma; Kanbara, Hiroya; Shiba, Kazuhiro; Kitamura, Yoji; Kozaka, Takashi; Kiwada, Tatsuto; Odani, Akira

2012-09-28

Sigma receptors are highly expressed in human tumors and should be appropriate targets for developing tumor imaging agents. Previously, we synthesized a vesamicol analog, (+)-2-[4-(4-iodophenyl)piperidino]cyclohexanol ((+)-pIV), with a high affinity for sigma receptors and prepared radioiodinated (+)-pIV. As a result, (+)-[125I]pIV showed high tumor uptake in biodistribution experiments. However, the accumulation of radioactivity in normal tissues, such as the liver, was high. We supposed that some parts of the accumulation of (+)-pIV in the liver should be because of its high lipophilicity, and prepared and evaluated a more hydrophilic radiolabeled vesamicol analog, (+)-4-[1-(2-hydroxycyclohexyl)piperidine-4-yl]-2-iodophenol ((+)-IV-OH). (+)-[125I]IV-OH was prepared by the chloramine T method from the precursor. The partition coefficient of (+)-[125I]IV-OH was measured. Biodistribution experiments were performed by intravenous administration of a mixed solution of (+)-[125I]IV-OH and (+)-[131I]pIV into DU-145 tumor-bearing mice. Blocking studies were performed by intravenous injection of (+)-[125I]IV-OH mixed with an excess amount of ligand into DU-145 tumor-bearing mice. The hydrophilicity of (+)-[125I]IV-OH was much higher than that of (+)-[125I]pIV. In biodistribution experiments, (+)-[125I]IV-OH and (+)-[131I]pIV showed high uptake in tumor tissues at 10-min post-injection. Although (+)-[131I]pIV tended to be retained in most tissues, (+)-[125I]IV-OH was cleared from most tissues. In the liver, the radioactivity level of (+)-[125I]IV-OH was significantly lower at all time points compared to those of (+)-[131I]pIV. In the blocking studies, co-injection of an excess amount of sigma ligands resulted in significant decreases of tumor/blood uptake ratios after injection of (+)-[125I]IV-OH. The results indicate that radioiodinated (+)-IV-OH holds a potential as a sigma receptor imaging agent.

Ping-Pong Beam Training with Hybrid Digital-Analog Antenna Arrays

DEFF Research Database (Denmark)

Manchón, Carles Navarro; Carvalho, Elisabeth De; Andersen, Jørgen Bach

2017-01-01

In this article we propose an iterative training scheme that approximates optimal beamforming between two transceivers equipped with hybrid digital-analog antenna arrays. Inspired by methods proposed for digital arrays that exploit algebraic power iterations, the proposed training procedure...... is based on a series of alternate (ping-pong) transmissions between the two devices over a reciprocal channel. During the transmissions, the devices updates their digital beamformers by conjugation and normalization operations on the received digital signal, while the analog beamformers are progressively...

Analysis of parallel optical sampling rate and ADC requirements in digital coherent receivers

DEFF Research Database (Denmark)

Lorences Riesgo, Abel; Galili, Michael; Peucheret, Christophe

2012-01-01

We comprehensively assess analog-to-digital converter requirements in coherent digital receiver schemes with parallel optical sampling. We determine the electronic requirements in accordance with the properties of the free running local oscillator.......We comprehensively assess analog-to-digital converter requirements in coherent digital receiver schemes with parallel optical sampling. We determine the electronic requirements in accordance with the properties of the free running local oscillator....

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Directory of Open Access Journals (Sweden)

Taninki Sai Lakshmi

2014-01-01

Full Text Available An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL value of −0.30 LSB and differential nonlinearity (DNL value of −0.24 LSB, of the flash ADC.

Comparing Analog and Digital Hearing Aids in Reducing Hearing Disability

Directory of Open Access Journals (Sweden)

Ghassem Mohammad Khani

2004-06-01

Full Text Available Objective: Comparing analog and digital hearing aids reducing disability caused by hearing deficiency among moderate to severe sensorineural hearing-impaired persons. Method and Material: This descriptive-analytic study was carried out on two groups of subjects participated in this study in some audiology clinics of hearing aid since May 2002 to October 2003. Twenty subjects wore analog hearing aids and twenty one subjects wore digital hearing aids. In this study , no subject had previous middle ear or psychological problems. APHAB questionnaire was completed before using hearing aid and 2 months after to determine benefit of hearing aid use. Results: Total score mean of APHAB inventory before and after use of analoge hearing aids were 52.215+6.420 and 32.300+3.443 respectively. Also total score mean of APHAB inventory before and after use of digital hearing aids were 54.9252+9.028 and 26.321+10.916 respectively. There was no significant difference between total mean score of APHAB inventory before and after using analog and digital hearing aids (P=0.058.While there was significant difference between total mean score of APHAB questionnaire before and after use of analog hearing aids (P<0.001 and also before and after use of digital hearing aids (P<0.001. Moreover age, gender , litracy level , occupation , degree of hearing loss and manner of hearing aid usage did not have significant effect on APHAB results. Configuration of loss had siginficant effect on aversiveness subscale before and after use of analog hearing aids (P=0.008. Previous experience and duration of hearing aid usage had significant effect on aversiveness subscale before and after use of digital hearing aids (P=0.043 and (P=0.024, respectively , while all of these three items did not have significant effect on total mean score of APHAB inventory and also total mean scores of three subscales of ease of communication , reverberation and background noise. Conclusion: Comparing to

Discussing the precipitation behavior of {sigma} phase using diffusion equation and thermodynamic simulation in dissimilar stainless steels

Energy Technology Data Exchange (ETDEWEB)

Hsieh, Chih-Chun [Department of Materials Science and Engineering, National Chung Hsing University, 250 Kuo-Kuang Rd., Taichung 402, Taiwan (China); Wu, Weite, E-mail: wwu@dragon.nchu.edu.t [Department of Materials Science and Engineering, National Chung Hsing University, 250 Kuo-Kuang Rd., Taichung 402, Taiwan (China)

2010-09-17

Research highlights: This article concentrates the phase transformation in {delta} {yields} {sigma} in dissimilar stainless steels using the Vitek equation and thermodynamics simulation during the multi-pass welding. The phase transformation in {delta} {yields} {sigma} is very important to the properties of stainless steel composites. In this study, the diffusion behavior of Cr, Ni and Si in the {delta}, {sigma}, and {gamma} phases were discussed using the DSC analysis and diffusion equation calculation. This method has a novelty for discussing the phase transformation in {delta} {yields} {sigma} in the dissimilar stainless steel. We hope that we can give a scientific contribution for the phase transformation of the dissimilar stainless steels during the multi-pass welding. - Abstract: This study performed a precipitation examination of the {sigma} phase using the Vitek diffusion equation and thermodynamic simulation in dissimilar stainless steels during multi-pass welding. The results of the experiment demonstrate that the diffusion rates (D{sub Cr}{sup {delta}} and D{sub Ni}{sup {delta}}) of Cr and Ni are higher in {delta}-ferrite than (D{sub Cr}{sup {gamma}} and D{sub Ni}{sup {gamma}}) in the {gamma} phase and that they facilitate the precipitation of {sigma} phase in the third pass fusion zone. When the diffusion activation energy of Cr in {delta}-ferrite is equal to that of Ni in {delta}-ferrite (Q{sub dCr}{sup {delta}}=Q{sub dNi}{sup {delta}}), phase transformation of the {delta} {yields} {sigma} can be occurred.

Regulatory requirements for replacement of analog systems with digital upgrades

International Nuclear Information System (INIS)

Loeser, P.J.

1993-01-01

This paper reviews briefly the regulatory guidelines which must be met in order to replace analog systems in nuclear power plants with digital systems. There is a move to do such replacements for a number of reasons: analog systems are aging, and showing considerable drift; few vendors manufacture analog systems today; support and parts are hard to get; digital systems provide flexibility. There is a safety concern however about undesirable and unpredictable effects to digital safety equipment due to plant transients, accidents, post-accident condition, and EMI/RF environmental interferences. License holders must comply with the requirements of 10 C.F.R. 50.59, which deals with safety concerns with respect to any changes to operating plants which may have an impact on the safety of the plant. NRC staff is taking the position that all digital upgrades will require an evaluation under this regulation

Two applications of direct digital down converters in beam diagnostics

International Nuclear Information System (INIS)

Powers, Tom; Flood, Roger; Hovater, Curt; Musson, John

2000-01-01

The technologies of direct digital down converters, digital frequency synthesis, and digital signal processing are being used in many commercial applications. Because of this commercialization, the component costs are being reduced to the point where they are economically viable for large scale accelerator applications. This paper will discuss two applications of these technologies to beam diagnostics. In the first application the combination of direct digital frequency synthesis and direct digital down converters are coupled with digital signal processor technology in order to maintain the stable gain environment required for a multi-electrode beam position monitoring system. This is done by injecting a CW reference signal into the electronics as part of the front-end circuitry. In the second application direct digital down converters are used to provide a novel approach to the measurement of beam intensity using cavity current monitors. In this system a pair of reference signals are injected into the cavity through an auxiliary port. The beam current is then calculated as the ratio of the beam signal divided by the average of the magnitude of the two reference signals

Systems and methods for self-synchronized digital sampling

Science.gov (United States)

Samson, Jr., John R. (Inventor)

2008-01-01

Systems and methods for self-synchronized data sampling are provided. In one embodiment, a system for capturing synchronous data samples is provided. The system includes an analog to digital converter adapted to capture signals from one or more sensors and convert the signals into a stream of digital data samples at a sampling frequency determined by a sampling control signal; and a synchronizer coupled to the analog to digital converter and adapted to receive a rotational frequency signal from a rotating machine, wherein the synchronizer is further adapted to generate the sampling control signal, and wherein the sampling control signal is based on the rotational frequency signal.

2 GHz self-aligning tandem A/D converter for SAR

DEFF Research Database (Denmark)

Søbjærg, Sten Schmidl; Christensen, Erik Lintz

2001-01-01

digitizing, and the other is to digitize the signal before digital I/Q demodulation. In both cases the digitizing may be performed by a digital front end (DFE) with two parallel analog-to-digital-converters (ADCs) sampling at 1 GHz in phase or in anti-phase respectively, provided the analog bandwidth...... of the ADC is sufficient. In the first case each ADC has to digitize a 0-400 MHz signal, and in the second case both ADCs have to digitize a 100-900 MHz signal. In both cases the sampling time alignment is a critical parameter. The paper addresses some aspects of ADC alignment in the implementation of a DFE...

The application of standardized control and interface circuits to three dc to dc power converters.

Science.gov (United States)

Yu, Y.; Biess, J. J.; Schoenfeld, A. D.; Lalli, V. R.

1973-01-01

Standardized control and interface circuits were applied to the three most commonly used dc to dc converters: the buck-boost converter, the series-switching buck regulator, and the pulse-modulated parallel inverter. The two-loop ASDTIC regulation control concept was implemented by using a common analog control signal processor and a novel digital control signal processor. This resulted in control circuit standardization and superior static and dynamic performance of the three dc-to-dc converters. Power components stress control, through active peak current limiting and recovery of switching losses, was applied to enhance reliability and converter efficiency.

23rd workshop on Advances in Analog Circuit Design

CERN Document Server

Baschirotto, Andrea; Makinwa, Kofi

2015-01-01

This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design.  Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.    • Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing; • Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; • Presents material in a tutorial-based format.

Principles of digital and analog communications

CERN Document Server

Gibson, Jerry D

1993-01-01

This textbook for the first course in communications covers analog and digital systems and emphasizes digital communications. It covers data transmission, signal space, optimal receivers, and pulse code modulation, and includes readable treatments of coded modulation and continuous phase modulation. Advanced mathematics is kept to a minimum-Fourier series, Fourier transforms, linear systems, random variables, and stochastic process are described thoroughly. It includes data compression of speech and images and a full chapter coverage of information theory, rate distortion theory and coded modulation. It relates digital communications theory to current practice and covers digital communications over band-width constrained channels, including pulse shaping and equilization. -- Dieser Text bezieht sich auf eine vergriffene oder nicht verfügbare Ausgabe dieses Titels.

Bandwidth tunable microwave photonic filter based on digital and analog modulation

Science.gov (United States)

Zhang, Qi; Zhang, Jie; Li, Qiang; Wang, Yubing; Sun, Xian; Dong, Wei; Zhang, Xindong

2018-05-01

A bandwidth tunable microwave photonic filter based on digital and analog modulation is proposed and experimentally demonstrated. The digital modulation is used to broaden the effective gain spectrum and the analog modulation is to get optical lines. By changing the symbol rate of data pattern, the bandwidth is tunable from 50 MHz to 700 MHz. The interval of optical lines is set according to the bandwidth of gain spectrum which is related to the symbol rate. Several times of bandwidth increase are achieved compared to a single analog modulation and the selectivity of the response is increased by 3.7 dB compared to a single digital modulation.

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

Science.gov (United States)

Quilligan, G.; Aslam, S.; DuMonthier, J.

2012-01-01

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Advances in Analog Circuit Design 2015

CERN Document Server

Baschirotto, Andrea; Harpe, Pieter

2016-01-01

This book is based on the 18 tutorials presented during the 24th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of efficient sensor interfaces and low-power RF systems. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development. ·         Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; ·         Presents material in a tutorial-based format; ·         Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing.

A 16-bit sigma-delta modulator applied in micro-machined inertial sensors

Science.gov (United States)

Honglin, Xu; Qiang, Fu; Hongna, Liu; Liang, Yin; Pengfei, Wang; Xiaowei, Liu

2014-04-01

A fourth-order low-distortion low-pass sigma-delta (ΣΔ) modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to decrease the nonlinearities and power consumption. The IC is implemented in a standard 0.6 μm CMOS technology and operates at a sampling frequency of 3.846 MHz. The chip area is 2.12 mm2 with 23 pads. The experimental results indicate a signal-to-noise ratio (SNR) of 100 dB and dynamic range (DR) of 103 dB at an oversampling rate (OSR) of 128 with the input signal amplitude of -3.88 dBFS at 9.8 kHz; the power consumption is 15 mW at a 5 V supply.

Mathematical Modeling and Digital Control of A Hybrid Switching Buck Converter

Directory of Open Access Journals (Sweden)

Muhammad Umar Abbasi

2017-06-01

Full Text Available The aim of this paper is to describe mathematical modeling and digital control of a hybrid switching buck converter. This converter belongs to a class of so called hybrid switching converters and contains a resonant capacitor, resonant inductor and a diode in addition to original buck converter components. The dc gain of this converter is shown to be independent of resonant branch parameters. Moreover the dc conversion ratio is derived for both ideal case and including main inductor dc resistance. Small signal model of the converter is derived and is shown to be similar to conventional buck converter. Simulation results in SIMPLIS Software as well as experimental results of digital control using an 8 bit STM microcontroller are presented. The potential advantages and applications of this converter are discussed.

Mismatch-shaping switching for two-capacitor DAC

DEFF Research Database (Denmark)

Steensgaard-Madsen, Jesper; Moon, U.; Temes, G.C.

1998-01-01

A mismatch-shaping scheme is proposed for a two-capacitor digital-to-analogue converter (DAC). It uses a delta-sigma loop for finding the optimal switching sequence for each input word. Simulations indicate that the scheme can be used for the realisation of DACs with 16 bit linearity and SNR...

Digitally Controlled Point of Load Converter with Very Fast Transient Response

DEFF Research Database (Denmark)

Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

2007-01-01

voltage mode control and very fast transient response. The DiSOM modulator is combined with a digital PID compensator algorithm is implemented in a hybrid CPLD/FPGA and is used to control a synchronous Buck converter, which is used in typical Point of Load applications. The computational time is only......This paper presents a new Digital Self-Oscillating Modulator (DiSOM) that allows the duty cycle to be changed instantly. The DiSOM modulator is shown to have variable switching that is a function of the duty cycle. Compared to a more traditional digital PWM modulator based on a counter...... and comparator the DiSOM modulator allows the sampling frequency of the output voltage control loop to be higher than the switching frequency of the power converter, typically a DC/DC converter. The features of the DiSOM modulator makes it possible to design a digitally controlled DC/DC converter with linear...

Epistemic Function and Ontology of Analog and Digital Images

Directory of Open Access Journals (Sweden)

Aleksandra Łukaszewicz Alcaraz

2016-01-01

Full Text Available The important epistemic function of photographic images is their active role in construction and reconstruction of our beliefs concerning the world and human identity, since we often consider photographs as presenting reality or even the Real itself. Because photography can convince people of how different social and ethnic groups and even they themselves look, documentary projects and the dissemination of photographic practices supported the transition from disciplinary society to the present-day society of control. While both analog and digital images are formed from the same basic materia, the ways in which this matter appears are distinctive. In the case of analog photography, we deal with physical and chemical matter, whereas with digital images we face electronic matter. Because digital photography allows endless modification of the image, we can no longer believe in the truthfulness of digital images.

Phase-locked loops. [in analog and digital circuits communication system

Science.gov (United States)

Gupta, S. C.

1975-01-01

An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented. The analog phase-locked loops are well documented in several books but discrete, analog-digital, and digital phase-locked loop work is scattered. Apart from discussing the various analysis, design, and application aspects of phase-locked loops, a number of references are given in the bibliography.

Analog and digital dividers for mass spectrometers

International Nuclear Information System (INIS)

Osipov, A.K.

1980-01-01

Errors of four different types of stress dividers used in statical mass-spectrometers for determination of mass number by accelerating stress are analyzed. The simplest flowsheet of the analog divider comprises operation amplifier, in the chain of the negative feedback of which a multiplication device on differential cascade is switched- in. This analog divider has high sensitivity to temperature and high error approximately 5%. Application of the multiplier on differential cascade with normalization permits to increase temperature stability and decrease the error up to 1%. Another type of the analog divider is a logarithmic divider the error of which is constant within the whole operation range and it constitutes 1-5%. The digital divider with a digital-analog transformer (DAT) has the error of +-0.015% which is determined by the error of detectors and resistance of keys in the locked state. Considered is the design of a divider based on transformation of the inlet stress into the time period. The error of the divider is determined in this case mainly by stress of the zero shift of the operation amplifier (it should be compensated) and relative threshold stability of the comparator triggering which equals (2-3)x10 -4 . It is noted that the divider with DAT application and the divider with the use of stress transformation within the time period are most perspective ones for statical mass-spectrometers [ru

Unified Digital Periodic Signal Filters for Power Converter Systems

DEFF Research Database (Denmark)

Yang, Yongheng; Xin, Zhen; Zhou, Keliang

2017-01-01

Periodic signal controllers like repetitive and resonant controllers have demonstrated much potential in the control of power electronic converters, where periodic signals (e.g., ac voltages and currents) can be precisely regulated to follow references. Beyond the control of periodic signals, ac...... signal processing (e.g., in synchronization and pre-filtering) is also very important for power converter systems. Hence, this paper serves to unify digital periodic signal filters so as to maximize their roles in power converter systems (e.g., enhance the control of ac signals). The unified digital...... periodic signal filters behave like a comb filter, but it can also be configured to selectively filter out the harmonics of interest (e.g., the odd-order harmonics in single-phase power converter systems). Moreover, a virtual variable-sampling-frequency unit delay that enables frequency adaptive periodic...

High Channel Count Time-to-Digital Converter and Lasercom Processor, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — High-channel-count, high-precision, and high-throughput time-to-digital converters (TDC) are needed to support detector arrays used in deep-space optical...

A radiation hardened digital fluxgate magnetometer for space applications

Science.gov (United States)

Miles, D. M.; Bennest, J. R.; Mann, I. R.; Millling, D. K.

2013-09-01

Space-based measurements of Earth's magnetic field are required to understand the plasma processes responsible for energising particles in the Van Allen radiation belts and influencing space weather. This paper describes a prototype fluxgate magnetometer instrument developed for the proposed Canadian Space Agency's (CSA) Outer Radiation Belt Injection, Transport, Acceleration and Loss Satellite (ORBITALS) mission and which has applications in other space and suborbital applications. The magnetometer is designed to survive and operate in the harsh environment of Earth's radiation belts and measure low-frequency magnetic waves, the magnetic signatures of current systems, and the static background magnetic field. The new instrument offers improved science data compared to its predecessors through two key design changes: direct digitisation of the sensor and digital feedback from two cascaded pulse-width modulators combined with analog temperature compensation. These provide an increase in measurement bandwidth up to 450 Hz with the potential to extend to at least 1500 Hz. The instrument can resolve 8 pT on a 65 000 nT field with a magnetic noise of less than 10 pT/√Hz at 1 Hz. This performance is comparable with other recent digital fluxgates for space applications, most of which use some form of sigma-delta (ΣΔ) modulation for feedback and omit analog temperature compensation. The prototype instrument was successfully tested and calibrated at the Natural Resources Canada Geomagnetics Laboratory.

Analog and digital appliance technology for the control and monitoring of space HVAC systems

Energy Technology Data Exchange (ETDEWEB)

Gyoeri, M

1987-01-01

Both analog and digital devices are expected to meet the required control functions. The analog control device meets this function by way of a complicated circuitry and wiring technology of varying sophistication. In the digital control by a preprogrammed microprocessor. Digital technology allows to use the copied programme in different devices. Any change in the control of a system can be implemented and met by a programme change in digital technology. In analog technology, this change involves a change in wiring. (orig./HW).

A 7 μW Offset- and Temperature-Compensated pH-to-Digital Converter

Directory of Open Access Journals (Sweden)

Saleh Heidary Shalmany

2017-01-01

Full Text Available This paper demonstrates a micropower offset- and temperature-compensated smart pH sensor, intended for use in battery-powered RFID systems that monitor the quality of perishable products. Low operation power is essential in such systems to enable autonomous logging of environmental parameters, such as the pH level, over extended periods of time using only a small, low-cost battery. The pH-sensing element in this work is an ion-sensitive extended-gate field-effect transistor (EGFET, which is incorporated in a low-power sensor front-end. The front-end outputs a pH-dependent voltage, which is then digitized by means of a co-integrated incremental delta-sigma ADC. To compensate for the offset and temperature cross-sensitivity of the EGFET, a compensation scheme using a calibration process and a temperature sensor has been devised. A prototype chip has been realized in a 0.16 μm CMOS process. It occupies 0.35 × 3.9 mm2 of die area and draws only 4 μA from a 1.8 V supply. Two different types of custom packaging have been used for measurement purposes. The pH sensor achieves a linearity of better than ±0.1 for pH values ranging from 4 to 10. The calibration and compensation scheme reduces errors due to temperature cross-sensitivity to less than ±0.1 in the temperature range of 6°C to 25°C.

Low-Power, Low-Voltage Resistance-to-Digital Converter for Sensing Applications

Directory of Open Access Journals (Sweden)

Sergey Y. YURISH

2016-09-01

Full Text Available IC (ASIP of Universal Sensors and Transducers Interface (USTI-MOB with low power consumption, working in the resistive measurement mode (one of 26 possible measuring modes is described in the article. The proposed IC has 20 W to 4.5 M W range of measurement, relative error< ±0.04 %, 0.85 mA supply current and 1.2 V supply voltage. The worst-case error of about< ±1.54 % is observed. IC has three popular serial interfaces: I2C, SPI and RS232/USB. Due to high metrological performance and technical characteristics the USTI- MOB is well suitable for such application as: sensor systems for IoT, wearable and mobile devices, and digital multimeters. The ICs can also work with any quasi-digital resistive converters, in which the resistance is converted to frequency, period, duty-cycle or pulse width.

The making of analog module for gamma camera interface

International Nuclear Information System (INIS)

Yulinarsari, Leli; Rl, Tjutju; Susila, Atang; Sukandar

2003-01-01

The making of an analog module for gamma camera has been conducted. For computerization of planar gamma camera 37 PMT it has been developed interface hardware technology and software between the planar gamma camera with PC. With this interface gamma camera image information (Originally analog signal) was changed to digital single, therefore processes of data acquisition, image quality increase and data analysis as well as data base processing can be conducted with the help of computers, there are three gamma camera main signals, i.e. X, Y and Z . This analog module makes digitation of analog signal X and Y from the gamma camera that conveys position information coming from the gamma camera crystal. Analog conversion to digital was conducted by 2 converters ADC 12 bit with conversion time 800 ns each, conversion procedure for each coordinate X and Y was synchronized using suitable strobe signal Z for information acceptance

Ultra-low power analog-digital converters for IoT

NARCIS (Netherlands)

Harpe, P.J.A.; Alioto, Massimo

2017-01-01

This chapter addresses ADCs for IoT nodes, which are needed to digitize sensor information before processing, storage or wireless transmission. ADCs are also required for the radio communication channel. This chapter focusses on successive approximation (SAR) ADCs, a popular architecture for IoT

Devices for measuring the capacitance of micromechanical sensors of mobile robots navigation systems and its deviation from the nominal value

Directory of Open Access Journals (Sweden)

Rudyk A.V.

2016-12-01

Full Text Available The article describes methods of constructing devices for measuring the capacitance of micromechanical sensors (accelerometers and gyros mobile robots navigation systems and its deviation from the nominal value. A modified diagram of a sigma-delta modulator is offered. It realizes a direct connection capacitive sensor connection to the sigma-delta converter, as a result increased resolution, accuracy and linearity of the conversion. This interface is insensitive to the value of capacitance between the sensor leads and common wire or leakage current to a common wire. Variants of expansion as the nominal of the test capacity and the range of conversion of the relative deviation of the nominal capacity using two integrators are offered. The versions of circuit implementation devices for measuring the capacitance deviation of a micromechanical sensor from the nominal value are designed on the basis of the completed integrated circuit AD7745 / AD7746 and AD7747 of Analog Devices, CAV414 / 424 firm Analog Microelectronics and precision analog microcontroller ADuCM360 / CM361 company ARM Limited.

ePix: a class of architectures for second generation LCLS cameras

International Nuclear Information System (INIS)

Dragone, A; Caragiulo, P; Markovic, B; Herbst, R; Reese, B; Herrmann, S C; Hart, P A; Segal, J; Carini, G A; Kenney, C J; Haller, G

2014-01-01

ePix is a novel class of ASIC architectures, based on a common platform, optimized to build modular scalable detectors for LCLS. The platform architecture is composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog-to-digital converters per column. It also implements a dedicated control interface and all the required support electronics to perform configuration, calibration and readout of the matrix. Based on this platform a class of front-end ASICs and several camera modules, meeting different requirements, can be developed by designing specific pixel architectures. This approach reduces development time and expands the possibility of integration of detector modules with different size, shape or functionality in the same camera. The ePix platform is currently under development together with the first two integrating pixel architectures: ePix100 dedicated to ultra low noise applications and ePix10k for high dynamic range applications.

A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter

NARCIS (Netherlands)

Kashmiri, S.M.; Xia, S.; Makinwa, K.A.A.

2009-01-01

This paper describes the design of a CMOS temperature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread

The C-Terminal RpoN Domain of sigma54 Forms an unpredictedHelix-Turn-Helix Motif Similar to domains of sigma70

Energy Technology Data Exchange (ETDEWEB)

Doucleff, Michaeleen; Malak, Lawrence T.; Pelton, Jeffrey G.; Wemmer, David E.

2005-11-01

The ''{delta}'' subunit of prokaryotic RNA-polymerase allows gene-specific transcription initiation. Two {sigma} families have been identified, {sigma}{sup 70} and {sigma}{sup 54}, which use distinct mechanisms to initiate transcription and share no detectable sequence homology. Although the {sigma}{sup 70}-type factors have been well characterized structurally by x-ray crystallography, no high-resolution structural information is available for the {sigma}{sup 54}-type factors. Here we present the NMR derived structure of the C-terminal domain of {sigma}{sup 54} from Aquifex aeolicus. This domain (Thr323 to Gly389), which contains the highly conserved RpoN box sequence, consists of a poorly structured N-terminal tail followed by a three-helix bundle, which is surprisingly similar to domains of the {sigma}{sup 70}-type proteins. Residues of the RpoN box, which have previously been shown to be critical for DNA binding, form the second helix of an unpredicted helix-turn-helix motif. This structure's homology with other DNA binding proteins, combined with previous biochemical data, suggest how the C-terminal domain of {sigma}{sup 54} binds to DNA.

On automatic synthesis of analog/digital circuits

Energy Technology Data Exchange (ETDEWEB)

Beiu, V.

1998-12-31

The paper builds on a recent explicit numerical algorithm for Kolmogorov`s superpositions, and will show that in order to synthesize minimum size (i.e., size-optimal) circuits for implementing any Boolean function, the nonlinear activation function of the gates has to be the identity function. Because classical and--or implementations, as well as threshold gate implementations require exponential size, it follows that size-optimal solutions for implementing arbitrary Boolean functions can be obtained using analog (or mixed analog/digital) circuits. Conclusions and several comments are ending the paper.

Multichannel analog temperature sensing system

International Nuclear Information System (INIS)

Gribble, R.

1985-08-01

A multichannel system that protects the numerous and costly water-cooled magnet coils on the translation section of the FRX-C/T magnetic fusion experiment is described. The system comprises a thermistor for each coil, a constant current circuit for each thermistor, and a multichannel analog-to-digital converter interfaced to the computer

The Transition from Analog to Digital Mammography: Overall Considerations

OpenAIRE

A. Sardo

2007-01-01

In the last decades a continuous growth of the infor-matics process around the world has been observed: paper documents, data, images…, converted into a “digital format” allow an easier and safer manage-ment, making possible its compatibility and access to internet networking. This migration confirms the huge technology progresses made especially in the image capture ways: from photography to graphic arts, from movie to healthcare imaging, where the end user/radiologist requires, at least, a ...

Design of a general purpose (RS-232C) analog-to-digital data converter

International Nuclear Information System (INIS)

Ali, Q.

1995-01-01

The purpose of this project is to design a general purpose hardware that interfaces analog devices with any desirable computer supporting the RS-232 interface. The hardware incorporates bidirectional data transmission at 1,200 bps, 2,400 bps, 4800 bps, 9,600 bps, 19,200 pbs and 38400 bps. The communication / processing software has been written in C language that incorporates the idea of the potability of the software from one environment to the other. (author)

Interpolating by a factor of 3 in low-voltage low-power ∑Δ DAC

DEFF Research Database (Denmark)

Pracný, Peter; Jørgensen, Ivan Harald Holger; Bruun, Erik

2014-01-01

This paper presents the power optimization of a sigma-delta (RD) modulator based digital-to-analog converter (DAC) for hearing aid audio back-end application. In a number of state-of-the-art publications the oversampling ratio (OSR) of the RD modulator is chosen as a factor of integer power of two...... by a factor of 3 are investigated. This new design freedom is used to lower the operating frequency of the whole back-end and save considerable amount of power. It is shown that the figure of- merit of such designs can be lower than designs using oversampling by a factor of integer powers of two. The same...... optimization approach can be used for other low voltage low power portable audio applications (mobile phones, notebook computers etc.)....

Miniaturized digital fluxgate magnetometer for small spacecraft applications

International Nuclear Information System (INIS)

Forslund, Åke; Ivchenko, Nickolay; Olsson, Göran; Edberg, Terry; Belyayev, Serhiy; Marusenkov, Andriy

2008-01-01

A novel design of an Earth field digital fluxgate magnetometer is presented, the small magnetometer in low-mass experiment (SMILE). The combination of a number of new techniques results in significant miniaturization of both sensor and electronics. The design uses a sensor with volume compensation, combining three dual rod cores in a Macor® cube with the side dimension of 20 mm. Use of volume compensation provides high geometrical stability of the axes and improved performance compared to component compensated sensors. The sensor is operated at an excitation frequency of 8 kHz. Most of the instrument functionality is combined in a digital signal processing core, implemented in a field programmable gate array (FPGA). The pick-up signal is digitized after amplification and filtering, and values of compensation currents for each of the axes are determined by a digital correlation algorithm, equivalent to a matched filter, and are fed to a hybrid pulse-width modulation/delta-sigma digital-to-analogue converter driving the currents through the compensation coils. Using digital design makes the instrument very flexible, reduces power consumption and opens possibilities for the customization of the operation modes. The current implementation of the design is based on commercial off-the-shelf components. A calibration of the SMILE instrument was carried out at the Nurmijärvi Geophysical Observatory, showing high linearity (within 6 nT on the whole ±50 µT scale), good orthogonality (22 arcmin) and very good temperature stability of the axes

Time-to-digital converter for a time-correlation analyzer

International Nuclear Information System (INIS)

Kumpf, S.

1979-01-01

An electronic circuit operating as a time-to-digital converter is described. It receives pulses from eight n-detectors on eight input channels which are converted into the first half of a 16-bit word. The work called 'label' is indicating the channel on which an event has arrived. Contemporarily a crystal controlled four stage 4-bit binary counter gives the time when the event arrives expressed in the form of a second 16-bit work called 'time'. These two words are fed via a FIFO-buffer and a DMA-control to a very fast minicomputer Miproc 16 from Plessey-Micro-Systems with a cycle time of 250 ns. The circuit is built in TTL-technique on two double Europa-format cards and is built into the card bay of the Miproc 16 and acts as a peripheral device

Signal Digitizer and Cross-Correlation Application Specific Integrated Circuit

Science.gov (United States)

Baranauskas, Dalius (Inventor); Baranauskas, Gytis (Inventor); Zelenin, Denis (Inventor); Kangaslahti, Pekka (Inventor); Tanner, Alan B. (Inventor); Lim, Boon H. (Inventor)

2017-01-01

According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.

Restructuring of a flash A/D converter to improve SEU rad tolerance

International Nuclear Information System (INIS)

Monnier, T.; Roche, R.M.; Corbiere, F.

1999-01-01

The purpose of this work is to present how structural changes in the conventional Flash Analog to Digital Converter can secure it for a harsh radiation environment. The method consists in a coupling of two complementary techniques: a robust reconfiguration of the logical structure joined to a design hardening of the individual blocks. This approach preserves the ADC performances. (authors)

A simple method of digitizing analog scintigrams for quantification and digital archiving. Eine einfache Methode der Digitalisierung von Analogszintigrammen zur Quantifizierung und digitalen Archivierung

Energy Technology Data Exchange (ETDEWEB)

Schramm, M. (Klinik fuer Nuklearmedizin, Kiel Univ. (Germany)); Kaempfer, B. (Klinik fuer Nuklearmedizin, Kiel Univ. (Germany)); Wolf, H. (Klinik fuer Nuklearmedizin, Kiel Univ. (Germany)); Clausen, M. (Klinik fuer Nuklearmedizin, Kiel Univ. (Germany)); Wendhausen, H. (Klinik fuer Nuklearmedizin, Kiel Univ. (Germany)); Henze, E. (Klinik fuer Nuklearmedizin, Kiel Univ. (Germany))

1993-02-01

This study was undertaken to evaluate a quick, reliable and cheap method of digitizing analog scintigrams. 40 whole-body bone scintigrams were obtained simultaneously in analog and genuine digital format. The analog scans on X-ray film were then digitized seecondarily by three different methods: 300 dpi flatbed scanning, high-resolution camera scanning and camcorder recording. A simple exposure approach using a light box, a cheap camcorder, a PC and image grabber hard- and software proved to be optimal. Visual interpretation showed no differences in clinical findings when comparing the analog images with their secondarily digitized counterparts. To test the possibility of quantification, 126 equivalent ROIs were drawn both in the genuine digital and the secondarily digitized images. Comparing the ROI count to whole-body count percentage of the corresponding ROIs showed the correlation to be linear. The evaluation of phantom studies showed the linear correlation to be true within a wide activity range. Thus, secondary digitalization of analog scintigrams is an easy, cheap and reliable method of archiving images and allows secondary digital quantification. (orig.)

Development of reconfigurable analog and digital circuits for plasma diagnostics measurement systems

International Nuclear Information System (INIS)

Srivastava, Amit Kumar; Sharma, Atish; Raval, Tushar

2009-01-01

In long pulse discharge tokamak, a large number of diagnostic channels are being used to understand the complex behavior of plasma. Different diagnostics demand different types of analog and digital processing for plasma parameters measurement. This leads to variable requirements of signal processing for diagnostic measurement. For such types of requirements, we have developed hardware with reconfigurable electronic devices, which provide flexible solution for rapid development of measurement system. Here the analog processing is achieved by Field Programmable Analog Array (FPAA) integrated circuit while reconfigurable digital devices (CPLD/FPGA) achieve digital processing. FPAA's provide an ideal integrated platform for implementing low to medium complexity analog signal processing. With dynamic reconfigurability, the functionality of the FPAA can be reconfigured in-system by the designer or on the fly by a microprocessor. This feature is quite useful to manipulate the tuning or the construction of any part of the analog circuit without interrupting operation of the FPAA, thus maintaining system integrity. The hardware operation control logic circuits are configured in the reconfigurable digital devices (CPLD/FPGA) to control proper hardware functioning. These reconfigurable devices provide the design flexibility and save the component space on the board. It also provides the flexibility for various setting through software. The circuit controlling commands are either issued by computer/processor or generated by circuit itself. (author)

Design Strategy for a Pipelined ADC Employing Digital Post-correction

NARCIS (Netherlands)

Harpe, P.J.A.; Zanikopoulos, A.; Hegt, J.A.; Roermund, van A.H.M.

2004-01-01

This paper describes how the usage of digital post-correction techniques in pipelined analog-to-digital converters (ADC's) can be exploited optimally during the design-phase of the converter. It is known that post-correction algorithms reduce the influence of several cir- cuit impairments on the

A Modified Design of a Thermocouple Based Digital Temperature Indicator with Opto-Isolation

Directory of Open Access Journals (Sweden)

S. C. BERA

2008-01-01

Full Text Available In the conventional thermocouple based digital temperature indicator the millivolt signal obtained from a thermocouple is first amplified and then converted into a digital signal by using analog-to-digital converter (ADC. This digital signal is then indicated as digital display of temperature using digital counter circuit or microprocessor/microcontroller based circuitry. In the present paper a modified AD conversion technique along with opto-isolation is used to indicate digitally the temperature without using any conventional analog-to-digital converter. The theory and design of the measuring technique are described in the paper. The non-linearity of thermocouple is eliminated by using look-up table within software program. The performance of the circuit has been experimentally tested by using mV input signal instead of a thermocouple as well as using a K-type thermocouple. The experimental results are reported in the paper.

[Trial digitalization of analog-data obtained from the AutoAnalyzer].

Science.gov (United States)

Omori, S

2000-10-01

The AutoAnalzer(Basic Model) manufactured on Technicon corporation was a very useful instrument for clinical laboratory automation, but it was necessary to convert the data obtained from the instrument to digital values used the chart reader. This was very troublesome and there was apprehension that there would be errors in A-D conversion. We tried converting data obtained from the AutoAnalzer to a digital value by on-line connection of the instruments with minicomputers(LINC-8 and FACOM-R). The output of the recorder was converted to voltage(0 to 100 V) using a potentiometer, quantitated(0 to 1.000) by the A-D converter attached to LINC-8, and processed by the minicomputer. The control-box was an experimental device mainly designed for the convenience of users. The functions of the control-box were designated analytical items, No. of A-D converters, start and stop of the AutoAnalzer operation to the minicomputer. Employing the control-box, a technician operated this system freely, without direct computer operation. We established a generally satisfactory system for clinical laboratory automation using the minicomputer.

High-Speed Universal Frequency-to-Digital Converter for Quasi-Digital Sensors and Transducers

Directory of Open Access Journals (Sweden)

Sergey Y. Yurish

2007-06-01

Full Text Available New fast, accurate universal integrated frequency-to-digital converter (UFDC-1M-16 is described in the article. It is based on the novel patented modified method of the dependent count and has non-redundant conversion time from 6.25 ms to 6.25 ms for 1 to 0.001 % relative errors respectively, comparable with conversion time for successive-approximation and S-D ADC. The IC can work with different sensors, transducers and encoders, which have frequency, period, duty-cycle, PWM, phase shift, pulse number, etc. output.

Hybrid digital-analog coding with bandwidth expansion for correlated Gaussian sources under Rayleigh fading

Science.gov (United States)

Yahampath, Pradeepa

2017-12-01

Consider communicating a correlated Gaussian source over a Rayleigh fading channel with no knowledge of the channel signal-to-noise ratio (CSNR) at the transmitter. In this case, a digital system cannot be optimal for a range of CSNRs. Analog transmission however is optimal at all CSNRs, if the source and channel are memoryless and bandwidth matched. This paper presents new hybrid digital-analog (HDA) systems for sources with memory and channels with bandwidth expansion, which outperform both digital-only and analog-only systems over a wide range of CSNRs. The digital part is either a predictive quantizer or a transform code, used to achieve a coding gain. Analog part uses linear encoding to transmit the quantization error which improves the performance under CSNR variations. The hybrid encoder is optimized to achieve the minimum AMMSE (average minimum mean square error) over the CSNR distribution. To this end, analytical expressions are derived for the AMMSE of asymptotically optimal systems. It is shown that the outage CSNR of the channel code and the analog-digital power allocation must be jointly optimized to achieve the minimum AMMSE. In the case of HDA predictive quantization, a simple algorithm is presented to solve the optimization problem. Experimental results are presented for both Gauss-Markov sources and speech signals.

Performance Effects of Display Incogruity in a Digital and Analog Clock Reading Task

Science.gov (United States)

Comstock, J. Raymond, Jr.; Derks, Peter L.

2004-01-01

In an era of increasing automation, it is important to design displays and input devices that minimize human error. In this context, information concerning the human response to the detection of incongruous information is important. Such incongruous information can be operationalized as unexpected (perhaps erroneous) information on which a decision by the human or operation by an automated system is based. In the aviation environment, decision making when faced with inadequate, incomplete, or incongruous information may occur in a failure scenario. An additional challenge facing the human operator in automated environments is maintaining alertness or vigilance. The vigilance issue is of particular concern as a factor that may interact with performance when faced with inadequate, incomplete, or incongruous information. From the literature on eye-scan behavior we know that the time spent looking at a particular display or indicator is a function of the type of information one is trying to discern from the display. For example, quick glances are all it takes for confirming that an indicator is in a normal position or range, whereas a continuous look of several seconds may be required for confirmation that a complex control input is having the desired effect. Important to consider is that while an extended look takes place, visual input from other sources may be missed. Much like an extended look, the interpretation of incongruous information may require extra time. The present experiment was designed to explore the performance consequences of a decision making task when incongruous information was presented. For this experiment a display incongruity was created on a subset of trials of a clock reading laboratory task. Display incongruity was made possible through presentation of 'impossible' times (e.g. 1:65 or 11:90). Subjects made 'same' 'different' decisions and keyboard responses to pairings of Analog-Analog (AA), Digital-Digital (DD), and Analog- Digital (AD

Digital control card based on digital signal processor

International Nuclear Information System (INIS)

Hou Shigang; Yin Zhiguo; Xia Le

2008-01-01

A digital control card based on digital signal processor was developed. Two Freescale DSP-56303 processors were utilized to achieve 3 channels proportional- integral-differential regulations. The card offers high flexibility for 100 MeV cyclotron RF system development. It was used as feedback controller in low level radio frequency control prototype, with the feedback gain parameters continuously adjustable. By using high precision analog to digital converter with 500 kHz sampling rate, a regulation bandwidth of 20 kHz was achieved. (authors)

Signal-to-noise ratio estimation in digital computer simulation of lowpass and bandpass systems with applications to analog and digital communications, volume 3

Science.gov (United States)

Tranter, W. H.; Turner, M. D.

1977-01-01

Techniques are developed to estimate power gain, delay, signal-to-noise ratio, and mean square error in digital computer simulations of lowpass and bandpass systems. The techniques are applied to analog and digital communications. The signal-to-noise ratio estimates are shown to be maximum likelihood estimates in additive white Gaussian noise. The methods are seen to be especially useful for digital communication systems where the mapping from the signal-to-noise ratio to the error probability can be obtained. Simulation results show the techniques developed to be accurate and quite versatile in evaluating the performance of many systems through digital computer simulation.

Digital to analog resistive switching transition induced by graphene buffer layer in strontium titanate based devices.

Science.gov (United States)

Wan, Tao; Qu, Bo; Du, Haiwei; Lin, Xi; Lin, Qianru; Wang, Da-Wei; Cazorla, Claudio; Li, Sean; Liu, Sidong; Chu, Dewei

2018-02-15

Resistive switching behaviour can be classified into digital and analog switching based on its abrupt and gradual resistance change characteristics. Realizing the transition from digital to analog switching in the same device is essential for understanding and controlling the performance of the devices with various switching mechanisms. Here, we investigate the resistive switching in a device made with strontium titanate (SrTiO 3 ) nanoparticles using X-ray diffractometry, scanning electron microscopy, Raman spectroscopy, and direct electrical measurements. It is found that the well-known rupture/formation of Ag filaments is responsible for the digital switching in the device with Ag as the top electrode. To modulate the switching performance, we insert a reduced graphene oxide layer between SrTiO 3 and the bottom FTO electrode owing to its good barrier property for the diffusion of Ag ions and high out-of-plane resistance. In this case, resistive switching is changed from digital to analog as determined by the modulation of interfacial resistance under applied voltage. Based on that controllable resistance, potentiation and depression behaviours are implemented as well. This study opens up new ways for the design of multifunctional devices which are promising for memory and neuromorphic computing applications. Copyright © 2017 Elsevier Inc. All rights reserved.

Comparison of digital selenium radiography with an analog screen-film system in the diagnostic process of pneumoconiosis according to ILO classification

International Nuclear Information System (INIS)

Zaehringer, M.; Winnekendonk, G.; Gossmann, A.; Krueger, K.; Krug, B.

2001-01-01

Purpose: The aim of the study was to determine the diagnostic value of digital selenium radiography in patients with pneumoconiosis. For this purpose chest X-rays by digital selenium radiography and analog screen-film system were compared according to the ILO classification of pneumoconiosis. Method: After approval of the study by the local ethic commission and the Federal German Office for Radiation Protection 50 patients were subjected to X-rays by digital selenium radiography (Thoravision; Philips Medical Systems, Hamburg, Germany) and analog screen-film system of the same day within the scope of an industrial medicine preventive checkup. Four investigators rated the chest X-rays according to the ILO classification of pneumoconiosis. Results: The findings demonstrated by chest X-rays according to ILO classification were rated similar by digital selenium radiography and analog screen film systems. Image quality of the digital pictures was rated significantly better. Conclusion: The use of digital selenium radiography in evaluating chest X-rays according to the ILO classification does not result in over- or underestimation of pulmonary pathologies. Hence, in the diagnosis of pneumoconiosis, digital selenium radiography can replace the tested analog screen-film system. (orig.) [de

CMOS time-to-digital converters for mixed-mode signal processing

OpenAIRE

Fei Yuan

2014-01-01

This study provides an in-depth review of the principles, architectures and design techniques of CMOS time-to-digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs. Sampling TDCs including direct-counter TDCs, tapped delay-line TDCs, pulse-shrinking delay-line TDCs, cyclic pulse-shrinking TDCs, direct-counter TDCs with interpolation, vernier TDCs, flash TDCs, successive approximation TDCs an...

Simple Digital Control of a Two-Stage PFC Converter Using DSPIC30F Microprocessor

DEFF Research Database (Denmark)

Török, Lajos; Munk-Nielsen, Stig

2010-01-01

The use of dsPIC digital signal controllers (DSC) in Switch Mode Power Supply (SMPS) applications opens new perspectives for cheap and flexible digital control solutions. This paper presents the digital control of a two stage power factor corrector (PFC) converter. The PFC circuit is designed...... and built for 70W rated output power. Average current mode control for boost converter and current programmed control for forward converter are implemented on a dsPIC30F1010. Pulse Width Modulation (PWM) technique is used to drive the switching MOSFETs. Results show that digital solutions with ds...

Digitally Controlled Offline Converter with Galvanic Isolation Based on an 8-bit Microcontroller

DEFF Research Database (Denmark)

Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

2007-01-01

This paper presents an offline AC/DC converter with digital control and galvanic isolation that can be implemented using cheap commercially available components. An ATMEL ATTiny26 8-bit microcontroller is used to control the converter. The microcontroller is placed on the secondary side of the co......This paper presents an offline AC/DC converter with digital control and galvanic isolation that can be implemented using cheap commercially available components. An ATMEL ATTiny26 8-bit microcontroller is used to control the converter. The microcontroller is placed on the secondary side...

Comparative study of digital laser film and analog paper image recordings

International Nuclear Information System (INIS)

Lee, K.R.; Cox, G.G.; Templeton, A.W.; Preston, D.F.; Anderson, W.H.; Hensley, K.S.; Dwyer, S.J.

1987-01-01

The increase in the use of various imaging modalities demands higher quality and more efficacious analog image recordings. Laser electronic recordings with digital array prints of 4,000 x 5,000 x 12 bits obtained using laser-sensitive film or paper are being evaluated. Dry silver paper recordings are being improved and evaluated. High-resolution paper dot printers are being studied to determine their gray-scale capabilities. The authors evaluated the image quality, costs, clinical utilization, and acceptability of CT scans, MR images, digital subtraction angiograms, digital radiographs, and radionuclide scans recorded by seven different printers (three laser, three silver paper, and one dot) and compared the same features in conventional film recording. This exhibit outlines the technical developments and instrumentation of digital laser film and analog paper recorders and presents the results of the study

Frequency to digital converter for IUAC Linac control system

International Nuclear Information System (INIS)

Jain, Mamta; Subramaiam, E.T.; Sahu, B.K.

2015-01-01

A frequency to digital converter CAMAC module has been designed and developed for LINAC control systems. This module is used to see the frequency difference of master clock and the resonator frequency digitally without using the oscilloscope. Later on this can be used for automatic tuning and locking of the cavities using piezoelectric actuator based tunner control. This module has eight independent channels to fulfill the need of all the eight cavities of the cryostat. A Schmitt trigger along with level converaccepts almost any form of pulse train, with 30 Vp-p. The time period is measured by counters clocked from a high resolution clock (10 MHz +/- 250 ps). The counter values are cross checked at both the input levels. Frequency is obtained from the computed time period by a special divisor core implemented inside the FPGA. The major task was the implementation of eight individual divisor cores and routing inside one Spartan 3s500E FPGA chip

'Six sigma approach' - an objective strategy in digital assessment of postoperative air leaks: a prospective randomised study.

Science.gov (United States)

Bertolaccini, Luca; Rizzardi, Giovanna; Filice, Mary Jo; Terzi, Alberto

2011-05-01

Until now, only way to report air leaks (ALs) has been with an analogue score in an inherently subjective manner. The Six Sigma quality improvement methodology is a data-driven approach applicable to evaluate the quality of the quantification method of repetitive procedures. We applied the Six Sigma concept to improve the process of AL evaluation. A digital device for AL measurement (Drentech PALM, Redax S.r.l., Mirandola (MO), Italy) was applied to 49 consecutive patients, who underwent pulmonary intervention, compared with a similar population with classical chest drainage. Data recorded were postoperative AL, chest-tube removal days, number of chest roentgenograms, hospital length of stay; device setup time, average time rating AL and patient satisfaction. Bivariable comparisons were made using the Mann-Whitney test, the χ² test and Fisher's exact test. Analysis of quality was conducted using the Six Sigma methodology. There were no significant differences regarding AL (p=0.075), although not statistically significant; there was a reduction of postoperative chest X-rays (four vs five) and of hospital length of stay (6.5 vs 7.1 days); and a marginally significant difference was found between chest-tube removal days (p=0.056). There were significant differences regarding device setup time (p=0.001), average time rating AL (p=0.001), inter-observer variability (p=0.001) and patient satisfaction (p=0.002). Six Sigma analyses revealed accurate assessment of AL. Continuous digital measurement of AL reduces degree of variability of AL score, gives more assurance for tube removal, and reports AL without the apprehension of observer error. Efficiency and effectiveness improved with the use of a digital device. We have noted that the AL curves depict actually sealing of AL. The clinical importance of AL curves requires further study. Copyright © 2010 European Association for Cardio-Thoracic Surgery. Published by Elsevier B.V. All rights reserved.

Digitally assisted analog beamforming for millimeter-wave communication

NARCIS (Netherlands)

Kokkeler, Andre B.J.; Smit, Gerardus Johannes Maria

2015-01-01

The paper addresses the research question on how digital beamsteering algorithms can be combined with analog beamforming in the context of millimeter-wave communication for next generation (5G) cellular systems. Key is the use of coarse quantisation of the individual antenna signals next to the

Real-time digital x-ray subtraction imaging

International Nuclear Information System (INIS)

Mistretta, C.A.; Kruger, R.A.; Houk, T.L.

1982-01-01

A method of producing visible difference images derived from an x-ray image of an anatomical subject is described. X-rays are directed through the subject, and the image is converted into television fields comprising trains of analog video signals. The analog signals are converted into digital signals, which are then integrated over a predetermined time corresponding to several television fields. Difference video signals are produced by performing a subtraction between the ongoing video signals and the corresponding integrated signals, and are converted into visible television difference images representing changes in the x-ray image

Sampled data CT system including analog filter and compensating digital filter

International Nuclear Information System (INIS)

Glover, G. H.; DallaPiazza, D. G.; Pelc, N. J.

1985-01-01

A CT scanner in which the amount of x-ray information acquired per unit time is substantially increased by using a continuous-on x-ray source and a sampled data system with the detector. An analog filter is used in the sampling system for band limiting the detector signal below the highest frequency of interest, but is a practically realizable filter and is therefore non-ideal. A digital filter is applied to the detector data after digitization to compensate for the characteristics of the analog filter, and to provide an overall filter characteristic more nearly like the ideal

Reconfigurable Bandpass Sigma-Delta Modulator With Programmable NTF for Low-IF Multi-Mode Receivers

DEFF Research Database (Denmark)

Zhang, Ke; Mikkelsen, Jan H.; Shen, Ming

2012-01-01

transfer function of the loop while still maintaining stability. Compared with conventional multi-mode BPSDM, employing cascade structures and multi-bit sub-ADCs, the proposed modulator features many attractive advantages, such as (1) avoiding coefficient mismatch between analog and digital components...

Implementation of high-resolution time-to-digital converter in 8-bit microcontrollers.

Science.gov (United States)

Bengtsson, Lars E

2012-04-01

This paper will demonstrate how a time-to-digital converter (TDC) with sub-nanosecond resolution can be implemented into an 8-bit microcontroller using so called "direct" methods. This means that a TDC is created using only five bidirectional digital input-output-pins of a microcontroller and a few passive components (two resistors, a capacitor, and a diode). We will demonstrate how a TDC for the range 1-10 μs is implemented with 0.17 ns resolution. This work will also show how to linearize the output by combining look-up tables and interpolation. © 2012 American Institute of Physics

Some important aspects of the amplitude, charge and shape analog signals digitization in nuclear physics experiment

International Nuclear Information System (INIS)

Kulka, Z.

1995-01-01

One of the fundamental reasons of the special requirements concerning analog-to-digital converters (ADC's) used in nuclear experimental physics, especially in nuclear spectroscopy, in comparison to the conventional ADC's is a fact that they are utilized for continuous distribution measurements which are the nuclear radiation spectra. The ADC's used for distribution registration in form of amplitude or charge histogram spectra should have the differential linearity of two orders of magnitude better than that for conventional ADC's. Moreover, the problem of achievement the acceptable differential linearity (as well as stability) in nuclear spectroscopy is much more complicated because high resolution and high speed of the converters are also required. The first requirement comes out from application of semiconductor detectors, the second one comes from the statistical character of the nuclear processes, as well as, a necessity of collection of huge amount of nuclear data - often in a short time. In this report the influence of the specific needs of the nuclear experiments on the conversion methods selection and construction principles of the pulse ADC's is analyzed. Focus is taken on these ADC's which are used mainly to digital amplitude and charge detector signals measurements in nuclear spectroscopy. Based on the chosen examples of different types of ADC's it is shown how to obtain the required metrological parameters by using enlarged converter's structures and proper choice of the electronics components. In addition, a problem of the detector signals shape measurements in particle physics using the high speed flash ADC's is also discussed. (author). 196 refs, 99 figs, 7 tabs

Polarized antiquark flavor asymmetry DELTA anti u(x)-DELTA anti d(x) and the pion cloud

CERN Document Server

Fries, R J; Weiss, C

2003-01-01

The flavor asymmetry of the unpolarized antiquark distributions in the proton, anti u(x)- anti d(x)0. Using a simple chiral linear sigma model as an example, we demonstrate that in the meson cloud picture a large positive DELTA anti u(x)-DELTA anti d(x) can be obtained from pi-sigma interference contributions. This calls into question previous estimates based on rho-meson contributions alone, and indicates how the results of the meson cloud picture may be reconciled with those of quark-based models. (orig.)

Converting Topographic Maps into Digital Form to Aid in Archeological Research in the Peten, Guatemala

Science.gov (United States)

Aldrich, Serena R.

1999-01-01

The purpose of my project was to convert a topographical map into digital form so that the data can be manipulated and easily accessed in the field. With the data in this particular format, Dr. Sever and his colleagues can highlight the specific features of the landscape that they require for their research of the ancient Mayan civilization. Digital elevation models (DEMs) can also be created from the digitized contour features adding another dimension to their research.

Energy-Efficient Capacitance-to-Digital Converters for Smart Sensor Applications

KAUST Repository

Alhoshany, Abdulaziz

2017-12-01

One of the key requirements in the design of wireless sensor nodes and miniature biomedical devices is energy efficiency. For a sensor node, which is a sensor and readout circuit, to survive on limited energy sources such as a battery or harvested energy, its energy consumption should be minimized. Capacitive sensors are candidates for use in energy-constrained applications, as they do not consume static power and can be used in a wide range of applications to measure different physical, chemical or biological quantities. However, the energy consumption is dominated by the capacitive interface circuit, i.e. the capacitance-to-digital converter (CDC). Several energy-efficient CDC architectures are introduced in this dissertation to meet the demand for high resolution and energy efficiency in smart capacitive sensors. First, we propose an energy-efficient CDC based on a differential successive-approximation data converter. The proposed differential CDC employs an energy-efficient operational transconductance amplifier (OTA) based on an inverter. A wide capacitance range with fine absolute resolution is implemented in the proposed coarse-fine DAC architecture which saves 89% of silicon area. The proposed CDC achieves an energy efficiency figure-of-merit () of 45.8fJ/step, which is the best reported energy efficiency to date. Second, we propose an energy efficient CDC for high-precision capacitive resolution by using oversampling and noise shaping. The proposed CDC achieves 150 aF absolute resolution and an energy efficiency of 187fJ/conversion-step which outperforms state of the art high-precision differential CDCs. In the third and last part, we propose an in-vitro cancer diagnostic biosensor-CMOS platform for low-power, rapid detection, and low cost. The introduced platform is the first to demonstrate the ability to screen and quantify the spermidine/spermine N1 acetyltransferase (SSAT) enzyme which reveals the presence of early-stage cancer, on the surface of a

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation.

Science.gov (United States)

Dei, Michele; Sutula, Stepan; Cisneros, Jose; Pun, Ernesto; Jansen, Richard Jan Engel; Terés, Lluís; Serra-Graells, Francisco

2017-06-02

Infrared imaging technology, used both to study deep-space bodies' radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm 2 chip integrated in a standard 0.18-µm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping,analogcalibration,nordigitalcompensationtechnique. Whencoupledtoa2048×2048 IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW.

Digitization errors using digital charge division positionsensitive detectors

International Nuclear Information System (INIS)

Berliner, R.; Mildner, D.F.R.; Pringle, O.A.

1981-01-01

The data acquisition speed and electronic stability of a charge division position-sensitive detector may be improved by using digital signal processing with a table look-up high speed multiply to form the charge division quotient. This digitization process introduces a positional quantization difficulty which reduces the detector position sensitivity. The degree of the digitization error is dependent on the pulse height spectrum of the detector and on the resolution or dynamic range of the system analog-to-digital converters. The effects have been investigated analytically and by computer simulation. The optimum algorithm for position sensing determination using 8-bit digitization and arithmetic has a digitization error of less than 1%. (orig.)

Project Birdseye Aerial Photograph Collection: Digital and Analog Materials

Data.gov (United States)

National Oceanic and Atmospheric Administration, Department of Commerce — This collection consists of both analog and digital aerial photographs from Arctic areas in and around Baffin Bay, the Labrador Sea, the Arctic Ocean, the Beaufort...

4 Channel Digital Down Converter – DDC (EDA-00991)

CERN Document Server

BLAS, A; DELONG, J (BNL)

2012-01-01

A novel rf beam control architecture has been successfully tested in the LEIR synchrotron. The design is based on a VME 64X carrier board, including a DSP (digital signal processor), into which different daughter cards can be plugged in. The DDC (Digital Down Converter) is one of them. Hardware wise it has the features of a four-channel ADC (analogue-to-digital converter) which outputs drive a powerful FPGA (field programmable logic array); the latter is connected to the DSP on the carrier board via high-speed connectors. Mainly, this unit will acquire rf signals to analyze their phase and amplitude at a specified harmonic of the revolution. The main sampling clock feeding the mezzanine board is at a high harmonic of the particle’s revolution frequency. In the PSB, this frequency is varying along the accelerating cycle and this choice allows analyzing the rf signals from the cavities or from the beam without changing any parameter along the cycle. The sampling clock is tagged at the revolution rate allowing...

Preliminary results of Digital Pulse Shape Acquisition from Chimera

International Nuclear Information System (INIS)

Alderighi, D.M.; Sechi, G.; Anzalone, A.; Cavallaro, S.; Giustolisi, F.; Laguidara, E.; Lanzalone, G.; Porto, F.; Bassini, R.; Boiano, C.; Guazzoni, P.; Russo, S.; Sassi, M.; Zetta, L.; Cardella, G.; Defilippo, S.E.; Lanzano, G.; Paganod, A.; Papa, M.; Pirrone, S.; Politi, G.; Geraci, E.

2003-01-01

A 100 MS/s 14-bit Sampling Analog-to-Digital converter has been used to perform digital pulse-shape acquisition of signals collected from CHIMERA telescopes. The signals from a typical CHIMERA detection cell have been collected using both a standard CHIMERA electronic chain up to the amplifier, and a very simple analog front end, basically reduced to the preamplifier. The preliminary on-beam results are presented. (authors)

Preliminary results of Digital Pulse Shape Acquisition from Chimera

Energy Technology Data Exchange (ETDEWEB)

Alderighi, D.M.; Sechi, G. [INFN Milano and IASF, CNR, Milano (France); Anzalone, A.; Cavallaro, S.; Giustolisi, F.; Laguidara, E.; Lanzalone, G.; Porto, F. [Catania Univ., LNS and Dipartimento di Fisica (France); Bassini, R.; Boiano, C.; Guazzoni, P.; Russo, S.; Sassi, M.; Zetta, L. [Milano Univ., INFN and Dipartimento di Fisica (Italy); Cardella, G.; Defilippo, S.E.; Lanzano, G.; Paganod, A.; Papa, M.; Pirrone, S.; Politi, G. [Catania Univ., INFN and Dipartimento di Fisica (Italy); Geraci, E. [Bologna Univ., INFN and Dipartimento di Fisica (Italy)

2003-07-01

A 100 MS/s 14-bit Sampling Analog-to-Digital converter has been used to perform digital pulse-shape acquisition of signals collected from CHIMERA telescopes. The signals from a typical CHIMERA detection cell have been collected using both a standard CHIMERA electronic chain up to the amplifier, and a very simple analog front end, basically reduced to the preamplifier. The preliminary on-beam results are presented. (authors)

High-speed multiple-channel analog to digital data-acquisition module for microprocessor systems

International Nuclear Information System (INIS)

Ethridge, C.D.

1977-01-01

Intelligent data acquisition and instrumentation systems established by the incorporation of microprocessor technology require high-speed analog to digital conversion of multiple-channel input signals. Sophisticated data systems or subsystems are enabled by the microprocessor software flexibility to establish adaptive input data procedures. These adaptive procedures are enhanced by versatile interface circuitry which is software controlled

Metallographic study of ferrite → sigma transformation using ferromagnetic colloid, microprobe analysis, and color etching

International Nuclear Information System (INIS)

Gray, R.J.; Crouse, R.S.; Sikka, V.K.; King, R.T.

1976-01-01

The mechanical properties of ferrite-containing austenitic stainless steel base metal and weldments are usually adversely affected by prolonged exposure to temperatures in the 482-900 0 C (900-1652 0 F) range. One cause of the property alteration is related to the transformation of relatively ductile delta-ferrite to less ductile sigma-phase. Attempts to identify sigma and delta ferrite phases by color staining techniques alone are well documented; however, the results are often questionable due to the difficulty in maintaining consistent color identifications. This investigation is concerned with the microstructural responses of the ferromagnetic delta-ferrite phase and the paramagnetic sigma-phase to a ferromagnetic iron colloid in a magnetic field. Such positive or negative responses of the two phases to the colloid offer a more definitive identification. With this technique, the identification of small amounts of these phases in the microstructure is limited only by the highest magnification and resolution of the optical microscope. The procedure is substantiated in this metallographic study with microprobe analysis and color metallography. Several examples of the correlative use of these three techniques in identifying varying amounts of delta-ferrite yields sigma transformation are presented

Switching power converters medium and high power

CERN Document Server

Neacsu, Dorin O

2013-01-01

An examination of all of the multidisciplinary aspects of medium- and high-power converter systems, including basic power electronics, digital control and hardware, sensors, analog preprocessing of signals, protection devices and fault management, and pulse-width-modulation (PWM) algorithms, Switching Power Converters: Medium and High Power, Second Edition discusses the actual use of industrial technology and its related subassemblies and components, covering facets of implementation otherwise overlooked by theoretical textbooks. The updated Second Edition contains many new figures, as well as

Digital versus analog complete-arch impressions for single-unit premolar implant crowns: Operating time and patient preference.

Science.gov (United States)

Schepke, Ulf; Meijer, Henny J A; Kerdijk, Wouter; Cune, Marco S

2015-09-01

Digital impression-making techniques are supposedly more patient friendly and less time-consuming than analog techniques, but evidence is lacking to substantiate this assumption. The purpose of this in vivo within-subject comparison study was to examine patient perception and time consumption for 2 complete-arch impression-making methods: a digital and an analog technique. Fifty participants with a single missing premolar were included. Treatment consisted of implant therapy. Three months after implant placement, complete-arch digital (Cerec Omnicam; Sirona) and analog impressions (semi-individual tray, Impregum; 3M ESPE) were made, and the participant's opinion was evaluated with a standard questionnaire addressing several domains (inconvenience, shortness of breath, fear of repeating the impression, and feelings of helplessness during the procedure) with the visual analog scale. All participants were asked which procedure they preferred. Operating time was measured with a stopwatch. The differences between impressions made for maxillary and mandibular implants were also compared. The data were analyzed with paired and independent sample t tests, and effect sizes were calculated. Statistically significant differences were found in favor of the digital procedure regarding all subjective domains (P<.001), with medium to large effect sizes. Of all the participants, over 80% preferred the digital procedure to the analog procedure. The mean duration of digital impression making was 6 minutes and 39 seconds (SD=1:51) versus 12 minutes and 13 seconds (SD=1:24) for the analog impression (P<.001, effect size=2.7). Digital impression making for the restoration of a single implant crown takes less time than analog impression making. Furthermore, participants preferred the digital scan and reported less inconvenience, less shortness of breath, less fear of repeating the impression, and fewer feelings of helplessness during the procedure. Copyright © 2015 Editorial Council

Custom Integrated Circuit Design for Portable Ultrasound Scanners

DEFF Research Database (Denmark)

Llimos Muntal, Pere

plane and the signals received from each transmit burst area summed. Each receiving channel is required to individually amplify and delay its signal in order to correctly pre-beamform. The handheld probe delivers the data to a processing unit digitally, hence, analog to digital converters (ADCs......-sigma analog-to-digital converter (CTDS ADC) operating at a sampling frequency of 320 MHz, a SNR of 45 dB, occupying an area of 0.0175 mm2 and a power consumption of 0.594 mW. The CTDS ADC digitizes the signal before the pre-beamform summing is applied. The SNR of the ADC is directly linked to the picture...... quality of the imaging. However, the SNR is also related to the power consumption, creating a tradeoff between power and picture quality. The design approach will be to achieve the minimum SNR that generates an acceptable picture quality while using the minimum power possible. The ADC is implemented...

Data Acquisition and Digital Filtering for Infrasonic Records on Active Volcanoes

Directory of Open Access Journals (Sweden)

José Chilo

2007-03-01

Full Text Available This paper presents the design of a digital data acquisition system for volcanic infrasound records. The system includes four electret condenser element microphones, a QF4A512 programmable signal converter from Quickfilter Technologies and a MSP430 microcontroller from Texas Instruments. The signal output of every microphone is converted to digital via a 16-bit Analog to Digital Converter (ADC. To prevent errors in the conversion process, Anti-Aliasing Filters are employed prior to the ADC. Digital filtering is performed after the ADC using a Digital Signal Processor, which is implemented on the QF4A512. The four digital signals are summed to get only one signal. Data storing and digital wireless data transmission will be described in a future paper.

Teleseism-based Relative Time Corrections for Modern Analyses of Digitized Analog Seismograms

Science.gov (United States)

Lee, T. A.; Ishii, M.

2017-12-01

With modern-day instruments and seismic networks timed by GPS systems, synchronization of data streams is all but a forgone conclusion. However, during the analog era, when each station had its own clock, comparing data timing from different stations was a far more daunting prospect. Today, with recently developed methods by which analog data can be digitized, having the ability to accurately reconcile the timings of two separate stations would open decades worth of data to modern analyses. For example, one possible and exciting application would be using noise interferometry with digitized analog data in order to investigate changing structural features (on a volcano for example) over a much longer timescale than was previously possible. With this in mind, we introduce a new approach to sync time between stations based on teleseismic arrivals. P-wave arrivals are identified at stations for pairs of earthquakes from the digital and analog eras that have nearly identical distances, locations, and depths. Assuming accurate timing of the modern data, relative time corrections between a pair of stations can then be inferred for the analog data. This method for time correction depends upon the analog stations having modern equivalents, and both having sufficiently long durations of operation to allow for recording of usable teleseismic events. The Hawaii Volcano Observatory (HVO) network is an especially ideal environment for this, as it not only has a large and well-preserved collection of analog seismograms, but also has a long operating history (1912 - present) with many of the older stations having modern equivalents. As such, the scope of this project is to calculate and apply relative time corrections to analog data from two HVO stations, HILB (1919-present) and UWE (1928-present)(HILB now part of Pacific Tsunami network). Further application of this method could be for investigation of the effects of relative clock-drift, that is, the determining factor for how

Amplitude-to-code converter for photomultipliers operating at high loadings

International Nuclear Information System (INIS)

Arkhangel'skij, B.V.; Evgrafov, G.N.; Pishchal'nikov, Yu.M.; Shuvalov, R.S.

1982-01-01

An 11-bit amplitude-to-code converter intended for the analysis of photomultiplier pulses under high loadings is described. To decrease the volume of digit electronics in the converter an analog memory on capacities is envisaged. A well-known bridge circuit with diodes on the main carriers is selected as a gating circuit. The gate control is realized by a switching circuit on fast-response transistors with boundary frequency of 1.2-1.5 GHz. The converter main characteristics are given, namely, maximum output signal amplitude equal to -1.5 V, minimum pulse selection duration of 10 ns, maximum number of counts at Usub(input)=-1.0 V and tsub(selection)=50 ns amounting to 1400, integral nonlinearity of +-0.1%, conversion temperature instability of 0.2%/deg C in the temperature range of (+10-+40) deg C, maximum time of data storage equal to 300 ms, conversion coefficient instability of 0.42 counts, number of channels in a unit CAMAC block equal to 12

Exploring dynamics of embedded ADC through adapted digital input stimuli

NARCIS (Netherlands)

Sheng, Xiaoqin; Kerkhoff, Hans G.; Zjajo, A.; Gronthoud, G.

2008-01-01

This paper reports an evaluation of adapted digital signals as a test stimulus to test dynamic parameters of analog-to-digital converters (ADC). In the first instance, the simplest digital waveform, a pulse signal, is taken as the test stimulus. The dynamics of the device under test while applying

Acquisition de donnees a haute resolution et faible latence dediee aux capteurs avioniques de position

Science.gov (United States)

Koubaa, Zied

The communication network and the detection mechanisms are two critical systems in a plane. Their performance has a direct impact on aircrafts. This is of particular interest for avionics designers, who have increasingly invested more and more in the development of these elements. As a part of a project in this domain, we introduce the design and the development of a smart interface for position sensors dedicated to flights (Smart Sensor Interface - SSI). This interface will serve to connect sensors of different technologies (electromagnetic, optical and MEMS) to the new communication network, AFDX. The role of this interface is to generate an appropriate excitation signal for certain types of sensors (R/LVDT), and to treat, demodulate, and digitize their output signals. The proposed interface is thus composed of a Signal Acquisition Path (SAP) and an Excitation Signal Generation (ESG). By adopting the Integrated Modular Avionics architecture (IMA), we can minimize the size of the classic interface, reduce its energy consumption and improve its reliability and its performance. The focus of our design is particularly on the Data Acquisition Path (DAP). An Architecture characterized by a high resolution (14 bits) and a low latency (1.2 ms) of this module is introduced and developed in this prestigious work. This architecture was developed after a wellconducted study of existing solutions found in literature work and a detailed analysis of the problems arise in the design and implementation of this system (DAP). The conversion of the sensor signal into a digital signal is the most important step in acquiring data, as it sets the resolution of the acquired information and generates the majority of its latency. This module can also affect the reliability and stability of the system. Among different models and architectures, the Delta-Sigma analog-to-digital converter (ADC) is preferred for this application (for better resolution). This converter is formed by an analog

Programmable electronic system for analog and digital gamma cameras modernization

International Nuclear Information System (INIS)

Osorio Deliz, J. F.; Diaz Garcia, A.; Arista Omeu, E. J.

2013-01-01

At present the use of analog and digital gamma cameras is continuously increasing in developing countries. Many of them still largely rely in old hardware electronics, which in many cases limits their use in actual nuclear medicine diagnostic studies. For this reason worldwide there are different medical equipment manufacturing companies engaged into partial or total Gamma Cameras modernization. Nevertheless in several occasions acquisition prices are not affordable for developing countries. This work describes the basic features of a programmable electronic system that allows improving acquisitions functions and processing of analog and digital gamma cameras. This system is based on an electronic board for the acquisition and digitization of nuclear pulses which have been generated by gamma camera detector. It comprises a hardware interface with PC and the associated software to fully signal processing. Signal shaping and image processing are included. The extensive use of reference tables in the processing and signal imaging software allowed the optimization of the processing speed. Time design and system cost were also decreased. (Author)

Degradation and aggregation of delta sleep-inducing peptide (DSIP) and two analogs in plasma and serum

International Nuclear Information System (INIS)

Graf, M.V.; Saegesser, B.; Schoenenberger, G.A.

1987-01-01

The biostability of DSIP (delta sleep-inducing peptide) and two analogs in blood was investigated in order to determine if rates of inactivation contribute to variable effects in vivo. Incubation of DSIP in human or rat blood led to release of products having retention times on a gel filtration column equivalent to Trp. Formation of products was dependent on temperature, time, and species. Incubation of 125 I-N-Tyr-DSIP and 125 I-N-Tyr-P-DSIP, a phosphorylated analog, revealed slower degradation and, in contrast to DSIP, produced complex formation. An excess of unlabeled material did not displace the radioactivity supporting the assumption of non-specific binding/aggregation. It was concluded that the rapid disappearance of injected DSIP in blood was due to degradation, whereas complex formation together with slower degradation resulted in longer persistence of apparently intact analogs. Whether this could explain the sometimes stronger and more consistent effects of DSIP-analogs remains to be examined

Digitally-controlled PC-interfaced Boost Converter for Educational Purposes

DEFF Research Database (Denmark)

Ljusev, Petar; Andersen, Michael A. E.

2004-01-01

This paper describes implementation of a simple digital PID control algorithm for a boost converter using a cheap fixed-point 8-bit microcontroller. Serial communication to a PC server program is established for easier downloading of compensator parameters and current and voltage waveform...

High-speed photonically assisted analog-to-digital conversion using a continuous wave multiwavelength source and phase modulation.

Science.gov (United States)

Bortnik, Bartosz J; Fetterman, Harold R

2008-10-01

A more simple photonically assisted analog-to-digital conversion system utilizing a cw multiwavelength source and phase modulation instead of a mode-locked laser is presented. The output of the cw multiwavelength source is launched into a dispersive device (such as a single-mode fiber). This fiber creates a pulse train, where the central wavelength of each pulse corresponds to a spectral line of the optical source. The pulses can then be either dispersed again to perform discrete wavelength time stretching or demultiplexed for continuous time analog-to-digital conversion. We experimentally demonstrate the operation of both time stretched and interleaved systems at 38 GHz. The potential of integrating this type of system on a monolithic chip is discussed.

Digital regulation of a phase controlled power converter

International Nuclear Information System (INIS)

Schultheiss, C.; Haque, T.

1995-01-01

The Relativistic Heavy Ion Collider, now in construction at Brookhaven National Laboratory, will use phase controlled power converters for the main dipole and quadrupole magnet strings. The rectifiers in these power supplies will be controlled by a digital regulator based on the TI 320C30 Digital Signal Processor (DSP). The DSP implements the current loop, the voltage loop, and a system to actively reduce the sub-harmonic ripple components. Digital firing circuits consisting of a phase locked lop and counters are used to fire the SCRs. Corrections for the sub-harmonic reduction are calculated by the DSP and stored in registers in the firing circuit. These corrections are added in hardware, to the over-all firing count provided by the DSP. the resultant count is compared to a reference counter to fire the SCRs. This combination of a digital control system and the digital firing circuits allows the correction of the sub-harmonics in a real-time sense. A prototype of the regulator has been constructed, and the preliminary testing indicates a sub-harmonic reduction of 60 dB

Beyond digital interference cancellation

NARCIS (Netherlands)

Venkateswaran, V.

2010-01-01

One of the major drawbacks towards the realization of MIMO and multi-sensor wireless communication systems is that multiple antennas at the receiver each have their own separate radio frequency (RF) front ends and analog to digital converter (ADC) units, leading to increased circuit size and power

Sadhana | Indian Academy of Sciences

Indian Academy of Sciences (India)

Temperature distribution and efficiency assessment of different PVT water collector ... UGO-A1, and AESOP-A1 with IAN (i.e., Interactive Analyzer) tool using X-Bar approach. ... authentication protocol for roaming user in mobile communication networks ... Design and implementation of sigma–delta digital to analog converter.

Noise and resolution with digital filtering for nuclear spectrometry

International Nuclear Information System (INIS)

Lakatos, T.

1991-01-01

Digital noise filtering looks very promising for semiconductor spectrometry. The resolution and conversion speed of the analog to digital converter (ADC) used at the input of a digital signal processor and analyzer can strongly influence the signal to noise ratio, the peak position and shape. The article leads with the investigation of these effects using computer modelling. (orig.)

High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming...

Algorithmic impediments filtration using the α-truncated mean method in resolver-to-digital converter

Directory of Open Access Journals (Sweden)

Gordiyenko V. I.

2009-02-01

Full Text Available A test diagram of the microcontroller-type resolver-to-digital converter and algorithms for impediments filtration therein are developed. Experimental verification of the α-truncated mean algorithm intended for the suppression of impulse and noise interference is conducted. The test results are given.

Image processing by use of the digital cross-correlator

International Nuclear Information System (INIS)

Katou, Yoshinori

1982-01-01

We manufactured for trial an instrument which achieved the image processing using digital correlators. A digital correlator perform 64-bit parallel correlation at 20 MH. The output of a digital correlator is a 7-bit word representing. An A-D converter is used to quantize it a precision of six bits. The resulting 6-bit word is fed to six correlators, wired in parallel. The image processing achieved in 12 bits, whose digital outputs converted an analog signal by a D-A converter. This instrument is named the digital cross-correlator. The method which was used in the image processing system calculated the convolution with the digital correlator. It makes various digital filters. In the experiment with the image processing video signals from TV camera were used. The digital image processing time was approximately 5 μs. The contrast was enhanced and smoothed. The digital cross-correlator has the image processing of 16 sorts, and was produced inexpensively. (author)

First observation of the production and decay of the Sigma /sub c//sup +/

CERN Document Server

Calicchio, M; Azemoon, T; Baker, N J; Bartley, J H; Baton, Jean-Pierre; Belusevic, R; Bertrand, D; Bingham, H H; Brisson, V; Bullock, F W; Colley, D C; Cooper, A M; Erriquez, O; Fogli-Muciaccia, M T; François, T; Gerbier, G; Guy, J G; Iori, M; Jones, G T; Kochowski, Claude; Leutz, H; Marage, P; Michette, A G; Moreels, J; Natali, S; Neveu, M; Nuzzo, S; O'Neale, S W; Petiau, P; Romano, F; Ruggieri, F; Sacton, J; Sewell, S J; Tyndel, M; Van Doninck, W K; Vander Velde-Wilquet, C; Venus, W; Votruba, M F; Wenninger, H; Wilquet, G

1980-01-01

An event with the decay chain Sigma /sub c//sup +/ to Lambda /sub c //sup +/+ pi /sup 0/, Lambda /sub c//sup +/ to K/sup -/+p+ pi /sup +/, has been observed in an exposure of BEBC, equipped with a track sensitive target, to the wide band neutrino beam from the SPS at CERN. The event has a unique three constraint kinematic fit to the Delta S=- Delta Q reaction nu +p to mu /sup -/+p+K/sup -/+ pi /sup +/+ pi /sup + /+ pi /sup 0/ with both gammas from the pi /sup 0/ decay detected. The proton and other final state particles are identified. The masses are M( Lambda /sub c//sup +/)=2290+or-3 MeV/c/sup 2/, M( Sigma /sub c//sup +/)=2457+or-4 MeV/c/sup 2/ and M( Sigma /sub c//sup +/)-M( Lambda /sub c//sup +/)=168+or-3 MeV/c/sup 2/. Including other data one obtains M( Sigma /sub c//sup ++/)-M( Sigma /sub c//sup +/)=0+or-4 Mev/c/sup 2/. (7 refs).

Fast successive approximation analog-to-digital converter

Energy Technology Data Exchange (ETDEWEB)

Gobbur, S G; Landis, D A; Goulding, F S [California Univ., Berkeley (USA). Lawrence Berkeley Lab.

1977-01-15

A new scheme has been developed for a 4096-channel (12-bit) successive approximation ADC which will allow more rapid coding than schemes commonly used at the present time. The allowable bit setting time for the major bits has been increased without adding to the total coding time. This is accomplished by permitting the initial accuracy of the setting of the major bits to be within eight channels. Towards the end of the coding time, when the major bits have settled, this error is corrected to an accuracy of a fraction of a channel. Using this scheme a differential nonlinearity of better than 20% has been achieved in the basic encoder with a total coding time of 4 ..mu..s. Applying a 6-bit sliding register (the method of Gatti) to the ADC, a differential nonlinearity less than 0.5% results in the complete ADC.

High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital...

Tripod sigma: results of a pro-active work stress-survey

NARCIS (Netherlands)

Nelemans, R.; Wiezer, N.; Vaas, F.; Gort, J.; Groeneweg, J.

2003-01-01

Work related stress is an important causes of disability and absenteeism. TNO Work and Employment has developed an instrument, called Tripod Sigma, that identifies risks to work stress and provides tools for remedying these risks. The Tripod Sigma model is developed analogous to the Tripod

The H1 SPACAL time-to-digital converter system

International Nuclear Information System (INIS)

Eisenhandler, E.; Landon, M.; Thompson, G.

1995-01-01

This paper describes a pipelined 1,400-channel Time-to-Digital Converter (TDC) system for the H1 Scintillating Fiber Calorimeter, which will soon be installed in the H1 experiment at DESY. The main task of the TDC system is to determine the time of arrival of energy depositions, and send this information from bunch crossings that satisfy the event trigger into the H1 data acquisition system. In addition, the TDC system must monitor the timing trigger, which vetoes bunch crossings that contain too much background energy. Products of the interaction are separated from background on the basis of their different times of arrival with respect to the bunch crossing clock. For this monitoring the TDC system uses automatic on-board histogramming hardware that produces a family of histograms for each of 1,400 channels. The TDC function is performed by the TMC1004 ASIC. The system digitizes over a range of 32ns per bunch crossing with 1ns bins and a precision of 1ns. Because of the way the TMC1004 is designed, it is possible to vary the size of the bins between 0.6ns and 3ns by trading off measurement range for bin size. The system occupies two 9U VME crates

Sensor Interfaces for Private Home Automation: From Analog to Digital, Wireless and Autonomous

Directory of Open Access Journals (Sweden)

Erich Leder

2007-08-01

Full Text Available In this paper a flexible and reliable system for smart home automation is presented. It is based on standardized hardware and open source communication protocols. Firstly, a special sensor interface has been developed, which allows the measurement of (slow analog signals to be determined by inexpensive digital PLC input terminals. Right now, up to eleven different modules have been implemented and the system is being tested in several configurations. In a second step, the communication is digitized. With the digitalization of the sensor modules, based on the implementation of a PIC Microcontroller, more intelligence is provided to the module, which increases the power and flexibility of the whole system. Thirdly, a wireless sensor-system consisting of a base station and of a mobile measuring unit is developed. The autonomous mobile unit is realized by using solar powering, gold cap energy storage, low-power circuits and a radio communication interface.

BPM ANALOG FRONT-END ELECTRONICS BASED ON THE AD8307 LOG AMPLIFIER

International Nuclear Information System (INIS)

R. SHURTER; ET AL

2000-01-01

Beam position monitor (BPM) signal-processing electronics utilizing the Analog Devices AD8307 logarithmic amplifier has been developed for the Low Energy Demonstration Accelerator (LEDA), part of the Accelerator Production of Tritium (APT) project at Los Alamos. The low-pass filtered 350 MHz fundamental signal from each of the four microstrip electrodes in a BPM is ''detected'' by an AD8307 log amp, amplified and scaled to accommodate the 0 to +5V input of an analog-to-digital (A/D) converter. The resultant four digitized signals represent a linear power relationship to the electrode signals, which are in turn related to beam current and position. As the AD8307 has a potential dynamic range of approximately 92 dB, much attention must be given to noise reduction, sources of which can be digital signals on the same board, power supplies, inter-channel coupling, stray RF and others. This paper will describe the operational experience of this particular analog front-end electronic circuit design

Tests on a digital neutron-gamma pulse shape discriminator with NE213

International Nuclear Information System (INIS)

Bell, Z.W.

1981-01-01

A technique using charge sensitive analog-to-digital converters to do neutron-gamma pulse shape discrimination is reported. The converters are gated by short (135 ns) pulses so as to reduce pile-up and the timing is such that the slow and total light output from the scintillator are measured. Preliminary tests indicate that the system performs reasonably well but poorer than some reported analog systems employing gated integrators or cross-over techniques. (orig.)

Transverse digital damper system for the Fermilab anti-proton recycler

International Nuclear Information System (INIS)

Eddy, N.; Crisp, J.; Fermilab

2006-01-01

A transverse damping system is used in the Recycler at Fermilab to damp beam instabilities which arise from large beam intensities with electron cooling. Initial tests of electron cooling demonstrated beam loss due to transverse beam motion when the beam was cooled past the beam density threshold. The transverse damper system consists of two horizontal and two vertical pickups whose signals are amplified and passed into an analog hybrid to generate a difference signal from each pickup. The difference signals are input to a custom digital damper board which digitizes the analog signals at 212mhz, performs digital processing of the signals inside a large Altera Stratix II FPGA, then provides analog output at 212mhz via digital to analog converters. The digital damper output is sent to amplifiers which drive one horizontal and one vertical kicker. An initial prototype digital damper board has been successfully used in the Recycler for over six months. Currently, work is underway to replace the prototype board with an upgraded VME version

Mixed Analog/Digital Matrix-Vector Multiplier for Neural Network Synapses

DEFF Research Database (Denmark)

Lehmann, Torsten; Bruun, Erik; Dietrich, Casper

1996-01-01

In this work we present a hardware efficient matrix-vector multiplier architecture for artificial neural networks with digitally stored synapse strengths. We present a novel technique for manipulating bipolar inputs based on an analog two's complements method and an accurate current rectifier...

High Speed Digitizer for Remote Sensing, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Alphacore, Inc. proposes to design and characterize a 24Gsps (giga-samples per-second), 6-bit, low-power, and low-cost analog-to-digital converter (ADC) for use in a...

PHOTO ENCODING OF ANALOG WATER METER FOR USER ACCESS AND PAYMENT SYSTEM

OpenAIRE

GODFREY A. MILLS; MOSES A. ACQUAH; APPAH BREMANG

2012-01-01

This paper presents design reconfiguration of analog water meter to provide remote access to user water consumption and billing records, payments, and meter device monitoring using photo-encoding as the detecting method for water consumption, a PIC18F2423 microcontroller for data processing, and SMS (short message service) technology for data transportation. To validate the system design, an analog water meter was converted into a digital equivalent and interfaced to the cellular network to t...

Application of digital sampling techniques to particle identification

International Nuclear Information System (INIS)

Bardelli, L.; Poggi, G.; Bini, M.; Carraresi, L.; Pasquali, G.; Taccetti, N.

2003-01-01

An application of digital sampling techniques is presented which can greatly simplify experiments involving sub-nanosecond time-mark determinations and energy measurements with nuclear detectors, used for Pulse Shape Analysis and Time of Flight measurements in heavy ion experiments. In this work a 100 M Sample/s, 12 bit analog to digital converter has been used: examples of this technique applied to Silicon and CsI(Tl) detectors in heavy-ions experiments involving particle identification via Pulse Shape analysis and Time of Flight measurements are presented. The system is suited for applications to large detector arrays and to different kinds of detectors. Some preliminary results regarding the simulation of current signals in Silicon detectors are also discussed. (authors)

BGS·SIGMA - Digital mapping at the British Geological Survey

Science.gov (United States)

Smith, Nichola; Lawrie, Ken

2017-04-01

. However, we recognise that in some areas usage is restricted due to access to the software platform used by the system. To combat this, and to try and facilitate access to the system for all, BGS is now developing the BGS·SIGMA companion app. This will be developed for smart phones and tablets, and as well as enabling users of open source software to access to the system it will also facilitate rapid point based mapping, something BGS geologists are increasingly required to carry out. Alongside this, BGS is also developing a set of modular, re-usable tools for data capture, storage, manipulation and delivery that will help organisations, which are just starting their journey into the digital world, to learn from our experiences and implement a system that is already fully integrated and can be customised for specific user requirements.

Method for Converter Synchronization with RF Injection

OpenAIRE

Joshua P. Bruckmeyer; Ivica Kostanic

2015-01-01

This paper presents an injection method for synchronizing analog to digital converters (ADC). This approach can eliminate the need for precision routed discrete synchronization signals of current technologies, such as JESD204. By eliminating the setup and hold time requirements at the conversion (or near conversion) clock rate, higher sample rate systems can be synchronized. Measured data from an existing multiple ADC conversion system was used to evaluate the method. Coherent beams were simu...

Mixed-Signal Hardware Security: Attacks and Countermeasures for ΔΣ ADC

Directory of Open Access Journals (Sweden)

Shayan Taheri

2017-08-01

Full Text Available Mixed-signal integrated circuits (ICs play an eminent and critical role in design and development of the embedded systems leveraged within smart weapons and military systems. These ICs can be a golden target for adversaries to compromise in order to function maliciously. In this work, we study the security aspects of a tunnel field effect transistor (TFET-based first-order one-bit delta-sigma ( Δ Σ analog to digital converter (ADC through proposing four attack and one defense models. The first attack manipulates the input signal to the Δ Σ modulator. The second attack manipulates the analog version of the modulator output bit and is triggered by the noise signal. The third attack manipulates the modulator output bit and has a controllable trigger mechanism. The fourth attack manipulates the analog version of the modulator output bit and is triggered by a victim capacitance within the chip. For the defense, a number of signal processing filters are used in order to purge the analog version of the modulator output bit for elimination of the malicious unwanted features, introduced by the attacks. According to the simulation results, the second threat model displays the strongest attack. Derived from the countermeasure evaluation, the best filter to confront the threat models is the robust regression using the least absolute residual computing method.

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

Energy Technology Data Exchange (ETDEWEB)

Zhang, Jie, E-mail: zhangjie071063@163.com [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China); University of Chinese Academy of Sciences, Beijing, China, 100049 (China); Zhou, Dongming [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China)

2015-01-21

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage.

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

International Nuclear Information System (INIS)

Zhang, Jie; Zhou, Dongming

2015-01-01

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage

Development of a fast time-to-digital converter (TDC) using a programmable gate array

International Nuclear Information System (INIS)

Mine, Shun-ichi; Tokushuku, Katsuo; Yamada, Sakue.

1994-09-01

A fast time-to-digital converter with a 5 ns step was designed and tested by utilizing a user-programmable gate array. The stabilities against temperature and supply voltage variation were measured. A module was built with this TDC, and was successfully used in the first-level trigger system of the ZEUS detector to reject proton-beam induced background events. (author)

Digital media labs in libraries

CERN Document Server

Goodman, Amanda L

2014-01-01

Families share stories with each other and veterans reconnect with their comrades, while teens edit music videos and then upload them to the web: all this and more can happen in the digital media lab (DML), a gathering of equipment with which people create digital content or convert content that is in analog formats. Enabling community members to create digital content was identified by The Edge Initiative, a national coalition of leading library and local government organizations, as a library technology benchmark. Surveying academic and public libraries in a variety of settings and sharing a

High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

Energy Technology Data Exchange (ETDEWEB)

Nishino, H., E-mail: nishino@post.kek.j [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A. [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Ishikawa, K.; Minegishi, A. [Iwatsu Test Instruments Corporation, Tokyo 168-8511 (Japan); Arai, Y. [The Institute of Particle and Nuclear Studies, KEK, Ibaraki 305-0801 (Japan)

2009-11-11

A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mVapprox3V; 0.2approx2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

International Nuclear Information System (INIS)

Nishino, H.; Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A.; Ishikawa, K.; Minegishi, A.; Arai, Y.

2009-01-01

A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mV∼3V; 0.2∼2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

Energy Technology Data Exchange (ETDEWEB)

He Xiaofeng; Ye Tianchun [Institute of Microelectronics, Chinese Academy of Science, Beijing 100029 (China); Mo Taishan; Ma Chengyan, E-mail: hexiaofeng@casic.ac.cn [Hangzhou Zhongke Microelectronics Co, Ltd, Hangzhou 310053 (China)

2011-02-15

An analog/digital reconfigurable automatic gain control (AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What's more, a novel DC offset cancellation (DCOC) circuit with an HPCF (high pass cutoff frequency) less than 10 kHz is proposed. The AGC is fabricated by a 0.18 {mu}m CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 x 300 {mu}m{sup 2}. (semiconductor integrated circuits)

Design and Implementation of Digital Current Mode Controller for DC-DC Converters

DEFF Research Database (Denmark)

Taeed, Fazel

to be regulated by a closed-loop controller. The Peak Current Mode Control (PCMC) is one of the most promising control methods for dc-dc converters. It has been known for high bandwidth (speed), and inherent current protection. Increasing the controller bandwidth decreases the output filter size and cost. Analog...

Analisis Migrasi Radio Trunking Analog ke Radio Trunking Digital di Indonesia

Directory of Open Access Journals (Sweden)

Riza Azmi

2013-09-01

Full Text Available Dalam Tabel Alokasi Spektrum Frekuensi di Indonesia pada catatan kaki INS9 dan INS13 disebutkan bahwa alokasi pada pita-pita frekuensi yang digunakan untuk teknologi trunking direncanakan dimigrasi ke sistem komunikasi trunking digital pada waktu yang akan ditentukan oleh pemerintah. Terkait dengan hal itu, studi ini bertujuan untuk mengkaji bagaimana kelayakan migrasi dari sistem trunking analog ke sistem trunking digital dan hal-hal yang terkait dengannya. Dengan menggunakan analisis biaya dan manfaat (Cost-Benefit Analysis studi ini melihat bahwa migrasi hanya dapat dilakukan jika umur masing-masing lisensi dari operator telah berakhir, atau dengan kata lain pemerintah dapat mendorong transisi ke digital dengan menerbitkan lisensi baru yaitu lisensi trunking digital.

Optimum phase shift in the self-oscillating loop for piezoelectric transformer-based power converters

DEFF Research Database (Denmark)

Ekhtiari, Marzieh; Zsurzsan, Tiberiu-Gabriel; Andersen, Michael A. E.

2017-01-01

A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitally controlled time delay through the self-oscillating loop results in very precise frequency control...... and ensures optimum operation of the piezoelectric transformer in terms of gain and efficiency. Time delay is implemented digitally for the first time through a 16 bit digital-to-analog converter in the self-oscillating loop. The new design of the delay circuit provides 45 ps time resolution, enabling fine......-grained control of phase in the self-oscillating loop. This allows the control loop to dynamically follow frequency changes of the transformer in each resonant cycle. Ultimately, by selecting the optimum phase shift, maximum efficiency under the load and temperature condition is achievable....

Telling time from analog and digital clocks: A multiple-route account

NARCIS (Netherlands)

Korvorst, M.H.W.; Roelofs, A.P.A.; Levelt, W.J.M.

2007-01-01

Does the naming of clocks always require conceptual preparation? To examine this question, speakers were presented with analog and digital clocks that had to be named in Dutch using either a relative (e.g., "quarter to four") or an absolute (e.g., "three forty-five") clock time expression format.

Reactions of small negative ions with O2(a 1[Delta]g) and O2(X 3[Sigma]g-)

Science.gov (United States)

Midey, Anthony; Dotan, Itzhak; Seeley, J. V.; Viggiano, A. A.

2009-02-01

The rate constants and product ion branching ratios were measured for the reactions of various small negative ions with O2(X 3[Sigma]g-) and O2(a 1[Delta]g) in a selected ion flow tube (SIFT). Only NH2- and CH3O- were found to react with O2(X) and both reactions were slow. CH3O- reacted by hydride transfer, both with and without electron detachment. NH2- formed both OH-, as observed previously, and O2-, the latter via endothermic charge transfer. A temperature study revealed a negative temperature dependence for the former channel and Arrhenius behavior for the endothermic channel, resulting in an overall rate constant with a minimum at 500 K. SF6-, SF4-, SO3- and CO3- were found to react with O2(a 1[Delta]g) with rate constants less than 10-11 cm3 s-1. NH2- reacted rapidly with O2(a 1[Delta]g) by charge transfer. The reactions of HO2- and SO2- proceeded moderately with competition between Penning detachment and charge transfer. SO2- produced a SO4- cluster product in 2% of reactions and HO2- produced O3- in 13% of the reactions. CH3O- proceeded essentially at the collision rate by hydride transfer, again both with and without electron detachment. These results show that charge transfer to O2(a 1[Delta]g) occurs readily if the there are no restrictions on the ion beyond the reaction thermodynamics. The SO2- and HO2- reactions with O2(a) are the only known reactions involving Penning detachment besides the reaction with O2- studied previously [R.S. Berry, Phys. Chem. Chem. Phys., 7 (2005) 289-290].

Variation in leaf water delta D and delta 18O values during the evapotranspiration process

International Nuclear Information System (INIS)

Leopoldo, P.R.; Foloni, L.L.

1984-01-01

A theoretical model was developed to evaluate leaf water delta D and delta 18 O variation in relation to: leaf temperature, relative humidity converted to leaf temperature and delta D and delta 18 O values of atmospheric water vapour and soil water. (M.A.C.) [pt

Digital television: a new way to deliver information

Science.gov (United States)

Huang, Samson

1998-12-01

Digital television (DTV) is a new way to deliver video, audio, and other data. Why should TV be converted to digital? How does DTV work? What can we do with it? This paper provides some introduction about DTV, its history, and its roll-out plan. It then compares DTV with analog TV, and describes how DTV works. It also describes why the computer industry, as well as the consumer electronics industry, are both very interested I the DTV market. Next, it describes what Intel has done on DTV, including how we build a PC- based DTV, its test evaluation results, its new applications, and Intel's DTV station DMRL. This paper also describes remaining issues, our roadmap, vision, and future directions.

Digitizing high frequency signals using serial analog memories

International Nuclear Information System (INIS)

Coonrod, J.W.

1975-10-01

An online computer system has been developed as a replacement for oscilloscopes and cameras on the Tormac project. Up to 32 simultaneous waveforms are recorded at up to 2 MHz in analog shift registers, then digitized sequentially after the event into a small PDP-11 computer. Data and functions of data may be displayed or plotted locally, and then forwarded for storage at a larger, remote computer via a network arrangement. Advantages over scopes have been lower incremental cost (approximately $200/channel), less noise pickup, better resolution (less than 1%), and immediate presentation of data

Digital parallel-to-series pulse-train converter

Science.gov (United States)

Hussey, J.

1971-01-01

Circuit converts number represented as two level signal on n-bit lines to series of pulses on one of two lines, depending on sign of number. Converter accepts parallel binary input data and produces number of output pulses equal to number represented by input data.

Analog synthetic biology.

Science.gov (United States)

Sarpeshkar, R

2014-03-28

We analyse the pros and cons of analog versus digital computation in living cells. Our analysis is based on fundamental laws of noise in gene and protein expression, which set limits on the energy, time, space, molecular count and part-count resources needed to compute at a given level of precision. We conclude that analog computation is significantly more efficient in its use of resources than deterministic digital computation even at relatively high levels of precision in the cell. Based on this analysis, we conclude that synthetic biology must use analog, collective analog, probabilistic and hybrid analog-digital computational approaches; otherwise, even relatively simple synthetic computations in cells such as addition will exceed energy and molecular-count budgets. We present schematics for efficiently representing analog DNA-protein computation in cells. Analog electronic flow in subthreshold transistors and analog molecular flux in chemical reactions obey Boltzmann exponential laws of thermodynamics and are described by astoundingly similar logarithmic electrochemical potentials. Therefore, cytomorphic circuits can help to map circuit designs between electronic and biochemical domains. We review recent work that uses positive-feedback linearization circuits to architect wide-dynamic-range logarithmic analog computation in Escherichia coli using three transcription factors, nearly two orders of magnitude more efficient in parts than prior digital implementations.

Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

Science.gov (United States)

Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

2012-10-21

Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

Precision measurement of $\\sigma(e^+e^-\\rightarrow\\pi^+\\pi^-\\gamma)/\\sigma(e^+e^-\\rightarrow \\mu^+\\mu^-\\gamma)$ and determination of the $\\pi^+\\pi^-$ contribution to the muon anomaly with the KLOE detector

CERN Document Server

Babusci, D.; Balwierz-Pytko, I.; Bencivenni, G.; Bini, C.; Bloise, C.; Bossi, F.; Branchini, P.; Budano, A.; Caldeira Balkestahl, L.; Capon, G.; Ceradini, F.; Ciambrone, P.; Curciarello, F.; Czerwinski, E.; Dane, E.; De Leo, V.; De Lucia, E.; De Robertis, G.; De Santis, A.; De Simone, P.; Di Domenico, A.; Di Donato, C.; Domenici, D.; Erriquez, O.; Fanizzi, G.; Felici, G.; Fiore, S.; Franzini, P.; Gauzzi, P.; Giardina, G.; Giovannella, S.; Gonnella, F.; Graziani, E.; Happacher, F.; Heijkenskjold, L.; Hoistad, B.; Iafolla, L.; Iarocci, E.; Jacewicz, M.; Johansson, T.; Kluge, W.; Kupsc, A.; Lee-Franzini, J.; Loddo, F.; Lukin, P.; Mandaglio, G.; Martemianov, M.; Martini, M.; Mascolo, M.; Messi, R.; Miscetti, S.; Morello, G.; Moricciani, D.; Moskal, P.; Muller, S.; Nguyen, F.; Passeri, A.; Patera, V.; Prado Longhi, I.; Ranieri, A.; Redmer, C.F.; Santangelo, P.; Sarra, I.; Schioppa, M.; Sciascia, B.; Silarski, M.; Taccini, C.; Tortora, L.; Venanzoni, G.; Versaci, R.; Wislicki, W.; Wolke, M.; Zdebik, J.

2013-01-01

We have measured the ratio $\\sigma(e^+e^-\\rightarrow\\pi^+\\pi^-\\gamma)/\\sigma(e^+e^-\\rightarrow \\mu^+\\mu^-\\gamma)$, with the KLOE detector at DA$\\Phi$NE for a total integrated luminosity of $\\sim$ 240 pb$^{-1}$. From this ratio we obtain the cross section $\\sigma(e^+e^-\\rightarrow\\pi^+\\pi^-)$. From the cross section we determine the pion form factor $|F_\\pi|^2$ and the two-pion contribution to the muon anomaly $a_\\mu$ for $0.592Delta^{\\pi\\pi} a_\\mu$= $({\\rm 385.1\\pm1.1_{stat}\\pm2.7_{sys+theo}})\\times10^{-10}$. This result confirms the current discrepancy between the Standard Model calculation and the experimental measurement of the muon anomaly.

Wideband Spectroscopy: The Design and Implementation of a 3 GHz, 2048 Channel Digital Spectrometer

Science.gov (United States)

Monroe, Ryan M.

2011-01-01

A state-of-the-art digital Fourier Transform spectrometer has been developed, with a combination of high bandwidth and fine resolution unavailable elsewhere. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved Analog-to-Digital Converters (ADC). This 6 Gsps (giga sample per second) digital representation of the analog signal is then processed through an FPGA-based streaming Fast Fourier Transform (FFT), the key development described below. Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers. The implementation, results and underlying math for this spectrometer, as well as potential for future extension to even higher bandwidth, resolution and channel orthogonality, needed to support proposed future advanced atmospheric science and radioastronomy, are discussed.

Digital compensation of receiver clipping for DVB reception on low-power mobile

NARCIS (Netherlands)

Linnartz, J.P.M.G.; Rietman, R.

2007-01-01

Battery life-time is a critical issue for digital television (DVB) viewing on mobile phones. The number of quantization steps used in the analog-to-digital converter (ADC) is an important factor in the total power consumption of a DVB receiver. The OFDM signals require a large resolution of the ADC.

Graphical Evaluation of Time-Delay Compensation Techniques for Digitally Controlled Converters

DEFF Research Database (Denmark)

Lu, Minghui; Wang, Xiongfei; Loh, Poh Chiang

2018-01-01

A main design constraint of the digitally controlled power electronics converters is the time delay of control systems, which may lead to the reduced control loop bandwidth and even unstable dynamics. Numerous time-delay compensation methods have been developed, of which the model-free schemes...

Digital signal processing for He3 proportional counter

International Nuclear Information System (INIS)

Zeynalov, Sh.S.; Ahmadov, Q.S.

2010-01-01

Full text : Data acquisition systems for nuclear spectroscopy have traditionally been based on systems with analog shaping amplifiers followed by analog-to-digital converters. Recently, however, new systems based on digital signal processing make possible to replace the analog shaping and timing circuitry the numerical algorithms to derive properties of the pulse such as its amplitude. DSP is a fully numerical analysis of the detector pulse signals and this technique demonstrates significant advantages over analog systems in some circumstances. From a mathematical point of view, one can consider the signal evolution from the detector to the ADC as a sequence of transformations that can be described by precisely defined mathematical expressions. Digital signal processing with ADCs has the possibility to utilize further information on the signal pulses from radiation detectors. In the experiment each step of the signal generation in the 3He filled proportional counter was described using digital signal processing techniques (DSP). The electronic system has consisted of a detector, a preamplifier and a digital oscilloscope. The pulses from the detector were digitized using a digital storage oscilloscope. This oscilloscope allowed signal digitization with accuracy of 8 bit (256 levels) and with frequency of up to 5 * 10 8 samples/s. As a neutron source was used Cf-252. To obtain detector output current pulse I(t) created by the motions of the ions/electrons pairs was written an algorithm which can easily be programmed using modern computer programming languages.

CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

International Nuclear Information System (INIS)

Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

1996-01-01

In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

Compact FPGA-based beamformer using oversampled 1-bit A/D converters

DEFF Research Database (Denmark)

Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

2005-01-01

A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadr......% of the available logic resources in a commercially available midrange FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.......A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in......-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal...

Comparisons between digital gamma-ray spectrometer (DSPec) and standard nuclear instrumentation methods (NIM) systems

International Nuclear Information System (INIS)

Vo, D.T.; Russo, P.A.; Sampson, T.E.

1998-03-01

Safeguards isotopic measurements require the best spectrometer systems with excellent resolution, stability and throughput. Up until about a year ago, gamma ray spectroscopy has always been done using the analog amplifier, which processes the pulses from the preamplifier to remove the noise, reject the pile up signals, and shape the signals into some desirable form before sending them to the analog to digital converter (ADC) to be digitized. In late 1996, EG and G Ortec introduced a digital gamma ray spectrometer (DSPec) which uses digital technology to analyze the preamplifiers' pulses from all types of germanium and silicon detectors. Considering its performance, digital based spectroscopy may become the way of future gamma ray spectroscopy