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Sample records for delta-sigma analog-to-digital converter

  1. A Delta-Sigma Analog-to-Digital Converter Using Resonant Tunneling Diodes

    Science.gov (United States)

    Yokoyama, Yuji; Ohno, Yutaka; Kishimoto, Shigeru; Maezawa, Koichi; Mizutani, Takashi

    2001-10-01

    A novel delta-sigma (ΔΣ) analog-to-digital converter (ADC) using resonant tunneling diodes (RTDs) is proposed. A ΔΣ modulator circuit, which is the key element of the ΔΣ ADC, can be designed in a very simple form using a monostable-bistable transition logic element (MOBILE). The operation of this ΔΣ modulator circuit is confirmed by numerical simulation.

  2. High-speed decimation filter for a delta-sigma analog-to-digital converter

    Science.gov (United States)

    Xie, Yiqun

    1998-10-01

    A decimation filter is a key component in a delta-sigma analog-to-digital converter system. The importance of the design of the decimation filter for the delta-sigma converter is due to several factors. The first, high resolution, which is the major advantage of the delta-sigma converter, can only be possible if the decimation filter can remove the high-frequency noise generated by the quantizer, without introducing significant distortion of the signals. The second is that a decimation filter occupies the dominant portion of the area and consumes the dominant portion of power in a delta-sigma converter; therefore, a well designed decimation filter can significantly save power and area for the converter and reduce production cost. The third is that the first-stage decimation filter has to operate in a very high frequency, equal to the sampling frequency of the delta-sigma converter. The circuit complexity and high-speed operation pose challenges to the design of a decimation filter. A superconductive decimation filter has the advantage of allowing sampling the analog signal at an ultra-high frequency in the modulator. This dissertation presents a superconductive decimation filter designed with voltage-state logic, which has the advantage of robustness, being relatively insensitive to clock timing, and easier to interface with semiconductor circuitry than other prevailing superconductive logic families. A structure of a multi-channel-input filter is developed to improve the speed performance. The filter is aimed to work at 16 Gbit/s or higher with state-of-the-art niobium technology. Extensive simulation is performed to optimize the circuit design. Circuit yield is predicted by Monte Carlo simulation using the knowledge of existing process variations. To improve yield, the circuit is simplified by using an accumulate-and-dump structure. A novel XOR gate is invented and used in the circuit to reduce gate count even further. A single-rail operation of signals, rather

  3. Development of superconducting bandpass delta-sigma analog-to-digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Bulzacchelli, John F.; Lee, Hae-Seung; Misewich, James A.; Ketchen, Mark

    2004-10-01

    This paper recounts the development of a superconducting bandpass delta-sigma ({delta}{sigma}) modulator for direct analog-to-digital conversion of radio frequency signals in the GHz range. The modulator design benefits from several advantages of superconducting electronics: high-Q resonators, fast Josephson comparators, naturally quantized single flux quantum pulses, and high circuit sensitivity. The measured center frequency (2.23 GHz), sampling rate (up to 45 GHz), dynamic range (greater than 57 dB over a 19.6 MHz bandwidth), and input sensitivity (-17.4 dBm full-scale) of the bandpass modulator are the highest reported to date in any technology. The SNR (49 dB over a 20.8 MHz bandwidth) is limited by the frequency resolution of the measurement but still exceeds the SNRs of semiconductor modulators with comparable center frequencies. The design of the modulator test chip and the high speed testing methodology are reviewed. Finally, the paper examines the prospects for improved performance with more advanced modulator architectures.

  4. Development of superconducting bandpass delta-sigma analog-to-digital converter

    Science.gov (United States)

    Bulzacchelli, John F.; Lee, Hae-Seung; Misewich, James A.; Ketchen, Mark B.

    2004-10-01

    This paper recounts the development of a superconducting bandpass delta-sigma (ΔΣ) modulator for direct analog-to-digital conversion of radio frequency signals in the GHz range. The modulator design benefits from several advantages of superconducting electronics: high-Q resonators, fast Josephson comparators, naturally quantized single flux quantum pulses, and high circuit sensitivity. The measured center frequency (2.23 GHz), sampling rate (up to 45 GHz), dynamic range (greater than 57 dB over a 19.6 MHz bandwidth), and input sensitivity (-17.4 dBm full-scale) of the bandpass modulator are the highest reported to date in any technology. The SNR (49 dB over a 20.8 MHz bandwidth) is limited by the frequency resolution of the measurement but still exceeds the SNRs of semiconductor modulators with comparable center frequencies. The design of the modulator test chip and the high speed testing methodology are reviewed. Finally, the paper examines the prospects for improved performance with more advanced modulator architectures.

  5. Experimental Demonstration of Ideal Noise Shaping in Resonant Tunneling Delta-Sigma Modulator for High Resolution, Wide Band Analog-to-Digital Converters

    Science.gov (United States)

    Maezawa, Koichi; Sakou, Mario; Matsubara, Wataru; Mizutani, Takashi; Matsuzaki, Hideaki

    2006-04-01

    A ΔΣ modulator using a frequency modulation intermediate signal was demonstrated using a resonant tunneling logic gate called a monostable bistable transition logic element (MOBILE). This ΔΣ modulator is based on the nature of an FM signal and suitable for high-speed operation. Experiments using an InP-based MOBILE demonstrate good noise shaping characteristics. Moreover, the operation with a higher FM carrier frequency than the sampling frequency was demonstrated, showing equally good noise shaping performance. This makes the design of the voltage-controlled oscillator, which is a key component of the FM ΔΣ modulator, much easier. Consequently, an FM ΔΣ modulator using MOBILE is promising for high-resolution, wide-band analog-to-digital converters (ADCs).

  6. Understanding delta-sigma data converters

    CERN Document Server

    Pavan, Shanti; Temes, Gabor C

    2017-01-01

    This new edition introduces novel analysis and design techniques for delta-sigma (ΔΣ) converters in physical and conceptual terms, and includes new chapters that explore developments in the field over the last decade. This book explains the principles and operation of delta-sigma analog-to-digital converters (ADCs) in physical and conceptual terms in accordance with the most recent developments in the field. The interest of ΔΣ converter designers has shifted significantly over the past decade, due to many new applications for data converters at the far ends of the frequency spectrum. Continuous-time delta-sigma A/D converters with GHz clocks, of both lowpass and bandpass types, are required for wireless applications. At the other extreme, multiplexed ADCs with very narrow (sometimes 10 Hz wide) signal bandwidths, but very high accuracy are needed in the interfaces of biomedical and environmental sensors. To reflect the changing eeds of designers, the second edition includes significant new material on bo...

  7. Novel Design for High Speed and Resolution Delta-sigma A/D Converter

    Institute of Scientific and Technical Information of China (English)

    TANG Sheng-xue; HE Yi-gang; GUO Jie-rong; LI Hong-min

    2007-01-01

    The delta-sigma converter is one of the high speed and resolution analog-to-digital modulators. Its implementation needs the low oversampling technique and the multi-bit D/A converter. The noise induced by the multi-bit D/A converter becomes one of the key factors deteriorating the signal-to-noise rate of the delta-sigma A/D converter. A novel structure with signal unity transfunction, dynamic element matching(DEM) and noise-shaping is discussed. The method is investigated to design converter based on the proposed structure. The behavior simulation indicates that the structure and the design method are feasible.

  8. Serial Pixel Analog-to-Digital Converter

    Energy Technology Data Exchange (ETDEWEB)

    Larson, E D

    2010-02-01

    This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream similar to a pseudo random number (PRN) generator. The resulting encoded pixel data is then decoded into a standard hexadecimal format before storage. The high-speed serial pixel ADC concept is based on the single-slope integrating pixel ADC architecture. Previous work has described a massively parallel pixel readout of a similar architecture. The serial ADC connection is similar to the state-of-the art method with the exception that the pixel ADC register is a shift register and the data path is a single bit. A state-of-the-art individual-pixel ADC uses a single-slope charge integration converter architecture with integral registers and “one-hot” counters. This implies that parallel data bits are routed among the counter and the individual on-chip pixel ADC registers. The data path bit-width to the pixel is therefore equivalent to the pixel ADC bit resolution.

  9. Photonic analog-to-digital converters

    Science.gov (United States)

    Valley, George C.

    2007-03-01

    This paper reviews over 30 years of work on photonic analog-to-digital converters. The review is limited to systems in which the input is a radio-frequency (RF) signal in the electronic domain and the output is a digital version of that signal also in the electronic domain, and thus the review excludes photonic systems directed towards digitizing images or optical communication signals. The state of the art in electronic ADCs, basic properties of ADCs and properties of analog optical links, which are found in many photonic ADCs, are reviewed as background information for understanding photonic ADCs. Then four classes of photonic ADCs are reviewed: 1) photonic assisted ADC in which a photonic device is added to an electronic ADC to improve performance, 2) photonic sampling and electronic quantizing ADC, 3) electronic sampling and photonic quantizing ADC, and 4) photonic sampling and quantizing ADC. It is noted, however, that all 4 classes of “photonic ADC” require some electronic sampling and quantization. After reviewing all known photonic ADCs in the four classes, the review concludes with a discussion of the potential for photonic ADCs in the future.

  10. Optical analog-to-digital converter

    Science.gov (United States)

    Evanchuk, Vincent L. (Inventor)

    1984-01-01

    A method and apparatus for converting the intensity of an unknown optical signal (B) into an electrical signal in digital form utilizes two elongated optical attenuators (11, 13), one for the unknown optical signal from a source (10) and one for a known optical signal (A) from a variable source (12), a plurality of photodetectors (e.g., 17, 18) along each attenuator for detecting the intensity of the optical signals, and a plurality of comparators (e.g., 21) connected to the photodetectors in pairs to determine at what points being compared the attenuated known signal equals the attenuated unknown signal. The intensity of the unknown relative to the known is thus determined by the output of a particular comparator. That output is automatically encoded to a relative intensity value in digital form through a balancing feedback control (24) and encoder (23). The digital value may be converted to analog form in a D-to-A converter (27) and used to vary the source of the known signal so that the attenuated intensity of the known signal at a predetermined point (comparator 16) equals the attenuated intensity of the unknown signal at the predetermined point of comparison. If the known signal is then equal to the unknown, there is verification of the analog-to-digital conversion being complete. Otherwise the output of the comparator indicating equality at some other point along the attenuators will provide an output which is encoded and added, through an accumulator comprised of a register (25) and an adder (26), to a previous relative intensity value thereby to further vary the intensity of the known signal source. The steps are repeated until full conversion is verified.

  11. Photonic analog-to-digital converter via asynchronous oversampling

    Science.gov (United States)

    Carver, Spencer; Reeves, Erin; Siahmakoun, Azad; Granieri, Sergio

    2012-06-01

    This paper presents a hybrid opto-electronic asynchronous delta-sigma modulator, implemented in the form of a fiber-optic Analog-to-Digital converter (ADC). This architecture was chosen for its independence of an external clock and ease of demodulation through a single low-pass filter stage. The fiber-optic prototype consists of an input laser (wavelength λ1) which is modulated with an input RF signal, a high-speed comparator circuit working as bi-stable quantizer, and a fiber-optic loop that includes a SOA and a band-pass filter that act as a leaky integrator. The fiber-optic loop acts as a fiber-ring resonator (FRR), and defines the resonance wavelength λ2 of the system. The gain within this loop is modified through cross-gain modulation (XGM) by the input wavelength λ1, and thus achieves the desired modulation effect. The proposed architecture has been constructed and characterized at a sampling rate of 15.4 MS/s processing input analog signals in the range of dc-3 MHz with a signal-to-noise ratio of 36 dB and an effective number of bits of 5.7.

  12. Error Models of the Analog to Digital Converters

    OpenAIRE

    Michaeli Linus; Šaliga Ján

    2014-01-01

    Error models of the Analog to Digital Converters describe metrological properties of the signal conversion from analog to digital domain in a concise form using few dominant error parameters. Knowledge of the error models allows the end user to provide fast testing in the crucial points of the full input signal range and to use identified error models for post correction in the digital domain. The imperfections of the internal ADC structure determine the error characteristics represented by t...

  13. Time-Interleaved Analog to Digital Converters

    NARCIS (Netherlands)

    Louwsma, S.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2010-01-01

    This book describes the research carried out by our PhD student Simon Louwsma at the University of Twente, The Netherlands in the field of high-speed Analogto- Digital (AD) converters. AD converters are crucial circuits for modern systems where information is stored or processed in digital form. Due

  14. Time interleaved counter analog to digital converters

    OpenAIRE

    Danesh, Seyed Amir Ali

    2011-01-01

    The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the ...

  15. Three-channel integrating analog-to-digital converter

    Science.gov (United States)

    Stevens, G. L.

    1978-01-01

    A three-channel integrating analog-to-digital converter was added to the complex mixer system to accept the baseband, complex signals generated by the complex mixers and output binary data to the digital demodulator for further processing and recording. The converter was first used for processing multistation data in radar experiments in the spring of 1977.

  16. A Novel All-Optical Analog-to-Digital Converter

    Institute of Scientific and Technical Information of China (English)

    Xiaobo; Hou; Afshin; Daryoush; Warren; Rosen

    2003-01-01

    An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of detectors with scalable apertures.

  17. Time-interleaved analog-to-digital converters

    CERN Document Server

    Louwsma, Simon; Nauta, Bram

    2010-01-01

    ""Time-interleaved Analog-to-Digital Converters"" describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that t

  18. Error Models of the Analog to Digital Converters

    Science.gov (United States)

    Michaeli, Linus; Šaliga, Ján

    2014-04-01

    Error models of the Analog to Digital Converters describe metrological properties of the signal conversion from analog to digital domain in a concise form using few dominant error parameters. Knowledge of the error models allows the end user to provide fast testing in the crucial points of the full input signal range and to use identified error models for post correction in the digital domain. The imperfections of the internal ADC structure determine the error characteristics represented by the nonlinearities as a function of the output code. Progress in the microelectronics and missing information about circuital details together with the lack of knowledge about interfering effects caused by ADC installation prefers another modeling approach based on the input-output behavioral characterization by the input-output error box. Internal links in the ADC structure cause that the input-output error function could be described in a concise form by suitable function. Modeled functional parameters allow determining the integral error parameters of ADC. Paper is a survey of error models starting from the structural models for the most common architectures and their linkage with the behavioral models represented by the simple look up table or the functional description of nonlinear errors for the output codes.

  19. Error Models of the Analog to Digital Converters

    Directory of Open Access Journals (Sweden)

    Michaeli Linus

    2014-04-01

    Full Text Available Error models of the Analog to Digital Converters describe metrological properties of the signal conversion from analog to digital domain in a concise form using few dominant error parameters. Knowledge of the error models allows the end user to provide fast testing in the crucial points of the full input signal range and to use identified error models for post correction in the digital domain. The imperfections of the internal ADC structure determine the error characteristics represented by the nonlinearities as a function of the output code. Progress in the microelectronics and missing information about circuital details together with the lack of knowledge about interfering effects caused by ADC installation prefers another modeling approach based on the input-output behavioral characterization by the input-output error box. Internal links in the ADC structure cause that the input-output error function could be described in a concise form by suitable function. Modeled functional parameters allow determining the integral error parameters of ADC. Paper is a survey of error models starting from the structural models for the most common architectures and their linkage with the behavioral models represented by the simple look up table or the functional description of nonlinear errors for the output codes.

  20. Reference-Free CMOS Pipeline Analog-to-Digital Converters

    CERN Document Server

    Figueiredo, Michael; Evans, Guiomar

    2013-01-01

    This book shows that digitally assisted analog-to-digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low ...

  1. Optimizing analog-to-digital converters for sampling extracellular potentials.

    Science.gov (United States)

    Artan, N Sertac; Xu, Xiaoxiang; Shi, Wei; Chao, H Jonathan

    2012-01-01

    In neural implants, an analog-to-digital converter (ADC) provides the delicate interface between the analog signals generated by neurological processes and the digital signal processor that is tasked to interpret these signals for instance for epileptic seizure detection or limb control. In this paper, we propose a low-power ADC architecture for neural implants that process extracellular potentials. The proposed architecture uses the spike detector that is readily available on most of these implants in a closed-loop with an ADC. The spike detector determines whether the current input signal is part of a spike or it is part of noise to adaptively determine the instantaneous sampling rate of the ADC. The proposed architecture can reduce the power consumption of a traditional ADC by 62% when sampling extracellular potentials without any significant impact on spike detection accuracy.

  2. Optical-spectrum-encoded analog-to-digital converter

    Institute of Scientific and Technical Information of China (English)

    LIAO Xiao-jun; YANG Ya-pei

    2007-01-01

    A novel optical-spectrum-encoded (OSE) analog-to-digital converter (ADC) is proposed in this letter. To simply exemplify the conversion idea, a 5-bit device structure consisted of Fabry-Perot interferometers (FPI) is analyzed and numerically simulated. The dependence of peak-transmission wavelength on modulation voltage in an electro-optical FPI and the dependence of transmitted power on incident light wavelength in an FPI are discussed and utilized to implement OSEADC.A linearly tunable mode-locked laser, as a voltage-wavelength transformer and a sampler, and chirped grating FPIs, as an encoder array, can be used to obtain much greater sampling rate and bit-resolution.

  3. Serial pixel analog-to-digital converter (ADC)

    Science.gov (United States)

    Larson, Eric D.

    2010-02-01

    This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream similar to a pseudo random number (PRN) generator. The resulting encoded pixel data is then decoded into a standard hexadecimal format before storage. The high-speed serial pixel ADC concept is based on the single-slope integrating pixel ADC architecture. Previous work has described a massively parallel pixel readout of a similar architecture. The serial ADC connection is similar to the state-of-the art method with the exception that the pixel ADC register is a shift register and the data path is a single bit. A state-of-the-art individual-pixel ADC uses a single-slope charge integration converter architecture with integral registers and "one-hot" counters. This implies that parallel data bits are routed among the counter and the individual on-chip pixel ADC registers. The data path bit-width to the pixel is therefore equivalent to the pixel ADC bit resolution.

  4. Lower Bounds on the Performance of Analog to Digital Converters

    CERN Document Server

    Osqui, Mitra; Roozbehani, Mardavij

    2012-01-01

    This paper deals with the task of finding certified lower bounds for the performance of Analog to Digital Converters (ADCs). A general ADC is modeled as a causal, discrete-time dynamical system with outputs taking values in a finite set. We define the performance of an ADC as the worst-case average intensity of the filtered input matching error, defined as the difference between the input and output of the ADC. The passband of the shaping filter used to filter the error signal determines the frequency region of interest for minimizing the error. The problem of finding a lower bound for the performance of an ADC is formulated as a dynamic game problem in which the input signal to the ADC plays against the output of the ADC. Furthermore, the performance measure must be optimized in the presence of quantized disturbances (output of the ADC) that can exceed the control variable (input of the ADC) in magnitude. We characterize the optimal solution in terms of a Bellman-type inequality. A numerical approach is pres...

  5. VHDL Implementation of Sigma-Delta Analog To Digital Converter

    Science.gov (United States)

    Chavan, R. N.; Chougule, D. G.

    2010-11-01

    Sigma-Delta modulation techniques provide a range of opportunities in a signal processing system for both increasing performance and data path optimization along the silicon area axis in the design space. One of the most challenging tasks in Analog to Digital Converter (ADC) design is to adapt the circuitry to ever new CMOS process technology. For digital circuits the number of gates per square mm app. doubles per chip generation. Integration of analog parts in newer deep submicron technologies is much more tough and additionally complicated because the usable voltage ranges are decreasing with every new integration step. This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs. Resolutions of up to 16 bit are achievable. Sample rates in the 1 MHz region are feasible so that the approach is also useful for ADCs for xDSL technologies.

  6. Automatic Synthesis of CMOS Algorithmic Analog To-Digital Converter.

    Science.gov (United States)

    Jusuf, Gani

    The steady decrease in technological feature size is allowing increasing levels of integration in analog/digital interface functions. These functions consist of analog as well as digital circuits. While the turn around time for an all digital IC chip is very short due to the maturity of digital IC computer-aided design (CAD) tools over the last ten years, most analog circuits have to be designed manually due to the lack of analog IC CAD tools. As a result, analog circuit design becomes the bottleneck in the design of mixed signal processing chips. One common analog function in a mixed signal processing chip is an analog-to-digital conversion (ADC) function. This function recurs frequently but with varying performance requirements. The objective of this research is to study the design methodology of a compilation program capable of synthesizing ADC's with a broad range of sampling rates and resolution, and silicon area and performance comparable with the manual approach. The automatic compilation of the ADC function is a difficult problem mainly because ADC techniques span such a wide spectrum of performance, with radically different implementations being optimum for different ranges of conversion range, resolution, and power dissipation. We will show that a proper choice of the ADC architectures and the incorporation of many analog circuit design techniques will simplify the synthesis procedure tremendously. Moreover, in order to speed up the device sizing, hierarchical optimization procedure and behavioral simulation are implemented into the ADC module generation steps. As a result of this study, a new improved algorithmic ADC without the need of high precision comparators has been developed. This type of ADC lends itself to automatic generation due to its modularity, simplicity, small area consumption, moderate speed, low power dissipation, and single parameter trim capability that can be added at high resolution. Furthermore, a performance-driven CMOS ADC module

  7. Delta-Sigma Modulated Photodetection Method to Reduce Laser Power Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This delta-sigma technique may be thought of as a form of analog-to-digital converter (ADC). The proposed network offers a means of processing electronic signals...

  8. Nonlinearities in SC Delta-Sigma A/D Converters

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    1998-01-01

    The effects of using nonlinear low-gain opamps in switched-capacitor delta-sigma modulators are analyzed. Using unconventional topologies, the state variables are made essentially uncorrelated with the input signal, hence opamp nonlinearity will cause very little harmonic distortion. Nonlinearity...

  9. [Principles of design of neural-network analog-to-digital converters of bioelectric signals].

    Science.gov (United States)

    Loktiukhin, V N; Chelebaev, S V

    2007-01-01

    A design principle and a procedure for synthesis of neural-network analog-to-digital converters of bioelectric signals are suggested. An example of implementation of an FPGA-based neural-network converter for classification of bioparameters is presented.

  10. Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier

    Science.gov (United States)

    Zhou, Zhimin (Inventor); Pain, Bedabrata (Inventor)

    1999-01-01

    An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

  11. 1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology

    OpenAIRE

    Hassan Raza Naqvi, Syed

    2007-01-01

    The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high pe...

  12. A Low-Power, Variable-Resolution Analog-to-Digital Converter

    OpenAIRE

    Aust, Carrie Ellen

    2000-01-01

    Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wire...

  13. Effects of Analog-to-Digital Converter Nonlinearities on Radar Range-Doppler Maps

    Energy Technology Data Exchange (ETDEWEB)

    Doerry, Armin Walter [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Dubbert, Dale F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Tise, Bertice L. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2014-07-01

    Radar operation, particularly Ground Moving Target Indicator (GMTI) radar modes, are very sensitive to anomalous effects of system nonlinearities. These throw off harmonic spurs that are sometimes detected as false alarms. One significant source of nonlinear behavior is the Analog to Digital Converter (ADC). One measure of its undesired nonlinearity is its Integral Nonlinearity (INL) specification. We examine in this report the relationship of INL to GMTI performance.

  14. Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology

    OpenAIRE

    2011-01-01

    Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mi...

  15. Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

    OpenAIRE

    Harikumar, Prakash

    2016-01-01

    Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these dist...

  16. A Pipeline Analog-To-Digital Converter for a Plasma Impedance Probe

    OpenAIRE

    El Hamoui, Mohamad A.

    2009-01-01

    Space instrumentation technology is an essential tool for rocket and satellite research, and is expected to become popular in commercial and military operations in fields such as radar, imaging, and communications. These instruments are traditionally implemented on printed circuit boards using discrete general-purpose Analog-to-Digital Converter (ADC) devices and other components. A large circuit board is not convenient for use in micro-satellite deployments, where the total payload volume is...

  17. Pipeline analog-to-digital converters for wide-band wireless communications

    OpenAIRE

    Sumanen, Lauri

    2002-01-01

    During the last decade, the development of the analog electronics has been dictated by the enormous growth of the wireless communications. Typical for the new communication standards has been an evolution towards higher data rates, which allows more services to be provided. Simultaneously, the boundary between analog and digital signal processing is moving closer to the antenna, thus aiming for a software defined radio. For analog-to-digital converters (ADCs) of radio receivers this indicates...

  18. A RESEARCH ON HIGH -PERFORMANCE ANALOG-TO-DIGITAL CONVERTERS IN WIRELESS COMMUNICATION SYSTEMSIN

    OpenAIRE

    伊藤, 朋彦; ITO,Tomohiko

    2014-01-01

    To realize next-generation high-throughput wireless communication systems, it is essential to develop analog-to-digital converters (ADC) with high conversion speed, high resolution, low power, and low operational supply voltage. In this work, the design methodologies and the new circuit architectures for these high-performance ADCs are researched.First, the methods to optimize these performances for ADCs were confirmed. In a pipeline ADC which is promising to realize the high-throughput syste...

  19. Pipeline analog-to-digital converters for wide-band wireless communications

    OpenAIRE

    Sumanen, Lauri

    2002-01-01

    During the last decade, the development of the analog electronics has been dictated by the enormous growth of the wireless communications. Typical for the new communication standards has been an evolution towards higher data rates, which allows more services to be provided. Simultaneously, the boundary between analog and digital signal processing is moving closer to the antenna, thus aiming for a software defined radio. For analog-to-digital converters (ADCs) of radio receivers this indicates...

  20. Predictive analog-to-digital converter for Fourier-transform spectrometers.

    Science.gov (United States)

    Deschênes, Jean-Daniel; Potvin, Simon; Ash, Jean-Simon; Genest, Jérôme

    2010-09-10

    This paper proposes the use of predictive analog-to-digital converters (ADC) to handle dynamic range issues in Fourier-transform spectrometers. Several predictive approaches are proposed, and one is implemented experimentally to show that the technique works. A system was implemented with 16 bit (13 bits effective) ADCs and digital-to-analog converters (DACs) operated at 8 bits to provide a comparison basis. Measurements of a blackbody at 900 °C performed using the setup show a 13 bit effective performance, limited by the input noise of the data acquisition card.

  1. High-performance Analog-to-Digital Converters and Line Drivers

    OpenAIRE

    Nieminen, Tero

    2016-01-01

    Nowadays, a high-speed medium-accuracy analog-to-digital converter (ADC) is required in numerous applications, such as a synthetic aperture radar (SAR) system, wireless local area network (WLAN) receiver, or DVD and Blu-Ray readout. As one of the two main parts, this dissertation presents the design and implementation of wideband high-speed medium-accuracy pipeline ADC as a part of a receiver of a SAR system, implemented in a deep-submicron CMOS process. Technology scaling of modern narrow li...

  2. Analog-To-Digital Converter For Sum-Of-Squares Measurements

    Science.gov (United States)

    Osborn, Stephen H.; Davies, Bryan L.; Sullender, Craig C.

    1993-01-01

    Analog-to-digital converter (ADC) circuit designed as part of larger circuit intended to measure root-mean-square current on 20-kHz powerline. Provides digital output of 11 bits of data plus 1-bit overflow signal at sampling rate of 4 MHz. Output processed by multiplying-and-accumulating circuitry to obtain sum of squares and digitized current samples accumulated during preset number of consecutive sampling periods. Used to digitize current samples from ADC directly as alternative or auxiliary output. Notable features include low power and fast conversion.

  3. Compendium of Single-Event Latchup and Total Ionizing Dose Test Results of Commercial Analog to Digital Converters

    Science.gov (United States)

    Irom, Farokh; Agarwal, Shri G.

    2012-01-01

    This paper reports single-event latchup and total dose results for a variety of analog to digital converters targeted for possible use in NASA spacecraft's. The compendium covers devices tested over the last 15 years.

  4. A new structure of substage in pipelined analog-to-digital converters

    Institute of Scientific and Technical Information of China (English)

    JIA Hua-yu; CHEN Gui-can; ZHANG Hong

    2009-01-01

    The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (ADC). When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators' decision levels. The ADC implemented in Semiconductor Manufactory International Corporation (SMIC) 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2.

  5. SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

    Science.gov (United States)

    Gauthier, M. K.; Perret, J.; Evans, K. C.

    1981-01-01

    The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

  6. Active-Pixel Image Sensor With Analog-To-Digital Converters

    Science.gov (United States)

    Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

    1995-01-01

    Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

  7. Design of 6-Bit Flash Analog to Digital Converter Using Variable Switching Voltage CMOS Comparator

    Directory of Open Access Journals (Sweden)

    Gulrej Ahmed

    2014-04-01

    Full Text Available This paper presents the design of 6-bit flash analog to digital Converter (ADC using the new variable switching voltage (VSV comparator. In general, Flash ADCs attain the highest conversion speed at the cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of 1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral nonlinearities (DNL and INL of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.

  8. A 8 bits Pipeline Analog to Digital Converter Design for High Speed Camera Application

    CERN Document Server

    Prasetyo, Eri; Ginhac, Nurul Huda Dominique; Paindavoine, Michel

    2008-01-01

    - This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage of pipeline is simple on concept, easy to implement in layout and have flexibility to increase speed. We made design and simulation using Mentor Graphics Software with 0.6 \\mu m CMOS technology with a total power dissipation of 75.47 mW. Circuit techniques used include a precise comparator, operational amplifier and clock management. A switched capacitor is used to sample and multiplying at each stage. Simulation a worst case DNL and INL of 0.75 LSB. The design operates at 5 V dc. The ADC achieves a SNDR of 44.86 dB. keywords: pipeline, switched capacitor, clock management

  9. Optimization of Power Dissipation in Pipelined Analog-to-Digital Converter

    Institute of Scientific and Technical Information of China (English)

    徐江涛; 姚素英; 赵毅强; 张为; 李树荣; 张生才

    2004-01-01

    Power optimization for pipelined analog-to-digital converter(ADC) was studied. Operational principle of pipelined ADC was discussed and noise voltage caused by two important thermal noise sources, sampling switch and amplifier,was quantitatively analyzed. Method used to minimize power and the values under simple model were presented. Power can be saved by making the sampling and feedback capacitors scale down in the pipeline.And the size of capacitors was limited by thermal noise in high resolution ADC.The equivalent circuits of the two important thermal noise sources were established.Thermal noise was optimally distributed among the pipeline stages,and the relationship between scaling factor and closed loop gain was obtained for minimum power dissipation.Typical closed loop gain was 2 or 4 in pipeline ADC, and the corresponding scaling factor was 1.217 and 1.317.These results can serve as useful guidelines for designers to minimize the ADC's power consumption.

  10. Design of Multi-Valued Quaternary Based Analog-to-Digital Converter

    Directory of Open Access Journals (Sweden)

    A. H.M.Z. Alam

    2009-01-01

    Full Text Available Problem statement: The design of multi-valued quaternary based Analog-to-Digital Converter (ADC circuit was presented. The ADC generates multi-valued logic outputs rather than the conventional binary output system to overall reduction in circuit complexity and size. Approach: Design was implemented using pipeline ADC architecture and was simulated using model parameters based on standard 0.13 µm CMOS process. Results: Performance analysis of the design showed desirable performance parameters in terms of response, low power consumption, and a sampling rate of 10 MHz at a supply voltage of 1.3V was achieved. Conclusion/Recommendations: The ADC design was suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.

  11. A low-power cryogenic analog to digital converter in standard CMOS technology

    Science.gov (United States)

    Zhao, Hongliang; Liu, Xinghui

    2013-05-01

    This paper presents a cryogenic successive approximation register (SAR) based analog to digital converter (ADC) in standard 0.35 μm complementary metal oxide semiconductor (CMOS) technology that functions from 300 K (room temperature) down to 20 K. It has been designed to operate in low temperature mid- and far-infrared imaging systems. In order to ensure the circuit performance at the extreme temperatures, a dedicated integral-based comparator architecture is employed. SPICE models have been developed for circuit simulation at 20 K. At 20 K, the experimental results exhibit that the ADC achieves 1.6 LSB maximum differential nonlinearity (DNL), 1.7 LSB maximum integral nonlinearity (INL), and 10.4 effective number of bits (ENOB) at 100 kS/s sampling rate with a current consumption of 75 μA from a 3.3 V supply.

  12. High precision (14 bit), high density (octal) analog to digital converter for spectroscopy applications

    Science.gov (United States)

    Subramaniam, E. T.; Jain, Mamta; Bhowmik, R. K.; Tripon, Michel

    2008-10-01

    Nuclear and particle physics experiments with large number of detectors require signal processing and data collection strategies that call for the ability to collect large amount of data while not sacrificing the precision and accuracy of the data being collected. This paper deals with the development of a high precision pulse peak detection, analog to digital converter (ADC) module with eight independent channels in plug-in daughter card motherboard model, best suited for spectroscopy experiments. This module provides multiple channels without cross-talk and of 14 bit resolution, while maintaining high density (each daughter card has an area of just 4.2″×0.51″) and exhibiting excellent integral nonlinearity (≤±2 mV or ±0.02% full scale reading) and differential nonlinearity (≤±1%). It was designed, developed and tested, in house, and gives added advantages of cost effectiveness and ease of maintenance.

  13. Increasing the dynamic range of a transient recorder by using two analog-to-digital converters.

    Science.gov (United States)

    Beavis, R C

    1996-01-01

    This article describes an algorithm for recording transient voltages with enhanced dynamic range by using two 8-bit analog-to-digital converters (ADCs). The method requires each transient to be recorded in both ADCs, with different input voltage gains. The transients then are compared and combined to produce a single signal that has less digitization noise and greater dynamic range than signals recorded by either ADC alone and with no decrease in the sampling rate of the ADCs. The selection of operating parameters is considered and guidelines are established for the performance of this type of transient recorder. The system described here was built as a data acquisition device for a time-of-flight mass spectrometer; however, the algorithm could be applied to other types of ADC-based applications to extend their dynamic range.

  14. GaAs multibit delta-sigma A/D converters based upon a new comparator design

    Energy Technology Data Exchange (ETDEWEB)

    Hickling, R.M.; Yagi, M.N.; Salman, H.H. [TechnoConcepts, Inc., Newbury Park, CA (United States)

    1995-12-31

    In this paper, the design of multibit delta-sigma converters based upon a new comparator bank structure is described. The comparator bank approach (patent pending) eliminates the need for comparator threshold terminals, allowing each of the individual latched comparators to operate upon the same differential input signal. This new comparator design was incorporated into a complete four-bit delta-sigma modulator which was fabricated on a 0.6{mu}m GaAs MESFET process.

  15. High-speed and high-resolution analog-to-digital and digital-to-analog converters

    NARCIS (Netherlands)

    van de Plassche, R.J.

    1989-01-01

    Analog-to-digital and digital-to-analog converters are important building blocks connecting the analog world of transducers with the digital world of computing, signal processing and data acquisition systems. In chapter two the converter as part of a system is described. Requirements of analog filte

  16. High-speed and high-resolution analog-to-digital and digital-to-analog converters

    NARCIS (Netherlands)

    van de Plassche, R.J.

    1989-01-01

    Analog-to-digital and digital-to-analog converters are important building blocks connecting the analog world of transducers with the digital world of computing, signal processing and data acquisition systems. In chapter two the converter as part of a system is described. Requirements of analog

  17. Switching Arithmetic for DC to DC Converters Using Delta Sigma Modulator Based Control Circuit

    Directory of Open Access Journals (Sweden)

    K.Diwakar

    2016-02-01

    Full Text Available In the proposed arithmetic unit for dc to dc converters using delta sigma modulator, a new technique is proposed for addition and multiplication of sampled analog signals. The output is in digital form to drive the converters. The conventional method has input signal limitation whereas in the proposed method the inputs can vary to full-scale. The addition of two discrete signals is done by sampling the two signals at a period called update period and feeding each signal to the input of signal dependant delta sigma modulator for half of the update period and combining the outputs for the update period. The extension of three discrete data addition can be carried out by using the same technique. For the multiplication of two discrete signals different method is adopted. One analog signal is fed to the input of first delta-sigma modulator (DSM1 after sampling. The sampled output of the second analog signal is negated or not negated depending on the bit state at the output of DSM1 and is fed to the input of second DSM(DSM2. The resulting bit stream at the output of DSM2 is the digital representation of the product of the sampled data of the two analog signals. In order to multiply three discrete data, the sampled output of third data is negated or not negated depending on the bit state at the output of DSM2 and is fed to the input of third DSM(DSM3. The resulting bit stream at the output of DSM3 is the digital representation of the product of the sampled data of the three analog signals. Using the proposed adder and multiplier circuits any expressions can be evaluated such that the average value of the digital output of the arithmetic unit over the update period gives the value of expressions during that period. The digital output of the arithmetic unit is used to drive the dc-dc converters.

  18. Cryogenic analog-to-digital converters using spread spectrum technology for coherent receivers

    Science.gov (United States)

    Shiao, Yu-Shao Jerry; Chiueh, Tzihong; Hu, Robert

    2012-09-01

    We propose analog-to-digital converters (ADCs) using spread spectrum technology in cryogenic receivers or at warm room temperature for coherent receiver backend systems. As receiver signals are processed and stored digitally, ADCs play a critical role in backend read-out systems. To minimize signal distortion, the down-converted signals should be digitized without further transportation. However, digitizing the signals in or near receivers may cause radio frequency interference. We suggest that spread spectrum technology can reduce the interference significantly. Moreover, cryogenic ADCs at regulated temperature in receiver dewars may also increase the bandwidth usage and simplify the backend digital signal process with fewer temperature-dependant components. While industrial semiconductor technology continuously reduces transistor power consumption, low power high speed cryogenic ADCs may become a better solution for coherent receivers. To examine the performance of cooled ADCs, first, we design 4 bit 65 nm and 40 nm CMOS ADCs specifically at 10 K temperature, which commonly is the second stage temperature in dewars. While the development of 65 nm and 40 nm CMOS ADCs are still on-going, we estimate the ENOB is 2.4 at 10 GSPS, corresponding to the correlation efficiency, 0.87. The power consumption is less than 20 mW.

  19. A Review: Compensation of Mismatches in Time Interleaved Analog to Digital Converters

    Directory of Open Access Journals (Sweden)

    Shivlal Mishra

    2014-08-01

    Full Text Available The execution of today's correspondence frameworks is exceedingly subject to the utilized Analog-to-Digital converters (ADCs, and with a specific end goal to give more flexibility and exactness to the developing correspondence innovations, superior-ADCs are needed. In this respect, the time-interleaved operation of an exhibit of ADCs (TI-ADC might be a sensible result. A TI-ADC can build its throughput by utilizing M channel ADCs or sub converters in parallel and examining the data motion in a period-interleaved way. In any case, the execution of a TI-ADC gravely suffers from the bungles around the channel ADCs. In this paper we survey the advancement in the configuration of low-intricacy advanced remedy structures and calculations for time-interleaved ADCs in the course of the most recent five years. We devise a discrete-time model, state the outline issue, and finally infer the calculations and structures. Specifically, we examine proficient calculations to outline time-differing remedy filters and additionally iterative structures using polynomial based filters. Thusly, the remuneration structure may be utilized to repay time-differing recurrence reaction befuddles in time-interleaved ADCs, and in addition to remake uniform examples from nonuniformly tested indicators. We examine the recompense structure, research its execution, and exhibit requisition zones of the structure through various illustrations. At long last, we give a standpoint to future examination questions.

  20. High-Speed Superconductive Decimation Filter for Sigma-Delta Analog to Digital Converter

    Science.gov (United States)

    Wakamatsu, Tomu; Yamanashi, Yuki; Yoshikawa, Nobuyuki

    2017-07-01

    A superconducting decimation filter is required to convert high-speed output data from a superconducting sigma-delta analog to digital (A/D) modulator to low-speed data for data acquisition by room-temperature electronics. Because the operating frequency of the conventional superconducting decimation filter is lower than that of the maximum operation frequency of A/D modulator, the system performance of the superconducting A/D converter is limited by the decimation filter. We propose a decimation filter that can operate at the sampling frequency of the A/D modulator by hybridizing a shift-register-based and a counter-based decimation filters. The investigated decimation filter can be implemented with a practical circuit area. We designed and tested the investigated decimation filter. The simulation result indicates that the maximum operation frequency of the designed decimation filter is 39.8 GHz assuming the 2.5 kA/cm2 Nb fabrication process. We experimentally confirmed the low-speed operation of the designed decimation filter with the bias margin of 93.8%-110.8%.

  1. Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS Analog to Digital Converter

    Directory of Open Access Journals (Sweden)

    Arun Kumar Sunaniya

    2013-06-01

    Full Text Available This work presents three different approaches which eliminates the resistor ladder completely and henc e reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched Inverter Scheme (SIS ADC; The test result obtained for it on 45nm technology indicates an offset erro r of 0.014 LSB. The full scale error is of -0.112LSB. Th e gain error is of 0.07 LSB, actual full scale rang e of 0.49V, worst case DNL & INL each of -0.3V. The powe r dissipation for the SIS ADC is 207.987 μ watts; Power delay product (PDP is 415.9 fWs, and the are a is 1.89μ m2. The second and third approaches are clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power dissipation as 57.5% & 71% respectively. Whereas PD P is 229.7 fWs and area is 0.05 μ m2 for Clocked SIS ADC and 107.3 fWs & 1.94 μ m2 for Sleep transistor S IS ADC.

  2. Basic Theoretical Model and Sampling Criteria for Time-Interleaved Photonic Analog-to-Digital Converters

    CERN Document Server

    Su, Feiran; Zou, Weiwen; Chen, Jianping

    2016-01-01

    In this paper, we present a basic model for time-interleaved photonic analog-to-digital converter (TIPADC) and analyze its linear, nonlinear, and noise performance. The basic operation mechanism of TIPADC is illustrated and the linear performance is analyzed in frequency domain. The mathematical expressions and the output of the system are presented in each processing step. We reveal that photonic sampling folds the whole spectrum of input signal in a narrow band, which enables the analog bandwidth of a TIPADC to be much higher than the bandwidth of back-end electronics. The feasible regions of the system is obtained in terms of system frequency response, and a set of sampling criteria determining the basic requirements to the system are summarized for typical applications. The results show that the global minimum feasible bandwidth of back-end electronics is the half of single channel sampling rate when the bandwidth of photonic sampling pulse is comparable to input signal frequency. The amplitude and phase ...

  3. Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS Analog to Digital Converter

    Directory of Open Access Journals (Sweden)

    Arun Kumar Sunaniya

    2013-07-01

    Full Text Available This work presents three different approaches which eliminates the resistor ladder completely and hencereduce the power demand drastically of a Analog to Digital Converter. The first approach is SwitchedInverter Scheme (SIS ADC; The test result obtained for it on 45nm technology indicates an offset error of0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;Power delay product (PDP is 415.9 fWs, and the area is 1.89μm2. The second and third approaches areclocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in powerdissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SISADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.

  4. Power Scaling in High Speed Analog-to-Digital Converters using Photonic Time Stretch Technique

    CERN Document Server

    Gupta, Shalabh; Walden, Robert H; Jalali, Bahram

    2009-01-01

    Factors that contribute to the rapid increase in power dissipation as a function of input bandwidth in high speed electronic Analog-to-Digital Converters (ADCs) are discussed. We find that the figure of merit (FOM), defined as the energy required per conversion step, increases linearly with bandwidth for high-speed ADCs with moderate to high resolution, or equivalently, the power dissipation increases quadratically. It is shown that by use of photonic time-stretch technique, it is possible to have ADCs in which this FOM remains constant for up to 10 GHz input RF frequency. Using this technique, it is also possible to overcome the barrier to achieving high resolution caused by clock jitter and speed limitations of electronics in such ADCs. Use of optics is actively being pursued for reducing power dissipation and achieving higher data-rates for board-level and chip-level serial communication links. In the same manner, we expect that optics will also help in reducing power dissipation in high-speed ADCs in addi...

  5. Robust symmetrical number system preprocessing for minimizing encoding errors in photonic analog-to-digital converters

    Science.gov (United States)

    Arvizo, Mylene R.; Calusdian, James; Hollinger, Kenneth B.; Pace, Phillip E.

    2011-08-01

    A photonic analog-to-digital converter (ADC) preprocessing architecture based on the robust symmetrical number system (RSNS) is presented. The RSNS preprocessing architecture is a modular scheme in which a modulus number of comparators are used at the output of each Mach-Zehnder modulator channel. The number of comparators with a logic 1 in each channel represents the integer values within each RSNS modulus sequence. When considered together, the integers within each sequence change one at a time at the next code position, resulting in an integer Gray code property. The RSNS ADC has the feature that the maximum nonlinearity is less than a least significant bit (LSB). Although the observed dynamic range (greatest length of combined sequences that contain no ambiguities) of the RSNS ADC is less than the optimum symmetrical number system ADC, the integer Gray code properties make it attractive for error control. A prototype is presented to demonstrate the feasibility of the concept and to show the important RSNS property that the largest nonlinearity is always less than a LSB. Also discussed are practical considerations related to multi-gigahertz implementations.

  6. Deep Cryogenic Low Power 24 Bits Analog to Digital Converter with Active Reverse Cryostat

    Science.gov (United States)

    Turqueti, Marcos; Prestemon, Soren; Albright, Robert

    LBNL is developing an innovative data acquisition module for superconductive magnets where the front-end electronics and digitizer resides inside the cryostat. This electronic package allows conventional electronic technologies such as enhanced metal-oxide-semiconductor to work inside cryostats at temperatures as low as 4.2 K. This is achieved by careful management of heat inside the module that keeps the electronic envelop at approximately 85 K. This approach avoids all the difficulties that arise from changes in carrier mobility that occur in semiconductors at deep cryogenic temperatures. There are several advantages in utilizing this system. A significant reduction in electrical noise from signals captured inside the cryostat occurs due to the low temperature that the electronics is immersed in, reducing the thermal noise. The shorter distance that signals are transmitted before digitalization reduces pickup and cross-talk between channels. This improved performance in signal-to-noise rate by itself is a significant advantage. Another important advantage is the simplification of the feedthrough interface on the cryostat head. Data coming out of the cryostat is digital and serial, dramatically reducing the number of lines going through the cryostat feedthrough interface. It is important to notice that all lines coming out of the cryostat are digital and low voltage, reducing the possibility of electric breakdown inside the cryostat. This paper will explain in details the architecture and inner workings of this data acquisition system. It will also provide the performance of the analog to digital converter when the system is immersed in liquid helium, and in liquid nitrogen. Parameters such as power dissipation, integral non-linearity, effective number of bits, signal-to-noise and distortion, will be presented for both temperatures.

  7. Continuous-Time Delta-Sigma Modulators for Wireless Communication

    OpenAIRE

    Andersson, Mattias

    2014-01-01

    The ever increasing data rates in wireless communication require analog to digital converters (ADCs) with greater requirements on speed and accuracy, while being power efficient to prolong battery life. This dissertation contains an introduction to the field and five papers that focus on the continuous-time (CT) Delta-Sigma modulator (DSM) as ADC. Paper I analyses the performance degradation of dynamic nonlinearity in the feedback DAC of the DSM, caused by Vth mismatch in the current-s...

  8. Radiation-tolerant delta-sigma time-to-digital converters

    CERN Document Server

    Cao, Ying; Steyaert, Michiel

    2015-01-01

    This book focuses on the design of a Mega-Gray (a standard unit of total ionizing radiation) radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) system used in a gamma-radiation environment. Several radiation-hardened-by-design (RHBD) techniques are demonstrated throughout the design of the TDC and other circuit techniques to improve the TDC's resolution in a harsh environment are also investigated. Readers can learn from scratch how to design a radiation-tolerant IC. Information regarding radiation effects, radiation-hardened design techniques and  measurements are organized in such a way that readers can easily gain a thorough understanding of the topic. Readers will also learn the design theory behind the newly proposed delta-sigma TDC. Readers can quickly acquire knowledge about the design of radiation-hardened bandgap voltage references and low-jitter relaxation oscillators, which are introduced in the content from a designer's perspective.   · �...

  9. A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

    Institute of Scientific and Technical Information of China (English)

    LI Dan; RONG Men-tian; MAO Jun-fa

    2007-01-01

    A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC).The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge.Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers.The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

  10. A complete theoretical description of the first-order delta-sigma modulation for analog-to-NRZ binary conversion

    Science.gov (United States)

    Siahmakoun, A.; Reeves, E.; Costanzo-Caso, P.

    2015-03-01

    A novel photonic analog-to-digital converter (ADC) based on asynchronous delta-sigma modulation (ADSM) has been investigated. The architecture utilizes an optical leaky integrator, optoelectronic bistable quantizer, and positive corrective feedback for a non-interferometric optical implementation of ADSM. The principles of the proposed 1st -order ADSM are mathematically modeled and simulated.

  11. Heterodyning technique to improve performance of delta-sigma-based beamformers.

    Science.gov (United States)

    Freeman, S R; Quick, M K; Morin, M A; Anderson, R C; Desilets, C S; Linnenbrink, T E; O'Donnell, M

    1999-01-01

    Delta-sigma (DeltaSigma) modulators can implement a simpler digital ultrasound beamformer than can traditional architectures based on multi-bit analog-to-digital converters (A/D). The signal-to-noise ratio (SNR) of the DeltaSigma modulators, however, suffers from limited oversampling ratios. To improve the SNR of each channel, a mixing signal heterodynes narrowband signals to lower frequencies where the baseband DeltaSigma modulator performs better. Noise figure analyses are presented that illustrate the effectiveness of this technique in improving noise performance. Also, spectral Doppler and color flow simulations are presented that realistically emulate a 32 channel oversampled beamformer and compare these results with traditional and ideal systems.

  12. A Modulated Hybrid Filter Bank for Wide-Band Analog-to-Digital Converters

    Directory of Open Access Journals (Sweden)

    Chunyan Yuan

    2014-04-01

    Full Text Available It is difficult to use a single analog-to-digital conversion (ADC to satisfy the requirements for conversion of an ultra-wideband signal. A parallel architecture for high bandwidth ADC, named cosine modulated hybrid filter bank, is presented to address this problem. First, the proposed architecture shifts the input signal spectrum by means of mixers. The modulated signal is channelized into smaller frequency subband signals using identical lowpass analog filters. Then the subband signals are digitized through identical narrowband ADCs, respectively. Finally, the digitized signals are up-sampled, then filtered and combined to reconstruct the digital representation of the original wide-band input signal. The digital filters are designed to use the eigenfilter method based on total least squares error criterion. Since the sample-and-hold circuits needed are only identical narrowband baseband circuits, the simplicity of the system makes the design easier and cheaper. Several design examples are used to illustrate the performance of the proposed system.

  13. Analysis of the resolution-bandwidth-noise trade-off in wavelength-based photonic analog-to-digital converters.

    Science.gov (United States)

    Stigwall, Johan; Galt, Sheila

    2006-06-20

    The performance of wavelength-based photonic analog-to-digital converters (ADCs) is theoretically analyzed in terms of resolution and bandwidth as well as of noise tolerance. The analysis applies to any photonic ADC in which the analog input signal is converted into the wavelength of an optical carrier, but special emphasis is put on the spectrometerlike setup in which the wavelength is mapped to a spatial spot position. The binary output signals are then retrieved by an array of fan-out diffractive optical elements that redirect the beam onto the correct detectors. In particular, the case when the input signal controls the wavelength directly such that it will chirp in frequency during each sampling pulse or interval is studied. This chirping obviously broadens the spot on the diffractive optical element array; the effect of this broadening on noise tolerance and comparator accuracy is analytically analyzed, and accurate numerical calculations of the probability of error are presented.

  14. A Delta-Sigma beamformer with integrated apodization

    DEFF Research Database (Denmark)

    Tomov, Borislav Gueorguiev; Stuart, Matthias Bo; Hemmsen, Martin Christian

    2013-01-01

    remains the same as in an unmodified one. The outputs of all receiving channels are delayed and summed, and the resulting multi-bit sample stream is filtered and decimated to become an image line. The simplicity of this beamformer allows the production of high-channel-count or very compact beamformers......This paper presents a new design of a discrete time Delta-Sigma (ΔΣ) oversampled ultrasound beamformer which integrates individual channel apodization by means of variable feedback voltage in the Delta-Sigma analog to digital (A/D) converters. The output bit-width of each oversampled A/D converter...... suitable for 2-D arrays or compact portable scanners. The new design is evaluated using measured data from the research scanner SARUS and a BK-8811 192 element linear array transducer (BK Medical, Herlev, Denmark), insonifying a water-filled wire phantom containing four wires orthogonal to the image plane...

  15. Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

    Science.gov (United States)

    Aytar, Oktay

    2015-09-01

    This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (-0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

  16. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits.

    Science.gov (United States)

    Guo, Xinjie; Merrikh-Bayat, Farnood; Gao, Ligang; Hoskins, Brian D; Alibart, Fabien; Linares-Barranco, Bernabe; Theogarajan, Luke; Teuscher, Christof; Strukov, Dmitri B

    2015-01-01

    The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2- x /Pt memristors and CMOS integrated circuit components.

  17. A photonic analog-to-digital converter using phase modulation and self-coherent detection with spatial oversampling.

    Science.gov (United States)

    Golani, Ori; Mauri, Luca; Pasinato, Fabiano; Cattaneo, Cristian; Consonnni, Guido; Balsamo, Stefano; Marom, Dan M

    2014-05-19

    We propose a new type of photonic analog-to-digital converter (ADC), designed for high-resolution (>7 bit) and high sampling rates (scalable to tens of GS/s). It is based on encoding the input analog voltage signal onto the phase of an optical pulse stream originating from a mode-locked laser, and uses spatial oversampling as a means to improve the conversion resolution. This paper describes the concept of spatial oversampling and draws its similarities to the commonly used temporal oversampling. The design and fabrication of a LiNbO(3)/silica hybrid photonic integrated circuit for implementing the spatial oversampling is shown, and its abilities are demonstrated experimentally by digitizing gigahertz signals (frequencies up to 18GHz) at an undersampled rate of 2.56GS/s with a conversion resolution of up to 7.6 effective bits. Oversampling factors of 1-4 are demonstrated.

  18. Optimal design of a low-loss 2-bit electrooptic analog-to-digital converter

    Institute of Scientific and Technical Information of China (English)

    ZHANG Chang-ming; LIAO Yi-tao; LIU Yong-zhi; DAI Ji-zhi

    2005-01-01

    The structure of the optical waveguide of 2-bit electrooptic A/D converter with proton-exchange micro prisms is optimized by the finite-difference beam propagation method (FD-BPM). The electrode parameters of the converter are optimized by conformal mapping. The optimal parameters are a half-wave voltage of Vπ= 4.5 V and a bandwidth of Δf=1.4 GHz.A normalized transmitted power of 69.75% is obtained by FD-BMP and the output waveguide gap is 300 μm.

  19. A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor.

    Science.gov (United States)

    Chakir, Mostafa; Akhamal, Hicham; Qjidaa, Hassan

    2017-01-01

    The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm(2). The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/-0.0787 LSB and 0.0811/-0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

  20. Multichannel analog-to-digital converters based on current mirrors for the optical systems

    Science.gov (United States)

    Krasilenko, Vladimir G.; Nikolskyy, A. I.; Nikolska, M. A.; Lobodzinska, R. F.

    2011-12-01

    The paper considers results of designing and modeling analogue-digital converters (ADC) based on current mirrors for the optical systems and neural networks with parallel inputs-outputs. Such ADC, named us multichannel analog-todigital converters based on current mirrors (M ADC CM). Compared with usual converters, for example, reading, a bitby- bit equilibration, and so forth, have a number of advantages: high speed and reliability, simplicity, small power consumption, the big degree of integration in linear and matrix structures. The considered aspects of designing of M_ADC CM in binary codes. Base digit cells (ABC) of such M_ADC CM, series-pipelined are connected in structures, consist from 20-30 CMOS the transistors, one photodiode, have low (1,5-3,5) supply voltage, work in current modes with the maximum values of currents (10-40)μA. Therefore such new principles of realization high-speed low-discharge M_ADC CM have allowed, as have shown modeling experiments, to reach time of transformation less than 20-30 nS at 5-6 bits of a binary code and the general power 1-5 mW. The quantity easily cascadable ABC depends on wordlength ADC, and makes n, and provides quantity of levels of quantization equal N=2n. Such simple enough on structure M ADC CM, having low power consumption CMOS-technologies has made 40 MHz, and can be increased 10 times) and accuracy (Δquantization 156,25nA for I max10μA) characteristics is show. The range can be transformed optical signals, taking into account sensitivity of modern photodetectors makes 20-200 μW in such ADC. M_ADC CM open new prospects for realization linear and matrix (with picture operands) micro photoelectronic structures which are necessary for neural networks, digital optoelectronic processors, neurofuzzy controllers, and so forth.

  1. A low-power piecewise linear analog to digital converter for use in particle tracking

    Energy Technology Data Exchange (ETDEWEB)

    Valencic, V.; Deval, P. [MEAD Microelectronics S.A., St. Sulpice (Switzerland)]|[EPFL, Lausanne (Switzerland). Electronics Labs.; Anghinolfi, F. [CERN, Geneva (Switzerland); Bonino, R.; Marra, D. La; Kambara, Hisanori [Univ. of Geneva (Switzerland)

    1995-08-01

    This paper describes a low-power piecewise linear A/D converter. A 5MHz {at} 5V with 25mW power consumption prototype has been implemented in a 1.5{micro}m CMOS process. The die area excluding pads is 5mm{sup 2}. 11-bit absolute accuracy is obtained with a new DC offset plus charge injection compensation technique used in the comparators scheme. This ADC with large dynamic range and high resolution is developed for the readout of a tracker and/or preshower in the future LHC experiments.

  2. Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

    CERN Document Server

    Chien, Yu-Tsun; Lou, Jea-Hong; Ma, Gin-Kou; Rutenbar, Rob A; Mukherjee, Tamal

    2011-01-01

    This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 $\\mu$m CMOS process.

  3. Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture

    Science.gov (United States)

    Mahmoodi, Alireza; Li, Jing; Joseph, Dileepan

    2013-01-01

    Like the human eye, logarithmic image sensors achieve wide dynamic range easily at video rates, but, unlike the human eye, they suffer from low peak signal-to-noise-and-distortion ratios (PSNDRs). To improve the PSNDR, we propose integrating a delta-sigma analog-to-digital converter (ADC) in each pixel. An image sensor employing this architecture is designed, built and tested in 0.18 micron complementary metal-oxide-semiconductor (CMOS) technology. It achieves a PSNDR better than state-of-the-art logarithmic sensors and comparable to the human eye. As the approach concerns an array of many ADCs, we use a small-area low-power delta-sigma design. For scalability, each pixel has its own decimator. The prototype is compared to a variety of other image sensors, linear and nonlinear, from industry and academia. PMID:23959239

  4. Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture

    Directory of Open Access Journals (Sweden)

    Jing Li

    2013-08-01

    Full Text Available Like the human eye, logarithmic image sensors achieve wide dynamic range easily at video rates, but, unlike the human eye, they suffer from low peak signal-to-noise-and-distortion ratios (PSNDRs. To improve the PSNDR, we propose integrating a delta-sigma analog-to-digital converter (ADC in each pixel. An image sensor employing this architecture is designed, built and tested in 0.18 micron complementary metal-oxide-semiconductor (CMOS technology. It achieves a PSNDR better than state-of-the-art logarithmic sensors and comparable to the human eye. As the approach concerns an array of many ADCs, we use a small-area low-power delta-sigma design. For scalability, each pixel has its own decimator. The prototype is compared to a variety of other image sensors, linear and nonlinear, from industry and academia.

  5. Digital pixel sensor array with logarithmic delta-sigma architecture.

    Science.gov (United States)

    Mahmoodi, Alireza; Li, Jing; Joseph, Dileepan

    2013-08-16

    Like the human eye, logarithmic image sensors achieve wide dynamic range easily at video rates, but, unlike the human eye, they suffer from low peak signal-to-noise-and-distortion ratios (PSNDRs). To improve the PSNDR, we propose integrating a delta-sigma analog-to-digital converter (ADC) in each pixel. An image sensor employing this architecture is designed, built and tested in 0.18 micron complementary metal-oxide-semiconductor (CMOS) technology. It achieves a PSNDR better than state-of-the-art logarithmic sensors and comparable to the human eye. As the approach concerns an array of many ADCs, we use a small-area low-power delta-sigma design. For scalability, each pixel has its own decimator. The prototype is compared to a variety of other image sensors, linear and nonlinear, from industry and academia.

  6. The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

    Science.gov (United States)

    Jiango, Homin; Liuo, Howard; Guzzino, Kim

    2016-07-01

    In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

  7. Compensation of multi-channel mismatches in high-speed high-resolution photonic analog-to-digital converter.

    Science.gov (United States)

    Yang, Guang; Zou, Weiwen; Yu, Lei; Wu, Kan; Chen, Jianping

    2016-10-17

    We demonstrate a method to compensate multi-channel mismatches that intrinsically exist in a photonic analog-to-digital converter (ADC) system. This system, nominated time-wavelength interleaved photonic ADC (TWI-PADC), is time-interleaved via wavelength demultiplexing/multiplexing before photonic sampling, wavelength demultiplexing channelization, and electronic quantization. Mismatches among multiple channels are estimated in frequency domain and hardware adjustment are used to approach the device-limited accuracy. A multi-channel mismatch compensation algorithm, inspired from the time-interleaved electronic ADC, is developed to effectively improve the performance of TWI-PADC. In the experiment, we configure out a 4-channel TWI-PADC system with 40 GS/s sampling rate based on a 10-GHz actively mode-locked fiber laser. After multi-channel mismatch compensation, the effective number of bit (ENOB) of the 40-GS/s TWI-PADC system is enhanced from ~6 bits to >8.5 bits when the RF frequency is within 0.1-3.1 GHz and from ~6 bits to >7.5 bits within 3.1-12.1 GHz. The enhanced performance of the TWI-PADC system approaches the limitation determined by the timing jitter and noise.

  8. High speed and wide bandwidth delta-sigma ADCs

    CERN Document Server

    Bolatkale, Muhammed; Makinwa, Kofi A A

    2014-01-01

    This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital converters (ADCs) in nanometer-CMOS processes.  The authors offer a clear and complete picture of system level challenges and practical design solutions in high-speed Delta-Sigma modulators.  Readers will be enabled to implement ADCs as continuous-time delta-sigma (CT∆Σ) modulators, offering simple resistive inputs, which do not require the use of power-hungry input buffers, as well as offering inherent anti-aliasing, which simplifies system integration. The authors focus on the design of high speed and wide-bandwidth ΔΣMs that make a step in bandwidth range which was previously only possible with Nyquist converters. More specifically, this book describes the stability, power efficiency, and linearity limits of ΔΣMs, aiming at a GHz sampling frequency.   • Provides overview of trends in Wide Bandwidth and High Dynamic Range analog-to-digital converters (ADCs); • Enables the design of a wide band...

  9. Analog-to-digital conversion

    CERN Document Server

    Pelgrom, Marcel J M

    2010-01-01

    The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for...

  10. FPGA implementation of a single-input fuzzy logic controller for boost converter with the absence of an external analog-to-digital converter

    DEFF Research Database (Denmark)

    Taeed, Fazel; Salam, Z.; Ayob, S.

    2012-01-01

    for the control surface to be approximated by a piecewise linear. It is shown that, despite the simplicity of SIFLC, its control performance is almost equivalent to that of the conventional FLC. As a proof of concept, the SIFLC is implemented using the Altera EP2C35F672C6N field-programmable gate array (FPGA......-to-digital converter (ADC). Instead, a simple analog-to-digital conversion scheme is implemented using the FPGA itself. Due to the simplicity of the SIFLC algorithm and the absence of an external ADC, the overall implementation requires only 408 logic elements and five input-output pins of the FPGA. © 2011 IEEE....

  11. A digital filter for an analog-digital converter with delta-sigma modulation

    Science.gov (United States)

    Beliavskaia, T. G.; Levchuk, Iu. P.; Strigina, E. V.

    1986-05-01

    Various methods of implementing the digital versions of analog-digital converters are examined, with attention given to homogeneous, triangular, and low-frequency digital filters. A comparison of the implementations proposed here makes it possible to optimize the structure of an analog-digital converter with respect to the hardware costs depending on the required accuracy.

  12. Synchronization sampling method based on delta-sigma analog-digital converter for underwater towed array system

    Science.gov (United States)

    Jiang, Jia-Jia; Duan, Fa-Jie; Li, Yan-Chao; Hua, Xiang-Ning

    2014-03-01

    Synchronization sampling is very important in underwater towed array system where every acquisition node (AN) samples analog signals by its own analog-digital converter (ADC). In this paper, a simple and effective synchronization sampling method is proposed to ensure synchronized operation among different ANs of the underwater towed array system. We first present a master-slave synchronization sampling model, and then design a high accuracy phase-locked loop to synchronize all delta-sigma ADCs to a reference clock. However, when the master-slave synchronization sampling model is used, both the time-delay (TD) of messages traveling along the wired transmission medium and the jitter of the clocks will bring out synchronization sampling error (SSE). Therefore, a simple method is proposed to estimate and compensate the TD of the messages transmission, and then another effective method is presented to overcome the SSE caused by the jitter of the clocks. An experimental system with three ANs is set up, and the related experimental results verify the validity of the synchronization sampling method proposed in this paper.

  13. Delta-Sigma AD-Converters Practical Design for Communication Systems

    CERN Document Server

    Gaggl, Richard

    2013-01-01

    The emphasis of this book is on practical design aspects for broadband A/D converters for communication systems. The embedded designs are employed for transceivers in the field of ADSL solutions and WLAN applications. An area- and power-efficient realization of a converter is mandatory to remain competitive in the market. The right choice for the converter topology and architecture needs to be done very carefully to result in a competitive FOM. The book begins with a brief overview of basic concepts about ADSL and WLAN to understand the ADC requirements. At architectural level, issues on different modulator topologies are discussed employing the provided technology node. The design issues are pointed out in detail for modern digital CMOS technologies, beginning with 180nm followed by 130nm and going down to 65nm feature size. Beside practical aspects, challenges to mixed-signal design level are addressed to optimize the converters in terms of consumed chip area, power consumption and design for high yield in ...

  14. Non-Inverted Buck-Boost Converters with Dual Delta Sigma Modulators

    Science.gov (United States)

    Kobori, Yasunori; Kono, Masashi; Shimizu, Toshihiko; Kobayashi, Haruo

    This paper presents a new control circuit to create high-performance non-inverted Buck-Boost converter with dual ⊿∑ modulations. Experimental load regulation, corresponding to load current steps of ±0.5A, is within 45mVpp, and the efficiency without synchronized rectifier is 83% at input voltage 2.5V and load current 0.8A.

  15. Low-frequency analog signal distribution on digital photonic networks by optical delta-sigma modulation

    Science.gov (United States)

    Kanno, Atsushi; Kawanishi, Tetsuya

    2013-12-01

    We propose a delta-sigma modulation scheme for low- and medium-frequency signal transmission in a digital photonic network system. A 10-Gb/s-class optical transceiver with a delta-sigma modulator utilized as a high-speed analog-to-digital converter (ADC) provides a binary optical signal. On the signal reception side, a low-cost and slow-speed photonic receiver directly converts the binary signal into an analog signal at frequencies from several hundreds of kilohertz several tens of megahertz. Further, by using a clock and data recovery circuit at the receiver to reduce jitters, the single-sideband phase noise of the generated signals can be significantly reduced.

  16. A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration

    Institute of Scientific and Technical Information of China (English)

    Chi Yingying; Li Dongmei

    2013-01-01

    A power efficient 96.1 dB-SFDR successive approximation register (SAR) analog-to-digital converter (ADC) with digital calibration aimed at capacitor mismatch is presented.The prototype is fabricated in a 0.18 μm CMOS.The charge redistribution (CR) design and an extra △Σ modulator for capacitance measurement are employed.With a 1.1 MS/s sampling rate,the ADC achieves 70.8 dB SNDR and the power consumption is 2.1 mW.

  17. Analog-to-digital conversion

    CERN Document Server

    Pelgrom, Marcel

    2017-01-01

    This textbook is appropriate for use in graduate-level curricula in analog-to-digital conversion, as well as for practicing engineers in need of a state-of-the-art reference on data converters. It discusses various analog-to-digital conversion principles, including sampling, quantization, reference generation, nyquist architectures and sigma-delta modulation. This book presents an overview of the state of the art in this field and focuses on issues of optimizing accuracy and speed, while reducing the power level. This new, third edition emphasizes novel calibration concepts, the specific requirements of new systems, the consequences of 22-nm technology and the need for a more statistical approach to accuracy. Pedagogical enhancements to this edition include additional, new exercises, solved examples to introduce all key, new concepts and warnings, remarks and hints, from a practitioner’s perspective, wherever appropriate. Considerable background information and practical tips, from designing a PCB, to lay-o...

  18. PIC microcontroller based external fast analog to digital converter to acquire wide-lined solid NMR spectra by BRUKER DRX and Avance-I spectrometers.

    Science.gov (United States)

    Koczor, Bálint; Rohonczy, János

    2015-01-01

    Concerning many former liquid or hybrid liquid/solid NMR consoles, the built in Analog-to-Digital Converters (ADCs) are incapable of digitizing the fids at sampling rates in the MHz range. Regarding both strong anisotropic interactions in the solid state and wide chemical shift dispersion nuclei in solution phase such as (195)Pt, (119)Sn, (207)Pb etc., the spectrum range of interest might be in the MHz range. As determining the informative tensor components of anisotropic NMR interactions requires nonlinear fitting over the whole spectrum including the asymptotic baseline, it is prohibited by low sampling rates of the ADCs. Wide spectrum width is also useful in solution NMR, since windowing of wide chemical shift ranges is avoidable. We built an external analog to digital converter with 10 MHz maximal sampling rate, which can work simultaneously with the built in ADC of the spectrometer. The ADC was tested on both Bruker DRX and Avance-I NMR consoles. In addition to the analog channels it only requires three external digital lines of the NMR console. The ADC sends data to PC via USB. The whole process is controlled by software written in JAVA which is implemented under TopSpin. Copyright © 2015 Elsevier Inc. All rights reserved.

  19. A low-power inverter-based CMOS level-crossing analog-to-digital converter for low-frequency biosignal sensing

    Science.gov (United States)

    Tanaka, Suiki; Niitsu, Kiichi; Nakazato, Kazuo

    2016-03-01

    Low-power analog-to-digital conversion is a key technique for power-limited biomedical applications such as power-limited continuous glucose monitoring. However, a conventional uniform-sampling analog-to-digital converter (ADC) is not suitable for nonuniform biosignals. A level-crossing ADC (LC-ADC) is a promising candidate for low-power biosignal processing because of its event-driven properties. The LC-ADC acquires data by level-crossing sampling. When an input signal crosses the threshold level, the LC-ADC samples the signal. The conventional LC-ADC employs a power-hungry comparator. In this paper, we present a low-power inverter-based LC-ADC. By adjusting the threshold level of the inverter, it can be used as a threshold-fixed window comparator. By using the inverter as an alternative to a comparator, power consumption can be markedly reduced. As a result, the total power consumption is successfully reduced by 90% of that of previous LC-ADC. The inverter-based LC-ADC was found to be very suitable for use in power-limited biomedical devices.

  20. 光学Sigma-Delta模数转换器的研究进展%Research and development of optical sigma-delta analog to digital converter

    Institute of Scientific and Technical Information of China (English)

    周雯; 王目光; 李博

    2012-01-01

    Optical analog to digital conversion techniques have been the developing trend of analog to digital converter(ADC) with high conversion rate and high bit accuracy in recent years. As a kind of optical ADC, optical Sigma-Delta ADC has distinguished advantages such as high conversion accuracy and simple analog circuitry. Basic principle of optical Sigma-Delta ADC is introduced. The structures of several typical optical Sigma-Delta ADCs are described detailedly.Finally the merits and demerits of optical Sigma-Delta ADCs with different structures are summed up.%采用光学模数转换技术已经成为高转换速率、高比特精度模数转换器(ADC)的发展趋势.光学Sigma-Delta ADC作为一种光学ADC,具有转换精度高和模拟电路简单等显著优点.介绍了光学Sigma-Delta ADC的基本原理,详细阐述了几种典型的光学Sigma-Delta ADC的系统结构,对不同结构的光学Sigma-Delta ADC的优缺点进行了归纳总结.

  1. Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters:State-of-the-Art and a Design Example

    Institute of Scientific and Technical Information of China (English)

    Sheng-Gang Dong; Xiao-Yang Wang; Hua Fan; Jun-Feng Gao; Qiang Li

    2013-01-01

    This paper makes a review of state-of-the-arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330μW.

  2. Small-area decimators for delta-sigma video sensors

    Science.gov (United States)

    Azabache Villar, Erika; Skorka, Orit; Joseph, Dileepan

    2014-04-01

    A delta-sigma, or sigma-delta, analog-to-digital converter (ADC) comprises both a modulator, which implements oversampling and noise shaping, and a decimator, which implements low-pass filtering and downsampling. Whereas these ADCs are ubiquitous in audio applications, their usage in video applications is emerging. Because of oversampling, it is preferable to integrate delta-sigma ADCs at the pixel level of megapixel video sensors. Moreover, with pixel-level applications, area usage per ADC is much more important than with chip-level applications, where there is only one or a few ADCs per chip. Recently, a small-area decimator was presented that is suitable for pixel-level applications. However, though the pixel-level design is small enough for invisible-band video sensors, it is too large for visible-band ones. As shown here, nanoscale CMOS processes offer a solution to this problem. Given constant specifications, small-area decimators are designed, simulated, and laid out, full custom, for 180, 130, and 65nm standard CMOS processes. Area usage of the whole decimator is analyzed to establish a roadmap for the design and demonstrate that it could be competitive compared to other digital pixel sensors, based on Nyquist-rate ADCs, that are being commercialized.

  3. Multirate Formulation for Mismatch Sensitivity Analysis of Analog-to-Digital Converters That Utilize Parallel ΣΔ-Modulators

    Directory of Open Access Journals (Sweden)

    Per Löwenborg

    2008-02-01

    Full Text Available A general formulation based on multirate filterbank theory for analog-to-digital converters using parallel sigmadelta modulators in conjunction with modulation sequences is presented. The time-interleaved modulators (TIMs, Hadamard modulators (HMs, and frequency-band decomposition modulators (FBDMs can be viewed as special cases of the proposed description. The usefulness of the formulation stems from its ability to analyze a system's sensitivity to aliasing due to channel mismatch and modulation sequence level errors. Both Nyquist-rate and oversampled systems are considered, and it is shown how the matching requirements between channels can be reduced for oversampled systems. The new formulation is useful also for the derivation of new modulation schemes, and an example is given of how it can be used in this context.

  4. An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology

    Institute of Scientific and Technical Information of China (English)

    Zhang Zhengping; Wang Yonglu; Huang Xingfa; Shen Xiaofeng; Zhu Can; Zhang Lei; Yu Jinshan; Zhang Ruitao

    2011-01-01

    A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented.The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

  5. Estimation of channel mismatches in time-interleaved analog-to-digital converters based on fractional delay and sine curve fitting.

    Science.gov (United States)

    Guo, Lianping; Tian, Shulin; Jiang, Jun

    2015-03-01

    This paper proposes an algorithm to estimate the channel mismatches in time-interleaved analog-to-digital converter (TIADC) based on fractional delay (FD) and sine curve fitting. Choose one channel as the reference channel and apply FD to the output samples of reference channel to obtain the ideal samples of non-reference channels with no mismatches. Based on least square method, the sine curves are adopted to fit the ideal and the actual samples of non-reference channels, and then the mismatch parameters can be estimated by comparing the ideal sine curves and the actual ones. The principle of this algorithm is simple and easily understood. Moreover, its implementation needs no extra circuits, lowering the hardware cost. Simulation results show that the estimation accuracy of this algorithm can be controlled within 2%. Finally, the practicability of this algorithm is verified by the measurement results of channel mismatch errors of a two-channel TIADC prototype.

  6. Analog-to-digital conversion

    CERN Document Server

    Pelgrom, Marcel J. M

    2013-01-01

    This textbook is appropriate for use in graduate-level curricula in analog to digital conversion, as well as for practicing engineers in need of a state-of-the-art reference on data converters.  It discusses various analog-to-digital conversion principles, including sampling, quantization, reference generation, nyquist architectures and sigma-delta modulation.  This book presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed, while reducing the power level. This new, second edition emphasizes novel calibration concepts, the specific requirements of new systems, the consequences of 45-nm technology and the need for a more statistical approach to accuracy.  Pedagogical enhancements to this edition include more than twice the exercises available in the first edition, solved examples to introduce all key, new concepts and warnings, remarks and hints, from a practitioner’s perspective, wherever appropriate.  Considerable background information and pr...

  7. A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

    Science.gov (United States)

    Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

    2014-11-17

    A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

  8. Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

    Directory of Open Access Journals (Sweden)

    Al Al

    2015-01-01

    Full Text Available Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ-comparator, the encoder and the parallel input serial output (PISO register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

  9. 100 gigasamples per second 12 bits optoelectronic analog-to-digital converter design and implementation based on cellular polyphase-sampling architecture

    Science.gov (United States)

    Villa-Angulo, Carlos

    The next generation digital information systems such as high performance computers, multigigabit/sec communication networks, distributed sensors, three dimensional digital imaging systems etc, will require analog-to-digital converters (ADCs) with high sampling rates exceeding 10 Gigasamples per second (GSPS) and high bit resolution of at least 10 bits. Such performance criteria are difficult to achieve with silicon electronics technology because the switching speeds peak at about 10-20GHz. Also, timing jitters, amplitude fluctuations, phase noise, thermal noise, and harmonic distortion, all contribute to reductions in ADC bit resolution as sampling rate increases. Photonics ADCs are rapidly emerging as the enabling technologies for high-performance digital signal processing systems. For this technology, high optical pulses repetition rate (in the order of GHz) with low time jitter and pulse width in the femtoseconds regime are the major attractive characteristics of optical sources. In this dissertation work, a novel 102.4 GSPS 12-bit optoelectronic analog-to-digital converter architecture that is based on a Cellular Polyphase-Sampling architecture is introduced. First, a 102.4 GHz all-optical clock was designed and implemented using a femtosecond laser source and passive optical components. Second, a novel optoelectronic architecture for optical sampling and parallel demultiplexing of different phases (polyphase) of an input analog signal is presented. The optoelectronic sampling and demultiplexing architecture is composed by 20 optoelectronic subcircuit referred as "OE-Cell"; these have been designed and implemented using optical passive components and InGaAs PIN photodiodes. A unique feature of this approach is that the optically sampled RF signal always remains in the electrical domain and thus eliminates the need for electrical-to-optical and optical-to-electrical conversions. The electrical-in to electrical-out transfer functions of the sampling and

  10. Successive approximation-like 4-bit full-optical analog-to-digital converter based on Kerr-like nonlinear photonic crystal ring resonators

    Science.gov (United States)

    Tavousi, Alireza; Mansouri-Birjandi, Mohammad Ali; Saffari, Mehdi

    2016-09-01

    Implementing of photonic sampling and quantizing analog-to-digital converters (ADCs) enable us to extract a single binary word from optical signals without need for extra electronic assisting parts. This would enormously increase the sampling and quantizing time as well as decreasing the consumed power. To this end, based on the concept of successive approximation method, a 4-bit full-optical ADC that operates using the intensity-dependent Kerr-like nonlinearity in a two dimensional photonic crystal (2DPhC) platform is proposed. The Silicon (Si) nanocrystal is chosen because of the suitable nonlinear material characteristic. An optical limiter is used for the clamping and quantization of each successive levels that represent the ADC bits. In the proposal, an energy efficient optical ADC circuit is implemented by controlling the system parameters such as ring-to-waveguide coupling coefficients, the ring's nonlinear refractive index, and the ring's length. The performance of the ADC structure is verified by the simulation using finite difference time domain (FDTD) method.

  11. A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

    Science.gov (United States)

    Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

    2016-11-01

    In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

  12. Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to- Digital Converter Based on a Polyphase Demultiplexing Architecture

    Directory of Open Access Journals (Sweden)

    C. Villa-Angulo

    2013-01-01

    Full Text Available In this paper we present the practical implementation of a high-speed polyphase sampling and demultiplexingarchitecture for optoelectronics analog-to-digital converters (OADCs. The architecture consists of a one-stage divideby-eight decimator circuit where optically-triggered samplers are cascaded to sample an analog input signal, anddemultiplex different phases of the sampled signal to yield low data rate for electronic quantization. Electrical-in toelectrical-out data format is maintained through the sampling, demultiplexing and quantization processes of thearchitecture thereby avoiding the need for electrical-to-optical and optical-to-electrical signal conversions. Weexperimentally demonstrate a 10.24 giga samples per second (GS/s, 12-bit resolution OADC system comprising theoptically-triggered sampling circuits integrated with commercial electronic quantizers. Measurements performed on theOADC yielded an effective bit resolution (ENOB of 10.3 bits, spurious free dynamic range (SFDR of -32 dB andsignal-to-noise and distortion ratio (SNDR of 63.7 dB.

  13. 数字信道化技术中ADC的性能分析%Performance Analysis of Analog-to-Digital Converters in Digital Channelization Techniques

    Institute of Scientific and Technical Information of China (English)

    马丽川; 潘亚汉; 袁方; 刘欣

    2011-01-01

    In the field of satellite communication,digital channelization techniques are used more and more widely.The analog-to-digital converter,one part of the digital channelizer,plays a great important role in the digital channelization techniques.Based on the elementary theory and performance of ADC,the effect on digital modulated signals exerted by the different number of quantization bit are discussed and simulated.%在卫星通信系统中,数字信道化技术的应用越来越广泛,而模数转换器(ADC)作为数字信道化器前端不可缺少的一部分起着至关重要的作用。基于ADC基本原理和性能,仿真分析了在ADC量化位数不同的条件下,ADC对数字已调信号解调性能的影响。

  14. Design and implementation of a platform for experimental testing and validation of analog-to-digital converters: static and dynamic parameters

    Directory of Open Access Journals (Sweden)

    Mansour Imen Ben

    2017-01-01

    Full Text Available This paper presents an implementation of a data acquisition system for analog-to-digital converters (ADCs using “Laboratory Virtual Instrument Engineering Workbench (LabVIEW” as software for data analysis. The designed and implemented platform allows interaction with the device under test through means of data acquisition and instrument controls. Developing custom tests in LabVIEW can result in reduced test time, which in turn will help reduce costs in testing. This system was developed for evaluation purposes of ADC's static and dynamic parameters (gain error, offset error, DNL, INL, SNR, SINAD, IMD, etc. using single and multi-frequency signals. The virtual control and analysis instrument was created in “LabVIEW” environment to control test signals generation and data acquisition. The testing performance of the platform is demonstrated using the classical ADC circuit “ADC0804”. A comparison with experimental results obtained by CANTEST platform from Bordeaux University (France is also presented to highlight our platform.

  15. Design challenges of EO polymer based leaky waveguide deflector for 40 Gs/s all-optical analog-to-digital converters

    Science.gov (United States)

    Hadjloum, Massinissa; El Gibari, Mohammed; Li, Hongwu; Daryoush, Afshin S.

    2016-08-01

    Design challenges and performance optimization of an all-optical analog-to-digital converter (AOADC) is presented here. The paper addresses both microwave and optical design of a leaky waveguide optical deflector using electro-optic (E-O) polymer. The optical deflector converts magnitude variation of the applied RF voltage into variation of deflection angle out of a leaky waveguide optical beam using the linear E-O effect (Pockels effect) as part of the E-O polymer based optical waveguide. This variation of deflection angle as result of the applied RF signal is then quantized using optical windows followed by an array of high-speed photodetectors. We optimized the leakage coefficient of the leaky waveguide and its physical length to achieve the best trade-off between bandwidth and the deflected optical beam resolution, by improving the phase velocity matching between lightwave and microwave on one hand and using pre-emphasis technique to compensate for the RF signal attenuation on the other hand. In addition, for ease of access from both optical and RF perspective, a via-hole less broad bandwidth transition is designed between coplanar pads and coupled microstrip (CPW-CMS) driving electrodes. With the best reported E-O coefficient of 350 pm/V, the designed E-O deflector should allow an AOADC operating over 44 giga-samples-per-seconds with an estimated effective resolution of 6.5 bits on RF signals with Nyquist bandwidth of 22 GHz. The overall DC power consumption of all components used in this AOADC is of order of 4 W and is dominated by power consumption in the power amplifier to generate a 20 V RF voltage in 50 Ohm system. A higher sampling rate can be achieved at similar bits of resolution by interleaving a number of this elementary AOADC at the expense of a higher power consumption.

  16. All optical binary delta-sigma modulator

    Science.gov (United States)

    Sayeh, Mohammad R.; Siahmakoun, Azad

    2005-09-01

    This paper describes a novel A/D converter called "Binary Delta-Sigma Modulator" (BDSM) which operates only with nonnegative signal with positive feedback and binary threshold. This important modification to the conventional delta-sigma modulator makes the high-speed (>100GHz) all-optical implementation possible. It has also the capability to modify its own sampling frequency as well as its input dynamic range. This adaptive feature helps designers to optimize the system performance under highly noisy environment and also manage the power consumption of the A/D converters.

  17. A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

    Science.gov (United States)

    Xin, Jing; Yiqi, Zhuang; Hualian, Tang; Li, Dai; Yongqian, Du; Li, Zhang; Hongbo, Duan

    2014-02-01

    A power-efficient 12-bit 40-MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two opamp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC's performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.43 to +0.48 LSB and -1.62 to +1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure-of-merit (FOM) of 0.63 pJ per conversion-step.

  18. A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology*

    Institute of Scientific and Technical Information of China (English)

    Yu Jinshan; Zhang Ruitao; Zhang Zhengping; Wang Yonglu; Zhu Can; Zhang Lei; Yu Zhou; Han Yong

    2011-01-01

    A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

  19. Optimization of Modulator and Circuits for Low Power Continuous-Time Delta-Sigma ADC

    DEFF Research Database (Denmark)

    Marker-Villumsen, Niels; Bruun, Erik

    2014-01-01

    This paper presents a new optimization method for achieving a minimum current consumption in a continuous-time Delta-Sigma analog-to-digital converter (ADC). The method is applied to a continuous-time modulator realised with active-RC integrators and with a folded-cascode operational transconduc......- tance amplifier (OTA). Based on a detailed circuit analysis of the integrator and the OTA, key expression are derived relating the biasing current of the OTA to the noise requirements of the integrator. In the optimization the corner frequency of the modulator loop filter and the number of quantizer...... levels are swept. Based on the results of the circuit analysis, for each modulator combination the summed current consumption of the 1st integrator and quantizer of the ADC is determined. By also sweeping the partitioning of the noise power for the different circuit parts, the optimum modulator...

  20. A design method for high performance seismic data acquisition based on oversampling delta-sigma modulation

    Science.gov (United States)

    Gao, Shanghua; Xue, Bing

    2017-04-01

    The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10-20 dB lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter (ADC) chips with more than 24 bits in the market. So the key difficulties for higher-resolution data acquisition devices lie in achieving more than 24-bit ADC circuit. In the paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus forming a complete analog to digital converting circuit. Experimental results show that, within the 0.1-40 Hz frequency range, the circuit board's dynamic range reaches 158.2 dB, its resolution reaches 25.99 dB, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even solve the amplitude-limitation problem that broadband observation systems so commonly have to face during strong earthquakes.

  1. 23 µW 8.9-effective number of bit 1.1 MS/s successive approximation register analog-to-digital converter with an energy-efficient digital-to-analog converter switching scheme

    Directory of Open Access Journals (Sweden)

    Lei Sun

    2014-08-01

    Full Text Available This study presents a successive approximation register analog-to-digital converter with an energy-efficient switching scheme. A split-most significant bit capacitor array is used with a least significant bit-down switching scheme. Compared with the conventional binary-weighted capacitor array, it reduces the area and average switching energy by 50 and 87% under the same unit capacitor. Moreover, capacitor matching requirement is relaxed by 75%. A prototype design was fabricated in a 0.13 µm complementary metal oxide semiconductor process. It consumes 23.2 µW under 1 V analog supply and 0.5 V digital supply. Measured results show a peak signal-to-distortion-and-noise ratio of 55.2 dB and an effective resolution bandwidth up to 1.1 MHz when it operates at 1.1 MS/s. Its figure-of-merit is 44.1 fJ/conversion-step.

  2. ANALOG-TO-DIGITAL CONVERSION OF SIGNALS WITH ANGULAR MANIPULATION FOR SOFTWARE DEFINED RADIO SYSTEMS

    OpenAIRE

    A. Y. Tsvetkov; A. G. Prygunov; N. D. Anikeichik; I. P. Rybalko; N. A. Osipov

    2016-01-01

    The paper deals with the search of ways for speeding up and accuracy increase of conversion of modern analog-to-digital converters. The main shortcomings interfering a solution of this task including the field of optoelectronic analog-to-digital converters are provided. The proposed solution gives the chance to increase high-speed performance of analog-to-digital converters on the basis of holographic interferometry principles without reducing their accuracy of conversion. The optical scheme ...

  3. Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion

    Science.gov (United States)

    Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.; Fossum, Eric R.

    1993-01-01

    The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance.

  4. Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion

    Science.gov (United States)

    Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.; Fossum, Eric R.

    1993-01-01

    The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance.

  5. Low-Power, Low-Voltage Analog to Digital ΣΔ

    DEFF Research Database (Denmark)

    Wismar, Ulrik Sørensen

    2007-01-01

    implementations of audio band modulators used as CMOS analog to digital converters. The intended application is hearing aids where analog to digital converters are used to convert the preamplied signal from a microphone into a digital signal which is fed into a microprocessor. A hearing aid is battery driven...

  6. Flexible Architecture of Ultra-Low-Power Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Rafał Długosz

    2007-01-01

    Full Text Available A novel 8-bit current mode interleaved successive approximation (SAR analog-digital converter (ADC has been proposed. The proposed converter architecture is very flexible. Using two control DC voltages and one reference current, the converter can be tuned to work with different sampling rates, number of bits of resolution, and power consumption levels. Due to its very low-power consumption and flexibility, the converter is particularly suitable for application in wireless sensor networks. Compared to other solutions presented in the literature, the proposed converter achieves very high figure of merit (FOM value due to numerous low-power circuit innovations utilized in its design. The circuit has been implemented in CMOS 0.18 μm technology. Minimum energy consumption has been found to be in a 25–250 kS/s range (for clock sampling frequency in a 200 kHz--2 MHz range for a single SAR section with the corresponding power dissipation varying from 220 nW to 560 nW for 0.55 V power supply.

  7. High-speed analog-to-digital conversion

    CERN Document Server

    Demler, Michael J

    1991-01-01

    This book covers the theory and applications of high-speed analog-to-digital conversion. An analog-to-digital converter takes real-world inputs (such as visual images, temperature readings, and rates of speed) and transforms them into digital form for processing by computer. This book discusses the design and uses of such circuits, with particular emphasis on improving the speed of the conversion process and the accuracy of its output--how well the output is a corresponding digital representation of the output*b1input signal. As computers become increasingly interfaced to the outside world, ""

  8. Low Power Continuous-Time Delta-Sigma ADC with Current Output DAC

    DEFF Research Database (Denmark)

    Marker-Villumsen, Niels; Jørgensen, Ivan Harald Holger; Bruun, Erik

    2015-01-01

    The paper presents a continuous-time (CT) DeltaSigma (∆Σ) analog-to-digital converter (ADC) using a current output digital-to-analog converter (DAC) for the feedback. From circuit analysis it is shown that using a current output DAC makes it possible to relax the noise requirements of the 1st...... integrator of the loopfilter, and thereby reduce the current consumption. Furthermore, the noise of the current output DAC being dependent on the ADC input signal level, enabling a dynamic range that is larger than the peak signal-to-noise ratio (SNR). The current output DAC is used in a 3rd order multibit...... CT ∆Σ ADC for audio applications, designed in a 0.18 µm CMOS process, with active-RC integrators, a 7-level Flash ADC quantizer and current output DAC for the feedback. From simulations the ADC achieves a dynamic range of 95.0 dB in the audio band, with a current consumption of 284 µA for a 1.7 V...

  9. A standardized way to select, evaluate, and test an analog-to-digital converter for ultrawide bandwidth radiofrequency signals based on user's needs, ideal, published,and actual specifications

    Science.gov (United States)

    Chang, Daniel Y.; Rowe, Neil C.

    2012-06-01

    The most important adverse impact on the Electronic Warfare (EW) simulation is that the number of signal sources that can be tested simultaneously is relatively small. When the number of signal sources increases, the analog hardware, complexity and costs grow by the order of N2, since the number of connections among N components is O(N*N) and the signal communication is bi-directional. To solve this problem, digitization of the signal is suggested. In digitizing a radiofrequency signal, an Analog-to-Digital Converter (ADC) is widely used. Most research studies on ADCs are conducted from designer/test engineers' perspective. Some research studies are conducted from market's perspective. This paper presents a generic way to select, evaluate and test ultra high bandwidth COTS ADCs and generate requirements for digitizing continuous time signals from the perspective of user's needs. Based on user's needs, as well as vendor's published, ideal and actual specifications, a decision can be made in selecting a proper ADC for an application. To support our arguments and illustrate the methodology, we evaluate a Tektronix TADC-1000, an 8-bit and 12 gigasamples per second ADC. This project is funded by JEWEL lab, NAWCWD at Point Mugu, CA.

  10. An analog-to-digital conversion system with a logarithmic characteristic

    Science.gov (United States)

    Bellomo, A.

    1972-01-01

    Detailed analysis of an analog-to-digital conversion system consisting of a linear converter and a logarithmic amplifier containing nonlinear elements. It is shown that the small-signal resolution of such a system is much greater than that of linear systems used under the same conditions. A design for a low-power analog-to-digital converter operating at medium speed with a large input signal variation field is outlined.

  11. ANALOG-TO-DIGITAL CONVERSION OF SIGNALS WITH ANGULAR MANIPULATION FOR SOFTWARE DEFINED RADIO SYSTEMS

    Directory of Open Access Journals (Sweden)

    A. Y. Tsvetkov

    2016-05-01

    Full Text Available The paper deals with the search of ways for speeding up and accuracy increase of conversion of modern analog-to-digital converters. The main shortcomings interfering a solution of this task including the field of optoelectronic analog-to-digital converters are provided. The proposed solution gives the chance to increase high-speed performance of analog-to-digital converters on the basis of holographic interferometry principles without reducing their accuracy of conversion. The optical scheme of interferential and holographic method of analog-to-digital conversion and results of its mathematical modeling are provided. Some recommendations about hardware implementation of this analog data digitizer are formulated. The physical principles and approaches to a choice of the converter structural elements are explained. An example of forming the functional scheme of a decoder for a luminous flux intensity in terms of registration of analog-to-digital converter is reviewed. The practical importance of the provided method consists in possibility of creation of analog-to-digital converters with high-speed performance about 600 MHz and with an accuracy of conversion up to 12 bits.

  12. Space-time delta-sigma modulation for reception of multiple simultaneous independent RF beams

    Science.gov (United States)

    Rong, Guoguang; Black, Bruce A.; Siahmakoun, Azad Z.

    2005-09-01

    In this paper we introduce and analyze a multiple-RF-beam beamformer in receive mode utilizing the principle of space-time delta-sigma modulation. This principle is based on sampling input signals in both time and space and converting the sampled signals into a digital format by delta-sigma conversion. Noise shaping is achieved in 2D frequency domain. We show that the modulator can receive signals of narrow and wide bandwidths with steering capability, can receive multiple beams, and establish tradeoffs between sampling in time and in space. The ability of the modulator to trade off between time and space provides an effective way to sample high frequency RF signals without down conversion. In addition, a space-time delta-sigma modulator has better performance than a solely temporal delta-sigma modulator (for the same filter order), as is typically used in communication systems to digitize the down-converted analog signals.

  13. A high performance receiver using a subsampling mixer and Delta-Sigma ADC

    OpenAIRE

    小林,和也; Kobayashi, Kazuya

    2012-01-01

    In this paper, we propose a high performance receiver architecture for wireless communication systems, such as Bluetooth. This architecture uses a subsampling mixer and a delta-sigma modulator. The proposed sub-sampling mixer has complex band-pass characteristics. The band-pass filter suppresses the aliasing noise generated by the subsampling mixer. The proposed discrete time delta-sigma modulator has an up-conversion mixer and a down-conversion mixer. An intermediate frequency signal convert...

  14. Adaptive Delta-Sigma Modulation for Enhanced Input Dynamic Range

    Directory of Open Access Journals (Sweden)

    Clemens M. Zierhofer

    2008-06-01

    Full Text Available An adaptive delta-sigma modulator of 1st order with one-bit quantization is presented. Adaptation is instantaneous and based on an exponential law. The feedback signal is a multibit discrete-level signal generated by a digital-to-analog converter (DAC. Compared to a nonadaptive delta-sigma modulator of 1st order, the input dynamic range is significantly enhanced. The gain in dynamic range is 6 dB per bit defining the feedback amplitude. The influence of nonideal DAC performance is discussed. It is demonstrated that an implementation of the system is realistic with standard CMOS technology. To relax the requirements to the one-bit quantizer, the quantizer input signal is amplified adaptively (Q-Switching.

  15. Adaptive Delta-Sigma Modulation for Enhanced Input Dynamic Range

    Science.gov (United States)

    Zierhofer, Clemens M.

    2006-12-01

    An adaptive delta-sigma modulator of 1st order with one-bit quantization is presented. Adaptation is instantaneous and based on an exponential law. The feedback signal is a multibit discrete-level signal generated by a digital-to-analog converter (DAC). Compared to a nonadaptive delta-sigma modulator of 1st order, the input dynamic range is significantly enhanced. The gain in dynamic range is 6 dB per bit defining the feedback amplitude. The influence of nonideal DAC performance is discussed. It is demonstrated that an implementation of the system is realistic with standard CMOS technology. To relax the requirements to the one-bit quantizer, the quantizer input signal is amplified adaptively (Q-Switching).

  16. 12 bit 40 MS/s pipelined analog-to-digital converter with an improved bootstrapped switch%采用改进自举开关的12 bit 40 MS/s流水线ADC

    Institute of Scientific and Technical Information of China (English)

    景鑫; 庄奕琪; 汤华莲; 戴力

    2013-01-01

    设计了一种用于分时长期演进(TD-LTE)系统基带信号处理的12 bit 40 MS/s无校准的流水线模数转换器(ADC).在采样保持前端设计了一种改进的栅压自举开关,有效减少了电路的非线性失真,提高了开关的线性度.设计的ADC采用全2.5 bit/级架构,利用级电路缩减技术满足面积与功耗要求.芯片基于130 nmCMOS(互补金属氧化物半导体)工艺流片验证,电源电压1.2V.实测整个ADC,最大INL(积分非线性)和DNL(微分非线性)误差分别为1.48 LSB(最低有效位)和0.48 LSB.动态特性测试结果表明:在40 MS/s采样频率、-1 dBFS(满度相对电平)、4.3 MHz正弦输入下,设计的模数转换器信噪失真比(SNDR)达到63.55dB,无杂散动态范围(SFDR)达到76.37 dB.整个ADC在40 MS/s全速工作时功耗48 mW,芯片面积(包含Pad)为3.1 mm×1.4 mm.%A 12 bit 40 MS/s calibration-free pipelined analog-to-digital convert (ADC) used in TDLTE(time division long term evolution) baseband was described.A gate-bootstrapping switch's linearity was improved and designed as the input-sampling switches in the front sample-and-hold (S/H) circuit in order to reduce the nonlinearity distortion of the ADC effectively.To achieve low power and small chip size,the pipelined stages were scaled in current and area,and implemented with 2.5 bit/stage architecture.The ADC was fabricated in 130 nm CMOS(complementary metal oxide semiconductor) process with 1.2 V power supply.The results show that the ADC achieves 63.55 dB signal-to-noise and distortion ration (SNDR),76.37 dB spurious free dynamic range (SFDR) under the conditions of 40 MS/s sampling rate and-1 dBFS (dB full scale),4.3 MHz sinusoidal input signal.The measured maximum integral nonlinearities (INL) errors and differential nonlinearities (DNL) errors are 1.48 LSB (least significant bit) and 0.48 LSB at 12 bit level,respectively.The entire ADC consumes 48 mW when operating at 40 MS/s sampling rate and the chip size (including Pad

  17. Linear device applications analysis: delta sigma modulator study. Final report September 1976-October 1977

    Energy Technology Data Exchange (ETDEWEB)

    Welling, P.A.

    1977-09-01

    The report describes the operation of the delta sigma modulator A-D converter and addresses the issues of integrating and hardening the circuit. The input/output relationship of the converter is stated for both DC and AC signals. A survey of commercial converters which use delta sigma modulation or related techniques is summarized. Various current switch designs, amplifier technologies, and resistive materials are examined to develop a radiation hard, integrated circuit configuration. A design which automatically nulls offset in the converter is outlined. (Author)

  18. Broadband analog to digital conversion with spatial-spectral holography

    Energy Technology Data Exchange (ETDEWEB)

    Babbitt, W. Randall [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States)]. E-mail: babbitt@physics.montana.edu; Neifeld, Mark A. [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States); Merkel, Kristian D. [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States)

    2007-11-15

    A new approach to broadband photonic-assisted analog-to-digital converter (ADC) technology is proposed and analyzed. The core of the device is a spatial spectral holographic (SSH) material, which can directly record the signals of interest in the frequency domain. An SSH-ADC acts as a frequency-domain stretch processor, which leverages the high performance of conventional ADCs by converting high bandwidth input signals to low bandwidth output signals without loss of information. Analysis of a 10 GHz bandwidth SSH-ADC predicts that 10-bit performance can be achieved with currently available materials and components. SSH-ADC technology is scalable to bandwidths over 100 GHz with recently developed SSH materials. While the SSH-ADC is a transient digitizer, the spatial parallelism of SSH materials can be utilized to enable continuous digitization.

  19. Reduced complexity MASH delta-sigma modulator

    OpenAIRE

    Ye, Zhipeng; Kennedy, Michael Peter

    2007-01-01

    A reduced complexity digital multi-stage noise shaping (MASH) delta-sigma modulator for fractional-N frequency synthesizer applications is proposed. A long word is used for the first modulator in a MASH structure; the sequence length is maximized by setting the least significant bit of the input to 1; shorter words are used in subsequent stages. Experimental results confirm simulations

  20. Xampling: Analog to Digital at Sub-Nyquist Rates

    CERN Document Server

    Mishali, Moshe; Dounaevsky, Oleg; Shoshan, Eli

    2009-01-01

    We present a sub-Nyquist analog-to-digital converter of wideband inputs. Our circuit realizes the recently proposed modulated wideband converter, which is a flexible platform for sampling signals according to their actual bandwidth occupation. The theoretical work enables, for example, a sub-Nyquist wideband receiver, which has no prior information on the transmitter carrier positions. Our design supports input signals with 2 GHz Nyquist rate and 120 MHz spectrum occupancy, with arbitrary transmission frequencies. The sampling rate is as low as 280 MHz. To the best of our knowledge, this is the first reported wideband hardware for sub-Nyquist conversion. Furthermore, the modular design is proven to compete with state-of-the-art Nyquist ADCs in terms of resolution bits and full-scale range. We describe the various circuit design considerations, with an emphasis on the nonordinary challenges the converter introduces: mixing a signal with a multiple set of sinusoids, rather than a single local oscillator, and ge...

  1. Analog to Digital Conversion in Physical Measurements

    CERN Document Server

    Kapitaniak, T; Feudel, U; Grebogi, C

    1999-01-01

    There exist measuring devices where an analog input is converted into a digital output. Such converters can have a nonlinear internal dynamics. We show how measurements with such converting devices can be understood using concepts from symbolic dynamics. Our approach is based on a nonlinear one-to-one mapping between the analog input and the digital output of the device. We analyze the Bernoulli shift and the tent map which are realized in specific analog/digital converters. Furthermore, we discuss the sources of errors that are inevitable in physical realizations of such systems and suggest methods for error reduction.

  2. All digital monolithic scanning readout based on Sigma-Delta analog to digital conversion

    Science.gov (United States)

    Mandl, William; Rutschow, Carl

    1992-07-01

    It is generally accepted that sensor systems can benefit from some form of on-focal-plane A/D conversion in terms of overall system noise improvement. The issue of whether or not the Delta-Sigma modulation process can be applied to the development of an approach using conventional A/D converters or cryogenic circuit materials is addressed from the standpoint of the scanning focal plane. Each pixel row of the scanning sensor is treated as a continuous analog signal source with a fixed signal bandwidth. By allocating a Delta-Sigma converter per sensor pixel row, theory predicts the oversample rate required to achieve the designed conversion resolution. The Delta-Sigma consists of two major parts. The modulator, which samples the analog input and develops a corresponding digital bit stream, and the digital signal processor, which compresses the bit stream into the Nyquist rate multibit codes and performs noise filtering, are described. Only the modulator needs to be on the focal plane since its output is digital. This reduces the development problem to one of fitting the modulator only into the allocated space and power budget per sensor.

  3. Superconducting bandpass delta-sigma modulator

    Science.gov (United States)

    Bulzacchelli, J. F.; Lee, H.-S.; Misewich, J. A.; Ketchen, M. B.

    1999-11-01

    Bandpass delta-sigma modulators digitize narrowband signals with high dynamic range and linearity. The required sampling rate is only a few times higher than the centre frequency of the input. This paper presents a superconducting bandpass delta-sigma modulator for direct analogue-to-digital conversion of RF signals in the GHz range. The input signal is capacitively coupled to one end of a microstrip transmission line, and a single flux quantum balanced comparator quantizes the current flowing out of the other end. Quantization noise is suppressed at the quarter-wave resonance of the transmission line (about 2 GHz in our design). Circuit performance at a 20 GHz sampling rate has been studied with several long JSIM simulations. Full-scale (FS) input sensitivity is 20 mV (rms), and in-band noise is -53 dBFS and -57 dBFS over bandwidths of 39 MHz and 19.5 MHz, respectively. In-band intermodulation distortion is better than -69 dBFS.

  4. Superconducting bandpass delta-sigma modulator

    Energy Technology Data Exchange (ETDEWEB)

    Bulzacchelli, J.F.; Lee, H.-S. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139 (United States); Misewich, J.A.; Ketchen, M.B. [IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598 (United States)

    1999-11-01

    Bandpass delta-sigma modulators digitize narrowband signals with high dynamic range and linearity. The required sampling rate is only a few times higher than the centre frequency of the input. This paper presents a superconducting bandpass delta-sigma modulator for direct analogue-to-digital conversion of RF signals in the GHz range. The input signal is capacitively coupled to one end of a microstrip transmission line, and a single flux quantum balanced comparator quantizes the current flowing out of the other end. Quantization noise is suppressed at the quarter-wave resonance of the transmission line (about 2 GHz in our design). Circuit performance at a 20 GHz sampling rate has been studied with several long JSIM simulations. Full-scale (FS) input sensitivity is 20 mV (rms), and in-band noise is -53 dBFS and -57 dBFS over bandwidths of 39 MHz and 19.5 MHz, respectively. In-band intermodulation distortion is better than -69 dBFS. (author)

  5. Automatisierte VHDL-Code-Generierung eines Delta-Sigma Modulators

    Science.gov (United States)

    Spilka, R.; Ostermann, T.

    2006-09-01

    Im vorliegenden Beitrag wird eine automatische Generierung des VHDL-Codes eines Delta-Sigma Modulators präsentiert. Die Koeffizientenmultiplikation wird hierbei durch Bit-Serielle-Addition durchgeführt. Mit Hilfe zweier neuer Matlab Funktionen wird der Systementwurf durch die bekannte Delta-Sigma Toolbox von R. Schreier erweitert und direkt synthesefähiger VHDL Code erzeugt.

  6. Post-Correction of Analog-to-Digital Converters

    OpenAIRE

    Lundin, Henrik; Skoglund, Mikael; Händel, Peter

    2003-01-01

    A dynamic post-correction method for ADCs is presented. The method utilizes bit-masking, and a tool for analyzing the effects thereof is proposed. This tool is used to calculate optimal bit allocations, in order to minimize the THD of the corrected ADC. An example based on experimental ADC data is presented. Abstract submitted to the “Northern Lights Workshop on Sensors, Signals & Systems”. January 27, 2003.Konferensen blev inställdQC 20111101

  7. Delta- Sigma Modulator with Signal Dependant Feedback Gain

    National Research Council Canada - National Science Library

    K.Diwakar; V.Vinoth Kumar

    2015-01-01

    Higher order Delta-Sigma Modulator (DSM) is basically an unstable system. The approximate conditions for stability cannot be used for the design of a DSM for industrial applications where risk is involved...

  8. A High Performance Delta-Sigma Modulator for Neurosensing

    National Research Council Canada - National Science Library

    Xu, Jian; Zhao, Menglian; Wu, Xiaobo; Islam, Md Kafiul; Yang, Zhi

    2015-01-01

    ... to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power...

  9. An integrated delta-sigma based IIR filter

    Science.gov (United States)

    Au, Dennis Kin-Wah

    Delta-sigma based infinite impulse response (IIR) filters are a recently developed circuit technique for efficiently realizing IIR filters operating directly on oversampled delta-sigma modulated signals. The design and single-chip implementation of a fifth-order delta-sigma based IIR filter are described. The filter coefficients are fully programmable and with the use of a structure that is inherently scaled for dynamic range, good filter performance is maintained over a wide variety of transfer functions. To eliminate multi-bit multiplications, five second-order digital delta-sigma modulators were used and dynamic range improvement was obtained through the use of multi-bit quantizers in these modulators. The filter was implemented as a very large scale integration chip using 1.2 micron complementary metal oxide semiconductor technology, occupying an area of 4,355 by 5,962 square microns. Simulations indicate that the clock range should operate up to 45 MHz.

  10. Automatisierte VHDL-Code-Generierung eines Delta-Sigma Modulators

    Directory of Open Access Journals (Sweden)

    R. Spilka

    2006-01-01

    Full Text Available Im vorliegenden Beitrag wird eine automatische Generierung des VHDL-Codes eines Delta-Sigma Modulators präsentiert. Die Koeffizientenmultiplikation wird hierbei durch Bit-Serielle-Addition durchgeführt. Mit Hilfe zweier neuer Matlab Funktionen wird der Systementwurf durch die bekannte Delta-Sigma Toolbox von R. Schreier erweitert und direkt synthesefähiger VHDL Code erzeugt.

  11. Doubling-resolution analog-to-digital conversion based on PIC18F45K80

    Directory of Open Access Journals (Sweden)

    Yueyang Yuan

    2014-08-01

    Full Text Available Aiming at the analog signal being converted into the digital with a higher precision, a method to improve the analog-to-digital converter (ADC resolution is proposed and described. Based on the microcomputer PIC18F45K80 in which the internal ADC modules are embedded, a circuit is designed for doubling the resolution of ADC. According to the circuit diagram, the mathematical formula for calculating this resolution is derived. The corresponding software and print circuit board assembly is also prepared. With the experiment, a 13 bit ADC is achieved based on the 12 bit ADC module predesigned in the PIC18F45K80.

  12. Photonic Analog-to-Digital Conversion of Time-Continuous Signals using a TDM Switching-Wavelength Sampling Source

    Institute of Scientific and Technical Information of China (English)

    K. L. Lee; M. P. Fok; C. Shu

    2003-01-01

    A 20 Gsample/s photonic analog-to-digital converter is constructed using a 4-switching-wavelength repetitive sampling pulse source. The signal-to-noise and distortion ratio (SINAD) is measured to be 44.5 dB and corresponds to 7 effective number of bits.

  13. Sliding mode control the delta-sigma modulation approach

    CERN Document Server

    Sira-Ramírez, Hebertt

    2015-01-01

    This monograph presents a novel method of sliding mode control for switch-regulated nonlinear systems. The Delta Sigma modulation approach allows one to implement a continuous control scheme using one or multiple, independent switches, thus effectively merging the available linear and nonlinear controller design techniques with sliding mode control.   Sliding Mode Control: The Delta-Sigma Modulation Approach, combines rigorous mathematical derivation of the unique features of Sliding Mode Control and Delta-Sigma modulation with numerous illustrative examples from diverse areas of engineering. In addition, engineering case studies demonstrate the applicability of the technique and the ease with which one can implement the exposed results. This book will appeal to researchers in control engineering and can be used as graduate-level textbook for a first course on sliding mode control.

  14. An analysis of nonlinear behavior in delta-sigma modulators

    Science.gov (United States)

    Ardalan, Sasan H.; Paulos, John J.

    1987-06-01

    The paper introduces a new method of analysis for delta-sigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

  15. All optical asynchronous binary delta-sigma modulator

    Science.gov (United States)

    Tafazoli, M.; Davoudzadeh, N.; Sayeh, M. R.

    2013-03-01

    We present the first all optical delta-sigma modulator using a bistable device and a leaky integrator. In this paper, a novel tri-coupled ring geometry is utilized, resulting in resonance which is a building block for delta-sigma modulator. In each ring, the main active element is a semiconductor optical amplifier (SOA). The experimental result of the implemented setup is in a good agreement with our presented theory. Applying optical discrete components leads to a sampling rate of 660 kS/s. The higher frequency can be reached easily by using faster bistable devices and shorter loops.

  16. 低电源电压超低功耗Delta-Sigma调制器%Low voltage ultra-low power delta-sigma modulator

    Institute of Scientific and Technical Information of China (English)

    赵津晨; 赵梦恋; 吴晓波

    2013-01-01

    为了在低电源电压约束下实现delta-sigma模数转换器(ADC)的低功耗与高精度设计,提出基于开关型运放以及新颖DWA技术的delta-sigma调制器.其中的开关型运放仅工作于半周期相位,可以在低于1V的电源电压下正常工作,节省了系统功耗.调制器的积分器采用运放分享技术,以降低硬件开销.采用双向循环移位数据加权平均(DCS-DWA)技术,在抑制调制回路中匹配单元误差引起的非线性失真的同时消除了与输入信号相关的寄生音调,提高系统分辨率.提出的delta-sigma调制器在SMIC 0.18 μm 1P6M工艺下流片,动态范围与峰值SNDR分别达94.6和92.5 dB,芯片面积为0.72 mm2.在0.9V电源电压下,测得系统功耗仅为56 μW,品质因数(FoM)低至34.2 fJ/c-step.结果表明,预期的主要设计目标均已实现.%A switched-opamp (SO) based delta-sigma modulator with novel data weighted averaging (DWA) technique was presented in order to achieve a high resolution low power consumption delta-sigma analog-to-digital converter (ADC) under the constraint of low supply voltage.The proposed SO structure operated only during a half clock phase under a sub-1 V supply voltage,which effectively reduced the power consumption of the system.The opamp-shared technique was applied to save the hardware overhead.Due to the use of dual cycle shift data weighted averaging (DCS-DWA) technique,the nonlinear distortion caused by units mismatch in the feedback loop of the modulator was removed without introducing signaldependent tones,so that the resolution of the system could be improved.The proposed delta-sigma modulator was implemented in a SMIC 0.18 μm 1P6M process.The measured dynamic range and peak signal to noise and distortion ratio (SNDR) were 94.6 dB and 92.5 dB,respectively,and the core area of the modulator was 0.72 mm2.The total power consumption was 56μW when a 0.9 V supply voltage was provided,and the figure-of-merit (FoM) was only 34.2 f

  17. High Speed and Wide Bandwidth Delta-Sigma ADCs

    NARCIS (Netherlands)

    Bolatkale, M.

    2013-01-01

    This thesis describes the theory, design and implementation of a high-speed, high-performance continuous-time delta-sigma (CTΔΣ) ADC for applications such as medical imaging, high-definition video processing, and wireline and wireless communications. In order to achieve a GHz clocking speed, this

  18. Multiplexed noise shaping structures for Delta-Sigma modulators

    Science.gov (United States)

    Czarnul, Z.; Yesilyurt, A. G.; Temes, G. C.

    1991-12-01

    A new structure for realizing a multiplexed noise-shaping A/D convertor is proposed. It improves the performance of first- or second-order Delta-Sigma modulators by employing additional feedback paths for suppressing the quantizer error. The structure, its theoretical analysis, and simulations confirming the improved resolution are presented.

  19. High Speed and Wide Bandwidth Delta-Sigma ADCs

    NARCIS (Netherlands)

    Bolatkale, M.

    2013-01-01

    This thesis describes the theory, design and implementation of a high-speed, high-performance continuous-time delta-sigma (CTΔΣ) ADC for applications such as medical imaging, high-definition video processing, and wireline and wireless communications. In order to achieve a GHz clocking speed, this th

  20. 用于CMOS低中频GPS接收机的模数转换器的设计考虑与实现%Design Considerations and Implementation of an Analog-to-Digital Converter for a CMOS Low-IF GPS Receiver

    Institute of Scientific and Technical Information of China (English)

    莫太山; 叶甜春; 马成炎

    2008-01-01

    首先对用于CMOS低中频GPS接收机的模数转换器(ADC)进行了设计考虑.由ADC引入的信噪比降低与四个因素有关:中频带宽,采样率,ADC的比特数及ADC的最大阈值与噪声均方根比值.在设计考虑的基础上,采用TSMC 0.25tan CMOS单层多晶硅五层金属工艺实现了一个4 bit 16.368 MHz闪烁型模数转换器,并将重点放在了前置放大器和提出的新的比较器的设计和优化上.在时钟采样率16.368 MHz和输入信号频率4.092 MHz的条件下,转换器测试得到的信噪失真比为24.7 dB,无杂散动态范围为32.1 dB,积分非线性为+0.31/-0.46LSB,差分非线性为+0.66/-0.46LSB,功耗为3.5mW.ADC占用芯片面积0.07 mm2.%The design considerations of an analog-to-digital converter (ADC) for a CMOS Low-IF GPS re- ceiver are described first. Signal-to-noise degradation due to ADC is dependent on four factors: the IF bandwidth, the sampling rate, the number of bits of the ADC, and the ratio of the maximum ADC thresh-old to the root-mean-square noise level. Then based on the design considerations, a 4 bit 16. 368 MHz Flash ADC is implemented using TSMC 0. 25/μm CMOS single-poly five-metal process and the special at-tention is spent on the design and optimization of the preamplifier and proposed new comparator. The con-verter achieves a peak signal-to-noise-and-distortion ratio of 24.7 dB, peak spurious-free dynamic range of 32.1 dB, integral nonlinearity of +0. 31/-0. 46LSB, integral nonlinearity of +0.66/-0.46LSB, and a pow-er of 3.5 mW at 16.368 MHz clock and fin=4. 092 MHz. The converter occupies 0.07 mm2 of chip area.

  1. On linearity of all optical asynchronous binary delta-sigma modulator

    Science.gov (United States)

    Davoudzadeh, N.; Tafazoli, M.; Sayeh, M. R.

    2013-11-01

    Since the role of optical signal processing is rapidly increasing within the communication systems, the opportunity to convert the analog signal to digital pulses directly in the optical domain will result in a systems simplification. Following our previous work, this paper describes a simple highly linear all-optical delta-sigma modulator, using the gain modulation in optically coupled single mode ring lasers. The key building blocks are an optical leaky integrator and a switching device, leading to meet the requirements of high-speed dynamic response, input/averaged-output linearity, and functioning without external clock. Linearity of the modulator and the corresponding parameters are discussed in theory, simulation, and experiment.

  2. From Analog to Digital Medias in Early Childhood Education

    DEFF Research Database (Denmark)

    Brandt, Erika Zimmer

    2015-01-01

    Considerations: A changed media environment reveals a kind of social vacuum. Educators find themselves lacking norms for how to interact in this new reality. This lack of knowhow and experience in this specific area of professionalism creates uncertainty and vulnerability in the informants which require micro......Research aims: The aim of the study is to explore how the encounters between children and their educators alter when the media changes from analog to digital. Relationship to previous research works Tablets and other handheld, electronic devices has become part of everyday life in kindergartens....... Research shows that there are both potential pedagogical difficulties and possibilities connected to using digital media (ex. Thestrup 2015, Tække and Paulsen 2014) Theoretical and conceptual framework: The study is a single case study of an educational experiment (Flyvbjerg 2006). It is carried out...

  3. The Transition from Analog to Digital Mammography: Overall Considerations

    Directory of Open Access Journals (Sweden)

    A. Sardo

    2007-05-01

    plays a very important role. Going to digital-images displayed on softcopy-monitors, with different contrast and image process-ing tools: the confidence in digital environment, at the start, could be reduced. The analog mammographic screen-film system is ca-pable of very high resolution, high contrast image and can provide adequate dynamic range for most breast types at a reasonable dose for patients. Excel-lent and consistent quality must be assured by proper Quality Control measurements of the x-ray unit AEC reproducibility and film processing and by a complete Quality Assurance program application. Major limita-tion of an analog mammography system is repre-sented in difficulty to simultaneously optimize film image in exposure, capture, processing, viewing and archive phases, even if the film is extremely versatile for being, at the same time a capture, display and ar-chive medium. Digital Mammography systems do not differ from the Analog for what concerns the breast examination: patient positioning and breast compression remain the same. The imaging phases of Digital systems -capture, processing, displaying, archive, printing- contrary to those of an Analog system can be sepa-rately optimized by reaching advantages in terms of dose, image quality, productivity and storage. A digi-tal capture may improve the diagnostic content in mammography: thanks to the linear response of the digital detector, to the image processing and contrast enhancement, a better visualization of dense or younger breast is possible, even if the absolute resolu-tion power of digital detectors results is inferior to the analog screen-film systems (7÷8 versus 15LP/mm. Clinical trials (DIMST study on 50.000 asymptomatic women with digital mammography systems showed an equivalent diagnostic accuracy to Analog Mammography, but a better visualization of pathologies on younger and dense breasts. The transition from analog to digital mammography often signifies the realization of a full digital health

  4. Demonstrations of analog-to-digital conversion using a frequency domain stretched processor.

    Science.gov (United States)

    Reibel, Randy Ray; Harrington, Calvin; Dahl, Jason; Ostrander, Charles; Roos, Peter Aaron; Berg, Trenton; Mohan, R Krishna; Neifeld, Mark A; Babbitt, Wm R

    2009-07-06

    The first proof-of-concept demonstrations are presented for a broadband photonic-assisted analog-to-digital converter (ADC) based on spatial spectral holography (SSH). The SSH-ADC acts as a frequency-domain stretch processor converting high bandwidth input signals to low bandwidth output signals, allowing the system to take advantage of high performance, low bandwidth electronic ADCs. Demonstrations with 50 MHz effective bandwidth are shown to highlight basic performance with approximately 5 effective bits of vertical resolution. Signal capture with 1600 MHz effective bandwidth is also shown. Because some SSH materials span over 100 GHz and have large time apertures (approximately 10 micros), this technique holds promise as a candidate for the next generation of ADCs.

  5. Multiple-Description Coding by Dithered Delta-Sigma Quantization

    CERN Document Server

    Ostergaard, Jan

    2007-01-01

    We address the connection between the multiple-description (MD) problem and Delta-Sigma quantization. The inherent redundancy due to oversampling in Delta-Sigma quantization, and the simple linear-additive noise model resulting from dithered lattice quantization, allow us to construct a symmetric MD coding scheme. We show that the use of a noise shaping filter makes it possible to trade off central distortion for side distortion. Asymptotically as the dimension of the lattice vector quantizer and order of the noise shaping filter approach infinity, the entropy rate of the dithered Delta-Sigma quantization scheme approaches the symmetric two-channel MD rate-distortion function for a memoryless Gaussian source and MSE fidelity criterion, at any side-to-central distortion ratio and any resolution. In the optimal scheme, the infinite-order noise shaping filter must be minimum phase and have a piece-wise flat power spectrum with a single jump discontinuity. We further show that the optimal noise-shaping filter of ...

  6. Optical Analog-to-digital Conversion Scheme Based on Tunable Fabry-Perot Resonator

    Institute of Scientific and Technical Information of China (English)

    LI Zheng

    2007-01-01

    Proposed is an interference type of optical analog-to-digital conversion(ADC). The refractive index of Fabry-Perot cavity changes with different voltages. The Fabry-Perot resonator converts electronic intensity into light wavelength through selecting lights of different wavelengthes. The parameters of the scheme are acquired with the transmission matrix of optical element and the time of steady-state light field. The maximum sampling speedes of 4-bit, 6-bit, 7-bit, 8-bit and 9-bit(ADC) are 1.695×1010 count/s, 4.33×109 count/s, 2.38×109 count/s, 1.24×109 count/s and 5.9×108 count/s, respectively.

  7. Practical Design of Delta-Sigma Multiple Description Audio Coding

    DEFF Research Database (Denmark)

    Leegaard, Jack Højholt; Østergaard, Jan; Jensen, Søren Holdt

    2014-01-01

    It was recently shown that delta-sigma quantization (DSQ) can be used for optimal multiple description (MD) coding of Gaussian sources. The DSQ scheme combined oversampling, prediction, and noise-shaping in order to trade off side distortion for central distortion in MD coding. It was shown......, it is possible to obtain good quality audio in the presence of packet losses. Simulations on real audio reveal that, contrary to existing designs, it is straightforward to obtain a large number of trade-off points between side distortion and central distortion, which makes the proposed coder suitable for a wide...

  8. Bandpass Delta Sigma A/D convertor using two-path multibit structure

    Science.gov (United States)

    Zhang, Z. X.; Temes, G. C.; Czarnul, Z.

    1991-10-01

    The concept of an N-path bandpass Delta Sigma A/D convertor is introduced. A multibit sixth-order SC implementation is described. The new scheme appears to be very effective for the realization of the narrowband bandpass delta-sigma modulators needed for communication applications.

  9. Low-voltage switched-current delta-sigma modulator

    Science.gov (United States)

    Tan, Nianxiong; Eriksson, Sven

    1995-05-01

    This paper presents the design of a fully differential switched-current delta-sigma modulator using a single 3.3-V power-supply voltage. At system level, we tailor the modulator structure considering the similarity and difference of switched-capacitor and switched-current realizations. At circuit level, we propose a new switched-current memory cell and integrator with improved common mode feedback, without which low power-supply-voltage operation would not be possible. The whole modulator was implemented in a 0.8- micron double-metal digital CMOS process. It occupies an active area of 0.53 x 0.48 mm(sup 2) and consumes a current of 0.6 mA from a single 3.3-V power supply. The measured dynamic range is over 10 b.

  10. All-optical analog-to-digital conversion using optical interconnection for gray code coding

    Science.gov (United States)

    Nishitani, Takashi; Konishi, Tsuyoshi; Itoh, Kazuyoshi

    2006-09-01

    The gray code based all-optical analog-to-digital conversion (ADC) using optical interconnection is described. Recent tremendous growths of optical communications and digital signal processing have encouraged the demand of high-speed and high-resolution ADC. To pursue a high-speed and high-resolution ADC, optical approaches have attracted much attention recently. ADC generally consists of three procedures: sampling, quantization and coding. Whereas the optical sampling techniques have been proposed and realized, the optical quantization and coding techniques have investigated depending on various applications. For the application to the binary detection of a high-speed digital signal, we previously proposed an all-optical ADC which consists of optical quantization using self-frequency shifting in a fiber and optical coding using optical interconnection for general binary code. In addition, since we can easily prepare optical interconnection patterns corresponding to the various codes, this technique can be used in any coding schemes. In this paper, we demonstrate the gray code based all-optical ADC to verify its scalability. Experimental results show that the 8-levels analog signals can be successfully converted into the bitwise allocated 3-bit gray code.

  11. An Enhanced Dual-Path ΔΣ A/D Converter

    Science.gov (United States)

    Nishida, Yoshio; Hamashita, Koichi; Temes, Gabor C.

    This paper presents an enhanced dual-path delta-sigma analog-to-digital converter. Compared with other architectures, the enhanced architecture increases the noise shaping order without any instability problems and displays analog complexity equivalent to the multi-stage noise shaping architecture. Our delta-sigma converter is based on this new architecture. It employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal. Regarding the circuit implementation, the first-order enhancement of the quantization noise shaping is achieved via the use of a switched capacitor circuit technique. The circuit is incorporated into the active adder in a low-distortion structure. The supporting clock generation circuit that provides additional phases of clocks with the enhancement block is also implemented in the CMOS logic gates. A digital dynamic element matching circuit (i.e., segmented data-weighted-average circuit) is designed to reduce mismatch errors caused by the feedback DAC of modulator. A test chip, fabricated in a 0.18-µm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is -101dB and the 3rd harmonic is -94dB when a -4.5-dB 100-kHz input signal is applied.

  12. Efficient Circuit Configuration for Enhancing Resolution of 8-bit flash Analog to Digital Convertor

    Directory of Open Access Journals (Sweden)

    Gururaj Balikatti

    2012-11-01

    Full Text Available The need constantly exists for converters with higher resolution, faster conversion speeds and lower power dissipation. High speed analog to digital converters (ADCs have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADCs unsuitable for high resolution applications. The focus of this paper is on efficient circuit configuration to enhance resolution of available 8-bit flash ADC, while maintaining number of comparators only 256 for 12 bit conversion. This technique optimizes the number of comparator requirements. In this approach, an 8-bit flash ADC partitions the analog input range into 256 quantization cells, separated by 255 boundary points. An 8-bit binary code 00000000 to 11111111 is assigned to each cell. The Microcontroller decides within which cell the input sample lies and assigns a 12-bit binary center code 000000000000 to 111111111111 according to the cell value. The exact 12-bit digital code is obtained by successive approximation technique. In this paper the focus will be on all-around efficient circuit for enhancing resolution of 8-bit Flash ADC. It is shown that by adopting this configuration, we can obtain 12-bit digital data just using 256 comparators. Therefore this technique is best suitable when high speed combined with high resolution is required. An experimental prototype of proposed 12-bit ADC was implemented using Philips P89V51RD2BN Microcontroller. Use of Microcontroller has greatly reduced the hardware requirement and cost. An ADC result of 12-bit prototype is presented. The results show that the ADC exhibits a maximum DNL of 0.52LSB and a maximum INL of 0.55LSB.

  13. A dynamic focusing technique for delta-sigma-based beamformers.

    Science.gov (United States)

    Li, P C; Huang, J J; Liu, H L; O'Donnell, M

    2000-10-01

    Beamformation using oversampling delta-sigma (deltasigma) modulators has been proposed for diagnostic ultrasound. Such a beamformer can reduce the size, complexity and cost of an imaging system while providing adequate signal-to-quantization noise ratio (SQNR). High quality images can also be generated if dynamic receive delays are applied correctly. Several dynamic focusing techniques were previously proposed. Generally, an additional bit or extra compensation circuit is required to preserve the power and frequency distribution of the signal. Without preserving the power and frequency distribution, the image background noise is increased. In this paper, an alternative technique is presented. The new technique exploits the symmetry of focusing delays relative to the center of a transducer array. By properly synchronizing the delays and selecting the inserted values, no noise is added to the beam sum signal and the image background level is not increased. Using real ultrasound data, it is shown that the proposed technique provides the same imaging performance as the previous approaches with reduced system complexity by using only a single bit to encode the output of the deltasigma modulator.

  14. A High Performance Delta-Sigma Modulator for Neurosensing.

    Science.gov (United States)

    Xu, Jian; Zhao, Menglian; Wu, Xiaobo; Islam, Md Kafiul; Yang, Zhi

    2015-08-07

    Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-µm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 µW, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.

  15. A High Performance Delta-Sigma Modulator for Neurosensing

    Directory of Open Access Journals (Sweden)

    Jian Xu

    2015-08-01

    Full Text Available Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-µm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 µW, which corresponds to a figure-of-merit (FOM of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.

  16. Delta- Sigma Modulator with Signal Dependant Feedback Gain

    Directory of Open Access Journals (Sweden)

    K.Diwakar

    2015-02-01

    Full Text Available Higher order Delta-Sigma Modulator (DSM is basically an unstable system. The approximate conditions for stability cannot be used for the design of a DSM for industrial applications where risk is involved. The conventional second order, single stage, single bit, unity feedback gain, discrete DSM cannot be used for the normalized full range (-1 to +1 of input signal since the DSM becomes unstable when the modulus of the input signal is above 0.55. The stability is also not guaranteed for amplitude of input signal less than 0.55. In this proposal, the conventional second order DSM is modified with input signal dependant feedback path gain. The proposed DSM is suitable for industrial applications where one needs the digital representation of the analog input signal, during each sampling period. This first configuration of proposed DSM can operate for the full range of input signal without causing instability. In order to improve the SNR of first configuration, it is combined with conventional second order DSM and proposed the second configuration of DSM.

  17. Gluing Lidar Signals Detected in Analog-to-Digital and Photon Counting Modes

    Science.gov (United States)

    Feng, Chang-Zhong; Liu, Bing-Yi; Liu, Jin-Tao; Wu, Song-Hua

    2016-06-01

    Lidar is one of the most effective tools for atmospheric remote sensing. For a ground-based lidar system, the backscattered light usually has large dynamic range. Photon-counting mode has the capability to measure weak signal from high altitude, while Analog-to-Digital mode with better linearity is good at measuring strong signal at low altitude. In some lidar systems, atmospheric return signal is measured in both Analog-to-Digital and Photon Counting modes and combined into an entire profile by using a gluing algorithm. A method for gluing atmospheric return signal is developed and tested. For the Photon Counting signal, the saturation characteristics are analyzed to calculate the coefficients for correction. Then the Analog-to-Digital and Photon Counting signals are glued by a weighted average process. Results show the glued signal is reliable at both low and high altitudes.

  18. Segmented correlation measurements on superconducting bandpass delta-sigma modulator with and without input tone

    Energy Technology Data Exchange (ETDEWEB)

    Bulzacchelli, John F [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139 (United States); Lee, Hae-Seung [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139 (United States); Hong, Merit Y [Motorola, Inc., Semiconductor Products Sector, Tempe, AZ 85284 (United States); Misewich, James A [IBM Research Division, T J Watson Research Center, Yorktown Heights, NY 10598 (United States); Ketchen, Mark B [IBM Research Division, T J Watson Research Center, Yorktown Heights, NY 10598 (United States)

    2003-12-01

    Segmented correlation is a useful technique for testing a superconducting analogue-to-digital converter, as it allows the output spectrum to be estimated with fine frequency resolution even when data record lengths are limited by small on-chip acquisition memories. Previously, we presented segmented correlation measurements on a superconducting bandpass delta-sigma modulator sampling at 40.2 GHz under idle channel (no input) conditions. This paper compares the modulator output spectra measured by segmented correlation with and without an input tone. Important practical considerations of calculating segmented correlations are discussed in detail. Resolution enhancement by segmented correlation does reduce the spectral width of the input tone in the desired manner, but the signal power due to the input increases the variance of the spectral estimate near the input frequency, hindering accurate calculation of the in-band noise. This increased variance, which is predicted by theory, must be considered carefully in the application of segmented correlation. Methods for obtaining more accurate estimates of the quantization noise spectrum which are closer to those measured with no input are described.

  19. Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators

    Science.gov (United States)

    Kennedy, Michael Peter

    Digital Delta-Sigma Modulators (DDSMs) are almost univerally used in integrated circuits for wireless communications and digital audio, particularly in fractional-N frequency synthesizers and oversampled digital-to-analog converters (DACs). A DDSM is a nonlinear dynamical system which reduces the wordlength of an oversampled digital signal without significantly degrading the SNR in the signal band. DDSMs can exhibit a number of behaviors that are characteristic of nonlinear dynamical systems such as oscillation, coexisting steady-state solutions, sensitivity to initial conditions, and sensitivity to the input. This paper explains the root cause of deterministic spurious and idle tones in DDSMs—short periodic cycles—and describes strategies to eliminate them. The use of a DDSM simplifies the design of analog circuitry in a mixed-signal system. By reducing the bus width in a prescribed way, a DDSM can also permit more efficient downstream digital signal processing—in terms of power and speed—with negligible degradation in performance.

  20. Segmented correlation measurements on superconducting bandpass delta sigma modulator with and without input tone

    Science.gov (United States)

    Bulzacchelli, John F.; Lee, Hae-Seung; Hong, Merit Y.; Misewich, James A.; Ketchen, Mark B.

    2003-12-01

    Segmented correlation is a useful technique for testing a superconducting analogue-to-digital converter, as it allows the output spectrum to be estimated with fine frequency resolution even when data record lengths are limited by small on-chip acquisition memories. Previously, we presented segmented correlation measurements on a superconducting bandpass delta-sigma modulator sampling at 40.2 GHz under idle channel (no input) conditions. This paper compares the modulator output spectra measured by segmented correlation with and without an input tone. Important practical considerations of calculating segmented correlations are discussed in detail. Resolution enhancement by segmented correlation does reduce the spectral width of the input tone in the desired manner, but the signal power due to the input increases the variance of the spectral estimate near the input frequency, hindering accurate calculation of the in-band noise. This increased variance, which is predicted by theory, must be considered carefully in the application of segmented correlation. Methods for obtaining more accurate estimates of the quantization noise spectrum which are closer to those measured with no input are described.

  1. Design of the 12-bit Delta-Sigma Modulator using SC Technique for Vibration Sensor Output Processing

    Directory of Open Access Journals (Sweden)

    M. Pavlik

    2012-04-01

    Full Text Available The work deals with the design of the 12-bit Delta-Sigma modulator using switched capacitors (SC technique. The modulator serves to vibration sensor output processing. The first part describes the Delta-Sigma modulator parameters definition. Results of the proposed topology ideal model were presented as well. Next, the Delta-Sigma modulator circuitry on the transistor level was done. The ONSemiconductor I2T100 0.7 um CMOS technology was used for design. Then, the Delta-Sigma modulator nonidealities were simulated and implemented into the MATLAB ideal model of the modulator. The model of real Delta-Sigma modulator was derived. Consequently, modulator coefficients were optimized. Finally, the corner analysis of the Delta-Sigma modulator with the optimized coefficients was simulated. The value of SNDR = 82.2 dB (ENOB = 13.4 bits was achieved.

  2. Design of the 12-bit Delta-Sigma Modulator using SC Technique for Vibration Sensor Output Processing

    OpenAIRE

    Pavlik, M; Kledrowetz, V.; J. Haze

    2012-01-01

    The work deals with the design of the 12-bit Delta-Sigma modulator using switched capacitors (SC) technique. The modulator serves to vibration sensor output processing. The first part describes the Delta-Sigma modulator parameters definition. Results of the proposed topology ideal model were presented as well. Next, the Delta-Sigma modulator circuitry on the transistor level was done. The ONSemiconductor I2T100 0.7 um CMOS technology was used for design. Then, the Delta-Sigma modulator nonide...

  3. A 1V low power second-order delta-sigma modulator for biomedical signal application.

    Science.gov (United States)

    Hsu, Chih-Han; Tang, Kea-Tiong

    2013-01-01

    This paper presents the design and implementation of a low-power delta-sigma modulator for biomedical application with a standard 90 nm CMOS technology. The delta-sigma architecture is implemented as 2nd order feedforward architecture. A low quiescent current operational transconductance amplifier (OTA) is utilized to reduce power consumption. This delta-sigma modulator operated in 1V power supply, and achieved 64.87 dB signal to noise distortion ratio (SNDR) at 10 KHz bandwidth with an oversampling ratio (OSR) of 64. The power consumption is 17.14 µW, and the figure-of-merit (FOM) is 0.60 pJ/conv.

  4. Transitioning from analog to digital audio recording in childhood speech sound disorders

    Science.gov (United States)

    Shriberg, Lawrence D.; McSweeny, Jane L.; Anderson, Bruce E.; Campbell, Thomas F.; Chial, Michael R.; Green, Jordan R.; Hauner, Katherina K.; Moore, Christopher A.; Rusiewicz, Heather L.; Wilson, David L.

    2014-01-01

    Few empirical findings or technical guidelines are available on the current transition from analog to digital audio recording in childhood speech sound disorders. Of particular concern in the present context was whether a transition from analog- to digital-based transcription and coding of prosody and voice features might require re-standardizing a reference database for research in childhood speech sound disorders. Two research transcribers with different levels of experience glossed, transcribed, and prosody-voice coded conversational speech samples from eight children with mild to severe speech disorders of unknown origin. The samples were recorded, stored, and played back using representative analog and digital audio systems. Effect sizes calculated for an array of analog versus digital comparisons ranged from negligible to medium, with a trend for participants’ speech competency scores to be slightly lower for samples obtained and transcribed using the digital system. We discuss the implications of these and other findings for research and clinical practise. PMID:16019779

  5. An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

    Directory of Open Access Journals (Sweden)

    A.R.Ashwatha

    2012-05-01

    Full Text Available This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder.This approach explores the use of a systematically incorporated input offset voltage in a differentialamplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.

  6. An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

    Directory of Open Access Journals (Sweden)

    P.RAJESWARI

    2012-04-01

    Full Text Available This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder.This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.

  7. Modeling of quantization noise in linear analog-to-digital converter

    Science.gov (United States)

    Švihlík, Jan; Fliegel, Karel

    2013-09-01

    Quantization noise is present in all the current digital imaging systems, therefore its understanding and modeling is crucial for optimization of image reconstruction techniques. Hence, this paper deals with modeling of the quantization noise. We exploit the undecimated wavelet transform (UWT) for signal representation. We assume that the quantization noise in the spatial domain can be seen as additive, white and uniformly distributed. Hence, the UWT causes the transform of noise distribution due to weighted sum of noise samples and filter coefficients. From the known quantization step we are able to estimate suitable moments of noise uniform probability density function (PDF). These moments then could be directly evaluated in the undecimated wavelet domain using the derived equations. The presented algorithm gives the a priori information about the quantization noise and can be used for the suppression of it.

  8. Performance requirements for analog-to-digital converters in wideband reconfigurable radios

    Science.gov (United States)

    Naughton, David; Baldwin, Gerard; Farrell, Ronan

    2005-06-01

    With the current trend towards software defined radio, several candidate architectures for the analog receiver front-end have been presented. A common proposal for software defined reconfigurable radio is to develop a wideband ADC and utilise this for capturing a large segment of the spectrum. This would enable the subsequent signal processing operations of channel selection and data extraction to be carried out by a digital processor. This would allow the radio to be reconfigured by simply changing the software. In analysis of these systems, powerful neighbouring signals, or blockers, are considered but it has been conveniently assumed that suitable dynamic range will be available at the ADC. This is an acceptable assumption in narrowband systems where automatic gain control and analogue channel select filters can be used, but is not appropriate for a wideband system. In this paper we present an analysis based on bit-error-rates (BER) which shows the effect of blockers in a wideband architecture on the performance of the communication link and on the dynamic range requirements of the ADC.

  9. Pixel-level Analog-To-Digital Converters for Hybrid Pixel Detectors with energy sensitivity

    NARCIS (Netherlands)

    San Segundo Bello, David; Nauta, Bram; Visschers, Jan

    2000-01-01

    Single-photon counting hybrid pixel detectors have shown to be a valid alternative to other types of X-ray imaging devices due to their high sensitivity, low noise, linear behavior and wide dynamic range. One important advantage of these devices is the fact that detector and readout electronics are

  10. Design of analog-to-digital converters for energy sensitive hybrid pixel detectors

    NARCIS (Netherlands)

    San Segundo Bello, David; Nauta, Bram; Visschers, Jan

    2001-01-01

    An important feature of hybrid semiconductor pixel detectors is the fact that detector and readout electronics are manufactured separately, allowing the use of industrial state-of-the-art CMOS processes to manufacture the readout electronics. As the feature size of these processes decreases, faster

  11. Time-stretch analog-to-digital conversion with a photonic crystal fiber

    Institute of Scientific and Technical Information of China (English)

    TENG Yun; YU Chong-xiu; YUAN Jin-hui; CHEN Jing-xuan; JIN Cang; XU Qian

    2011-01-01

    All-optical analog-to-digital conversion (ADC) has been extensively researched to break through the inherently limited operating speed of electronic devices. In this paper, we use the photonic crystal fiber (PCF) for time-stretch (TS) analog-todigital (A/D) conversion system through generating low noise, linear chirp distribution and fiat super-continuum (SC).Based on the radio frequency (RF) analog signal modulated to the linearly chirped super-continuum, the large-dispersion photonic crystal fiber is used for time-domain stretching.

  12. A Novel Analog-to-digital conversion Technique using nonlinear duty-cycle modulation

    Directory of Open Access Journals (Sweden)

    Jean Mbihi

    2012-06-01

    Full Text Available A new type of analog-to-digital conversion technique is presented in this paper. The interfacing hardware is a very simple nonlinear circuit with 1-bit modulated output. As a implication, behind the hardware simplicity retained is hidden a dreadful nonlinear duty-cycle modulation ratio. However, the overall nonlinear behavior embeds a sufficiently wide linear range, for a rigorous digital reconstitution of the analog input signal using a standard linear filter. Simulation and experimental results obtained using a well tested prototyping system, show the feasibility and good quality of the proposed conversion technique.

  13. Design Methodology for a Maximum Sequence Length MASH Digital Delta-Sigma Modulator

    OpenAIRE

    Tao Xu; Marissa Condon

    2009-01-01

    The paper proposes a novel structure for a MASH digital delta-sigma modulator (DDSM) in order to achieve a long sequence length. The expression for the sequence length is derived. The condition to produce the maximum sequence length is also stated. It is proved that the modulator output only depends on the structure of the first-order error feedback modulator (EFM1) which is the first stage of a Multi-stAge noise SHaping (MASH) modulator.

  14. A high-temperature superconducting delta-sigma modulator based on a multilayer technology with bicrystal Josephson junctions

    Energy Technology Data Exchange (ETDEWEB)

    Ruck, B.; Chong, Y.; Dittmann, R.; Engelhardt, A.; Sodtke, E.; Siegel, M. [Institut fur Schicht- und Ionentechnik (ISI), Forschungszentrum Julich GmbH, 52425 Juelich (Germany)

    1999-11-01

    We have designed, fabricated and successfully tested a first-order delta-sigma modulator using a high-temperature superconducting multilayer technology with bicrystal Josephson junctions. The circuit has been fabricated on a SrTiO{sub 3} bicrystal substrate. The YBa{sub 2}Cu{sub 3}O{sub 7}/SrTiO{sub 3}/YBa{sub 2}Cu{sub 3}O{sub 7} trilayer was fabricated by laser deposition. The bottom layer served as a superconducting ground plane. The Josephson junctions were formed at the bicrystal line in the upper layer. The integrator resistance has been made from a Pd/Au thin film. The circuit consists of a dc-SFQ converter, a Josephson transmission line, a comparator, an L/R integrator and an output stage. The correct operation of the modulatorhas been tested using dc measurements. The linearity of the modulator was studied by measuring the harmonic distortions of a 19.5 kHz sine wave input signal. From the recorded spectrum, a minimum resolution of at least 5 bits can be estimated. This accuracy was limited by the noise of the preamplifier. The correct operation of the current feedback loop was demonstrated by cutting the feedback inductance. (author)

  15. A high-temperature superconducting delta-sigma modulator based on a multilayer technology with bicrystal Josephson junctions

    Science.gov (United States)

    Ruck, B.; Chong, Y.; Dittmann, R.; Engelhardt, A.; Sodtke, E.; Siegel, M.

    1999-11-01

    We have designed, fabricated and successfully tested a first-order delta-sigma modulator using a high-temperature superconducting multilayer technology with bicrystal Josephson junctions. The circuit has been fabricated on a SrTiO3 bicrystal substrate. The YBa2Cu3O7/SrTiO3/YBa2Cu3O7 trilayer was fabricated by laser deposition. The bottom layer served as a superconducting groundplane. The Josephson junctions were formed at the bicrystal line in the upper layer. The integrator resistance has been made from a Pd/Au thin film. The circuit consists of a dc-SFQ converter, a Josephson transmission line, a comparator, an L/R integrator and an output stage. The correct operation of the modulator has been tested using dc measurements. The linearity of the modulator was studied by measuring the harmonic distortions of a 19.5 kHz sine wave input signal. From the recorded spectrum, a minimum resolution of at least 5 bits can be estimated. This accuracy was limited by the noise of the preamplifier. The correct operation of the current feedback loop was demonstrated by cutting the feedback inductance.

  16. A 0.9-V switched-opamp-based delta-sigma ADC with dual cycle shift DWA

    Institute of Scientific and Technical Information of China (English)

    Zhao Jinchen; Zhao Menglian; Wu Xiaobo; Wang Hanqing

    2013-01-01

    This paper presents a low-power high-precision switched-opamp (SO)-based delta-sigma (△ ∑) analogto-digital converter (ADC).The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging (DCS-DWA) technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58 μW for the modulator at 0.9 V supply voltage and 96 μW for the decimation filter,which translate to the figure-of-merit (FOM) of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.

  17. Transceiver Design with Low-Precision Analog-to-Digital Conversion : An Information-Theoretic Perspective

    CERN Document Server

    Singh, Jaspreet; Madhow, Upamanyu

    2008-01-01

    Modern communication receiver architectures center around digital signal processing (DSP), with the bulk of the receiver processing being performed on digital signals obtained after analog-to-digital conversion (ADC). In this paper, we explore Shannon-theoretic performance limits when ADC precision is drastically reduced, from typical values of 8-12 bits used in current communication transceivers, to 1-3 bits. The goal is to obtain insight on whether DSP-centric transceiver architectures are feasible as communication bandwidths scale up, recognizing that high-precision ADC at high sampling rates is either unavailable, or too costly or power-hungry. Specifically, we evaluate the communication limits imposed by low-precision ADC for the ideal real discrete-time Additive White Gaussian Noise (AWGN) channel, under an average power constraint on the input. For an ADC with K quantization bins (i.e., a precision of log2 K bits), we show that the Shannon capacity is achievable by a discrete input distribution with at...

  18. A 10 MHz Bandwidth Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Jørgensen, Ivan Harald Holger; Bruun, Erik

    2016-01-01

    A fourth-order 1-bit continuous-time delta-sigma modulator designed in a 65 nm process for portable ultrasound scanners is presented in this paper. The loop filter consists of RCintegrators, with programmable capacitor arrays and resistors, and the quantizer is implemented with a high-speed clocked...... comparator and a pull-down clocked latch. The feedback signal is generated with voltage DACs based on transmission gates. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The modulator has a bandwidth of 10 MHz with an oversampling...

  19. Delta-Sigma Modulated Displacement of a Digital Fluid Power Pump

    DEFF Research Database (Denmark)

    Johansen, Per; Roemer, Daniel Beck; Andersen, Torben Ole

    2015-01-01

    chambers of the pump are operated in full-stroke mode and a pulse density modulation method is used to approximate a desired displacement output. This pulse density modulation is performed with delta-sigma modulation, whereby the chamber activation pattern is determined. The method is implemented......Successful application of digital fluid power displacement pumps rely on proper control of the actively controlled high pressure and low pressure manifold valves. This paper concerns a method, where the valve timing control and the overall displacement modulation are separated. The displacement...

  20. Sensor Signal Processing for Ultrasonic Sensors Using Delta-Sigma Modulated Single-Bit Digital Signal

    Science.gov (United States)

    Hirata, S.; Kurosawa, M. K.; Katagiri, T.

    Ultrasonic distance measurement is based on determining the time of flight of ultrasonic wave. The pulse compression technique that obtains the cross-correlation function between the received signal and the reference signal is used to improve the resolution of distance measurement. The cross-correlation method requires high-cost digital signal processing. This paper presents a cross-correlation method using a delta-sigma modulated single-bit digital signal. Sensor signal processing composed of the cross-correlation between two single-bit signals and a post-moving average filter is proposed and enables reducing the cost of digital signal processing.

  1. A High Dynamic Range and Low Power Consumption Audio Delta-Sigma Modulator with Opamp Sharing Technique among Three Integrators

    Science.gov (United States)

    Kanemoto, Daisuke; Ido, Toru; Taniguchi, Kenji

    A low power and high performance with third order delta-sigma modulator for audio applications, fabricated in a 0.18µm CMOS process, is presented. The modulator utilizes a third order noise shaping with only one opamp by using an opamp sharing technique. The opamp sharing among three integrator stages is achieved through the optimal operation timing, which makes use of the load capacitance differences between the three integrator stages. The designed modulator achieves 101.1dB signal-to-noise ratio (A-weighted) and 101.5dB dynamic range (A-weighted) with 7.5mW power consumption from a 3.3V supply. The die area is 1.27mm2. The fabricated delta-sigma modulator achieves the highest figure-of-merit among published high performance low power audio delta-sigma modulators.

  2. Realization of High-Order Filters for 1-bit Signal Processing Based on Delta-Sigma Modulation

    Science.gov (United States)

    Murahashi, Yoshimitsu; Doki, Shinji; Okuma, Shigeru

    We discuss a realization method of basic 1-bit signal processing based on Delta-Sigma modulation in this paper. Additionally, we show the characteristics of basic 1-bit processor and an effective design method from the view point of SNR. As the application of the 1-bit signal processing, we proposed a realization method of high-order filters based on Delta-Sigma modulation. We applied the effective design method to decide coefficients of a 4th-order butterworth low pass filter. We show that the filter designed by using the proposed method achieves the highest SNR.

  3. A low-noise delta-sigma phase modulator for polar transmitters.

    Science.gov (United States)

    Zhou, Bo

    2014-01-01

    A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18 μ m CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms) and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of -104 dBc/Hz and -120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively.

  4. Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator

    Directory of Open Access Journals (Sweden)

    Awinash Anand

    2013-01-01

    Full Text Available Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.

  5. Low-power switched-capacitor delta-sigma modulator for EEG recording applications

    Energy Technology Data Exchange (ETDEWEB)

    Chen Jin; Zhang Xu; Chen Hongda, E-mail: chenjin@semi.ac.c [State Key Laboratory of Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2010-07-15

    This paper presents a third-order single-loop delta-sigma modulator of a biomedical micro-system for portable electroencephalogram (EEG) monitoring applications. To reduce the power consumption, the loop filter of the proposed modulator is implemented by applying a switched-capacitor structure. The modulator is designed in a 0.35-{mu}m 2P4M standard CMOS process, with an active area of 365 x 290 {mu}m{sup 2}. Experimental results show that this modulator achieves a 68 dB dynamic range with an input sinusoidal signal of 100 Hz signal bandwidth under a 64 over-sampling ratio. The whole circuit consumes 515 {mu}W under a 2.5 V power supply, which is suitable for portable EEG monitoring.

  6. Correlation-based correction of sound velocity inhomogeneities using delta-sigma modulators.

    Science.gov (United States)

    Li, P C; Huang, J J; O'Donnell, M

    2000-10-01

    Delta-sigma (deltasigma) modulator based beamformers have been proposed for high-quality ultrasonic imaging. Due to the high sampling rate and single bit data width, the cost and complexity of the receive beamformer can be significantly reduced. It was shown that with proper dynamic focusing controls, equivalent image quality could be achieved with an adequate signal-to-quantization noise ratio (SQNR). In this paper, deltasigma modulator based beamformers are used for correlation-based phase aberrations correction of sound velocity inhomogeneities in the body. It is shown that the correction can be efficiently implemented at a performance level similar to that of a conventional radio frequency (rf) beamformer. In addition, more than 6 dB contrast improvement is demonstrated. The different dynamic focusing techniques are also investigated in the context of phase aberration correction. It is shown that the single bit dynamic focusing approach does not affect the overall performance of phase aberration correction.

  7. A Low-Noise Delta-Sigma Phase Modulator for Polar Transmitters

    Directory of Open Access Journals (Sweden)

    Bo Zhou

    2014-01-01

    Full Text Available A low-noise phase modulator, using finite-impulse-response (FIR filtering embedded delta-sigma (ΔΣ fractional-N phase-locked loop (PLL, is fabricated in 0.18 μm CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20 mW power dissipation from 1.6 V supply and achieves the root-mean-square (rms and peak phase errors of 4° and 8.5°, respectively. The measured and simulated phase noises of −104 dBc/Hz and −120 dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively.

  8. Compact FPGA-based beamformer using oversampled 1-bit A/D converters.

    Science.gov (United States)

    Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

    2005-05-01

    A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal reconstruction is done using finite impulse reponse (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50% of the available logic resources in a commercially available mid-range FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.

  9. Une nouvelle stratégie de modulation du vecteur d'espace pour un onduleur de tension triphasé: La Modulation Delta Sigma Vectorielle

    Science.gov (United States)

    Vilain, J. P.; Lesbroussart, Ch.

    1995-07-01

    In this paper, the authors propose a new strategy for the command of the three-phase voltage inverter's switches. After a recall of the principle on which the Delta-Sigma modulation single-phase converter works, they emphasize the avantages it provides and they show how this strategy can be extended to the three-phase voltage inverter by a vectorial approach. Compared to usual modulations and space vector modulation techniques that are now frequently to be found, for identical average switching frequency, this process improves the quality of the output voltages applied to the load. The numerical simulation results are presented. Dans cet article, les auteurs proposent une nouvelle stratégie de commande des interrupteurs d'un onduleur de tension triphasé. Après avoir rappelé le principe de la modulation Delta Sigma utilisée pour les convertisseurs monophasés, et souligné les avantages qu'elle apporte, ils montrent comment cette stratégie peut être étendue au cas de l'onduleur de tension triphasé par une approche vectorielle. Par rapport aux modulations classiques et aux techniques de “Modulation du Vecteur d'Espace", que l'on rencontre aujourd'hui fréquemment et pour une fréquence moyenne de commutation identique, ce procédé améliore la “qualité" des tensions de sortie appliquées à la charge. Les résultats de la simulation numérique sont présentés.

  10. Continuous-Time Delta-Sigma Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

    Science.gov (United States)

    Dosho, Shiro

    This paper presents a tutorial overview of Continuous-Time Delta-Sigma Modulators (CTDSM); their operating principles to understand what is important intuitively and architectures to achieve higher conversion efficiency and to operate low supply voltage, design methods against loop stability problem, tuning methods of the bandwidth and so on. A survey of cutting-edge CMOS implementations is described.

  11. Improving performance of mobile fronthaul architecture employing high order delta-sigma modulator with PAM-4 format.

    Science.gov (United States)

    Li, Haibo; Hu, Rong; Yang, Qi; Luo, Ming; He, Zhixue; Jiang, Peng; Liu, Yongpiao; Li, Xiang; Yu, Shaohua

    2017-01-09

    An improved high-order delta-sigma modulator with multi-level quantizer is proposed to enable carrier aggregation of 4G-LTE signals in mobile fronthaul. Different from conventional delta-sigma modulation-based digital mobile fronthaul, a 2-bit quantizer is employed to reduce the quantization noise, which enabling the transmission via PAM-4 based IM-DD channel. Moreover, we employ the 4th-order high-pass filter (HPF) to replace the 1st-order HPF in the conventional delta-sigma modulator, resulting in a much better noise shaping performance. In the experiment, a PAM-4 based mobile fronthaul transmission of 32 aggregated 4G-LTE signals with a CPRI equivalent data rate of 39.32-Gb/s is demonstrated in a single-λ 10-Gb/s IM-DD channel. Significant improvement of 68% is achieved in the average EVM performance compared to the previous delta-sigma modulation-based digital mobile fronthaul.

  12. A Delta-Sigma Modulator Using a Non-uniform Quantizer Adjusted for the Probability Density of Input Signals

    Science.gov (United States)

    Kitayabu, Toru; Hagiwara, Mao; Ishikawa, Hiroyasu; Shirai, Hiroshi

    A novel delta-sigma modulator that employs a non-uniform quantizer whose spacing is adjusted by reference to the statistical properties of the input signal is proposed. The proposed delta-sigma modulator has less quantization noise compared to the one that uses a uniform quantizer with the same number of output values. With respect to the quantizer on its own, Lloyd proposed a non-uniform quantizer that is best for minimizing the average quantization noise power. The applicable condition of the method is that the statistical properties of the input signal, the probability density, are given. However, the procedure cannot be directly applied to the quantizer in the delta-sigma modulator because it jeopardizes the modulator's stability. In this paper, a procedure is proposed that determine the spacing of the quantizer with avoiding instability. Simulation results show that the proposed method reduces quantization noise by up to 3.8dB and 2.8dB with the input signal having a PAPR of 16dB and 12dB, respectively, compared to the one employing a uniform quantizer. Two alternative types of probability density function (PDF) are used in the proposed method for the calculation of the output values. One is the PDF of the input signal to the delta-sigma modulator and the other is an approximated PDF of the input signal to the quantizer inside the delta-sigma modulator. Both approaches are evaluated to find that the latter gives lower quantization noise.

  13. Total ionizing dose effects on a radiation-induced BiMOS analog-to-digital converter

    Institute of Scientific and Technical Information of China (English)

    Wu Xue; Lu Wu; Wang Yiyuan; Xu Jialing; Zhang Leqing; Lu Jian; Yu Xin; Zhang Xingyao; Hu Tianle

    2013-01-01

    The total dose effect of an AD678 with a BiMOS process is studied.We investigate the performance degradation of the device in different bias states and at several dose rates.The results show that an AD678 can endure 3 krad(Si) at low dose rate and 5 krad(Si) at a high dose rate for static bias.The sensitive parameters to the bias states also differ distinctly.We find that the degradation is more serious on static bias.The underlying mechanisms are discussed in detail.

  14. High-Performance Photonic Analog-to-Digital Converter and Low-Noise Mode-Locked Fiber Lasers

    Science.gov (United States)

    2007-11-02

    input signal spanning a time period given by MKT . The sampling times tn, where 0 ≤ n ≤ MK−1, can then be written as: nn nTt ∆+= (1) ∆n is thus... MKT a fa = (5) 22 MKMK a ≤≤− (6) Substitution of (2), (3), (5) into (4) and separation of the overall summation into summations over the...the FFT will be evaluated at frequencies ranging from −1/(2MT) to 1/(2MT) in increments of 1/ MKT . This gives K + 1 total points, but the first and

  15. A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation †

    Science.gov (United States)

    Dei, Michele; Sutula, Stepan; Cisneros, Jose; Pun, Ernesto; Jansen, Richard Jan Engel; Terés, Lluís; Serra-Graells, Francisco

    2017-01-01

    Infrared imaging technology, used both to study deep-space bodies’ radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm2 chip integrated in a standard 0.18-μm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping, analog calibration, nor digital compensation technique. When coupled to a 2048×2048 IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW. PMID:28574466

  16. A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching

    Science.gov (United States)

    Ninh, Hong Phuc; Miyahara, Masaya; Matsuzawa, Akira

    This paper considers a simple type of Dynamic Element Matching (DEM), Clocked Averaging (CLA) method referred to as one-element-shifting (OES) and its effectiveness for the implementation of high spurious-free dynamic range (SFDR) multi-bit Delta-Sigma modulators (DSMs). Generic DEM techniques are successful at suppressing the mismatch error and increasing the SFDR of data converters. However, they will induce additional glitch energy in most cases. Some recent DEM methods achieve improvements in minimizing glitch energy but sacrificing their effects in harmonic suppression due to mismatches. OES technique discussed in this paper can suppress the effect of glitch while preserving the reduction of element mismatch effects. Hence, this approach achieves better SFDR performance over the other published DEM methods. With this OES, a 3rd order, 10MHz bandwidth continuous-time DSM is implemented in 90nm CMOS process. The measured SFDR attains 83dB for a 10MHz bandwidth. The measurement result also shows that OES improves the SFDR by higher than 10dB.

  17. A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation.

    Science.gov (United States)

    Dei, Michele; Sutula, Stepan; Cisneros, Jose; Pun, Ernesto; Jansen, Richard Jan Engel; Terés, Lluís; Serra-Graells, Francisco

    2017-06-02

    Infrared imaging technology, used both to study deep-space bodies' radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm(2) chip integrated in a standard 0.18-µm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping,analogcalibration,nordigitalcompensationtechnique. Whencoupledtoa2048×2048 IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW.

  18. Digital Filter Design with State Space Method for 1-Bit Signal Processing Based on Delta-Sigma Modulation

    Science.gov (United States)

    Ito, Yuji; Doki, Shinji; Okuma, Sigeru

    1-bit signal processing based on delta-sigma modulation has been studied for hardware implementation of signal processng systems. In the 1-bit signal processing, finite word-length problems such as overflow and coefficent quantization error occur. To solve the problems, new design method with state space is proposed in this paper. Digital filters are designed to show the feasibility of the method. Firstly, L1/L2-sensitivity is shown to evaluate coefficient quantization error and L2 scaling constraints to prevent overflow. Secondly, state space equation is shown and L1/L2-sensitivity and L2-scaling constraints are extended to take filter structure and oversampling effects into account. Finally, the proposed method is shown to attain higher SNR than conventional ones.

  19. An 11 mW 79 dB DR {Delta}{Sigma} modulator for ADSL applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhu Yingjia; Li Dongmei [Department of Electronic Engineering, Tsinghua University, Beijing 100084 (China); Liu Liyuan, E-mail: syj03@mails.tsinghua.edu.c [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2009-10-15

    This paper shows the design of a second-order multi-bit {Delta}{Sigma} modulator with hybrid structure for ADSL applications. A modified two phase non-overlapping clock generator is designed to let PH2 borrow 12% of the time from PH1, which relaxes the speed of OTAs, comparators and the DEM block. The clock feed through problem of the passive adder is solved by revising the timing of the comparators and the adder. The chip is designed and fabricated in UMC 0.18 {mu}m CMOS technology. Measurement results show that with an oversampling ratio of 32 and a clock rate of 80 MHz, the modulator can achieve 79 dB dynamic range, 71.3 dB SNDR, 11 mW power consumption from a 1.8 V power supply. The FOM is 1.47 pJ/step.

  20. A 1.1 mW 87 dB dynamic range {Delta} {sigma} modulator for audio applications

    Energy Technology Data Exchange (ETDEWEB)

    Liu Liyuan; Wang Zhihua; Wei Shaojun [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China); Chen Liangdong; Li Dongmei, E-mail: lidmei@tsinghua.edu.c [Department of Electronic Engineering, Tsinghua University, Beijing 100084 (China)

    2010-05-15

    This paper presents a 1.1 mW 87 dB dynamic range third order {Delta} {sigma} modulator implemented in 0.18 {mu}m CMOS technology for audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed. A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal. (semiconductor integrated circuits)

  1. Review of Josephson Waveform Synthesis and Possibility of New Operation Method by Multibit Delta-Sigma Modulation and Thermometer Code for Its Further Advancement

    Science.gov (United States)

    Kaneko, Nobu-hisa; Maruyama, Michitaka; Urano, Chiharu; Kiryu, Shogo

    2012-01-01

    A method of AC waveform synthesis with quantum-mechanical accuracy has been developed on the basis of the Josephson effect in national metrology institutes, not only for its scientific interest but its potential benefit to industries. In this paper, we review the development of Josephson arbitrary waveform synthesizers based on the two types of Josephson junction array and their distinctive driving methods. We also discuss a new operation technique with multibit delta-sigma modulation and a thermometer code, which possibly enables the generation of glitch-free waveforms with high voltage levels. A Josephson junction array for this method has equally weighted branches that are operated by thermometer-coded bias current sources with multibit delta-sigma conversion.

  2. A measurement of. Delta. sigma. sub L (np), the difference between neutron-proton total cross sections in pure longitudinal spin states

    Energy Technology Data Exchange (ETDEWEB)

    Beddo, M.E.

    1990-10-01

    A measurement off {Delta}{sigma}{sub L}(np), the difference between neutron-proton total cross sections in pure longitudinal spin states, is described. The results will help determine the isospin-zero (I = 0) scattering amplitudes, which are not well known above laboratory energies of 500 MeV, whereas the isospin-one (I = 1) amplitudes are fairly well-determined to 1 GeV. Data points were taken at the Los Alamos Meson Physics Facility (LAMPF) at Los Alamos, New Mexico, for five neutron beam energies: 484, 568, 634,720 and 788 MeV; they are the first in this energy range. Polarized neutrons were produced by charge-exchange of polarized protons on a liquid deuterium target (LD{sub 2}). Large-volume neutron counters detected the neutrons that passed through a polarized proton target. The counters subtended a range of solid angles large enough to allow extrapolation of the scattered neutrons to 0{degree}. Two modifications to the LAMPF accelerator system which were made for this work are described. They included a beam buncher,'' which modified the normal rf-time structure of the proton beam and allowed for the selection of peak-energy neutrons by time-of-flight means, and a computerized beam steering program, which reduced systematic effects due to beam motion at the LD{sub 2} target. The experimental values of {Delta}{sigma}{sub L}(np) are found to be consistent with other np data, including preliminary data from SIN and Saclay, but not with some results from Argonne which used a polarized proton beam and a polarized deuteron target. The I = 0 component was extracted from {Delta}{sigma}{sub L}(np) using existing pp data (I = 1), with the unexpected result that {Delta}{sigma}{sub L}(I = 0) was found to be essentially identical in shape to {Delta}{sigma}{sub L}(I = 1). The significance of this is not yet understood.

  3. A 1 MHz BW 34.2 fJ/step Continuous Time Delta Sigma Modulator With an Integrated Mixer for Cardiac Ultrasound.

    Science.gov (United States)

    Kaald, Rune; Eggen, Trym; Ytterdal, Trond

    2017-02-01

    Fully digitized 2D ultrasound transducer arrays require one ADC per channel with a beamforming architecture consuming low power. We give design considerations for per-channel digitization and beamforming, and present the design and measurements of a continuous time delta-sigma modulator (CTDSM) for cardiac ultrasound applications. By integrating a mixer into the modulator frontend, the phase and frequency of the input signal can be shifted, thereby enabling both improved conversion efficiency and narrowband beamforming. To minimize the power consumption, we propose an optimization methodology using a simulated annealing framework combined with a C++ simulator solving linear electrical networks. The 3rd order single-bit feedback type modulator, implemented in a 65 nm CMOS process, achieves an SNR/SNDR of 67.8/67.4 dB across 1 MHz bandwidth consuming 131 [Formula: see text] of power. The achieved figure of merit of 34.2 fJ/step is comparable with state-of-the-art feedforward type multi-bit designs. We further demonstrate the influence to the dynamic range when performing dynamic receive beamforming on recorded delta-sigma modulated bit-stream sequences.

  4. High Performance Ultra Low-Power ADCs and DACs Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The objective of the Phase-I research is to design a multi-GHz high bandwidth Delta Sigma Analog-to-Digital and Digital-to-Analog converter using a deep sub-micron...

  5. A REVIEW OF HUMAN-SYSTEM INTERFACE DESIGN ISSUES OBSERVED DURING ANALOG-TO-DIGITAL AND DIGITAL-TO-DIGITAL MIGRATIONS IN U.S. NUCLEAR POWER PLANTS

    Energy Technology Data Exchange (ETDEWEB)

    Kovesdi, C.; Joe, J.

    2017-05-01

    The United States (U.S.) Department of Energy (DOE) Light Water Reactor Sustainability (LWRS) program is developing a scientific basis through targeted research and development (R&D) to support the U.S. nuclear power plant (NPP) fleet in extending their existing licensing period and ensuring their long-term reliability, productivity, safety, and security. Over the last several years, human factors engineering (HFE) professionals at the Idaho National Laboratory (INL) have supported the LWRS Advanced Instrumentation, Information, and Control (II&C) System Technologies pathway across several U.S. commercial NPPs in analog-to-digital migrations (i.e., turbine control systems) and digital-to-digital migrations (i.e., Safety Parameter Display System). These efforts have included in-depth human factors evaluation of proposed human-system interface (HSI) design concepts against established U.S. Nuclear Regulatory Commission (NRC) design guidelines from NUREG-0700, Rev 2 to inform subsequent HSI design prior to transitioning into Verification and Validation. This paper discusses some of the overarching design issues observed from these past HFE evaluations. In addition, this work presents some observed challenges such as common tradeoffs utilities are likely to face when introducing new HSI technologies into NPP hybrid control rooms. The primary purpose of this work is to distill these observed design issues into general HSI design guidance that industry can use in early stages of HSI design.

  6. Analysis on multiple-component synchronization of ultra-fast time-interleaved analog-to-digital conversion systems and its novel parameterized hardware solution.

    Science.gov (United States)

    Huang, Wuhuang; Wang, Houjun; Tian, Shulin; Ye, Peng; Zeng, Hao; Qiu, Duyu

    2014-10-01

    Parallelism-based technique of time-interleaved analog-to-digital conversion (TIADC) has become an effective solution for the higher sampling rate acquisition system to acquire non-repetitive waveforms. With the increase of sampling frequency, the indeterminacy of combining sequence of sampled data among multiple components has become a highlighted barrier for the reset operation of high-speed acquisition systems, and this is especially obvious for the ultra-fast TIADC systems. In this paper, we clarify the root of the problem in multiple-component synchronization (MCS) caused by such reset operation. Also we propose a novel and reliable hardware solution to precisely condition each reset signal, including three key circuit design parameters, i.e., the best time interval, required edge uncertainty, and the minimum delay precision. Besides, the designing scheme and debugging procedures are presented in detail in a generalized platform of this system type. Finally, in order to demonstrate the feasibility, parametric materialization and testing verification are gradually accomplished in a 20 Giga Samples Per Second (GSPS) TIADC system composed of four 5 GSPS ADC components. The results show that the proposed method is feasible and effective for ensuring the combined determinacy of multiple groups of sampled data and solving the MCS problem. In comparison with other existing solutions, it adopts some simple logic components more easily and flexibly, and this is significant for the development of congeneric systems or instruments featuring the MCS.

  7. Design of Second-Order Delta-Sigma Modulator for Measurement of Battery Capacity%用于电池电量测量的 Delta-Sigma调制器设计

    Institute of Scientific and Technical Information of China (English)

    2013-01-01

    In order to make the analog - digital converter can be directly used for various battery capacity measurement system without voltage conversion chip ,the modulator in the Delta -Sigma ADC is designed in second-order single-loop structure with 0 .35μm CMOS technology ,and its measurement scope of application range 1 .4 V to 4 .2 V with 12bits resolution at the 5V power supply .The ADC with this modulator has the advantages of wide measurement scope of range to batteries and low cost .%  为使模拟-数字信号转换芯片能直接用于各种电池电量测量的系统中而无需另加电压转换芯片,在应用于Delta-Sigma结构的ADC(模数转换器)的调制器设计中,使用0.35μm CMOS的集成电路工艺,采用二阶单环的电路结构,在5V供电的工作电压下可达到的电压测量范围为1.4V至4.2V ,测量精度为12位.因而采用此Del-ta-Sigma调制器的ADC可直接用于多种电池种类的电量测量,且具有制作成本低廉的特点.

  8. A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver

    Science.gov (United States)

    Obata, Koji; Matsukawa, Kazuo; Mitani, Yosuke; Takayama, Masao; Tokunaga, Yusuke; Sakiyama, Shiro; Dosho, Shiro

    This paper presents a low distortion 3rd-order continuous-time delta-sigma modulator for a worldwide digital TV-receiver whose peak SNDR is 69.8dB and SNR is 70.2dB under 1V power supply. To enhance SNDR performance, the mechanisms to occur harmonic distortions at feedback current-steering DAC and flash ADC have been analyzed. A low power tuning system using RC-relaxation oscillator has been developed in order to achieve high yield against PVT variations. A 3rd-order modulator with modified single opamp resonator contributes to cost reduction by realizing a very compact circuit. Reduction schemes of the distortions enabled the modulator to achieve FOM of 0.18pJ/conv-step.

  9. Transverse-spin dependence of the p-p total cross section. delta. sigma/sub T/ from 0. 8 to 2. 5 GeV/c

    Energy Technology Data Exchange (ETDEWEB)

    Madigan, W.P.; Bell, D.A.; Buchanan, J.A.; Calkin, M.M.; Clement, J.M.; Copel, M.; Corcoran, M.D.; Johns, K.A.; Lesikar, J.D.; Miettinen, H.E.; Mutchler, G.S.; Naudet, C.J.; Pepin, G.P.; Phillips, G.C.; Roberts, J.B.; Turpin, S.E.; Hungerford, E.V.; Mayes, B.W.; Hancock, A.D.; Pinsky, L.S.; Sekharan, K.K.; Hollas, C.L.; Riley, P.J.; Allred, J.C.; Bonner, B.E.; Cameron, P.; Linn, S.T.; von Witsch, W.; Furic, M.; Valkovic, V.

    1985-03-01

    The difference ..delta..sigma/sub T/ = sigma(arrow-downup-arrow)-sigma(up-arrowup-arrow) between the proton-proton total cross sections for protons in pure transverse-spin states, was measured at incident momenta 0.8 to 2.5 GeV/c in experiments performed at the Los Alamos Clinton P. Anderson Meson Physics Facility and the Argonne Zero Gradient Synchrotron. In agreement with other data, peaks were observed at center-of-mass energies of 2.14 and 2.43 GeV/c/sup 2/, where /sup 1/D/sub 2/ and /sup 1/G/sub 4/ dibaryon resonances have been proposed.

  10. Analog-digital converters for industrial applications including an introduction to digital-analog converters

    CERN Document Server

    Ohnhäuser, Frank

    2015-01-01

    This book offers students and those new to the topic of analog-to-digital converters (ADCs) a broad introduction, before going into details of the state-of-the-art design techniques for SAR and DS converters, including the latest research topics, which are valuable for IC design engineers as well as users of ADCs in applications. The book then addresses important topics, such as correct connectivity of ADCs in an application, the verification, characterization and testing of ADCs that ensure high-quality end products. Analog-to-digital converters are the central element in any data processing system and regulation loops such as modems or electrical motor drives. They significantly affect the performance and resolution of a system or end product. System development engineers need to be familiar with the performance parameters of the converters and understand the advantages and disadvantages of the various architectures. Integrated circuit development engineers have to overcome the problem of achieving high per...

  11. ⊿Σ変調ADCを利用したモータ駆動用信号処理方式の研究

    OpenAIRE

    小掘, 康功; 小林, 春夫

    2010-01-01

    [Abstract] This paper propose a new control method for the VCM (Voice Coil Motor) of the HDD (Hard Disc Drive) with a Delta Sigma Analog-to-Digital converter and digital Delta Sigma bit converters. In the ADC, the sense voltage of motor current is converted to 2 bits data with 25MHz over-sampling method. This data is added with 16 bits motor controlled digital signal and then it is converted to 2 bits data. After some digital signal processing, the data is down sampled to lower frequency afte...

  12. A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

    NARCIS (Netherlands)

    Nauta, Bram; Venes, Ardie G.W.

    1995-01-01

    A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance ampl

  13. A Methodology to Teach Advanced A/D Converters, Combining Digital Signal Processing and Microelectronics Perspectives

    Science.gov (United States)

    Quintans, C.; Colmenar, A.; Castro, M.; Moure, M. J.; Mandado, E.

    2010-01-01

    ADCs (analog-to-digital converters), especially Pipeline and Sigma-Delta converters, are designed using complex architectures in order to increase their sampling rate and/or resolution. Consequently, the learning of ADC devices also encompasses complex concepts such as multistage synchronization, latency, oversampling, modulation, noise shaping,…

  14. Simplified design of data converters

    CERN Document Server

    Lenk, John

    1997-01-01

    Simplified Design of Data Converters shows how to design and experiment with data converters, both analog-to-digital and digital to analog. The design approach here is the same one used in all of John Lenk's best-selling books on simplified and practical design. Throughout the book, design problems start with guidelines for selecting all components on a trial-value basis, assuming a specific design goal and set of conditions. Then, using the guideline values in experimental circuits, the desired results are produced by varying the experimental component values, if needed.If you are a w

  15. Expediting analog design retargeting by design knowledge re-use and circuit synthesis: a practical example on a Delta-Sigma modulator

    Science.gov (United States)

    Webb, Matthew; Tang, Hua

    2016-08-01

    In the past decade or two, due to constant and rapid technology changes, analog design re-use or design retargeting to newer technologies has been brought to the table in order to expedite the design process and improve time-to-market. If properly conducted, analog design retargeting could significantly cut down design cycle compared to designs starting from the scratch. In this article, we present an empirical and general method for efficient analog design retargeting by design knowledge re-use and circuit synthesis (CS). The method first identifies circuit blocks that compose the source system and extracts the performance parameter specifications of each circuit block. Then, for each circuit block, it scales the values of design variables (DV) from the source design to derive an initial design in the target technology. Depending on the performance of this initial target design, a design space is defined for synthesis. Subsequently, each circuit block is automatically synthesised using state-of-art analog synthesis tools based on a combination of global and local optimisation techniques to achieve comparable performance specifications to those extracted from the source system. Finally, the overall system is composed of those synthesised circuit blocks in the target technology. We illustrate the method using a practical example of a complex Delta-Sigma modulator (DSM) circuit.

  16. Realization of ICA for Pulsed Neural Networks Based on Delta-Sigma Modulation and Their Hardware Implementation

    Science.gov (United States)

    Hotta, Hirohisa; Murahashi, Yoshimitsu; Doki, Shinji; Okuma, Shigeru

    In order to ride on the strength of paralell operation a feature of neural network, it is preferable that all neuron is implemented on hardware. Formerly, we combine Neural Network and ΔΣ modulation, which is a method of converting to 1bit pulsed signal. Then we succeeded to configurate “a Pulsed Neural Network based on ΔΣ modulation(DSM-PNN)", which keep the circuit scale as same as to operate precisely. In last paper, we proposed hardware implementation methods of DSM-PNN with GHA learning rule and show its availability in linear operation. However, since neural networks are characterized by nonlinear map, signals needs to be treated with sufficient precision, also in nonlinear operation. In this paper, in order to shows that the 1-bit signal processing by DSM-PNN can be available, even when it includes nonlinear operation, we proposed the technique of realizing algorithm of ICA including nonlinear operation in DSM-PNN and confirm the performance of it.

  17. Data Converter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

    2004-01-01

    This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...... Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures...

  18. Delta-Sigma调制器在空间指向镜位置伺服系统中的应用%Application of Delta-Sigma Modulator in Space Pointer Mirror Position Servo System

    Institute of Scientific and Technical Information of China (English)

    王淳; 谢妮慧; 林喆

    2014-01-01

    在目前的空间指向镜位置伺服系统中,数字控制器输出脉宽调制(PWM)的量化误差会导致指向出现小幅角度振荡,使得指向的稳定性降低,进而导致光学遥感成像质量发生退化。针对航天器工程实现的特点,将 Delta-Sigma 调制器引入到数控软件中,在不改变硬件电路与系统参数的前提下,显著的降低了输出量化误差对伺服系统的影响。Matlab仿真结果表明,该方法可使指向镜的指向角度振荡幅值衰减至原来的1/5以下,有效地提高了指向镜的指向稳定性。%The quantization error of DPWM causes slight angle oscillation and stability decrease in pointer mirror position servo system, which results in degradation of optical imaging quality in space remote sensor. On the premise of changing no circuit and system parameters, Delta-Sigma modulator is applied to the software of products in this paper, which significantly lessens the impact of DPWM quantization error on the servo system. A Matlab simulation of pointer mirror position servo system is presented, with the result of more than 5 times attenuation of the amplitude of the angle oscillation by using Delta-Sigma modulator.

  19. An Auto ranging Data Converter Implementation in FPGA

    Directory of Open Access Journals (Sweden)

    Jithin Krishnan

    2013-06-01

    Full Text Available A novel project is being presented here for implementation an auto ranging analog to digital converter for biomedical applications completely inside an FPGA - i.e. an all-digital analog to digital (A/D converter system. The only analog part is the auto ranging circuitry and an RC Integrator outside FPGA. The system outputs 24 bits and features a sigma delta ADC of 16 bits resolution, a range detection unit with 7 bits and a sign bit for polarity detection. The analog part of the modulator is done utilizing the LVDS transceiver in the FPGA making it a real digital one. The digital section of sigma delta ADC containing the decimation filter banks is done in a cascaded filter structure form including a CIC decimation filter, droop compensation and half-band filters. The top level module was coded using VHDL and the simulation was carried out with ModelSim and MATLAB.

  20. A Delta-Sigma Modulator with Non-Delay Integrator for Capacitance Detection%基于非延时积分器Delta-Sigma调制的电容传感器探测电路

    Institute of Scientific and Technical Information of China (English)

    严博; 曾韡; 高峰

    2009-01-01

    研究一种基于非延时积分器Delta-Sigma调制的差分电容探测接口电路,该电路的Delta-Sigma调制使用非延时积分器将采样与积分同时进行,减小普通Delta-Sigma调制型电容探测电路中积分保持阶段的电荷泄露效应,仿真结果表明该结构可明显提高探测较小电容的信噪比,增加了调制器可探测电容的动态范围.%This paper introduces a Delta-Sigma modulator with non-delay integrator for capacitance detection, which reduces the leak charge by integrating and sampling simultaneously instead of taking them separately in most occasions. This structure can greatly improve the performance of Delta-Sigma modulator u-sing in small capacitance detection. The end of this paper shows the simulation results of a 2nd order modulation which achieve a great increase ability in detecting SNR(Signal to Noise Ratio) for ultra small capacitance and a larger dynamic range in application.

  1. 如何为高性能模数变换器设计变压器耦合型前端%Designing Transformer Coupled Front-Ends for High Performance Analog to Digital Converters

    Institute of Scientific and Technical Information of China (English)

    Rob Reeder; Salina Downing

    2007-01-01

    采用高输入频率(IF)的高速模拟-数字变换器(ADC)的系统,其设计一直被证明是一项具有挑战性的任务。而变压器的采用则使得这一任务变得更为困难,因为变压器存在固有的非线性,这些非线性特性会造成性能难以达到标准。本文就高速分级比较(subranging)ADC采用变压器耦合前端设计时应该注意的问题进行了分类说明。

  2. The HHT Method for Testing the Effective Numbers of Bits of High-Resolution Analog to Digital Converter%测试高分辨率ADC有效位数的HHT方法

    Institute of Scientific and Technical Information of China (English)

    王慧; 刘正士; 汪家慰; 王勇

    2009-01-01

    提出一种新颖的正弦拟合法,它基于希尔伯特.黄变换(HHT)以及遍历法,从A/D转换器(ADC)输出数据中求出拟合正弦曲线的各个波形参数.和传统3参数和4参数正弦拟合法不同,它省去了严格选取参数初值的步骤,避免了求解非线性方程组.利用该方法,在信号源分辨率仅有7位以及含有谐波失真和噪声失真的情况下,实现了对14位ADC有效位数(ENOBs)的精确评价.

  3. 高速模数转换器与TMS320C6000 DSP接口的FIFO实现%The Implementation of FIFO to Interface High-speed Analog-to-digital Converters with TI TMS320C6000

    Institute of Scientific and Technical Information of China (English)

    杨恒; 王召巴

    2006-01-01

    大多数的高速模数转换器不能够直接和DSP相连.一个比较好的解决办法是使用FIFO作为输入缓冲.FIFO可以通过C6000系列的外部存储器接口(EMIF)与TMS320C6000系列DSP相连,DSP通过脉冲触发模式从FIFO中读取数据块.介绍如何使用SN74ALVC7806 FIFO实现TMS320C6201与模数转换器的接口.

  4. Analysis of Test Result of Analog-to-Digital Converter Based on Overlapping of Output Data%基于输出迭代法的A/D转换器测试数据分析

    Institute of Scientific and Technical Information of China (English)

    朱凯; 叶凡; 陈廷乾; 任俊彦; 许俊

    2007-01-01

    介绍了一种将模拟/数字转换器(ADC)的采样输出按照正弦输入信号的周期进行迭代的数据处理方法,可以评估输入噪声和时钟抖动对动态性能测试结果的影响.同时,通过分析迭代后的信号波形,可以发现高频输入信号在ADC转换过程中存在的畸变、非单调、失码、跳码、失真等现象,而这些现象很难从输出数据中直接观察到.这种分析对ADC的设计具有重要的指导意义.实验结果表明,这种方法是实用有效的.

  5. 模数转换系统无杂散动态范围的测量技巧%Measurement Techniques for Spurious Free Dynamic Range(SFDR) of Analog to Digital Converter (ADC)

    Institute of Scientific and Technical Information of China (English)

    杨莉军; 朱晓峰; 刘书明

    2013-01-01

    SFDR是评估ADC模数转换系统的重要指标,往往决定了数据采集和信号处理系统的整体性能,但在实际工程中很难得到准确的测量结果。其原因有对概念的理解问题、测试条件问题、算法问题以及测试技巧问题。总结了多年工程实践的经验,从多个方面分析了影响SFDR准确测量的因素,提出了解决的办法和技巧。根据提示,基本可以测量出满意的ADC模数转换系统的SFDR指标。%SFDR is an important index in evaluating the ADC module conversion system, often determines the overall performance of the data acquisition and signal processing system , but it is difficult to get accurate measurement results in the practical engineering. The reasons are for the understanding of the concept of the algorithm, test conditions, and test techniques. Summarizing many years experience of en-gineering practice, are analyzed from the aspects of multiple factors influencing SFDR accurate measurement, which puts forward the solution and skill. According to this article, we can basicly measure the satisfactory SFDR indicator of ADC modulus conversion system.

  6. Optical Oversampled Analog-to-Digital Conversion

    Science.gov (United States)

    1992-06-29

    current structure is that both the modulator and photodiode can be constructed from the same GaAs material and can therefore be monolithically integrated ...the modulator, this modulator lends it- self to monolithic integration . If the entire modulator is monolithically integrated in GaAs (same as S-SEED...using a symmetric MQW mod- ulator ........................................... 40 3.7 Structure and configuration of the reflection electroabsorption

  7. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  8. Quantization Effects on Period Doubling Route to Chaos in a ZAD-Controlled Buck Converter

    Directory of Open Access Journals (Sweden)

    John Alexander Taborda

    2012-01-01

    cycles. On the other hand many studies have been devoted to analyze the ZAD-controlled buck power converter, but these past studies did not include hardware considerations. In this paper, analog-to-digital conversion process is explicitly introduced in the modeling stage. As the feedback gain is varied, the dynamic behavior depending on the analog-to-digital converter resolution is numerically analyzed. Particularly, it is observed that including the quantizer in the model carries out several changes in the transitions to chaos, which include interruption of band-merging process by cascades of periodic inclusions, disappearing of band transitions, and multiple coexisting of periodic orbits. Many of these phenomena have not been reported as a consequence of the quantization effects.

  9. Data Converter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

    2004-01-01

    This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...... Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures....... The entire ADC consumes about 5.5 mW and occupies an active area of about 0.36 mm(2). A test circuit has been developed and fabricated and measurements show that both the required programmability and the required performance can be obtained using the proposed configurations....

  10. Charge to digital converter with constant resolution over the dynamic range

    Energy Technology Data Exchange (ETDEWEB)

    Nascetti, A. [Department of Aerospace and Astronautics Engineering, Sapienza University of Rome, via Eudossiana 16, 00184, Rome (Italy)

    2009-12-15

    A novel pixel-level charge to digital converter circuit suitable for multi-channel charge sensitive amplifiers or pixelated readout ICs for hybrid detectors is presented. The proposed circuit features large dynamic range operation with constant relative resolution over the whole dynamic range. These characteristics have been obtained by introducing the fractional charge packet counting concept. In particular, a solution has been proposed to obtain the analog-to-digital conversion with constant number of significant bits.

  11. Restructuring of a flash A/D converter to improve SEU rad tolerance; Amelioration de la tolerance aux SEU d'un convertisseur A/N flash par restructuration

    Energy Technology Data Exchange (ETDEWEB)

    Monnier, T.; Roche, R.M. [Montpellier-2 Univ., Lab. d' Informatique de Robotique et de Microelectronique de Montpellier, CNRS, 34 (France); Corbiere, F. [SUPAERO, 31 - Toulouse (France)

    1999-07-01

    The purpose of this work is to present how structural changes in the conventional Flash Analog to Digital Converter can secure it for a harsh radiation environment. The method consists in a coupling of two complementary techniques: a robust reconfiguration of the logical structure joined to a design hardening of the individual blocks. This approach preserves the ADC performances. (authors)

  12. VLSI Potentiostat Array With Oversampling Gain Modulation for Wide-Range Neurotransmitter Sensing.

    Science.gov (United States)

    Stanacevic, M; Murari, K; Rege, A; Cauwenberghs, G; Thakor, N V

    2007-03-01

    A 16-channel current-measuring very large-scale integration (VLSI) sensor array system for highly sensitive electrochemical detection of electroactive neurotransmiters like dopamine and nitric-oxide is presented. Each channel embeds a current integrating potentiostat within a switched-capacitor first-order single-bit delta-sigma modulator implementing an incremental analog-to-digital converter. The duty-cycle modulation of current feedback in the delta-sigma loop together with variable oversampling ratio provide a programmable digital range selection of the input current spanning over six orders of magnitude from picoamperes to microamperes. The array offers 100-fA input current sensitivity at 3.4-muW power consumption per channel. The operation of the 3 mm times3 mm chip fabricated in 0.5-mum CMOS technology is demonstrated with real-time multichannel acquisition of neurotransmitter concentration.

  13. Capacitive digital-to-analogue converters with least significant bit down in differential successive approximation register ADCs

    Directory of Open Access Journals (Sweden)

    Lei Sun

    2014-01-01

    Full Text Available This Letter proposes a least significant bit-down switching scheme in the capacitive digital-to-analogue converters (CDACs of successive approximation register analog-to-digital converter (ADC. Under the same unit capacitor, the chip area and the switching energy are halved without increasing the complexity of logic circuits. Compared with conventional CDAC, when it is applied to one of the most efficient switching schemes, V(cm-based structure, it achieves 93% less switching energy and 75% less chip area with the same differential non linearity (DNL/integral non linearity (INL performance.

  14. Design of a Parallel Sampling Encoder for Analog to Information (A2I Converters: Theory, Architecture and CMOS Implementation

    Directory of Open Access Journals (Sweden)

    Andreas G. Andreou

    2013-03-01

    Full Text Available We discuss the architecture and design of parallel sampling front ends for analog to information (A2I converters. As a way of example, we detail the design of a custom 0.5 µm CMOS implementation of a mixed signal parallel sampling encoder architecture. The system consists of configurable parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs. The analog front-end modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. An FPGA is employed to generate the chipping sequences and process the digitized samples.

  15. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  16. Design of a 3D-IC multi-resolution digital pixel sensor

    Science.gov (United States)

    Brochard, N.; Nebhen, J.; Dubois, J.; Ginhac, D.

    2016-04-01

    This paper presents a digital pixel sensor (DPS) integrating a sigma-delta analog-to-digital converter (ADC) at pixel level. The digital pixel includes a photodiode, a delta-sigma modulation and a digital decimation filter. It features adaptive dynamic range and multiple resolutions (up to 10-bit) with a high linearity. A specific row decoder and column decoder are also designed to permit to read a specific pixel chosen in the matrix and its neighborhood of 4 x 4. Finally, a complete design with the CMOS 130 nm 3D-IC FaStack Tezzaron technology is also described, revealing a high fill-factor of about 80%.

  17. Adaptive Digital Calibration of Amplifier Finite Gain Effects and C-ratio Matching Errors for MASH Modulators

    Institute of Scientific and Technical Information of China (English)

    Feng Hui(冯晖); Lin Zhenghui

    2004-01-01

    Cascaded sigma-delta (MASH) modulators for higher order oversampled analog-to-digital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This paper studies the effect of analog imperfections in the implementation, such as finite gain of the amplifiers and capacitor ratio mismatch, and presents an adaptive algorithm and implementation architectures for digital correction of such analog imperfections. Behavioral simulations on 1-1-1 oversampled converters demonstrate over 10dB improvements in signal-to-noise and over 20 dB improvements in dynamic range performance.

  18. Inverter-based successive approximation capacitance-to-digital converter

    KAUST Repository

    Omran, Hesham

    2017-03-23

    An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog- to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter- based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.

  19. The design of adaptive sigma-delta A/D converter

    Institute of Scientific and Technical Information of China (English)

    Feng Hui; Lin Zhenghui

    2005-01-01

    The signal to noise vatio (SNR) of conventional sigma delta analog to digital converter (ΣΔADC) reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ΣΔADC to improve SNR with high dynamic range. An adaptive algorithm and its circuit implementation is proposed. Because of the error due to the circuit implementation,an error self-calibration circuit is also designed. Simulation results indicate that SNR can be nearly independent of the signal strength.

  20. A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER

    Directory of Open Access Journals (Sweden)

    Sudakar S. Chauhan

    2011-07-01

    Full Text Available In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented.CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, theswitching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation resultsshow that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supplyvoltage in TSMC 0.35 μm process. Compared with the traditional flash ADC, this proposed method canreduce about 78% in power consumption.

  1. Background Calibration of Time-Interleaved Data Converters

    CERN Document Server

    El-Chammas, Manar

    2012-01-01

    This book describes techniques for time-interleaving a number of analog-to-digital data converters to achieve demanding bandwidth requirements.  Readers will benefit from the presentation of a low-power solution that can be used in actual products, while alleviating the time-varying signal artifacts that typically arise when implementing such a system architecture. Discusses time-interleaved ADC theory in detail; Presents and analyzes a full solution for timing-skew in time-interleaved ADCs; Demonstrates how to optimize the design of a time-interleaved ADC for extremely low-power and very high sample rate.   Presents and analyzes a full solution for timing-skew in time-interleaved ADCs; Demonstrates how to optimize the design of a time-interleaved ADC for extremely low-power and very high sample rate.  

  2. Data Converters Performance at Extreme Temperatures

    Science.gov (United States)

    Rejeshuni, Rarnesham; Kumar, Nikil; Mao, James; Keymeulen, Didier; Zebulum, Ricardo S.; Stoica, Adrian

    2006-01-01

    Space missions often require radiation and extreme-temperature hardened electronics to survive the harsh environments beyond earth's atmosphere. Traditional approaches to preserve electronics incorporate shielding, insulation and redundancy at the expense of power and weight. However, a novel way of bypassing these problems is the concept of evolutionary hardware. A reconfgurable device, consisting of several switches interconnected with analog/digital parts, is controlled by an evolutionary processor (EP). When the EP detects degradation in the circuit it sends signals to reconfgure the switches, thus forming a new circuit with the desired output. This concept has been developed since the mid-90s, but one problem remains - the EP cannot degrade substantially. For this reason, extensive testing at extreme temperatures (-180' to 120(deg)C) has been done on devices found on FPGA boards (taking the role of the EP) such as the Analog to Digital and the Digital to Analog Converter. Analysis of the results has shown that FPGA boards implementing EP with some compensation may be a practical solution to evolving circuits. This paper describes results on the tests of data converters at extreme temperatures.

  3. A low-power 10-bit continuous-time CMOS ΣΔ A/D converter

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Bruun, Erik

    2004-01-01

    This paper presents the design of a third-order low-pass ΣΔ analog-to-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using Gm - C integrators, where the transconductors are implemented using CMOS transistors only. System level as well...... as transistor level design issues for power efficiency is discussed. A prototype ΣΔ ADC intended for weak biological signals restricted to bandwidths below 4 kHz has been manufactured in a standard 0.35 μm CMOS technology. The ADC has a measured resolution of 10 bits and a dynamic range (DR) of 67 d...

  4. Transitioning from analog to digital communications: An information security perspective

    Science.gov (United States)

    Dean, Richard A.

    1990-01-01

    A summary is given of the government's perspective on evolving digital communications as they affect secure voice users and approaches for operating during a transition period to an all digital world. An integrated architecture and a mobile satellite interface are discussed.

  5. Analog to digital workflow improvement: a quantitative study.

    Science.gov (United States)

    Wideman, Catherine; Gallet, Jacqueline

    2006-01-01

    This study tracked a radiology department's conversion from utilization of a Kodak Amber analog system to a Kodak DirectView DR 5100 digital system. Through the use of ProModel Optimization Suite, a workflow simulation software package, significant quantitative information was derived from workflow process data measured before and after the change to a digital system. Once the digital room was fully operational and the radiology staff comfortable with the new system, average patient examination time was reduced from 9.24 to 5.28 min, indicating that a higher patient throughput could be achieved. Compared to the analog system, chest examination time for modality specific activities was reduced by 43%. The percentage of repeat examinations experienced with the digital system also decreased to 8% vs. the level of 9.5% experienced with the analog system. The study indicated that it is possible to quantitatively study clinical workflow and productivity by using commercially available software.

  6. Design Low Power Encoder for Threshold Inverter Quantization Based Flash ADC Converter

    Directory of Open Access Journals (Sweden)

    Mamta Gurjar

    2013-04-01

    Full Text Available Analog-to-Digital converters are the useful component in signal processing and communication system. In the digital signal processing low power and low voltage becomes a considerable component in that are challenging for designing high speed devices and converters. This paper describes the ultra high speed ADC design with a fat tree encoder that became highly suitable and accurate. Speed becomes the important part that enhanced by component of 2 guidelines of fat tree encoder. This paper also describes the implementation of TIQ based comparator that exhibits low power consumption as compared to other comparator based design. A 3 bit ADC has been designed and simulated in CMOS 45 nm technology with input voltage range of 0 V to 0.7 V. The simulated and analysed results shows low power and a high speed performance for optimised ADC

  7. Nyquist AD Converters, Sensor Interfaces, and Robustness Advances in Analog Circuit Design, 2012

    CERN Document Server

    Baschirotto, Andrea; Steyaert, Michiel

    2013-01-01

    This book is based on the presentations during the 21st workshop on Advances in Analog Circuit Design.  Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity.  This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.  Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format; Includes coverage of Nyquist A/D converters, capacitive sensor interfaces, reliability, variability, and connectivity.

  8. 大规模MIMO系统中单精度模数转换器的量化门限设置方案%Adaptive Quantization Threshold Setting Method for Massive MIMO Systems with 1-bit Analog-to-Digital Converter

    Institute of Scientific and Technical Information of China (English)

    严飞; 李国兵; 张国梅; 吕刚明

    2016-01-01

    针对配置单精度模数转换器(ADC)的大规模多输入多输出(MIMO)系统中信道估计误差和上行信号误符号率较高的问题,提出一种基于大规模MIMO信道相关性的自适应ADC量化门限设置方案,并据此给出了相应的信道估计及上行多用户检测方案.首先根据3GPP信道模型建模并生成信道数据,对该数据进行线性分类以获得与发射功率及用户数自适应的量化门限及相应的量化值,以此对上行导频及有用信号进行量化,然后设计基于该自适应量化门限的信道估计及信号检测矩阵,最终检测出上行信号.所提自适应门限设置方法将相关性强的天线进行组合,为同一组合内的多个单精度ADC设置不同的量化门限以提升量化精度.仿真结果表明:与传统固定量化门限的方法相比,所提出的自适应门限设置方法可充分利用信道相关特性,当天线的相关性较强(天线间距小于等于0.5λ)的时候,信道估计的最小均方误差降低到原来的50%左右,同时系统的误符号率提升了5 dB以上.

  9. Implementation Interface of High-Speed Analog-to-Digital Converter and TMS320C6000 DSP with FIFO%用FIFO实现高速模数转换器与TMS320C6000系列DSP的接口

    Institute of Scientific and Technical Information of China (English)

    刘国华; 王宏波

    2005-01-01

    说明了如何使用CY7C4265-10AC FIFO来实现TMS320C6205与AD9042AST模数转换器的接口,详细介绍了TMS320C6205读取FIFO中数据的速度以及如何设置EMIF的CExCTL寄存器的接口时序.

  10. Design, development, and fabrication of a electronic analog microminiaturized electronic analog signal to discrete time interval converter

    Science.gov (United States)

    Schoenfeld, A. D.; Schuegraf, K. K.

    1973-01-01

    The microminiaturization of an electronic analog signal to discrete time interval converter is presented. Discrete components and integrated circuits comprising the converter were assembled on a thin-film ceramic substrate containing nichrome resistors with gold interconnections. The finished assembly is enclosed in a flat package measuring 3.30 by 4.57 centimeters. The module can be used whenever conversion of analog to digital signals is required, in particular for the purpose of regulation by means of pulse modulation. In conjunction with a precision voltage reference, the module was applied to control the duty cycle of a switching regulator within a temperature range of -55 C to +125 C, and an input voltage range of 10V to 35V. The output-voltage variation was less than + or - 300 parts per million, i.e., less than + or - 3mV for a 10V output.

  11. A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER

    Directory of Open Access Journals (Sweden)

    Sudakar S. Chauhan

    2011-06-01

    Full Text Available In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 μm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.

  12. A 16-bit cascaded sigma-delta pipeline A/D converter

    Institute of Scientific and Technical Information of China (English)

    Li Liang; Li Ruzhang; Yu Zhou; Zhang Jiabin; Zhang Jun'an

    2009-01-01

    A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low oversampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate, The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.

  13. Toward systematic design of multi-standard converters

    Science.gov (United States)

    Rivas, V. J.; Castro-López, R.; Morgado, A.; Guerra, O.; Roca, E.; del Río, R.; de la Rosa, J. M.; Fernández, F. V.

    2007-05-01

    In the last few years, we are witnessing the convergence of more and more communication capabilities into a single terminal. A basic component of these communication transceivers is the multi-standard Analog-to-Digital-Converter (ADC). Many systematic, partially automated approaches for the design of ADCs dealing with a single communication standard have been reported. However, most multi-standard converters reported in the literature follow an ad-hoc approach, which do not guarantee either an efficient occupation of silicon area or its power efficiency in the different standards. This paper aims at the core of this problem by formulating a systematic design approach based on the following key elements: (1) Definition of a set of metrics for reconfigurability: impact in area and power consumption, design complexity and performances; (2) Definition of the reconfiguration capabilities of the component blocks at different hierarchical levels, with assessment of the associated metrics; (3) Exploration of candidate architectures by using a combination of simulated annealing and evolutionary algorithms; (4) Improved top-down synthesis with bottom-up generated low-level design information. The systematic design methodology is illustrated via the design of a multi-standard ΣΔ modulator meeting the specifications of three wireless communication standards.

  14. Design and simulation of Low Power Successive Approximation Register for A/D Converters using 0.18um CMOS Technology

    Directory of Open Access Journals (Sweden)

    Kalmeshwar N. Hosur

    2016-04-01

    Full Text Available This Paper presents the design and simulation of low power successive approximation register for the Analog to Digital Converters (ADC using 0.18um CMOS Technology. This acts as digital part of successive approximation ADC. The principle of the Successive Approximation Register (SAR circuit is to determine the value of each bit of the ADC in a sequential manner, depending on the value of the comparator output. If an N bit analog to digital converter is implemented, there are 2N possible conversion output values, which means that the SAR needs at least 2N states and so, as minimum, N FFs. For N bit SAR ADC, the sequence/code register SAR structure requires 2N Flip-Flops and hence power consumption and area occupied is more and Non redundant SAR structure requires N Flip-Flops and a little combinational Logic and hence power consumption is less and area occupied is also less compared to that of Conventional. For 10 bit SAR architecture, the dynamic power consumed by sequence/code register SAR structure is 63.4359uW and non reduandant SAR architecture is 49.2569 uW. The total power reduction using non redundant architecture is 22.35%.

  15. Analog circuit design structured mixed-mode design, multi-bit sigma-delta converters, short range RF circuits

    CERN Document Server

    van Roermund, Arthur

    2007-01-01

    Preface. Part I: Structured Mixed-Mode Design. Introduction. Structured Oscillator Design; C. Verhoeven, A. van Staveren. Systematic Design of High-frequency gm-C Filters; E. Lauwers, G. Gielen. Structured LNA Design; E.H. Nordholt. High-Level Simulation and Modeling Tools for Mixed-Signal Front-ends of Wireless Systems; P. Wambacq, et al. Structured Simulation-Based Analog Design Synthesis; R.A. Rutenbar. Structured Analog layout Design; K. Lampaert. Part II: Multi-Bit Sigma Delta Converters. Introduction. Architecture Considerations for Multi-Bit SigmaDelta ADCs; T. Brooks. Multirate Sigma-Delta Modulators, an Alternative to Multibit; F. Colodro, A. Torralba. Circuit Design Aspects of Multi-Bit Delta-Sigma Converters; Y. Geerts, et al. High-speed Digital to Analog Converter Issues with Applications to Sigma Delta Modulators; K. Doris, et al. Correction-Free Multi-Bit Sigma-Delta Modulators for ADSL; R. del Rio, et al. Sigma Delta Converters in Wireline Communications; A. Wiesbauer, et al. Part III: Short Ra...

  16. Wavelength Converters

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Wolfson, David;

    1999-01-01

    at 2.5 Gbit/s, the regeneration causes a reduction of the required input power to an in-line EDFA of ~6 dB for a power penalty of 1 dB at a bit error rate of 10-9. If two converters are concatenated the power requirement is reduced ~8 dB. Obviously, the power reduction allows for longer spans between....... It is predicted that jitter accumulation can be minimised by using a 9-10 dB ratio between the signal and CW power also assuring a high extinction ratio. Using this guideline simulations show that 20 cross-gain modulation converters can be cascaded at 10 Gbit/s with only ~20 ps of accumulated jitter...... and an extinction ratio of ~10 dB.The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s, where the noise redistribution and improvement of the signal-to-noise ratio clearly is demonstrated by controlling the input power to an EDFA. In a similar experiment...

  17. Focal-plane CMOS wavelet feature extraction for real-time pattern recognition

    Science.gov (United States)

    Olyaei, Ashkan; Genov, Roman

    2005-09-01

    Kernel-based pattern recognition paradigms such as support vector machines (SVM) require computationally intensive feature extraction methods for high-performance real-time object detection in video. The CMOS sensory parallel processor architecture presented here computes delta-sigma (ΔΣ)-modulated Haar wavelet transform on the focal plane in real time. The active pixel array is integrated with a bank of column-parallel first-order incremental oversampling analog-to-digital converters (ADCs). Each ADC performs distributed spatial focal-plane sampling and concurrent weighted average quantization. The architecture is benchmarked in SVM face detection on the MIT CBCL data set. At 90% detection rate, first-level Haar wavelet feature extraction yields a 7.9% reduction in the number of false positives when compared to classification with no feature extraction. The architecture yields 1.4 GMACS simulated computational throughput at SVGA imager resolution at 8-bit output depth.

  18. Multi-Purpose Low Voltage Dual Output DC-DC Converter For 100V Power Bus Telecom Platform

    Science.gov (United States)

    Galiana, D.; Mollard, J. M.

    2011-10-01

    The decreasing supply voltages of digital electronic and high speed ADC (Analog to Digital Converter) and DAC (Digital to Analog Converter) require flexible and high current secondary power distribution system. In the frame of the Inmarsat I-XL program, a 12 kW geomobile SatCom satellite, with 100 V regulated power bus, a multi purpose dual output converter was developed for the payload processor as a building block. After a short introduction on the main performance requirements, the baseline architecture is presented. The main drivers of the architecture are reliability, adjustability, radiation tolerant and single event free, volume and mass. The combination of all these constraints highlights the need of significant breakthrough in various domains. Many research results related to packaging and power electronic topics are brought up. These results directly drive the adopted solution presented in the next step followed by a description of the integration of the defined building block in the Inmarsat I-XL payload IP (Integrated Processor). Finally, the main electrical performances such as output ripple and spikes, load step transient and stability are summarized.

  19. Wavelength converter technology

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov;

    1999-01-01

    Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers....

  20. Wavelength converter technology

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov;

    1999-01-01

    Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on air-optical wavelength converter types based on semiconductor optical amplifiers....

  1. Technologies for converter topologies

    Energy Technology Data Exchange (ETDEWEB)

    Zhou, Yan; Zhang, Haiyu

    2017-02-28

    In some embodiments of the disclosed inverter topologies, an inverter may include a full bridge LLC resonant converter, a first boost converter, and a second boost converter. In such embodiments, the first and second boost converters operate in an interleaved manner. In other disclosed embodiments, the inverter may include a half-bridge inverter circuit, a resonant circuit, a capacitor divider circuit, and a transformer.

  2. Power Converters for Accelerators

    CERN Document Server

    Visintini, R

    2015-01-01

    Particle accelerators use a great variety of power converters for energizing their sub-systems; while the total number of power converters usually depends on the size of the accelerator or combination of accelerators (including the experimental setup), the characteristics of power converters depend on their loads and on the particle physics requirements: this paper aims to provide an overview of the magnet power converters in use in several facilities worldwide.

  3. Wide-Dynamic-Range Analog-to-Digital Conversion for HFDF.

    Science.gov (United States)

    1986-11-01

    spectral density function of frequency f. estimation situation variance of orediction error 1/2 no...frequency 1/(2T) is called the folding frequency. IfI < W G2(f) (l/T)Gl(f), < Wc2f) I[ 0 w < JfI < (1/2T) Note the following spectral density function for...34 1 0 , W < Ifi < 1/(2T) 1/(2T) rI(nt) - J s2 (f) e 12wfnT df. -1/(2T) In other words, the spectral density function for the oversampled random

  4. Conversion of the Defense Communications System from Analog to Digital Form.

    Science.gov (United States)

    1974-06-01

    Digital Services ," Proceedings of the IEEE, LX, No. 11 (November 1972), 1352. I p. 1353. 69Allen R. Worley, "The DATRAN System," Proceedings o t he IEE...August 1973, entire issue. Cox, J. E. "Western Union Digital Services ." Proceedings of the IEEE, LX, No. 11 (November 1972), 1350-57. "Crosstalk." Lenkurt

  5. Evolution of Photonic Time Stretch: From Analog to Digital Conversion to Blood Screening

    CERN Document Server

    Jalali, Bahram; Fard, Ali; Kim, Sang Hyup

    2011-01-01

    We show how the ability to slow down, amplify, and capture fast transient events can produce high-throughput real-time instruments ranging from digitizers to imaging flow cytometers for detection of rare diseased cells in blood.

  6. Design automation techniques for high-resolution current folding and interpolating CMOS A/D converters

    Science.gov (United States)

    Gevaert, D.

    2007-05-01

    The design and testing of a 12-bit Analog-to-Digital (A/D) converter, in current mode, arranged in an 8-bit LSB and a 4- bit MSB architecture together with the integration of specialized test building blocks on chip allows the set up of a design automation technique for current folding and interpolation CMOS A/D converter architectures. The presented design methodology focuses on the automation for CMOS A/D building blocks in a flexible target current folding and interpolating architecture for a downscaling technology and for different quality specifications. The comprehensive understanding of all sources of mismatching in the crucial building blocks and the use of physical based mismatch modeling in the prediction of mismatch errors, more adequate and realistic sizing of all transistors will result in an overall area reduction of the A/D converter. In this design the folding degree is 16, the number of folders is 64 and the interpolation level is 4. The number of folders is reduced by creating intermediate folding signals with a 4-level interpolator based on current division techniques. Current comparators detect the zero-crossing between the differential folder output currents. The outputs of the comparators deliver a cyclic thermometer code. The digital synthesis part for decoding and error correction building blocks is a standardized digital standard cell design. The basic building blocks in the target architecture were designed in 0.35μ CMOS technology; they are suitable for topological reuse and are in an automated way downscaled into a 0.18μ CMOS technology.

  7. Ein 10 bit 10MS/s Low-Power AD-Converter in 0.11mm2

    Science.gov (United States)

    Muthers, D.; Tielert, R.

    2004-05-01

    Ein 10 bit 10MS/s Analog-Digital- Wandler mit niedriger Leistungaufnahme von 8,4mW wurde implementiert. Der geringe Flächenbedarf von 0,11mm2 macht diesen Wandler besonders geeignet f¨ur Multikanalanwendungen. Um die Anforderungen von 10 bit, 10 MS/s möglichst effizient zu erfüllen wurde eine zyklische Wandlerarchitektur gewählt, die in einem 0,18μm-CMOSProzess mit MIM-Kondensatoren implementiert wurde. Der entworfene ADC wurde in 21 parallelen Kanälen auf einem mixed-signal-Chip zusammen mit digitalen Filtern, vier RISC-CPUs und I/O-Schaltungen implementiert. A 10 bit 10MS/s Analog to Digital Converter, consuming a power of 8,4mW, has been implemented. Due to the small area of 0,11mm2 this ADC is highly suited for multichannel implementations. A cyclic converter architecture is best suited for this application, being implemented in a 0,18μm CMOS process with MIM-capacitors. The designed ADC was implemented in an array of 21 channels on a mixed signal chip together with digital filters, four RISC-CPUs and I/O circuitry.

  8. Ein 10 bit 10MS/s Low-Power AD-Converter in 0.11mm2

    Directory of Open Access Journals (Sweden)

    D. Muthers

    2004-01-01

    Full Text Available Ein 10 bit 10MS/s Analog-Digital- Wandler mit niedriger Leistungaufnahme von 8,4mW wurde implementiert. Der geringe Flächenbedarf von 0,11mm2 macht diesen Wandler besonders geeignet f¨ur Multikanalanwendungen. Um die Anforderungen von 10 bit, 10 MS/s möglichst effizient zu erfüllen wurde eine zyklische Wandlerarchitektur gewählt, die in einem 0,18μm-CMOSProzess mit MIM-Kondensatoren implementiert wurde. Der entworfene ADC wurde in 21 parallelen Kanälen auf einem mixed-signal-Chip zusammen mit digitalen Filtern, vier RISC-CPUs und I/O-Schaltungen implementiert. A 10 bit 10MS/s Analog to Digital Converter, consuming a power of 8,4mW, has been implemented. Due to the small area of 0,11mm2 this ADC is highly suited for multichannel implementations. A cyclic converter architecture is best suited for this application, being implemented in a 0,18μm CMOS process with MIM-capacitors. The designed ADC was implemented in an array of 21 channels on a mixed signal chip together with digital filters, four RISC-CPUs and I/O circuitry.

  9. The photoelectric displacement converter

    Science.gov (United States)

    Dragoner, Valeriu V.

    2005-02-01

    In the article are examined questions of constructing photoelectric displacement converter satisfying demands that are stated above. Converter has channels of approximate and precise readings. The approximate reading may be accomplished either by the method of reading from a code mask or by the method of the consecutive calculation of optical scale gaps number. Phase interpolator of mouar strips" gaps is determined as a precise measuring. It is shown mathematical model of converter that allow evaluating errors and operating speed of conversion.

  10. High speed data converters

    CERN Document Server

    Ali, Ahmed MA

    2016-01-01

    This book covers high speed data converters from the perspective of a leading high speed ADC designer and architect, with a strong emphasis on high speed Nyquist A/D converters. For our purposes, the term 'high speed' is defined as sampling rates that are greater than 10 MS/s.

  11. Electrical Power Converter

    NARCIS (Netherlands)

    Ferreira, J.A.

    2014-01-01

    Electrical power converter for converting electrical power of a power source connected or connectable at an input to electrical DC-power at an output, wherein between the input and the output a first circuit of submodules is provided, wherein said first circuit of submodules and the power source for

  12. Cascaded resonant bridge converters

    Science.gov (United States)

    Stuart, Thomas A. (Inventor)

    1989-01-01

    A converter for converting a low voltage direct current power source to a higher voltage, high frequency alternating current output for use in an electrical system where it is desired to use low weight cables and other circuit elements. The converter has a first stage series resonant (Schwarz) converter which converts the direct current power source to an alternating current by means of switching elements that are operated by a variable frequency voltage regulator, a transformer to step up the voltage of the alternating current, and a rectifier bridge to convert the alternating current to a direct current first stage output. The converter further has a second stage series resonant (Schwarz) converter which is connected in series to the first stage converter to receive its direct current output and convert it to a second stage high frequency alternating current output by means of switching elements that are operated by a fixed frequency oscillator. The voltage of the second stage output is controlled at a relatively constant value by controlling the first stage output voltage, which is accomplished by controlling the frequency of the first stage variable frequency voltage controller in response to second stage voltage. Fault tolerance in the event of a load short circuit is provided by making the operation of the first stage variable frequency voltage controller responsive to first and second stage current limiting devices. The second stage output is connected to a rectifier bridge whose output is connected to the input of the second stage to provide good regulation of output voltage wave form at low system loads.

  13. Converting Nonclassicality into Entanglement

    Science.gov (United States)

    Killoran, N.; Steinhoff, F. E. S.; Plenio, M. B.

    2016-02-01

    Quantum mechanics exhibits a wide range of nonclassical features, of which entanglement in multipartite systems takes a central place. In several specific settings, it is well known that nonclassicality (e.g., squeezing, spin squeezing, coherence) can be converted into entanglement. In this work, we present a general framework, based on superposition, for structurally connecting and converting nonclassicality to entanglement. In addition to capturing the previously known results, this framework also allows us to uncover new entanglement convertibility theorems in two broad scenarios, one which is discrete and one which is continuous. In the discrete setting, the classical states can be any finite linearly independent set. For the continuous setting, the pertinent classical states are "symmetric coherent states," connected with symmetric representations of the group S U (K ). These results generalize and link convertibility properties from the resource theory of coherence, spin coherent states, and optical coherent states, while also revealing important connections between local and nonlocal pictures of nonclassicality.

  14. Improving Power Converter Reliability

    DEFF Research Database (Denmark)

    Ghimire, Pramod; de Vega, Angel Ruiz; Beczkowski, Szymon

    2014-01-01

    The real-time junction temperature monitoring of a high-power insulated-gate bipolar transistor (IGBT) module is important to increase the overall reliability of power converters for industrial applications. This article proposes a new method to measure the on-state collector?emitter voltage...... of a high-power IGBT module during converter operation, which may play a vital role in improving the reliability of the power converters. The measured voltage is used to estimate the module average junction temperature of the high and low-voltage side of a half-bridge IGBT separately in every fundamental...... is measured in a wind power converter at a low fundamental frequency. To illustrate more, the test method as well as the performance of the measurement circuit are also presented. This measurement is also useful to indicate failure mechanisms such as bond wire lift-off and solder layer degradation...

  15. Converting Nonclassicality into Entanglement.

    Science.gov (United States)

    Killoran, N; Steinhoff, F E S; Plenio, M B

    2016-02-26

    Quantum mechanics exhibits a wide range of nonclassical features, of which entanglement in multipartite systems takes a central place. In several specific settings, it is well known that nonclassicality (e.g., squeezing, spin squeezing, coherence) can be converted into entanglement. In this work, we present a general framework, based on superposition, for structurally connecting and converting nonclassicality to entanglement. In addition to capturing the previously known results, this framework also allows us to uncover new entanglement convertibility theorems in two broad scenarios, one which is discrete and one which is continuous. In the discrete setting, the classical states can be any finite linearly independent set. For the continuous setting, the pertinent classical states are "symmetric coherent states," connected with symmetric representations of the group SU(K). These results generalize and link convertibility properties from the resource theory of coherence, spin coherent states, and optical coherent states, while also revealing important connections between local and nonlocal pictures of nonclassicality.

  16. Thermionic photovoltaic energy converter

    Science.gov (United States)

    Chubb, D. L. (Inventor)

    1985-01-01

    A thermionic photovoltaic energy conversion device comprises a thermionic diode mounted within a hollow tubular photovoltaic converter. The thermionic diode maintains a cesium discharge for producing excited atoms that emit line radiation in the wavelength region of 850 nm to 890 nm. The photovoltaic converter is a silicon or gallium arsenide photovoltaic cell having bandgap energies in this same wavelength region for optimum cell efficiency.

  17. Pixel-level continuous-time incremental sigma-delta A/D converter for THz sensors

    Science.gov (United States)

    Khatib, Moustafa; Perenzoni, Matteo

    2016-04-01

    A readout channel based on continuous-time incremental sigma-delta analog-to-digital converter for FET-based terahertz (THz) imaging applications was implemented in a 0.15 μm standard CMOS technology. The designed readout circuit is suitable for implementation in pixel arrays due to its compact size and power consumption. The system-level analysis used to define the modulator parameters and to specify its analog building blocks is presented. The loop filter has been realized by using a Gm-C integrator. Circuit linearization techniques have been implemented to improve the linearity of the transconductor cell and reduce the impact of parasitic capacitances. Moreover, chopper stabilization technique is adopted in the loop filter, significantly reducing the low-frequency flicker noise thereby preserving the Noise Equivalent Power (NEP) of the FET detector within the required specifications of minimum detectable signal. The resulting input referred noise voltage is 87.5 nV/√Hz . The incremental ADC achieves 68-dB peak signal-to-noise-and-distortion-ratio (SNDR), equivalent to 11 bits effective resolution over 1 kHz signal bandwidth at 1 MHz sampling frequency. In order to meet the requirements of large sensor arrays, a first order architecture is realized. This leads to lower area occupancy and power consumption. The readout circuit draws 80 μW of power from a supply voltage of 1.8 V. The channel occupies an area of 90 x 273μm2.

  18. Angiotensin-converting enzyme

    DEFF Research Database (Denmark)

    Sørensen, P G; Rømer, F K; Cortes, D

    1984-01-01

    In order to evaluate bleomycin-associated lung damage in humans, lung function parameters and serum levels of the endothelial-bound angiotensin-converting enzyme (ACE) were determined by serial measurements in 11 patients who were treated for testicular cancer. None developed clinical or radiolog......In order to evaluate bleomycin-associated lung damage in humans, lung function parameters and serum levels of the endothelial-bound angiotensin-converting enzyme (ACE) were determined by serial measurements in 11 patients who were treated for testicular cancer. None developed clinical...

  19. Converting the reset

    NARCIS (Netherlands)

    Hoogland, J.K.; Neumann, C.D.D.; Bloch, D.

    2001-01-01

    We give a simple algorithm to incorporate the effects of resets in convertible bond prices, without having to add an extra factor to take into account the value of the reset. Furthermore we show that the effect of a notice period, and additional make-whole features, can be treated in a straightforwa

  20. An Electromagnetic Beam Converter

    DEFF Research Database (Denmark)

    2009-01-01

    The present invention relates to an electromagnetic beam converter and a method for conversion of an input beam of electromagnetic radiation having a bell shaped intensity profile a(x,y) into an output beam having a prescribed target intensity profile l(x',y') based on a further development...

  1. Definition of Power Converters

    CERN Document Server

    Bordry, F

    2015-01-01

    The paper is intended to introduce power conversion principles and to define common terms in the domain. The concept s of sources and switches are defined and classified. From the basic laws of source interconnections, a generic method of power converter synthesis is presented. Some examples illustrate this systematic method. Finally, the commutation cell and soft commuta tion are introduced and discussedd.

  2. Convertible Proxy Signcryption Scheme

    Institute of Scientific and Technical Information of China (English)

    李继国; 李建中; 曹珍富; 张亦辰

    2004-01-01

    In 1996, Mambo et al introduced the concept of proxy signature. However, proxy signature can only provide the delegated authenticity and cannot provide confidentiality. Recently, Gamage et al and Chan and Wei proposed different proxy signcryption schemes respectively, which extended the concept of proxy signature.However, only the specified receiver can decrypt and verify the validity of proxy signcryption in their schemes.To protect the receiver' s benefit in case of a later dispute, Wu and Hsu proposed a convertible authenticated encryption scheme, which carn enable the receiver to convert signature into an ordinary one that can be verified by anyone. Based on Wu and Hsu' s scheme and improved Kim' s scheme, we propose a convertible proxy signcryption scheme. The security of the proposed scheme is based on the intractability of reversing the one-way hash function and solving the discrete logarithm problem. The proposed scheme can satisfy all properties of strong proxy signature and withstand the public key substitution attack and does not use secure channel. In addition, the proposed scheme can be extended to convertible threshold proxy signcryption scheme.

  3. The Convertible Arbitrage Strategy Analyzed

    NARCIS (Netherlands)

    Loncarski, I.; Ter Horst, J.R.; Veld, C.H.

    2006-01-01

    This paper analyzes convertible bond arbitrage on the Canadian market for the period 1998 to 2004.Convertible bond arbitrage is the combination of a long position in convertible bonds and a short position in the underlying stocks. Convertible arbitrage has been one of the most successful strategies

  4. Advanced DC/DC converters

    CERN Document Server

    Luo, Fang Lin

    2003-01-01

    INTRODUCTIONHistorical ReviewMultiple Quadrant ChoppersPump CircuitsDevelopment of DC/DC Conversion TechniqueCategorize Prototypes and DC/DC Converters Family TreeVOLTAGE-LIFT CONVERTERSIntroductionSeven Self-Lift ConvertersPositive Output Luo-ConvertersNegative Output Luo-ConvertersModified Positive Output Luo-Converters Double Output Luo-ConvertersPOSITIVE OUTPUT SUPER-LIFT LUO-CONVERTERS IntroductionMain SeriesAdditional SeriesEnhanced Series Re-Enhanced Series Multiple-Enhanced Series Summary of Positive Output

  5. Microprocessor controlled static converter

    Directory of Open Access Journals (Sweden)

    Stefan Szabo

    2005-10-01

    Full Text Available This paper wants to demonstrate a way of implementing a microcontroller into an DC motor speed control loop. The static power converter is a fully controlled rectifier bridge, using standard SCR's. The bridge's control signals are supplied by the microcontroller and are phase-angle or burst types. The automation loop contains a software PI-style regulator. All the experimental results shows that this aproach is flexibile enough to be used on a large scale.

  6. DSP controlled power converter

    OpenAIRE

    Chan, CH; Pong, MH

    1995-01-01

    A digital controller is designed and implemented by a Digital Signal Processor (DSP) to replace the Pulse Width Modulator (PWM) and error amplifier compensation network in a two wheeler forward converter. The DSP controller is designed in three approaches: a) Discretization of analog controller - the design is based on the transfer function of the error amplifier compensation network. b) Digital PID controller design - the design is based on the general form of the pulse transfer function of ...

  7. SSG Wave Energy Converter

    DEFF Research Database (Denmark)

    Margheritini, Lucia; Vicinanza, Diego; Frigaard, Peter

    2008-01-01

    head hydroturbines are converting the potential energy of the stored water into power. A key to success for the SSG will be the low cost of the structure and its robustness. The construction of the pilot plant is scheduled and this paper aims to describe the concept of the SSG wave energy converter...... and the studies behind the process that leads to its construction. The pilot plant is an on-shore full scale module in 3 levels with an expected power production of 320 MWh/y in the North Sea. Location, wave climate and laboratory tests results will be used here to describe the pilot plant and its characteristics.......The SSG (Sea Slot-cone Generator) is a wave energy converter of the overtopping type. The structure consists of a number of reservoirs one on the top of each others above the mean water level, in which the water of incoming waves is stored temporary. In each reservoir, expressively designed low...

  8. X-Y Converter Family

    DEFF Research Database (Denmark)

    Bhaskar, Mahajan Sagar; Sanjeevikumar, Padmanaban; Wheeler, Patrick

    2016-01-01

    A New breed of a buck boost converter, named as the XY converter family is proposed in this article. In the XY family, 16 topologies are presented which are highly suitable for renewable energy applications which require a high ratio of DC-DC converter; such as a photovoltaic multilevel inverter...... system, high voltage automotive applications and industrial drives. Compared to the traditional boost converter and existing recent converters, the proposed XY converter family has the ability to provide a higher output voltage by using less number of power devices and reactive components. Other distinct...... features of the XY converter family are i) Single control switch ii) Provide negative output voltage iii) Non-isolated topologies iv) High conversion ratio without making the use of high duty cycle and v) modular structure. XY family is compared with the recent high step-up converters and the detailed...

  9. Resonant power converters

    CERN Document Server

    Kazimierczuk, Marian K

    2012-01-01

    This book is devoted to resonant energy conversion in power electronics. It is a practical, systematic guide to the analysis and design of various dc-dc resonant inverters, high-frequency rectifiers, and dc-dc resonant converters that are building blocks of many of today's high-frequency energy processors. Designed to function as both a superior senior-to-graduate level textbook for electrical engineering courses and a valuable professional reference for practicing engineers, it provides students and engineers with a solid grasp of existing high-frequency technology, while acquainting them wit

  10. Cycloidal Wave Energy Converter

    Energy Technology Data Exchange (ETDEWEB)

    Stefan G. Siegel, Ph.D.

    2012-11-30

    This program allowed further advancing the development of a novel type of wave energy converter, a Cycloidal Wave Energy Converter or CycWEC. A CycWEC consists of one or more hydrofoils rotating around a central shaft, and operates fully submerged beneath the water surface. It operates under feedback control sensing the incoming waves, and converts wave power to shaft power directly without any intermediate power take off system. Previous research consisting of numerical simulations and two dimensional small 1:300 scale wave flume experiments had indicated wave cancellation efficiencies beyond 95%. The present work was centered on construction and testing of a 1:10 scale model and conducting two testing campaigns in a three dimensional wave basin. These experiments allowed for the first time for direct measurement of electrical power generated as well as the interaction of the CycWEC in a three dimensional environment. The Atargis team successfully conducted two testing campaigns at the Texas A&M Offshore Technology Research Center and was able to demonstrate electricity generation. In addition, three dimensional wave diffraction results show the ability to achieve wave focusing, thus increasing the amount of wave power that can be extracted beyond what was expected from earlier two dimensional investigations. Numerical results showed wave cancellation efficiencies for irregular waves to be on par with results for regular waves over a wide range of wave lengths. Using the results from previous simulations and experiments a full scale prototype was designed and its performance in a North Atlantic wave climate of average 30kW/m of wave crest was estimated. A full scale WEC with a blade span of 150m will deliver a design power of 5MW at an estimated levelized cost of energy (LCOE) in the range of 10-17 US cents per kWh. Based on the new results achieved in the 1:10 scale experiments these estimates appear conservative and the likely performance at full scale will

  11. System Level Design of a Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Færch, Kjartan; Jørgensen, Ivan Harald Holger

    2015-01-01

    In this paper the system level design of a continuous-time ∆Σ modulator for portable ultrasound scanners is presented. The overall required signal-to-noise ratio (SNR) is derived to be 42 dB and the sampling frequency used is 320 MHz for an oversampling ratio of 16. In order to match these requir......In this paper the system level design of a continuous-time ∆Σ modulator for portable ultrasound scanners is presented. The overall required signal-to-noise ratio (SNR) is derived to be 42 dB and the sampling frequency used is 320 MHz for an oversampling ratio of 16. In order to match...... these requirements, a fourth order, 1-bit modulator with optimal zero placing is used. An analysis shows that the thermal noise from the resistors and operational transconductance amplifier is not a limiting factor due to the low required SNR, leading to an inherently very low-power implementation. Furthermore......, based on high-level VerilogA simulations, the performance of the ∆Σ modulator versus various block performance parameters is presented as trade-off curves. Based on these results, the block specifications are derived....

  12. System Level Design of a Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Færch, Kjartan; Jørgensen, Ivan Harald Holger;

    2015-01-01

    In this paper the system level design of a continuous-time ∆Σ modulator for portable ultrasound scanners is presented. The overall required signal-to-noise ratio (SNR) is derived to be 42 dB and the sampling frequency used is 320 MHz for an oversampling ratio of 16. In order to match these requir......, based on high-level VerilogA simulations, the performance of the ∆Σ modulator versus various block performance parameters is presented as trade-off curves. Based on these results, the block specifications are derived....

  13. Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters

    Science.gov (United States)

    Saponara, Sergio; Nuzzo, Pierluigi; Nani, Claudio; van der Plas, Geert; Fanucci, Luca

    Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15pJ/conversion-step.

  14. Bidirectional buck boost converter

    Science.gov (United States)

    Esser, Albert Andreas Maria

    1998-03-31

    A bidirectional buck boost converter and method of operating the same allows regulation of power flow between first and second voltage sources in which the voltage level at each source is subject to change and power flow is independent of relative voltage levels. In one embodiment, the converter is designed for hard switching while another embodiment implements soft switching of the switching devices. In both embodiments, first and second switching devices are serially coupled between a relatively positive terminal and a relatively negative terminal of a first voltage source with third and fourth switching devices serially coupled between a relatively positive terminal and a relatively negative terminal of a second voltage source. A free-wheeling diode is coupled, respectively, in parallel opposition with respective ones of the switching devices. An inductor is coupled between a junction of the first and second switching devices and a junction of the third and fourth switching devices. Gating pulses supplied by a gating circuit selectively enable operation of the switching devices for transferring power between the voltage sources. In the second embodiment, each switching device is shunted by a capacitor and the switching devices are operated when voltage across the device is substantially zero.

  15. Gallium phosphide energy converters

    Energy Technology Data Exchange (ETDEWEB)

    Sims, P.E.; Dinetta, L.C.; Goetz, M.A.

    1995-10-01

    Gallium phosphide (GaP) energy converters may be successfully deployed to provide new mission capabilities for spacecraft. Betavoltaic power supplies based on the conversion of tritium beta decay to electricity using GaP energy converters can supply long term low-level power with high reliability. High temperature solar cells, also based on GaP, can be used in inward-bound missions greatly reducing the need for thermal dissipation. Results are presented for GaP direct conversion devices powered by Ni-63 and compared to the conversion of light emitted by tritiarated phosphors. Leakage currents as low as 1.2 x 10(exp {minus}17) A/sq cm have been measured and the temperature dependence of the reverse saturation current is found to have ideal behavior. Temperature dependent IV, QE, R(sub sh), and V(sub oc) results are also presented. These data are used to predict the high-temperature solar cell and betacell performance of GaP devices and suggest appropriate applications for the deployment of this technology.

  16. Manufacturing method of photoelectric converter

    Energy Technology Data Exchange (ETDEWEB)

    Yamazaki, Shunpei; Suzuki, Kunio; Fukada, Takeshi; Kanehana, Mikio

    1987-06-25

    This is a photoelectric converter wherein a photoelectromotive force is generated by utilizing the shorter wavelength side by the 1st converter and by utilizing the longer wavelength side by the 2nd converter; as a whole, wider wavelength range of light can be converted into electricity. In the 1st. converter, an electrode on the side of semi-incident surface is made transparent as well as an electrode equipped on the back of a non-mono-crystalline semiconductor. Light which passed this is introduced into the 2nd converter to generate an electromotive force. This invention especially relates with a method of forming this 2nd converter. In preparing I-type non-mono-crystalline semiconductor among the semiconductors having PIN junction, PCVD method is used by means of ECR (Electron Cyclotron Resonance) by using a hydrogen- or halogen- added Si-semiconductor instead of using expensive Ge, etc, which are common in the conventional method. (3 figs)

  17. Unity power factor converter

    Science.gov (United States)

    Wester, Gene W. (Inventor)

    1980-01-01

    A unity power factor converter capable of effecting either inversion (dc-to-dc) or rectification (ac-to-dc), and capable of providing bilateral power control from a DC source (or load) through an AC transmission line to a DC load (or source) for power flow in either direction, is comprised of comparators for comparing the AC current i with an AC signal i.sub.ref (or its phase inversion) derived from the AC ports to generate control signals to operate a switch control circuit for high speed switching to shape the AC current waveform to a sine waveform, and synchronize it in phase and frequency with the AC voltage at the AC ports, by selectively switching the connections to a series inductor as required to increase or decrease the current i.

  18. Electromagnetic wave energy converter

    Science.gov (United States)

    Bailey, R. L. (Inventor)

    1973-01-01

    Electromagnetic wave energy is converted into electric power with an array of mutually insulated electromagnetic wave absorber elements each responsive to an electric field component of the wave as it impinges thereon. Each element includes a portion tapered in the direction of wave propagation to provide a relatively wideband response spectrum. Each element includes an output for deriving a voltage replica of the electric field variations intercepted by it. Adjacent elements are positioned relative to each other so that an electric field subsists between adjacent elements in response to the impinging wave. The electric field results in a voltage difference between adjacent elements that is fed to a rectifier to derive dc output power.

  19. Integrated power electronic converters and digital control

    CERN Document Server

    Emadi, Ali; Nie, Zhong

    2009-01-01

    Non-isolated DC-DC ConvertersBuck ConverterBoost ConverterBuck-Boost ConverterIsolated DC-DC ConvertersFlyback ConverterForward ConverterPush-Pull ConverterFull-Bridge ConverterHalf-Bridge ConverterPower Factor CorrectionConcept of PFCGeneral Classification of PFC CircuitsHigh Switching Frequency Topologies for PFCApplication of PFC in Advanced Motor DrivesIntegrated Switched-Mode Power ConvertersSwitched-Mode Power SuppliesThe Concept of Integrated ConverterDefinition of Integrated Switched-Mode Power Supplies (ISMPS)Boost-Type Integrated TopologiesGeneral Structure of Boost-Type Integrated T

  20. Advanced power electronics converters PWM converters processing AC voltages

    CERN Document Server

    dos Santos, Euzeli

    2014-01-01

    This book covers power electronics, in depth, by presenting the basic principles and application details, which can be used both as a textbook and reference book.  Introduces a new method to present power electronics converters called Power Blocks Geometry. Applicable for courses focusing on power electronics, power electronics converters, and advanced power converters. Offers a comprehensive set of simulation results to help understand the circuits presented throughout the book

  1. Nanostructure Neutron Converter Layer Development

    Science.gov (United States)

    Park, Cheol (Inventor); Sauti, Godfrey (Inventor); Kang, Jin Ho (Inventor); Lowther, Sharon E. (Inventor); Thibeault, Sheila A. (Inventor); Bryant, Robert G. (Inventor)

    2016-01-01

    Methods for making a neutron converter layer are provided. The various embodiment methods enable the formation of a single layer neutron converter material. The single layer neutron converter material formed according to the various embodiments may have a high neutron absorption cross section, tailored resistivity providing a good electric field penetration with submicron particles, and a high secondary electron emission coefficient. In an embodiment method a neutron converter layer may be formed by sequential supercritical fluid metallization of a porous nanostructure aerogel or polyimide film. In another embodiment method a neutron converter layer may be formed by simultaneous supercritical fluid metallization of a porous nanostructure aerogel or polyimide film. In a further embodiment method a neutron converter layer may be formed by in-situ metalized aerogel nanostructure development.

  2. Impedance source power electronic converters

    CERN Document Server

    Liu, Yushan; Ge, Baoming; Blaabjerg, Frede; Ellabban, Omar; Loh, Poh Chiang

    2016-01-01

    Impedance Source Power Electronic Converters brings together state of the art knowledge and cutting edge techniques in various stages of research related to the ever more popular impedance source converters/inverters. Significant research efforts are underway to develop commercially viable and technically feasible, efficient and reliable power converters for renewable energy, electric transportation and for various industrial applications. This book provides a detailed understanding of the concepts, designs, controls, and application demonstrations of the impedance source converters/inverters. Key features: Comprehensive analysis of the impedance source converter/inverter topologies, including typical topologies and derived topologies. Fully explains the design and control techniques of impedance source converters/inverters, including hardware design and control parameter design for corresponding control methods. Presents the latest power conversion solutions that aim to advance the role of pow...

  3. Δ-Σ変調方式による空間光伝送装置の研究開発

    OpenAIRE

    香川, 直己; 粕谷, 俊之; 古南, 卓治; 鈴木, 洋隆; 佐野, 博也; カガワ, ナオキ; カスタニ, トシユキ; コミナミ, タクジ; スズキ, ヒロタカ; サノ, ヒロヤ; Naoki, KAGAWA; Toshiyuki, KASUTANI; Takuji, KOMINAMI; Hirotaka, SUZUKI; Hiroya, SANO

    1994-01-01

    This paper describes development of a free space optical communication system with the delta-sigma modulation scheme. The delta-sigma modulater can convert analog signals into 1 bit digital signals whose SNR against the quantum noise is equal to maltibit AD converters by means of over sampling and noise shaping. Constructed second-order delta-sigma modulator has 256 over sampling ratio that causes the same ability of 18-bit AD converters, and has 16 kHz band width from dc to 16 kHz. The 1 bit...

  4. Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

    Science.gov (United States)

    Ruiz-Amaya, Jesus; de la Rosa, Jose M.; Delgado-Restituto, Manuel; Rodriguez-Vazquez, Angel

    2005-06-01

    This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK platform by using the MATLAB engine library, so that the optimization core runs in background while MATLAB acts as a computation engine. The implementation on the MATLAB platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13μm CMOS 12-bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.

  5. A thermochemical energy converter

    Energy Technology Data Exchange (ETDEWEB)

    Toyeguti, K.; Indzima, T.

    1982-08-09

    Mercury is used as the active mass of the anode in the converter and 0/sub 2/ is used as the active cathode material. The reaction of Mercury + 1/2 0/sub 2/-Hg0 occurs with a discharge. With heating to 500/sup 0/C the regeneration of the Mercury, Hg0 yields Mercury + 1/2 0/sub 2/, occurs. The device for performing the thermochenical conversion of energy contains an element body, an oxygen chamber, an oxygen electrode, a chamber with an alkaline liquid electrolyte, a separator, an auxiliary separator, an electrode and a chamber with the Mercury. The thermochemical reaction occurs in the reactor to which the Hg0 is transported along a pipe which has a refrigerator and a valve. The Mercury is fed into the element from a reservoir. The Mercury reduced in the reactor and in a reaction tower is fed into it through a closed cycle. The bellows is connected with the reactor by a pipe with a refrigerator. Through it the 0/sub 2/ goes in a closed cycle to the chamber. The current forming reactions are Hg + 20H-anion yields Hg0 + H/sub 2/0 + 2e and 1/2 0/sub 2/ + H/sub 2/0 + 2e yields 20H-anion. The voltage on the outleads of the element is approximately 0.3 volts.

  6. DC to DC converters: operation; Hacheurs: fonctionnement

    Energy Technology Data Exchange (ETDEWEB)

    Bernot, F. [Ecole d' Ingenieurs de Tours, 37 (France)

    2002-05-01

    This article deals with pulse width modulation (PWM) and pulse position modulation (PPM) DC to DC converters. A tri-phase PWM converter is made of 6 simple DC/DC converters grouped together into 3 reversible converters of the same type: 1 - single-quadrant voltage lowering converters (hydraulic analogy, study with ideal elements, full scheme with input and output filters); 2 - single-quadrant voltage raising converters (hydraulic analogy, operation); 3 - two quadrants reversible converters (structure construction, quadrants of operation, reversible converter connected to a DC motor); 4 - four-quadrants reversible converters; 5 - other converters structure (current converters and converters with intermediate storage, asymmetrical converters, converters with capacitive storage, insulated converters, resonating converters, status); 6 - conclusion. (J.S.)

  7. Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

    Science.gov (United States)

    Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

    2004-06-01

    Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

  8. Mixed-Signal Hardware Security: Attacks and Countermeasures for ΔΣ ADC

    Directory of Open Access Journals (Sweden)

    Shayan Taheri

    2017-08-01

    Full Text Available Mixed-signal integrated circuits (ICs play an eminent and critical role in design and development of the embedded systems leveraged within smart weapons and military systems. These ICs can be a golden target for adversaries to compromise in order to function maliciously. In this work, we study the security aspects of a tunnel field effect transistor (TFET-based first-order one-bit delta-sigma ( Δ Σ analog to digital converter (ADC through proposing four attack and one defense models. The first attack manipulates the input signal to the Δ Σ modulator. The second attack manipulates the analog version of the modulator output bit and is triggered by the noise signal. The third attack manipulates the modulator output bit and has a controllable trigger mechanism. The fourth attack manipulates the analog version of the modulator output bit and is triggered by a victim capacitance within the chip. For the defense, a number of signal processing filters are used in order to purge the analog version of the modulator output bit for elimination of the malicious unwanted features, introduced by the attacks. According to the simulation results, the second threat model displays the strongest attack. Derived from the countermeasure evaluation, the best filter to confront the threat models is the robust regression using the least absolute residual computing method.

  9. A Fast Digital Integrator for Magnetic Measurements

    CERN Document Server

    Spiezia, G

    2008-01-01

    In this work, the Fast Digitial Integrator (FDI), conceived for characterizing dynamic features of superconducting magnets and measuring fast transients of magnetic fields at the European Organization for Nuclear Research (CERN) and other high-energy physics research centres, is presented. FDI development was carried out inside a framework of cooperation between the group of Magnet Tests and Measurements of CERN and the Department of Engineering of the University of Sannio. Drawbacks related to measurement time decrease of main high-performance analog-to-digital architectures, such as Delta-Sigma and integrators, are overcome by founding the design on (i) a new generation of successive approximation converters, for high resolution (18-bit) at high rate (500 kS/s), (ii) a digital signal processor, for on-line down-sampling by integrating the input signal, (iii) a custom time base, based on a Universal Time Counter, for reducing time-domain uncertainty, and (iv) a PXI board, for high bus transfer rate, as well ...

  10. Wireless micropower instrumentation for multimodal acquisition of electrical and chemical neural activity.

    Science.gov (United States)

    Mollazadeh, M; Murari, K; Cauwenberghs, G; Thakor, N

    2009-12-01

    The intricate coupling between electrical and chemical activity in neural pathways of the central nervous system, and the implication of this coupling in neuropathologies, such as Parkinson's disease, motivates simultaneous monitoring of neurochemical and neuropotential signals. However, to date, neurochemical sensing has been lacking in integrated clinical instrumentation as well as in brain-computer interfaces (BCI). Here, we present an integrated system capable of continuous acquisition of data modalities in awake, behaving subjects. It features one channel each of a configurable neuropotential and a neurochemical acquisition system. The electrophysiological channel is comprised of a 40-dB gain, fully differential amplifier with tunable bandwidth from 140 Hz to 8.2 kHz. The amplifier offers input-referred noise below 2 muV rms for all bandwidth settings. The neurochemical module features a picoampere sensitivity potentiostat with a dynamic range spanning six decades from picoamperes to microamperes. Both systems have independent on-chip, configurable DeltaSigma analog-to-digital converters (ADCs) with programmable digital gain and resolution. The system was also interfaced to a wireless power harvesting and telemetry module capable of powering up the circuits, providing clocks for ADC operation, and telemetering out the data at up to 32 kb/s over 3.5 cm with a bit-error rate of less than 10(-5). Characterization and experimental results from the electrophysiological and neurochemical modules as well as the full system are presented.

  11. Analog to Digital: Transitions in Theory and Practice in Archaeological Photography at Çatalhöyük

    Directory of Open Access Journals (Sweden)

    Colleen Morgan

    2016-09-01

    Full Text Available Archaeology and photography has a long, co-constructed history that has increasingly come under scrutiny as archaeologists negotiate the visual turn. Yet these investigations do not make use of existing qualitative and quantitative strategies developed by visual studies to understand representation in archaeological photographs. This article queries the large photographic archive created by ongoing work at the archaeological site of Çatalhöyük in Turkey to consider the visual impact of changing photographic technologies and of a shifting theoretical focus in archaeology. While using content analysis and semiotic analysis to gain a better understanding of the visual record, these analyses also unexpectedly reveal power dynamics and other social factors present during archaeological investigation. Consequently, becoming conversant in visual analyses can contribute to developing more reflexive modes of representation in archaeology.

  12. Proposed electromagnetic wave energy converter

    Science.gov (United States)

    Bailey, R. L.

    1973-01-01

    Device converts wave energy into electric power through array of insulated absorber elements responsive to field of impinging electromagnetic radiation. Device could also serve as solar energy converter that is potentially less expensive and fragile than solar cells, yet substantially more efficient.

  13. Impedance Source Power Electronic Converters

    DEFF Research Database (Denmark)

    Liu, Yushan; Abu-Rub, Haitham; Ge, Baoming

    Impedance Source Power Electronic Converters brings together state of the art knowledge and cutting edge techniques in various stages of research related to the ever more popular impedance source converters/inverters. Significant research efforts are underway to develop commercially viable...... and technically feasible, efficient and reliable power converters for renewable energy, electric transportation and for various industrial applications. This book provides a detailed understanding of the concepts, designs, controls, and application demonstrations of the impedance source converters/inverters. Key...... control methods. Presents the latest power conversion solutions that aim to advance the role of power electronics into industries and sustainable energy conversion systems. Compares impedance source converter/inverter applications in renewable energy power generation and electric vehicles as well...

  14. Radiation tolerant power converter controls

    CERN Document Server

    Todd, B; King, Q; Uznanski, S

    2012-01-01

    The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world's most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Each converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). The FGC allows remote control of the power converter and forms the central part of a closed-loop control system where the power converter voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, having a direct impact upon the accelerator's availability. Following the first long shut down (LS1), the LHC will be able to run with higher intensity beams and higher beam energy. This is expected to lead to signifi...

  15. Power converter simulation and analysis

    Energy Technology Data Exchange (ETDEWEB)

    Ghazy, M.A.

    1989-01-01

    There has been a great deal of progress made in computer aided design and analysis in the power electronic field. Many of the simulation packages are inefficient and time consuming in simulating switching converters. This thesis proposes an efficient, simple, general simulation approach to simulate any power converter with less computation time and space requirements on computer. In this approach the equations of power converters are formulated using network topology. In this thesis several procedures have been explained for the steady-state computation of power electronic circuits. Also, the steady-state analyses have been accomplished by a new technique called Fourier series method. For a complete system consisting of converters, filters, and electric machines, the simulation is complicated if a frequency domain technique is used. This thesis introduces a better technique which decouples the system into subsystems and simulates it in the time domain. The design of power converters using optimization techniques is presented in this thesis. Finally, the theory of Variable Structured Systems has been applied to power converters. Sliding mode control for DC-DC and DC-AC power converters is introduced as a tool to accomplish desired characteristics.

  16. PWM DC/DC Converter

    OpenAIRE

    Chen, Juan

    2008-01-01

    This report is the result of a Master Thesis work done at Seaward Electronics Inc. in Beijing, China from June to December in 2007. The main goal for this thesis is to verify and improve the performance of Honey-PWM DC-DC converter, which has been fabricated by a standard 0.6um CMOS processes. The project was started with studying of Buck converter structure. After the understanding of the converter structure, the project goes in to the analyses phase for each sub-cells, including the theory,...

  17. Laser system with wavelength converter

    DEFF Research Database (Denmark)

    2012-01-01

    The present invention relates to an apparatus comprising a diode laser (10) providing radiation in a first wavelength interval, a radiation conversion unit (12) having an input and an output, the radiation converter configured to receive the radiation in the first wavelength interval from the diode...... laser at the input, the radiation conversion unit configured to convert the radiation in the first wavelength interval to radiation in a second wavelength interval and the output configured to output the converted radiation, the second wavelength interval having one end point outside the first...... wavelength interval. Further, the invention relates to a method of optically pumping a target laser (14) in a laser system, the laser system comprising a laser source providing radiation at a first frequency, the laser source being optically connected to an input of a frequency converter, the frequency...

  18. Time-to-digital converters

    CERN Document Server

    Henzler, Stephan

    2010-01-01

    This text covers the fundamentals of time-to-digital converters on analog and digital conversion principles. It includes a theoretical investigation into quantization, linearity, noise and variability, and it details a range of advanced TDC architectures.

  19. Boron nitride converted carbon fiber

    Science.gov (United States)

    Rousseas, Michael; Mickelson, William; Zettl, Alexander K.

    2016-04-05

    This disclosure provides systems, methods, and apparatus related to boron nitride converted carbon fiber. In one aspect, a method may include the operations of providing boron oxide and carbon fiber, heating the boron oxide to melt the boron oxide and heating the carbon fiber, mixing a nitrogen-containing gas with boron oxide vapor from molten boron oxide, and converting at least a portion of the carbon fiber to boron nitride.

  20. Photoelectric converters with quantum coherence

    OpenAIRE

    Su, Shan-He; Sun, Chang-Pu; Li, Sheng-Wen; Chen, Jin-Can

    2016-01-01

    Photon impingement is capable of liberating electrons in electronic devices and driving the electron flux from the lower chemical potential to higher chemical potential. Previous studies hinted that the thermodynamic efficiency of a nano-sized photoelectric converter at maximum power is bounded by the Curzon-Ahlborn efficiency. In this study, we apply quantum effects to design a photoelectric converter based on a three-level quantum dot (QD) interacting with fermionic baths and photons. We sh...

  1. Radiation tolerant power converter controls

    Science.gov (United States)

    Todd, B.; Dinius, A.; King, Q.; Uznanski, S.

    2012-11-01

    The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world's most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Each converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). The FGC allows remote control of the power converter and forms the central part of a closed-loop control system where the power converter voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, having a direct impact upon the accelerator's availability. Following the first long shut down (LS1), the LHC will be able to run with higher intensity beams and higher beam energy. This is expected to lead to significantly increased radiation induced effects in materials close to the accelerator, including the FGC. Recent radiation tests indicate that the current FGC would not be sufficiently reliable. A so-called FGClite is being designed to work reliably in the radiation environment in the post-LS1 era. This paper outlines the concepts of power converter controls for machines such as the LHC, introduces the risks related to radiation and a radiation tolerant project flow. The FGClite is then described, with its key concepts and challenges: aiming for high reliability in a radiation field.

  2. Transformerless dc-Isolated Converter

    Science.gov (United States)

    Rippel, Wally E.

    1987-01-01

    Efficient voltage converter employs capacitive instead of transformer coupling to provide dc isolation. Offers buck/boost operation, minimal filtering, and low parts count, with possible application in photovoltaic power inverters, power supplies and battery charges. In photovoltaic inverter circuit with transformerless converter, Q2, Q3, Q4, and Q5 form line-commutated inverter. Switching losses and stresses nil because switching performed when current is zero.

  3. Wave energy converter test application

    OpenAIRE

    Hottola, Niko

    2016-01-01

    This thesis was made for wave energy company Wello Oy. Given assignment was to find the suitable generator and frequency converter for a wave energy converter test application. The primary objective was to find a suitable generator for direct drive, in order to avoid the weight of the test application rising too high. In this thesis the possible machine types for test application are presented and what are their advenatages and disadvantages. In addition, the operation of the frequency co...

  4. Design of a 12-b 10 Msample/s CMOS Pipeline A/D Converter%12位1O MS/s CMOS流水线A/D转换器的设计

    Institute of Scientific and Technical Information of China (English)

    雷铿铭; 刘三清; 东振中; 陈钊

    2001-01-01

    文中介绍了一种六级12位10 Msample/s CMOS流水线A/D转换器的设计。该设计方案采用了双差分动态比较器结构,保证了处理模拟信号的精度与速度;采用冗余编码技术,进行数字误差校正,减小了多种误差敏感性,避免了由于余量电压超限而导致的失码,并降低了采样/保持电路和D/A转换电路的设计难度。%A six-stage 12-b 10-Msample/s CMOS pipeline analog-to-digital converter(ADC) is presented in the paper. The structure of double differential dynamic comparator is used in the proposed scheme to realize high resolution and high speed. The technology of redundance decode ia used in this scheme to correct the digital error and reduce error source ,thus avoiding the missing code and reducing the difficulty in the design of the circuit.

  5. Radiation effects on DC-DC Converters

    Science.gov (United States)

    Zhang, Dexin; Attia, John O.; Kankam, Mark D. (Technical Monitor)

    2000-01-01

    DC-DC switching converters are circuits that can be used to convert a DC voltage of one value to another by switching action. They are increasing being used in space systems. Most of the popular DC-DC switching converters utilize power MOSFETs. However power MOSFETs, when subjected to radiation, are susceptible to degradation of device characteristics or catastrophic failure. This work focuses on the effects of total ionizing dose on converter performance. Four fundamental switching converters (buck converter, buck-boost converter, cuk converter, and flyback converter) were built using Harris IRF250 power MOSFETs. These converters were designed for converting an input of 60 volts to an output of about 12 volts with a switching frequency of 100 kHz. The four converters were irradiated with a Co-60 gamma source at dose rate of 217 rad/min. The performances of the four converters were examined during the exposure to the radiation. The experimental results show that the output voltage of the converters increases as total dose increases. However, the increases of the output voltage were different for the four different converters, with the buck converter and cuk converter the highest and the flyback converter the lowest. We observed significant increases in output voltage for cuk converter at a total dose of 24 krad (si).

  6. Compact FPGA-based beamformer using oversampled 1-bit A/D converters

    DEFF Research Database (Denmark)

    Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

    2005-01-01

    reconstruction is done using finite impulse response (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50......% of the available logic resources in a commercially available midrange FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz....

  7. Binary/BCD-to-ASCII data converter

    Science.gov (United States)

    Miller, A. J.

    1977-01-01

    Converter inputs multiple precision binary words, converts data to multiple precision binary-coded decimal, and routes data back to computer. Converter base can be readily changed without need for new gate structure for each base changeover.

  8. PWM Converter Power Density Barriers

    Science.gov (United States)

    Kolar, Johann W.; Drofenik, Uwe; Biela, Juergen; Heldwein, Marcelo; Ertl, Hans; Friedli, Thomas; Round, Simon

    Power density of power electronic converters has roughly doubled every 10 years since 1970. Behind this trajectory is the continuous advancement of power semiconductor devices, which has increased the converter switching frequencies by a factor of 10 every decade. However, today's cooling concepts and passive components are major barriers for a continuation of this trend. To identify such technological barriers, this paper investigates the volume of the cooling system and passive components as a function of the switching frequency for power electronic converters and determines the switching frequency that minimizes the total volume. A power density limit of 28kW/dm3 at 300kHz is calculated for an isolated DC-DC converter, 44kW/dm3 at 820kHz for a three-phase unity power factor PWM rectifier, and 26kW/dm3 at 21kHz for a sparse matrix converter. For single-phase AC-DC conversion a general limit of 35kW/dm3 results from the DC link capacitor. These power density limits highlight the need to broaden the scope of power electronics research to include cooling systems, high frequency electromagnetics, interconnection and packaging technology, and multi-domain modelling and simulation to ensure further advancement along the power density trajectory.

  9. Post combustion in converter steelmaking

    Energy Technology Data Exchange (ETDEWEB)

    Oghbasilasie, H.; Holappa, L.

    1997-12-31

    The purpose of this work is to study the fundamentals of post combustion and the effect of different process parameters on the post combustion ratio (PCR) and heat transfer efficiency (HTE) in converter steelmaking process. The PCR and HTE have been determined under normal operating conditions. Trials assessed the effect of lance height, vessel volume, foaming slag and pellet additions on PCR and HTE. Based on enthalpy considerations, post combustion of CO gas is regarded as one of the most effective means of increasing the heat supply to the BOP. The thermodynamic study of gas-metal-slag reactions gives the limiting conditions for post combustion inside the converter reactor. Different process parameters influencing both thermodynamic equilibria and kinetic conditions can greatly affect the post combustion ratio. Different features of converter processes as well smelting reduction processes utilizing post combustion have been reviewed. (orig.) SULA 2 Research Programme; 26 refs.

  10. Stirling Converters For Solar Power

    Science.gov (United States)

    Shaltens, Richard K.; Schreiber, Jeffrey G.

    1993-01-01

    Two designs expected to meet long-term goals for performance and cost. Proposed for advanced systems to convert solar thermal power to electrical power. Each system, designed to operate with 11-m-diameter paraboloidal reflector, includes solar-energy receiver, liquid-metal heat-transport subsystem, free-piston Stirling engine, cooling subsystem, alternator or generator coupled directly or indirectly to commercial electric-power system, and control and power-conditioning circuitry. System converts approximately 75 kW of input solar thermal power falling on collector to about 25 kW of output electrical power.

  11. Design and Control for the Buck-Boost Converter Combining 1-Plus-D Converter and Synchronous Rectified Buck Converters

    OpenAIRE

    2015-01-01

    In this paper, a design and control for the buck-boost converter, i.e., 1-plus-D converter with a positive output voltage, is presented, which combines the 1-plus-D converter and the synchronous rectified (SR) buck converter. By doing so, the problem in voltage bucking of the 1-plus-D converter can be solved, thereby increasing the application capability of the 1-plus-D converter. Since such a converter operates in continuous conduction mode inherently, it possesses the nonpulsating output cu...

  12. AC-DC PFC Converter Using Combination of Flyback Converter and Full-bridge DC-DC Converter

    Directory of Open Access Journals (Sweden)

    Moh. Zaenal Efendi

    2014-06-01

    Full Text Available This paper presents a combination of power factor correction converter using Flyback converter and Full-bridge dc-dc converter in series connection. Flyback converter is operated in discontinuous conduction mode so that it can serve as a power factor correction converter and meanwhile Full-bridge dc-dc converter is used for dc regulator. This converter system is designed to produce a 86 Volt of output voltage and 2 A of output current. Both simulation and experiment results show that the power factor of this converter achieves up to 0.99 and meets harmonic standard of IEC61000-3-2. Keywords: Flyback Converter, Full-bridge DC-DC Converter, Power Factor Correction.

  13. XML Docbook to Mediawiki Converter

    Directory of Open Access Journals (Sweden)

    Maria Chiara Pievatolo

    2013-05-01

    Full Text Available A Perl script, based on the work of Stefano Selleri, to migrate XML-Docbook 4.X documents to Wiki markup. I added some lines to meet my need to convert my Kant translations from Docbook to MediaWiki. A sample of the output can be...

  14. Charge-pump voltage converter

    Science.gov (United States)

    Brainard, John P.; Christenson, Todd R.

    2009-11-03

    A charge-pump voltage converter for converting a low voltage provided by a low-voltage source to a higher voltage. Charge is inductively generated on a transfer rotor electrode during its transit past an inductor stator electrode and subsequently transferred by the rotating rotor to a collector stator electrode for storage or use. Repetition of the charge transfer process leads to a build-up of voltage on a charge-receiving device. Connection of multiple charge-pump voltage converters in series can generate higher voltages, and connection of multiple charge-pump voltage converters in parallel can generate higher currents. Microelectromechanical (MEMS) embodiments of this invention provide a small and compact high-voltage (several hundred V) voltage source starting with a few-V initial voltage source. The microscale size of many embodiments of this invention make it ideally suited for MEMS- and other micro-applications where integration of the voltage or charge source in a small package is highly desirable.

  15. High-Performance Data Converters

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    Novel techniques for multi-bit oversampled data conversion are described. State-of-the-art oversampled data converters are analyzed, leading to the conclusion that their performance is limited mainly by low-resolution signal representation. To increase the resolution, high-performance, high...

  16. Bidirectional dc-to-dc Power Converter

    Science.gov (United States)

    Griesbach, C. R.

    1986-01-01

    Solid-state, series-resonant converter uses high-voltage thyristors. Converter used either to convert high-voltage, low-current dc power to lowvoltage, high current power or reverse. Taking advantage of newly-available high-voltage thyristors to provide better reliability and efficiency than traditional converters that use vacuum tubes as power switches. New converter essentially maintenance free and provides greatly increased mean time between failures. Attractive in industrial applications whether or not bidirectional capability is required.

  17. Parametric study of laser photovoltaic energy converters

    Science.gov (United States)

    Walker, G. H.; Heinbockel, J. H.

    1987-01-01

    Photovoltaic converters are of interest for converting laser power to electrical power in a space-based laser power system. This paper describes a model for photovoltaic laser converters and the application of this model to a neodymium laser silicon photovoltaic converter system. A parametric study which defines the sensitivity of the photovoltaic parameters is described. An optimized silicon photovoltaic converter has an efficiency greater than 50 percent for 1000 W/sq cm of neodymium laser radiation.

  18. Photoelectric converters with quantum coherence

    Science.gov (United States)

    Su, Shan-He; Sun, Chang-Pu; Li, Sheng-Wen; Chen, Jin-Can

    2016-05-01

    Photon impingement is capable of liberating electrons in electronic devices and driving the electron flux from the lower chemical potential to higher chemical potential. Previous studies hinted that the thermodynamic efficiency of a nanosized photoelectric converter at maximum power is bounded by the Curzon-Ahlborn efficiency ηCA. In this study, we apply quantum effects to design a photoelectric converter based on a three-level quantum dot (QD) interacting with fermionic baths and photons. We show that, by adopting a pair of suitable degenerate states, quantum coherences induced by the couplings of QDs to sunlight and fermion baths can coexist steadily in nanoelectronic systems. Our analysis indicates that the efficiency at maximum power is no longer limited to ηCA through manipulation of carefully controlled quantum coherences.

  19. Photoelectric converter; Koden henkan soshi

    Energy Technology Data Exchange (ETDEWEB)

    Sawayama, I.

    1995-04-07

    The conventional solar cell module wherein plural photovoltaic elements formed on a metal substrate are connected and coated by weatherproof and translucent resin has defects such as pinholes, and separation because moisture infiltrating from the outside causes dissolution of such conductive matrix as silver in the collecting electrode. This invention relates to a photoelectric converter which has little decrease in the output under the environment of light irradiation, wherein a photoelectric converting semiconductor, a transparent conductive layer on the above-mentioned semiconductor, and conductive member containing water repellent fine powder grains on this transparent conductive layer are laminated successively. Polytetrafluoroethylene, polydimethyl siloxane, polyethylene, and nylon are desirable to be employed as the water repellent fine powder grains. The fine powder grains are mixed with conductive filler and binder to produce conductive paste, pattern-applied by a screen printing machine, and subjected to thermal treatment to form a conductive member. 3 figs., 1 tab.

  20. Photoelectric converters with quantum coherence.

    Science.gov (United States)

    Su, Shan-He; Sun, Chang-Pu; Li, Sheng-Wen; Chen, Jin-Can

    2016-05-01

    Photon impingement is capable of liberating electrons in electronic devices and driving the electron flux from the lower chemical potential to higher chemical potential. Previous studies hinted that the thermodynamic efficiency of a nanosized photoelectric converter at maximum power is bounded by the Curzon-Ahlborn efficiency η_{CA}. In this study, we apply quantum effects to design a photoelectric converter based on a three-level quantum dot (QD) interacting with fermionic baths and photons. We show that, by adopting a pair of suitable degenerate states, quantum coherences induced by the couplings of QDs to sunlight and fermion baths can coexist steadily in nanoelectronic systems. Our analysis indicates that the efficiency at maximum power is no longer limited to η_{CA} through manipulation of carefully controlled quantum coherences.

  1. Simplified dc to dc converter

    Science.gov (United States)

    Gruber, R. P. (Inventor)

    1984-01-01

    A dc to dc converter which can start with a shorted output and which regulates output voltage and current is described. Voltage controlled switches directed current through the primary of a transformer the secondary of which includes virtual reactance. The switching frequency of the switches is appropriately varied to increase the voltage drop across the virtual reactance in the secondary winding to which there is connected a low impedance load. A starting circuit suitable for voltage switching devices is provided.

  2. Biomass compounds converted to gasoline

    Energy Technology Data Exchange (ETDEWEB)

    1979-10-08

    It is claimed that corn, castor, and jojoba oils as well as Hevea latex can be converted in high yields to gasoline by passage over zeolite catalysts at 450 degrees to 500 degrees centigrade. Gasoline yields are 60% from corn oil (essentially tristearin), compared with 50% yields from methanol. Latex depolymerizes before conversion. Fat and oil molecules adopt conformations that enable them to enter zeolite interstices, resulting in high yields of C6 to C9 aromatics.

  3. Workshop 4 Converter cooling & recuperation

    Science.gov (United States)

    Iles, Peter; Hindman, Don

    1995-01-01

    Cooling the PV converter increases the overall TPV system efficiency, and more than offsets the losses incurred in providing cooling systems. Convective air flow methods may be sufficient, and several standard water cooling systems, including thermo-syphon radiators, capillary pumps or microchannel plates, are available. Recuperation is used to increase system efficiency, rather than to increase the emitter temperature. Recuperators operating at comparable high temperatures, such as in high temperature turbines have worked effectively.

  4. Computerized simulation of converter process

    Energy Technology Data Exchange (ETDEWEB)

    Jalkanen, H.; Suomi, M.L.; Wallgren, M. [Helsinki Univ. of Technology, Otaniemi (Finland). Lab. of Metallurgy

    1996-12-31

    Converter process is essentially an oxidising refining process aiming in addition to (1) the primary refining action, decarburisation of high carbon iron melt, also to (2) maximal elimination of impurity elements, especially silicon, phosphorus and sulphur, (3) melting of substantial amounts of scrap using the extra heat released in oxidation reactions and (4) to exact final steel temperature control, optimal for further treatments. `Quantitative modelling of such a complex non-stationary chemical process as oxygen converting necessitates extensive formulation of chemical and thermal evolution of the process in connection with the technological properties of the reactor and the process control measures. A comprehensive converter simulation program like CONSIM-3. 1 and its preceding versions that is based on the theoretical and practical knowledge on the process can be used for (1) educating specialists and smelter personnel, (2) planning of the blowing programs, (3) developing and testing of process control systems and after some elaboration and restructuring (4) it can be integrated to static or dynamic process control systems. (orig.) SULA 2 Research Programme; 10 refs.

  5. Design and Control for the Buck-Boost Converter Combining 1-Plus-D Converter and Synchronous Rectified Buck Converters

    Directory of Open Access Journals (Sweden)

    Jeevan Naik

    2015-06-01

    Full Text Available In this paper, a design and control for the buck-boost converter, i.e., 1-plus-D converter with a positive output voltage, is presented, which combines the 1-plus-D converter and the synchronous rectified (SR buck converter. By doing so, the problem in voltage bucking of the 1-plus-D converter can be solved, thereby increasing the application capability of the 1-plus-D converter. Since such a converter operates in continuous conduction mode inherently, it possesses the nonpulsating output current, thereby not only decreasing the current stress on the output capacitor but also reducing the output voltage ripple. Above all, both the 1-plus-D converter and the SR buck converter, combined into a buck–boost converter with no right-half plane zero, use the same power switches, thereby causing the required circuit to be compact and the corresponding cost to be down. Furthermore, during the magnetization period, the input voltage of the 1-plus-D converter comes from the input voltage source, whereas during the demagnetization period, the input voltage of the 1-plus-D converter comes from the output voltage of the SR buck converter.

  6. Simulation Results of Double Forward Converter

    Directory of Open Access Journals (Sweden)

    P. Vijaya KUMAR

    2009-12-01

    Full Text Available This work aims to find a better forward converter for DC to DC conversion.Simulation of double forward converter in SMPS system is discussed in this paper. Aforward converter with RCD snubber to synchronous rectifier and/or to current doubleris also discussed. The evolution of the forward converter is first reviewed in a tutorialfashion. Performance parameters are discussed including operating principle, voltageconversion ratio, efficiency, device stress, small-signal dynamics, noise and EMI. Itscircuit operation and its performance characteristics of the forward converter with RCDsnubber and double forward converter are described and the simulation results arepresented.

  7. Si Bule Masuk Islam: Western Converts to Islam in Indonesia - more than just Converts of Convenience?

    OpenAIRE

    M. A. Kevin Brice

    2015-01-01

    In discussing converts to Islam, two different types of converts are often identified based on the reason for conversion: converts of convenience and converts of conviction. The common view is that in most (if not all) cases, conversion to Islam in Indonesia by Westerners is about facilitating marriage and so the converts should be classified as converts of convenience. Evidence of the commonality of this view is considered by reference to advice offered to Westerners about marriage to Indone...

  8. multilevel buck converter for automotive electrical load

    African Journals Online (AJOL)

    user

    development of DCM based buck converter and its applications in the HEVs/EVs using ... The paper also highlights the implications of implementing a single stage buck converter, and ..... instance when the saw tooth signal within the internal.

  9. Converting pest insects into food

    DEFF Research Database (Denmark)

    Offenberg, Hans Joachim; Wiwatwittaya, Decha

    2010-01-01

    on management, 32-115 kg ant brood (mainly new queens) was harvested per ha per year without detrimental effect on colony survival and worker ant densities. This suggest that ant biocontrol and ant harvest can be sustainable integrated in plantations and double benefits derived. As ant production is fuelled...... by pest insects, problematic pests are converted into food and additional earnings. To assess the profitability of providing additional food for the ants, O. smaragdina food conversion efficiency (ECI) was estimated in the laboratory. This estimate suggests the feeding of weaver ants in ant farms...

  10. Power electronics converters and regulators

    CERN Document Server

    Dokić, Branko L

    2015-01-01

    This book is the result of the extensive experience the authors gained through their year-long occupation at the Faculty of Electrical Engineering at the University of Banja Luka. Starting at the fundamental basics of electrical engineering, the book guides the reader into this field and covers all the relevant types of converters and regulators. Understanding is enhanced by the given examples, exercises and solutions. Thus this book can be used as a textbook for students, for self-study or as a reference book for professionals.

  11. Converting pest insects into food

    DEFF Research Database (Denmark)

    Offenberg, Hans Joachim; Wiwatwittaya, Decha

    2010-01-01

    Canopy dwelling weaver ants (Oecophylla spp.) are used to control a variety of pests in a number of tropical tree crops. What is less familiar is the existence of commercial markets where these ants and their brood are sold for (i) human consumption, (ii) pet food or (iii) traditional medicine...... by pest insects, problematic pests are converted into food and additional earnings. To assess the profitability of providing additional food for the ants, O. smaragdina food conversion efficiency (ECI) was estimated in the laboratory. This estimate suggests the feeding of weaver ants in ant farms...

  12. OAM mode converter in twisted fibers

    DEFF Research Database (Denmark)

    Usuga Castaneda, Mario A.; Beltran-Mejia, Felipe; Cordeiro, Cristiano

    2014-01-01

    We analyze the case of an OAM mode converter based on a twisted fiber, through finite element simulations where we exploit an equivalence between geometric and material transformations. The obtained converter has potential applications in MDM. © 2014 OSA.......We analyze the case of an OAM mode converter based on a twisted fiber, through finite element simulations where we exploit an equivalence between geometric and material transformations. The obtained converter has potential applications in MDM. © 2014 OSA....

  13. Analysis and design of converters in Matlab

    OpenAIRE

    Lorente Sanjurjo, Rodrigo

    2010-01-01

    This project will try to provide better understanding of data converters, more specifically in the mathematical representation and coding of non idealities of the converter. As programming tool it will be used the MATLAB environment, with which will carry out the coding and the analysis of the behavior of the converters by adding diverse nonlinearities, taking advantage of the simplicity, clarity, and extensibility that provides this environment. Summarizing, it is going to study the converte...

  14. Ecologically Optimal Solution of Power Semiconductors Converters

    Directory of Open Access Journals (Sweden)

    Ivan Lokseninec

    2003-01-01

    Full Text Available One of the relevant scientific programs of Department of Power Electrical Systems is research of ecologically optimal topologies main circuits of power converters. This paper presents some methods how to reduce unfavourable influences of power converters on the grid. The achieved results were applieed in praxis, especially in the power converters produced by Electrotechnical Research and Projecting Institute in Nova Dubnica.

  15. Time-interleaved oversampling convertors

    Science.gov (United States)

    Khoini-Poorfard, R.; Johns, D. A.

    1993-09-01

    A new architecture is proposed which exploits the time-interleaving concept to increase the oversampling ratio in delta-sigma modulators. It is shown that the effective oversampling ratio is increased by a factor M through the use of M interconnected modulators. Although a high speed sample-and-hold circuit is still required for an analog-to-digital convertor, speed constraints are significantly reduced for the majority of analogue parts such as loop filters, A/D and D/A blocks.

  16. A dc to dc converter

    Science.gov (United States)

    Willis, A. E.; Gould, J. M.; Matheney, J. L.; Garrett, H. (Inventor)

    1984-01-01

    The object of the invention is to provide an improved converter for converting one direct current voltage to another. A plurality of phased square wave voltages are provided from a ring counter through amplifiers to a like plurality of output transformers. Each of these transformers has two windings, and S(1) winding and an S(2) winding. The S(1) windings are connected in series, then the S(2) windings are connected in series, and finally, the two sets of windings are connected in series. One of six SCRs is connected between each two series connected windings to a positive output terminal and one of diodes is connected between each set of two windings of a zero output terminal. By virtue of this configuration, a quite high average direct current voltage is obtained, which varies between full voltage and two-thirds full voltage rather than from full voltage to zero. Further, its variation, ripple frequency, is reduced to one-sixth of that present in a single phase system. Application to raising battery voltage for an ion propulsion system is mentioned.

  17. Valuing Convertible Bonds Based on LSRQM Method

    Directory of Open Access Journals (Sweden)

    Jian Liu

    2014-01-01

    Full Text Available Convertible bonds are one of the essential financial products for corporate finance, while the pricing theory is the key problem to the theoretical research of convertible bonds. This paper demonstrates how to price convertible bonds with call and put provisions using Least-Squares Randomized Quasi-Monte Carlo (LSRQM method. We consider the financial market with stochastic interest rates and credit risk and present a detailed description on calculating steps of convertible bonds value. The empirical results show that the model fits well the market prices of convertible bonds in China’s market and the LSRQM method is effective.

  18. Efficiency of Capacitively Loaded Converters

    DEFF Research Database (Denmark)

    Andersen, Thomas; Huang, Lina; Andersen, Michael A. E.;

    2012-01-01

    This paper explores the characteristic of capacitance versus voltage for dielectric electro active polymer (DEAP) actuator, 2kV polypropylene film capacitor as well as 3kV X7R multi layer ceramic capacitor (MLCC) at the beginning. An energy efficiency for capacitively loaded converters...... is introduced as a definition of efficiency. The calculated and measured efficiency curves for charging DEAP actuator, polypropylene film capacitor and X7R MLCC are provided and compared. The attention has to be paid for the voltage dependent capacitive load, like X7R MLCC, when evaluating the charging...... polypropylene film capacitor can be the equivalent capacitive load. Because of the voltage dependent characteristic, X7R MLCC cannot be used to replace the DEAP actuator. However, this type of capacitor can be used to substitute the capacitive actuator with voltage dependent property at the development phase....

  19. Reliability of Wave Energy Converters

    DEFF Research Database (Denmark)

    Ambühl, Simon

    . Structural reliability considerations and optimizations impact operation and maintenance (O&M) costs as well as the initial investment costs. Furthermore, there is a control system for WEC applications which defines the harvested energy but also the loads onto the structure. Therefore, extreme loads but also...... WEPTOS. Calibration of safety factors are performed for welded structures at theWavestar device including different control systems for harvesting energy from waves. In addition, a case study of different O&M strategies for WECs is discussed, and an example of reliability-based structural optimization......There are many different working principles for wave energy converters (WECs) which are used to produce electricity from waves. In order for WECs to become successful and more competitive to other renewable electricity sources, the consideration of the structural reliability of WECs is essential...

  20. Reliability of Wave Energy Converters

    DEFF Research Database (Denmark)

    Ambühl, Simon

    for welded structures at the Wavestar device includingdifferent control systems for harvesting energy from waves. In addition, a casestudy of different O&M strategies for WECs is discussed, and an example ofreliability-based structural optimization of the Wavestar foundation ispresented. The work performed......There are many different working principles for wave energy converters (WECs) which are used to produce electricity from waves. In order for WECs tobecome successful and more competitive to other renewable electricity sources,the consideration of the structural reliability of WECs is essential.......Structural reliability considerations and optimizations impact operation andmaintenance (O&M) costs as well as the initial investment costs.Furthermore, there is a control system for WEC applications which defines theharvested energy but also the loads onto the structure. Therefore, extremeloads but also fatigue loads...

  1. Reliability of Wave Energy Converters

    DEFF Research Database (Denmark)

    Ambühl, Simon

    There are many different working principles for wave energy converters (WECs) which are used to produce electricity from waves. In order for WECs to become successful and more competitive to other renewable electricity sources, the consideration of the structural reliability of WECs is essential....... Structural reliability considerations and optimizations impact operation and maintenance (O&M) costs as well as the initial investment costs. Furthermore, there is a control system for WEC applications which defines the harvested energy but also the loads onto the structure. Therefore, extreme loads but also...... of the Wavestar foundation is presented. The work performed in this thesis focuses on the Wavestar and WEPTOS WEC devices which are only two working principles out of a large diversity. Therefore, in order to gain general statements and give advice for standards for structural WEC designs, more working principles...

  2. Manufacturing method of photoelectric converter

    Energy Technology Data Exchange (ETDEWEB)

    Toda, Koji; Niwa, Yasuo

    1987-06-24

    In a method of making a thin film for a photoelectric converter by a method to form an electroconductive layer by burning a mixture of lead oxide and chromic oxide, thickness of the film was limited and the poreless uniform film was not obtainable. The intransparency of the film gave low conversion efficiency only. This invention enabled to obtain a transparent film wherein an oxide (containing lead and chrome) is used as a target to form, in vacuum, a thin film of the oxide, and then this thin film is heat-treated in an atmosphere at least containing lead. Thin transparent film was obtained enhancing the conversion efficiency. High quality and high reliability are ensured because a poreless uniform film can be obtained. Cost was reduced because mass-production was made possible by the use of a vacuum technique. (5 figs)

  3. The SSG Wave Energy Converter

    DEFF Research Database (Denmark)

    Vicinanza, Diego; Margheritini, Lucia; Kofoed, Jens Peter

    2012-01-01

    The Sea-wave Slot-cone Generator concept (SSG) is a Wave Energy Converter based on the wave overtopping principle utilizing several reservoirs placed on top of each other, in which the energy of the incoming wave will be stored as potential energy. The water captured in the reservoirs will then run...... through turbines for electricity production. The system utilizes a wide spectrum of different wave conditions by means of multiple reservoirs, located at different levels above the still water level. Thereby, it obtains a high overall efficiency and it can be suitable for shoreline and breakwater...... applications, presenting particular advantages such as: sharing structure costs, availability of grid connection and infrastructures, recirculation of water inside the harbor, as the outlet of the turbines is on the rear part of the system. Recently, plans for the SSG pilot installation were in progress...

  4. Three-phase AC-AC power converters based on matrix converter topology matrix-reactance frequency converters concept

    CERN Document Server

    Szczesniak, Pawel

    2013-01-01

    AC voltage frequency changes is one of the most important functions of solid state power converters. The most desirable features in frequency converters are the ability to generate load voltages with arbitrary amplitude and frequency, sinusoidal currents and voltages waveforms; the possibility of providing unity power factor for any load; and, finally, a simple and compact power circuit. Over the past decades, a number of different frequency converter topologies have appeared in the literature, but only the converters with either a voltage or current DC link are commonly used in industrial app

  5. Radiation-Tolerant DC-DC Converters

    Science.gov (United States)

    Skutt, Glenn; Sable, Dan; Leslie, Leonard; Graham, Shawn

    2012-01-01

    A document discusses power converters suitable for space use that meet the DSCC MIL-PRF-38534 Appendix G radiation hardness level P classification. A method for qualifying commercially produced electronic parts for DC-DC converters per the Defense Supply Center Columbus (DSCC) radiation hardened assurance requirements was developed. Development and compliance testing of standard hybrid converters suitable for space use were completed for missions with total dose radiation requirements of up to 30 kRad. This innovation provides the same overall performance as standard hybrid converters, but includes assurance of radiation- tolerant design through components and design compliance testing. This availability of design-certified radiation-tolerant converters can significantly reduce total cost and delivery time for power converters for space applications that fit the appropriate DSCC classification (30 kRad).

  6. Converting Relational Database Into Xml Document

    Directory of Open Access Journals (Sweden)

    Kanagaraj.S

    2012-03-01

    Full Text Available XML (Extensible Markup Language is emerging and gradually accepted as the standard for data interchange in the Internet world. Interoperation of relational database and XML database involves schema and data translations. Through EER (extended entity relationship model can convert the schema of relational database into XML. The semantics of the relational database, captured in EER diagram, are mapped to XML schema using stepwise procedures and mapped to XML document under the definitions of the XML schema. Converting Relational Database into XML Document is a process of converting the existing databases into XML file format. Existing conversion techniques convert a single database into xml. The proposed approach performs the conversion of databases like Ms-Access, MS-SQL to XML file format. Read the tables information from the corresponding database and generate code for the appropriate databases and convert the tables into XML flat file format. This converted XML file is been presented to the user.

  7. Ocean floor mounting of wave energy converters

    Science.gov (United States)

    Siegel, Stefan G

    2015-01-20

    A system for mounting a set of wave energy converters in the ocean includes a pole attached to a floor of an ocean and a slider mounted on the pole in a manner that permits the slider to move vertically along the pole and rotate about the pole. The wave energy converters can then be mounted on the slider to allow adjustment of the depth and orientation of the wave energy converters.

  8. Development of a Modular Power Converter

    Science.gov (United States)

    Stepanov, A.; Biesenieks, L.; Sokolovs, A.; Galkin, I.

    2009-01-01

    This report describes the most important details of elaboration of a versatile power module that can be utilized as a part of various converters. Two or more modules connected together can form a frequency converter or multilevel converter or 3-phase inverter/rectifier etc. Initially the module was developed for fast prototyping of uninterruptible power supplies and energy systems with alternative energy sources. The module can be used also as a basis for laboratory equipment of the power electronics course.

  9. Regeneration of ZVS converter with Resonant inductor

    Directory of Open Access Journals (Sweden)

    J.Sivavara Prasad

    2011-09-01

    Full Text Available This paper presents an analysis of the regeneration of zero-voltage-switching converter with resonant inductor, quasi-resonant converters, and full-bridge zero-voltage-switched PWM Converter. The design of a clamping circuit considering a saturable resonant inductor is presented and compared with the design of a clamping circuit with a linear resonant inductor. A diode model with reverse recovery is employed to simulate the effects.

  10. Application of 12-bit A/D Converter ADS1286 in Temperature Detection%12位串行模/数转换器ADS1286在温度检测中的应用

    Institute of Scientific and Technical Information of China (English)

    毕金虎; 朴相范

    2011-01-01

    To achieve high-accuracy temperature detection, the micro power consumption analog-to-digital converter ADS1286 wit 12-bit resolution and microcontroller AT 89C2051 were employed for the design of the hardware and software in temperature collection secton of temperature detecting system. The temperature acquisition circuit was applied to the design of microheater in GPLPME apparatus, whose temperature detection range is 0~350℃ and temperature detection accuracy is up to ±0. 1 ℃. It is proved that the temperature acquisition circuit has high detecting accuracy, and works reliably and smoothly. It can be applied to the area of industry control and the intelligent instruments which have a demand of high-accuracy temperature detection.%为了实现对温度检测的高精度要求,利用12位分辨率的微功耗A/D转换芯片ADS1286,配合AT89C2051单片机,对温度检测系统中的温度采集部分进行了硬件和软件设计.将该温度采集电路应用在气流式液相微萃取仪微型加热器的设计中,检测温度范围在0~350℃之间,温度检测精度达到士0.1℃.实践证明,该温度采集电路测量精度高,工作可靠稳定,适用于工业测控领域及智能化仪器仪表中对温度检测提出高精度要求的应用场合.

  11. Fundamentals and hard-switching converters

    CERN Document Server

    Ioinovici, Adrian

    2013-01-01

    Volume 1 Fundamentals and Hard-switching Converters introduces the key challenges in power electronics from basic components to operation principles and presents classical hard- and soft-switching DC to DC converters, rectifiers and inverters. At a more advanced level, it provides comprehensive analysis of DC and AC models comparing the available approaches for their derivation and results. A full treatment of DC to DC hard-switching converters is given, from fundamentals to modern industrial solutions and practical engineering insight. The author elucidates various contradictions and misunderstandings in the literature, for example, in the treatment of the discontinuous conduction operation or in deriving AC small-signal models of converters.

  12. DC/DC Converter Stability Testing Study

    Science.gov (United States)

    Wang, Bright L.

    2008-01-01

    This report presents study results on hybrid DC/DC converter stability testing methods. An input impedance measurement method and a gain/phase margin measurement method were evaluated to be effective to determine front-end oscillation and feedback loop oscillation. In particular, certain channel power levels of converter input noises have been found to have high degree correlation with the gain/phase margins. It becomes a potential new method to evaluate stability levels of all type of DC/DC converters by utilizing the spectral analysis on converter input noises.

  13. Commutation Processes in Multiresonant ZVS Bridge Converter

    Directory of Open Access Journals (Sweden)

    Miroslaw Luft

    2008-01-01

    Full Text Available The analysis of the multiresonant ZVS DC/DC bridge converter is presented. The control system of the converter is basedon the method of frequency control at the constant time of transistor turn-off with a phase shift. The operation of the circuit is givenand the operating range of the converter is defined where ZVS switching operation is assured. Control characteristics are given andthe converter’s efficiency is defined. The circuit’s operation is analysed on the basis of results of the converter simulation tests using Simplorer programme.

  14. Reliability of Power Electronic Converter Systems

    DEFF Research Database (Denmark)

    -link capacitance in power electronic converter systems; wind turbine systems; smart control strategies for improved reliability of power electronics system; lifetime modelling; power module lifetime test and state monitoring; tools for performance and reliability analysis of power electronics systems; fault......-tolerant adjustable speed drive systems; mission profile oriented reliability design in wind turbine and photovoltaic systems; reliability of power conversion systems in photovoltaic applications; power supplies for computers; and high-power converters. Reliability of Power Electronic Converter Systems is essential...... reading for researchers, professionals and students working with power electronics and their applications, particularly those specializing in the development and application of power electronic converters and systems....

  15. An 18-bit high performance audio {sigma}-{Delta} D/A converter

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Hao; Han Yan; Han Xiaoxia; Wang Hao; Liang Guo [Institute of Microelectronics and Photoelectronics, Zhejiang University, Hangzhou 310027 (China); Huang Xiaowei [CISD, Institute of Microelectronic CAD, Hangzhou 310018 (China); Cheung, Ray C., E-mail: huangxw@hdu.edu.c [Department of Electronic Engineering, City University of Hong Kong (Hong Kong)

    2010-07-15

    A multi-bit quantized high performance sigma-delta ({sigma}-{Delta}) audio DAC is presented. Compared to its single-bit counterpart, the multi-bit quantization offers many advantages, such as simpler {sigma}-{Delta} modulator circuit, lower clock frequency and smaller spurious tones. With the data weighted average (DWA) mismatch shaping algorithm, element mismatch errors induced by multi-bit quantization can be pushed out of the signal band, hence the noise floor inside the signal band is greatly lowered. To cope with the crosstalk between digital and analog circuits, every analog component is surrounded by a guard ring, which is an innovative attempt. The 18-bit DAC with the above techniques, which is implemented in a 0.18 {mu}m mixed-signal CMOS process, occupies a core area of 1.86 mm{sup 2}. The measured dynamic range (DR) and peak SNDR are 96 dB and 88 dB, respectively.

  16. Multilevel converters for 10 MW Wind Turbines

    DEFF Research Database (Denmark)

    Ma, Ke; Blaabjerg, Frede

    2011-01-01

    Several promising multi-level converter configurations for 10 MW Wind Turbines both with direct drive and one-stage gear box drive using Permanent Magnet Synchronous Generator (PMSG) are proposed, designed and compared. Reliability is a crucial indicator for large scale wind power converters...

  17. Present trends in HVDC converter station design

    Energy Technology Data Exchange (ETDEWEB)

    Carlsson, Lennart; Asplund, Gunnar; Bjorklund, Hans; Flisberg, Gunnar [ABB Power Systems AB, Ludvika (Sweden)

    1994-12-31

    HVDC converter station technology has developed rapidly to satisfy increasing requirements during past 10 - 15 years, but there has not been any dramatic changes since thyristor valves were introduced in the mid 70s. This paper describes some recent and expected future developments, that will substantiality change and simplify future converter stations. (author) 4 refs., 7 figs.

  18. High-Efficiency dc/dc Converter

    Science.gov (United States)

    Sturman, J.

    1982-01-01

    High-efficiency dc/dc converter has been developed that provides commonly used voltages of plus or minus 12 Volts from an unregulated dc source of from 14 to 40 Volts. Unique features of converter are its high efficiency at low power level and ability to provide output either larger or smaller than input voltage.

  19. Power Converters Secure Electronics in Harsh Environments

    Science.gov (United States)

    2013-01-01

    In order to harden power converters for the rigors of space, NASA awarded multiple SBIR contracts to Blacksburg, Virginia-based VPT Inc. The resulting hybrid DC-DC converters have proven valuable in aerospace applications, and as a result the company has generated millions in revenue from the product line and created four high-tech jobs to handle production.

  20. High Precision Current Measurement for Power Converters

    CERN Document Server

    Cerqueira Bastos, M

    2015-01-01

    The accurate measurement of power converter currents is essential to controlling and delivering stable and repeatable currents to magnets in particle accelerators. This paper reviews the most commonly used devices for the measurement of power converter currents and discusses test and calibration methods.

  1. Input-output rearrangement of isolated converters

    DEFF Research Database (Denmark)

    Madsen, Mickey Pierre; Kovacevic, Milovan; Mønster, Jakob Døllner;

    2015-01-01

    is not a requirement. The proposed technique is particularly valuable in power conversion at very high frequencies, and may be combined with other stress reduction methods. Finally, the new arrangements are experimentally verified both on off the shelf converters and on a VHF resonant SEPIC converter. All results...

  2. Modeling and Simulation of Matrix Converter

    DEFF Research Database (Denmark)

    Liu, Fu-rong; Klumpner, Christian; Blaabjerg, Frede

    2005-01-01

    This paper discusses the modeling and simulation of matrix converter. Two models of matrix converter are presented: one is based on indirect space vector modulation and the other is based on power balance equation. The basis of these two models is• given and the process on modeling is introduced...

  3. A Low Cost BLE Transceiver with RX Matching Network Reusing PA Load Inductor for WSNs Applications

    Science.gov (United States)

    Liang, Zhen; Li, Bin; Huang, Mo; Zheng, Yanqi; Ye, Hui; Xu, Ken; Deng, Fangming

    2017-01-01

    In this work, a low cost Bluetooth Low Energy (BLE) transceiver for wireless sensor network (WSN) applications, with a receiver (RX) matching network reusing power amplifier (PA) load inductor, is presented. In order to decrease the die area, only two inductors were used in this work. Besides the one used in the voltage control oscillator (VCO), the PA load inductor was reused as the RX impedance matching component in the front-end. Proper controls have been applied to achieve high transmitter (TX) input impedance when the transceiver is in the receiving mode, and vice versa. This allows the TRX-switch/matching network integration without significant performance degradation. The RX adopted a low-IF structure and integrated a single-ended low noise amplifier (LNA), a current bleeding mixer, a 4th complex filter and a delta-sigma continuous time (CT) analog-to-digital converter (ADC). The TX employed a two-point PLL-based architecture with a non-linear PA. The RX achieved a sensitivity of −93 dBm and consumes 9.7 mW, while the TX achieved a 2.97% error vector magnitude (EVM) with 9.4 mW at 0 dBm output power. This design was fabricated in a 0.11 μm complementary metal oxide semiconductor (CMOS) technology and the front-end circuit only occupies 0.24 mm2. The measurement results verify the effectiveness and applicability of the proposed BLE transceiver for WSN applications. PMID:28422068

  4. A Wireless FSCV Monitoring IC with Analog Background Subtraction and UWB Telemetry

    Science.gov (United States)

    Dorta-Quiñones, Carlos I.; Wang, Xiao Y.; Dokania, Rajeev K.; Gailey, Alycia; Lindau, Manfred; Apsel, Alyssa B.

    2015-01-01

    A 30-μW wireless fast-scan cyclic voltammetry monitoring integrated circuit for ultra-wideband (UWB) transmission of dopamine release events in freely-behaving small animals is presented. On-chip integration of analog background subtraction and UWB telemetry yields a 32-fold increase in resolution versus standard Nyquist-rate conversion alone, near a four-fold decrease in the volume of uplink data versus single-bit, third-order, delta-sigma modulation, and more than a 20-fold reduction in transmit power versus narrowband transmission for low data rates. The 1.5-mm2 chip, which was fabricated in 65-nm CMOS technology, consists of a low-noise potentiostat frontend, a two-step analog-to-digital converter (ADC), and an impulse-radio UWB transmitter (TX). The duty-cycled frontend and ADC/UWB-TX blocks draw 4 μA and 15 μA from 3-V and 1.2-V supplies, respectively. The chip achieves an input-referred current noise of 92 pArms and an input current range of ±430 nA at a conversion rate of 10 kHz. The packaged device operates from a 3-V coin-cell battery, measures 4.7 × 1.9 cm2, weighs 4.3 g (including the battery and antenna), and can be carried by small animals. The system was validated by wirelessly recording flow-injection of dopamine with concentrations in the range of 250 nM to 1 μM with a carbon-fiber microelectrode (CFM) using 300-V/s FSCV. PMID:26057983

  5. A Wireless FSCV Monitoring IC With Analog Background Subtraction and UWB Telemetry.

    Science.gov (United States)

    Dorta-Quiñones, Carlos I; Wang, Xiao Y; Dokania, Rajeev K; Gailey, Alycia; Lindau, Manfred; Apsel, Alyssa B

    2016-04-01

    A 30-μW wireless fast-scan cyclic voltammetry monitoring integrated circuit for ultra-wideband (UWB) transmission of dopamine release events in freely-behaving small animals is presented. On-chip integration of analog background subtraction and UWB telemetry yields a 32-fold increase in resolution versus standard Nyquist-rate conversion alone, near a four-fold decrease in the volume of uplink data versus single-bit, third-order, delta-sigma modulation, and more than a 20-fold reduction in transmit power versus narrowband transmission for low data rates. The 1.5- mm(2) chip, which was fabricated in 65-nm CMOS technology, consists of a low-noise potentiostat frontend, a two-step analog-to-digital converter (ADC), and an impulse-radio UWB transmitter (TX). The duty-cycled frontend and ADC/UWB-TX blocks draw 4 μA and 15 μA from 3-V and 1.2-V supplies, respectively. The chip achieves an input-referred current noise of 92 pA(rms) and an input current range of ±430 nA at a conversion rate of 10 kHz. The packaged device operates from a 3-V coin-cell battery, measures 4.7 × 1.9 cm(2), weighs 4.3 g (including the battery and antenna), and can be carried by small animals. The system was validated by wirelessly recording flow-injection of dopamine with concentrations in the range of 250 nM to 1 μM with a carbon-fiber microelectrode (CFM) using 300-V/s FSCV.

  6. A Low Cost Bluetooth Low Energy Transceiver for Wireless Sensor Network Applications with a Front-end Receiver-Matching Network-Reusing Power Amplifier Load Inductor.

    Science.gov (United States)

    Liang, Zhen; Li, Bin; Huang, Mo; Zheng, Yanqi; Ye, Hui; Xu, Ken; Deng, Fangming

    2017-04-19

    In this work, a low cost Bluetooth Low Energy (BLE) transceiver for wireless sensor network (WSN) applications, with a receiver (RX)-matching network-reusing power amplifier (PA) load inductor, is presented. In order to decrease the die area, only two inductors were used in this work. Besides the one used in the voltage control oscillator (VCO), the PA load inductor was reused as the RX impedance matching component in the front-end. Proper controls have been applied to achieve high transmitter (TX) input impedance when the transceiver is in the receiving mode, and vice versa. This allows the TRX-switch/matching network integration without significant performance degradation. The RX adopted a low-IF structure and integrated a single-ended low noise amplifier (LNA), a current bleeding mixer, a 4th complex filter and a delta-sigma continuous time (CT) analog-to-digital converter (ADC). The TX employed a two-point PLL-based architecture with a non-linear PA. The RX achieved a sensitivity of -93 dBm and consumes 9.7 mW, while the TX achieved a 2.97% error vector magnitude (EVM) with 9.4 mW at 0 dBm output power. This design was fabricated in a 0.11 μm complementary metal oxide semiconductor (CMOS) technology and the front-end circuit only occupies 0.24 mm². The measurement results verify the effectiveness and applicability of the proposed BLE transceiver for WSN applications.

  7. Radiation Effects on DC-DC Converters

    Science.gov (United States)

    Zhang, De-Xin; AbdulMazid, M. D.; Attia, John O.; Kankam, Mark D. (Technical Monitor)

    2001-01-01

    In this work, several DC-DC converters were designed and built. The converters are Buck Buck-Boost, Cuk, Flyback, and full-bridge zero-voltage switched. The total ionizing dose radiation and single event effects on the converters were investigated. The experimental results for the TID effects tests show that the voltages of the Buck Buck-Boost, Cuk, and Flyback converters increase as total dose increased when using power MOSFET IRF250 as a switching transistor. The change in output voltage with total dose is highest for the Buck converter and the lowest for Flyback converter. The trend of increase in output voltages with total dose in the present work agrees with those of the literature. The trends of the experimental results also agree with those obtained from PSPICE simulation. For the full-bridge zero-voltage switch converter, it was observed that the dc-dc converter with IRF250 power MOSFET did not show a significant change of output voltage with total dose. In addition, for the dc-dc converter with FSF254R4 radiation-hardened power MOSFET, the output voltage did not change significantly with total dose. The experimental results were confirmed by PSPICE simulation that showed that FB-ZVS converter with IRF250 power MOSFET's was not affected with the increase in total ionizing dose. Single Event Effects (SEE) radiation tests were performed on FB-ZVS converters. It was observed that the FB-ZVS converter with the IRF250 power MOSFET, when the device was irradiated with Krypton ion with ion-energy of 150 MeV and LET of 41.3 MeV-square cm/mg, the output voltage increased with the increase in fluence. However, for Krypton with ion-energy of 600 MeV and LET of 33.65 MeV-square cm/mg, and two out of four transistors of the converter were permanently damaged. The dc-dc converter with FSF254R4 radiation hardened power MOSFET's did not show significant change at the output voltage with fluence while being irradiated by Krypton with ion energy of 1.20 GeV and LET of 25

  8. Modelling, analyses and design of switching converters

    Science.gov (United States)

    Cuk, S. M.; Middlebrook, R. D.

    1978-01-01

    A state-space averaging method for modelling switching dc-to-dc converters for both continuous and discontinuous conduction mode is developed. In each case the starting point is the unified state-space representation, and the end result is a complete linear circuit model, for each conduction mode, which correctly represents all essential features, namely, the input, output, and transfer properties (static dc as well as dynamic ac small-signal). While the method is generally applicable to any switching converter, it is extensively illustrated for the three common power stages (buck, boost, and buck-boost). The results for these converters are then easily tabulated owing to the fixed equivalent circuit topology of their canonical circuit model. The insights that emerge from the general state-space modelling approach lead to the design of new converter topologies through the study of generic properties of the cascade connection of basic buck and boost converters.

  9. Qualitative model of a plasma photoelectric converter

    Science.gov (United States)

    Gorbunov, N. A.; Flamant, G.

    2009-01-01

    A converter of focused optical radiation into electric current is considered on the basis of the photovoltaic effect in plasmas. The converter model is based on analysis of asymmetric spatial distributions of charge particle number density and ambipolar potential in the photoplasma produced by external optical radiation focused in a heat pipe filled with a mixture of alkali vapor and a heavy inert gas. Energy balance in the plasma photoelectric converter is analyzed. The conditions in which the external radiation energy is effectively absorbed in the converter are indicated. The plasma parameters for which the energy of absorbed optical radiation is mainly spent on sustaining the ambipolar field in the plasma are determined. It is shown that the plasma photoelectric converter makes it possible to attain a high conversion efficiency for focused solar radiation.

  10. Transformer Isolated Buck-Boost Converters

    Directory of Open Access Journals (Sweden)

    Barry W. Williams

    2016-12-01

    Full Text Available Of the single-switch dc-to-dc converters, those with the buck-boost voltage transfer function offer most potential for transformer coupling, hence isolation, at the kilowatt level. This paper highlights the limitations of the traditional magnetic coupled, buck-boost topology. Then four split-capacitor transformer-coupled topologies (specifically the Cuk, sepic, zeta, and a new, converters with a common ac equivalent circuit are explored, that do not temporarily store core magnetic energy as does the traditional isolated buck-boost converter nor have a core dc magnetizing current bias, as with the sepic and zeta transformer coupled topologies. Core dc bias capacitive voltage compensation is a practical design constraint in three of the four topologies, while all four must cater for stray and leakage inductance effects. Simulations and experimental results for the new converter at 408W support the transformer-coupled, single-switch dc-to-dc converter concepts investigated.

  11. Periodic Control of Power Electronic Converters

    DEFF Research Database (Denmark)

    Zhou, Keliang; Danwei, Wang; Yang, Yongheng

    Advanced power electronic converters convert, control and condition electricity. Power converters require control strategies for periodic signal compensation to assure good power quality and stable power system operation. This comprehensive text presents the most recent internal model principle...... based periodic control technology, which offers the perfect periodic control solution for power electronic conversion. It also provides complete analysis and synthesis methods for periodic control systems, and plenty of practical examples to demonstrate the validity of proposed periodic control...... technology for power converters. It proposes a unified framework for housing periodic control schemes for power converters, and provides a general proportional-integral-derivative control solution to periodic signal compensation in extensive engineering applications. Periodic Control of Power Electronic...

  12. SPECTRAL ANALYSIS OF BUCK AND SEPIC CONVERTERS

    Directory of Open Access Journals (Sweden)

    CHAKIB ALAOUI

    2011-02-01

    Full Text Available Switched mode power converters generate harmonic currents, which will be injected into the utility grid, causing distortion of the utility waveform. They also become a source for the generation of EMI, which may affect the communication systems. This work is about the design and evaluation of the two most frequently used SMPS used in step down mode of operation: the Buck converter and the Sepic converter working in step-down mode of operation. These converters were designed using optimized equations for their components ratings. Simulation results show that although the Buck output voltage is low in harmonics, it has high harmonic contents in currents circulating in its inductor and diode, and hence requires strong filtering. The Sepic converterhas lower harmonic contents than the Buck converter.

  13. A novel power converter for photovoltaic applications

    Science.gov (United States)

    Yuvarajan, S.; Yu, Dachuan; Xu, Shanguang

    A simple and economical power conditioner to convert the power available from solar panels into 60 Hz ac voltage is described. The raw dc voltage from the solar panels is converted to a regulated dc voltage using a boost converter and a large capacitor and the dc output is then converted to 60 Hz ac using a bridge inverter. The ratio between the load current and the short-circuit current of a PV panel at maximum power point is nearly constant for different insolation (light) levels and this property is utilized in designing a simple maximum power point tracking (MPPT) controller. The controller includes a novel arrangement for sensing the short-circuit current without disturbing the operation of the PV panel and implementing MPPT. The switching losses in the inverter are reduced by using snubbers. The results obtained on an experimental converter are presented.

  14. PERFORMANCE ANALYSIS OF 2D CONVERTER BY COMBINING SR & KY CONVERTERS

    Directory of Open Access Journals (Sweden)

    V. Manoj Kumar

    2014-03-01

    Full Text Available Most of the portable equipments use battery as power source. The increasing use of low voltage portable devices and growing requirements of functionalities embedded into such devices. Thus an efficient power management technique is needed for longer battery life for them. Highly variable nature of batteries systems often require supply voltages to be both higher and lower than the battery. This is most efficiently generated by a buck-boost switching converter. But here the converter efficiency is decreased since the power loss occurs in the storage devices. Step by step, process of designing, feedback control and simulation of a novel voltage-buck boost converter, combining KY and synchronous Rectifier buck converter for battery power applications. Unlike the traditional buck–boost converter, this converter has the positive output voltage and system is stable, different from the negative output voltage and low stable of the traditional inverting buck–boost converters. Since such a converter operates in continuous conduction mode. Also it possesses the non-pulsating output current, thereby not only decreasing the current stress on the output capacitor but also reducing the output voltage ripple. Both the KY converter and the synchronous buck converter, combined into a positive buck– boost converter, uses the same power switches. Here it makes the circuit to be compact and the corresponding cost to be down. Voltage conversion ratio is 2D,so it is also called 2D converter.

  15. The GANDALF 128-Channel Time-to-Digital Converter

    CERN Document Server

    Büchele, Maximilian; Herrmann, Florian; Königsmann, Kay; Schill, Christian; Schopferer, Sebastian

    2011-01-01

    The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an employment of the system in very different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition or fast trigger generation. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In this concept each input signal is continuously sampled by 16 flip-flops using equidistant phase-shifted clocks. Compared to previous FPGA designs, usually based on delay lines and comprising few TDC channels with resolutions in the order of 10 ps, our design permits the implementation of a large number of TDC channels with a resolution of 64 ps in a single FPGA. Predictable placement of logic components and uniform routing inside the FPGA fabr...

  16. Electromagnetic Compatibility of Matrix Converter System

    Directory of Open Access Journals (Sweden)

    S. Fligl

    2006-12-01

    Full Text Available The presented paper deals with matrix converters pulse width modulation strategies design with emphasis on the electromagnetic compatibility. Matrix converters provide an all-silicon solution to the problem of converting AC power from one frequency to another, offering almost all the features required of an ideal static frequency changer. They possess many advantages compared to the conventional voltage or current source inverters. A matrix converter does not require energy storage components as a bulky capacitor or an inductance in the DC-link, and enables the bi-directional power flow between the power supply and load. The most of the contemporary modulation strategies are able to provide practically sinusoidal waveforms of the input and output currents with negligible low order harmonics, and to control the input displacement factor. The perspective of matrix converters regarding EMC in comparison with other types of converters is brightly evident because it is no need to use any equipment for power factor correction and current and voltage harmonics reduction. Such converter with proper control is properly compatible both with the supply mains and with the supplied load. A special digital control system was developed for the realized experimental test bed which makes it possible to achieve greater throughput of the digital control system and its variability.

  17. Underwater noise from a wave energy converter

    DEFF Research Database (Denmark)

    Tougaard, Jakob

    A recent addition to the anthropogenic sources of underwater noise is offshore wave energy converters. Underwater noise was recorded from the Wavestar wave energy converter located at Hastholm, Denmark (57°7.73´N, 8°37.23´E). The Wavestar is a full-scale test and demonstration converter...... in full operation and start and stop of the converter. Median broad band (10 Hz – 20 kHz) sound pressure level (Leq) was 123 dB re. 1 Pa, irrespective of status of the wave energy converter (stopped, running or starting/stopping). The most pronounced peak in the third-octave spectrum was in the 160 Hz...... significant noise above ambient could be detected above the 250 Hz band. The absolute increase in noise above ambient was very small. L50 third-octave levels in the four bands with the converter running were thus only 1-2 dB above ambient L50 levels. The noise recorded 25 m from the wave energy converter...

  18. Propagation characteristics of converted refracted wave and its application in static correction of converted wave

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    Three-component seismic exploration through P-wave source and three-component geophone is an effective technique used in complicated reservoir exploration. In three-component seismic exploration data processing,one of the difficulties is static correction of converted wave. This paper analyzes propagation characteristics of non-converted and converted refracted waves,and discovers a favor-able condition for the formation of converted refracted wave,i.e. the velocity of overlaying medium S wave is much lower than that of underlying medium S wave. In addition,the paper proposes the static correction method of converted wave based on PPS converted refracted wave,and processes the real three-component seismic data with better results of static correction of converted wave.

  19. High-power converters and AC drives

    CERN Document Server

    Wu, Bin

    2017-01-01

    This new edition reflects the recent technological advancements in the MV drive industry, such as advanced multilevel converters and drive configurations. It includes three new chapters, Control of Synchronous Motor Drives, Transformerless MV Drives, and Matrix Converter Fed Drives. In addition, there are extensively revised chapters on Multilevel Voltage Source Inverters and Voltage Source Inverter-Fed Drives. This book includes a systematic analysis on a variety of high-power multilevel converters, illustrates important concepts with simulations and experiments, introduces various megawatt drives produced by world leading drive manufacturers, and addresses practical problems and their mitigations methods.

  20. Selective harmonic control for power converters

    DEFF Research Database (Denmark)

    Zhou, Keliang; Yang, Yongheng; Blaabjerg, Frede;

    2014-01-01

    This paper proposes an Internal Model Principle (IMP) based Selective Harmonic Controller (SHC) for power converters. The proposed SHC offers an optimal control solution for power converters to mitigate power harmonics. It makes a good trade-off among cost, complexity and performance. It has high...... accuracy and fast transient response, and it is cost-effective, easy for real-time implementation, and compatible for design rules-of-thumb. An application on a three-phase PWM converter has confirmed the effectiveness of the proposed control scheme in terms of harmonic mitigation....

  1. New PWM switched-mode converter topologies

    Science.gov (United States)

    Hua, Gui-Chao; Huang, Shi-Peng

    Two augmented switching cells are proposed from which four novel topologies can be derived: an augmented buck converter, an augmented boost converter, a novel switching power amplifier, and a novel switching controlled rectifier. The augmented buck and the augmented boost converters realize higher step-down and step-up ratios, respectively, under a given switch duty ratio by proper design of the turn ratios of the transformer and coupled inductor. The switching power amplifier achieves four-quadrant output by the use of two bidirectional current switches and a single power supply, while the inverse converter can be used as a switching controlled rectifier. The experimental verification of the power amplifier is presented.

  2. "Forback" Dc-To-Dc Converters

    Science.gov (United States)

    Lukemire, Alan T.

    1992-01-01

    Dc-to-dc power-converter circuits called "forback" resemble circuits of standard configurations called "forward", "flyback", and "Cuk". Circuit employs minor modifications to existing topologies, combines advantages, while eliminating disadvantages, of older circuits.

  3. A three-port direct current converter

    DEFF Research Database (Denmark)

    2016-01-01

    The three-port direct current converter comprising: at least one input direct current source; at least one storage battery; a primary side circuit; a secondary side circuit; a first single magnetic component shared by the primary side circuit and the secondary side circuit, wherein the primary side...... circuit comprises a connection between the at least one input direct current source and the at least one storage battery, the primary side circuit configured for operating as a buck converter; a second magnetic component serially coupled to the first single magnetic component, wherein the first and second...... magnetic components are configured to perform a voltage step-up, wherein the secondary side circuit comprises a connection between the at least one storage battery and at least one load, the secondary side configured for operating as a tapped boost converter; wherein the three-port direct current converter...

  4. Interface of magnetoresistive converter of active power

    Directory of Open Access Journals (Sweden)

    A. I. Vytiaganets

    2009-10-01

    Full Text Available The vehicle and programmatic interfaces of magnetoresistive converter of active power are considered, the results of statistical treatment of the multiple measuring of active-power are analysed.

  5. Catalytic converters as a source of platinum

    Directory of Open Access Journals (Sweden)

    A. Fornalczyk

    2011-10-01

    Full Text Available The increase of Platinum Group Metals demand in automotive industry is connected with growing amount of cars equipped with the catalytic converters. The paper presents the review of available technologies during recycling process. The possibility of removing platinum from the used catalytic converters applying pyrometallurgical and hyrdometallurgical methods were also investigated. Metals such as Cu, Pb, Ca, Mg, Cd were used in the pyrometallurgical research (catalytic converter was melted with Cu, Pb and Ca or Mg and Cd vapours were blown through the whole carrier. In hydrometallurgical research catalytic converters was dissolved in aqua regia. Analysis of Pt contents in the carrier before and after the process was performed by means of atomic absorption spectroscopy. Obtained result were discussed.

  6. Reliability of power electronic converter systems

    CERN Document Server

    Chung, Henry Shu-hung; Blaabjerg, Frede; Pecht, Michael

    2016-01-01

    This book outlines current research into the scientific modeling, experimentation, and remedial measures for advancing the reliability, availability, system robustness, and maintainability of Power Electronic Converter Systems (PECS) at different levels of complexity.

  7. State estimation for wave energy converters

    Energy Technology Data Exchange (ETDEWEB)

    Bacelli, Giorgio; Coe, Ryan Geoffrey

    2017-04-01

    This report gives a brief discussion and examples on the topic of state estimation for wave energy converters (WECs). These methods are intended for use to enable real-time closed loop control of WECs.

  8. New design trends in photovoltaic converters

    OpenAIRE

    Van den Bossche, Alex

    2013-01-01

    The reason to look at new trends in PV converters is that, in the total cost of ownership the converter is more expensive than the PV panel. Another trend is that one uses them without transformer to increase efficiency, but one has to take into account safety. One can increase the switching frequency and at the same time reducing the switching losses using SiC components, but still good cost effective solutions can be made with Si-IGBTs.

  9. Industrial application, 1MHz, quasi resonant converter

    OpenAIRE

    Carrasco Solís, Juan Manuel; Pérez Ridao, Francisco; Quero Reboul, José Manuel; Janer Jiménez, Carlos; García Franquelo, Leopoldo

    1993-01-01

    An industrial multi-output QRC converter is presented. Its main designing constraints are low cost, small in size, reduced EMI and EMC, high efficiency and severe dynamic behaviour in all outputs. Accomplishing this last restriction proved to be a difficult task. This has been done by means of a classical controller and cross regulation. The actual performance was tested on a 1MHz prototype rated at 50W. The low cost developed converter is characterized by its simplicity of design and operati...

  10. AC – AC Converters for UPS

    Directory of Open Access Journals (Sweden)

    Rusalin Lucian R. Păun

    2008-05-01

    Full Text Available This paper propose a new control technique forsingle – phase AC – AC converters used for a on-line UPSwith a good dynamic response, a reduced-partscomponents, a good output characteristic, a good powerfactorcorrection(PFC. This converter no needs anisolation transformer. A power factor correction rectifierand an inverter with the proposed control scheme has beendesigned and simulated using Caspoc2007, validating theconcept.

  11. Switching power converters medium and high power

    CERN Document Server

    Neacsu, Dorin O

    2013-01-01

    An examination of all of the multidisciplinary aspects of medium- and high-power converter systems, including basic power electronics, digital control and hardware, sensors, analog preprocessing of signals, protection devices and fault management, and pulse-width-modulation (PWM) algorithms, Switching Power Converters: Medium and High Power, Second Edition discusses the actual use of industrial technology and its related subassemblies and components, covering facets of implementation otherwise overlooked by theoretical textbooks. The updated Second Edition contains many new figures, as well as

  12. Local Bifurcations in DC-DC Converters

    OpenAIRE

    2012-01-01

    Three local bifurcations in DC-DC converters are reviewed. They are period-doubling bifurcation, saddle-node bifurcation, and Neimark bifurcation. A general sampled-data model is employed to study the types of loss of stability of the nominal (periodic) solution and their connection with local bifurcations. More accurate prediction of instability and bifurcation than using the averaging approach is obtained. Examples of bifurcations associated with instabilities in DC-DC converters are given.

  13. LHC Power Converters: A Precision Game

    CERN Multimedia

    2001-01-01

    The LHC test-bed, String 2, is close to commissioning and one important element to get a first chance to prove what it can do is the power converter system. In String 2 there are 16 converters, in the full LHC there will be almost 1800. This article takes a look at what is so special about the power converters for the LHC. The 13 000 Amps power converters with the watercooled cables going to the String 2 feedboxes. The LHC's superconducting magnets will be the pinnacle of high technology. But to work, they'll need the help of high-precision power converters to supply them with extremely stable DC current. Perfection will be the name of the game, with an accuracy of just 1-2 parts per million (ppm) required. LEP, for the sake of comparison, could live with 10-20 ppm. The LHC's power converters will be very different from those of LEP or the SPS since the new accelerator's magnets are mostly superconducting. That means that they require much higher currents at a lower voltage since superconductors have no re...

  14. Low arc drop hybrid mode thermionic converter

    Science.gov (United States)

    Shimada, K.

    1977-01-01

    The hybrid mode operation for the reduction of plasma drops is being investigated. This report discusses the results obtained from two molybdenum emitter converters. One converter had a molybdenum collector and the other a nickel collector. The molybdenum collector converter was operated in a hybrid mode (at an interelectrode distance of 1.7 mm) and produced a minimum barrier index of 1.96 eV at an emitter temperature of 1500 K. The arc drop was calculated to be 0.14 eV, using the published results for a molybdenum collector. On the other hand, the nickel collector converter was operated in a conventional ignited mode (at an interelectrode distance of 0.5 mm) and produced a minimum barrier index of 2.1 eV at an emitter temperature of 1700 K. It is tentatively concluded that a large-gap operation of the hybrid mode converter permits the diffusion of cesium ions to a distance in the order of one millimeter for an effective neutralization of electron space charge. By employing a low work function collector (1.55 eV) in a hybrid mode converter with an arc drop of 0.14 eV, it appears that a barrier index as low as 1.69 eV could be achieved.

  15. Simulation of Multi output Fly back Converter with Integrated Auxiliary Buck Converter with reduced components

    Directory of Open Access Journals (Sweden)

    J.KOMATHI

    2015-04-01

    Full Text Available The fly back converter has been widely used for multi outputs due to the simple structure and low cost in low-power applications. This paper presents a new multi output converter. It consists of a half-bridge inverter with boost converter in primary side and a fly back rectifier that is integrated with an auxiliary buck converter in secondary side. The boost converter is used to generate high voltage dc from Low voltage PV cells. The primary switches control the main output voltage and the secondary synchronous switches control the auxiliary output voltage. The main advantages of the proposed converter are that the transformer size can be reduced due to the less magnetizing offset current, all the power switches including synchronous ones can achieve the zero-voltage switching (ZVS and it has no output cross regulation problems. The circuit is simulated using MATLAB. The performance is verified with simulation results.

  16. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming...

  17. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital...

  18. Rad-Hard Sigma-Delta 3-channel ADC for Fluxgate Magnetometers Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposed project aims to develop a multi-channel analog to digital converter (ADC) required for a fluxgate magnetometer (EPD) employed on NASA's planetary...

  19. High Performance ADC for Reconfigurable/Reprogrammable Communication Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will develop a 3X improvement in sampling resolution over current state-of-the art analog-to-digital converter (ADC) technology to support...

  20. Analysis of parallel optical sampling rate and ADC requirements in digital coherent receivers

    DEFF Research Database (Denmark)

    Lorences Riesgo, Abel; Galili, Michael; Peucheret, Christophe

    2012-01-01

    We comprehensively assess analog-to-digital converter requirements in coherent digital receiver schemes with parallel optical sampling. We determine the electronic requirements in accordance with the properties of the free running local oscillator....

  1. A Sea Floor Penetrometer.

    Science.gov (United States)

    processed through an analog-to-digital (A/D) converter, and stored in the memory of a mini-computer. Computer algorithms are applied to the deceleration data to provide real-time sea floor classification.

  2. Low Power 1-Bit ADC Array with Serial Output Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Microwave interferometers for NASA missions such as PATH and SCLP consist of up to 900 receivers. Each receiver requires I and Q ADCs (analog-to-digital converters)...

  3. Extremelly High Bandwidth Rad Hard Data Acquisition System Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Analog-to-digital converters (ADCs) are the key components for digitizing high-speed analog data in modern data acquisition systems, which is a critical part of...

  4. SiGe 130 nm-based Rad-Hard ADC for the JEO Mission Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop will demonstrate the feasibility of developing a radiation-hardened analog-to-digital converter (ADC) suitable for the Jupiter Europa Orbiter mission. This...

  5. Materials technology for Stirling space power converters

    Science.gov (United States)

    Baggenstoss, William; Mittendorf, Donald

    1992-01-01

    This program was conducted in support of the NASA LeRC development of the Stirling power converter (SPC) for space power applications. The objectives of this contract were: (1) to perform a technology review and analyses to support the evaluation of materials issues for the SPC; (2) to evaluate liquid metal compatibility issues of the SPC; (3) to evaluate and define a transient liquid phase diffusion bonding (TLPDB) process for the SPC joints to the Udimet 720 heater head; and (4) to evaluate alternative (to the TLPDB) joining techniques. In the technology review, several aspects of the current Stirling design were examined including the power converter assembly process, materials joining, gas bearings, and heat exchangers. The supporting analyses included GLIMPS power converter simulation in support of the materials studies, and system level analysis in support of the technology review. The liquid metal compatibility study evaluated process parameters for use in the Stirling power converter. The alternative joining techniques study looked at the applicability of various joining techniques to the Stirling power converter requirements.

  6. Efficiency of Thermionic and Thermoelectric Converters

    Science.gov (United States)

    Gerstenmaier, York Christian; Wachutka, Gerhard

    2007-02-01

    Thermoelectric and thermionic converters — also in micro- and nano-meter design — are considered for power generation and cooling applications. The potential of thermionic vacuum gap converters is investigated precisely by a new advanced theory with inclusion of backward currents from the 2nd electrode, losses due to thermal radiation and ohmic resistance in the electrodes, tunneling through the gap, image forces, and space charge effects. The efficiency of nano-meter gap thermionic converters is by far higher than for thermoelectric devices (including nano-structured superlattices) for operating temperatures above 800°K, however, there is no chance of realization with today's technology. For a vacuum gap width of about 1 μm the performance is higher than for hypothetical bulk- thermoelectric generators (TEGs) with ZT = 1 for T > 1000°K and also higher than for hypothetical nano-structured superlattices (ZT = 2.4) for T > 1200°K. A thermionic converter with gap width of 5μm has lower performance than a TEG with ZT = 1, however, also operates at T > 1200°K. Reasonable performance of thermionic converters at T ⩽ 500°K necessitates materials with workfunctions ⩽ 0.5 eV.

  7. A linear temperature-to-frequency converter

    DEFF Research Database (Denmark)

    Løvborg, Leif

    1965-01-01

    The possibility of converting temperature into a frequency signal by means of a thermistor which is part of the frequency-determining network of an RC oscillator is investigated. It is shown that a temperature - frequency characteristic which has a point of inflection may be realized, and that th......The possibility of converting temperature into a frequency signal by means of a thermistor which is part of the frequency-determining network of an RC oscillator is investigated. It is shown that a temperature - frequency characteristic which has a point of inflection may be realized......, and that the maximum value of the temperature-frequency coefficient beta in this point is-1/3 alpha, where a is the temperature coefficient of the thermistor at the corresponding temperature. Curves showing the range in which the converter is expected to be linear to within plusmn0.1 degC are given. A laboratory...

  8. Converters for Distributed Power Generation Systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Yang, Yongheng

    2015-01-01

    Power electronics technology has become the enabling technology for the integration of distributed power generation systems (DPGS) such as offshore wind turbine power systems and commercial photovoltaic power plants. Depending on the applications, a vast array of DPGS-based power converter...... presents an overview of the power converters for the DPGS, mainly based on wind turbine systems and photovoltaic systems, covering a wide range of applications. Moreover, the modulation schemes and interfacing power filters for the power converters are also exemplified. Finally, the general control...... topologies has been developed and more are coming into the market in order to achieve an efficient and reliable power conversion from the renewables. In addition, stringent demands from both the distribution system operators and the consumers have been imposed on the renewable-based DPGS. This article...

  9. CMOS Integrated Capacitive DC-DC Converters

    CERN Document Server

    Van Breussegem, Tom

    2013-01-01

    This book provides a detailed analysis of all aspects of capacitive DC-DC converter design: topology selection, control loop design and noise mitigation. Readers will benefit from the authors’ systematic overview that starts from the ground up, in-depth circuit analysis and a thorough review of recently proposed techniques and design methodologies.  Not only design techniques are discussed, but also implementation in CMOS is shown, by pinpointing the technological opportunities of CMOS and demonstrating the implementation based on four state-of-the-art prototypes.  Provides a detailed analysis of all aspects of capacitive DC-DC converter design;  Analyzes the potential of this type of DC-DC converter and introduces a number of techniques to unleash their full potential; Combines system theory with practical implementation techniques; Includes unique analysis of CMOS technology for this application; Provides in-depth analysis of four fabricated prototypes.

  10. External ionization mechanisms for advanced thermionic converters

    Science.gov (United States)

    Hatziprokopiou, M. E.

    Ion generation and recombination mechanisms in the cesium plasma were investigated as they pertain to the advanced mode thermionic energy converters. The changes in plasma density and temperature within the converter were studied under the influence of several promising auxiliary ionization candidate sources. Three novel approaches of external cesium ion generation were investigated in some detail, namely vibrationally excited N2 as an energy source of ionization of Cs ions in a DC discharge, microwave power as a means of resonant sustenance of the cesium plasma, and ion generation in a pulse N2-Cs mixture. The experimental data obtained and discussed in this work show that all three techniques--i.e. the non-LTE high-voltage pulsing, the energy transfer from vibrationally excited diatomic gases, and the external pumping with a microwave power--have considerable promise as schemes in auxiliary ion generation applicable to the advanced thermionic energy converter.

  11. Power system applications for PASC converter systems

    Energy Technology Data Exchange (ETDEWEB)

    Donnelly, M.K. [Pacific Northwest Lab., Richland, WA (United States); Johnson, R.M. [Montana State Univ., Bozeman, MT (United States)

    1994-04-01

    This paper shows, using computer EMTP simulations, some preliminary results of applying pulse amplitude synthesis and control (PASC) technology to single-source level voltage converter system. The method can be applied to any single terminal pair source with appropriate modifications in power extraction interface and computer control program to match source and load impedance characteristics. The PASC realization as discussed here employs banks of transformers, one bank per phase, in which the primaries are connected in parallel through a switch matrix to the dc source. Two opposite polarity primaries per transformer are pulsed alternatively in time to produce an oscillatory sinusoidal output waveform. PASC conversion system capabilities to produce both leading and lagging power factor power output in single-phase and three-phase {Delta} or Y configurations are illustrated. EMTP simulations are used to demonstrate the converter capabilities. Also included are discussions regarding harmonics and potential control strategies to adapt the converter to an application or to minimize harmonics.

  12. Self-oscillating resonant power converter

    DEFF Research Database (Denmark)

    2014-01-01

    The present invention relates to resonant power converters and inverters comprising a self-oscillating feedback loop coupled from a switch output to a control input of a switching network comprising one or more semiconductor switches. The self-oscillating feedback loop sets a switching frequency...... of the power converter and comprises a first intrinsic switch capacitance coupled between a switch output and a control input of the switching network and a first inductor. The first inductor is coupled in-between a first bias voltage source and the control input of the switching network and has...... a substantially fixed inductance. The first bias voltage source is configured to generate an adjustable bias voltage applied to the first inductor. The output voltage of the power converter is controlled in a flexible and rapid manner by controlling the adjustable bias voltage....

  13. High Efficiency Reversible Fuel Cell Power Converter

    DEFF Research Database (Denmark)

    Pittini, Riccardo

    The large scale integration of renewable energy sources requires suitable energy storage systems to balance energy production and demand in the electrical grid. Bidirectional fuel cells are an attractive technology for energy storage systems due to the high energy density of fuel. Compared...... entitled "High Efficiency Reversible Fuel Cell Power Converter" and it presents the design of a high efficiency dc-dc converter developed and optimized for bidirectional fuel cell applications. First, a brief overview of fuel cell and energy storage technologies is presented. Different system topologies...... to traditional unidirectional fuel cell, bidirectional fuel cells have increased operating voltage and current ranges. These characteristics increase the stresses on dc-dc and dc-ac converters in the electrical system, which require proper design and advanced optimization. This work is part of the PhD project...

  14. Single phase AC-DC power factor corrected converter with high frequency isolation using buck converter

    Directory of Open Access Journals (Sweden)

    R. Ramesh,

    2014-03-01

    Full Text Available Single phase ac-dc converters having high frequency isolation are implemented in buck, boost, buck-boost configuration with improving the power quality in terms of reducing the harmonics of input current. The paperpropose the circuit configuration, control mechanism, and simulation result for the single phase ac-dc converter.

  15. Dual Converter Fed Open-End Transformer Topology with Parallel Converters and Integrated Magnetics

    DEFF Research Database (Denmark)

    Gohil, Ghanshyamsinh Vijaysinh; Bede, Lorand; Teodorescu, Remus

    2016-01-01

    A converter system for high power applications, connected to a medium-voltage network using a stepup transformer, is presented in this paper. The converterside winding of the transformer is configured as an openend and both the ends of the windings are fed from two different converter groups. Each...

  16. Si Bule Masuk Islam: Western Converts to Islam in Indonesia - more than just Converts of Convenience?

    Directory of Open Access Journals (Sweden)

    M. A. Kevin Brice

    2015-04-01

    Full Text Available In discussing converts to Islam, two different types of converts are often identified based on the reason for conversion: converts of convenience and converts of conviction. The common view is that in most (if not all cases, conversion to Islam in Indonesia by Westerners is about facilitating marriage and so the converts should be classified as converts of convenience. Evidence of the commonality of this view is considered by reference to advice offered to Westerners about marriage to Indonesians on specialist web sites and examples of coverage of the topic in Indonesian social media. By considering a number of brief case studies, the common view is challenged. The binary of “convert of convenience” versus “convert of conviction” is revisited to suggest that individuals may move between the types over a period of time. Finally the paper will consider whether there is anything about Islam in Indonesia which contributes to the phenomenon of “transnational” conversion by Westerners in Indonesia.DOI: 10.15408/sdi.v22i1.1386

  17. Solar energy converter using surface plasma waves

    Science.gov (United States)

    Anderson, L. M. (Inventor)

    1984-01-01

    Sunlight is dispersed over a diffraction grating formed on the surface of a conducting film on a substrate. The angular dispersion controls the effective grating period so that a matching spectrum of surface plasmons is excited for parallel processing on the conducting film. The resulting surface plasmons carry energy to an array of inelastic tunnel diodes. This solar energy converter does not require different materials for each frequency band, and sunlight is directly converted to electricity in an efficient manner by extracting more energy from the more energetic photons.

  18. Modeling and Simulation of Matrix Converter

    DEFF Research Database (Denmark)

    Liu, Fu-rong; Klumpner, Christian; Blaabjerg, Frede

    2005-01-01

    This paper discusses the modeling and simulation of matrix converter. Two models of matrix converter are presented: one is based on indirect space vector modulation and the other is based on power balance equation. The basis of these two models is• given and the process on modeling is introduced...... in details. The results of simulations developed for different researches reveal that different mdel may be suitable for different purpose, thus the model should be chosen different carefully. Some details and tricks in modeling are also introduced which give a reference for further research....

  19. Combination solar photovoltaic heat engine energy converter

    Science.gov (United States)

    Chubb, Donald L.

    1987-01-01

    A combination solar photovoltaic heat engine converter is proposed. Such a system is suitable for either terrestrial or space power applications. The combination system has a higher efficiency than either the photovoltaic array or the heat engine alone can attain. Advantages in concentrator and radiator area and receiver mass of the photovoltaic heat engine system over a heat-engine-only system are estimated. A mass and area comparison between the proposed space station organic Rankine power system and a combination PV-heat engine system is made. The critical problem for the proposed converter is the necessity for high temperature photovoltaic array operation. Estimates of the required photovoltaic temperature are presented.

  20. Metamaterial polarization converter analysis: limits of performance

    DEFF Research Database (Denmark)

    Markovich, Dmitry L.; Andryieuski, Andrei; Zalkovskij, Maksim;

    2013-01-01

    In this paper, we analyze the theoretical limits of a metamaterial-based converter with orthogonal linear eigenpolarizations that allow linear-to-elliptical polarization transformation with any desired ellipticity and ellipse orientation. We employ the transmission line approach providing a needed...... and a single layer with a ground plane can have 100 % polarization conversion efficiency. We tested our conclusions numerically reaching the designated limits of efficiency using a simple metamaterial design. Our general analysis provides useful guidelines for the metamaterial polarization converter design...

  1. Is China Ready for Full Yuan Convertibility?

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    Although China has made headway in reforming the exchange rate regime of its currency,the yuan,and expanding the use of it in cross-border trade during the past year,the yuan is far from fully convertible.Huang Yiping,a professor at the National School of Development of Peking University,said in an article for Beijing Review that China has the conditions for capital account liberalization and should strive for basic convertibility within five years. Edited excerpts follow

  2. Generalized modular multilevel converter and modulation

    DEFF Research Database (Denmark)

    Liu, Hui; Loh, Poh Chiang; Blaabjerg, Frede

    2014-01-01

    Modular multilevel converter (MMC) has gained popularity recently with its modulation, capacitor voltage balancing and circulating current issues widely discussed. Contributing to this effort, a study is presented here to show how the MMC topology can be derived from the viewpoint of two series...... converters regulating a power grid. The generalized topology derived and notated as GMMC can then be altered to create various types of MMC, including the traditional topology that is presently well-known. This effort has not been previously discussed, and may smoothen the understanding of MMC operation...

  3. Efficient, lightweight dc/dc switching converter

    Science.gov (United States)

    Cuk, S.; Middlebrook, R. D.

    1981-01-01

    Converters have input properties of boost power stage and output properties of buck power stage, yet they perform general conversion function with high efficiency. Other features include non-pulsating input/output currents, use of capacitive energy transfer, low output voltage ripple, reduced EMI, and small size.

  4. Power electronics converters for wind turbine systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Liserre, Marco; Ma, Ke

    2011-01-01

    The steady growth of installed wind power which reached 200 GW capacity in 2010, together with the up-scaling of the single wind turbine power capability - 7 MW’s has been announced by manufacturers - has pushed the research and development of power converters towards full scale power conversion,...

  5. Power Electronics Converters for Wind Turbine Systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Liserre, Marco; Ma, Ke

    2012-01-01

    The steady growth of installed wind power together with the upscaling of the single wind turbine power capability has pushed the research and development of power converters toward full-scale power conversion, lowered cost pr kW, increased power density, and also the need for higher reliability. ...

  6. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    @@ China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.

  7. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

      China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.……

  8. Power electronics converters for wind turbine systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Liserre, Marco; Ma, Ke

    2011-01-01

    The steady growth of installed wind power which reached 200 GW capacity in 2010, together with the up-scaling of the single wind turbine power capability - 7 MW’s has been announced by manufacturers - has pushed the research and development of power converters towards full scale power conversion,...

  9. Mathematical modeling of the flash converting process

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, H.Y.; Perez-Tello, M.; Riihilahti, K.M. [Utah Univ., Salt Lake City, UT (United States)

    1996-12-31

    An axisymmetric mathematical model for the Kennecott-Outokumpu flash converting process for converting solid copper matte to copper is presented. The model is an adaptation of the comprehensive mathematical model formerly developed at the University of Utah for the flash smelting of copper concentrates. The model incorporates the transport of momentum, heat, mass, and reaction kinetics between gas and particles in a particle-laden turbulent gas jet. The standard k-{epsilon} model is used to describe gas-phase turbulence in an Eulerian framework. The particle-phase is treated from a Lagrangian viewpoint which is coupled to the gas-phase via the source terms in the Eulerian gas-phase governing equations. Matte particles were represented as Cu{sub 2}S yFeS, and assumed to undergo homogeneous oxidation to Cu{sub 2}O, Fe{sub 3}O{sub 4}, and SO{sub 2}. A reaction kinetics mechanism involving both external mass transfer of oxygen gas to the particle surface and diffusion of oxygen through the porous oxide layer is proposed to estimate the particle oxidation rate Predictions of the mathematical model were compared with the experimental data collected in a bench-scale flash converting facility. Good agreement between the model predictions and the measurements was obtained. The model was used to study the effect of different gas-injection configurations on the overall fluid dynamics in a commercial size flash converting shaft. (author)

  10. Development of the Wave Energy Converter

    DEFF Research Database (Denmark)

    Kofoed, Jens Peter; Frigaard, Peter; Sørensen, Hans Christian

    2000-01-01

    The development of the wave energy converter Wave Dragon (WD) is presented. The WD is based on the overtopping principle. Initially a description of the WD is given. Then the development over time in terms of the various research and development projects working with the concept is described...

  11. Aquabuoy Wave Energy Converter

    DEFF Research Database (Denmark)

    Vicinanza, Diego; Margheritini, Lucia; Frigaard, Peter

    The work reported here is part of the contract agreement between the Finavera Renewables Ocean Energy Ltd. and the Department of Civil Engineering Hydraulics and Coastal Engineering Laboratory to instrument a model in scale 1:10 to prototype of the AquaBuOY (AB) wave energy converter and to analyse...

  12. Fast Constant Weight Codeword to Index Converter

    Science.gov (United States)

    2011-08-01

    is achievable; a 64-out- of-128 bit converter uses only 9% of the available ALMs. The large values of n required special Verilog programming. For...n r ) in a MATLAB program and wrote it to a header file that was included in the Verilog code. III. COMPLEX DISJOINT DECOMPOSITION SOLUTION It can

  13. Low-power variable frequency PFC converters

    Energy Technology Data Exchange (ETDEWEB)

    Li Yani; Yang Yintang; Zhu Zhangming, E-mail: yanili@mail.xidian.edu.c [Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of the Ministry of Education, Institute of Microelectronics, Xidian University, Xi' an 710071 (China)

    2010-01-15

    Based on the SinoMOS 1 {mu}m 40 V CMOS process, a novel power factor contention (PFC) converter with a low-power variable frequency function is presented. The circuit introduces a multi-vector error amplifier and a programmable oscillator to achieve frequency modulation, which provides a rapid dynamic response and precise output voltage clamping with low power in the entire load. According to the external load variation, the system can modulate the circuit operating frequency linearly, thereby ensuring that the PFC converter can work in frequency conversion-mode. Measured results show that the normal operating frequency of the PFC converter is 5-6 kHz, the start-up current is 36 {mu}A, the stable operating current is only 2.43 mA, the efficiency is 97.3%, the power factor (PF) is 0.988, THD is 3.8%, the load adjust rate is 3%, and the linear adjust rate is less than 1%. Both theoretical and practical results reveal that the power consumption of the whole supply system is reduced efficiently, especially when the load varies. The active die area of the PFC converter chip is 1.61 x 1.52 mm{sup 2}. (semiconductor integrated circuits)

  14. Oxygen activity measurements in simulated converter matte

    CSIR Research Space (South Africa)

    Tshilombo, KG

    2007-01-01

    Full Text Available to the composition of the gas atmosphere over the melt. The measured oxygen activity was generally close to that predicted by FactSage calculations. This indicates that such oxygen activity measurements could be useful to monitor iron removal during converting...

  15. Online Scheduling in Distributed Message Converter Systems

    NARCIS (Netherlands)

    Risse, Thomas; Wombacher, Andreas; Surridge, Mike; Taylor, Steve; Aberer, Karl

    2001-01-01

    The optimal distribution of jobs among hosts in distributed environments is an important factor to achieve high performance. The optimal strategy depends on the application. In this paper we present a new online scheduling strategy for distributed EDI converter system. The strategy is based on the B

  16. Converting Student Support Services to Online Delivery.

    Science.gov (United States)

    Brigham, David E.

    2001-01-01

    Uses a systems framework to analyze the creation of student support services for distance education at Regents College: electronic advising, electronic peer network, online course database, online bookstore, virtual library, and alumni services website. Addresses the issues involved in converting distance education programs from print-based and…

  17. Online Scheduling in Distributed Message Converter Systems

    NARCIS (Netherlands)

    Risse, Thomas; Wombacher, Andreas; Surridge, Mike; Taylor, Steve; Aberer, Karl

    2001-01-01

    The optimal distribution of jobs among hosts in distributed environments is an important factor to achieve high performance. The optimal strategy depends on the application. In this paper we present a new online scheduling strategy for distributed EDI converter system. The strategy is based on the B

  18. Online Scheduling in Distributed Message Converter Systems

    NARCIS (Netherlands)

    Risse, Thomas; Wombacher, Andreas; Surridge, Mike; Taylor, Steve; Aberer, Karl

    The optimal distribution of jobs among hosts in distributed environments is an important factor to achieve high performance. The optimal strategy depends on the application. In this paper we present a new online scheduling strategy for distributed EDI converter system. The strategy is based on the

  19. Near-Shore Floating Wave Energy Converters

    DEFF Research Database (Denmark)

    Ruol, Piero; Zanuttigh, Barbara; Martinelli, Luca

    2011-01-01

    Aim of this note is to analyse the possible application of a Wave Energy Converter (WEC) as a combined tool to protect the coast and harvest energy. Physical model tests are used to evaluate wave transmission past a near-shore floating WEC of the wave activated body type, named DEXA. Efficiency...

  20. Hybrid switch for resonant power converters

    Science.gov (United States)

    Lai, Jih-Sheng; Yu, Wensong

    2014-09-09

    A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters.

  1. A New Hard Switching Bidirectional Converter With High Power Density

    Directory of Open Access Journals (Sweden)

    Bahador Fani

    2010-01-01

    Full Text Available In this paper, a new isolated dc-dc bidirectional converter is proposed. This converter consists of two transformers (flyback and forward and only one switch in primary side and one switch in secondary side of transformers. In this converter energy transfers to the output in both on and off switch states so power density of this converter is high This converter controlled by PWM signal. Also this converter operates over a wide input voltage range. Theoretical analysis is presented and computer simulation and experimental results verify the converter analysis.

  2. Bidirectional converter interface for a battery energy storage test bench

    DEFF Research Database (Denmark)

    Trintis, Ionut; Thomas, Stephan; Blank, Tobias;

    2011-01-01

    This paper presents the bidirectional converter interface for a 6 kV battery energy storage test bench. The power electronic interface consists a two stage converter topology having a low voltage dc-ac grid connected converter and a new dual active bridge dc-dc converter with high transformation...... ratio. The dc-dc converter controls the battery charge/discharge current while the grid converter controls the common dc-link voltage and the grid current. The applied control structures and the hardware implementation of both converters are presented, together with their interaction. Experimental...

  3. Bidirectional converter interface for a battery energy storage test bench

    DEFF Research Database (Denmark)

    Trintis, Ionut; Thomas, Stephan; Blank, Tobias

    2011-01-01

    This paper presents the bidirectional converter interface for a 6 kV battery energy storage test bench. The power electronic interface consists a two stage converter topology having a low voltage dc-ac grid connected converter and a new dual active bridge dc-dc converter with high transformation...... ratio. The dc-dc converter controls the battery charge/discharge current while the grid converter controls the common dc-link voltage and the grid current. The applied control structures and the hardware implementation of both converters are presented, together with their interaction. Experimental...

  4. Multi-output DC-DC converters based on diode-clamped converters configuration

    DEFF Research Database (Denmark)

    Nami, A.; Zare, F.; Ghosh, A.;

    2010-01-01

    for a diode-clamed inverter in the grid connection systems, where boosting low rectified output-voltage and series DC link capacitors is required. To verify the proposed topology, steady-state and dynamic analyses of a MOB converter are examined. A simple control strategy has been proposed to demonstrate...... the performance of the proposed topology for a double-output boost converter. The topology and its control strategy can easily be extended to offer multiple outputs. Simulation and experimental results are presented to show the validity of the control strategy for the proposed converter....

  5. Emissions Tests Of Two Dc-To-Dc Converters

    Science.gov (United States)

    Mclyman, W. T.

    1992-01-01

    Report describes tests to characterize unwanted electric and magnetic fields, at frequencies up to few megahertz, radiated by two dc-to-dc converters, one 20-kHz square-wave converter; the other, a 33-kHz sine-wave converter. Part of effort to develop "quiet" power converter for use aboard spacecraft. Converter required to interfere minimally with delicate instruments measuring electric and magnetic fields.

  6. Coordinated Control of Wave Energy Converters Subject to Motion Constraints

    OpenAIRE

    2016-01-01

    In this paper, a generic coordinated control method for wave energy converters is proposed, and the constraints on motion amplitudes and the hydrodynamic interaction between converters are considered. The objective of the control problem is to maximize the energy converted from ocean waves, and this is achieved by coordinating the power take-off (PTO) damping of each wave energy converter in the frequency domain in each sea state. In a case study, a wave energy farm consisting of four convert...

  7. Design of Digital Synthesis Filters for Hybrid Filter Bank A/D Converters Using Semidefinite Programming

    Directory of Open Access Journals (Sweden)

    Wei Wang

    2014-05-01

    Full Text Available Hybrid filter bank (HFB analog-to-digital systems permit wideband, high frequency conversion. This paper presents mixed norm optimal design of digital synthesis filters of a HFB. The mixed norm is a convex combination of the 2-norm and the Chebyshev norm with a weighting parameter. Robust HFB design method based on worst-case ellipsoidal uncertainty in analog filters errors is also proposed. Both the problems can be solved using semidefinite programming. The proposed mixed norm method allows designers to select the best suitable filters among a family of synthesis filters for specific applications, and the robust design method is more insensitive to analog filters errors than the nominal minimax design

  8. Research on Converter Valve Overvoltage Mechanism and Calculation Conditions of ± 800 kV Converter Station

    Institute of Scientific and Technical Information of China (English)

    WANG Dongju; DENG Xu; ZHOU Hao; CHEN Xilei; XU Anwen; SHEN Yang

    2012-01-01

    The thyristor converter valve is the key equipment of commutation in ultra high voltage direct current (UHVDC) transmission systems. Owing to the limited voltage and current overload capacity, any transient overvoltage may cause permanent damage to the thyristor converter valve. In order to specify the converter valves' overvoltage levels of the ±800 kV UHVDC transmission system, the mechanisms of its generation and development are discussed in detail, from which the calculation conditions for the highest stresses of the converter valves are given. Finally, the converter valve's overvoltage of Xiluodu UHV converter station is simulated. The research results show that the overvoltages of the converter valves in the upper 3-pulse group of the high voltage(HV) and low voltage(LV) 12-pulse converter are generated jointly by the DC line voltage and the converter transformer's voltage at its valve side. Calculation conditions for this overvoltage are: DC system in bipolar operation mode, converter station operating as rectifier, maximum DC system operating voltage, minimum DC current, minimum AC system voltage of the converter station. Furthermore, the other converter valves' overvoltage is caused by the phase-to-phase switching surge generated at the converter station's AC side, penetrating into the valve hall. Overall, the maximum overvoltages of Xiluodu converter station in the upper 3-pulse group of the HV and LV 12-pulse converter are 379.1 kV and 384.9 kV, for other converter valves the maximum overvoltage is 375.3 kV.

  9. Imbalance between pulmonary angiotensin-converting enzyme and angiotensin-converting enzyme 2 activity in acute respiratory distress syndrome

    NARCIS (Netherlands)

    Wosten-van Asperen, Roelie M.; Bos, Albert; Bem, Reinout A.; Dierdorp, Barbara S.; Dekker, Tamara; van Goor, Harry; Kamilic, Jelena; van der Loos, Chris M.; van den Berg, Elske; Bruijn, Martijn; van Woensel, Job B.; Lutter, Rene

    2013-01-01

    Objective: Angiotensin-converting enzyme and its effector peptide angiotensin II have been implicated in the pathogenesis of acute respiratory distress syndrome. Recently, angiotensin-converting enzyme 2 was identified as the counter-regulatory enzyme of angiotensin-converting enzyme that converts

  10. Imbalance between pulmonary angiotensin-converting enzyme and angiotensin-converting enzyme 2 activity in acute respiratory distress syndrome

    NARCIS (Netherlands)

    Wosten-van Asperen, Roelie M.; Bos, Albert; Bem, Reinout A.; Dierdorp, Barbara S.; Dekker, Tamara; van Goor, Harry; Kamilic, Jelena; van der Loos, Chris M.; van den Berg, Elske; Bruijn, Martijn; van Woensel, Job B.; Lutter, Rene

    2013-01-01

    Objective: Angiotensin-converting enzyme and its effector peptide angiotensin II have been implicated in the pathogenesis of acute respiratory distress syndrome. Recently, angiotensin-converting enzyme 2 was identified as the counter-regulatory enzyme of angiotensin-converting enzyme that converts a

  11. Efficient Wide Range Converters (EWiRaC): A new family of high efficient AC-DC Converters

    DEFF Research Database (Denmark)

    Petersen, Lars; Andersen, Michael Andreas E.

    2006-01-01

    The performance in terms of efficiency of the existing power supplies used for PFC is very dependent on the input voltage range. The boost converter is the most commonly used PFC converter because of its simplicity and high efficiency. But, the boost converter as well as other known converters...... the converter topology according to the input voltage. This new converter type has been named: efficient wide range converter (EWiRaC). The performance of the EWiRaC is experimental verified in a universal input range (90-270VAC) application with an output voltage of 185VDC capable of 500W output power. The EWi...

  12. TiConverter: A training image converting tool for multiple-point geostatistics

    Science.gov (United States)

    Fadlelmula F., Mohamed M.; Killough, John; Fraim, Michael

    2016-11-01

    TiConverter is a tool developed to ease the application of multiple-point geostatistics whether by the open source Stanford Geostatistical Modeling Software (SGeMS) or other available commercial software. TiConverter has a user-friendly interface and it allows the conversion of 2D training images into numerical representations in four different file formats without the need for additional code writing. These are the ASCII (.txt), the geostatistical software library (GSLIB) (.txt), the Isatis (.dat), and the VTK formats. It performs the conversion based on the RGB color system. In addition, TiConverter offers several useful tools including image resizing, smoothing, and segmenting tools. The purpose of this study is to introduce the TiConverter, and to demonstrate its application and advantages with several examples from the literature.

  13. Radiation effects in power converters: Design of a radiation hardened integrated switching DC/DC converter

    Science.gov (United States)

    Adell, Philippe

    When electronic devices are used in space and military systems, they may be exposed to various types of radiation, including photons, electrons, protons, neutrons, and heavy ions. The effects of radiation on the semiconductor devices within the systems range from gradual degradation to catastrophic failure. In order to design and produce reliable systems for space or military applications, it is necessary to understand the device-level effects of radiation and develop appropriate strategies for reducing system susceptibility. This research focuses on understanding radiation effects in power converters for space and military applications. We show that power converters are very sensitive to radiation (total-dose, single event effects and displacement damage) and that their radiation response is dependent on input bias conditions and load conditions. We compared the radiation hardness of various power converter topologies using experiments and simulations. Evaluation of these designs under different modes of operation is demonstrated to be critical for determining radiation hardness. We emphasize the correlation between radiation effects and the role of the dynamic response of these topologies. For instance, total dose exposure has been found to degrade loop gain and affect regulation in some converters. We propose several radiation-hardening solutions to improve the radiation response of these designs. For instance, we demonstrate the design of a digitally controlled boost converter suitable for space applications based on an SRAM FPGA. A design hardening solution has been developed and successfully applied through VHDL simulations and experiments to assure the continuous operation of the converter in the presence of SEES (more precisely SEFIs). This research led to the design of a digitally controlled radiation hardened integrated switching buck converter. The proposed design is suitable for micro-satellite applications and is based on a high-voltage/CMOS process

  14. Parametric study of minimum converter loss in an energy-storage dc-to-dc converter

    Science.gov (United States)

    Wong, R. C.; Owen, H. A., Jr.; Wilson, T. G.

    1982-01-01

    Through a combination of analytical and numerical minimization procedures, a converter design that results in the minimum total converter loss (including core loss, winding loss, capacitor and energy-storage-reactor loss, and various losses in the semiconductor switches) is obtained. Because the initial phase involves analytical minimization, the computation time required by the subsequent phase of numerical minimization is considerably reduced in this combination approach. The effects of various loss parameters on the optimum values of the design variables are also examined.

  15. MAGIC: Model and Graphic Information Converter

    Science.gov (United States)

    Herbert, W. C.

    2009-01-01

    MAGIC is a software tool capable of converting highly detailed 3D models from an open, standard format, VRML 2.0/97, into the proprietary DTS file format used by the Torque Game Engine from GarageGames. MAGIC is used to convert 3D simulations from authoritative sources into the data needed to run the simulations in NASA's Distributed Observer Network. The Distributed Observer Network (DON) is a simulation presentation tool built by NASA to facilitate the simulation sharing requirements of the Data Presentation and Visualization effort within the Constellation Program. DON is built on top of the Torque Game Engine (TGE) and has chosen TGE's Dynamix Three Space (DTS) file format to represent 3D objects within simulations.

  16. Faults and Diagnosis Systems in Power Converters

    DEFF Research Database (Denmark)

    Lee, Kyo-Beum; Choi, Uimin

    2014-01-01

    efforts have been put into making these systems better in terms of reliability in order to achieve high power source availability, reduce the cost of energy and also increase the reliability of overall systems. Among the components used in power converters, a power device and a capacitor fault occurs most......A power converter is needed in almost all kinds of renewable energy systems and drive systems. It is used both for controlling the renewable source and for interfacing with the load, which can be grid-connected or working in standalone mode. Further, it drives the motors efficiently. Increasing...... frequently. Therefore, it is important to monitor the power device and capacitor fault to increase the reliability of power electronics. In this chapter, the diagnosis methods for power device fault will be discussed by dividing into open- and short-circuit faults. Then, the condition monitoring methods...

  17. Strained quantum well photovoltaic energy converter

    Science.gov (United States)

    Freundlich, Alexandre (Inventor); Renaud, Philippe (Inventor); Vilela, Mauro Francisco (Inventor); Bensaoula, Abdelhak (Inventor)

    1998-01-01

    An indium phosphide photovoltaic cell is provided where one or more quantum wells are introduced between the conventional p-conductivity and n-conductivity indium phosphide layer. The approach allows the cell to convert the light over a wider range of wavelengths than a conventional single junction cell and in particular convert efficiently transparency losses of the indium phosphide conventional cell. The approach hence may be used to increase the cell current output. A method of fabrication of photovoltaic devices is provided where ternary InAsP and InGaAs alloys are used as well material in the quantum well region and results in an increase of the cell current output.

  18. Component technology for Stirling power converters

    Science.gov (United States)

    Thieme, Lanny G.

    NASA Lewis Research Center has organized a component technology program as part of the efforts to develop Stirling converter technology for space power applications. The Stirling Space Power Program is part of the NASA High Capacity Power Project of the Civil Space Technology Initiative (CSTI). NASA Lewis is also providing technical management for the DOE/Sandia program to develop Stirling converters for solar terrestrial power producing electricity for the utility grid. The primary contractors for the space power and solar terrestrial programs develop component technologies directly related to their goals. This Lewis component technology effort, while coordinated with the main programs, aims at longer term issues, advanced technologies, and independent assessments. An overview of work on linear alternators, engine/alternator/load interactions and controls, heat exchangers, materials, life and reliability, and bearings is presented.

  19. A Variational Inequality from Pricing Convertible Bond

    Directory of Open Access Journals (Sweden)

    Yan Huiwen

    2011-01-01

    Full Text Available The model of pricing American-style convertible bond is formulated as a zero-sum Dynkin game, which can be transformed into a parabolic variational inequality (PVI. The fundamental variable in this model is the stock price of the firm which issued the bond, and the differential operator in PVI is linear. The optimal call and conversion strategies correspond to the free boundaries of PVI. Some properties of the free boundaries are studied in this paper. We show that the bondholder should convert the bond if and only if the price of the stock is equal to a fixed value, and the firm should call the bond back if and only if the price is equal to a strictly decreasing function of time. Moreover, we prove that the free boundaries are smooth and bounded. Eventually we give some numerical results.

  20. MOCCASIN: converting MATLAB ODE models to SBML.

    Science.gov (United States)

    Gómez, Harold F; Hucka, Michael; Keating, Sarah M; Nudelman, German; Iber, Dagmar; Sealfon, Stuart C

    2016-06-15

    MATLAB is popular in biological research for creating and simulating models that use ordinary differential equations (ODEs). However, sharing or using these models outside of MATLAB is often problematic. A community standard such as Systems Biology Markup Language (SBML) can serve as a neutral exchange format, but translating models from MATLAB to SBML can be challenging-especially for legacy models not written with translation in mind. We developed MOCCASIN (Model ODE Converter for Creating Automated SBML INteroperability) to help. MOCCASIN can convert ODE-based MATLAB models of biochemical reaction networks into the SBML format. MOCCASIN is available under the terms of the LGPL 2.1 license (http://www.gnu.org/licenses/lgpl-2.1.html). Source code, binaries and test cases can be freely obtained from https://github.com/sbmlteam/moccasin : mhucka@caltech.edu More information is available at https://github.com/sbmlteam/moccasin. © The Author 2016. Published by Oxford University Press.