WorldWideScience

Sample records for computer chips

  1. Architectures for single-chip image computing

    Science.gov (United States)

    Gove, Robert J.

    1992-04-01

    This paper will focus on the architectures of VLSI programmable processing components for image computing applications. TI, the maker of industry-leading RISC, DSP, and graphics components, has developed an architecture for a new-generation of image processors capable of implementing a plurality of image, graphics, video, and audio computing functions. We will show that the use of a single-chip heterogeneous MIMD parallel architecture best suits this class of processors--those which will dominate the desktop multimedia, document imaging, computer graphics, and visualization systems of this decade.

  2. Computer System Design System-on-Chip

    CERN Document Server

    Flynn, Michael J

    2011-01-01

    The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses th

  3. Solving wood chip transport problems with computer simulation.

    Science.gov (United States)

    Dennis P. Bradley; Sharon A. Winsauer

    1976-01-01

    Efficient chip transport operations are difficult to achieve due to frequent and often unpredictable changes in distance to market, chipping rate, time spent at the mill, and equipment costs. This paper describes a computer simulation model that allows a logger to design an efficient transport system in response to these changing factors.

  4. A single-chip computer analysis system for liquid fluorescence

    International Nuclear Information System (INIS)

    Zhang Yongming; Wu Ruisheng; Li Bin

    1998-01-01

    The single-chip computer analysis system for liquid fluorescence is an intelligent analytic instrument, which is based on the principle that the liquid containing hydrocarbons can give out several characteristic fluorescences when irradiated by strong light. Besides a single-chip computer, the system makes use of the keyboard and the calculation and printing functions of a CASIO printing calculator. It combines optics, mechanism and electronics into one, and is small, light and practical, so it can be used for surface water sample analysis in oil field and impurity analysis of other materials

  5. Titanium based flat heat pipes for computer chip cooling

    Science.gov (United States)

    Soni, Gaurav; Ding, Changsong; Sigurdson, Marin; Bozorgi, Payam; Piorek, Brian; MacDonald, Noel; Meinhart, Carl

    2008-11-01

    We are developing a highly conductive flat heat pipe (called Thermal Ground Plane or TGP) for cooling computer chips. Conventional heat pipes have circular cross sections and thus can't make good contact with chip surface. The flatness of our TGP will enable conformal contact with the chip surface and thus enhance cooling efficiency. Another limiting factor in conventional heat pipes is the capillary flow of the working fluid through a wick structure. In order to overcome this limitation we have created a highly porous wick structure on a flat titanium substrate by using micro fabrication technology. We first etch titanium to create very tall micro pillars with a diameter of 5 μm, a height of 40 μm and a pitch of 10 μm. We then grow a very fine nano structured titania (NST) hairs on all surfaces of the pillars by oxidation in H202. In this way we achieve a wick structure which utilizes multiple length scales to yield high performance wicking of water. It's capable of wicking water at an average velocity of 1 cm/s over a distance of several cm. A titanium cavity is laser-welded onto the wicking substrate and a small quantity of water is hermetically sealed inside the cavity to achieve a TGP. The thermal conductivity of our preliminary TGP was measured to be 350 W/m-K, but has the potential to be several orders of magnitude higher.

  6. Hot Chips and Hot Interconnects for High End Computing Systems

    Science.gov (United States)

    Saini, Subhash

    2005-01-01

    I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

  7. Single-Chip Computers With Microelectromechanical Systems-Based Magnetic Memory

    NARCIS (Netherlands)

    Carley, L. Richard; Bain, James A.; Fedder, Gary K.; Greve, David W.; Guillou, David F.; Lu, Michael S.C.; Mukherjee, Tamal; Santhanam, Suresh; Abelmann, Leon; Min, Seungook

    This article describes an approach for implementing a complete computer system (CPU, RAM, I/O, and nonvolatile mass memory) on a single integrated-circuit substrate (a chip)—hence, the name "single-chip computer." The approach presented combines advances in the field of microelectromechanical

  8. Neural chips, neural computers and application in high and superhigh energy physics experiments

    International Nuclear Information System (INIS)

    Nikityuk, N.M.; )

    2001-01-01

    Architecture peculiarity and characteristics of series of neural chips and neural computes used in scientific instruments are considered. Tendency of development and use of them in high energy and superhigh energy physics experiments are described. Comparative data which characterize the efficient use of neural chips for useful event selection, classification elementary particles, reconstruction of tracks of charged particles and for search of hypothesis Higgs particles are given. The characteristics of native neural chips and accelerated neural boards are considered [ru

  9. Experimental demonstration of reservoir computing on a silicon photonics chip

    Science.gov (United States)

    Vandoorne, Kristof; Mechet, Pauline; van Vaerenbergh, Thomas; Fiers, Martin; Morthier, Geert; Verstraeten, David; Schrauwen, Benjamin; Dambre, Joni; Bienstman, Peter

    2014-03-01

    In today’s age, companies employ machine learning to extract information from large quantities of data. One of those techniques, reservoir computing (RC), is a decade old and has achieved state-of-the-art performance for processing sequential data. Dedicated hardware realizations of RC could enable speed gains and power savings. Here we propose the first integrated passive silicon photonics reservoir. We demonstrate experimentally and through simulations that, thanks to the RC paradigm, this generic chip can be used to perform arbitrary Boolean logic operations with memory as well as 5-bit header recognition up to 12.5 Gbit s-1, without power consumption in the reservoir. It can also perform isolated spoken digit recognition. Our realization exploits optical phase for computing. It is scalable to larger networks and much higher bitrates, up to speeds >100 Gbit s-1. These results pave the way for the application of integrated photonic RC for a wide range of applications.

  10. On-chip photonic interconnects a computer architect's perspective

    CERN Document Server

    Nitta, Christopher J; Akella, Venkatesh

    2013-01-01

    As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection appli

  11. Study on irradiation effects of nucleus electromagnetic pulse on single chip computer system

    International Nuclear Information System (INIS)

    Hou Minsheng; Liu Shanghe; Wang Shuping

    2001-01-01

    Intense electromagnetic pulse, namely nucleus electromagnetic pulse (NEMP), lightning electromagnetic pulse (LEMP) and high power microwave (HPM), can disturb and destroy the single chip computer system. To study this issue, the authors made irradiation experiments by NEMPs generated by gigahertz transversal electromagnetic (GTEM) Cell. The experiments show that shutdown, restarting, communication errors of the single chip microcomputer system would occur when it was irradiated by the NEMPs. Based on the experiments, the cause on the effects on the single chip microcomputer system is discussed

  12. 3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems

    Directory of Open Access Journals (Sweden)

    Lee Mike Myung-Ok

    2006-01-01

    Full Text Available This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D vertically integrated adaptive computing system combining state-of-the-art processing and 3D interconnection technology. It comprises the vertical integration of two chips (a configurable array processor and an intelligent configurable switch through an indium bump interconnection array (IBIA. The configurable array processor (CAP is an array of heterogeneous processing elements (PEs, while the intelligent configurable switch (ICS comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer, along with a direct memory access (DMA controller. This paper introduces the novel 3D-SoftChip architecture for real-time communication and multimedia signal processing as a next-generation computing system. The paper further describes the advanced HW/SW codesign and verification methodology, including high-level system modeling of the 3D-SoftChip using SystemC, being used to determine the optimum hardware specification in the early design stage.

  13. Transportable GPU (General Processor Units) chip set technology for standard computer architectures

    Science.gov (United States)

    Fosdick, R. E.; Denison, H. C.

    1982-11-01

    The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

  14. Solid state isotopic power source for computer chips

    International Nuclear Information System (INIS)

    Brown, P.M.

    1992-01-01

    This paper reports that recent developments in materials technology now make it possible to fabricate nonthermal thin-film isotopic energy converters (REC) with a specific power of 24 W/kg and 5 to 10 year working life at 5 to 10 Watts. This creates applications never before possible, such as placing the power supply directly on integrated circuit chips. The efficiency of the REC is about 25% which is two to three times greater than the 6 to 8% capabilities of current thermoelectric systems

  15. Heat-driven liquid metal cooling device for the thermal management of a computer chip

    Energy Technology Data Exchange (ETDEWEB)

    Ma Kunquan; Liu Jing [Cryogenic Laboratory, PO Box 2711, Technical Institute of Physics and Chemistry, Chinese Academy of Sciences, Beijing 100080 (China)

    2007-08-07

    The tremendous heat generated in a computer chip or very large scale integrated circuit raises many challenging issues to be solved. Recently, liquid metal with a low melting point was established as the most conductive coolant for efficiently cooling the computer chip. Here, by making full use of the double merits of the liquid metal, i.e. superior heat transfer performance and electromagnetically drivable ability, we demonstrate for the first time the liquid-cooling concept for the thermal management of a computer chip using waste heat to power the thermoelectric generator (TEG) and thus the flow of the liquid metal. Such a device consumes no external net energy, which warrants it a self-supporting and completely silent liquid-cooling module. Experiments on devices driven by one or two stage TEGs indicate that a dramatic temperature drop on the simulating chip has been realized without the aid of any fans. The higher the heat load, the larger will be the temperature decrease caused by the cooling device. Further, the two TEGs will generate a larger current if a copper plate is sandwiched between them to enhance heat dissipation there. This new method is expected to be significant in future thermal management of a desk or notebook computer, where both efficient cooling and extremely low energy consumption are of major concern.

  16. Heat-driven liquid metal cooling device for the thermal management of a computer chip

    International Nuclear Information System (INIS)

    Ma Kunquan; Liu Jing

    2007-01-01

    The tremendous heat generated in a computer chip or very large scale integrated circuit raises many challenging issues to be solved. Recently, liquid metal with a low melting point was established as the most conductive coolant for efficiently cooling the computer chip. Here, by making full use of the double merits of the liquid metal, i.e. superior heat transfer performance and electromagnetically drivable ability, we demonstrate for the first time the liquid-cooling concept for the thermal management of a computer chip using waste heat to power the thermoelectric generator (TEG) and thus the flow of the liquid metal. Such a device consumes no external net energy, which warrants it a self-supporting and completely silent liquid-cooling module. Experiments on devices driven by one or two stage TEGs indicate that a dramatic temperature drop on the simulating chip has been realized without the aid of any fans. The higher the heat load, the larger will be the temperature decrease caused by the cooling device. Further, the two TEGs will generate a larger current if a copper plate is sandwiched between them to enhance heat dissipation there. This new method is expected to be significant in future thermal management of a desk or notebook computer, where both efficient cooling and extremely low energy consumption are of major concern

  17. Chips challenging champions games, computers and artificial intelligence

    CERN Document Server

    Schaeffer, J

    2002-01-01

    One of the earliest dreams of the fledgling field of artificial intelligence (AI) was to build computer programs that could play games as well as or better than the best human players. Despite early optimism in the field, the challenge proved to be surprisingly difficult. However, the 1990s saw amazing progress. Computers are now better than humans in checkers, Othello and Scrabble; are at least as good as the best humans in backgammon and chess; and are rapidly improving at hex, go, poker, and shogi. This book documents the progress made in computers playing games and puzzles. The book is the

  18. Fish and chips: implementation of a neural network model into computer chips to maximize swimming efficiency in autonomous underwater vehicles.

    Science.gov (United States)

    Blake, R W; Ng, H; Chan, K H S; Li, J

    2008-09-01

    Recent developments in the design and propulsion of biomimetic autonomous underwater vehicles (AUVs) have focused on boxfish as models (e.g. Deng and Avadhanula 2005 Biomimetic micro underwater vehicle with oscillating fin propulsion: system design and force measurement Proc. 2005 IEEE Int. Conf. Robot. Auto. (Barcelona, Spain) pp 3312-7). Whilst such vehicles have many potential advantages in operating in complex environments (e.g. high manoeuvrability and stability), limited battery life and payload capacity are likely functional disadvantages. Boxfish employ undulatory median and paired fins during routine swimming which are characterized by high hydromechanical Froude efficiencies (approximately 0.9) at low forward speeds. Current boxfish-inspired vehicles are propelled by a low aspect ratio, 'plate-like' caudal fin (ostraciiform tail) which can be shown to operate at a relatively low maximum Froude efficiency (approximately 0.5) and is mainly employed as a rudder for steering and in rapid swimming bouts (e.g. escape responses). Given this and the fact that bioinspired engineering designs are not obligated to wholly duplicate a biological model, computer chips were developed using a multilayer perception neural network model of undulatory fin propulsion in the knifefish Xenomystus nigri that would potentially allow an AUV to achieve high optimum values of propulsive efficiency at any given forward velocity, giving a minimum energy drain on the battery. We envisage that externally monitored information on flow velocity (sensory system) would be conveyed to the chips residing in the vehicle's control unit, which in turn would signal the locomotor unit to adopt kinematics (e.g. fin frequency, amplitude) associated with optimal propulsion efficiency. Power savings could protract vehicle operational life and/or provide more power to other functions (e.g. communications).

  19. Spreaders for immersion nucleate boiling cooling of a computer chip with a central hot spot

    International Nuclear Information System (INIS)

    Ali, Amir F.; El-Genk, Mohamed S.

    2012-01-01

    Highlights: ► The paper introduces a spreader concept for cooling high power chip with a hot spot. ► Spreader is comprised of a Cu substrate and copper micro-porous surface. ► Spreaders surface is cooled by nucleate boiling of PF-5060 dielectric liquid. ► Analysis demonstrated spreader effectiveness for mitigating hot spot effect. - Abstract: This paper numerically investigates the performance of composite spreaders comprised of Cu substrates and Cu micro-porous surfaces of different thicknesses for immersion cooling of 10 × 10 mm underlying computer chip with a 2 × 2 mm central hot spot. The local heat flux at the hot spot is three times the chip’s surface average outside the hot spot. The thickness of the Cu substrate changes from 1.6 to 3.2 mm and that of the Cu micro-porous surface changes from 80 to 197 μm. The spreaders are cooled by saturation nucleate boiling of PF-5060 dielectric liquid. The local values of the nucleate boiling heat transfer coefficients on the various Cu micro-porous surfaces are based on pool boiling experimental measurements. Results demonstrated the effectiveness of immersion cooling nucleate boiling for mitigating the effect of the hot spot. The spreaders decrease the maximum surface temperature and the temperature gradient on the chip surface and increase the dissipated thermal power by the chip and removed from the spreader surface. Increasing the thickness of the Cu substrate and/or decreasing the thickness of the Cu micro-porous surface increases the total thermal power removed, the chip surface temperature and the spreader’s footprint area.

  20. The human brain on a computer, the design neuromorphic chips aims to process information as does the mind

    International Nuclear Information System (INIS)

    Pajuelo, L.

    2015-01-01

    Develop chips that mimic the brain processes It will help create computers capable of interpreting information from image, sound and touch so that it may offer answers intelligent-not programmed before- according to these sensory data. chips neuromorphic may mimic the electrical activity neurons and brain synapses, and will be key to intelligence systems artificial (ia) that require interaction with the environment being able to extract information cognitive of what surrounds them. (Author)

  1. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip

    Science.gov (United States)

    Shulaker, Max M.; Hills, Gage; Park, Rebecca S.; Howe, Roger T.; Saraswat, Krishna; Wong, H.-S. Philip; Mitra, Subhasish

    2017-07-01

    The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors—promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage—fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce ‘highly processed’ information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

  2. A Compute Environment of ABC95 Array Computer Based on Multi-FPGA Chip

    Institute of Scientific and Technical Information of China (English)

    2000-01-01

    ABC95 array computer is a multi-function network's computer based on FPGA technology, The multi-function network supports processors conflict-free access data from memory and supports processors access data from processors based on enhanced MESH network.ABC95 instruction's system includes control instructions, scalar instructions, vectors instructions.Mostly net-work instructions are introduced.A programming environment of ABC95 array computer assemble language is designed.A programming environment of ABC95 array computer for VC++ is advanced.It includes load function of ABC95 array computer program and data, store function, run function and so on.Specially, The data type of ABC95 array computer conflict-free access is defined.The results show that these technologies can develop programmer of ABC95 array computer effectively.

  3. Computational On-Chip Imaging of Nanoparticles and Biomolecules using Ultraviolet Light

    KAUST Repository

    Daloglu, Mustafa Ugur

    2017-03-09

    Significant progress in characterization of nanoparticles and biomolecules was enabled by the development of advanced imaging equipment with extreme spatial-resolution and sensitivity. To perform some of these analyses outside of well-resourced laboratories, it is necessary to create robust and cost-effective alternatives to existing high-end laboratory-bound imaging and sensing equipment. Towards this aim, we have designed a holographic on-chip microscope operating at an ultraviolet illumination wavelength (UV) of 266 nm. The increased forward scattering from nanoscale objects at this short wavelength has enabled us to detect individual sub-30 nm nanoparticles over a large field-of-view of >16 mm2 using an on-chip imaging platform, where the sample is placed at ≤0.5 mm away from the active area of an opto-electronic sensor-array, without any lenses in between. The strong absorption of this UV wavelength by biomolecules including nucleic acids and proteins has further enabled high-contrast imaging of nanoscopic aggregates of biomolecules, e.g., of enzyme Cu/Zn-superoxide dismutase, abnormal aggregation of which is linked to amyotrophic lateral sclerosis (ALS) - a fatal neurodegenerative disease. This UV-based wide-field computational imaging platform could be valuable for numerous applications in biomedical sciences and environmental monitoring, including disease diagnostics, viral load measurements as well as air- and water-quality assessment.

  4. Computational On-Chip Imaging of Nanoparticles and Biomolecules using Ultraviolet Light.

    Science.gov (United States)

    Daloglu, Mustafa Ugur; Ray, Aniruddha; Gorocs, Zoltan; Xiong, Matthew; Malik, Ravinder; Bitan, Gal; McLeod, Euan; Ozcan, Aydogan

    2017-03-09

    Significant progress in characterization of nanoparticles and biomolecules was enabled by the development of advanced imaging equipment with extreme spatial-resolution and sensitivity. To perform some of these analyses outside of well-resourced laboratories, it is necessary to create robust and cost-effective alternatives to existing high-end laboratory-bound imaging and sensing equipment. Towards this aim, we have designed a holographic on-chip microscope operating at an ultraviolet illumination wavelength (UV) of 266 nm. The increased forward scattering from nanoscale objects at this short wavelength has enabled us to detect individual sub-30 nm nanoparticles over a large field-of-view of >16 mm 2 using an on-chip imaging platform, where the sample is placed at ≤0.5 mm away from the active area of an opto-electronic sensor-array, without any lenses in between. The strong absorption of this UV wavelength by biomolecules including nucleic acids and proteins has further enabled high-contrast imaging of nanoscopic aggregates of biomolecules, e.g., of enzyme Cu/Zn-superoxide dismutase, abnormal aggregation of which is linked to amyotrophic lateral sclerosis (ALS) - a fatal neurodegenerative disease. This UV-based wide-field computational imaging platform could be valuable for numerous applications in biomedical sciences and environmental monitoring, including disease diagnostics, viral load measurements as well as air- and water-quality assessment.

  5. Computational sensing of herpes simplex virus using a cost-effective on-chip microscope

    KAUST Repository

    Ray, Aniruddha

    2017-07-03

    Caused by the herpes simplex virus (HSV), herpes is a viral infection that is one of the most widespread diseases worldwide. Here we present a computational sensing technique for specific detection of HSV using both viral immuno-specificity and the physical size range of the viruses. This label-free approach involves a compact and cost-effective holographic on-chip microscope and a surface-functionalized glass substrate prepared to specifically capture the target viruses. To enhance the optical signatures of individual viruses and increase their signal-to-noise ratio, self-assembled polyethylene glycol based nanolenses are rapidly formed around each virus particle captured on the substrate using a portable interface. Holographic shadows of specifically captured viruses that are surrounded by these self-assembled nanolenses are then reconstructed, and the phase image is used for automated quantification of the size of each particle within our large field-of-view, ~30 mm2. The combination of viral immuno-specificity due to surface functionalization and the physical size measurements enabled by holographic imaging is used to sensitively detect and enumerate HSV particles using our compact and cost-effective platform. This computational sensing technique can find numerous uses in global health related applications in resource-limited environments.

  6. A powerful way of cooling computer chip using liquid metal with low melting point as the cooling fluid

    Energy Technology Data Exchange (ETDEWEB)

    Li Teng; Lv Yong-Gang [Chinese Academy of Sciences, Beijing (China). Cryogenic Lab.; Chinese Academy of Sciences, Beijing (China). Graduate School; Liu Jing; Zhou Yi-Xin [Chinese Academy of Sciences, Beijing (China). Cryogenic Lab.

    2006-12-15

    With the improvement of computational speed, thermal management becomes a serious concern in computer system. CPU chips are squeezing into tighter and tighter spaces with no more room for heat to escape. Total power-dissipation levels now reside about 110 W, and peak power densities are reaching 400-500 W/mm{sup 2} and are still steadily climbing. As a result, higher performance and greater reliability are extremely tough to attain. But since the standard conduction and forced-air convection techniques no longer be able to provide adequate cooling for sophisticated electronic systems, new solutions are being looked into liquid cooling, thermoelectric cooling, heat pipes, and vapor chambers. In this paper, we investigated a novel method to significantly lower the chip temperature using liquid metal with low melting point as the cooling fluid. The liquid gallium was particularly adopted to test the feasibility of this cooling approach, due to its low melting point at 29.7 C, high thermal conductivity and heat capacity. A series of experiments with different flow rates and heat dissipation rates were performed. The cooling capacity and reliability of the liquid metal were compared with that of the water-cooling and very attractive results were obtained. Finally, a general criterion was introduced to evaluate the cooling performance difference between the liquid metal cooling and the water-cooling. The results indicate that the temperature of the computer chip can be significantly reduced with the increasing flow rate of liquid gallium, which suggests that an even higher power dissipation density can be achieved with a large flow of liquid gallium and large area of heat dissipation. The concept discussed in this paper is expected to provide a powerful cooling strategy for the notebook PC, desktop PC and large computer. It can also be extended to more wide area involved with thermal management on high heat generation rate. (orig.)

  7. Computer Simulation of Replaceable Many Sider Plates (RMSP) with Enhanced Chip-Breaking Characteristics

    OpenAIRE

    Korchuganova, Mariya Anatolievna; Syrbakov, Andrey Pavlovich; Chernysheva, Tatiana Yurievna; Ivanov, G.; Gnedasch, E.

    2016-01-01

    Out of all common chip curling methods, a special tool face form has become the most widespread which is developed either by means of grinding or by means of profile pressing in the production process of RMSP. Currently, over 15 large tool manufacturers produce tools using instrument materials of over 500 brands. To this, we must add a large variety of tool face geometries, which purpose includes the control over form and dimensions of the chip. Taking into account all the many processed mate...

  8. The composing technique of fast and large scale nuclear data acquisition and control system with single chip microcomputers and PC computers

    International Nuclear Information System (INIS)

    Xu Zurun; Wu Shiying; Liu Haitao; Yao Yangsen; Wang Yingguan; Yang Chaowen

    1998-01-01

    The technique of employing single-chip microcomputers and PC computers to compose a fast and large scale nuclear data acquisition and control system was discussed in detail. The optimum composition mode of this kind of system, the acquisition and control circuit unit based on single-chip microcomputers, the real-time communication methods and the software composition under the Windows 3.2 were also described. One, two and three dimensional spectra measured by this system were demonstrated

  9. The human brain on a computer, the design neuromorphic chips aims to process information as does the mind; El cerebro humano en un ordenador

    Energy Technology Data Exchange (ETDEWEB)

    Pajuelo, L.

    2015-07-01

    Develop chips that mimic the brain processes It will help create computers capable of interpreting information from image, sound and touch so that it may offer answers intelligent-not programmed before- according to these sensory data. chips neuromorphic may mimic the electrical activity neurons and brain synapses, and will be key to intelligence systems artificial (ia) that require interaction with the environment being able to extract information cognitive of what surrounds them. (Author)

  10. The composing technique of fast and large scale nuclear data acquisition and control system with single chip microcomputers and PC computers

    International Nuclear Information System (INIS)

    Xu Zurun; Wu Shiying; Liu Haitao; Yao Yangsen; Wang Yingguan; Yang Chaowen

    1997-01-01

    The technique of employing single-chip microcomputers and PC computers to compose a fast and large scale nuclear data acquisition and control system was discussed in detail. The optimum composition mode of this kind of system, the acquisition and control circuit unit based on single-chip microcomputers, the real-time communication methods and the software composition under the Windows 3.2 were also described. One, two and three dimensional spectra measured by this system were demonstrated

  11. Computational On-Chip Imaging of Nanoparticles and Biomolecules using Ultraviolet Light

    KAUST Repository

    Daloglu, Mustafa Ugur; Ray, Aniruddha; Gorocs, Zoltan; Xiong, Matthew; Malik, Ravinder; Bitan, Gal; McLeod, Euan; Ozcan, Aydogan

    2017-01-01

    wavelength (UV) of 266 nm. The increased forward scattering from nanoscale objects at this short wavelength has enabled us to detect individual sub-30 nm nanoparticles over a large field-of-view of >16 mm2 using an on-chip imaging platform, where the sample

  12. Computer Simulation of Replaceable Many Sider Plates (RMSP) with Enhanced Chip-Breaking Characteristics

    Science.gov (United States)

    Korchuganova, M.; Syrbakov, A.; Chernysheva, T.; Ivanov, G.; Gnedasch, E.

    2016-08-01

    Out of all common chip curling methods, a special tool face form has become the most widespread which is developed either by means of grinding or by means of profile pressing in the production process of RMSP. Currently, over 15 large tool manufacturers produce tools using instrument materials of over 500 brands. To this, we must add a large variety of tool face geometries, which purpose includes the control over form and dimensions of the chip. Taking into account all the many processed materials, specific tasks of the process planner, requirements to the quality of manufactured products, all this makes the choice of a proper tool which can perform the processing in the most effective way significantly harder. Over recent years, the nomenclature of RMSP for lathe tools with mechanical mounting has been considerably broadened by means of diversification of their faces

  13. A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip.

    Science.gov (United States)

    Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

    2012-01-01

    This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min.

  14. A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks

    Directory of Open Access Journals (Sweden)

    Jim Harkin

    2009-01-01

    Full Text Available FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE, incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.

  15. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  16. Smart vision chips: An overview

    Science.gov (United States)

    Koch, Christof

    1994-01-01

    This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

  17. A Chip in the Curtain: Computer Technology in the Soviet Union

    Science.gov (United States)

    1989-03-01

    authority of the tsar. British historian Lionel Kochan recounted some of the rather complicated story of religion and the tsars: The Church, because of... pseudosciences " and their study was forbidden. Stalin’s policy delayed the development of a scientific and academic foundation for the study of the computer in...leaders, the doctrine of Marx and Lenin is a matter of faith comparable to a religion in Western terms. When the General Secretary of the Soviet Union

  18. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  19. Amdahl 470 Chip Package

    CERN Multimedia

    1975-01-01

    In the late 70s the larger IBM computers were water cooled. Amdahl, an IBM competitor, invented an air cooling technology for it's computers. His company worked hard, developing a computer that was faster and less expensive than the IBM System/360 mainframe computer systems. This object contains an actual Amdahl series 470 computer logic chip with an air cooling device mounted on top. The package leads and cooling tower are gold-plated.

  20. Phonon-based scalable platform for chip-scale quantum computing

    Directory of Open Access Journals (Sweden)

    Charles M. Reinke

    2016-12-01

    Full Text Available We present a scalable phonon-based quantum computer on a phononic crystal platform. Practical schemes involve selective placement of a single acceptor atom in the peak of the strain field in a high-Q phononic crystal cavity that enables coupling of the phonon modes to the energy levels of the atom. We show theoretical optimization of the cavity design and coupling waveguide, along with estimated performance figures of the coupled system. A qubit can be created by entangling a phonon at the resonance frequency of the cavity with the atom states. Qubits based on this half-sound, half-matter quasi-particle, called a phoniton, may outcompete other quantum architectures in terms of combined emission rate, coherence lifetime, and fabrication demands.

  1. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  2. The single chip microcomputer technique in an intelligent nuclear instrument

    International Nuclear Information System (INIS)

    Wang Tieliu; Sun Punan; Wang Ying

    1995-01-01

    The authors present that how to acquire and process the output signals from the nuclear detector adopting single chip microcomputer technique, including working principles and the designing method of the computer's software and hardware in the single chip microcomputer instrument

  3. Many-core technologies: The move to energy-efficient, high-throughput x86 computing (TFLOPS on a chip)

    CERN Multimedia

    CERN. Geneva

    2012-01-01

    With Moore's Law alive and well, more and more parallelism is introduced into all computing platforms at all levels of integration and programming to achieve higher performance and energy efficiency. Especially in the area of High-Performance Computing (HPC) users can entertain a combination of different hardware and software parallel architectures and programming environments. Those technologies range from vectorization and SIMD computation over shared memory multi-threading (e.g. OpenMP) to distributed memory message passing (e.g. MPI) on cluster systems. We will discuss HPC industry trends and Intel's approach to it from processor/system architectures and research activities to hardware and software tools technologies. This includes the recently announced new Intel(r) Many Integrated Core (MIC) architecture for highly-parallel workloads and general purpose, energy efficient TFLOPS performance, some of its architectural features and its programming environment. At the end we will have a br...

  4. Combining on-chip synthesis of a focused combinatorial library with computational target prediction reveals imidazopyridine GPCR ligands.

    Science.gov (United States)

    Reutlinger, Michael; Rodrigues, Tiago; Schneider, Petra; Schneider, Gisbert

    2014-01-07

    Using the example of the Ugi three-component reaction we report a fast and efficient microfluidic-assisted entry into the imidazopyridine scaffold, where building block prioritization was coupled to a new computational method for predicting ligand-target associations. We identified an innovative GPCR-modulating combinatorial chemotype featuring ligand-efficient adenosine A1/2B and adrenergic α1A/B receptor antagonists. Our results suggest the tight integration of microfluidics-assisted synthesis with computer-based target prediction as a viable approach to rapidly generate bioactivity-focused combinatorial compound libraries with high success rates. Copyright © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. Multimedia-Based Chip Design Education.

    Science.gov (United States)

    Catalkaya, Tamer; Golze, Ulrich

    This paper focuses on multimedia computer-based training programs on chip design. Their development must be fast and economical, in order to be affordable by technical university institutions. The self-produced teaching program Illusion, which demonstrates a monitor controller as an example of a small but complete chip design, was implemented to…

  6. Photonic network-on-chip design

    CERN Document Server

    Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

    2013-01-01

    This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

  7. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  8. Simulating the Effect of Modulated Tool-Path Chip Breaking On Surface Texture and Chip Length

    Energy Technology Data Exchange (ETDEWEB)

    Smith, K.S.; McFarland, J.T.; Tursky, D. A.; Assaid, T. S.; Barkman, W. E.; Babelay, Jr., E. F.

    2010-04-30

    One method for creating broken chips in turning processes involves oscillating the cutting tool in the feed direction utilizing the CNC machine axes. The University of North Carolina at Charlotte and the Y-12 National Security Complex have developed and are refining a method to reliably control surface finish and chip length based on a particular machine's dynamic performance. Using computer simulations it is possible to combine the motion of the machine axes with the geometry of the cutting tool to predict the surface characteristics and map the surface texture for a wide range of oscillation parameters. These data allow the selection of oscillation parameters to simultaneously ensure broken chips and acceptable surface characteristics. This paper describes the machine dynamic testing and characterization activities as well as the computational method used for evaluating and predicting chip length and surface texture.

  9. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  10. MOISTURE HUMIDITY EQUILIBRIUM OF WOOD CHIPS FROM ENERGETIC CROPS

    Directory of Open Access Journals (Sweden)

    Jan Barwicki

    2008-09-01

    Full Text Available Processes occurring during storage of wood chips for energetic or furniture industry purposes were presented. As a result of carried out investigations, dependences of temperature and relative humidity changes of surrounding air were shown. Modified Henderson equation can be utilized for computer simulation of storing and drying processes concerning wood chips for energetic and furniture industry purposes. It reflects also obtained results from experiments carried out with above mentioned material. Using computer simulation program we can examine different wood chips storing conditions to avoid overheating and loss problems.

  11. Medicaid CHIP ESPC Database

    Data.gov (United States)

    U.S. Department of Health & Human Services — The Environmental Scanning and Program Characteristic (ESPC) Database is in a Microsoft (MS) Access format and contains Medicaid and CHIP data, for the 50 states and...

  12. A proposed holistic approach to on-chip, off-chip, test, and package interconnections

    Science.gov (United States)

    Bartelink, Dirk J.

    1998-11-01

    The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

  13. Runtime adaptive multi-processor system-on-chip: RAMPSoC

    OpenAIRE

    Göhringer, D.; Hübner, M.; Schatz, V.; Becker, J.

    2008-01-01

    Current trends in high performance computing show, that the usage of multiprocessor systems on chip are one approach for the requirements of computing intensive applications. The multiprocessor system on chip (MPSoC) approaches often provide a static and homogeneous infrastructure of networked microprocessor on the chip die. A novel idea in this research area is to introduce the dynamic adaptivity of reconfigurable hardware in order to provide a flexible heterogeneous set of processing elemen...

  14. Ultrahigh-speed hybrid laser for silicon photonic integrated chips

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Park, Gyeong Cheol; Ran, Qijiang

    2013-01-01

    Increasing power consumption for electrical interconnects between and inside chips is posing a real challenge to continue the performance scaling of processors/computers as predicted by D. Moore. In recent processors, energy consumption for electrical interconnects is half of power supplied...... and will be 80% in near future. This challenge strongly has motivated replacing electrical interconnects with optical ones even in chip level communications [1]. This chip-level optical interconnects need quite different performance of optoelectronic devices than required for conventional optical communications....... For a light source, the energy consumption per sending a bit is required to be

  15. Price of forest chips decreasing

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

  16. Optimal selection of TLD chips

    International Nuclear Information System (INIS)

    Phung, P.; Nicoll, J.J.; Edmonds, P.; Paris, M.; Thompson, C.

    1996-01-01

    Large sets of TLD chips are often used to measure beam dose characteristics in radiotherapy. A sorting method is presented to allow optimal selection of chips from a chosen set. This method considers the variation

  17. An automatic chip structure optical inspection system for electronic components

    Science.gov (United States)

    Song, Zhichao; Xue, Bindang; Liang, Jiyuan; Wang, Ke; Chen, Junzhang; Liu, Yunhe

    2018-01-01

    An automatic chip structure inspection system based on machine vision is presented to ensure the reliability of electronic components. It consists of four major modules, including a metallographic microscope, a Gigabit Ethernet high-resolution camera, a control system and a high performance computer. An auto-focusing technique is presented to solve the problem that the chip surface is not on the same focusing surface under the high magnification of the microscope. A panoramic high-resolution image stitching algorithm is adopted to deal with the contradiction between resolution and field of view, caused by different sizes of electronic components. In addition, we establish a database to storage and callback appropriate parameters to ensure the consistency of chip images of electronic components with the same model. We use image change detection technology to realize the detection of chip images of electronic components. The system can achieve high-resolution imaging for chips of electronic components with various sizes, and clearly imaging for the surface of chip with different horizontal and standardized imaging for ones with the same model, and can recognize chip defects.

  18. Chip-based microtrap arrays for cold polar molecules

    Science.gov (United States)

    Hou, Shunyong; Wei, Bin; Deng, Lianzhong; Yin, Jianping

    2017-12-01

    Compared to the atomic chip, which has been a powerful platform to perform an astonishing range of applications from rapid Bose-Einstein condensate (BEC) production to the atomic clock, the molecular chip is only in its infant stages. Recently a one-dimensional electric lattice was demonstrated to trap polar molecules on a chip. This excellent work opens up the way to building a molecular chip laboratory. Here we propose a two-dimensional (2D) electric lattice on a chip with concise and robust structure, which is formed by arrays of squared gold wires. Arrays of microtraps that originate in the microsize electrodes offer a steep gradient and thus allow for confining both light and heavy polar molecules. Theoretical analysis and numerical calculations are performed using two types of sample molecules, N D3 and SrF, to justify the possibility of our proposal. The height of the minima of the potential wells is about 10 μm above the surface of the chip and can be easily adjusted in a wide range by changing the voltages applied on the electrodes. These microtraps offer intriguing perspectives for investigating cold molecules in periodic potentials, such as quantum computing science, low-dimensional physics, and some other possible applications amenable to magnetic or optical lattice. The 2D adjustable electric lattice is expected to act as a building block for a future gas-phase molecular chip laboratory.

  19. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  20. Hardware support for CSP on a Java chip multiprocessor

    DEFF Research Database (Denmark)

    Gruian, Flavius; Schoeberl, Martin

    2013-01-01

    Due to memory bandwidth limitations, chip multiprocessors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithreaded...... applications. Programmatically, the Communicating Sequential Processes (CSPs) paradigm provides a sound computational model for such an architecture with message based communication. In this paper we explore hardware support for CSP in the context of an embedded Java CMP. The hardware support for CSP are on......-chip communication channels, implemented by a ring-based network-on-chip (NoC), to reduce the memory bandwidth pressure on the shared memory.The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. CMP architectures of three to eight processors were...

  1. COMPUTING

    CERN Multimedia

    M. Kasemann

    Overview In autumn the main focus was to process and handle CRAFT data and to perform the Summer08 MC production. The operational aspects were well covered by regular Computing Shifts, experts on duty and Computing Run Coordination. At the Computing Resource Board (CRB) in October a model to account for service work at Tier 2s was approved. The computing resources for 2009 were reviewed for presentation at the C-RRB. The quarterly resource monitoring is continuing. Facilities/Infrastructure operations Operations during CRAFT data taking ran fine. This proved to be a very valuable experience for T0 workflows and operations. The transfers of custodial data to most T1s went smoothly. A first round of reprocessing started at the Tier-1 centers end of November; it will take about two weeks. The Computing Shifts procedure was tested full scale during this period and proved to be very efficient: 30 Computing Shifts Persons (CSP) and 10 Computing Resources Coordinators (CRC). The shift program for the shut down w...

  2. Silicon Chip-to-Chip Mode-Division Multiplexing

    DEFF Research Database (Denmark)

    Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

    2018-01-01

    A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

  3. Surface enhanced raman spectroscopy on chip

    DEFF Research Database (Denmark)

    Hübner, Jörg; Anhøj, Thomas Aarøe; Zauner, Dan

    2007-01-01

    In this paper we report low resolution surface enhanced Raman spectra (SERS) conducted with a chip based spectrometer. The flat field spectrometer presented here is fabricated in SU-8 on silicon, showing a resolution of around 3 nm and a free spectral range of around 100 nm. The output facet...... is projected onto a CCD element and visualized by a computer. To enhance the otherwise rather weak Raman signal, a nanosurface is prepared and a sample solutions is impregnated on this surface. The surface enhanced Raman signal is picked up using a Raman probe and coupled into the spectrometer via an optical...... fiber. The obtained spectra show that chip based spectrometer together with the SERS active surface can be used as Raman sensor....

  4. COMPUTING

    CERN Multimedia

    I. Fisk

    2011-01-01

    Introduction CMS distributed computing system performed well during the 2011 start-up. The events in 2011 have more pile-up and are more complex than last year; this results in longer reconstruction times and harder events to simulate. Significant increases in computing capacity were delivered in April for all computing tiers, and the utilisation and load is close to the planning predictions. All computing centre tiers performed their expected functionalities. Heavy-Ion Programme The CMS Heavy-Ion Programme had a very strong showing at the Quark Matter conference. A large number of analyses were shown. The dedicated heavy-ion reconstruction facility at the Vanderbilt Tier-2 is still involved in some commissioning activities, but is available for processing and analysis. Facilities and Infrastructure Operations Facility and Infrastructure operations have been active with operations and several important deployment tasks. Facilities participated in the testing and deployment of WMAgent and WorkQueue+Request...

  5. COMPUTING

    CERN Multimedia

    P. McBride

    The Computing Project is preparing for a busy year where the primary emphasis of the project moves towards steady operations. Following the very successful completion of Computing Software and Analysis challenge, CSA06, last fall, we have reorganized and established four groups in computing area: Commissioning, User Support, Facility/Infrastructure Operations and Data Operations. These groups work closely together with groups from the Offline Project in planning for data processing and operations. Monte Carlo production has continued since CSA06, with about 30M events produced each month to be used for HLT studies and physics validation. Monte Carlo production will continue throughout the year in the preparation of large samples for physics and detector studies ramping to 50 M events/month for CSA07. Commissioning of the full CMS computing system is a major goal for 2007. Site monitoring is an important commissioning component and work is ongoing to devise CMS specific tests to be included in Service Availa...

  6. COMPUTING

    CERN Multimedia

    M. Kasemann

    Overview During the past three months activities were focused on data operations, testing and re-enforcing shift and operational procedures for data production and transfer, MC production and on user support. Planning of the computing resources in view of the new LHC calendar in ongoing. Two new task forces were created for supporting the integration work: Site Commissioning, which develops tools helping distributed sites to monitor job and data workflows, and Analysis Support, collecting the user experience and feedback during analysis activities and developing tools to increase efficiency. The development plan for DMWM for 2009/2011 was developed at the beginning of the year, based on the requirements from the Physics, Computing and Offline groups (see Offline section). The Computing management meeting at FermiLab on February 19th and 20th was an excellent opportunity discussing the impact and for addressing issues and solutions to the main challenges facing CMS computing. The lack of manpower is particul...

  7. A survey of research and practices of network-on-chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Mahadevan, Shankar

    2006-01-01

    The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures...

  8. COMPUTING

    CERN Multimedia

    I. Fisk

    2013-01-01

    Computing activity had ramped down after the completion of the reprocessing of the 2012 data and parked data, but is increasing with new simulation samples for analysis and upgrade studies. Much of the Computing effort is currently involved in activities to improve the computing system in preparation for 2015. Operations Office Since the beginning of 2013, the Computing Operations team successfully re-processed the 2012 data in record time, not only by using opportunistic resources like the San Diego Supercomputer Center which was accessible, to re-process the primary datasets HTMHT and MultiJet in Run2012D much earlier than planned. The Heavy-Ion data-taking period was successfully concluded in February collecting almost 500 T. Figure 3: Number of events per month (data) In LS1, our emphasis is to increase efficiency and flexibility of the infrastructure and operation. Computing Operations is working on separating disk and tape at the Tier-1 sites and the full implementation of the xrootd federation ...

  9. COMPUTING

    CERN Multimedia

    I. Fisk

    2010-01-01

    Introduction It has been a very active quarter in Computing with interesting progress in all areas. The activity level at the computing facilities, driven by both organised processing from data operations and user analysis, has been steadily increasing. The large-scale production of simulated events that has been progressing throughout the fall is wrapping-up and reprocessing with pile-up will continue. A large reprocessing of all the proton-proton data has just been released and another will follow shortly. The number of analysis jobs by users each day, that was already hitting the computing model expectations at the time of ICHEP, is now 33% higher. We are expecting a busy holiday break to ensure samples are ready in time for the winter conferences. Heavy Ion An activity that is still in progress is computing for the heavy-ion program. The heavy-ion events are collected without zero suppression, so the event size is much large at roughly 11 MB per event of RAW. The central collisions are more complex and...

  10. COMPUTING

    CERN Multimedia

    M. Kasemann P. McBride Edited by M-C. Sawley with contributions from: P. Kreuzer D. Bonacorsi S. Belforte F. Wuerthwein L. Bauerdick K. Lassila-Perini M-C. Sawley

    Introduction More than seventy CMS collaborators attended the Computing and Offline Workshop in San Diego, California, April 20-24th to discuss the state of readiness of software and computing for collisions. Focus and priority were given to preparations for data taking and providing room for ample dialog between groups involved in Commissioning, Data Operations, Analysis and MC Production. Throughout the workshop, aspects of software, operating procedures and issues addressing all parts of the computing model were discussed. Plans for the CMS participation in STEP’09, the combined scale testing for all four experiments due in June 2009, were refined. The article in CMS Times by Frank Wuerthwein gave a good recap of the highly collaborative atmosphere of the workshop. Many thanks to UCSD and to the organizers for taking care of this workshop, which resulted in a long list of action items and was definitely a success. A considerable amount of effort and care is invested in the estimate of the comput...

  11. Estimate the thermomechanical fatigue life of two flip chip packages

    International Nuclear Information System (INIS)

    Pash, R.A.; Ullah, H.S.; Khan, M.Z.

    2005-01-01

    The continuing demand towards high density and low profile integrated circuit packaging has accelerated the development of flip chip structures as used in direct chip attach (DCA) technology, ball grid array (BOA) and chip scale package (CSP). In such structures the most widely used flip chip interconnects are solder joints. The reliability of flip chip structures largely depends on the reliability of solder joints. In this work solder joint fatigue life prediction for two chip scale packages is carried out. Elasto-plastic deformation behavior of the solder was simulated using ANSYS. Two dimensional plain strain finite element models were developed for each package to numerically compute the stress and total strain of the solder joints under temperature cycling. These stress and strain values are then used to predict the solder joint lifetime through modified Coffin Manson equation. The effect of solder joint's distance from edge of silicon die on life of the package is explored. The solder joint fatigue response is modeled for a typical temperature cycling of -60 to 140 degree C. (author)

  12. CATCHprofiles: Clustering and Alignment Tool for ChIP Profiles

    DEFF Research Database (Denmark)

    G. G. Nielsen, Fiona; Galschiøt Markus, Kasper; Møllegaard Friborg, Rune

    2012-01-01

    IP-profiling data and detect potentially meaningful patterns, the areas of enrichment must be aligned and clustered, which is an algorithmically and computationally challenging task. We have developed CATCHprofiles, a novel tool for exhaustive pattern detection in ChIP profiling data. CATCHprofiles is built upon...... a computationally efficient implementation for the exhaustive alignment and hierarchical clustering of ChIP profiling data. The tool features a graphical interface for examination and browsing of the clustering results. CATCHprofiles requires no prior knowledge about functional sites, detects known binding patterns...... it an invaluable tool for explorative research based on ChIP profiling data. CATCHprofiles and the CATCH algorithm run on all platforms and is available for free through the CATCH website: http://catch.cmbi.ru.nl/. User support is available by subscribing to the mailing list catch-users@bioinformatics.org....

  13. Experiment list: SRX122496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available || chip antibody=Rel || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip ant...ibody catalog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc

  14. A single chip with multiple talents

    CERN Multimedia

    Francesco Poppi

    2010-01-01

    The Medipix chips developed at CERN are being used in a variety of fields: from medicine to education and back to high-tech engineering. The scene is set for a bright future for this versatile technology.   The Medipix chip. It didn’t take long for a brilliant team of physicists and engineers who were working on pixel detectors for the LHC to realize that the technology had great potential in medical imaging. This was the birth of the Medipix project. Fifteen years later, with the collaboration of 18 research institutes, the team has produced an advanced version of the initial ideas: Medipix3 is a device that can measure very accurately the position and energy of the photons (one by one) that hit the associated detector. Radiography and computed tomography (CT) use X-ray photons to study the human body. The different energies of the photons in the beam can be thought of as the colours of the X-ray spectrum. This is why the use of Medipix3 chips in such diagnostic techniques is referred...

  15. Chips with everything

    CERN Document Server

    CERN. Geneva

    2007-01-01

    In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

  16. COMPUTING

    CERN Multimedia

    P. McBride

    It has been a very active year for the computing project with strong contributions from members of the global community. The project has focused on site preparation and Monte Carlo production. The operations group has begun processing data from P5 as part of the global data commissioning. Improvements in transfer rates and site availability have been seen as computing sites across the globe prepare for large scale production and analysis as part of CSA07. Preparations for the upcoming Computing Software and Analysis Challenge CSA07 are progressing. Ian Fisk and Neil Geddes have been appointed as coordinators for the challenge. CSA07 will include production tests of the Tier-0 production system, reprocessing at the Tier-1 sites and Monte Carlo production at the Tier-2 sites. At the same time there will be a large analysis exercise at the Tier-2 centres. Pre-production simulation of the Monte Carlo events for the challenge is beginning. Scale tests of the Tier-0 will begin in mid-July and the challenge it...

  17. COMPUTING

    CERN Multimedia

    M. Kasemann

    Introduction During the past six months, Computing participated in the STEP09 exercise, had a major involvement in the October exercise and has been working with CMS sites on improving open issues relevant for data taking. At the same time operations for MC production, real data reconstruction and re-reconstructions and data transfers at large scales were performed. STEP09 was successfully conducted in June as a joint exercise with ATLAS and the other experiments. It gave good indication about the readiness of the WLCG infrastructure with the two major LHC experiments stressing the reading, writing and processing of physics data. The October Exercise, in contrast, was conducted as an all-CMS exercise, where Physics, Computing and Offline worked on a common plan to exercise all steps to efficiently access and analyze data. As one of the major results, the CMS Tier-2s demonstrated to be fully capable for performing data analysis. In recent weeks, efforts were devoted to CMS Computing readiness. All th...

  18. COMPUTING

    CERN Multimedia

    I. Fisk

    2011-01-01

    Introduction It has been a very active quarter in Computing with interesting progress in all areas. The activity level at the computing facilities, driven by both organised processing from data operations and user analysis, has been steadily increasing. The large-scale production of simulated events that has been progressing throughout the fall is wrapping-up and reprocessing with pile-up will continue. A large reprocessing of all the proton-proton data has just been released and another will follow shortly. The number of analysis jobs by users each day, that was already hitting the computing model expectations at the time of ICHEP, is now 33% higher. We are expecting a busy holiday break to ensure samples are ready in time for the winter conferences. Heavy Ion The Tier 0 infrastructure was able to repack and promptly reconstruct heavy-ion collision data. Two copies were made of the data at CERN using a large CASTOR disk pool, and the core physics sample was replicated ...

  19. COMPUTING

    CERN Multimedia

    I. Fisk

    2012-01-01

    Introduction Computing continued with a high level of activity over the winter in preparation for conferences and the start of the 2012 run. 2012 brings new challenges with a new energy, more complex events, and the need to make the best use of the available time before the Long Shutdown. We expect to be resource constrained on all tiers of the computing system in 2012 and are working to ensure the high-priority goals of CMS are not impacted. Heavy ions After a successful 2011 heavy-ion run, the programme is moving to analysis. During the run, the CAF resources were well used for prompt analysis. Since then in 2012 on average 200 job slots have been used continuously at Vanderbilt for analysis workflows. Operations Office As of 2012, the Computing Project emphasis has moved from commissioning to operation of the various systems. This is reflected in the new organisation structure where the Facilities and Data Operations tasks have been merged into a common Operations Office, which now covers everything ...

  20. COMPUTING

    CERN Multimedia

    M. Kasemann

    CCRC’08 challenges and CSA08 During the February campaign of the Common Computing readiness challenges (CCRC’08), the CMS computing team had achieved very good results. The link between the detector site and the Tier0 was tested by gradually increasing the number of parallel transfer streams well beyond the target. Tests covered the global robustness at the Tier0, processing a massive number of very large files and with a high writing speed to tapes.  Other tests covered the links between the different Tiers of the distributed infrastructure and the pre-staging and reprocessing capacity of the Tier1’s: response time, data transfer rate and success rate for Tape to Buffer staging of files kept exclusively on Tape were measured. In all cases, coordination with the sites was efficient and no serious problem was found. These successful preparations prepared the ground for the second phase of the CCRC’08 campaign, in May. The Computing Software and Analysis challen...

  1. COMPUTING

    CERN Multimedia

    I. Fisk

    2010-01-01

    Introduction The first data taking period of November produced a first scientific paper, and this is a very satisfactory step for Computing. It also gave the invaluable opportunity to learn and debrief from this first, intense period, and make the necessary adaptations. The alarm procedures between different groups (DAQ, Physics, T0 processing, Alignment/calibration, T1 and T2 communications) have been reinforced. A major effort has also been invested into remodeling and optimizing operator tasks in all activities in Computing, in parallel with the recruitment of new Cat A operators. The teams are being completed and by mid year the new tasks will have been assigned. CRB (Computing Resource Board) The Board met twice since last CMS week. In December it reviewed the experience of the November data-taking period and could measure the positive improvements made for the site readiness. It also reviewed the policy under which Tier-2 are associated with Physics Groups. Such associations are decided twice per ye...

  2. COMPUTING

    CERN Multimedia

    M. Kasemann

    Introduction More than seventy CMS collaborators attended the Computing and Offline Workshop in San Diego, California, April 20-24th to discuss the state of readiness of software and computing for collisions. Focus and priority were given to preparations for data taking and providing room for ample dialog between groups involved in Commissioning, Data Operations, Analysis and MC Production. Throughout the workshop, aspects of software, operating procedures and issues addressing all parts of the computing model were discussed. Plans for the CMS participation in STEP’09, the combined scale testing for all four experiments due in June 2009, were refined. The article in CMS Times by Frank Wuerthwein gave a good recap of the highly collaborative atmosphere of the workshop. Many thanks to UCSD and to the organizers for taking care of this workshop, which resulted in a long list of action items and was definitely a success. A considerable amount of effort and care is invested in the estimate of the co...

  3. A hidden Ising model for ChIP-chip data analysis

    KAUST Repository

    Mo, Q.; Liang, F.

    2010-01-01

    , our method is computationally much more efficient. Availability: A software called iChip is freely available at http://www.bioconductor.org/. Contact: moq@mskcc.org. © The Author 2010. Published by Oxford University Press. All rights reserved

  4. COMPUTING

    CERN Multimedia

    2010-01-01

    Introduction Just two months after the “LHC First Physics” event of 30th March, the analysis of the O(200) million 7 TeV collision events in CMS accumulated during the first 60 days is well under way. The consistency of the CMS computing model has been confirmed during these first weeks of data taking. This model is based on a hierarchy of use-cases deployed between the different tiers and, in particular, the distribution of RECO data to T1s, who then serve data on request to T2s, along a topology known as “fat tree”. Indeed, during this period this model was further extended by almost full “mesh” commissioning, meaning that RECO data were shipped to T2s whenever possible, enabling additional physics analyses compared with the “fat tree” model. Computing activities at the CMS Analysis Facility (CAF) have been marked by a good time response for a load almost evenly shared between ALCA (Alignment and Calibration tasks - highest p...

  5. COMPUTING

    CERN Multimedia

    Contributions from I. Fisk

    2012-01-01

    Introduction The start of the 2012 run has been busy for Computing. We have reconstructed, archived, and served a larger sample of new data than in 2011, and we are in the process of producing an even larger new sample of simulations at 8 TeV. The running conditions and system performance are largely what was anticipated in the plan, thanks to the hard work and preparation of many people. Heavy ions Heavy Ions has been actively analysing data and preparing for conferences.  Operations Office Figure 6: Transfers from all sites in the last 90 days For ICHEP and the Upgrade efforts, we needed to produce and process record amounts of MC samples while supporting the very successful data-taking. This was a large burden, especially on the team members. Nevertheless the last three months were very successful and the total output was phenomenal, thanks to our dedicated site admins who keep the sites operational and the computing project members who spend countless hours nursing the...

  6. COMPUTING

    CERN Multimedia

    M. Kasemann

    Introduction A large fraction of the effort was focused during the last period into the preparation and monitoring of the February tests of Common VO Computing Readiness Challenge 08. CCRC08 is being run by the WLCG collaboration in two phases, between the centres and all experiments. The February test is dedicated to functionality tests, while the May challenge will consist of running at all centres and with full workflows. For this first period, a number of functionality checks of the computing power, data repositories and archives as well as network links are planned. This will help assess the reliability of the systems under a variety of loads, and identifying possible bottlenecks. Many tests are scheduled together with other VOs, allowing the full scale stress test. The data rates (writing, accessing and transfer¬ring) are being checked under a variety of loads and operating conditions, as well as the reliability and transfer rates of the links between Tier-0 and Tier-1s. In addition, the capa...

  7. COMPUTING

    CERN Multimedia

    Matthias Kasemann

    Overview The main focus during the summer was to handle data coming from the detector and to perform Monte Carlo production. The lessons learned during the CCRC and CSA08 challenges in May were addressed by dedicated PADA campaigns lead by the Integration team. Big improvements were achieved in the stability and reliability of the CMS Tier1 and Tier2 centres by regular and systematic follow-up of faults and errors with the help of the Savannah bug tracking system. In preparation for data taking the roles of a Computing Run Coordinator and regular computing shifts monitoring the services and infrastructure as well as interfacing to the data operations tasks are being defined. The shift plan until the end of 2008 is being put together. User support worked on documentation and organized several training sessions. The ECoM task force delivered the report on “Use Cases for Start-up of pp Data-Taking” with recommendations and a set of tests to be performed for trigger rates much higher than the ...

  8. COMPUTING

    CERN Multimedia

    P. MacBride

    The Computing Software and Analysis Challenge CSA07 has been the main focus of the Computing Project for the past few months. Activities began over the summer with the preparation of the Monte Carlo data sets for the challenge and tests of the new production system at the Tier-0 at CERN. The pre-challenge Monte Carlo production was done in several steps: physics generation, detector simulation, digitization, conversion to RAW format and the samples were run through the High Level Trigger (HLT). The data was then merged into three "Soups": Chowder (ALPGEN), Stew (Filtered Pythia) and Gumbo (Pythia). The challenge officially started when the first Chowder events were reconstructed on the Tier-0 on October 3rd. The data operations teams were very busy during the the challenge period. The MC production teams continued with signal production and processing while the Tier-0 and Tier-1 teams worked on splitting the Soups into Primary Data Sets (PDS), reconstruction and skimming. The storage sys...

  9. COMPUTING

    CERN Multimedia

    I. Fisk

    2013-01-01

    Computing operation has been lower as the Run 1 samples are completing and smaller samples for upgrades and preparations are ramping up. Much of the computing activity is focusing on preparations for Run 2 and improvements in data access and flexibility of using resources. Operations Office Data processing was slow in the second half of 2013 with only the legacy re-reconstruction pass of 2011 data being processed at the sites.   Figure 1: MC production and processing was more in demand with a peak of over 750 Million GEN-SIM events in a single month.   Figure 2: The transfer system worked reliably and efficiently and transferred on average close to 520 TB per week with peaks at close to 1.2 PB.   Figure 3: The volume of data moved between CMS sites in the last six months   The tape utilisation was a focus for the operation teams with frequent deletion campaigns from deprecated 7 TeV MC GEN-SIM samples to INVALID datasets, which could be cleaned up...

  10. COMPUTING

    CERN Multimedia

    I. Fisk

    2012-01-01

      Introduction Computing activity has been running at a sustained, high rate as we collect data at high luminosity, process simulation, and begin to process the parked data. The system is functional, though a number of improvements are planned during LS1. Many of the changes will impact users, we hope only in positive ways. We are trying to improve the distributed analysis tools as well as the ability to access more data samples more transparently.  Operations Office Figure 2: Number of events per month, for 2012 Since the June CMS Week, Computing Operations teams successfully completed data re-reconstruction passes and finished the CMSSW_53X MC campaign with over three billion events available in AOD format. Recorded data was successfully processed in parallel, exceeding 1.2 billion raw physics events per month for the first time in October 2012 due to the increase in data-parking rate. In parallel, large efforts were dedicated to WMAgent development and integrati...

  11. Computer software.

    Science.gov (United States)

    Rosenthal, L E

    1986-10-01

    Software is the component in a computer system that permits the hardware to perform the various functions that a computer system is capable of doing. The history of software and its development can be traced to the early nineteenth century. All computer systems are designed to utilize the "stored program concept" as first developed by Charles Babbage in the 1850s. The concept was lost until the mid-1940s, when modern computers made their appearance. Today, because of the complex and myriad tasks that a computer system can perform, there has been a differentiation of types of software. There is software designed to perform specific business applications. There is software that controls the overall operation of a computer system. And there is software that is designed to carry out specialized tasks. Regardless of types, software is the most critical component of any computer system. Without it, all one has is a collection of circuits, transistors, and silicone chips.

  12. Pelly Crossing wood chip boiler

    Energy Technology Data Exchange (ETDEWEB)

    1985-03-11

    The Pelly wood chip project has demonstrated that wood chips are a successful fuel for space and domestic water heating in a northern climate. Pelly Crossing was chosen as a demonstration site for the following reasons: its extreme temperatures, an abundant local supply of resource material, the high cost of fuel oil heating and a lack of local employment. The major obstacle to the smooth operation of the boiler system was the poor quality of the chip supply. The production of poor quality chips has been caused by inadequate operation and maintenance of the chipper. Dull knives and faulty anvil adjustments produced chips and splinters far in excess of the one centimetre size specified for the system's design. Unanticipated complications have caused costs of the system to be higher than expected by approximately $15,000. The actual cost of the project was approximately $165,000. The first year of the system's operation was expected to accrue $11,600 in heating cost savings. This estimate was impossible to confirm given the system's irregular operation and incremental costs. Consistent operation of the system for a period of at least one year plus the installation of monitoring devices will allow the cost effectiveness to be calculated. The wood chip system's impact on the environment was estimated to be minimal. Wood chip burning was considered cleaner and safer than cordwood burning. 9 refs., 6 figs., 6 tabs.

  13. Single chip camera active pixel sensor

    Science.gov (United States)

    Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

    2003-01-01

    A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

  14. Ultra-thin chip technology and applications

    CERN Document Server

    2010-01-01

    Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

  15. COMPUTING

    CERN Multimedia

    I. Fisk

    2011-01-01

    Introduction The Computing Team successfully completed the storage, initial processing, and distribution for analysis of proton-proton data in 2011. There are still a variety of activities ongoing to support winter conference activities and preparations for 2012. Heavy ions The heavy-ion run for 2011 started in early November and has already demonstrated good machine performance and success of some of the more advanced workflows planned for 2011. Data collection will continue until early December. Facilities and Infrastructure Operations Operational and deployment support for WMAgent and WorkQueue+Request Manager components, routinely used in production by Data Operations, are provided. The GlideInWMS and components installation are now deployed at CERN, which is added to the GlideInWMS factory placed in the US. There has been new operational collaboration between the CERN team and the UCSD GlideIn factory operators, covering each others time zones by monitoring/debugging pilot jobs sent from the facto...

  16. FY1995 trial production of brain functional chip; 1995 nendo no kino shuseki chip no shisaku

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The present computer system will run on a program which is prepared in advance. On the other hand, the human brain can acquire some processes from learning with experiments. It would be very useful us human nature, if these learning process should be build up artificially. Our aim is to reveal basic self-acquiring mechanism of information and its processes of the brain, and preliminary research, including theoretical problems, for building up specialized processor chip. Many research on the brain have been held at the views of scientifically and medically. However; we focused on the principle brain learning process itself. The results of the research was directly realized on a specialized processor chip tuned for high-speed simulation of neural network. We could pointed out some problems on the present brain type processor, and discussed about basic technique for implementation of the next age brain type processor and theories. (NEDO)

  17. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  18. A Time-predictable Memory Network-on-Chip

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Chong, David VH; Puffitsch, Wolfgang

    2014-01-01

    To derive safe bounds on worst-case execution times (WCETs), all components of a computer system need to be time-predictable: the processor pipeline, the caches, the memory controller, and memory arbitration on a multicore processor. This paper presents a solution for time-predictable memory...... arbitration and access for chip-multiprocessors. The memory network-on-chip is organized as a tree with time-division multiplexing (TDM) of accesses to the shared memory. The TDM based arbitration completely decouples processor cores and allows WCET analysis of the memory accesses on individual cores without...

  19. COMPUTING

    CERN Multimedia

    M. Kasemann

    CMS relies on a well functioning, distributed computing infrastructure. The Site Availability Monitoring (SAM) and the Job Robot submission have been very instrumental for site commissioning in order to increase availability of more sites such that they are available to participate in CSA07 and are ready to be used for analysis. The commissioning process has been further developed, including "lessons learned" documentation via the CMS twiki. Recently the visualization, presentation and summarizing of SAM tests for sites has been redesigned, it is now developed by the central ARDA project of WLCG. Work to test the new gLite Workload Management System was performed; a 4 times increase in throughput with respect to LCG Resource Broker is observed. CMS has designed and launched a new-generation traffic load generator called "LoadTest" to commission and to keep exercised all data transfer routes in the CMS PhE-DEx topology. Since mid-February, a transfer volume of about 12 P...

  20. Tunable on chip optofluidic laser

    DEFF Research Database (Denmark)

    Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders

    2016-01-01

    On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range.......On chip tunable laser is demonstrated by realizing a microfluidic droplet array. The periodicity is controlled by the pressure applied to two separate inlets, allowing to tune the lasing frequency over a broad spectral range....

  1. Error correcting code with chip kill capability and power saving enhancement

    Energy Technology Data Exchange (ETDEWEB)

    Gara, Alan G [Mount Kisco, NY; Chen, Dong [Croton On Husdon, NY; Coteus, Paul W [Yorktown Heights, NY; Flynn, William T [Rochester, MN; Marcella, James A [Rochester, MN; Takken, Todd [Brewster, NY; Trager, Barry M [Yorktown Heights, NY; Winograd, Shmuel [Scarsdale, NY

    2011-08-30

    A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.

  2. GRAPE-5: A Special-Purpose Computer for N-body Simulation

    OpenAIRE

    Kawai, Atsushi; Fukushige, Toshiyuki; Makino, Junichiro; Taiji, Makoto

    1999-01-01

    We have developed a special-purpose computer for gravitational many-body simulations, GRAPE-5. GRAPE-5 is the successor of GRAPE-3. Both consist of eight custom pipeline chips (G5 chip and GRAPE chip). The difference between GRAPE-5 and GRAPE-3 are: (1) The G5 chip contains two pipelines operating at 80 MHz, while the GRAPE chip had one at 20 MHz. Thus, the calculation speed of the G5 chip and that of GRAPE-5 board are 8 times faster than that of GRAPE chip and GRAPE-3 board. (2) The GRAPE-5 ...

  3. Foundations of Neuromorphic Computing

    Science.gov (United States)

    2013-05-01

    paradigms: few sensors/complex computations and many sensors/simple computation. Challenges with Nano-enabled Neuromorphic Chips A wide variety of...FOUNDATIONS OF NEUROMORPHIC COMPUTING MAY 2013 FINAL TECHNICAL REPORT APPROVED FOR PUBLIC RELEASE; DISTRIBUTION...2009 – SEP 2012 4. TITLE AND SUBTITLE FOUNDATIONS OF NEUROMORPHIC COMPUTING 5a. CONTRACT NUMBER IN-HOUSE 5b. GRANT NUMBER N/A 5c. PROGRAM

  4. Cache-aware network-on-chip for chip multiprocessors

    Science.gov (United States)

    Tatas, Konstantinos; Kyriacou, Costas; Dekoulis, George; Demetriou, Demetris; Avraam, Costas; Christou, Anastasia

    2009-05-01

    This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

  5. Atom chip gravimeter

    Science.gov (United States)

    Schubert, Christian; Abend, Sven; Gebbe, Martina; Gersemann, Matthias; Ahlers, Holger; Müntinga, Hauke; Matthias, Jonas; Sahelgozin, Maral; Herr, Waldemar; Lämmerzahl, Claus; Ertmer, Wolfgang; Rasel, Ernst

    2016-04-01

    Atom interferometry has developed into a tool for measuring rotations [1], accelerations [2], and testing fundamental physics [3]. Gravimeters based on laser cooled atoms demonstrated residual uncertainties of few microgal [2,4] and were simplified for field applications [5]. Atomic gravimeters rely on the interference of matter waves which are coherently manipulated by laser light fields. The latter can be interpreted as rulers to which the position of the atoms is compared. At three points in time separated by a free evolution, the light fields are pulsed onto the atoms. First, a coherent superposition of two momentum states is produced, then the momentum is inverted, and finally the two trajectories are recombined. Depending on the acceleration the atoms experienced, the number of atoms detected in the output ports will change. Consequently, the acceleration can be determined from the output signal. The laser cooled atoms with microkelvin temperatures used in state-of-the-art gravimeters impose limits on the accuracy [4]. Therefore, ultra-cold atoms generated by Bose-Einstein condensation and delta-kick collimation [6,7] are expected to be the key for further improvements. These sources suffered from a low flux implying an incompatible noise floor, but a competitive performance was demonstrated recently with atom chips [8]. In the compact and robust setup constructed for operation in the drop tower [6] we demonstrated all steps necessary for an atom chip gravimeter with Bose-Einstein condensates in a ground based operation. We will discuss the principle of operation, the current performance, and the perspectives to supersede the state of the art. The authors thank the QUANTUS cooperation for contributions to the drop tower project in the earlier stages. This work is supported by the German Space Agency (DLR) with funds provided by the Federal Ministry for Economic Affairs and Energy (BMWi) due to an enactment of the German Bundestag under grant numbers DLR 50WM

  6. Experiment list: SRX214075 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available age=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  7. Experiment list: SRX122523 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  8. Experiment list: SRX122414 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  9. Experiment list: SRX214071 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available Undifferentiated || treatment=Overexpress Sox2-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacturer 2=

  10. Experiment list: SRX214086 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available entiated || cell line=KH2 || chip antibody 1=none || chip antibody manufacturer 1=none || chip antibody 2=none || chip antibody manuf...acturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-

  11. Experiment list: SRX122485 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100

  12. Experiment list: SRX122521 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  13. Experiment list: SRX122417 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  14. Experiment list: SRX122520 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  15. Experiment list: SRX122413 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

  16. Experiment list: SRX122412 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

  17. Experiment list: SRX122406 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 http:/

  18. Experiment list: SRX122415 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  19. Experiment list: SRX214074 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ge=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  20. Experiment list: SRX214072 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  1. Experiment list: SRX214067 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available fferentiated || cell line=F9 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufacture...r 1=Santa Cruz || chip antibody 2=none || chip antibody manufacturer 2=none http://dbarchive.bioscien

  2. Experiment list: SRX122416 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  3. Experiment list: SRX122565 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http:/

  4. Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems.

    Science.gov (United States)

    Indiveri, Giacomo

    2008-09-03

    Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

  5. Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

    Directory of Open Access Journals (Sweden)

    Giacomo Indiveri

    2008-09-01

    Full Text Available Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

  6. Chip compacting press; Jido kirikuzu asshukuki

    Energy Technology Data Exchange (ETDEWEB)

    Oura, K. [Yuken Kogyo Co. Ltd., Kanagawa (Japan)

    1998-08-15

    The chips exhausted from various machine tools are massy, occupy much space and make working environment worse by staying added cutting oil to lower part. The chips are exhausted as a result of machining and have not constant quality. Even if used material is same the chips have various shapes and properties by kinds and machining methods of used machine tools, and are troublesome materials from a standpoint of their treatment. Pressing and solidification of the chips have frequently been tried. A chip compacting press introduced in this paper, a relatively cheap chip compacting press aimed for relatively small scale chip treatment, and has such characteristics and effects as follows. Chips are pressed and solidified by each raw material, so fractional management can be easily conducted. As casting metal chips and curled chips of iron and aluminum can be pressed to about 1/3 to 1/5 and about 1/40, respectively, space saving can be conducted. Chip compacting pressing upgrades its transporting efficiency to make possible to reduce its transporting cost. As chip solidification controls its oxidation and most cutting oil are removed, chips are easy to recycle. 2 figs., 1 tab.

  7. STUDY OF CHIP IGNITION AND CHIP MORPHOLOGY AFTER MILLING OF MAGNESIUM ALLOYS

    Directory of Open Access Journals (Sweden)

    Ireneusz Zagórski

    2016-12-01

    Full Text Available The paper analyses the impact of specified technological parameters of milling (vc, fz, ap on time to ignition. Stages leading to chip ignition were analysed. Metallographic images of magnesium chip were presented. No significant difference was observed in time to ignition in different chip fractions. Moreover, the surface of chips was free of products of ignition and signs of strong oxidation.

  8. CMOS foveal image sensor chip

    Science.gov (United States)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  9. Industrial and scientific technology research and development project fiscal 1997 commissioned by the New Energy and Industrial Technology Development Organization. Report on research and development of a brain type computer architecture `trial fabrication and high-level evaluation on chips for a large-scale artificial neural system` and on results of evaluation studies on the chips; 1997 nendo sangyo kagaku gijutsu kenkyu kaihatsu jigyo Shin energy Sangyo Gijutsu Sogo Kaihatsu Kiko itaku. Nogata computer architecture no kenkyu kaihatsu `daikibo jinko shinkei kairo system yo chip no shisaku to kodo hyoka` chip hyoka kenkyu seika hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1998-03-01

    In order to develop a brain type computer architecture, a brain mimic processor (BMP) has been developed (which was made in LSI in fiscal 1997), and studies are being made on developing its applications. Development has been made on an element in which linkage of one million cells with one thousand neural cells can be realized. Evaluation substrates mounted with the BMP, control software, and compilers were provided to 15 organizations including the National Research Institutes, universities, corporations, and other societies (for 19 themes) to evaluate capability of the LSI and its application development. All of the research organizations are using these items utilizing features of the LSI or the network for such purposes as learning, storage, recognition and control. The applicable theme may include infrared spectrum pattern recognition and domain division of document images using neural network functions. It can also include structural analysis of mass spectrum molecules, time series pattern recognition, location of corresponding points in images, estimation of moving images, satellite control, character recognition, short time storage, long-term association memory models, and invention process studies, all utilizing the functions of the BMP. 71 refs., 89 figs., 9 tabs.

  10. Space division multiplexing chip-to-chip quantum key distribution

    DEFF Research Database (Denmark)

    Bacco, Davide; Ding, Yunhong; Dalgaard, Kjeld

    2017-01-01

    nodes of the quantum keys to their respective destinations. In this paper we present an experimental demonstration of a photonic integrated silicon chip quantum key distribution protocols based on space division multiplexing (SDM), through multicore fiber technology. Parallel and independent quantum...

  11. Influence of passivation process on chip performance

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; Schmitz, Jurriaan

    2009-01-01

    In this work, we have studied the performance of CMOS chips before and after a low temperature post-processing step. In order to prevent damage to the IC chips by the post-processing steps, a first passivation layers is needed on top of the IC chips. Two different passivation layer deposition

  12. Ultracold atoms on atom chips

    DEFF Research Database (Denmark)

    Krüger, Peter; Hofferberth, S.; Haller, E.

    2005-01-01

    Miniaturized potentials near the surface of atom chips can be used as flexible and versatile tools for the manipulation of ultracold atoms on a microscale. The full scope of possibilities is only accessible if atom-surface distances can be reduced to microns. We discuss experiments in this regime...

  13. FERMI multi-chip module

    CERN Multimedia

    This FERMI multi-chip module contains five million transistors. 25 000 of these modules will handle the flood of information through parts of the ATLAS and CMS detectors at the LHC. To select interesting events for recording, crucial decisions are taken before the data leaves the detector. FERMI modules are being developed at CERN in partnership with European industry.

  14. Tunable on chip optofluidic laser

    DEFF Research Database (Denmark)

    Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders

    2015-01-01

    A chip scale tunable laser in the visible spectral band is realized by generating a periodic droplet array inside a microfluidic channel. Combined with a gain medium within the droplets, the periodic structure provides the optical feedback of the laser. By controlling the pressure applied to two...

  15. Chip & Cut Tests an Elastomeren

    OpenAIRE

    Euchler, Eric; Heinrich, Gert; Michael, Hannes; Gehde, Michael; Stocek, Radek; Kratina, Ondrej; Kipscholl, Reinhold

    2016-01-01

    Dieser Vortrag stellt einen neuartigen Prüfstand vor, mit welchem das Chip & Cut Verhalten von Elastomeren charakterisiert werden kann. Sowohl theoretischer Hintergrund als auch praktische Erkenntnisse werden diskutiert. Die Vorstellung der Praxisrelevanz dieser Untersuchungen steht im Fokus des Vortrags.

  16. Edge chipping and flexural resistance of monolithic ceramics☆

    Science.gov (United States)

    Zhang, Yu; Lee, James J.-W.; Srikanth, Ramanathan; Lawn, Brian R.

    2014-01-01

    Objective Test the hypothesis that monolithic ceramics can be developed with combined esthetics and superior fracture resistance to circumvent processing and performance drawbacks of traditional all-ceramic crowns and fixed-dental-prostheses consisting of a hard and strong core with an esthetic porcelain veneer. Specifically, to demonstrate that monolithic prostheses can be produced with a much reduced susceptibility to fracture. Methods Protocols were applied for quantifying resistance to chipping as well as resistance to flexural failure in two classes of dental ceramic, microstructurally-modified zirconias and lithium disilicate glass–ceramics. A sharp indenter was used to induce chips near the edges of flat-layer specimens, and the results compared with predictions from a critical load equation. The critical loads required to produce cementation surface failure in monolithic specimens bonded to dentin were computed from established flexural strength relations and the predictions validated with experimental data. Results Monolithic zirconias have superior chipping and flexural fracture resistance relative to their veneered counterparts. While they have superior esthetics, glass–ceramics exhibit lower strength but higher chip fracture resistance relative to porcelain-veneered zirconias. Significance The study suggests a promising future for new and improved monolithic ceramic restorations, with combined durability and acceptable esthetics. PMID:24139756

  17. A Vision Chip for Color Segmentation and Pattern Matching

    Directory of Open Access Journals (Sweden)

    Ralph Etienne-Cummings

    2003-06-01

    Full Text Available A 128(H × 64(V × RGB CMOS imager is integrated with region-of-interest selection, RGB-to-HSI transformation, HSI-based pixel segmentation, (36bins × 12bits-HSI histogramming, and sum-of-absolute-difference (SAD template matching. Thirty-two learned color templates are stored and compared to each image. The chip captures the R, G, and B images using in-pixel storage before passing the pixel content to a multiplying digital-to-analog converter (DAC for white balancing. The DAC can also be used to pipe in images for a PC. The color processing uses a biologically inspired color opponent representation and an analog lookup table to determine the Hue (H of each pixel. Saturation (S is computed using a loser-take-all circuit. Intensity (I is given by the sum of the color components. A histogram of the segments of the image, constructed by counting the number of pixels falling into 36 Hue intervals of 10 degrees, is stored on a chip and compared against the histograms of new segments using SAD comparisons. We demonstrate color-based image segmentation and object recognition with this chip. Running at 30 fps, it uses 1 mW. To our knowledge, this is the first chip that integrates imaging, color segmentation, and color-based object recognition at the focal plane.

  18. Optical lattice on an atom chip

    DEFF Research Database (Denmark)

    Gallego, D.; Hofferberth, S.; Schumm, Thorsten

    2009-01-01

    Optical dipole traps and atom chips are two very powerful tools for the quantum manipulation of neutral atoms. We demonstrate that both methods can be combined by creating an optical lattice potential on an atom chip. A red-detuned laser beam is retroreflected using the atom chip surface as a high......-quality mirror, generating a vertical array of purely optical oblate traps. We transfer thermal atoms from the chip into the lattice and observe cooling into the two-dimensional regime. Using a chip-generated Bose-Einstein condensate, we demonstrate coherent Bloch oscillations in the lattice....

  19. A Cytomorphic Chip for Quantitative Modeling of Fundamental Bio-Molecular Circuits.

    Science.gov (United States)

    2015-08-01

    We describe a 0.35 μm BiCMOS silicon chip that quantitatively models fundamental molecular circuits via efficient log-domain cytomorphic transistor equivalents. These circuits include those for biochemical binding with automatic representation of non-modular and loading behavior, e.g., in cascade and fan-out topologies; for representing variable Hill-coefficient operation and cooperative binding; for representing inducer, transcription-factor, and DNA binding; for probabilistic gene transcription with analogic representations of log-linear and saturating operation; for gain, degradation, and dynamics of mRNA and protein variables in transcription and translation; and, for faithfully representing biological noise via tunable stochastic transistor circuits. The use of on-chip DACs and ADCs enables multiple chips to interact via incoming and outgoing molecular digital data packets and thus create scalable biochemical reaction networks. The use of off-chip digital processors and on-chip digital memory enables programmable connectivity and parameter storage. We show that published static and dynamic MATLAB models of synthetic biological circuits including repressilators, feed-forward loops, and feedback oscillators are in excellent quantitative agreement with those from transistor circuits on the chip. Computationally intensive stochastic Gillespie simulations of molecular production are also rapidly reproduced by the chip and can be reliably tuned over the range of signal-to-noise ratios observed in biological cells.

  20. Customizable computing

    CERN Document Server

    Chen, Yu-Ting; Gill, Michael; Reinman, Glenn; Xiao, Bingjun

    2015-01-01

    Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory

  1. Multicore systems on-chip practical software/hardware design

    CERN Document Server

    Abdallah, Abderazek Ben

    2013-01-01

    System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing.The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowi

  2. Shor's quantum factoring algorithm on a photonic chip.

    Science.gov (United States)

    Politi, Alberto; Matthews, Jonathan C F; O'Brien, Jeremy L

    2009-09-04

    Shor's quantum factoring algorithm finds the prime factors of a large number exponentially faster than any other known method, a task that lies at the heart of modern information security, particularly on the Internet. This algorithm requires a quantum computer, a device that harnesses the massive parallelism afforded by quantum superposition and entanglement of quantum bits (or qubits). We report the demonstration of a compiled version of Shor's algorithm on an integrated waveguide silica-on-silicon chip that guides four single-photon qubits through the computation to factor 15.

  3. MIL-STD-1553B Marconi LSI chip set in a remote terminal application

    Science.gov (United States)

    Dimarino, A.

    1982-11-01

    Marconi Avionics is utilizing the MIL-STD-1553B LSI Chip Set in the SCADC Air Data Computer application to perform all of the required remote terminal MIL-STD-1553B protocol functions. Basic components of the RTU are the dual redundant chip set, CT3231 Transceivers, 256 x 16 RAM and a Z8002 microprocessor. Basic transfers are to/from the RAM command of the bus controller or Z8002 processor. During transfers from the processor to the RAM, the chip set busy bit is set for a period not exceeding 250 microseconds. When the transfer is complete, the busy bit is released and transfers to the data bus occur on command. The LSI Chip Set word count lines are used to locate each data word in the local memory and 4 mode codes are used in the application: reset remote terminal, transmit status word, transmitter shut-down, and override transmitter shutdown.

  4. A Wireless Biomedical Signal Interface System-on-Chip for Body Sensor Networks.

    Science.gov (United States)

    Lei Wang; Guang-Zhong Yang; Jin Huang; Jinyong Zhang; Li Yu; Zedong Nie; Cumming, D R S

    2010-04-01

    Recent years have seen the rapid development of biosensor technology, system-on-chip design, wireless technology. and ubiquitous computing. When assembled into an autonomous body sensor network (BSN), the technologies become powerful tools in well-being monitoring, medical diagnostics, and personal connectivity. In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-property blocks include low-power analog sensor interface for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors, and it satisfied typical system requirements.

  5. Experiment list: SRX122465 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 6 || chip antibody=Relb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Bethyl || chip anti...body catalog number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2

  6. Experiment list: SRX122555 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available chip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip anti...body catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-7

  7. Selective attention in multi-chip address-event systems.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2009-01-01

    Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the "Selective Attention Chip" (SAC), which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

  8. Color sensor and neural processor on one chip

    Science.gov (United States)

    Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

    1998-10-01

    Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

  9. Flip chip assembly of thinned chips for hybrid pixel detector applications

    International Nuclear Information System (INIS)

    Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

  10. Wax-bonding 3D microfluidic chips

    KAUST Repository

    Gong, Xiuqing; Yi, Xin; Xiao, Kang; Li, Shunbo; Kodzius, Rimantas; Qin, Jianhua; Wen, Weijia

    2013-01-01

    We report a simple, low-cost and detachable microfluidic chip incorporating easily accessible paper, glass slides or other polymer films as the chip materials along with adhesive wax as the recycling bonding material. We use a laser to cut through the paper or film to form patterns and then sandwich the paper and film between glass sheets or polymer membranes . The hot-melt adhesive wax can realize bridge bonding between various materials, for example, paper, polymethylmethacrylate (PMMA) film, glass sheets, or metal plate. The bonding process is reversible and the wax is reusable through a melting and cooling process. With this process, a three-dimensional (3D) microfluidic chip is achievable by vacuating and venting the chip in a hot-water bath. To study the biocompatibility and applicability of the wax-based microfluidic chip, we tested the PCR compatibility with the chip materials first. Then we applied the wax-paper based microfluidic chip to HeLa cell electroporation (EP ). Subsequently, a prototype of a 5-layer 3D chip was fabricated by multilayer wax bonding. To check the sealing ability and the durability of the chip, green fluorescence protein (GFP) recombinant Escherichia coli (E. coli) bacteria were cultured, with which the chemotaxis of E. coli was studied in order to determine the influence of antibiotic ciprofloxacin concentration on the E. coli migration.

  11. Wax-bonding 3D microfluidic chips

    KAUST Repository

    Gong, Xiuqing

    2013-10-10

    We report a simple, low-cost and detachable microfluidic chip incorporating easily accessible paper, glass slides or other polymer films as the chip materials along with adhesive wax as the recycling bonding material. We use a laser to cut through the paper or film to form patterns and then sandwich the paper and film between glass sheets or polymer membranes . The hot-melt adhesive wax can realize bridge bonding between various materials, for example, paper, polymethylmethacrylate (PMMA) film, glass sheets, or metal plate. The bonding process is reversible and the wax is reusable through a melting and cooling process. With this process, a three-dimensional (3D) microfluidic chip is achievable by vacuating and venting the chip in a hot-water bath. To study the biocompatibility and applicability of the wax-based microfluidic chip, we tested the PCR compatibility with the chip materials first. Then we applied the wax-paper based microfluidic chip to HeLa cell electroporation (EP ). Subsequently, a prototype of a 5-layer 3D chip was fabricated by multilayer wax bonding. To check the sealing ability and the durability of the chip, green fluorescence protein (GFP) recombinant Escherichia coli (E. coli) bacteria were cultured, with which the chemotaxis of E. coli was studied in order to determine the influence of antibiotic ciprofloxacin concentration on the E. coli migration.

  12. A scalable single-chip multi-processor architecture with on-chip RTOS kernel

    NARCIS (Netherlands)

    Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

    2003-01-01

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

  13. Self-powered integrated systems-on-chip (energy chip)

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-04-23

    In today\\'s world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  14. Self-powered integrated systems-on-chip (energy chip)

    Science.gov (United States)

    Hussain, M. M.; Fahad, H.; Rojas, J.; Hasan, M.; Talukdar, A.; Oommen, J.; Mink, J.

    2010-04-01

    In today's world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  15. Optic nerve signals in a neuromorphic chip II: Testing and results.

    Science.gov (United States)

    Zaghloul, Kareem A; Boahen, Kwabena

    2004-04-01

    Seeking to match the brain's computational efficiency, we draw inspiration from its neural circuits. To model the four main output (ganglion) cell types found in the retina, we morphed outer and inner retina circuits into a 96 x 60-photoreceptor, 3.5 x 3.3 mm2, 0.35 microm-CMOS chip. Our retinomorphic chip produces spike trains for 3600 ganglion cells (GCs), and consumes 62.7 mW at 45 spikes/s/GC. This chip, which is the first silicon retina to successfully model inner retina circuitry, approaches the spatial density of the retina. We present experimental measurements showing that the chip's subthreshold current-mode circuits realize luminance adaptation, bandpass spatiotemporal filtering, temporal adaptation and contrast gain control. The four different GC outputs produced by our chip encode light onset or offset in a sustained or transient fashion, producing a quadrature-like representation. The retinomorphic chip's circuit design is described in a companion paper [Zaghloul and Boahen (2004)].

  16. Study of cutting speed on surface roughness and chip formation when machining nickel-based alloy

    International Nuclear Information System (INIS)

    Khidhir, Basim A.; Mohamed, Bashir

    2010-01-01

    Nickel- based alloy is difficult-to-machine because of its low thermal diffusive property and high strength at higher temperature. The machinability of nickel- based Hastelloy C-276 in turning operations has been carried out using different types of inserts under dry conditions on a computer numerical control (CNC) turning machine at different stages of cutting speed. The effects of cutting speed on surface roughness have been investigated. This study explores the types of wear caused by the effect of cutting speed on coated and uncoated carbide inserts. In addition, the effect of burr formation is investigated. The chip burr is found to have different shapes at lower speeds. Triangles and squares have been noticed for both coated and uncoated tips as well. The conclusion from this study is that the transition from thick continuous chip to wider discontinuous chip is caused by different types of inserts. The chip burr has a significant effect on tool damage starting in the line of depth-of-cut. For the coated insert tips, the burr disappears when the speed increases to above 150 m/min with the improvement of surface roughness; increasing the speed above the same limit for uncoated insert tips increases the chip burr size. The results of this study showed that the surface finish of nickel-based alloy is highly affected by the insert type with respect to cutting speed changes and its effect on chip burr formation and tool failure

  17. Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design

    Directory of Open Access Journals (Sweden)

    Oluwole John Famoriji

    2017-01-01

    Full Text Available Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

  18. Modeling, analysis and optimization of network-on-chip communication architectures

    CERN Document Server

    Ogras, Umit Y

    2013-01-01

    Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures. This book explores outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

  19. The use of forest chips in Finland

    International Nuclear Information System (INIS)

    Hakkila, P.

    2001-01-01

    International commitments require the industrial world to restrict their greenhouse gas emissions. In Finland, where the annual timber cut per capita is more than ten times the average cut in the other EU countries, the primary means to reduce CO 2 emissions is to replace fossil fuels with forest biomass. The annual consumption of wood-based energy corresponds to 6 million tonnes of oil equivalent (toe) or almost 20% of the total primary energy consumption. The goal is to rise the annual production of wood-based energy to 7.8 million toe by 2010. Substantial part of the targeted increase could be obtained by forest chips produced of unmerchantable small-diameter trees and logging residues. The goal for 2010 is to use 5 million solid m 3 of forest chips, which equals to 0.9 million toe. The use of forest chips is increasing. About 474 000 solid m 3 of forest chips were used as fuel in 1999. At the moment, the growth is rapid especially in cogeneration plants producing both heat and electricity. The growth is based primarily on chips obtained from logging residues. The price of forest chips decreased considerably during the 1990s but the price range remained wide. Chips made of logging residues are cheaper than those made of small trees. The average price of forest chips at the plant, VAT excluded, is about 53 FIM per MWh. In Sweden, the average price is more than 40% higher

  20. Least cost supply strategies for wood chips

    DEFF Research Database (Denmark)

    Möller, Bernd

    The abstract presents a study based on a geographical information system, which produce  cost-supply curves by location for forest woods chips in Denmark.......The abstract presents a study based on a geographical information system, which produce  cost-supply curves by location for forest woods chips in Denmark....

  1. Teaching Quality Control with Chocolate Chip Cookies

    Science.gov (United States)

    Baker, Ardith

    2014-01-01

    Chocolate chip cookies are used to illustrate the importance and effectiveness of control charts in Statistical Process Control. By counting the number of chocolate chips, creating the spreadsheet, calculating the control limits and graphing the control charts, the student becomes actively engaged in the learning process. In addition, examining…

  2. A Chip for an Implantable Neural Stimulator

    DEFF Research Database (Denmark)

    Gudnason, Gunnar; Bruun, Erik; Haugland, Morten

    2000-01-01

    This paper describes a chip for a multichannel neural stimulator for functional electrical stimulation (FES). The purpose of FES is to restore muscular control in disabled patients. The chip performs all the signal processing required in an implanted neural stimulator. The power and digital data...

  3. Performance evaluation of chip seals in Idaho.

    Science.gov (United States)

    2010-08-01

    The intent of this research project is to identify a wide variety of parameters that influence the performance of pavements treated via chip seals within the State of Idaho. Chip sealing is currently one of the most popular methods of maintenance for...

  4. Simple photolithographic rapid prototyping of microfluidic chips

    DEFF Research Database (Denmark)

    Kunstmann-Olsen, Casper; Hoyland, James; Rubahn, Horst-Günter

    2012-01-01

    Vi præsenterer en simpel metode til at producere støbeforme til støbning af PDMS mikrofluide chips vha. fotolitografi, med 35mm fotonegativer som masker. Vi demonstrer metodens muligheder og begrænsninger. Vi har optimeret processen til at fremstille planare lab-on-a-chip strukturer med meget høj...

  5. Microneedle Array Interface to CE on Chip

    NARCIS (Netherlands)

    Lüttge, Regina; Gardeniers, Johannes G.E.; Vrouwe, E.X.; van den Berg, Albert; Northrup, M.A.; Jensen, K.F; Harrison, D.J.

    2003-01-01

    This paper presents a microneedle array sampler interfaced to a capillary electrophoresis (CE) glass chip with integrated conductivity detection electrodes. A solution of alkali ions was electrokinetically loaded through the microneedles onto the chip and separation was demonstrated compared to a

  6. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  7. Versatile single-chip event sequencer for atomic physics experiments

    Science.gov (United States)

    Eyler, Edward

    2010-03-01

    A very inexpensive dsPIC microcontroller with internal 32-bit counters is used to produce a flexible timing signal generator with up to 16 TTL-compatible digital outputs, with a time resolution and accuracy of 50 ns. This time resolution is easily sufficient for event sequencing in typical experiments involving cold atoms or laser spectroscopy. This single-chip device is capable of triggered operation and can also function as a sweeping delay generator. With one additional chip it can also concurrently produce accurately timed analog ramps, and another one-chip addition allows real-time control from an external computer. Compared to an FPGA-based digital pattern generator, this design is slower but simpler and more flexible, and it can be reprogrammed using ordinary `C' code without special knowledge. I will also describe the use of the same microcontroller with additional hardware to implement a digital lock-in amplifier and PID controller for laser locking, including a simple graphics-based control unit. This work is supported in part by the NSF.

  8. METAL CHIP HEATING PROCESS INVESTIGATION (Part I

    Directory of Open Access Journals (Sweden)

    O. M. Dyakonov

    2007-01-01

    Full Text Available The main calculation methods for heat- and mass transfer in porous heterogeneous medium have been considered. The paper gives an evaluation of the possibility to apply them for calculation of metal chip heating process. It has been shown that a description of transfer processes in a chip has its own specific character that is attributed to difference between thermal and physical properties of chip material and lubricant-coolant components on chip surfaces. It has been determined that the known expressions for effective heat transfer coefficients can be used as basic ones while approaching mutually penetrating continuums. A mathematical description of heat- and mass transfer in chip medium can be considered as a basis of mathematical modeling, numerical solution and parameter optimization of the mentioned processes.

  9. A 16X16 Discrete Cosine Transform Chip

    Science.gov (United States)

    Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

    1987-10-01

    Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

  10. SVM classifier on chip for melanoma detection.

    Science.gov (United States)

    Afifi, Shereen; GholamHosseini, Hamid; Sinha, Roopak

    2017-07-01

    Support Vector Machine (SVM) is a common classifier used for efficient classification with high accuracy. SVM shows high accuracy for classifying melanoma (skin cancer) clinical images within computer-aided diagnosis systems used by skin cancer specialists to detect melanoma early and save lives. We aim to develop a medical low-cost handheld device that runs a real-time embedded SVM-based diagnosis system for use in primary care for early detection of melanoma. In this paper, an optimized SVM classifier is implemented onto a recent FPGA platform using the latest design methodology to be embedded into the proposed device for realizing online efficient melanoma detection on a single system on chip/device. The hardware implementation results demonstrate a high classification accuracy of 97.9% and a significant acceleration factor of 26 from equivalent software implementation on an embedded processor, with 34% of resources utilization and 2 watts for power consumption. Consequently, the implemented system meets crucial embedded systems constraints of high performance and low cost, resources utilization and power consumption, while achieving high classification accuracy.

  11. FY1995 evolvable hardware chip; 1995 nendo shinkasuru hardware chip

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    This project aims at the development of 'Evolvable Hardware' (EHW) which can adapt its hardware structure to the environment to attain better hardware performance, under the control of genetic algorithms. EHW is a key technology to explore the new application area requiring real-time performance and on-line adaptation. 1. Development of EHW-LSI for function level hardware evolution, which includes 15 DSPs in one chip. 2. Application of the EHW to the practical industrial applications such as data compression, ATM control, digital mobile communication. 3. Two patents : (1) the architecture and the processing method for programmable EHW-LSI. (2) The method of data compression for loss-less data, using EHW. 4. The first international conference for evolvable hardware was held by authors: Intl. Conf. on Evolvable Systems (ICES96). It was determined at ICES96 that ICES will be held every two years between Japan and Europe. So the new society has been established by us. (NEDO)

  12. Microfluidics and Lab-on-a-Chip Devices

    DEFF Research Database (Denmark)

    Castillo, Jaime

    2015-01-01

    The rapid advances in microfabrication and nanofabrication in combination with the synthesis and discovery of new materials have propelled the drive to develop new technological devices such as smartphones, personal and tablet computers. These devices have changed the way humankind interacts......TAS technologies need to join forces with those behind the new communication devices which provide sources of power, detection and data transmission complementing the features that lab-on-a-chip and microTAS platforms can offer. An increasing number of microfluidic-based devices, developed both in small start...

  13. On-chip COMA cache-coherence protocol for microgrids of microthreaded cores

    NARCIS (Netherlands)

    Zhang, L.; Jesshope, C.

    2008-01-01

    This paper describes an on-chip COMA cache coherency protocol to support the microthread model of concurrent program composition. The model gives a sound basis for building multi-core computers as it captures concurrency, abstracts communication and identifies resources, such as processor groups

  14. Advanced Nanofabrication Process Development for Self-Powered System-on-Chip

    KAUST Repository

    Rojas, Jhonathan Prieto

    2010-01-01

    In summary, by using a novel sustainable energy component and scalable nano-patterning for logic and computing module, this work has successfully collected the essential base knowledge and joined two different elements that synergistically will contribute for the future implementation of a Self-Powered System-on-Chip.

  15. Supply chains of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, Kalle (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

    2010-07-15

    The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6.5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40% at terminals

  16. Supply systems of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

    2010-07-01

    The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small-diameter thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2009. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2009 by these suppliers was 8,4 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected from March-May, 2010. The majority of the logging residue chips and chips from small-diameter thinning wood were produced using the roadside chipping supply system in Finland in 2009. The chipping at plant supply system was also significant in the production of logging residue chips. Nearly 70 % of all stump wood chips consumed were comminuted at the plant and 28 % at terminals. The role of the terminal chipping supply system was also significant in the production of chips from logging residues and small-diameter wood chips. When producing chips from large-sized (rotten) roundwood, similarly roughly 70 % of chips were comminuted at plants and 23 % at terminals. (orig.)

  17. Supply chains of forest chip production in Finland

    Energy Technology Data Exchange (ETDEWEB)

    Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), Email: kalle.karha@metsateho.fi

    2009-07-01

    The Metsaeteho study investigated how logging residue chips. stump wood chips, and chips from small-sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6,5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40 % at terminals. (orig.)

  18. Experiment list: SRX122563 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  19. Experiment list: SRX122564 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  20. Experiment list: SRX122488 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 h

  1. Experiment list: SRX122510 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Egr1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-110 ht

  2. Experiment list: SRX122491 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

  3. Experiment list: SRX122519 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http:

  4. Experiment list: SRX122548 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody... catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A

  5. Experiment list: SRX122468 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Rela || treatment=LPS || time=0 min || chip antibody manufacturer 1=Bethyl || chip antibody catalo...g number 1=A301-824A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-372 htt

  6. Experiment list: SRX122561 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  7. Experiment list: SRX122551 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ca...talog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A htt

  8. Experiment list: SRX122409 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Irf1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody cata...log number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 htt

  9. Experiment list: SRX122487 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 h

  10. Experiment list: SRX122546 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

  11. Experiment list: SRX122552 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibo...dy catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753

  12. Experiment list: SRX122547 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

  13. Experiment list: SRX214084 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available turer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox17-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufac

  14. Experiment list: SRX122472 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Runx1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab61753 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-8564 http

  15. Experiment list: SRX122544 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

  16. Experiment list: SRX122408 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Irf1 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 http

  17. Experiment list: SRX122473 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Runx1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab61753 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-8564

  18. Experiment list: SRX122513 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Egr1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-110

  19. Experiment list: SRX214077 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available erentiated || treatment=Overexpress Sox17_V5 tagged || cell line=KH2 || chip antibody 1=Sox17 || chip antibody manufacture...r 1=R&D || chip antibody 2=V5 || chip antibody manufacturer 2=Invit

  20. Experiment list: SRX122497 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Rel || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http:

  1. Experiment list: SRX214082 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available facturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...age=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manu

  2. Experiment list: SRX122410 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog n...umber 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://db

  3. Experiment list: SRX122567 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 ht

  4. Experiment list: SRX122466 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Relb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Bethyl || chip antibody cata...log number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-226 h

  5. Experiment list: SRX122490 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

  6. Experiment list: SRX214068 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available inoic acid || cell line=F9 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufacturer 1=Santa Cruz || chip... antibody 2=none || chip antibody manufacturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDat

  7. Experiment list: SRX122558 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available hip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antib...ody catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-75

  8. Experiment list: SRX122494 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available hip antibody=Atf4 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab28830-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-2

  9. Experiment list: SRX122545 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

  10. Experiment list: SRX186172 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 1=YY1 || chip antibody manufacturer 1=Abcam || chip antibody 2=YY1 || chip antibody manufacturer 2=Santa Cru...ip-Seq; Mus musculus; ChIP-Seq source_name=Rag1 -/- pro-B cells || chip antibody

  11. Experiment list: SRX122557 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available hip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antib...ody catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-75

  12. Experiment list: SRX122492 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

  13. Experiment list: SRX122493 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf4 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab28830-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-200

  14. Experiment list: SRX122571 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http

  15. Experiment list: SRX122411 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog n...umber 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://db

  16. Experiment list: SRX122549 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody... catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A

  17. Experiment list: SRX122498 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Rel || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http:

  18. Experiment list: SRX122516 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http:

  19. Experiment list: SRX122484 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Atf3 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cata...log number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 http

  20. Experiment list: SRX122514 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available tibody=Irf2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog nu...mber 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://db

  1. Experiment list: SRX122570 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available p antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 ht

  2. Experiment list: SRX214080 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available cturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufa

  3. Experiment list: SRX122569 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 h

  4. Experiment list: SRX122511 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Egr1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-11

  5. Experiment list: SRX122471 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Rela || treatment=LPS || time=60 min || chip antibody manufacturer 1=Bethyl || chip antibody cat...alog number 1=A301-824A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-372

  6. Experiment list: SRX122495 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Rel || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody catal...og number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http://

  7. Experiment list: SRX122554 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibo...dy catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753

  8. Experiment list: SRX214081 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available cturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufa

  9. Computers in Defence: An Assessment

    OpenAIRE

    R.K. Bagga

    1993-01-01

    Computer technology has revolutionised weapons system and hardware during the last decade 'miracle chip' has had impact in all areas of battlefield. The recent Gulf War has amply demonstrated the important role of computer technology in warfare. The best of the high technology was used during the 45 days of air battle followed by 100 hours of ground offensive. Computer and communication formed the heart of every weapon system from Tomahawk, SLAM, Scud, Patriot missile to night vision o...

  10. Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

    Science.gov (United States)

    Hashida, Takushi; Nagata, Makoto

    Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

  11. Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips

    OpenAIRE

    Tran, Nhat-Phuong; Lee, Myungho; Choi, Dong Hoon

    2015-01-01

    Aho-Corasick (AC) algorithm is a multiple patterns string matching algorithm commonly used in computer and network security and bioinformatics, among many others. In order to meet the highly demanding computational requirements imposed on these applications, achieving high performance for the AC algorithm is crucial. In this paper, we present a high performance parallelization of the AC on the many-core accelerator chips such as the Graphic Processing Unit (GPU) from Nvidia and...

  12. Driving the SID chip: Assembly language, composition, and sound design for the C64

    Directory of Open Access Journals (Sweden)

    James Newman

    2017-12-01

    Full Text Available The MOS6581, more commonly known as the Sound Interface Device, or SID chip, was the sonic heart of the Commodore 64 home computer. By considering the chip’s development, specification, uses and creative abuses by composers and programmers, alongside its continuing legacy, this paper argues that, more than any other device, the SID chip is responsible for shaping the sound of videogame music. Compared with the brutal atonality of chips such as Atari’s TIA, the SID chip offers a complex 3-channel synthesizer with dynamic waveform selection, per-channel ADSR envelopes, multi-mode filter, ring and cross modulation. However, while the specification is sophisticated, the exploitation of the vagaries and imperfections of the chip are just as significant to its sonic character. As such, the compositional, sound design and programming techniques developed by 1980s composer-coders like Rob Hubbard and Martin Galway are central in defining the distinctive sound of C64 gameplay. Exploring the affordances of the chip and the distinctive ways they were harnessed, the argument of this paper centers on the inexorable link between the technological and the musical. Crucially, composers like Hubbard et al. developed their own bespoke low-level drivers to interface with the SID chip to create pseudo-polyphony through rapid arpeggiation and channel sharing, drum synthesis through waveform manipulation, portamento, and even sample playback. This paper analyses the indivisibility of sound design, synthesis and composition in the birth of these musical forms and aesthetics, and assesses their impact on what would go on to be defined as chiptunes.

  13. Instrument for measuring moisture in wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Werme, L

    1980-06-01

    A method to determine the moisture content in wood chips, in batch and on-line, has been investigated. The method can be used for frozen and non frozen chips. Samples of wood chips are thawn and dryed with microwaves. During the drying the sample is weighed continously and the rate of drying is measured. The sample is dried t 10 percent moisture content. The result is extrapolated to the drying rate zero. The acccuracy at the method is 1.6 to 1.7 percent for both frozen and non frozen chips. The accuracy of the method is considered acceptable, but sofisticated sampling equipment is necessary. This makes the method too complex to make the instrument marketable.

  14. Medicaid CHIP Environmental Scanning and Program Char...

    Data.gov (United States)

    U.S. Department of Health & Human Services — ESPC development is sponsored by the CMS Center for Medicare and Medicaid Innovation in partnership with the Center for Medicaid and CHIP Services (CMCS) under the...

  15. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  16. On-chip power delivery and management

    CERN Document Server

    Vaisband, Inna P; Popovich, Mikhail; Mezhiba, Andrey V; Köse, Selçuk; Friedman, Eby G

    2016-01-01

    This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

  17. Distributed Processing Using Single-chip Microcomputers

    National Research Council Canada - National Science Library

    Pritchett, William

    1996-01-01

    This project investigates the use of single-chip microprocessors as nodes in a token ring control network and explores the implementation of a protocol to manage communication across such a network...

  18. Optical bio-sensors in microfluidic chips

    NARCIS (Netherlands)

    Pollnau, Markus; Dongre, C.; Pham Van So, P.V.S.; Bernhardi, Edward; Worhoff, Kerstin; de Ridder, R.M.; Hoekstra, Hugo

    2012-01-01

    Direct femtosecond laser writing is used to integrate optical waveguides that intersect the microfluidic channels in a commercial optofluidic chip. With laser excitation, fluorescently labeled DNA molecules of different sizes are separated by capillary electrophoresis with high operating speed and

  19. Optics and molecules on atom chips

    International Nuclear Information System (INIS)

    Tscherneck, M; Holmes, M E; Quinto-Su, P A; Haimberger, C; Kleinert, J; Bigelow, N P

    2005-01-01

    In this paper we will report on four experiments which have been carried out in the last year in our group. All of these experiments are necessary steps towards the trapping and probing of ultracold molecules on a chip surface

  20. The CHIP surveys | IDRC - International Development Research ...

    International Development Research Centre (IDRC) Digital Library (Canada)

    2011-07-08

    Jul 8, 2011 ... Many of the young scholars relied on data generated by the China Household Income Project (CHIP), a collaboration between Chinese and international economists that has tracked inequality in China for the past 20 years.

  1. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    International Nuclear Information System (INIS)

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-01-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

  2. Multifrequency Excitation Method for Rapid and Accurate Dynamic Test of Micromachined Gyroscope Chips

    Directory of Open Access Journals (Sweden)

    Yan Deng

    2014-10-01

    Full Text Available A novel multifrequency excitation (MFE method is proposed to realize rapid and accurate dynamic testing of micromachined gyroscope chips. Compared with the traditional sweep-frequency excitation (SFE method, the computational time for testing one chip under four modes at a 1-Hz frequency resolution and 600-Hz bandwidth was dramatically reduced from 10 min to 6 s. A multifrequency signal with an equal amplitude and initial linear-phase-difference distribution was generated to ensure test repeatability and accuracy. The current test system based on LabVIEW using the SFE method was modified to use the MFE method without any hardware changes. The experimental results verified that the MFE method can be an ideal solution for large-scale dynamic testing of gyroscope chips and gyroscopes.

  3. Ceramic thermal wind sensor based on advanced direct chip attaching package

    International Nuclear Information System (INIS)

    Zhou Lin; Qin Ming; Chen Shengqi; Chen Bei

    2014-01-01

    An advanced direct chip attaching packaged two-dimensional ceramic thermal wind sensor is studied. The thermal wind sensor chip is fabricated by metal lift-off processes on the ceramic substrate. An advanced direct chip attaching (DCA) packaging is adopted and this new packaged method simplifies the processes of packaging further. Simulations of the advanced DCA packaged sensor based on computational fluid dynamics (CFD) model show the sensor can detect wind speed and direction effectively. The wind tunnel testing results show the advanced DCA packaged sensor can detect the wind direction from 0° to 360° and wind speed from 0 to 20 m/s with the error less than 0.5 m/s. The nonlinear fitting based least square method in Matlab is used to analyze the performance of the sensor. (semiconductor devices)

  4. Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

    Science.gov (United States)

    Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

    2016-01-21

    Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

  5. Industry trends in chip storage and handling

    Science.gov (United States)

    Tim McDonald; Alastair Twaddle

    2000-01-01

    A survey was conducted of US pulp and paper mills to characterize chip pile management trends. The survey was developed by members of the TAPPI Fiber Raw Material Supply Committee and mailed out in December of 1999. There were a total of 80 respondents to the survey. A typical mill was foudn to maintain one sofhvood and one hardwood chip pile, with maximum inventory of...

  6. FY1995 evolvable hardware chip; 1995 nendo shinkasuru hardware chip

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    This project aims at the development of 'Evolvable Hardware' (EHW) which can adapt its hardware structure to the environment to attain better hardware performance, under the control of genetic algorithms. EHW is a key technology to explore the new application area requiring real-time performance and on-line adaptation. 1. Development of EHW-LSI for function level hardware evolution, which includes 15 DSPs in one chip. 2. Application of the EHW to the practical industrial applications such as data compression, ATM control, digital mobile communication. 3. Two patents : (1) the architecture and the processing method for programmable EHW-LSI. (2) The method of data compression for loss-less data, using EHW. 4. The first international conference for evolvable hardware was held by authors: Intl. Conf. on Evolvable Systems (ICES96). It was determined at ICES96 that ICES will be held every two years between Japan and Europe. So the new society has been established by us. (NEDO)

  7. Materials for microfluidic chip fabrication.

    Science.gov (United States)

    Ren, Kangning; Zhou, Jianhua; Wu, Hongkai

    2013-11-19

    Through manipulating fluids using microfabricated channel and chamber structures, microfluidics is a powerful tool to realize high sensitive, high speed, high throughput, and low cost analysis. In addition, the method can establish a well-controlled microenivroment for manipulating fluids and particles. It also has rapid growing implementations in both sophisticated chemical/biological analysis and low-cost point-of-care assays. Some unique phenomena emerge at the micrometer scale. For example, reactions are completed in a shorter amount of time as the travel distances of mass and heat are relatively small; the flows are usually laminar; and the capillary effect becomes dominant owing to large surface-to-volume ratios. In the meantime, the surface properties of the device material are greatly amplified, which can lead to either unique functions or problems that we would not encounter at the macroscale. Also, each material inherently corresponds with specific microfabrication strategies and certain native properties of the device. Therefore, the material for making the device plays a dominating role in microfluidic technologies. In this Account, we address the evolution of materials used for fabricating microfluidic chips, and discuss the application-oriented pros and cons of different materials. This Account generally follows the order of the materials introduced to microfluidics. Glass and silicon, the first generation microfluidic device materials, are perfect for capillary electrophoresis and solvent-involved applications but expensive for microfabriaction. Elastomers enable low-cost rapid prototyping and high density integration of valves on chip, allowing complicated and parallel fluid manipulation and in-channel cell culture. Plastics, as competitive alternatives to elastomers, are also rapid and inexpensive to microfabricate. Their broad variety provides flexible choices for different needs. For example, some thermosets support in-situ fabrication of

  8. Prototyping chips in minutes: Direct Laser Plotting (DLP) of functional microfluidic structures

    KAUST Repository

    Wang, Limu

    2013-10-10

    We report a fast and simple prototyping method to fabricate polymer-based microfluidic chips using Direct Laser Plotting (DLP) technique, by which various functional micro-structures can be realized within minutes, in a mask-free and out-of-cleanroom fashion. A 2D Computer-Aid-Design (CAD) software was employed to layout the required micro-structures and micro-channels, a CO2 laser plotter was then used to construct the microstructures. The desired patterns can be plotted directly on PDMS substrates and bio-compatible polymer films by manipulating the strength and density of laser pulses. With the DLP technique, chip-embedded micro-electrodes, micro-mixers and 3D microfluidic chips with 5 layers, which normally require several days of work in a cleanroom facility, can be fabricated in minutes in common laboratory. This novel method can produce microfluidic channels with average feature size of 100 μm, while feature size of 50 μm or smaller is achievable by making use of the interference effect from laser impulsion. In this report, we present the optimized parameters for successful fabrication of 3D microchannels, micro-mixers and microfluidic chips for protein concentration measurements (Bovine Serum Albumine (BSA) test), and a novel procedure to pattern flexible embedding electrodes on PDMS-based microfluidic chips. DLP offers a convenient and low cost alternative to conventional microfluidic channel fabrication technique which relies on complicated and hazardous soft lithography process.

  9. Edge chipping resistance and flexural strength of polymer infiltrated ceramic network and resin nanoceramic restorative materials.

    Science.gov (United States)

    Argyrou, Renos; Thompson, Geoffrey A; Cho, Seok-Hwan; Berzins, David W

    2016-09-01

    Two novel restorative materials, a polymer infiltrated ceramic network (PICN) and a resin nanoceramic (RNC), for computer-assisted design and computer-assisted manufacturing (CAD-CAM) applications have recently become commercially available. Little independent evidence regarding their mechanical properties exists to facilitate material selection. The purpose of this in vitro study was to measure the edge chipping resistance and flexural strength of the PICN and RNC materials and compare them with 2 commonly used feldspathic ceramic (FC) and leucite reinforced glass-ceramic (LRGC) CAD-CAM materials that share the same clinical indications. PICN, RNC, FC, and LRGC material specimens were obtained by sectioning commercially available CAD-CAM blocks. Edge chipping test specimens (n=20/material) were adhesively attached to a resin substrate before testing. Edge chips were produced using a 120-degree, sharp, conical diamond indenter mounted on a universal testing machine and positioned 0.1 to 0.7 mm horizontally from the specimen's edge. The chipping force was plotted against distance to the edge, and the data were fitted to linear and quadratic equations. One-way ANOVA determined intergroup differences (α=.05) in edge chipping toughness. Beam specimens (n=22/material) were tested for determining flexural strength using a 3-point bend test. Weibull statistics determined intergroup differences (α=.05). Flexural modulus and work of fracture were also calculated, and 1-way ANOVA determined intergroup differences (α=.05) RESULTS: Significant (Pmaterials for the 4 mechanical properties. Specifically, the material rankings were edge chipping toughness: RNC>LRGC=FC>PICN; flexural strength: RNC=LRGC>PICN>FC; flexural modulus: RNCLRGC=PICN>FC. The RNC material demonstrated superior performance for the mechanical properties tested compared with the other 3 materials. Copyright © 2016 Editorial Council for the Journal of Prosthetic Dentistry. Published by Elsevier Inc. All

  10. The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

    Directory of Open Access Journals (Sweden)

    Amlan Ganguly

    2018-02-01

    Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

  11. Discovery Mondays: Chips with everything!

    CERN Multimedia

    2003-01-01

    Electronics to hear the sound of matter From the TV to the fridge, the wristwatch to the washing machine, hardly any consumer product in this day and age can escape the influence of electronics, and the ever more powerful microchip. So it's hardly surprising to learn that such sophisticated devices as particle detectors are bristling with the best and most powerful microchips technology has to offer! Particle detectors known as trackers are like 3-D digital cameras. They are used to detect the tracks of particles created in the accelerator and to pin down their momentum and thus their identity. A chip seen with a microscope.Come to Microcosm and see with your own eyes a silicon detector, packed full of electronic microchips. Get up closer with a microscope and admire the way in which the fine details of the etchings break down light. Further on, watch a TV as you've never done before - from the inside! Then try out our special simulation game that helps you understand the purpose of a particle detector. Bu...

  12. Flip chip assembly of thinned chips for hybrid pixel detector applications

    CERN Document Server

    Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

  13. On-chip digital power supply control for system-on-chip applications

    NARCIS (Netherlands)

    Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

    2005-01-01

    The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

  14. Reconfigurable computing the theory and practice of FPGA-based computation

    CERN Document Server

    Hauck, Scott

    2010-01-01

    Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap between the separate worlds of hardware and software design- the key feature of reconfigurable computing is its groundbreaking ability to perform computations in hardware to increase performance while retaining the flexibility of a software solution. Reconfigurable computers serve as affordable, fast, and accurate tools for developing designs ranging from single chip architectures to multi-chip and embedded systems. Scott Hauck and Andre DeHon have assembled a group of the key experts in the fields of both hardwa

  15. Tracker Readout ASIC for Proton Computed Tomography Data Acquisition.

    Science.gov (United States)

    Johnson, Robert P; Dewitt, Joel; Holcomb, Cole; Macafee, Scott; Sadrozinski, Hartmut F-W; Steinberg, David

    2013-10-01

    A unique CMOS chip has been designed to serve as the front-end of the tracking detector data acquisition system of a pre-clinical prototype scanner for proton computed tomography (pCT). The scanner is to be capable of measuring one to two million proton tracks per second, so the chip must be able to digitize the data and send it out rapidly while keeping the front-end amplifiers active at all times. One chip handles 64 consecutive channels, including logic for control, calibration, triggering, buffering, and zero suppression. It outputs a formatted cluster list for each trigger, and a set of field programmable gate arrays merges those lists from many chips to build the events to be sent to the data acquisition computer. The chip design has been fabricated, and subsequent tests have demonstrated that it meets all of its performance requirements, including excellent low-noise performance.

  16. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

    Science.gov (United States)

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-27

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

  17. Automated Parallel Computing Tools for Multicore Machines and Clusters, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to improve productivity of high performance computing for applications on multicore computers and clusters. These machines built from one or more chips...

  18. Computer Architecture A Quantitative Approach

    CERN Document Server

    Hennessy, John L

    2007-01-01

    The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelis

  19. Prototype detection unit for the CHIPS experiment

    Science.gov (United States)

    Pfützner, Maciej M.

    2017-09-01

    CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

  20. A novel conductive-polymer-based integration process for high-performance flip-chip packages

    Science.gov (United States)

    Lohokare, Saurabh

    Conductive polymers have recently attracted considerable attention for low-temperature fabrication of lead-free, reworkable, and flexible flip-chip interconnects. Using these materials, I demonstrate in this thesis a process that enables low-cost and high-resolution flip-chip interconnects using conventional micro-fabrication techniques. This fabrication process offers improved performance as compared to conventional flip-chip techniques, such as screen-printing, and allows for definition of interconnects with excellent surface uniformity and control over the bump profile. In order to demonstrate the utility and wide applicability of this process, several test implementations that serve as case studies were investigated. Specifically, novel InGaAsSb avalanche photodiodes (APDs), operating around lambda = 2m and targeted for free-space communication and biomedical spectroscopy applications, were fabricated and flip-chip-integrated to test the static electrical characteristics of the polymer bumps. Additionally, the dynamic electrical performance characteristics of the polymer bumps were studied by using AlGaAsSb/AlGaSb p-i-n photodetectors as a case study. The fabrication of these photodetectors, operating around lambda = 1.55mum and targeted for optical communication applications, was accomplished using a customized inductively coupled plasma (ICP) etch process that resulted in a low dark current and excellent speed (3dB bandwidth of 10GHz) and, responsivity (60% external quantum efficiency) characteristics. Furthermore, flip-chip integration was used to demonstrate a three-dimensional, point-to-point micro-optical interconnect, which was 2.33mm-long in a system 15.27mm3 in volume. Lastly, high-speed parallel optical interconnects were demonstrated using polymer-flip-chip-integrated 10GHz vertical-cavity surface-emitting laser (VCSEL) and DOEs. Such interconnects offer the ability to alleviate the communication bottleneck that is projected to occur in future, high

  1. A hidden Ising model for ChIP-chip data analysis

    KAUST Repository

    Mo, Q.

    2010-01-28

    Motivation: Chromatin immunoprecipitation (ChIP) coupled with tiling microarray (chip) experiments have been used in a wide range of biological studies such as identification of transcription factor binding sites and investigation of DNA methylation and histone modification. Hidden Markov models are widely used to model the spatial dependency of ChIP-chip data. However, parameter estimation for these models is typically either heuristic or suboptimal, leading to inconsistencies in their applications. To overcome this limitation and to develop an efficient software, we propose a hidden ferromagnetic Ising model for ChIP-chip data analysis. Results: We have developed a simple, but powerful Bayesian hierarchical model for ChIP-chip data via a hidden Ising model. Metropolis within Gibbs sampling algorithm is used to simulate from the posterior distribution of the model parameters. The proposed model naturally incorporates the spatial dependency of the data, and can be used to analyze data with various genomic resolutions and sample sizes. We illustrate the method using three publicly available datasets and various simulated datasets, and compare it with three closely related methods, namely TileMap HMM, tileHMM and BAC. We find that our method performs as well as TileMap HMM and BAC for the high-resolution data from Affymetrix platform, but significantly outperforms the other three methods for the low-resolution data from Agilent platform. Compared with the BAC method which also involves MCMC simulations, our method is computationally much more efficient. Availability: A software called iChip is freely available at http://www.bioconductor.org/. Contact: moq@mskcc.org. © The Author 2010. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oxfordjournals.org.

  2. The impact of CHIP premium increases on insurance outcomes among CHIP eligible children.

    Science.gov (United States)

    Nikolova, Silviya; Stearns, Sally

    2014-03-03

    Within the United States, public insurance premiums are used both to discourage private health policy holders from dropping coverage and to reduce state budget costs. Prior research suggests that the odds of having private coverage and being uninsured increase with increases in public insurance premiums. The aim of this paper is to test effects of Children's Health Insurance Program (CHIP) premium increases on public insurance, private insurance, and uninsurance rates. The fact that families just below and above a state-specific income cut-off are likely very similar in terms of observable and unobservable characteristics except the premium contribution provides a natural experiment for estimating the effect of premium increases. Using 2003 Medical Expenditure Panel Survey (MEPS) merged with CHIP premiums, we compare health insurance outcomes for CHIP eligible children as of January 2003 in states with a two-tier premium structure using a cross-sectional regression discontinuity methodology. We use difference-in-differences analysis to compare longitudinal insurance outcomes by December 2003. Higher CHIP premiums are associated with higher likelihood of private insurance. Disenrollment from CHIP in response to premium increases over time does not increase the uninsurance rate. When faced with higher CHIP premiums, private health insurance may be a preferable alternative for CHIP eligible families with higher incomes. Therefore, competition in the insurance exchanges being formed under the Affordable Care Act could enhance choice.

  3. A compact PE memory for vision chips

    Science.gov (United States)

    Cong, Shi; Zhe, Chen; Jie, Yang; Nanjian, Wu; Zhihua, Wang

    2014-09-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.

  4. A compact PE memory for vision chips

    International Nuclear Information System (INIS)

    Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

    2014-01-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

  5. Variation Tolerant On-Chip Interconnects

    CERN Document Server

    Nigussie, Ethiopia Enideg

    2012-01-01

    This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

  6. Microplasma fabrication: from semiconductor technology for 2D-chips and microfluidic channels to rapid prototyping and 3D-printing of microplasma devices

    Science.gov (United States)

    Shatford, R.; Karanassios, Vassili

    2014-05-01

    Microplasmas are receiving attention in recent conferences and current scientific literature. In our laboratory, microplasmas-on-chips proved to be particularly attractive. The 2D- and 3D-chips we developed became hybrid because they were fitted with a quartz plate (quartz was used due to its transparency to UV). Fabrication of 2D- and 3D-chips for microplasma research is described. The fabrication methods described ranged from semiconductor fabrication technology, to Computer Numerical Control (CNC) machining, to 3D-printing. These methods may prove to be useful for those contemplating in entering microplasma research but have no access to expensive semiconductor fabrication equipment.

  7. Experiment list: SRX180159 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available sd || cell type=hemogenic endothelium || chip antibody=CEBPb || chip antibody vendor=santa cruz biotechnol...ogy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachData/bw/SRX180159.bw http://

  8. Experiment list: SRX112178 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available line=OS25 ES cells || chip antibody=8WG16 (MMS-126R, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads...=Magnetic beads http://dbarchive.biosciencedbc.jp/kyushu-u/mm

  9. Experiment list: SRX319550 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e embryonic stem cells || genotype/variation=expressing Flag-bio tagged Myc || chip beads=Dynabeads MyOne Streptavidin T1 || chip bea...ds vendor=Invitrogen http://dbarchive.biosciencedbc.jp/k

  10. Experiment list: SRX319556 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ype=mouse embryonic stem cells || genotype/variation=expressing Flag-bio tagged Dax1 || chip beads=Dynabeads... MyOne Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.bioscienc

  11. Experiment list: SRX112184 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available line=OS25 ES cells || chip antibody=CTD4H8 (MMS-128P, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads...=Sepharose beads http://dbarchive.biosciencedbc.jp/kyushu-u/m

  12. Experiment list: SRX319558 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available | cell type=mouse embryonic stem cells || genotype/variation=expressing control BirA || chip beads=Dynabeads... MyOne Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.bioscienc

  13. Experiment list: SRX319553 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available se embryonic stem cells || genotype/variation=expressing Flag-bio tagged Tip60 || chip beads=Dynabeads MyOne... Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.biosciencedbc.j

  14. Experiment list: SRX319557 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available se embryonic stem cells || genotype/variation=expressing Flag-bio tagged Nanog || chip beads=Dynabeads MyOne... Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.biosciencedbc.j

  15. Experiment list: SRX319555 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ype=mouse embryonic stem cells || genotype/variation=expressing Flag-bio tagged Dax1 || chip beads=Dynabeads... MyOne Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.bioscienc

  16. Experiment list: SRX319551 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available use embryonic stem cells || genotype/variation=expressing Flag-bio tagged Dmap1 || chip beads=Dynabeads MyOn...e Streptavidin T1 || chip beads vendor=Invitrogen http://dbarchive.biosciencedbc.

  17. Experiment list: SRX185907 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available Homo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-...7 || cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_

  18. Experiment list: SRX367330 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nology) || sirna transfection=siBrd4 http://dbarchive.bi...=HEK293T cell || cell line=Human Embryonic Kidney 293 cells || chip antibody=CDK9 || chip antibody details=2316S (Cell Signaling Tech

  19. Experiment list: SRX367328 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nology) || sirna transfection=siCTL http://dbarchive.bio...=HEK293T cell || cell line=Human Embryonic Kidney 293 cells || chip antibody=CDK9 || chip antibody details=2316S (Cell Signaling Tech

  20. Development of gold based solder candidates for flip chip assembly

    DEFF Research Database (Denmark)

    Chidambaram, Vivek; Hald, John; Hattel, Jesper Henri

    2009-01-01

    Flip chip technology is now rapidly replacing the traditional wire bonding interconnection technology in the first level packaging applications due to the miniaturization drive in the microelectronics industry. Flip chip assembly currently involves the use of high lead containing solders...

  1. Experiment list: SRX543048 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/ea...CID.adh murine thymic lymphoma || development stage=DN3 || chip antibody=rabbit anti-Miz-1 || chip antibody vendor=Santa Cruz Biotech

  2. Lab-on a-Chip

    Science.gov (United States)

    1999-01-01

    Labs on chips are manufactured in many shapes and sizes and can be used for numerous applications, from medical tests to water quality monitoring to detecting the signatures of life on other planets. The eight holes on this chip are actually ports that can be filled with fluids or chemicals. Tiny valves control the chemical processes by mixing fluids that move in the tiny channels that look like lines, connecting the ports. Scientists at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama designed this chip to grow biological crystals on the International Space Station (ISS). Through this research, they discovered that this technology is ideally suited for solving the challenges of the Vision for Space Exploration. For example, thousands of chips the size of dimes could be loaded on a Martian rover looking for biosignatures of past or present life. Other types of chips could be placed in handheld devices used to monitor microbes in water or to quickly conduct medical tests on astronauts. The portable, handheld Lab-on-a Chip Application Development Portable Test System (LOCAD-PTS) made its debut flight aboard Discovery during the STS-116 mission launched December 9, 2006. The system allowed crew members to monitor their environment for problematic contaminants such as yeast, mold, and even E.coli, and salmonella. Once LOCAD-PTS reached the ISS, the Marshall team continued to manage the experiment, monitoring the study from a console in the Payload Operations Center at MSFC. The results of these studies will help NASA researchers refine the technology for future Moon and Mars missions. (NASA/MSFC/D.Stoffer)

  3. Biostability of an implantable glucose sensor chip

    Science.gov (United States)

    Fröhlich, M.; Birkholz, M.; Ehwald, K. E.; Kulse, P.; Fursenko, O.; Katzer, J.

    2012-12-01

    Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and Ra roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

  4. Biostability of an implantable glucose sensor chip

    International Nuclear Information System (INIS)

    Fröhlich, M; Ehwald, K E; Kulse, P; Fursenko, O; Katzer, J; Birkholz, M

    2012-01-01

    Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO 2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and R a roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

  5. Modified precision-husky progrind H-3045 for chipping biomass

    Science.gov (United States)

    Dana Mitchell; Fernando Seixas; John. Klepac

    2008-01-01

    A specific size of whole tree chip was needed to co-mill wood chips with coal. The specifications are stringent because chips must be mixed with coal, as opposed to a co-firing process. In co-firing, two raw products are conveyed separately to a boiler. In co-milling, such as at Alabama Power's Plant Gadsden, the chip and coal mix must pass through a series of...

  6. Silicon microstrip detectors with SVX chip readout

    International Nuclear Information System (INIS)

    Brueckner, W.; Dropmann, F.; Godbersen, M.; Konorov, I.; Koenigsmann, K.; Masciocchi, S.; Newsom, C.; Paul, S.; Povh, B.; Russ, J.S.; Timm, S.; Vorwalter, K.; Werding, R.

    1995-01-01

    A new silicon strip detector has been designed for the fixed target experiment WA89 at CERN. The system of about 30 000 channels is equipped with SVX chips and read out via a double buffer into a FASTBUS memory. The detector provides a fast readout by offering zero-suppressed data extraction on the chip. The silicon counters are the largest detectors built on a monocrystal so far in order to achieve good transversal acceptance. Construction and performance during the 1993 data taking run are discussed. ((orig.))

  7. MCMII and the TriP chip

    Energy Technology Data Exchange (ETDEWEB)

    Juan Estrada et al.

    2003-12-19

    We describe the development of the electronics that will be used to read out the Fiber Tracker and Preshower detectors in Run IIb. This electronics is needed for operation at 132ns bunch crossing, and may provide a measurement of the z coordinate of the Fiber Tracker hits when operating at 396ns bunch crossing. Specifically, we describe the design and preliminary tests of the Trip chip, MCM IIa, MCM IIb and MCM IIc. This document also serves as a user manual for the Trip chip and the MCM.

  8. Challenges in physical chip design

    NARCIS (Netherlands)

    Otten, R.H.J.M.; Stravers, P.

    2000-01-01

    On behalf of the ICCAD-2000 Executive and Technical Program Committees, I would like to welcome you tothe International Conference on Computer-Aided Design, which will take place between November 5-9 at theSan Jose DoubleTree Hotel. The technical program for ICCAD-2000 was assembled by a program

  9. Protein folding on a chip

    CERN Multimedia

    2004-01-01

    "Scientists at the U.S. Department of Energy's Brookhaven National Laboratory are proposing to use a super- computer originally developed to simulate elementary particles in high- energy physics to help determine the structures and functions of proteins, including, for example, the 30,000 or so proteins encoded by the human genome" (1 page)

  10. A Neuron- and a Synapse Chip for Artificial Neural Networks

    DEFF Research Database (Denmark)

    Lansner, John; Lehmann, Torsten

    1992-01-01

    A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where...

  11. Developing an Integrated Design Strategy for Chip Layout Optimization

    NARCIS (Netherlands)

    Wits, Wessel Willems; Jauregui Becker, Juan Manuel; van Vliet, Frank Edward; te Riele, G.J.

    2011-01-01

    This paper presents an integrated design strategy for chip layout optimization. The strategy couples both electric and thermal aspects during the conceptual design phase to improve chip performances; thermal management being one of the major topics. The layout of the chip circuitry is optimized

  12. Wood chip delivery and research project at Mikkeli region

    International Nuclear Information System (INIS)

    Saksa, T.; Auvinen, P.

    1995-01-01

    In 1994, a large-scale energywood production chain was started as a co-operation project by the Mikkeli city forest office and local forestry societies. Over 60 000 m 3 (about 46 000 MWh of energy) of forest processed chips were delivered to Pursiala heat and power plant in Mikkeli. About 60 % of these chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 51 FIM/m 3 (68 FIM/MWh) for the whole tree chips and 40 FIM/m 3 (53 FIM/MWh) for logging waste chips. The delivery costs of wood chips could compete with those of fuel peat only in the most favourable cases. The resources of forest processed chips were studied on the basis of forestry plans. According to the study, there is enough raw material for permanent, large-scale delivery of forest processed chips (up to 250 000 m 3 /a) in the forests located at a distance of under 40 road kilometers from the Pursiala heat and power plant. The following project stages will involve further development of the wood chip delivery chain logistics, as well as improvement of logging and chipping equipment and methods in energywood and logging waste production. Also the effects of wood energy production on the economy and environment of the whole Mikkeli region will be studied. (author)

  13. Experiment list: SRX485203 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346544: Rhino ChIP from control germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq ...source_name=Rhino ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult ||... Sex=female || tissue=ovary || germline knock-down=control || chip antibody=custo

  14. Experiment list: SRX485202 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346543: Rhino ChIP from control germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq ...source_name=Rhino ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult ||... Sex=female || tissue=ovary || germline knock-down=control || chip antibody=custo

  15. Experiment list: SRX485205 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 46546: Rhino ChIP from deadlock germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=R...hino ChIP from deadlock germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female ...|| tissue=ovary || germline knock-down=deadlock || chip antibody=custom-made rabb

  16. Experiment list: SRX485212 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346553: Cutoff ChIP from cutoff germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=C...utoff ChIP from cutoff germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female |...| tissue=ovary || germline knock-down=cutoff || chip antibody=custom-made rabbit

  17. Experiment list: SRX485210 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 6551: Deadlock ChIP from deadlock germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name...=Deadlock ChIP from deadlock germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fe...male || tissue=ovary || germline knock-down=deadlock || chip antibody=custom-made

  18. Experiment list: SRX485220 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 53 GSM1346561: RNA Polymerase II ChIP from rhino germline knock-down ovaries; Drosophila melanogaster; ChIP-...Seq source_name=RNA Polymerase II ChIP from rhino germline knock-down ovaries || developmental stage=4-6 day...s old adult || Sex=female || tissue=ovary || germline knock-down=rhino || chip an

  19. Experiment list: SRX485211 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346552: Cutoff ChIP from control germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=...Cutoff ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female... || tissue=ovary || germline knock-down=control || chip antibody=custom-made rabb

  20. Experiment list: SRX485204 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346545: Rhino ChIP from rhino germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=Rhi...no ChIP from rhino germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female || ti...ssue=ovary || germline knock-down=rhino || chip antibody=custom-made rabbit polyc

  1. Experiment list: SRX485208 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346549: Rhino ChIP from piwi germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq sou...rce_name=Rhino ChIP from piwi germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=piwi || chip antibody=custom-made ra

  2. Experiment list: SRX485206 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346547: Rhino ChIP from cutoff germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_name=Rh...ino ChIP from cutoff germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female || ...tissue=ovary || germline knock-down=cutoff || chip antibody=custom-made rabbit po

  3. Experiment list: SRX485209 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 346550: Deadlock ChIP from control germline knock-down ovaries; Drosophila melanogaster; ChIP-Seq source_nam...e=Deadlock ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fe...male || tissue=ovary || germline knock-down=control || chip antibody=custom-made

  4. Energy Model of Networks-on-Chip and a Bus

    NARCIS (Netherlands)

    Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jürgen; Nurmi, J.; Takala, J.; Hamalainen, T.D.

    2005-01-01

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both

  5. Experiment list: SRX110782 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e3 (ab6002, abcam), Pol II (CTD4H8, Millipore) || chip antibody 1 manufacturer=ab...cam || chip antibody 2=Pol II (CTD4H8, Millipore) || chip antibody 2 manufacturer=Millipore http://dbarchive

  6. Geometric Algorithms for Private-Cache Chip Multiprocessors

    DEFF Research Database (Denmark)

    Ajwani, Deepak; Sitchinava, Nodari; Zeh, Norbert

    2010-01-01

    -D convex hulls. These results are obtained by analyzing adaptations of either the PEM merge sort algorithm or PRAM algorithms. For the second group of problems—orthogonal line segment intersection reporting, batched range reporting, and related problems—more effort is required. What distinguishes......We study techniques for obtaining efficient algorithms for geometric problems on private-cache chip multiprocessors. We show how to obtain optimal algorithms for interval stabbing counting, 1-D range counting, weighted 2-D dominance counting, and for computing 3-D maxima, 2-D lower envelopes, and 2...... these problems from the ones in the previous group is the variable output size, which requires I/O-efficient load balancing strategies based on the contribution of the individual input elements to the output size. To obtain nearly optimal algorithms for these problems, we introduce a parallel distribution...

  7. Selective Attention in Multi-Chip Address-Event Systems

    Directory of Open Access Journals (Sweden)

    Giacomo Indiveri

    2009-06-01

    Full Text Available Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the “Selective Attention Chip” (SAC, which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

  8. An analog VLSI chip emulating polarization vision of Octopus retina.

    Science.gov (United States)

    Momeni, Massoud; Titus, Albert H

    2006-01-01

    Biological systems provide a wealth of information which form the basis for human-made artificial systems. In this work, the visual system of Octopus is investigated and its polarization sensitivity mimicked. While in actual Octopus retina, polarization vision is mainly based on the orthogonal arrangement of its photoreceptors, our implementation uses a birefringent micropolarizer made of YVO4 and mounted on a CMOS chip with neuromorphic circuitry to process linearly polarized light. Arranged in an 8 x 5 array with two photodiodes per pixel, each consuming typically 10 microW, this circuitry mimics both the functionality of individual Octopus retina cells by computing the state of polarization and the interconnection of these cells through a bias-controllable resistive network.

  9. On the Scalability of Time-predictable Chip-Multiprocessing

    DEFF Research Database (Denmark)

    Puffitsch, Wolfgang; Schoeberl, Martin

    2012-01-01

    Real-time systems need a time-predictable execution platform to be able to determine the worst-case execution time statically. In order to be time-predictable, several advanced processor features, such as out-of-order execution and other forms of speculation, have to be avoided. However, just using...... simple processors is not an option for embedded systems with high demands on computing power. In order to provide high performance and predictability we argue to use multiprocessor systems with a time-predictable memory interface. In this paper we present the scalability of a Java chip......-multiprocessor system that is designed to be time-predictable. Adding time-predictable caches is mandatory to achieve scalability with a shared memory multi-processor system. As Java bytecode retains information about the nature of memory accesses, it is possible to implement a memory hierarchy that takes...

  10. On-chip electrochromic micro display for a disposable bio-sensor chip

    Science.gov (United States)

    Zhu, Yanjun; Tsukamoto, Takashiro; Tanaka, Shuji

    2017-12-01

    This paper reports an on-chip electrochromic micro display made of polyaniline (PANi) which can be easily made on a CMOS chip. Micro-patterned PANi thin films were selectively deposited on pre-patterned microelectrodes by using electrodeposition. The optimum conditions for deposition and electrochromism were investigated. An 8-pixel on-chip micro display was made on a Si chip. The color of each PANi film could be independently but simultaneously controlled, which means any 1-byte digital data could be displayed on the display. The PANi display had a response time as fast as about 100 ms, which means the transfer data rate was as fast as 80 bits per second.

  11. Safety-critical Java with cyclic executives on chip-multiprocessors

    DEFF Research Database (Denmark)

    Ravn, Anders P.; Schoeberl, Martin

    2012-01-01

    Chip-multiprocessors offer increased processing power at a low cost. However, in order to use them for real-time systems, tasks have to be scheduled efficiently and predictably. It is well known that finding optimal schedules is a computationally hard problem. In this paper we present a solution ...... for multiprocessors, we have implemented it in the context of safety-critical Java on a Java processor....

  12. A Neuromorphic Approach for Tracking using Dynamic Neural Fields on a Programmable Vision-chip

    OpenAIRE

    Martel Julien N.P.; Sandamirskaya Yulia

    2016-01-01

    In artificial vision applications, such as tracking, a large amount of data captured by sensors is transferred to processors to extract information relevant for the task at hand. Smart vision sensors offer a means to reduce the computational burden of visual processing pipelines by placing more processing capabilities next to the sensor. In this work, we use a vision-chip in which a small processor with memory is located next to each photosensitive element. The architecture of this device is ...

  13. "Hook"-calibration of GeneChip-microarrays: Chip characteristics and expression measures

    Directory of Open Access Journals (Sweden)

    Krohn Knut

    2008-08-01

    Full Text Available Abstract Background Microarray experiments rely on several critical steps that may introduce biases and uncertainty in downstream analyses. These steps include mRNA sample extraction, amplification and labelling, hybridization, and scanning causing chip-specific systematic variations on the raw intensity level. Also the chosen array-type and the up-to-dateness of the genomic information probed on the chip affect the quality of the expression measures. In the accompanying publication we presented theory and algorithm of the so-called hook method which aims at correcting expression data for systematic biases using a series of new chip characteristics. Results In this publication we summarize the essential chip characteristics provided by this method, analyze special benchmark experiments to estimate transcript related expression measures and illustrate the potency of the method to detect and to quantify the quality of a particular hybridization. It is shown that our single-chip approach provides expression measures responding linearly on changes of the transcript concentration over three orders of magnitude. In addition, the method calculates a detection call judging the relation between the signal and the detection limit of the particular measurement. The performance of the method in the context of different chip generations and probe set assignments is illustrated. The hook method characterizes the RNA-quality in terms of the 3'/5'-amplification bias and the sample-specific calling rate. We show that the proper judgement of these effects requires the disentanglement of non-specific and specific hybridization which, otherwise, can lead to misinterpretations of expression changes. The consequences of modifying probe/target interactions by either changing the labelling protocol or by substituting RNA by DNA targets are demonstrated. Conclusion The single-chip based hook-method provides accurate expression estimates and chip-summary characteristics

  14. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    OpenAIRE

    Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

  15. Results of irriadiating the APV5 chip

    CERN Document Server

    Raymond, M

    1996-01-01

    An APV5 chip has been irradiated in steps up to 16 Mrads using a Co-60 source in order to confirm the radiation hardness expected from individual transistor and sub-circuit measurements. Full functionality is preserved after irradiation and measurements of the amplifier pulse shape and noise are presented.

  16. Chip based electroanalytical systems for cell analysis

    DEFF Research Database (Denmark)

    Spegel, C.; Heiskanen, A.; Skjolding, L.H.D.

    2008-01-01

    ' measurements of processes related to living cells, i.e., systems without lysing the cells. The focus is on chip based amperometric and impedimetric cell analysis systems where measurements utilizing solely carbon fiber microelectrodes (CFME) and other nonchip electrode formats, such as CFME for exocytosis...

  17. Increasing security in inter-chip communication

    Science.gov (United States)

    Edwards, Nathan J; Hamlet, Jason; Bauer, Todd; Helinski, Ryan

    2014-10-28

    An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both.

  18. Cytostretch, an Organ-on-Chip Platform

    NARCIS (Netherlands)

    Gaio, N.; van Meer, B.; Quiros Solano, W.F.; Bergers, L.; van de Stolpe, A; Mummery, CL; Sarro, P.M.; Dekker, R.

    2016-01-01

    Organ-on-Chips (OOCs) are micro-fabricated devices which are used to culture cells in order to mimic functional units of human organs. The devices are designed to simulate the physiological environment of tissues in vivo. Cells in some types of OOCs can be stimulated in situ by electrical and/or

  19. Microprocessors: From basic chips to complete systems

    International Nuclear Information System (INIS)

    Dobinson, R.W.

    1985-01-01

    These lectures aim to present and explain in general terms some of the characteristics of microprocessor chips and associated components. They show how systems are synthesized from the basic integrated circuit building blocks which are currently available; processor, memory, input-output (I/0) devices, etc. (orig./HSI)

  20. Potential roughness near lithographically fabricated atom chips

    DEFF Research Database (Denmark)

    Krüger, Peter; Andersson, L. M.; Wildermuth, Stefan

    2007-01-01

    Potential roughness has been reported to severely impair experiments in magnetic microtraps. We show that these obstacles can be overcome as we measure disorder potentials that are reduced by two orders of magnitude near lithographically patterned high-quality gold layers on semiconductor atom chip...

  1. Smart Chips for Smart Surroundings -- 4S

    NARCIS (Netherlands)

    Schuler, Eberhard; König, Ralf; Becker, Jürgen; Rauwerda, G.K.; van de Burgwal, M.D.; Smit, Gerardus Johannes Maria; Cardoso, João M.P.; Hübner, Michael

    2011-01-01

    The overall mission of the 4S project (Smart Chips for Smart Surroundings) was to define and develop efficient flexible, reconfigurable core building blocks, including the supporting tools, for future Ambient System Devices. Reconfigurability offers the needed flexibility and adaptability, it

  2. On-chip mode division multiplexing technologies

    DEFF Research Database (Denmark)

    Ding, Yunhong; Frellsen, Louise Floor; Guan, Xiaowei

    2016-01-01

    Space division multiplexing (SDM) is currently widely investigated in order to provide enhanced capacity thanks to the utilization of space as a new degree of multiplexing freedom in both optical fiber communication and on-chip interconnects. Basic components allowing the processing of spatial...... photonic integrated circuit mode (de) multiplexer for few-mode fibers (FMFs)....

  3. What's A Pixel Particle Sensor Chip?

    CERN Multimedia

    2008-01-01

    ATLAS particle physics experiment aided with collaboration ON Semiconductor was recently honored by the European Council for Nuclear Research (CERN), with an Industrial Award recognizing the company's contribution in supplying complex "Pixel Particle Sensor" chips for use in CERN's ATLAS particle physics experiment.

  4. Microarrays (DNA Chips) for the Classroom Laboratory

    Science.gov (United States)

    Barnard, Betsy; Sussman, Michael; BonDurant, Sandra Splinter; Nienhuis, James; Krysan, Patrick

    2006-01-01

    We have developed and optimized the necessary laboratory materials to make DNA microarray technology accessible to all high school students at a fraction of both cost and data size. The primary component is a DNA chip/array that students "print" by hand and then analyze using research tools that have been adapted for classroom use. The…

  5. Drying characteristics of willow chips and stems

    NARCIS (Netherlands)

    Gigler, J.K.; Loon, van W.K.P.; Seres, I.; Meerdink, G.; Coumans, W.J.

    2000-01-01

    In supply chains of willow (Salix viminalis) biomass to energy plants, drying is advisable in order to enable safe long-term storage, increase boiler efficiency and reduce gaseous emissions. To gain insight into the drying process, drying characteristics of willow chips and stems were investigated

  6. Atom chips: mesoscopic physics with cold atoms

    International Nuclear Information System (INIS)

    Krueger, P.; Wildermuth, S.; Hofferberth, S.; Haller, E.; GAllego Garcia, D.; Schmiedmayer, J.

    2005-01-01

    Full text: Cold neutral atoms can be controlled and manipulated in microscopic potentials near surfaces of atom chips. These integrated micro-devices combine the known techniques of atom optics with the capabilities of well established micro- and nanofabrication technology. In analogy to electronic microchips and integrated fiber optics, the concept of atom chips is suitable to explore the domain of mesoscopic physics with matter waves. We use current and charge carrying structures to form complex potentials with high spatial resolution only microns from the surface. In particular, atoms can be confined to an essentially one-dimensional motion. In this talk, we will give an overview of our experiments studying the manipulation of both thermal atoms and BECs on atom chips. First experiments in the quasi one-dimensional regime will be presented. These experiments profit from strongly reduced residual disorder potentials caused by imperfections of the chip fabrication with respect to previously published experiments. This is due to our purely lithographic fabrication technique that proves to be advantageous over electroplating. We have used one dimensionally confined BECs as an ultra-sensitive probe to characterize these potentials. These smooth potentials allow us to explore various aspects of the physics of degenerate quantum gases in low dimensions. (author)

  7. On-chip steering of entangled photons in nonlinear photonic crystals.

    Science.gov (United States)

    Leng, H Y; Yu, X Q; Gong, Y X; Xu, P; Xie, Z D; Jin, H; Zhang, C; Zhu, S N

    2011-08-16

    One promising technique for working toward practical photonic quantum technologies is to implement multiple operations on a monolithic chip, thereby improving stability, scalability and miniaturization. The on-chip spatial control of entangled photons will certainly benefit numerous applications, including quantum imaging, quantum lithography, quantum metrology and quantum computation. However, external optical elements are usually required to spatially control the entangled photons. Here we present the first experimental demonstration of on-chip spatial control of entangled photons, based on a domain-engineered nonlinear photonic crystal. We manipulate the entangled photons using the inherent properties of the crystal during the parametric downconversion, demonstrating two-photon focusing and beam-splitting from a periodically poled lithium tantalate crystal with a parabolic phase profile. These experimental results indicate that versatile and precise spatial control of entangled photons is achievable. Because they may be operated independent of any bulk optical elements, domain-engineered nonlinear photonic crystals may prove to be a valuable ingredient in on-chip integrated quantum optics.

  8. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif; Salama, Khaled N.; Sedky, S.; Soliman, E. A.

    2012-01-01

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  9. On-chip antenna: Practical design and characterization considerations

    KAUST Repository

    Shamim, Atif

    2012-07-28

    This paper highlights the challenges of an emergent field, namely, on-chip antenna design. Consistent with the RF System-on-Chip (SoC) concept, co-design strategy for circuits and on-chip antennas is described. A number of design and layout issues, arising from the highly integrated nature of this kind of systems, are discussed. The characterization difficulties related to on-chip antennas radiation properties are also highlighted. Finally, a novel on-wafer test fixture is proposed to measure the gain and radiation pattern of the on-chip antennas in the anechoic chamber.

  10. Introduction to computer networking

    CERN Document Server

    Robertazzi, Thomas G

    2017-01-01

    This book gives a broad look at both fundamental networking technology and new areas that support it and use it. It is a concise introduction to the most prominent, recent technological topics in computer networking. Topics include network technology such as wired and wireless networks, enabling technologies such as data centers, software defined networking, cloud and grid computing and applications such as networks on chips, space networking and network security. The accessible writing style and non-mathematical treatment makes this a useful book for the student, network and communications engineer, computer scientist and IT professional. • Features a concise, accessible treatment of computer networking, focusing on new technological topics; • Provides non-mathematical introduction to networks in their most common forms today;< • Includes new developments in switching, optical networks, WiFi, Bluetooth, LTE, 5G, and quantum cryptography.

  11. On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

    International Nuclear Information System (INIS)

    Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

    2010-01-01

    We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

  12. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

    Science.gov (United States)

    Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

    2018-04-01

    Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

  13. On-chip particle trapping and manipulation

    Science.gov (United States)

    Leake, Kaelyn Danielle

    The ability to control and manipulate the world around us is human nature. Humans and our ancestors have used tools for millions of years. Only in recent years have we been able to control objects at such small levels. In order to understand the world around us it is frequently necessary to interact with the biological world. Optical trapping and manipulation offer a non-invasive way to move, sort and interact with particles and cells to see how they react to the world around them. Optical tweezers are ideal in their abilities but they require large, non-portable, and expensive setups limiting how and where we can use them. A cheap portable platform is required in order to have optical manipulation reach its full potential. On-chip technology offers a great solution to this challenge. We focused on the Liquid-Core Anti-Resonant Reflecting Optical Waveguide (liquid-core ARROW) for our work. The ARROW is an ideal platform, which has anti-resonant layers which allow light to be guided in liquids, allowing for particles to easily be manipulated. It is manufactured using standard silicon manufacturing techniques making it easy to produce. The planner design makes it easy to integrate with other technologies. Initially I worked to improve the ARROW chip by reducing the intersection losses and by reducing the fluorescence and background on the ARROW chip. The ARROW chip has already been used to trap and push particles along its channel but here I introduce several new methods of particle trapping and manipulation on the ARROW chip. Traditional two beam traps use two counter propagating beams. A trapping scheme that uses two orthogonal beams which counter to first instinct allow for trapping at their intersection is introduced. This scheme is thoroughly predicted and analyzed using realistic conditions. Simulations of this method were done using a program which looks at both the fluidics and optical sources to model complex situations. These simulations were also used to

  14. On-chip photonic synapse.

    Science.gov (United States)

    Cheng, Zengguang; Ríos, Carlos; Pernice, Wolfram H P; Wright, C David; Bhaskaran, Harish

    2017-09-01

    The search for new "neuromorphic computing" architectures that mimic the brain's approach to simultaneous processing and storage of information is intense. Because, in real brains, neuronal synapses outnumber neurons by many orders of magnitude, the realization of hardware devices mimicking the functionality of a synapse is a first and essential step in such a search. We report the development of such a hardware synapse, implemented entirely in the optical domain via a photonic integrated-circuit approach. Using purely optical means brings the benefits of ultrafast operation speed, virtually unlimited bandwidth, and no electrical interconnect power losses. Our synapse uses phase-change materials combined with integrated silicon nitride waveguides. Crucially, we can randomly set the synaptic weight simply by varying the number of optical pulses sent down the waveguide, delivering an incredibly simple yet powerful approach that heralds systems with a continuously variable synaptic plasticity resembling the true analog nature of biological synapses.

  15. Darwinian evolution on a chip.

    Directory of Open Access Journals (Sweden)

    Brian M Paegel

    2008-04-01

    Full Text Available Computer control of Darwinian evolution has been demonstrated by propagating a population of RNA enzymes in a microfluidic device. The RNA population was challenged to catalyze the ligation of an oligonucleotide substrate under conditions of progressively lower substrate concentrations. A microchip-based serial dilution circuit automated an exponential growth phase followed by a 10-fold dilution, which was repeated for 500 log-growth iterations. Evolution was observed in real time as the population adapted and achieved progressively faster growth rates over time. The final evolved enzyme contained a set of 11 mutations that conferred a 90-fold improvement in substrate utilization, coinciding with the applied selective pressure. This system reduces evolution to a microfluidic algorithm, allowing the experimenter to observe and manipulate adaptation.

  16. Applications of holographic on-chip microscopy (Conference Presentation)

    Science.gov (United States)

    Ozcan, Aydogan

    2017-02-01

    My research focuses on the use of computation/algorithms to create new optical microscopy, sensing, and diagnostic techniques, significantly improving existing tools for probing micro- and nano-objects while also simplifying the designs of these analysis tools. In this presentation, I will introduce a set of computational microscopes which use lens-free on-chip imaging to replace traditional lenses with holographic reconstruction algorithms. Basically, 3D images of specimens are reconstructed from their "shadows" providing considerably improved field-of-view (FOV) and depth-of-field, thus enabling large sample volumes to be rapidly imaged, even at nanoscale. These new computational microscopes routinely generate benefit of this technology is that it lends itself to field-portable and cost-effective designs which easily integrate with smartphones to conduct giga-pixel tele-pathology and microscopy even in resource-poor and remote settings where traditional techniques are difficult to implement and sustain, thus opening the door to various telemedicine applications in global health. Through the development of similar computational imagers, I will also report the discovery of new 3D swimming patterns observed in human and animal sperm. One of this newly discovered and extremely rare motion is in the form of "chiral ribbons" where the planar swings of the sperm head occur on an osculating plane creating in some cases a helical ribbon and in some others a twisted ribbon. Shedding light onto the statistics and biophysics of various micro-swimmers' 3D motion, these results provide an important example of how biomedical imaging significantly benefits from emerging computational algorithms/theories, revolutionizing existing tools for observing various micro- and nano-scale phenomena in innovative, high-throughput, and yet cost-effective ways.

  17. Microengineered physiological biomimicry: organs-on-chips.

    Science.gov (United States)

    Huh, Dongeun; Torisawa, Yu-suke; Hamilton, Geraldine A; Kim, Hyun Jung; Ingber, Donald E

    2012-06-21

    Microscale engineering technologies provide unprecedented opportunities to create cell culture microenvironments that go beyond current three-dimensional in vitro models by recapitulating the critical tissue-tissue interfaces, spatiotemporal chemical gradients, and dynamic mechanical microenvironments of living organs. Here we review recent advances in this field made over the past two years that are focused on the development of 'Organs-on-Chips' in which living cells are cultured within microfluidic devices that have been microengineered to reconstitute tissue arrangements observed in living organs in order to study physiology in an organ-specific context and to develop specialized in vitro disease models. We discuss the potential of organs-on-chips as alternatives to conventional cell culture models and animal testing for pharmaceutical and toxicology applications. We also explore challenges that lie ahead if this field is to fulfil its promise to transform the future of drug development and chemical safety testing.

  18. On-Chip Microwave Quantum Hall Circulator

    Directory of Open Access Journals (Sweden)

    A. C. Mahoney

    2017-01-01

    Full Text Available Circulators are nonreciprocal circuit elements that are integral to technologies including radar systems, microwave communication transceivers, and the readout of quantum information devices. Their nonreciprocity arises from the interference of microwaves over the centimeter scale of the signal wavelength, in the presence of bulky magnetic media that breaks time-reversal symmetry. Here, we realize a completely passive on-chip microwave circulator with size 1/1000th the wavelength by exploiting the chiral, “slow-light” response of a two-dimensional electron gas in the quantum Hall regime. For an integrated GaAs device with 330  μm diameter and about 1-GHz center frequency, a nonreciprocity of 25 dB is observed over a 50-MHz bandwidth. Furthermore, the nonreciprocity can be dynamically tuned by varying the voltage at the port, an aspect that may enable reconfigurable passive routing of microwave signals on chip.

  19. Microfluidic chip-capillary electrophoresis devices

    CERN Document Server

    Fung, Ying Sing; Du, Fuying; Guo, Wenpeng; Ma, Tongmei; Nie, Zhou; Sun, Hui; Wu, Ruige; Zhao, Wenfeng

    2015-01-01

    Capillary electrophoresis (CE) and microfluidic chip (MC) devices are relatively mature technologies, but this book demonstrates how they can be integrated into a single, revolutionary device that can provide on-site analysis of samples when laboratory services are unavailable. By introducing the combination of CE and MC technology, Microfluidic Chip-Capillary Electrophoresis Devices broadens the scope of chemical analysis, particularly in the biomedical, food, and environmental sciences. The book gives an overview of the development of MC and CE technology as well as technology that now allows for the fabrication of MC-CE devices. It describes the operating principles that make integration possible and illustrates some achievements already made by the application of MC-CE devices in hospitals, clinics, food safety, and environmental research. The authors envision further applications for private and public use once the proof-of-concept stage has been passed and obstacles to increased commercialization are ad...

  20. Heat toxicant contaminant mitigation in potato chips

    DEFF Research Database (Denmark)

    Mariotti, Maria; Cortes, Pablo; Fromberg, Arvid

    2015-01-01

    Heating foods immersed in oil during frying provides many attractive sensorial attributes including taste, flavor and color. However, some toxic compounds formed during frying of potatoes such as furan and acrylamide may constitute an increased cancer risk for consumers. The objective of this work...... was to mitigate the furan and acrylamide formation in potato chips without increasing their oil uptake by optimizing the blanching treatment before final frying. Potato slices were blanched in order to simultaneously leach out ascorbic acid and reducing sugars, the most important precursors of furan...... and acrylamide generation in thermally treated starchy foods. A central composite design was implemented to optimize the temperature-time blanching conditions under which furan, acrylamide and oil content in potato chips were minimized. The optimum blanching conditions were 64 degrees C and 17 min in which...

  1. Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

    Science.gov (United States)

    Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

    2016-01-01

    The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154

  2. Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

    Science.gov (United States)

    Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

    2016-04-13

    The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

  3. Technology Roadmap: Lab-on-a-Chip

    OpenAIRE

    Pattharaporn Suntharasaj; Tugrul U Daim

    2010-01-01

    With the integration of microfluidic and MEMS technologies, biochips such as the lab-on-a-chip (LOC) devices are at the brink of revolutionizing the medical disease diagnostics industries. Remarkable advancements in the biochips industry are making products resembling Star Trek.s "tricorder" and handheld medical scanners a reality. Soon, doctors can screen for cancer at the molecular level without costly and cumbersome equipments, and discuss treatment plans based on immediate lab results. Th...

  4. Silicon-Chip-Based Optical Frequency Combs

    Science.gov (United States)

    2015-10-26

    fiber-based polarization controllers and a polarization beam splitter , and the output power is monitored with a sensitive photodiode. We use a...a single CW laser beam coupled to a microresonators can produce stabilized, octave-spanning combs through highly cascaded four-wave mixing (FWM...resonator designs , the resonator and the coupling waveguide are monolithically integrated. Thus, the entire on-chip configuration of CMOS-compatible

  5. Routing algorithms in networks-on-chip

    CERN Document Server

    Daneshtalab, Masoud

    2014-01-01

    This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.   ·         Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; ·         Describe...

  6. DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.

    Science.gov (United States)

    Zhou, Xichuan; Li, Shengli; Tang, Fang; Hu, Shengdong; Lin, Zhi; Zhang, Lei

    2017-07-18

    Deep neural networks (NNs) are the state-of-the-art models for understanding the content of images and videos. However, implementing deep NNs in embedded systems is a challenging task, e.g., a typical deep belief network could exhaust gigabytes of memory and result in bandwidth and computational bottlenecks. To address this challenge, this paper presents an algorithm and hardware codesign for efficient deep neural computation. A hardware-oriented deep learning algorithm, named the deep adaptive network, is proposed to explore the sparsity of neural connections. By adaptively removing the majority of neural connections and robustly representing the reserved connections using binary integers, the proposed algorithm could save up to 99.9% memory utility and computational resources without undermining classification accuracy. An efficient sparse-mapping-memory-based hardware architecture is proposed to fully take advantage of the algorithmic optimization. Different from traditional Von Neumann architecture, the deep-adaptive network on chip (DANoC) brings communication and computation in close proximity to avoid power-hungry parameter transfers between on-board memory and on-chip computational units. Experiments over different image classification benchmarks show that the DANoC system achieves competitively high accuracy and efficiency comparing with the state-of-the-art approaches.

  7. On-Chip High-Finesse Fabry-Perot Microcavities for Optical Sensing and Quantum Information

    Directory of Open Access Journals (Sweden)

    Mohammad H. Bitarafan

    2017-07-01

    Full Text Available For applications in sensing and cavity-based quantum computing and metrology, open-access Fabry-Perot cavities—with an air or vacuum gap between a pair of high reflectance mirrors—offer important advantages compared to other types of microcavities. For example, they are inherently tunable using MEMS-based actuation strategies, and they enable atomic emitters or target analytes to be located at high field regions of the optical mode. Integration of curved-mirror Fabry-Perot cavities on chips containing electronic, optoelectronic, and optomechanical elements is a topic of emerging importance. Micro-fabrication techniques can be used to create mirrors with small radius-of-curvature, which is a prerequisite for cavities to support stable, small-volume modes. We review recent progress towards chip-based implementation of such cavities, and highlight their potential to address applications in sensing and cavity quantum electrodynamics.

  8. On-Chip Single-Plasmon Nanocircuit Driven by a Self-Assembled Quantum Dot.

    Science.gov (United States)

    Wu, Xiaofei; Jiang, Ping; Razinskas, Gary; Huo, Yongheng; Zhang, Hongyi; Kamp, Martin; Rastelli, Armando; Schmidt, Oliver G; Hecht, Bert; Lindfors, Klas; Lippitz, Markus

    2017-07-12

    Quantum photonics holds great promise for future technologies such as secure communication, quantum computation, quantum simulation, and quantum metrology. An outstanding challenge for quantum photonics is to develop scalable miniature circuits that integrate single-photon sources, linear optical components, and detectors on a chip. Plasmonic nanocircuits will play essential roles in such developments. However, for quantum plasmonic circuits, integration of stable, bright, and narrow-band single photon sources in the structure has so far not been reported. Here we present a plasmonic nanocircuit driven by a self-assembled GaAs quantum dot. Through a planar dielectric-plasmonic hybrid waveguide, the quantum dot efficiently excites narrow-band single plasmons that are guided in a two-wire transmission line until they are converted into single photons by an optical antenna. Our work demonstrates the feasibility of fully on-chip plasmonic nanocircuits for quantum optical applications.

  9. Microwave potentials and optimal control for robust quantum gates on an atom chip

    International Nuclear Information System (INIS)

    Treutlein, Philipp; Haensch, Theodor W.; Reichel, Jakob; Negretti, Antonio; Cirone, Markus A.; Calarco, Tommaso

    2006-01-01

    We propose a two-qubit collisional phase gate that can be implemented with available atom chip technology and present a detailed theoretical analysis of its performance. The gate is based on earlier phase gate schemes, but uses a qubit state pair with an experimentally demonstrated, very long coherence lifetime. Microwave near fields play a key role in our implementation as a means to realize the state-dependent potentials required for conditional dynamics. Quantum control algorithms are used to optimize gate performance. We employ circuit configurations that can be built with current fabrication processes and extensively discuss the impact of technical noise and imperfections that characterize an actual atom chip. We find an overall infidelity compatible with requirements for fault-tolerant quantum computation

  10. Color development and acrylamide content of pre-dried potato chips

    DEFF Research Database (Denmark)

    Pedreschi, Franco; León, Jorge; Mery, Domingo

    2007-01-01

    The objective of this work was to study the development of color formation in pre-dried potato slices during frying and acrylamide formation in the final potato chips. Color measurement was done by using an inexpensive computer vision technique which allowed quantifying representatively...... and precisely the color of complex surfaces such as those of potato chips in L*a*b* units from RGB images. Prior to frying, potato slices (Desiree variety, diameter: 37 mm, width: 2.2 mm) were blanched in hot water at 85 degrees C for 3.5 min. Unblanched slices were considered as the control. Slices of the same...... dimensions were blanched as in the previous step, and then air-dried until reaching a moisture content of 60% (wet basis). These samples were called pre-dried potato slices. Potato slices were fried at 120 degrees C, 140 degrees C, 160 degrees C and 180 degrees C until reaching moisture contents of similar...

  11. On-Chip High-Finesse Fabry-Perot Microcavities for Optical Sensing and Quantum Information.

    Science.gov (United States)

    Bitarafan, Mohammad H; DeCorby, Ray G

    2017-07-31

    For applications in sensing and cavity-based quantum computing and metrology, open-access Fabry-Perot cavities-with an air or vacuum gap between a pair of high reflectance mirrors-offer important advantages compared to other types of microcavities. For example, they are inherently tunable using MEMS-based actuation strategies, and they enable atomic emitters or target analytes to be located at high field regions of the optical mode. Integration of curved-mirror Fabry-Perot cavities on chips containing electronic, optoelectronic, and optomechanical elements is a topic of emerging importance. Micro-fabrication techniques can be used to create mirrors with small radius-of-curvature, which is a prerequisite for cavities to support stable, small-volume modes. We review recent progress towards chip-based implementation of such cavities, and highlight their potential to address applications in sensing and cavity quantum electrodynamics.

  12. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

    International Nuclear Information System (INIS)

    Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

    2013-01-01

    A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

  13. A fast template matching method for LED chip Localization

    Directory of Open Access Journals (Sweden)

    Zhong Fuqiang

    2015-01-01

    Full Text Available Efficiency determines the profits of the semiconductor producers. So the producers spare no effort to enhance the efficiency of every procedure. The purpose of the paper is to present a method to shorten the time to locate the LED chips on wafer. The method consists of 3 steps. Firstly, image segmentation and blob analyzation are used to predict the positions of potential chips. Then predict the orientations of potential chips based on their dominant orientations. Finally, according to the positions and orientations predicted above, locate the chips precisely based on gradient orientation features. Experiments show that the algorithm is faster than the traditional method we choose to locate the LED chips. Besides, even the orientations of the chips on wafer are of big deviation to the orientation of the template, the efficiency of this method won't be affected.

  14. A primary battery-on-a-chip using monolayer graphene

    Science.gov (United States)

    Iost, Rodrigo M.; Crespilho, Frank N.; Kern, Klaus; Balasubramanian, Kannan

    2016-07-01

    We present here a bottom-up approach for realizing on-chip on-demand batteries starting out with chemical vapor deposition-grown graphene. Single graphene monolayers contacted by electrode lines on a silicon chip serve as electrodes. The anode and cathode are realized by electrodeposition of zinc and copper respectively onto graphene, leading to the realization of a miniature graphene-based Daniell cell on a chip. The electrolyte is housed partly in a gel and partly in liquid form in an on-chip enclosure molded using a 3d printer or made out of poly(dimethylsiloxane). The realized batteries provide a stable voltage (∼1.1 V) for many hours and exhibit capacities as high as 15 μAh, providing enough power to operate a pocket calculator. The realized batteries show promise for deployment as on-chip power sources for autonomous systems in lab-on-a-chip or biomedical applications.

  15. Modeling ChIP sequencing in silico with applications.

    Directory of Open Access Journals (Sweden)

    Zhengdong D Zhang

    2008-08-01

    Full Text Available ChIP sequencing (ChIP-seq is a new method for genomewide mapping of protein binding sites on DNA. It has generated much excitement in functional genomics. To score data and determine adequate sequencing depth, both the genomic background and the binding sites must be properly modeled. To develop a computational foundation to tackle these issues, we first performed a study to characterize the observed statistical nature of this new type of high-throughput data. By linking sequence tags into clusters, we show that there are two components to the distribution of tag counts observed in a number of recent experiments: an initial power-law distribution and a subsequent long right tail. Then we develop in silico ChIP-seq, a computational method to simulate the experimental outcome by placing tags onto the genome according to particular assumed distributions for the actual binding sites and for the background genomic sequence. In contrast to current assumptions, our results show that both the background and the binding sites need to have a markedly nonuniform distribution in order to correctly model the observed ChIP-seq data, with, for instance, the background tag counts modeled by a gamma distribution. On the basis of these results, we extend an existing scoring approach by using a more realistic genomic-background model. This enables us to identify transcription-factor binding sites in ChIP-seq data in a statistically rigorous fashion.

  16. Solid state silicon based condenser microphone for hearing aid, has transducer chip and IC chip between intermediate chip and openings on both sides of intermediate chip, to allow sound towards diaphragm

    DEFF Research Database (Denmark)

    2000-01-01

    towards diaphragm. Surface of the chip (2) has electrical conductors (14) to connect chip with IC chip (3). USE - For use in miniature electroacoustic devices such as hearing aid. ADVANTAGE - Since sound inlet is covered by filter, dust, moisture and other impurities do not obstruct interior and sound...... inlet of microphone. External electrical connection can be made economically reliable and the thermal stress is avoided with the small size solid state silicon based condenser microphone....

  17. Firing with wood chips in heating and cogeneration plants

    International Nuclear Information System (INIS)

    Kofman, P.D.

    1992-01-01

    The document was produced for use as detailed teaching material aimed at spreading information on the use of wood chips as fuel for heating and cogeneration plants. It includes information and articles on wood fuels generally, combustion values, chopping machines, suppliers, occupational health hazards connected with the handling of wood chips, measuring amounts, the selection of types, prices, ash, environmental aspects and information on the establishment of a wood-chip fired district heating plant. (AB)

  18. Wood chips procurement and research project at the Mikkeli region

    International Nuclear Information System (INIS)

    Saksa, T.; Auvinen, P.

    1996-01-01

    In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m 3 (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m 3 (60 FIM/MWh) for the whole tree chips and 38 FIM/m 3 (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m 3 /ha

  19. Experiment list: SRX485216 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 3K9me3 ChIP from rhino germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_na...me=H3K9me3 ChIP from rhino germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fema...le || tissue=ovary || germline knock-down=rhino || chip antibody=Histone H3K9me3

  20. Experiment list: SRX485222 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 4me2 ChIP from control germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_na...me=H3K4me2 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=fe...male || tissue=ovary || germline knock-down=control || chip antibody=Anti-dimethy

  1. Experiment list: SRX485221 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K4me2 ChIP from control germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_n...ame=H3K4me2 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=control || chip antibody=Anti-dimeth

  2. Experiment list: SRX485215 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from rhino germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_nam...e=H3K9me3 ChIP from rhino germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=femal...e || tissue=ovary || germline knock-down=rhino || chip antibody=Histone H3K9me3 a

  3. Experiment list: SRX485218 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from piwi germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_name...=H3K9me3 ChIP from piwi germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female ...|| tissue=ovary || germline knock-down=piwi || chip antibody=Histone H3K9me3 anti

  4. Experiment list: SRX485213 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from control germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_n...ame=H3K9me3 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=control || chip antibody=Histone H3K

  5. Experiment list: SRX485214 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available K9me3 ChIP from control germline knock-down ovaries, replicate 2; Drosophila melanogaster; ChIP-Seq source_n...ame=H3K9me3 ChIP from control germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=f...emale || tissue=ovary || germline knock-down=control || chip antibody=Histone H3K

  6. Experiment list: SRX485217 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 3K9me3 ChIP from piwi germline knock-down ovaries, replicate 1; Drosophila melanogaster; ChIP-Seq source_nam...e=H3K9me3 ChIP from piwi germline knock-down ovaries || developmental stage=4-6 days old adult || Sex=female... || tissue=ovary || germline knock-down=piwi || chip antibody=Histone H3K9me3 ant

  7. CMOS Image Sensors: Electronic Camera On A Chip

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  8. The Cutting Process, Chips and Cutting Forces in Machining CFRP

    DEFF Research Database (Denmark)

    Koplev, A.; Lystrup, Aage; Vorm, T.

    1983-01-01

    The cutting of unidirectional CFRP, perpendicular as well as parallel to the fibre orientation, is examined. Shaping experiments, ‘quick-stop’ experiments, and a new chip preparation technique are used for the investigation. The formation of the chips, and the quality of the machined surface...... is discussed. The cutting forces parallel and perpendicular to the cutting direction are measured for various parameters, and the results correlated to the formation of chips and the wear of the tool....

  9. A simple clockless Network-on-Chip for a commercial audio DSP chip

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    We design a very small, packet-switched, clockless Network-on-Chip (NoC) as a replacement for the existing crossbar-based communication infrastructure in a commercial audio DSP chip. Both solutions are laid out in a 0.18 um process, and compared in terms of area, power consumption and routing...... to the existing crossbar, it allows all blocks to communicate. The total wire length is decreased by 22% which eases the layout process and makes the design less prone to routing congestion. Not least, the communicating blocks are decoupled by means of the NoC, providing a Globally-Asynchronous, Locally...

  10. Integrated lasers for polymer Lab-on-a-Chip systems

    DEFF Research Database (Denmark)

    Mappes, Timo; Vannahme, Christoph; Grosmann, Tobias

    2012-01-01

    We develop optical Lab-on-a-Chips on different platforms for marker-based and label-free biophotonic sensor applications. Our chips are based on polymers and fabricated by mass production technologies to integrate microfluidic channels, optical waveguides and miniaturized lasers.......We develop optical Lab-on-a-Chips on different platforms for marker-based and label-free biophotonic sensor applications. Our chips are based on polymers and fabricated by mass production technologies to integrate microfluidic channels, optical waveguides and miniaturized lasers....

  11. Ultrasonic Vibration Assisted Grinding of Bio-ceramic Materials: Modeling, Simulation, and Experimental Investigations on Edge Chipping

    Science.gov (United States)

    Tesfay, Hayelom D.

    , and Alumina) were conducted. Based on the experimental results, analytical models for UVAG and CG (conventional grinding without ultrasonic vibration) processes were developed. As for the numerical study, an extended finite element method (XFEM) based on Virtual Crack Closure Technique (VCCT) in ABAQUS was used to model the formation of edge chippings both for UVAG and CG processes. The experimental results are compared against the numerical FEA and the analytical models. The experimental, theoretical, and computational simulation results revealed that the edge chipping size of bioceramics can be significantly reduced with the assistance of ultrasonic vibration. The investigation procedures and the results obtained in this dissertation would be used as a reference and practical guidance for choosing reasonable process variables as well as designing mathematical (analytical and numerical) models in manufacturing industries and academic institutions when the edge chippings of brittle materials are expected to be controlled.

  12. Adiabatic quantum computation and quantum annealing theory and practice

    CERN Document Server

    McGeoch, Catherine C

    2014-01-01

    Adiabatic quantum computation (AQC) is an alternative to the better-known gate model of quantum computation. The two models are polynomially equivalent, but otherwise quite dissimilar: one property that distinguishes AQC from the gate model is its analog nature. Quantum annealing (QA) describes a type of heuristic search algorithm that can be implemented to run in the ``native instruction set'''' of an AQC platform. D-Wave Systems Inc. manufactures {quantum annealing processor chips} that exploit quantum properties to realize QA computations in hardware. The chips form the centerpiece of a nov

  13. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  14. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    Science.gov (United States)

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-07-14

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  15. A Case for Tamper-Resistant and Tamper-Evident Computer Systems

    National Research Council Canada - National Science Library

    Solihin, Yan

    2007-01-01

    .... These attacks attempt to snoop or modify data transfer between various chips in a computer system such as between the processor and memory, and between processors in a multiprocessor interconnect network...

  16. Methods for size classification of wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Hartmann, Hans; Boehm, Thorsten [Technologie- und Foerderzentrum im Kompetenzzentrum fuer Nachwachsende Rohstoffe (TFZ), Schulgasse 18, D-94315 Straubing (Germany); Daugbjerg Jensen, Peter [Forest and Landscape FLD, The Royal Veterinary and Agricultural University, Rolighedsvej 23, DK-1958 Frederiksberg C (Denmark); Temmerman, Michaeel; Rabier, Fabienne [Centre wallon de Recherches agronomiques CRA-W Departement Genie rural, 146, Chaussee de Namur, B-5030 Gembloux (Belgium); Golser, Michael [Holzforschung Austria HFA Franz Grill-Stra beta e 7, A-1031 Wien (Austria)

    2006-11-15

    Methods for size classification of wood chips were analysed in an international round robin using 13 conventional wood chip samples and two specially prepared standard samples, one from wood chips and one from hog fuel. The true size distribution of these two samples (according to length, width and height) had been determined stereometrically (reference method) using a digital calliper gauge and by weighing each of the about 7000 wood particles per sample. Five different horizontal and three rotary screening devices were tested using five different screen hole diameters (3.15, 8, 16, 45, 63mm, round holes). These systems are compared to a commercially available continuously measuring image analysis equipment. The results show that among the devices of a measuring principle-horizontal and rotary screening-the results are quite comparable, while there is a severe incompatibility when distributions are determined by different measuring principles. Highest conformity with the reference values is given for measurements with an image analysis system, whereas for all machines with horizontal screens the median value of the size distribution only reached between one-third to half of the reference median value for the particle length distribution. These deviations can be attributed to a higher particle misplacement, which is particularly found in the larger fractions. Such differences decrease when the particle's shape is more roundish (i.e. sphericity closer to one). The median values of length distributions from screenings with a rotary classifier are between the measurements from an image analysis and horizontal screening devices. (author)

  17. Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

    Science.gov (United States)

    Lee, Dasheng

    2008-01-01

    In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

  18. Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

    Directory of Open Access Journals (Sweden)

    Dasheng Lee

    2008-12-01

    Full Text Available In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV measurement. The energy harvesting wireless sensor network (WSN was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an

  19. Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network.

    Science.gov (United States)

    Lee, Dasheng

    2008-12-02

    In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

  20. Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

    Energy Technology Data Exchange (ETDEWEB)

    Kaipainen, H.; Seppaenen, V.

    1996-12-31

    The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

  1. Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

    Energy Technology Data Exchange (ETDEWEB)

    Kaipainen, H; Seppaenen, V

    1997-12-31

    The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

  2. An economic evaluation of a chlorhexidine chip for treating chronic periodontitis: the CHIP (chlorhexidine in periodontitis) study.

    Science.gov (United States)

    Henke, C J; Villa, K F; Aichelmann-Reidy, M E; Armitage, G C; Eber, R M; Genco, R J; Killoy, W J; Miller, D P; Page, R C; Polson, A M; Ryder, M I; Silva, S J; Somerman, M J; Van Dyke, T E; Wolff, L F; Evans, C J; Finkelman, R D

    2001-11-01

    The authors previously suggested that an adjunctive, controlled-release chlorhexidine, or CHX, chip may reduce periodontal surgical needs at little additional cost. This article presents an economic analysis of the CHX chip in general dental practice. In a one-year prospective clinical trial, 484 chronic periodontitis patients in 52 general practices across the United States were treated with either scaling and root planing, or SRP, plus any therapy prescribed by treating, unblinded dentists; or SRP plus other therapy as above but including the CHX chip. Economic data were collected from bills, case report forms and 12-month treatment recommendations from blinded periodontist evaluators. Total dental charges were higher for SRP + CHX chip patients vs. SRP patients when CHX chip costs were included (P = .027) but lower when CHX chip costs were excluded (P = .012). About one-half of the CHX chip acquisition cost was offset by savings in other charges. SRP + CHX chip patients were about 50 percent less likely to undergo surgical procedures than were SRP patients (P = .021). At the end of the trial, periodontist evaluators recommended similar additional procedures for both groups: SRP, about 46 percent; maintenance, about 37 percent; surgery, 56 percent for SRP alone and 63 percent for SRP + CHX chip. Adjunctive CHX chip use for general-practice patients with periodontitis increased costs but reduced surgeries over one year. At study's end, periodontists recommended similar additional surgical treatment for both groups. In general practice, routine use of the CHX chip suggests that costs will be partially offset by reduced surgery over at least one year.

  3. Experiment list: SRX507380 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available + (wildtype) || age of animals=1-5 day old || tissue=Ovaries || chip antibody=anti-HP1 || chip antibody vend...1770: WT anti-HP1- replicate#2; Drosophila melanogaster; ChIP-Seq source_name=WT_WT_anti-HP1 || strain=piwi/

  4. Experiment list: SRX507384 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available + (wildtype) || age of animals=1-5 day old || tissue=Ovaries || chip antibody=Anti-H3K4me2 || chip antibody ... Anti-H3K4me2- replicate#2; Drosophila melanogaster; ChIP-Seq source_name=WT_WT_Anti-H3K4me2 || strain=piwi/

  5. Experiment list: SRX507382 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available + (wildtype) || age of animals=1-5 day old || tissue=Ovaries || chip antibody=Anti-H3K9me3 || chip antibody ... Anti-H3K9me3- replicate#2; Drosophila melanogaster; ChIP-Seq source_name=WT_WT_Anti-H3K9me3 || strain=piwi/

  6. The Chip-Scale Atomic Clock - Recent Development Progress

    Science.gov (United States)

    2004-09-01

    35th Annual Precise Time and Time Interval (PTTI) Meeting 467 THE CHIP-SCALE ATOMIC CLOCK – RECENT DEVELOPMENT PROGRESS R. Lutwak ...1] R. Lutwak , et al., 2003, “The Chip-Scale Atomic Clock – Coherent Population Trapping vs. Conventional Interrogation,” in

  7. A microfluidic chip for electrochemical conversions in drug metabolism studies

    NARCIS (Netherlands)

    Odijk, Mathieu; Baumann, A.; Lohmann, W.; van den Brink, Floris Teunis Gerardus; Olthuis, Wouter; Karst, U.; van den Berg, Albert

    2009-01-01

    We have designed a microfluidic microreactor chip for electrochemical conversion of analytes, containing a palladium reference electrode and platinum working and counter electrodes. The counter electrode is placed in a separate side-channel on chip to prevent unwanted side-products appearing in the

  8. A Process Technology For Conversion Of Dried Cassava Chips Into ...

    African Journals Online (AJOL)

    “Gari”, made from fermented bitter Cassava roots (Manihot esculenta crantz) were successfully processed from already dried Cassava chips at 7% moisture level. Cassava mash at 67% moisture was prepared from dried Cassava chips. This was seeded severally with fresh cassava mash and fermented for 72hours.

  9. Design of a 1-chip IBM-3270 protocol handler

    NARCIS (Netherlands)

    Spaanenburg, L.

    1989-01-01

    The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be compiled and optimized into a 35 mm**2 chip in 4

  10. Experiment list: SRX144526 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available stein-Barr Virus transformed 11803840,92.5,91.6,38 GSM922971: NRF2 ChIP vehicle treated rep2; Homo sapiens; ...ChIP-Seq source_name=NRF2 ChIP vehicle treated || biomaterial_provider=Coriell; h

  11. Experiment list: SRX176063 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available =Carcinoma 11279321,95.5,3.6,13985 GSM984395: LNCAP ACH3 vehicle; Homo sapiens; ChIP-Seq source_name=prostat...e cancer cells || cell line=LNCaP || chip antibody=AcH3 || chip antibody manufacturer=Millipore || treatment=EtOH vehicle

  12. Experiment list: SRX176057 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nosis=Carcinoma 21582823,90.1,7.3,1074 GSM984389: 22RV1 AR vehicle; Homo sapiens; ChIP-Seq source_name=prost...ate cancer cells || cell line=22RV1 || chip antibody=AR || chip antibody manufacturer=Abcam || treatment=EtOH vehicle

  13. Experiment list: SRX176054 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available nosis=Carcinoma 13338805,91.2,4.9,792 GSM984386: LNCAP AR vehicle; Homo sapiens; ChIP-Seq source_name=prosta...te cancer cells || cell line=LNCaP || chip antibody=AR || chip antibody manufacturer=Abcam || treatment=EtOH vehicle

  14. Experiment list: SRX176067 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available sis=Carcinoma 6619400,91.7,7.2,13648 GSM984399: LNCAP H3K4ME3 vehicle; Homo sapiens; ChIP-Seq source_name=pr...ostate cancer cells || cell line=LNCaP || chip antibody=H3K4Me3 || chip antibody manufacturer=Millipore || treatment=EtOH vehicle

  15. Experiment list: SRX144527 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available neage=mesoderm|Description=parental cell type to lymphoblastoid cell lines 8704444,92.1,92.5,9 GSM922972: NRF2 ChIP vehicle... treated rep3; Homo sapiens; ChIP-Seq source_name=NRF2 ChIP vehicle treated || biomaterial_pr

  16. Experiment list: SRX144525 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available neage=mesoderm|Description=parental cell type to lymphoblastoid cell lines 14487710,85.8,82.8,188 GSM922970: NRF2 ChIP vehicle... treated rep1; Homo sapiens; ChIP-Seq source_name=NRF2 ChIP vehicle treated || biomaterial

  17. Experiment list: SRX144524 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available neage=mesoderm|Description=parental cell type to lymphoblastoid cell lines 4766716,6.2,89.4,0 GSM922969: NRF2 ChIP vehicle... treated pilot; Homo sapiens; ChIP-Seq source_name=NRF2 ChIP vehicle treated || biomaterial_pr

  18. Single-chip microcomputer application in nuclear radiation monitoring instruments

    International Nuclear Information System (INIS)

    Zhang Songshou

    1994-01-01

    The single-chip microcomputer has advantage in many respects i.e. multiple function, small size, low-power consumption,reliability etc. It is widely used now in industry, instrumentation, communication and machinery. The author introduced usage of single-chip microcomputer in nuclear radiation monitoring instruments for control, linear compensation, calculation, changeable parameter presetting and military training

  19. Experiment list: SRX352046 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available SM1232564: CSB M CHIP; Homo sapiens; ChIP-Seq source_name=fibroblast_menadione_CSB-ChIP || cell type=fibroblast || treated with=menad...ione || chip antibody=Mouse monoclonal anti-CSB N Terminus (1B1) http://dbarchive.b

  20. Experiment list: SRX262797 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 3T3_SAP1_03 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SAP-1a || chip antibody vendor=Santa Cruz Biotechnolo...gy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDa

  1. Experiment list: SRX262799 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available H3T3_SAP1_LAT || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SAP-1a || chip antibody vendor=Santa Cruz Biotechno...logy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/each

  2. Experiment list: SRX262781 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available _name=NIH3T3_SRF_15 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SRF || chip antibody vendor=Santa Cruz Biotec...hnology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/e

  3. Experiment list: SRX262786 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available H3T3_MRTFA_15 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-A || chip antibody vendor=Santa Cruz Biotechno...logy http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/each

  4. Experiment list: SRX262791 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available IH3T3_MRTFB_LAT || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-B || chip antibody vendor=Santa Cruz Biotech...nology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/ea

  5. Experiment list: SRX262782 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available echnology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9...ce_name=NIH3T3_SRF_15 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SRF || chip antibody vendor=Santa Cruz Biot

  6. Experiment list: SRX262788 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available IH3T3_MRTFA_UO || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-A || chip antibody vendor=Santa Cruz Biotechn...ology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eac

  7. Experiment list: SRX262787 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available IH3T3_MRTFA_LAT || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=MRTF-A || chip antibody vendor=Santa Cruz Biotech...nology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/ea

  8. Experiment list: SRX262780 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available chnology http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/...e_name=NIH3T3_SRF_03 || cell line=NIH3T3 fibroblasts || genotype=normal || chip antibody=SRF || chip antibody vendor=Santa Cruz Biote

  9. Experiment list: SRX319552 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available embryonic stem cells || genotype/variation=expressing Flag-bio tagged E2F4 || chip beads=Dynabeads MyOne Streptavidin T1 || chip bea...ds vendor=Invitrogen http://dbarchive.biosciencedbc.jp/k

  10. Experiment list: SRX112179 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available =OS25 ES cells || chip antibody=H5 (MMS-129R, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads=Magnetic bea...ds http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDa

  11. Experiment list: SRX112176 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e=OS25 ES cells || chip antibody=CTD4H8 (MMS-128P, Covance) || chip antibody manufacturer=Covance || chromatin=Fixed || beads...=Magnetic beads http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/e

  12. An automatic system for elaboration of chip breaking diagrams

    DEFF Research Database (Denmark)

    Andreasen, Jan Lasson; De Chiffre, Leonardo

    1998-01-01

    A laboratory system for fully automatic elaboration of chip breaking diagrams has been developed and tested. The system is based on automatic chip breaking detection by frequency analysis of cutting forces in connection with programming of a CNC-lathe to scan different feeds, speeds and cutting...

  13. Experiment list: SRX185915 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available mo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-7 |...| cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_tar

  14. Experiment list: SRX153147 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Seq source_name=Human breast adenocarcinoma cell-line MCF7 || cell-line=MCF7 || passage=5 || chip antibody=...on=Pleura|Tissue Diagnosis=Adenocarcinoma 64054379,98.7,5.2,764 GSM946851: MCF7 H3K27me3; Homo sapiens; ChIP

  15. Experiment list: SRX153146 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Seq source_name=Human breast adenocarcinoma cell-line MCF7 || cell-line=MCF7 || passage=5 || chip antibody=...n=Pleura|Tissue Diagnosis=Adenocarcinoma 60170246,98.4,5.7,16756 GSM946850: MCF7 H3K27ac; Homo sapiens; ChIP

  16. Experiment list: SRX185909 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available omo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-7 ...|| cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_ta

  17. Experiment list: SRX153148 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Seq source_name=Human breast adenocarcinoma cell-line MCF7 || cell-line=MCF7 || passage=5 || chip antibody=...n=Pleura|Tissue Diagnosis=Adenocarcinoma 57306360,95.7,15.1,2666 GSM946852: MCF7 H3K9me3; Homo sapiens; ChIP

  18. Experiment list: SRX185917 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available omo sapiens; ChIP-Seq source_name=MCF-7 breast adenocarcinoma cells, control, FOXM1 ChIP || cell_line=MCF-7 ...|| cell_type=ER-positive breast adenocarcinoma cells || treatment=DMSO || chip_ta

  19. Experiment list: SRX150568 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available is=Adenocarcinoma 59265240,72.4,16.4,4779 GSM935489: Harvard ChipSeq HeLa-S3 RPC155 std source_name=HeLa-S3 ...|| biomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipS

  20. Experiment list: SRX150661 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available is=Adenocarcinoma 59396606,71.7,11.1,1200 GSM935582: Harvard ChipSeq HeLa-S3 BRF1 std source_name=HeLa-S3 ||... biomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq

  1. Experiment list: SRX150495 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available is=Adenocarcinoma 62508352,67.6,8.4,1556 GSM935416: Harvard ChipSeq HeLa-S3 ZZZ3 std source_name=HeLa-S3 || ...biomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq

  2. Experiment list: SRX150565 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available =Adenocarcinoma 54953593,74.3,12.2,1703 GSM935486: Harvard ChipSeq HeLa-S3 BDP1 std source_name=HeLa-S3 || b...iomaterial_provider=ATCC || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq |

  3. Experiment list: SRX150586 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Barr Virus 33195472,90.4,25.9,15633 GSM935507: Harvard ChipSeq GM12878 NF-YB IgG-mus source_name=GM12878 ||...?PgId=165&q=GM12878 || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq || dat

  4. Experiment list: SRX150496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ein-Barr Virus 63040797,85.0,19.7,1435 GSM935417: Harvard ChipSeq GM12878 SPT20 std source_name=GM12878 || b...gId=165&q=GM12878 || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq || datat

  5. Experiment list: SRX150585 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available -Barr Virus 32926476,94.0,12.0,2668 GSM935506: Harvard ChipSeq GM12878 NF-YA IgG-mus source_name=GM12878 || ...PgId=165&q=GM12878 || lab=Harvard || lab description=Struhl - Harvard University || datatype=ChipSeq || data

  6. Power and Thermal Management of System-on-Chip

    DEFF Research Database (Denmark)

    Liu, Wei

    , are necessary at the chip design level. In this work, we investigate the power and thermal management of System-on- Chips (SoCs). Thermal analysis is performed in a SPICE simulation approach based on the electrical-thermal analogy. We investigate the impact of inter- connects on heat distribution...

  7. SNP typing on the NanoChip electronic microarray

    DEFF Research Database (Denmark)

    Børsting, Claus; Sanchez Sanchez, Juan Jose; Morling, Niels

    2005-01-01

    We describe a single nucleotide polymorphism (SNP) typing protocol developed for the NanoChip electronic microarray. The NanoChip array consists of 100 electrodes covered by a thin hydrogel layer containing streptavidin. An electric currency can be applied to one, several, or all electrodes...

  8. Exploration within the Network-on-Chip Paradigm

    NARCIS (Netherlands)

    Wolkotte, P.T.

    2009-01-01

    A general purpose processor used to consist of a single processing core, which performed and controlled all tasks on the chip. Its functionality and maximum clock frequency grew steadily over the years. Due to the continuous increase of the number of transistors available on-chip and the operational

  9. Experiment list: SRX119679 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 8,18360 GSM874985: ES.H3K27me3; Homo sapiens; ChIP-Seq source_name=H1 human Embryonic stem cells || cell line=H1 || treatment=diagnos...tic sample (pre-treatment) || chip antibody=H3K27me3 || chip antibody manufacturer=

  10. Experiment list: SRX119684 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 2,13603 GSM874990: ES.H3K79me2; Homo sapiens; ChIP-Seq source_name=H1 human Embryonic stem cell || cell line=H1 || treatment=diagnost...ic sample (pre-treatment) || chip antibody=H3K79me2 || chip antibody manufacturer=A

  11. Experiment list: SRX037432 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available s from PBMC, normal || gender=male || cell type=aTconv cells || chip antibody=H3K4me1 || chip antibody vendo...=peripheral blood mononuclear cells 14792460,17.0,2.9,5804 GSM648494: aTconv-H3K4me1 source_name=aTconv cell

  12. Experiment list: SRX485219 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 56 GSM1346560: RNA Polymerase II ChIP from control germline knock-down ovaries; Drosophila melanogaster; ChI...P-Seq source_name=RNA Polymerase II ChIP from control germline knock-down ovaries || developmental stage=4-6... days old adult || Sex=female || tissue=ovary || germline knock-down=control || c

  13. Experiment list: SRX107410 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available Adenocarcinoma 37378122,96.3,56.7,376 GSM838388: h3k36me3 si23 ChIP-Seq; Homo sapiens; ChIP-Seq source_name=Hela cells knock...down Med23 || chip antibody=H3K36me3 || treatment=knockdown Med23 || cell line=HeLa || chip

  14. On-chip integrated lasers for biophotonic applications

    DEFF Research Database (Denmark)

    Mappes, Timo; Wienhold, Tobias; Bog, Uwe

    Meeting the need of biomedical users, we develop disposable Lab-on-a-Chip systems based on commercially available polymers. We are combining passive microfluidics with active optical elements on-chip by integrating multiple solid-state and liquid-core lasers. While covering a wide range of laser ...

  15. Experiment list: SRX160914 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available M970829: IgG for KSHV LANA; Homo sapiens; ChIP-Seq source_name=BCBL1 pleural effusion lymphoma, IgG ChIP || ...cell line=BCBL1 || cell type=KSHV-infected pleural effusion lymphoma cells || chip antibody=Rabbit IgG [Sant

  16. Experiment list: SRX151246 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 11: SMC1 ChIPSeq; Homo sapiens; ChIP-Seq source_name=BCBL1 pleural effusion lymphoma, SMC1 ChIP || cell line...=BCBL1 || cell type=KSHV-infected pleural effusion lymphoma cells || chip antibody=rabbit anti-SMC1 || antib

  17. Experiment list: SRX160915 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available M970828: IgG for CTCF SMC1; Homo sapiens; ChIP-Seq source_name=BCBL1 pleural effusion lymphoma, IgG ChIP || ...cell line=BCBL1 || cell type=KSHV-infected pleural effusion lymphoma cells || chip antibody=Mouse IgG [Santa

  18. Experiment list: SRX151245 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available 0: CTCF ChIPSeq; Homo sapiens; ChIP-Seq source_name=BCBL1 pleural effusion lymphoma, CTCF ChIP || cell line=...BCBL1 || cell type=KSHV-infected pleural effusion lymphoma cells || chip antibody=rabbit anti-CTCF || antibo

  19. Cassava chips quality as influenced by cultivar, blanching time and ...

    African Journals Online (AJOL)

    Currently, fried cassava chips and crisps are increasingly being consumed as snacks; and fried cassava chips are produced by street processors. The quality and safety of these products is not known, therefore, the current study was to establish the influence of cassava cultivar, blanching time and slice thickness on quality ...

  20. On-chip photonic microsystem for optical signal processing based on silicon and silicon nitride platforms

    Science.gov (United States)

    Li, Yu; Li, Jiachen; Yu, Hongchen; Yu, Hai; Chen, Hongwei; Yang, Sigang; Chen, Minghua

    2018-04-01

    The explosive growth of data centers, cloud computing and various smart devices is limited by the current state of microelectronics, both in terms of speed and heat generation. Benefiting from the large bandwidth, promising low power consumption and passive calculation capability, experts believe that the integrated photonics-based signal processing and transmission technologies can break the bottleneck of microelectronics technology. In recent years, integrated photonics has become increasingly reliable and access to the advanced fabrication process has been offered by various foundries. In this paper, we review our recent works on the integrated optical signal processing system. We study three different kinds of on-chip signal processors and use these devices to build microsystems for the fields of microwave photonics, optical communications and spectrum sensing. The microwave photonics front receiver was demonstrated with a signal processing range of a full-band (L-band to W-band). A fully integrated microwave photonics transceiver without the on-chip laser was realized on silicon photonics covering the signal frequency of up 10 GHz. An all-optical orthogonal frequency division multiplexing (OFDM) de-multiplier was also demonstrated and used for an OFDM communication system with the rate of 64 Gbps. Finally, we show our work on the monolithic integrated spectrometer with a high resolution of about 20 pm at the central wavelength of 1550 nm. These proposed on-chip signal processing systems potential applications in the fields of radar, 5G wireless communication, wearable devices and optical access networks.

  1. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  2. On-Chip Laser-Power Delivery System for Dielectric Laser Accelerators

    Science.gov (United States)

    Hughes, Tyler W.; Tan, Si; Zhao, Zhexin; Sapra, Neil V.; Leedle, Kenneth J.; Deng, Huiyang; Miao, Yu; Black, Dylan S.; Solgaard, Olav; Harris, James S.; Vuckovic, Jelena; Byer, Robert L.; Fan, Shanhui; England, R. Joel; Lee, Yun Jo; Qi, Minghao

    2018-05-01

    We propose an on-chip optical-power delivery system for dielectric laser accelerators based on a fractal "tree-network" dielectric waveguide geometry. This system replaces experimentally demanding free-space manipulations of the driving laser beam with chip-integrated techniques based on precise nanofabrication, enabling access to orders-of-magnitude increases in the interaction length and total energy gain for these miniature accelerators. Based on computational modeling, in the relativistic regime, our laser delivery system is estimated to provide 21 keV of energy gain over an acceleration length of 192 μ m with a single laser input, corresponding to a 108-MV/m acceleration gradient. The system may achieve 1 MeV of energy gain over a distance of less than 1 cm by sequentially illuminating 49 identical structures. These findings are verified by detailed numerical simulation and modeling of the subcomponents, and we provide a discussion of the main constraints, challenges, and relevant parameters with regard to on-chip laser coupling for dielectric laser accelerators.

  3. Smartphone technology can be transformative to the deployment of lab-on-chip diagnostics

    Science.gov (United States)

    Erickson, David; O’Dell, Dakota; Jiang, Li; Oncescu, Vlad; Gumus, Abdurrahman; Lee, Seoho; Mancuso, Matthew; Mehta, Saurabh

    2014-01-01

    The rapid expansion of mobile technology is transforming the biomedical landscape. By 2016 there will be 260M active smartphones in the US and millions of health accessories and software “apps” running off them. In parallel with this have come major technical achievements in lab-on-a-chip technology leading to incredible new biochemical sensors and molecular diagnostic devices. Despite these advancements, the uptake of lab-on-a-chip technologies at the consumer level has been somewhat limited. We believe that the widespread availability of smartphone technology and the capabilities they offer in terms of computation, communication, social networking, and imaging will be transformative to the deployment of lab-on-a-chip type technology both in the developed and developing world. In this paper we outline why we believe this is the case, the new business models that may emerge, and detail some specific application areas in which this synergy will have long term impact, namely: nutrition monitoring and disease diagnostics in limited resource settings. PMID:24700127

  4. Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

    Science.gov (United States)

    Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

    2014-09-01

    The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

  5. Smartphone technology can be transformative to the deployment of lab-on-chip diagnostics.

    Science.gov (United States)

    Erickson, David; O'Dell, Dakota; Jiang, Li; Oncescu, Vlad; Gumus, Abdurrahman; Lee, Seoho; Mancuso, Matthew; Mehta, Saurabh

    2014-09-07

    The rapid expansion of mobile technology is transforming the biomedical landscape. By 2016 there will be 260 M active smartphones in the US and millions of health accessories and software "apps" running off them. In parallel with this have come major technical achievements in lab-on-a-chip technology leading to incredible new biochemical sensors and molecular diagnostic devices. Despite these advancements, the uptake of lab-on-a-chip technologies at the consumer level has been somewhat limited. We believe that the widespread availability of smartphone technology and the capabilities they offer in terms of computation, communication, social networking, and imaging will be transformative to the deployment of lab-on-a-chip type technology both in the developed and developing world. In this paper we outline why we believe this is the case, the new business models that may emerge, and detail some specific application areas in which this synergy will have long term impact, namely: nutrition monitoring and disease diagnostics in limited resource settings.

  6. Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

    Science.gov (United States)

    Pastur-Romay, Lucas Antón; Cedrón, Francisco; Pazos, Alejandro; Porto-Pazos, Ana Belén

    2016-01-01

    Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure–Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron–Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods. PMID:27529225

  7. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  8. 'Fluorescent Cell Chip' for immunotoxicity testing: Development of the c-fos expression reporter cell lines

    International Nuclear Information System (INIS)

    Trzaska, Dominika; Zembek, Patrycja; Olszewski, Maciej; Adamczewska, Violetta; Ulleras, Erik; Dastych, JarosIaw

    2005-01-01

    The Fluorescent Cell Chip for in vitro immunotoxicity testing employs cell lines derived from lymphocytes, mast cells, and monocytes-macrophages transfected with various EGFP cytokine reporter gene constructs. While cytokine expression is a valid endpoint for in vitro immunotoxicity screening, additional marker for the immediate-early response gene expression level could be of interest for further development and refinement of the Fluorescent Cell Chip. We have used BW.5147.3 murine thymoma transfected with c-fos reporter constructs to obtain reporter cell lines expressing ECFP under the control of murine c-fos promoter. These cells upon serum withdrawal and readdition and incubation with heavy metal compounds showed paralleled induction of c-Fos expression as evidenced by Real-Time PCR and ECFP fluorescence as evidenced by computer-supported fluorescence microscopy. In conclusion, we developed fluorescent reporter cell lines that could be employed in a simple and time-efficient screening assay for possible action of chemicals on c-Fos expression in lymphocytes. The evaluation of usefulness of these cells for the Fluorescent Cell Chip-based detection of immunotoxicity will require additional testing with a larger number of chemicals

  9. Banknote Validation through an Embedded RFID Chip and an NFC-Enabled Smartphone

    Directory of Open Access Journals (Sweden)

    Mohamed Hamdy Eldefrawy

    2015-01-01

    Full Text Available With the new, state-of-the-art printing devices and equipment, there has been rapid growth in the counterfeiting of banknotes. Traditional security features on banknotes are easy targets for counterfeiters, and they can easily imitate the original banknotes with fake ones. Conventional methods for validating currency require specialized devices for the authentication of banknotes. However, cost and lack of mobility of sophisticated banknote validation devices are big problems for general consumers. Modern digital solutions are attempting to complement the traditional security features through embedding radio frequency identification (RFID chips in the banknotes, for example, Euro currency. Unfortunately, the requirement of specialized RFID readers for banknote validation impedes their widespread proliferation among consumers. To overcome this problem, a new method of banknote validation using an RFID chip and an NFC-enabled smartphone is presented. The consumer sends a banknote validation request to the Monetary Agency (MA using her or his smartphone and an Internet connection. The MA replies by sending a random challenge to the consumer’s smartphone. The RFID chip in the banknote receives the challenge, via the NFC, and calculates an equivalent response to the MA’s challenge. If any of the messages are incorrect, authentication is denied. By the proposed method, consumers can easily and instantly check the originality of currency notes with the MA using their smartphones and an Internet connection. The proposed system is less expensive, computationally, than regular methods and preserves the privacy of people who carry banknotes.

  10. Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications.

    Science.gov (United States)

    Pastur-Romay, Lucas Antón; Cedrón, Francisco; Pazos, Alejandro; Porto-Pazos, Ana Belén

    2016-08-11

    Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure-Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron-Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

  11. Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

    Directory of Open Access Journals (Sweden)

    Lucas Antón Pastur-Romay

    2016-08-01

    Full Text Available Over the past decade, Deep Artificial Neural Networks (DNNs have become the state-of-the-art algorithms in Machine Learning (ML, speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs. All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS, Quantitative Structure–Activity Relationship (QSAR research, protein structure prediction and genomics (and other omics data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron–Astrocyte Networks (DANAN could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

  12. Decapsulation Method for Flip Chips with Ceramics in Microelectronic Packaging

    Science.gov (United States)

    Shih, T. I.; Duh, J. G.

    2008-06-01

    The decapsulation of flip chips bonded to ceramic substrates is a challenging task in the packaging industry owing to the vulnerability of the chip surface during the process. In conventional methods, such as manual grinding and polishing, the solder bumps are easily damaged during the removal of underfill, and the thin chip may even be crushed due to mechanical stress. An efficient and reliable decapsulation method consisting of thermal and chemical processes was developed in this study. The surface quality of chips after solder removal is satisfactory for the existing solder rework procedure as well as for die-level failure analysis. The innovative processes included heat-sink and ceramic substrate removal, solder bump separation, and solder residue cleaning from the chip surface. In the last stage, particular temperatures were selected for the removal of eutectic Pb-Sn, high-lead, and lead-free solders considering their respective melting points.

  13. Modelling, Synthesis, and Configuration of Networks-on-Chips

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo

    This thesis presents three contributions in two different areas of network-on-chip and system-on-chip research: Application modelling and identifying and solving different optimization problems related to two specific network-on-chip architectures. The contribution related to application modelling...... is an analytical method for deriving the worst-case traffic pattern caused by an application and the cache-coherence protocol in a cache-coherent shared-memory system. The contributions related to network-on-chip optimization problems consist of two parts: The development and evaluation of six heuristics...... for solving the network synthesis problem in the MANGO network-on-chip, and the identification and formalization of the ReNoC configuration problem together with three heuristics for solving it....

  14. Research of Dielectric Breakdown Micro fluidic Sampling Chip

    International Nuclear Information System (INIS)

    Jiang, F.; Lei, Y.; Yu, J.

    2013-01-01

    Micro fluidic chip is mainly driven electrically by external electrode and array electrode, but there are certain disadvantages in both of ways, which affect the promotion and application of micro fluidic technology. This paper discusses a scheme that uses the conductive solution in a microchannel made by PDMS, replacing electrodes and the way of dielectric breakdown to achieve microfluidic chip driver. It could reduce the driving voltage and simplify the chip production process. To prove the feasibility of this method, we produced a micro fluidic chip used in PDMS material with the lithography technology and experimented it. The results showed that using the dielectric breakdown to achieve microfluidic chip driver is feasible, and it has certain application prospect.

  15. Reagent-loaded plastic microfluidic chips for detecting homocysteine

    International Nuclear Information System (INIS)

    Suk, Ji Won; Jang, Jae-Young; Cho, Jun-Hyeong

    2008-01-01

    This report describes the preliminary study on plastic microfluidic chips with pre-loaded reagents for detecting homocysteine (Hcy). All reagents needed in an Hcy immunoassay were included in a microfluidic chip to remove tedious assay steps. A simple and cost-effective bonding method was developed to realize reagent-loaded microfluidic chips. This technique uses an intermediate layer between two plastic substrates by selectively patterning polydimethylsiloxane (PDMS) on the embossed surface of microchannels and fixing the substrates under pressure. Using this bonding method, the competitive immunoassay for SAH, a converted form of Hcy, was performed without any damage to reagents in chips, and the results showed that the fluorescent signal from antibody antigen binding decreased as the SAH concentration increased. Based on the SAH immunoassay, whole immunoassay steps for Hcy detection were carried out in plastic microfluidic chips with all necessary reagents. These experiments demonstrated the feasibility of the Hcy immunoassay in microfluidic devices

  16. Optical continuum generation on a silicon chip

    Science.gov (United States)

    Jalali, Bahram; Boyraz, Ozdal; Koonath, Prakash; Raghunathan, Varun; Indukuri, Tejaswi; Dimitropoulos, Dimitri

    2005-08-01

    Although the Raman effect is nearly two orders of magnitude stronger than the electronic Kerr nonlinearity in silicon, under pulsed operation regime where the pulse width is shorter than the phonon response time, Raman effect is suppressed and Kerr nonlinearity dominates. Continuum generation, made possible by the non-resonant Kerr nonlinearity, offers a technologically and economically appealing path to WDM communication at the inter-chip or intra-chip levels. We have studied this phenomenon experimentally and theoretically. Experimentally, a 2 fold spectral broadening is obtained by launching ~4ps optical pulses with 2.2GW/cm2 peak power into a conventional silicon waveguide. Theoretical calculations, that include the effect of two-photon-absorption, free carrier absorption and refractive index change indicate that up to >30 times spectral broadening is achievable in an optimized device. The broadening is due to self phase modulation and saturates due to two photon absorption. Additionally, we find that free carrier dynamics also contributes to the spectral broadening and cause the overall spectrum to be asymmetric with respect to the pump wavelength.

  17. Readout Architecture for Hybrid Pixel Readout Chips

    CERN Document Server

    AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

    The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

  18. Biosensors-on-chip: a topical review

    International Nuclear Information System (INIS)

    Chen, Sensen; Shamsi, Mohtashim H

    2017-01-01

    This review will examine the integration of two fields that are currently at the forefront of science, i.e. biosensors and microfluidics. As a lab-on-a-chip (LOC) technology, microfluidics has been enriched by the integration of various detection tools for analyte detection and quantitation. The application of such microfluidic platforms is greatly increased in the area of biosensors geared towards point-of-care diagnostics. Together, the merger of microfluidics and biosensors has generated miniaturized devices for sample processing and sensitive detection with quantitation. We believe that microfluidic biosensors (biosensors-on-chip) are essential for developing robust and cost effective point-of-care diagnostics. This review is relevant to a variety of disciplines, such as medical science, clinical diagnostics, LOC technologies including MEMs/NEMs, and analytical science. Specifically, this review will appeal to scientists working in the two overlapping fields of biosensors and microfluidics, and will also help new scientists to find their directions in developing point-of-care devices. (topical review)

  19. Nano technologies for Biosensor and Bio chip

    International Nuclear Information System (INIS)

    Kim, I.M.; Park, T.J.; Paskaleva, E.E.; Sun, F.; Seo, J.W.; Mehta, K.K.

    2015-01-01

    The bio sensing devices are characterized by their biological receptors, which have specificity to their corresponding analytes. These analytes are a vast and diverse group of biological molecules, DNAs, proteins (such as antibodies), fatty acids, or entire biological systems, such as pathogenic bacteria, viruses, cancerous cells, or other living organisms. A main challenge in the development of biosensor applications is the efficient recognition of a biological signal in a low signal-to-noise ratio environment, and its transduction into an electrochemical, optical, or other signals. The advent of nano material technology greatly increased the potential for achieving exquisite sensitivity of such devises, due to the innate high surface-to-volume ratio and high reactivity of the nano material. The second major challenge facing the biosensor application, that of sca lability, is addressed by multiplexing and miniaturizing of the biosensor devises into a bio chip. In recent years, biosensor and bio chip technologies have made significant progress by taking advantages of diverse kinds of nano materials that are derived from nano technology

  20. COMPUTATIONAL SCIENCE CENTER

    International Nuclear Information System (INIS)

    DAVENPORT, J.

    2006-01-01

    Computational Science is an integral component of Brookhaven's multi science mission, and is a reflection of the increased role of computation across all of science. Brookhaven currently has major efforts in data storage and analysis for the Relativistic Heavy Ion Collider (RHIC) and the ATLAS detector at CERN, and in quantum chromodynamics. The Laboratory is host for the QCDOC machines (quantum chromodynamics on a chip), 10 teraflop/s computers which boast 12,288 processors each. There are two here, one for the Riken/BNL Research Center and the other supported by DOE for the US Lattice Gauge Community and other scientific users. A 100 teraflop/s supercomputer will be installed at Brookhaven in the coming year, managed jointly by Brookhaven and Stony Brook, and funded by a grant from New York State. This machine will be used for computational science across Brookhaven's entire research program, and also by researchers at Stony Brook and across New York State. With Stony Brook, Brookhaven has formed the New York Center for Computational Science (NYCCS) as a focal point for interdisciplinary computational science, which is closely linked to Brookhaven's Computational Science Center (CSC). The CSC has established a strong program in computational science, with an emphasis on nanoscale electronic structure and molecular dynamics, accelerator design, computational fluid dynamics, medical imaging, parallel computing and numerical algorithms. We have been an active participant in DOES SciDAC program (Scientific Discovery through Advanced Computing). We are also planning a major expansion in computational biology in keeping with Laboratory initiatives. Additional laboratory initiatives with a dependence on a high level of computation include the development of hydrodynamics models for the interpretation of RHIC data, computational models for the atmospheric transport of aerosols, and models for combustion and for energy utilization. The CSC was formed to bring together

  1. COMPUTATIONAL SCIENCE CENTER

    Energy Technology Data Exchange (ETDEWEB)

    DAVENPORT, J.

    2006-11-01

    Computational Science is an integral component of Brookhaven's multi science mission, and is a reflection of the increased role of computation across all of science. Brookhaven currently has major efforts in data storage and analysis for the Relativistic Heavy Ion Collider (RHIC) and the ATLAS detector at CERN, and in quantum chromodynamics. The Laboratory is host for the QCDOC machines (quantum chromodynamics on a chip), 10 teraflop/s computers which boast 12,288 processors each. There are two here, one for the Riken/BNL Research Center and the other supported by DOE for the US Lattice Gauge Community and other scientific users. A 100 teraflop/s supercomputer will be installed at Brookhaven in the coming year, managed jointly by Brookhaven and Stony Brook, and funded by a grant from New York State. This machine will be used for computational science across Brookhaven's entire research program, and also by researchers at Stony Brook and across New York State. With Stony Brook, Brookhaven has formed the New York Center for Computational Science (NYCCS) as a focal point for interdisciplinary computational science, which is closely linked to Brookhaven's Computational Science Center (CSC). The CSC has established a strong program in computational science, with an emphasis on nanoscale electronic structure and molecular dynamics, accelerator design, computational fluid dynamics, medical imaging, parallel computing and numerical algorithms. We have been an active participant in DOES SciDAC program (Scientific Discovery through Advanced Computing). We are also planning a major expansion in computational biology in keeping with Laboratory initiatives. Additional laboratory initiatives with a dependence on a high level of computation include the development of hydrodynamics models for the interpretation of RHIC data, computational models for the atmospheric transport of aerosols, and models for combustion and for energy utilization. The CSC was formed to

  2. 75 FR 16149 - Medicaid and CHIP Programs; Meeting of the CHIP Working Group-April 26, 2010

    Science.gov (United States)

    2010-03-31

    ... DEPARTMENT OF HEALTH AND HUMAN SERVICES Centers for Medicare & Medicaid Services [CMS-2312-N] DEPARTMENT OF LABOR Employee Benefits Security Administration Medicaid and CHIP Programs; Meeting of the CHIP Working Group-- April 26, 2010 AGENCIES: Centers for Medicare & Medicaid Services (CMS), Department of...

  3. 75 FR 30046 - Medicaid and CHIP Programs; Meeting of the CHIP Working Group-June 14, 2010

    Science.gov (United States)

    2010-05-28

    ..., Employee Benefits Security Administration, DOL at (202) 693-8335. News media representatives must contact... eligible for benefits under titles XIX or XXI of the Social Security Act (the Act) to enable them to enroll...] DEPARTMENT OF LABOR Employee Benefits Security Administration Medicaid and CHIP Programs; Meeting of the CHIP...

  4. Magnetic Tools for Lab-on-a-chip Technologies

    Energy Technology Data Exchange (ETDEWEB)

    Pekas, Nikola Slobodan [Iowa State Univ., Ames, IA (United States)

    2006-01-01

    This study establishes a set of magnetics-based tools that have been integrated with microfluidic systems. The overall impact of the work begins to enable the rapid and efficient manipulation and detection of magnetic entities such as particles, picoliter-sized droplets, or bacterial cells. Details of design, fabrication, and theoretical and experimental assessments are presented. The manipulation strategy has been demonstrated in the format of a particle diverter, whereby micron-sized particles are actively directed into desired flow channels at a split-flow junction by means of integrated microelectromagnets. Magnetic detection has been realized by deploying Giant Magnetoresistance (GMR) sensors--microfabricated structures originally developed for use as readout elements in computer hard-drives. We successfully transferred the GMR technology to the lab-on-a-chip arena, and demonstrated the versatility of the concept in several important areas: real-time, integrated monitoring of the properties of multiphase droplet flows; rapid quantitative determination of the concentration of magnetic nanoparticles in droplets of ferrofluids; and high-speed detection of individual magnetic microparticles and magnetotactic bacteria. The study also includes novel schemes for hydrodynamic flow focusing that work in conjunction with GMR-based detection to ensure precise navigation of the sample stream through the GMR detection volume, therefore effectively establishing a novel concept of a microfabricated magnetic flow cytometer.

  5. 3D-Printed Chips: Compatibility of Additive Manufacturing Photopolymeric Substrata with Biological Applications

    Directory of Open Access Journals (Sweden)

    Megan Carve

    2018-02-01

    Full Text Available Additive manufacturing (AM is ideal for building adaptable, structurally complex, three-dimensional, monolithic lab-on-chip (LOC devices from only a computer design file. Consequently, it has potential to advance micro- to milllifluidic LOC design, prototyping, and production and further its application in areas of biomedical and biological research. However, its application in these areas has been hampered due to material biocompatibility concerns. In this review, we summarise commonly used AM techniques: vat polymerisation and material jetting. We discuss factors influencing material biocompatibility as well as methods to mitigate material toxicity and thus promote its application in these research fields.

  6. A chip-level modeling approach for rail span collapse and survivability analyses

    International Nuclear Information System (INIS)

    Marvis, D.G.; Alexander, D.R.; Dinger, G.L.

    1989-01-01

    A general semiautomated analysis technique has been developed for analyzing rail span collapse and survivability of VLSI microcircuits in high ionizing dose rate radiation environments. Hierarchical macrocell modeling permits analyses at the chip level and interactive graphical postprocessing provides a rapid visualization of voltage, current and power distributions over an entire VLSIC. The technique is demonstrated for a 16k C MOS/SOI SRAM and a CMOS/SOS 8-bit multiplier. The authors also present an efficient method to treat memory arrays as well as a three-dimensional integration technique to compute sapphire photoconduction from the design layout

  7. On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip

    Directory of Open Access Journals (Sweden)

    Jian Lu

    2008-01-01

    Full Text Available A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed to offer a cost effective approach realizing power systems on chip (SOC. We have investigated the concept both experimentally and with finite element modeling. A Q factor of 30–40 is experimentally demonstrated for the bondwire inductors which represents an improvement by a factor of 3–30 over the state-of-the-art MEMS micromachined inductors. Transformer parameters including self- and mutual inductance and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SOC manufacturing processes with minimal changes and open enormous possibilities for realizing cost-effective, high-current, high-efficiency power SOCs.

  8. Numerical analysis of the interaction between high-pressure resin spray and wood chips in a vapour stream

    Directory of Open Access Journals (Sweden)

    Massimo Milani

    2016-04-01

    Full Text Available This article investigates the interaction between the resin spray and the wood chips in a vapour stream using a multi-phase multi-component computational fluid dynamics approach. The interaction between the spray and the chips is one of the main issues in the industrial process for manufacturing medium density fibre boards. Thus, the optimization of this process can lead to important benefits, such as the reduction in the emission of formaldehyde-based toxic chemicals, the reduction in energy consumption in the blending process and energy saving in the fibreboard drying process. First step of the study is the numerical analysis of the resin injector in order to extend the experimental measurements carried out with water to the resin spray. The effects of the injector’s geometrical features on the spray formation are highlighted under different injection pressure values and needle displacements. Afterwards, the results obtained in the analysis of the single injector are used for the complete simulation of multi-injector rail where the mixing of the resin spray and wood chips takes place. The influence of the main operating conditions, such as the vapour and the wood chip flow rates, on the resin distribution is addressed in order to optimize the resination process.

  9. Rework of flip chip bonded radiation pixel detectors

    International Nuclear Information System (INIS)

    Vaehaenen, S.; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S.

    2008-01-01

    In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process

  10. Rework of flip chip bonded radiation pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Vaehaenen, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)], E-mail: sami.vahanen@vtt.fi; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)

    2008-06-11

    In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process.

  11. Thermal-Aware Scheduling for Future Chip Multiprocessors

    Directory of Open Access Journals (Sweden)

    Pedro Trancoso

    2007-04-01

    Full Text Available The increased complexity and operating frequency in current single chip microprocessors is resulting in a decrease in the performance improvements. Consequently, major manufacturers offer chip multiprocessor (CMP architectures in order to keep up with the expected performance gains. This architecture is successfully being introduced in many markets including that of the embedded systems. Nevertheless, the integration of several cores onto the same chip may lead to increased heat dissipation and consequently additional costs for cooling, higher power consumption, decrease of the reliability, and thermal-induced performance loss, among others. In this paper, we analyze the evolution of the thermal issues for the future chip multiprocessor architectures and show that as the number of on-chip cores increases, the thermal-induced problems will worsen. In addition, we present several scenarios that result in excessive thermal stress to the CMP chip or significant performance loss. In order to minimize or even eliminate these problems, we propose thermal-aware scheduler (TAS algorithms. When assigning processes to cores, TAS takes their temperature and cooling ability into account in order to avoid thermal stress and at the same time improve the performance. Experimental results have shown that a TAS algorithm that considers also the temperatures of neighboring cores is able to significantly reduce the temperature-induced performance loss while at the same time, decrease the chip's temperature across many different operation and configuration scenarios.

  12. On-chip photonic particle sensor

    Science.gov (United States)

    Singh, Robin; Ma, Danhao; Agarwal, Anu; Anthony, Brian

    2018-02-01

    We propose an on-chip photonic particle sensor design that can perform particle sizing and counting for various environmental applications. The sensor is based on micro photonic ring resonators that are able to detect the presence of the free space particles through the interaction with their evanescent electric field tail. The sensor can characterize a wide range of the particle size ranging from a few nano meters to micron ( 1 micron). The photonic platform offers high sensitivity, compactness, fast response of the device. Further, FDTD simulations are performed to analyze different particle-light interactions. Such a compact and portable platform, packaged with integrated photonic circuit provides a useful sensing modality in space shuttle and environmental applications.

  13. MAROC, a generic photomultiplier readout chip

    International Nuclear Information System (INIS)

    Blin, S; Barrillon, P; La Taille, C de

    2010-01-01

    The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( ∼ 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: ∼ 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

  14. Scalable on-chip quantum state tomography

    Science.gov (United States)

    Titchener, James G.; Gräfe, Markus; Heilmann, René; Solntsev, Alexander S.; Szameit, Alexander; Sukhorukov, Andrey A.

    2018-03-01

    Quantum information systems are on a path to vastly exceed the complexity of any classical device. The number of entangled qubits in quantum devices is rapidly increasing, and the information required to fully describe these systems scales exponentially with qubit number. This scaling is the key benefit of quantum systems, however it also presents a severe challenge. To characterize such systems typically requires an exponentially long sequence of different measurements, becoming highly resource demanding for large numbers of qubits. Here we propose and demonstrate a novel and scalable method for characterizing quantum systems based on expanding a multi-photon state to larger dimensionality. We establish that the complexity of this new measurement technique only scales linearly with the number of qubits, while providing a tomographically complete set of data without a need for reconfigurability. We experimentally demonstrate an integrated photonic chip capable of measuring two- and three-photon quantum states with statistical reconstruction fidelity of 99.71%.

  15. MAROC, a generic photomultiplier readout chip

    Energy Technology Data Exchange (ETDEWEB)

    Blin, S; Barrillon, P; La Taille, C de, E-mail: blin@lal.in2p3.f [CNRS/IN2p3/LAL-OMEGA, Universite Paris Sud, Bat.200, 91898 Orsay (France)

    2010-12-15

    The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( {approx} 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: {approx} 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

  16. MAROC, a generic photomultiplier readout chip

    Science.gov (United States)

    Blin, S.; Barrillon, P.; de La Taille, C.

    2010-12-01

    The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( ~ 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: ~ 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

  17. Synchronization of Integrated Systems on a Chip

    Directory of Open Access Journals (Sweden)

    González-Díaz O.

    2012-04-01

    Full Text Available In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor N-well 0.35 µm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 µm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.

  18. CERN_DxCTA counting mode chip

    CERN Document Server

    Moraes, D; Nygård, E

    2008-01-01

    This ASIC is a counting mode front-end electronic optimized for the readout of CdZnTe/CdTe and silicon sensors, for possible use in applications where the flux of ionizing radiation is high. The chip is implemented in 0.25 μm CMOS technology. The circuit comprises 128 channels equipped with a transimpedance amplifier followed by a gain shaper stage with 21 ns peaking time, two discriminators and two 18-bit counters. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. The amplifier shows a linear sensitivity of 118 mV/fC and an equivalent noise charge of about 711 e−, for a detector capacitance of 5 pF. Complete evaluation of the circuit is presented using electronic pulses and pixel detectors.

  19. CERNDxCTA counting mode chip

    International Nuclear Information System (INIS)

    Moraes, D.; Kaplon, J.; Nygard, E.

    2008-01-01

    This ASIC is a counting mode front-end electronic optimized for the readout of CdZnTe/CdTe and silicon sensors, for possible use in applications where the flux of ionizing radiation is high. The chip is implemented in 0.25 μm CMOS technology. The circuit comprises 128 channels equipped with a transimpedance amplifier followed by a gain shaper stage with 21 ns peaking time, two discriminators and two 18-bit counters. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. The amplifier shows a linear sensitivity of 118 mV/fC and an equivalent noise charge of about 711 e - , for a detector capacitance of 5 pF. Complete evaluation of the circuit is presented using electronic pulses and pixel detectors

  20. Wideband pulse amplifiers for the NECTAr chip

    Science.gov (United States)

    Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribó, M.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

    2012-12-01

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  1. Wideband pulse amplifiers for the NECTAr chip

    International Nuclear Information System (INIS)

    Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J-F.; Naumann, C.L.; Nayman, P.; Ribó, M.

    2012-01-01

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1–3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  2. Wideband pulse amplifiers for the NECTAr chip

    Energy Technology Data Exchange (ETDEWEB)

    Sanuy, A., E-mail: asanuy@ecm.ub.es [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Gascon, D. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Sieiro, X. [Departament d' Electronica, Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, CC072, bat. 13, place Eugene Bataillon, 34095 Montpellier (France); Glicenstein, J-F. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Ribo, M. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); and others

    2012-12-11

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  3. Production of chips in the forest

    Energy Technology Data Exchange (ETDEWEB)

    Sukhanov, V S; Potapova, L A; Stepin, A V; Savostina, T I; Osipov, A A

    1981-01-01

    Details are given of schemes developed in the USSR for the production of chips in the forest, for two particular cases, viz. (a) the conversion of young low-grade stands, and (b) thinnings. Scheme (a) involves two fellers with chain-saws (or one LP-17 machine), one LT-168 forwarder, one LO-63 chipper, and containers (for removal by lorry). Scheme (b) involves two fellers with chain-saws, two T-40 tractors with power-driven semi-trailer, one LT-168 forwarder, one LO-63 chipper, and containers (for removal by lorry). The organizational lay-out of both schemes is illustrated and discussed. Output with scheme (a) was approximately 6 or 7 cubic meters/man-day, and with scheme (b) it was 4 cubic meters/man-day.

  4. Resonator quantum electrodynamics on a microtrap chip

    International Nuclear Information System (INIS)

    Steinmetz, Tilo

    2008-01-01

    In the present dissertation experiments on resonator quantum electrodynamics on a microtrap chip are described. Thereby for the first time single atoms catched in a chip trap could be detected. For this in the framework of this thesis a novel optical microresonator was developed, which can because of its miniaturization be combined with the microtrap technique introduced in our working group for the manipulation of ultracold atoms. For this resonator glass-fiber ends are used as mirror substrates, between which a standing light wave is formed. With such a fiber Fabry-Perot resonator we obtain a finess of up to ∼37,000. Because of the small mode volumina in spite of moderate resonator quality the coherent interaction between an atom and a photon can be made so large that the regime of the strong atom-resonator coupling is reached. For the one-atom-one-photon coupling rate and the one-atom-one-photon cooperativity thereby record values of g 0 =2π.300 MHz respectively C 0 =210 are reached. Just so for the first time the strong coupling regime between a Bose-Einstein condensate (BEC) and the field of a high-quality resonator could be reached. The BEC was thereby by means of the magnetic microtrap potentials deterministically brought to a position within the resonator and totally transformed in a well defined antinode of an additionally optical standing-wave trap. The spectrum of the coupled atom-resonator system was measured for different atomic numbers and atom-resonator detunings, whereby a collective vacuum Rabi splitting of more than 20 GHz could be reached. [de

  5. 1984 CERN school of computing

    International Nuclear Information System (INIS)

    1985-01-01

    The eighth CERN School of Computing covered subjects mainly related to computing for elementary-particle physics. These proceedings contain written versions of most of the lectures delivered at the School. Notes on the following topics are included: trigger and data-acquisition plans for the LEP experiments; unfolding methods in high-energy physics experiments; Monte Carlo techniques; relational data bases; data networks and open systems; the Newcastle connection; portable operating systems; expert systems; microprocessors - from basic chips to complete systems; algorithms for parallel computers; trends in supercomputers and computational physics; supercomputing and related national projects in Japan; application of VLSI in high-energy physics, and single-user systems. See hints under the relevant topics. (orig./HSI)

  6. Rapid prototyping of versatile atom chips for atom interferometry applications.

    Science.gov (United States)

    Kasch, Brian; Squires, Matthew; Olson, Spencer; Kroese, Bethany; Imhof, Eric; Kohn, Rudolph; Stuhl, Benjamin; Schramm, Stacy; Stickney, James

    2016-05-01

    We present recent advances in the manipulation of ultracold atoms with ex-vacuo atom chips (i.e. atom chips that are not inside to the UHV chamber). Details will be presented of an experimental system that allows direct bonded copper (DBC) atom chips to be removed and replaced in minutes, requiring minimal re-optimization of parameters. This system has been used to create Bose-Einstein condensates, as well as magnetic waveguides with precisely tunable axial parameters, allowing double wells, pure harmonic confinement, and modified harmonic traps. We investigate the effects of higher order magnetic field contributions to the waveguide, and the implications for confined atom interferometry.

  7. Design and Performance of the CMS Pixel Detector Readout Chip

    CERN Document Server

    Kästli, H C; Erdmann, W; Hörmann, C; Horisberger, R P; Kotlinski, D; Meier, B; Hoermann, Ch.

    2006-01-01

    The readout chip for the CMS pixel detector has to deal with an enormous data rate. On-chip zero suppression is inevitable and hit data must be buffered locally during the latency of the first level trigger. Dead-time must be kept at a minimum. It is dominated by contributions coming from the readout. To keep it low an analog readout scheme has been adopted where pixel addresses are analog coded. We present the architecture of the final CMS pixel detector readout chip with special emphasis on the analog readout chain. Measurements of its performance are discussed.

  8. Application of software technology to a future spacecraft computer design

    Science.gov (United States)

    Labaugh, R. J.

    1980-01-01

    A study was conducted to determine how major improvements in spacecraft computer systems can be obtained from recent advances in hardware and software technology. Investigations into integrated circuit technology indicated that the CMOS/SOS chip set being developed for the Air Force Avionics Laboratory at Wright Patterson had the best potential for improving the performance of spaceborne computer systems. An integral part of the chip set is the bit slice arithmetic and logic unit. The flexibility allowed by microprogramming, combined with the software investigations, led to the specification of a baseline architecture and instruction set.

  9. Associative Memory Computing Power and Its Simulation

    CERN Document Server

    Volpi, G; The ATLAS collaboration

    2014-01-01

    The associative memory (AM) system is a computing device made of hundreds of AM ASICs chips designed to perform “pattern matching” at very high speed. Since each AM chip stores a data base of 130000 pre-calculated patterns and large numbers of chips can be easily assembled together, it is possible to produce huge AM banks. Speed and size of the system are crucial for real-time High Energy Physics applications, such as the ATLAS Fast TracKer (FTK) Processor. Using 80 million channels of the ATLAS tracker, FTK finds tracks within 100 micro seconds. The simulation of such a parallelized system is an extremely complex task if executed in commercial computers based on normal CPUs. The algorithm performance is limited, due to the lack of parallelism, and in addition the memory requirement is very large. In fact the AM chip uses a content addressable memory (CAM) architecture. Any data inquiry is broadcast to all memory elements simultaneously, thus data retrieval time is independent of the database size. The gr...

  10. Associative Memory computing power and its simulation

    CERN Document Server

    Ancu, L S; The ATLAS collaboration; Britzger, D; Giannetti, P; Howarth, J W; Luongo, C; Pandini, C; Schmitt, S; Volpi, G

    2014-01-01

    The associative memory (AM) system is a computing device made of hundreds of AM ASICs chips designed to perform “pattern matching” at very high speed. Since each AM chip stores a data base of 130000 pre-calculated patterns and large numbers of chips can be easily assembled together, it is possible to produce huge AM banks. Speed and size of the system are crucial for real-time High Energy Physics applications, such as the ATLAS Fast TracKer (FTK) Processor. Using 80 million channels of the ATLAS tracker, FTK finds tracks within 100 micro seconds. The simulation of such a parallelized system is an extremely complex task if executed in commercial computers based on normal CPUs. The algorithm performance is limited, due to the lack of parallelism, and in addition the memory requirement is very large. In fact the AM chip uses a content addressable memory (CAM) architecture. Any data inquiry is broadcast to all memory elements simultaneously, thus data retrieval time is independent of the database size. The gr...

  11. Throwing computing into reverse

    Energy Technology Data Exchange (ETDEWEB)

    Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-09-01

    For more than 50 years, computers have made steady and dramatic improvements, all thanks to Moore’s Law—the exponential increase over time in the number of transistors that can be fabricated on an integrated circuit of a given size. Moore’s Law owed its success to the fact that as transistors were made smaller, they became simultaneously cheaper, faster, and more energy efficient. The payoff from this win-win-win scenario enabled reinvestment in semiconductor fabrication technology that could make even smaller, more densely-packed transistors. And so this virtuous cycle continued, decade after decade. Now though, experts in industry, academia, and government laboratories anticipate that semiconductor miniaturization won’t continue much longer—maybe 10 years or so, at best. Making transistors smaller no longer yields the improvements it used to. The physical characteristics of small transistors forced clock speeds to cease getting faster more than a decade ago, which drove the industry to start building chips with multiple cores. But even multi-core architectures must contend with increasing amounts of “dark silicon,” areas of the chip that must be powered off to avoid overheating.

  12. A Tuning Process in a Tunable Archtecture Computer System

    OpenAIRE

    深沢, 良彰; 岸野, 覚; 門倉, 敏夫

    1986-01-01

    A tuning process in a tunable archtecture computer is described. We have designed a computer system with tunable archtecture. Main components of this computer are four AM2903 bit-slice chips. The control schema of micro instructions is horizontal-type, and the length of each instruction is 104 bits. Our tunable algorithm utilizes an execution history of machine level instructions, because the execution history can be regarded as a property of the user program. In execution histories of simila...

  13. Experiment list: SRX150258 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available CEREBELLUM; and other structures in the BRAIN STEM. 10945554,97.9,14.2,523 GSM939572: ChIP of sonicated who...); and RHOMBENCEPHALON (the hindbrain). The developed brain consists of CEREBRUM;

  14. Experiment list: SRX150262 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available alance, and learn motor skills. 26472027,92.7,6.9,186 GSM939576: ChIP of MNase mononucleosome selected cereb... cerebellar nuclei. Its function is to coordinate voluntary movements, maintain b

  15. Experiment list: SRX143851 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available lance, and learn motor skills. 57796523,71.5,23.1,31516 GSM918759: LICR ChipSeq Cerebellum CTCF adult-8wks s...cerebellar nuclei. Its function is to coordinate voluntary movements, maintain ba

  16. Experiment list: SRX333580 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e/variation=MBD3flox/- mouse Embryonic Fibroblast Cells (MEF) transgenic for DOX inducible OSKM reprogramming || stage in reprogrammi...ng=iPSC || chip antibody=none http://dbarchive.bioscienc

  17. Experiment list: SRX500852 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available cell type=Embryonic Fibroblast Cells (MEF) || genotype/variation=MBD3+/+ transgenic for DOX inducible OSKM reprogramming... || stage in reprogramming=8 days after DOX induction || chip antibod

  18. Experiment list: SRX333559 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available genotype/variation=MBD3+/+ mouse Embryonic Fibroblast Cells (MEF) transgenic for DOX inducible OSKM reprogramming || stage in reprogr...amming=12 days after DOX induction || chip antibody=none

  19. Experiment list: SRX333571 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available duction || genotype/variation=MBD3flox/- mouse Embryonic Fibroblast Cells (MEF) transgenic for DOX inducible OSKM reprogramming... || stage in reprogramming=4 days after DOX induction || chip

  20. Tractor performance monitor based on a single-chip microcomputer

    Energy Technology Data Exchange (ETDEWEB)

    Bedri, A.R.; Marley, S.J.; Buchelle, W.F.; Smay, T.A.

    1981-01-01

    A tractor performance monitor based on a single-chip microcomputer was developed to measure ground speed, slip, fuel consumption (rate and total), total area, theoretical time, and total time. Transducers used are presented in detail. 5 refs.