A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

International Nuclear Information System (INIS)

Li Chen; Liao Huailin; Huang Ru; Wang Yangyuan

2008-01-01

In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications. (cross-disciplinary physics and related areas of science and technology)

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.

2014-06-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

Science.gov (United States)

Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

2018-01-01

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

Ultra-low crosstalk, CMOS compatible waveguide crossings for densely integrated photonic interconnection networks.

Science.gov (United States)

Jones, Adam M; DeRose, Christopher T; Lentine, Anthony L; Trotter, Douglas C; Starbuck, Andrew L; Norwood, Robert A

2013-05-20

We explore the design space for optimizing CMOS compatible waveguide crossings on a silicon photonics platform. This paper presents simulated and experimental excess loss and crosstalk suppression data for vertically integrated silicon nitride over silicon-on-insulator waveguide crossings. Experimental results show crosstalk suppression exceeding -49/-44 dB with simulation results as low as -65/-60 dB for the TE/TM mode in a waveguide crossing with a 410 nm vertical gap.

Ultra compact 45 GHz CMOS compatible Germanium waveguide photodiode with low dark current.

Science.gov (United States)

DeRose, Christopher T; Trotter, Douglas C; Zortman, William A; Starbuck, Andrew L; Fisher, Moz; Watts, Michael R; Davids, Paul S

2011-12-05

We present a compact 1.3 × 4 μm2 Germanium waveguide photodiode, integrated in a CMOS compatible silicon photonics process flow. This photodiode has a best-in-class 3 dB cutoff frequency of 45 GHz, responsivity of 0.8 A/W and dark current of 3 nA. The low intrinsic capacitance of this device may enable the elimination of transimpedance amplifiers in future optical data communication receivers, creating ultra low power consumption optical communications.

Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

Science.gov (United States)

León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

2018-05-01

We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

Wavelength conversion of QAM signals in a low loss CMOS compatible spiral waveguide

DEFF Research Database (Denmark)

Da Ros, Francesco; Porto da Silva, Edson; Zibar, Darko

2017-01-01

We demonstrate wavelength conversion of quadrature amplitude modulation (QAM) signals, including 32-GBd quadrature phase-shift keying and 10-GBd 16-QAM, in a 50-cm long high index doped glass spiral waveguide. The quality of the generated idlers for up to 20 nm of wavelength shift is sufficient...... to achieve a BER performance below the hard decision forward error correction threshold BER performance (...

Integrated Cu-based TM-pass polarizer using CMOS technology platform

KAUST Repository

Ng, Tien Khee

2010-01-01

A transverse-magnetic-pass (TM-pass) copper (Cu) polarizer is proposed and analyzed using the previously published two-dimensional Method-of-Lines beam-propagation model. The proposed polarizer exhibits a simulated high-pass filter characteristics, with TM0 and TE0 mode transmissivity of >70% and <5%, respectively, in the wavelength regime of 1.2-1.6 μm. The polarization extinction ratio (PER) given by 10 log10 (PTM0)/(PTE0) is +11.5 dB across the high-pass wavelength regime. To the best of the authors\\' knowledge, we report here the smallest footprint CMOS-platform compatible TM-polarizer.

Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

Science.gov (United States)

Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

2017-05-01

Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive

CMOS-compatible batch processing of monolayer MoS2 MOSFETs

Science.gov (United States)

Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

2018-04-01

Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

High efficiency grating couplers based on shared process with CMOS MOSFETs

International Nuclear Information System (INIS)

Qiu Chao; Sheng Zhen; Wu Ai-Min; Wang Xi; Zou Shi-Chang; Gan Fu-Wan; Li Le; Albert Pang

2013-01-01

Grating couplers are widely investigated as coupling interfaces between silicon-on-insulator waveguides and optical fibers. In this work, a high-efficiency and complementary metal—oxide—semiconductor (CMOS) process compatible grating coupler is proposed. The poly-Si layer used as a gate in the CMOS metal—oxide—semiconductor field effect transistor (MOSFET) is combined with a normal fully etched grating coupler, which greatly enhances its coupling efficiency. With optimal structure parameters, a coupling efficiency can reach as high as ∼ 70% at a wavelength of 1550 nm as indicated by simulation. From the angle of fabrication, all masks and etching steps are shared between MOSFETs and grating couplers, thereby making the high performance grating couplers easily integrated with CMOS circuits. Fabrication errors such as alignment shift are also simulated, showing that the device is quite tolerant in fabrication. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

Electrical Interconnections Through CMOS Wafers

DEFF Research Database (Denmark)

Rasmussen, Frank Engel

2003-01-01

Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

Energy Technology Data Exchange (ETDEWEB)

Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2012-11-15

Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

International Nuclear Information System (INIS)

Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

2012-01-01

Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

Directory of Open Access Journals (Sweden)

Hongyi Mi

2017-03-01

Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2014-01-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

Growth and optical properties of CMOS-compatible silicon nanowires for photonic devices

Science.gov (United States)

Guichard, Alex Richard

Silicon (Si) is the dominant semiconductor material in both the microelectronic and photovoltaic industries. Despite its poor optical properties, Si is simply too abundant and useful to be completely abandoned in either industry. Since the initial discovery of efficient room temperature photoluminescence (PL) from porous Si and the following discoveries of PL and time-resolved optical gain from Si nanocrystals (Si-nc) in SiO2, many groups have studied the feasibility of making Si-based, CMOS-compatible electroluminescent devices and electrically pumped lasers. These studies have shown that for Si-ne sizes below about 10 nm, PL can be attributed to radiative recombination of confined excitons and quantum efficiencies can reach 90%. PL peak energies are blue-shifted from the bulk Si band edge of 1.1 eV due to the quantum confinement effect and PL decay lifetimes are on mus timescales. However, many unanswered questions still exist about both the ease of carrier injection and various non-radiative and loss mechanisms that are present. A potential alternative material system to porous Si and Si-nc is Si nanowires (SiNWs). In this thesis, I examine the optical properties of SiNWs with diameters in the range of 3-30 nm fabricated by a number of compound metal oxide semiconductor (CMOS) compatible fabrication techniques including Chemical Vapor Deposition on metal nanoparticle coated substrates, catalytic wet etching of bulk Si and top-down electron-beam lithographic patterning. Using thermal oxidation and etching, we can increase the degree of confinement in the SiNWs. I demonstrate PL peaked in the visible and near-infrared (NIR) wavelength ranges that is tunable by controlling the crystalline SiNW core diameter, which is measured with dark field and high-resolution transmission electron microscopy. PL decay lifetimes of the SiNWs are on the order of 50 mus after proper surface passivation, which suggest that the PL is indeed from confined carriers in the SiNW cores

CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

National Research Council Canada - National Science Library

An, S

2001-01-01

.... Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step...

A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

Science.gov (United States)

Fu, Guoqing; Sonkusale, Sameer R

2018-06-01

Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

Design and fabrication of a CMOS-compatible MHP gas sensor

Directory of Open Access Journals (Sweden)

Ying Li

2014-03-01

Full Text Available A novel micro-hotplate (MHP gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO2 film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3% in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

A study of the switching mechanism and electrode material of fully CMOS compatible tungsten oxide ReRAM

Science.gov (United States)

Chien, W. C.; Chen, Y. C.; Lai, E. K.; Lee, F. M.; Lin, Y. Y.; Chuang, Alfred T. H.; Chang, K. P.; Yao, Y. D.; Chou, T. H.; Lin, H. M.; Lee, M. H.; Shih, Y. H.; Hsieh, K. Y.; Lu, Chih-Yuan

2011-03-01

Tungsten oxide (WO X ) resistive memory (ReRAM), a two-terminal CMOS compatible nonvolatile memory, has shown promise to surpass the existing flash memory in terms of scalability, switching speed, and potential for 3D stacking. The memory layer, WO X , can be easily fabricated by down-stream plasma oxidation (DSPO) or rapid thermal oxidation (RTO) of W plugs universally used in CMOS circuits. Results of conductive AFM (C-AFM) experiment suggest the switching mechanism is dominated by the REDOX (Reduction-oxidation) reaction—the creation of conducting filaments leads to a low resistance state and the rupturing of the filaments results in a high resistance state. Our experimental results show that the reactions happen at the TE/WO X interface. With this understanding in mind, we proposed two approaches to boost the memory performance: (i) using DSPO to treat the RTO WO X surface and (ii) using Pt TE, which forms a Schottky barrier with WO X . Both approaches, especially the latter, significantly reduce the forming current and enlarge the memory window.

The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

Directory of Open Access Journals (Sweden)

Liping Wei

2014-09-01

Full Text Available Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies.

Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

Directory of Open Access Journals (Sweden)

Kwang-Jow Gan

2016-06-01

Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

KAUST Repository

Ghoneim, Mohamed T.; Hanna, Amir; Hussain, Muhammad Mustafa

2014-01-01

Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with prefabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.

CMOS compatible fabrication of flexible and semi-transparent FeRAM on ultra-thin bulk monocrystalline silicon (100) fabric

KAUST Repository

Ghoneim, Mohamed T.

2014-08-01

Commercialization of flexible electronics requires reliable, high performance, ultra-compact and low power devices. To achieve them, we fabricate traditional electronics on bulk mono-crystalline silicon (100) and transform the top portion into an ultra-thin flexible silicon fabric with prefabricated devices, preserving ultra-large-scale-integration density and same device performance. This can be done in a cost effective manner due to its full compatibility with standard CMOS processes. In this paper, using the same approach, for the first time we demonstrate a ferroelectric random access memory (FeRAM) cell on flexible silicon fabric platform and assess its functionality and practical potential.

Ge quantum dot arrays grown by ultrahigh vacuum molecular-beam epitaxy on the Si(001) surface: nucleation, morphology, and CMOS compatibility.

Science.gov (United States)

Yuryev, Vladimir A; Arapkina, Larisa V

2011-09-05

Issues of morphology, nucleation, and growth of Ge cluster arrays deposited by ultrahigh vacuum molecular beam epitaxy on the Si(001) surface are considered. Difference in nucleation of quantum dots during Ge deposition at low (≲600°C) and high (≳600°C) temperatures is studied by high resolution scanning tunneling microscopy. The atomic models of growth of both species of Ge huts--pyramids and wedges-- are proposed. The growth cycle of Ge QD arrays at low temperatures is explored. A problem of lowering of the array formation temperature is discussed with the focus on CMOS compatibility of the entire process; a special attention is paid upon approaches to reduction of treatment temperature during the Si(001) surface pre-growth cleaning, which is at once a key and the highest-temperature phase of the Ge/Si(001) quantum dot dense array formation process. The temperature of the Si clean surface preparation, the final high-temperature step of which is, as a rule, carried out directly in the MBE chamber just before the structure deposition, determines the compatibility of formation process of Ge-QD-array based devices with the CMOS manufacturing cycle. Silicon surface hydrogenation at the final stage of its wet chemical etching during the preliminary cleaning is proposed as a possible way of efficient reduction of the Si wafer pre-growth annealing temperature.

Ge quantum dot arrays grown by ultrahigh vacuum molecular-beam epitaxy on the Si(001 surface: nucleation, morphology, and CMOS compatibility

Directory of Open Access Journals (Sweden)

Yuryev Vladimir

2011-01-01

Full Text Available Abstract Issues of morphology, nucleation, and growth of Ge cluster arrays deposited by ultrahigh vacuum molecular beam epitaxy on the Si(001 surface are considered. Difference in nucleation of quantum dots during Ge deposition at low (≲600°C and high (≳600°C temperatures is studied by high resolution scanning tunneling microscopy. The atomic models of growth of both species of Ge huts--pyramids and wedges-- are proposed. The growth cycle of Ge QD arrays at low temperatures is explored. A problem of lowering of the array formation temperature is discussed with the focus on CMOS compatibility of the entire process; a special attention is paid upon approaches to reduction of treatment temperature during the Si(001 surface pre-growth cleaning, which is at once a key and the highest-temperature phase of the Ge/Si(001 quantum dot dense array formation process. The temperature of the Si clean surface preparation, the final high-temperature step of which is, as a rule, carried out directly in the MBE chamber just before the structure deposition, determines the compatibility of formation process of Ge-QD-array based devices with the CMOS manufacturing cycle. Silicon surface hydrogenation at the final stage of its wet chemical etching during the preliminary cleaning is proposed as a possible way of efficient reduction of the Si wafer pre-growth annealing temperature.

Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

KAUST Repository

Ghoneim, Mohamed T.; Alfaraj, Nasir; Torres-Sevilla, Galo A.; Fahad, Hossain M.; Hussain, Muhammad Mustafa

2016-01-01

. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied

A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

Science.gov (United States)

Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

2012-08-01

An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes.

Direct, CMOS In-Line Process Flow Compatible, Sub 100 °C Cu-Cu Thermocompression Bonding Using Stress Engineering

Science.gov (United States)

Panigrahi, Asisa Kumar; Ghosh, Tamal; Kumar, C. Hemanth; Singh, Shiv Govind; Vanjari, Siva Rama Krishna

2018-03-01

Diffusion of atoms across the boundary between two bonding layers is the key for achieving excellent thermocompression Wafer on Wafer bonding. In this paper, we demonstrate a novel mechanism to increase the diffusion across the bonding interface and also shows the CMOS in-line process flow compatible Sub 100 °C Cu-Cu bonding which is devoid of Cu surface treatment prior to bonding. The stress in sputtered Cu thin films was engineered by adjusting the Argon in-let pressure in such a way that one film had a compressive stress while the other film had tensile stress. Due to this stress gradient, a nominal pressure (2 kN) and temperature (75 °C) was enough to achieve a good quality thermocompression bonding having a bond strength of 149 MPa and very low specific contact resistance of 1.5 × 10-8 Ω-cm2. These excellent mechanical and electrical properties are resultant of a high quality Cu-Cu bonding having grain growth between the Cu films across the boundary and extended throughout the bonded region as revealed by Cross-sectional Transmission Electron Microscopy. In addition, reliability assessment of Cu-Cu bonding with stress engineering was demonstrated using multiple current stressing and temperature cycling test, suggests excellent reliable bonding without electrical performance degradation.

Direct, CMOS In-Line Process Flow Compatible, Sub 100 °C Cu-Cu Thermocompression Bonding Using Stress Engineering

Science.gov (United States)

Panigrahi, Asisa Kumar; Ghosh, Tamal; Kumar, C. Hemanth; Singh, Shiv Govind; Vanjari, Siva Rama Krishna

2018-05-01

Diffusion of atoms across the boundary between two bonding layers is the key for achieving excellent thermocompression Wafer on Wafer bonding. In this paper, we demonstrate a novel mechanism to increase the diffusion across the bonding interface and also shows the CMOS in-line process flow compatible Sub 100 °C Cu-Cu bonding which is devoid of Cu surface treatment prior to bonding. The stress in sputtered Cu thin films was engineered by adjusting the Argon in-let pressure in such a way that one film had a compressive stress while the other film had tensile stress. Due to this stress gradient, a nominal pressure (2 kN) and temperature (75 °C) was enough to achieve a good quality thermocompression bonding having a bond strength of 149 MPa and very low specific contact resistance of 1.5 × 10-8 Ω-cm2. These excellent mechanical and electrical properties are resultant of a high quality Cu-Cu bonding having grain growth between the Cu films across the boundary and extended throughout the bonded region as revealed by Cross-sectional Transmission Electron Microscopy. In addition, reliability assessment of Cu-Cu bonding with stress engineering was demonstrated using multiple current stressing and temperature cycling test, suggests excellent reliable bonding without electrical performance degradation.

Low resistive edge contacts to CVD-grown graphene using a CMOS compatible metal

Energy Technology Data Exchange (ETDEWEB)

Shaygan, Mehrdad; Otto, Martin; Sagade, Abhay A.; Neumaier, Daniel [Advanced Microelectronic Center Aachen, AMO GmbH, Aachen (Germany); Chavarin, Carlos A. [Lehrstuhl Werkstoffe der Elektrotechnik, Duisburg-Essen Univ., Duisburg (Germany); Innovations for High Performance Microelectronics, IHP GmbH, Frankfurt (Oder) (Germany); Bacher, Gerd; Mertin, Wolfgang [Lehrstuhl Werkstoffe der Elektrotechnik, Duisburg-Essen Univ., Duisburg (Germany)

2017-11-15

The exploitation of the excellent intrinsic electronic properties of graphene for device applications is hampered by a large contact resistance between the metal and graphene. The formation of edge contacts rather than top contacts is one of the most promising solutions for realizing low ohmic contacts. In this paper the fabrication and characterization of edge contacts to large area CVD-grown monolayer graphene by means of optical lithography using CMOS compatible metals, i.e. Nickel and Aluminum is reported. Extraction of the contact resistance by Transfer Line Method (TLM) as well as the direct measurement using Kelvin Probe Force Microscopy demonstrates a very low width specific contact resistance down to 130 Ωμm. The contact resistance is found to be stable for annealing temperatures up to 150 C enabling further device processing. Using this contact scheme for edge contacts, a field effect transistor based on CVD graphene with a high transconductance of 0.63 mS/μm at 1 V bias voltage is fabricated. (copyright 2017 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Ultralow-loss CMOS copper plasmonic waveguides

DEFF Research Database (Denmark)

Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

2016-01-01

with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

CMOS dot matrix microdisplay

Science.gov (United States)

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

Poly-SiGe for MEMS-above-CMOS sensors

CERN Document Server

Gonzalez Ruiz, Pilar; Witvrouw, Ann

2014-01-01

Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

Science.gov (United States)

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Decal electronics for printed high performance cmos electronic systems

KAUST Repository

Hussain, Muhammad Mustafa

2017-11-23

High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

A design of a wavelength-hopping time-spreading incoherent optical code division multiple access system

International Nuclear Information System (INIS)

Glesk, I.; Baby, V.

2005-01-01

We present the architecture and code design for a highly scalable, 2.5 Gb/s per user optical code division multiple access (OCDMA) system. The system is scalable to 100 potential and more than 10 simultaneous users, each with a bit error rate (BER) of less than 10 -9 . The system architecture uses a fast wavelength-hopping, time-spreading codes. Unlike frequency and phase sensitive coherent OCDMA systems, this architecture utilizes standard on off keyed optical pulses allocated in the time and wavelength dimensions. This incoherent OCDMA approach is compatible with existing WDM optical networks and utilizes off the shelf components. We discuss the novel optical subsystem design for encoders and decoders that enable the realization of a highly scalable incoherent OCDMA system with rapid reconfigurability. A detailed analysis of the scalability of the two dimensional code is presented and select network deployment architectures for OCDMA are discussed (Authors)

Micromachined high-performance RF passives in CMOS substrate

International Nuclear Information System (INIS)

Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

2016-01-01

This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

Science.gov (United States)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Single-photon sensitive fast ebCMOS camera system for multiple-target tracking of single fluorophores: application to nano-biophotonics

Science.gov (United States)

Cajgfinger, Thomas; Chabanat, Eric; Dominjon, Agnes; Doan, Quang T.; Guerin, Cyrille; Houles, Julien; Barbier, Remi

2011-03-01

Nano-biophotonics applications will benefit from new fluorescent microscopy methods based essentially on super-resolution techniques (beyond the diffraction limit) on large biological structures (membranes) with fast frame rate (1000 Hz). This trend tends to push the photon detectors to the single-photon counting regime and the camera acquisition system to real time dynamic multiple-target tracing. The LUSIPHER prototype presented in this paper aims to give a different approach than those of Electron Multiplied CCD (EMCCD) technology and try to answer to the stringent demands of the new nano-biophotonics imaging techniques. The electron bombarded CMOS (ebCMOS) device has the potential to respond to this challenge, thanks to the linear gain of the accelerating high voltage of the photo-cathode, to the possible ultra fast frame rate of CMOS sensors and to the single-photon sensitivity. We produced a camera system based on a 640 kPixels ebCMOS with its acquisition system. The proof of concept for single-photon based tracking for multiple single-emitters is the main result of this paper.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

Science.gov (United States)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Application of CMOS Technology to Silicon Photomultiplier Sensors

Science.gov (United States)

D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-01-01

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

PARAMETERIZED LAYOUT SYNTHESIS OF A CMOS-COMPATIBLE SCANNING MICROMIRROR WITH ELECTROTHERMAL ACTUATION AND BIMODAL RESONANT BEHAVIOR

Directory of Open Access Journals (Sweden)

Sergio Camacho León

2011-01-01

Full Text Available Este trabajo presenta una metodología de síntesis de parámetros para la automatización del diseño de un microespejo de escaneado compatible CMOS con comportamiento resonante bimodal. El microespejo está suspendido por actuadores térmicos bimorfos en voladizo con accionamiento fuera del plano. La metodología propone la optimización de espesores y el escaneo en el segundo modo de resonancia como estrategias para superar el conflicto característico entre el desempeño estático y dinámico del dispositivo. El objetivo es obtener automáticamente los parámetros de diseño del dispositivo que, de manera concurrente, maximizan el ángulo de rotación, minimizan el consumo de energía y satisfacen tanto las limitaciones de fabricación de un proceso CMOS estándar como las especificaciones de alto nivel para la posición del eje de rotación en el segundo modo de resonancia, la frecuencia de escaneado y el voltaje máximo de actuación. La metodología utiliza un espacio de diseño de nivel intermedio, definido por la razón de resistencia térmica a resistencia eléctrica del dispositivo a temperatura ambiente, para acoplar las restricciones del esfuerzo térmico máximo con la densidad de corriente eléctrica máxima de los materiales CMOS. El procedimiento de evaluación de funciones objetivos se desarrolla sobre la base de un modelo de elementos concentrados de la resistencia térmica del dispositivo para explorar sistemáticamente el espacio de diseño utilizando variaciones paramétricas. La metodología se aplica para diseñar un microescáner que tiene aplicaciones en sistemas imagenológicos de coherencia óptica. El desempeño del microescáner sintetizado es verificado por simulaciones mediante el método de elementos finitos. Los resultados obtenidos numéricamente presentan un buen ajuste con las especificaciones de alto nivel.

A novel multi-actuation CMOS RF MEMS switch

Science.gov (United States)

Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

2008-12-01

This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

International Nuclear Information System (INIS)

Yu Xiaomei; Tang Yaquan; Zhang Haitao

2008-01-01

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

Science.gov (United States)

Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2013-05-06

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

Tuning direct bandgap GeSn/Ge quantum dots' interband and intraband useful emission wavelength: Towards CMOS compatible infrared optical devices

Science.gov (United States)

Baira, Mourad; Salem, Bassem; Madhar, Niyaz Ahamad; Ilahi, Bouraoui

2018-05-01

In this work, interband and intraband optical transitions from direct bandgap strained GeSn/Ge quantum dots are numerically tuned by evaluating the confined energies for heavy holes and electrons in D- and L-valley. The practically exploitable emission wavelength ranges for efficient use in light emission and sensing should fulfill specific criteria imposing the electrons confined states in D-valley to be sufficiently below those in L-valley. This study shows that GeSn quantum dots offer promising opportunity towards high efficient group IV based infrared optical devices operating in the mid-IR and far-IR wavelength regions.

Low-loss CMOS copper plasmonic waveguides at the nanoscale (Conference Presentation)

Science.gov (United States)

Fedyanin, Dmitry Y.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.; Volkov, Valentyn S.

2016-05-01

Implementation of optical components in microprocessors can increase their performance by orders of magnitude. However, the size of optical elements is fundamentally limited by diffraction, while miniaturization is one of the essential concepts in the development of high-speed and energy-efficient electronic chips. Surface plasmon polaritons (SPPs) are widely considered to be promising candidates for the next generation of chip-scale technology thanks to the ability to break down the fundamental diffraction limit and manipulate optical signals at the truly nometer scale. In the past years, a variety of deep-subwavelength plasmonic structures have been proposed and investigated, including dielectric-loaded SPP waveguides, V-groove waveguides, hybrid plasmonic waveguides and metal nanowires. At the same time, for practical application, such waveguide structures must be integrated on a silicon chip and be fabricated using CMOS fabrication process. However, to date, acceptable characteristics have been demonstrated only with noble metals (gold and silver), which are not compatible with industry-standard manufacturing technologies. On the other hand, alternative materials introduce enormous propagation losses due absorption in the metal. This prevents plasmonic components from implementation in on-chip nanophotonic circuits. In this work, we experimentally demonstrate for the first time that copper plasmonic waveguides fabricated in a CMOS compatible process can outperform gold waveguides showing the same level of mode confinement and lower propagation losses. At telecommunication wavelengths, the fabricated ultralow-loss deep-subwavelength hybrid plasmonic waveguides ensure a relatively long propagation length of more than 50 um along with strong mode confinement with the mode size down to lambda^2/70, which is confirmed by direct scanning near-field optical microscopy (SNOM) measurements. These results create the backbone for design and development of high

A CMOS 128-APS linear array integrated with a LVOF for highsensitivity and high-resolution micro-spectrophotometry

NARCIS (Netherlands)

Liu, C.; Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

2010-01-01

A linear array of 128 Active Pixel Sensors has been developed in standard CMOS technology and a Linear Variable Optical Filter (LVOF) is added using CMOS-compatible post-process, resulting in a single chip highly-integrated highresolution microspectrometer. The optical requirements imposed by the

Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors

NARCIS (Netherlands)

Chen, Y.; Theuwissen, A.J.P.; Chae, Y.

2011-01-01

This paper presents a low noise CMOS image sensor (CIS) using 10/12 bit configurable column-parallel single slope ADCs (SS-ADCs) and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with a pinned-photodiode as photon detector. The test sensor was

Investigation on thermodynamics of ion-slicing of GaN and heterogeneously integrating high-quality GaN films on CMOS compatible Si(100) substrates.

Science.gov (United States)

Huang, Kai; Jia, Qi; You, Tiangui; Zhang, Runchun; Lin, Jiajie; Zhang, Shibin; Zhou, Min; Zhang, Bo; Yu, Wenjie; Ou, Xin; Wang, Xi

2017-11-08

Die-to-wafer heterogeneous integration of single-crystalline GaN film with CMOS compatible Si(100) substrate using the ion-cutting technique has been demonstrated. The thermodynamics of GaN surface blistering is in-situ investigated via a thermal-stage optical microscopy, which indicates that the large activation energy (2.5 eV) and low H ions utilization ratio (~6%) might result in the extremely high H fluence required for the ion-slicing of GaN. The crystalline quality, surface topography and the microstructure of the GaN films are characterized in detail. The full width at half maximum (FWHM) for GaN (002) X-ray rocking curves is as low as 163 arcsec, corresponding to a density of threading dislocation of 5 × 10 7  cm -2 . Different evolution of the implantation-induced damage was observed and a relationship between the damage evolution and implantation-induced damage is demonstrated. This work would be beneficial to understand the mechanism of ion-slicing of GaN and to provide a platform for the hybrid integration of GaN devices with standard Si CMOS process.

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

KAUST Repository

Chen, Min Cheng; Lin, Chia Yi; Li, Kai Hsin; Li, Lain-Jong; Chen, Chang Hsiao; Chuang, Cheng Hao; Lee, Ming Dao; Chen, Yi Ju; Hou, Yun Fang; Lin, Chang Hsien; Chen, Chun Chi; Wu, Bo Wei; Wu, Cheng San; Yang, Ivy; Lee, Yao Jen; Yeh, Wen Kuan; Wang, Tahui; Yang, Fu Liang; Hu, Chenming

2014-01-01

Stackable 3DFETs such as FinFET using hybrid Si/MoS2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) Ion,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. © 2014 IEEE.

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

KAUST Repository

Chen, Min Cheng

2014-12-01

Stackable 3DFETs such as FinFET using hybrid Si/MoS2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) Ion,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. © 2014 IEEE.

Construction of a single/multiple wavelength RZ optical pulse source at 40 GHz by use of wavelength conversion in a high-nonlinearity DSF-NOLM

DEFF Research Database (Denmark)

Yu, Jianjun; Yujun, Qian; Jeppesen, Palle

2001-01-01

A single or multiple wavelength RZ optical pulse source at 40 GHz is successfully obtained by using wavelength conversion in a nonlinear optical loop mirror consisting of high nonlinearity-dispersion shifted fiber.......A single or multiple wavelength RZ optical pulse source at 40 GHz is successfully obtained by using wavelength conversion in a nonlinear optical loop mirror consisting of high nonlinearity-dispersion shifted fiber....

Electromagnetic Investigation of a CMOS MEMS Inductive Microphone

Directory of Open Access Journals (Sweden)

Farès TOUNSI

2009-09-01

Full Text Available This paper presents a detailed electromagnetic modeling for a new structure of a monolithic CMOS micromachined inductive microphone. We have shown, that the use of an alternative current (AC in the primary fixed inductor results in a substantially higher induced voltage in the secondary inductor comparing to the case when a direct current (DC is used. The expected increase of the induced voltage can be expressed by a voltage ratio of AC and DC solutions that is in the range of 3 to 6. A prototype fabrication of this microphone has been realized using a combination of standard CMOS 0.6 µm process with a CMOS-compatible post-process consisting in a bulk micromachining technology. The output voltage of the electrodynamic microphone that achieves the µV range can be increased by the use of the symmetric dual-layer spiral inductor structure.

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

Science.gov (United States)

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

CMOS-compatible silicon nanowire field-effect transistors for ultrasensitive and label-free microRNAs sensing.

Science.gov (United States)

Lu, Na; Gao, Anran; Dai, Pengfei; Song, Shiping; Fan, Chunhai; Wang, Yuelin; Li, Tie

2014-05-28

MicroRNAs (miRNAs) have been regarded as promising biomarkers for the diagnosis and prognosis of early-stage cancer as their expression levels are associated with different types of human cancers. However, it is a challenge to produce low-cost miRNA sensors, as well as retain a high sensitivity, both of which are essential factors that must be considered in fabricating nanoscale biosensors and in future biomedical applications. To address such challenges, we develop a complementary metal oxide semiconductor (CMOS)-compatible SiNW-FET biosensor fabricated by an anisotropic wet etching technology with self-limitation which provides a much lower manufacturing cost and an ultrahigh sensitivity. This nanosensor shows a rapid (< 1 minute) detection of miR-21 and miR-205, with a low limit of detection (LOD) of 1 zeptomole (ca. 600 copies), as well as an excellent discrimination for single-nucleotide mismatched sequences of tumor-associated miRNAs. To investigate its applicability in real settings, we have detected miRNAs in total RNA extracted from lung cancer cells as well as human serum samples using the nanosensors, which demonstrates their potential use in identifying clinical samples for early diagnosis of cancer. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

NARCIS (Netherlands)

Lee, M.J.; Youn, J.S.; Park, K.Y.; Choi, W.Y.

2014-01-01

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche

Fabrication of Large Area Fishnet Optical Metamaterial Structures Operational at Near-IR Wavelengths

Directory of Open Access Journals (Sweden)

Dennis W. Prather

2010-12-01

Full Text Available In this paper, we demonstrate a fabrication process for large area (2 mm × 2 mm fishnet metamaterial structures for near IR wavelengths. This process involves: (a defining a sacrificial Si template structure onto a quartz wafer using deep-UV lithography and a dry etching process (b deposition of a stack of Au-SiO2-Au layers and (c a ‘lift-off’ process which removes the sacrificial template structure to yield the fishnet structure. The fabrication steps in this process are compatible with today’s CMOS technology making it eminently well suited for batch fabrication. Also, depending on area of the exposure mask available for patterning the template structure, this fabrication process can potentially lead to optical metamaterials spanning across wafer-size areas.

CMOS MEMS capacitive absolute pressure sensor

International Nuclear Information System (INIS)

Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

2013-01-01

This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

Science.gov (United States)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Dual wavelength multiple-angle light scattering system for cryptosporidium detection

Science.gov (United States)

Buaprathoom, S.; Pedley, S.; Sweeney, S. J.

2012-06-01

A simple, dual wavelength, multiple-angle, light scattering system has been developed for detecting cryptosporidium suspended in water. Cryptosporidium is a coccidial protozoan parasite causing cryptosporidiosis; a diarrheal disease of varying severity. The parasite is transmitted by ingestion of contaminated water, particularly drinking-water, but also accidental ingestion of bathing-water, including swimming pools. It is therefore important to be able to detect these parasites quickly, so that remedial action can be taken to reduce the risk of infection. The proposed system combines multiple-angle scattering detection of a single and two wavelengths, to collect relative wavelength angle-resolved scattering phase functions from tested suspension, and multivariate data analysis techniques to obtain characterizing information of samples under investigation. The system was designed to be simple, portable and inexpensive. It employs two diode lasers (violet InGaN-based and red AlGaInP-based) as light sources and silicon photodiodes as detectors and optical components, all of which are readily available. The measured scattering patterns using the dual wavelength system showed that the relative wavelength angle-resolved scattering pattern of cryptosporidium oocysts was significantly different from other particles (e.g. polystyrene latex sphere, E.coli). The single wavelength set up was applied for cryptosporidium oocysts'size and relative refractive index measurement and differential measurement of the concentration of cryptosporidium oocysts suspended in water and mixed polystyrene latex sphere suspension. The measurement results showed good agreement with the control reference values. These results indicate that the proposed method could potentially be applied to online detection in a water quality control system.

Very low drift and high sensitivity of nanocrystal-TiO2 sensing membrane on pH-ISFET fabricated by CMOS compatible process

International Nuclear Information System (INIS)

Bunjongpru, W.; Sungthong, A.; Porntheeraphat, S.; Rayanasukha, Y.; Pankiew, A.; Jeamsaksiri, W.; Srisuwan, A.; Chaisriratanakul, W.; Chaowicharat, E.; Klunngien, N.; Hruanun, C.; Poyai, A.; Nukeaw, J.

2013-01-01

High sensitivity and very low drift rate pH sensors are successfully prepared by using nanocrystal-TiO 2 as sensing membrane of ion sensitive field effect transistor (ISFET) device fabricated via CMOS process. This paper describes the physical properties and sensing characteristics of the TiO 2 membrane prepared by annealing Ti and TiN thin films that deposited on SiO 2 /p-Si substrates through reactive DC magnetron sputtering system. The X-ray diffraction, scanning electron microscopy and Auger electron spectroscopy were used to investigate the structural and morphological features of deposited films after they had been subjected to annealing at various temperatures. The experimental results are interpreted in terms of the effects of amorphous-to-crystalline phase transition and subsequent oxidation of the annealed films. The electrolyte–insulator–semiconductor (EIS) device incorporating Ti-O-N membrane that had been obtained by annealing of TiN thin film at 850 °C exhibited a higher sensitivity (57 mV/pH), a higher linearity (1), a lower hysteresis voltage (1 mV in the pH cycle of 7 → 4 → 7 → 10 → 7), and a smaller drift rate (0.246 mV/h) than did those devices prepared at the other annealing temperatures. Furthermore, this pH-sensing device fabrication process is fully compatible with CMOS fabrication process technology.

A new CMOS SiGeC avalanche photo-diode pixel for IR sensing

Science.gov (United States)

Augusto, Carlos; Forester, Lynn; Diniz, Pedro C.

2009-05-01

Near-infra-red sensing with silicon is limited by the bandgap of silicon, corresponding to a maximum wavelength of absorption of 1.1 μm. A new type of CMOS sensor is presented, which uses a SiGeC epitaxial film in conjunction with novel device architecture to extend absorption into the infra-red. The SiGeC film composition and thickness determine the spectrum of absorption; in particular for SiGeC superlattices, the layer ordering to create pseudo direct bandgaps is the critical parameter. In this new device architecture, the p-type SiGeC film is grown on an active region surrounded by STI, linked to the S/D region of an adjacent NMOS, under the STI by a floating N-Well. On a n-type active, a P-I-N device is formed, and on a p-type active, a P-I-P device is formed, each sensing different regions of the spectrum. The SiGeC films can be biased for avalanche operation, as the required vertical electric field is confined to the region near the heterojunction interface, thereby not affecting the gate oxide of the adjacent NMOS. With suitable heterojunction and doping profiles, the avalanche region can also be bandgap engineered, allowing for avalanche breakdown voltages that are compatible with CMOS devices.

Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

Science.gov (United States)

Kim, Sung Yoon; Seo, Jae Hwa; Yoon, Young Jun; Lee, Ho-Young; Lee, Seong Min; Cho, Seongjae; Kang, In Man

2015-10-01

In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

Directory of Open Access Journals (Sweden)

Min-Kyu Kim

2015-12-01

Full Text Available This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs. The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

A back-illuminated megapixel CMOS image sensor

Science.gov (United States)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

Flexible-CMOS and biocompatible piezoelectric AlN material for MEMS applications

International Nuclear Information System (INIS)

Jackson, Nathan; Keeney, Lynette; Mathewson, Alan

2013-01-01

The development of a CMOS compatible flexible piezoelectric material is desired for numerous applications and in particular for biomedical MEMS devices. Aluminum nitride (AlN) is the most commonly used CMOS compatible piezoelectric material, which is typically deposited on Si in order to enhance the c-axis (002) crystal orientation which gives AlN its high piezoelectric properties. This paper reports on the successful deposition of AlN on polyimide (PI-2611) material. The AlN deposited has a FWHM (002) value of 5.1° and a piezoelectric d 33 value of 1.12 pm V −1 , and SEM images show high quality columnar grains. The highly crystalline AlN material is due to the semi-crystalline properties of the polyimide film used. Cytotoxicity testing showed the AlN/polyimide material to be non-toxic to 3T3 cells and primary neurons. Surface properties of the AlN/polyimide film were evaluated as they have a significant effect on the adhesion of cells to the film. The results show neurons adhering to the AlN surface. The results of this paper show the characterization of a new flexible-CMOS and biocompatible AlN/polyimide material for MEMS devices with improved crystallinity and piezoelectric properties. (paper)

Ultra-low Voltage CMOS Cascode Amplifier

OpenAIRE

Lehmann, Torsten; Cassia, Marco

2000-01-01

In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique.

Ultra-low Voltage CMOS Cascode Amplifier

DEFF Research Database (Denmark)

Lehmann, Torsten; Cassia, Marco

2000-01-01

In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique......, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique....

Athermal and wavelength-trimmable photonic filters based on TiO₂-cladded amorphous-SOI.

Science.gov (United States)

Lipka, Timo; Moldenhauer, Lennart; Müller, Jörg; Trieu, Hoc Khiem

2015-07-27

Large-scale integrated silicon photonic circuits suffer from two inevitable issues that boost the overall power consumption. First, fabrication imperfections even on sub-nm scale result in spectral device non-uniformity that require fine-tuning during device operation. Second, the photonic devices need to be actively corrected to compensate thermal drifts. As a result significant amount of power is wasted if no athermal and wavelength-trimmable solutions are utilized. Consequently, in order to minimize the total power requirement of photonic circuits in a passive way, trimming methods are required to correct the device inhomogeneities from manufacturing and athermal solutions are essential to oppose temperature fluctuations of the passive/active components during run-time. We present an approach to fabricate CMOS backend-compatible and athermal passive photonic filters that can be corrected for fabrication inhomogeneities by UV-trimming based on low-loss amorphous-SOI waveguides with TiO2 cladding. The trimming of highly confined 10 μm ring resonators is proven over a free spectral range retaining athermal operation. The athermal functionality of 2nd-order 5 μm add/drop microrings is demonstrated over 40°C covering a broad wavelength interval of 60 nm.

Materials and processing approaches for foundry-compatible transient electronics

Science.gov (United States)

Chang, Jan-Kai; Fang, Hui; Bower, Christopher A.; Song, Enming; Yu, Xinge; Rogers, John A.

2017-07-01

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

Science.gov (United States)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

Radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

Pikor, A.; Reiss, E.M.

1980-01-01

Substantial effort has been directed at radiation-hardening CMOS integrated circuits using various oxide processes. While most of these integrated circuits have been successful in demonstrating megarad hardness, further investigations have shown that the 'wet-oxide process' is most compatible with the RCA CD4000 Series process. This article describes advances in the wet-oxide process that have resulted in multimegarad hardness and yield to MIL-M-38510 screening requirements. The implementation of these advances into volume manufacturing is geared towards supplying devices for aerospace requirements such as the Defense Meterological Satellite program (DMSP) and the Global Positioning Satellite (GPS). (author)

CMOS circuits manual

CERN Document Server

Marston, R M

1995-01-01

CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

Micro- and nano-scale optical devices for high density photonic integrated circuits at near-infrared wavelengths

Science.gov (United States)

Chatterjee, Rohit

In this research work, we explore fundamental silicon-based active and passive photonic devices that can be integrated together to form functional photonic integrated circuits. The devices which include power splitters, switches and lenses are studied starting from their physics, their design and fabrication techniques and finally from an experimental standpoint. The experimental results reveal high performance devices that are compatible with standard CMOS fabrication processes and can be easily integrated with other devices for near infrared telecom applications. In Chapter 2, a novel method for optical switching using nanomechanical proximity perturbation technique is described and demonstrated. The method which is experimentally demonstrated employs relatively low powers, small chip footprint and is compatible with standard CMOS fabrication processes. Further, in Chapter 3, this method is applied to develop a hitless bypass switch aimed at solving an important issue in current wavelength division multiplexing systems namely hitless switching of reconfigurable optical add drop multiplexers. Experimental results are presented to demonstrate the application of the nanomechanical proximity perturbation technique to practical situations. In Chapter 4, a fundamental photonic component namely the power splitter is described. Power splitters are important components for any photonic integrated circuits because they help split the power from a single light source to multiple devices on the same chip so that different operations can be performed simultaneously. The power splitters demonstrated in this chapter are based on multimode interference principles resulting in highly compact low loss and highly uniform power splitting to split the power of the light from a single channel to two and four channels. These devices can further be scaled to achieve higher order splitting such as 1x16 and 1x32 power splits. Finally in Chapter 5 we overcome challenges in device

UV lithography-based protein patterning on silicon: Towards the integration of bioactive surfaces and CMOS electronics

Energy Technology Data Exchange (ETDEWEB)

Lenci, S., E-mail: silvia.lenci@iet.unipi.it [Dipartimento di Ingegneria dell' Informazione, via G.Caruso 16, Pisa I-56122 (Italy); Tedeschi, L. [Istituto di Fisiologia Clinica - CNR, via G. Moruzzi 1, Pisa I-56124 (Italy); Pieri, F. [Dipartimento di Ingegneria dell' Informazione, via G.Caruso 16, Pisa I-56122 (Italy); Domenici, C. [Istituto di Fisiologia Clinica - CNR, via G. Moruzzi 1, Pisa I-56124 (Italy)

2011-08-01

A simple and fast methodology for protein patterning on silicon substrates is presented, providing an insight into possible issues related to the interaction between biological and microelectronic technologies. The method makes use of standard photoresist lithography and is oriented towards the implementation of biosensors containing Complementary Metal-Oxide-Semiconductor (CMOS) conditioning circuitry. Silicon surfaces with photoresist patterns were prepared and hydroxylated by means of resist- and CMOS backend-compatible solutions. Subsequent aminosilane deposition and resist lift-off in organic solvents resulted into well-controlled amino-terminated geometries. The discussion is focused on resist- and CMOS-compatibility problems related to the used chemicals. Some samples underwent gold nanoparticle (Au NP) labeling and Scanning Electron Microscopy (SEM) observation, in order to investigate the quality of the silane layer. Antibodies were immobilized on other samples, which were subsequently exposed to a fluorescently labeled antigen. Fluorescence microscopy observation showed that this method provides spatially selective immobilization of protein layers onto APTES-patterned silicon samples, while preserving protein reactivity inside the desired areas and low non-specific adsorption elsewhere. Strong covalent biomolecule binding was achieved, giving stable protein layers, which allows stringent binding conditions and a good binding specificity, really useful for biosensing.

High power multiple wavelength diode laser stack for DPSSL application without temperature control

Science.gov (United States)

Hou, Dong; Yin, Xia; Wang, Jingwei; Chen, Shi; Zhan, Yun; Li, Xiaoning; Fan, Yingmin; Liu, Xingsheng

2018-02-01

High power diode laser stack is widely used in pumping solid-state laser for years. Normally an integrated temperature control module is required for stabilizing the output power of solid-state laser, as the output power of the solid-state laser highly depends on the emission wavelength and the wavelength shift of diode lasers according to the temperature changes. However the temperature control module is inconvenient for this application, due to its large dimension, high electric power consumption and extra adding a complicated controlling system. Furthermore, it takes dozens of seconds to stabilize the output power when the laser system is turned on. In this work, a compact hard soldered high power conduction cooled diode laser stack with multiple wavelengths is developed for stabilizing the output power of solid-state laser in a certain temperature range. The stack consists of 5 laser bars with the pitch of 0.43mm. The peak output power of each bar in the diode laser stack reaches as much as 557W and the combined lasing wavelength spectrum profile spans 15nm. The solidstate laser, structured with multiple wavelength diode laser stacks, allows the ambient temperature change of 65°C without suddenly degrading the optical performance.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

International Nuclear Information System (INIS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.

2016-01-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

Science.gov (United States)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

Energy Technology Data Exchange (ETDEWEB)

Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

2016-09-21

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

Science.gov (United States)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Rimoldi, Marco; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

Advanced CMOS device technologies for 45 nm node and below

Directory of Open Access Journals (Sweden)

A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans

2007-01-01

Full Text Available We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG candidates for scaled CMOS technologies are fully silicided (FUSI gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff, meeting the ITRS 45 nm node requirement for low-power (LP CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.

Dual-wavelength phase-shifting digital holography selectively extracting wavelength information from wavelength-multiplexed holograms.

Science.gov (United States)

Tahara, Tatsuki; Mori, Ryota; Kikunaga, Shuhei; Arai, Yasuhiko; Takaki, Yasuhiro

2015-06-15

Dual-wavelength phase-shifting digital holography that selectively extracts wavelength information from five wavelength-multiplexed holograms is presented. Specific phase shifts for respective wavelengths are introduced to remove the crosstalk components and extract only the object wave at the desired wavelength from the holograms. Object waves in multiple wavelengths are selectively extracted by utilizing 2π ambiguity and the subtraction procedures based on phase-shifting interferometry. Numerical results show the validity of the proposed technique. The proposed technique is also experimentally demonstrated.

Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

International Nuclear Information System (INIS)

Miucci, A; Gonzalez-Sevilla, S; Ferrere, D; Iacobucci, G; Rosa, A La; Muenstermann, D; Gonella, L; Hemperek, T; Hügging, F; Krüger, H; Obermann, T; Wermes, N; Garcia-Sciveres, M; Backhaus, M; Capeans, M; Feigl, S; Nessi, M; Pernegger, H; Ristic, B; George, M

2014-01-01

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

FEM Analysis of Sezawa Mode SAW Sensor for VOC Based on CMOS Compatible AlN/SiO2/Si Multilayer Structure

Directory of Open Access Journals (Sweden)

Muhammad Zubair Aslam

2018-05-01

Full Text Available A Finite Element Method (FEM simulation study is conducted, aiming to scrutinize the sensitivity of Sezawa wave mode in a multilayer AlN/SiO2/Si Surface Acoustic Wave (SAW sensor to low concentrations of Volatile Organic Compounds (VOCs, that is, trichloromethane, trichloroethylene, carbon tetrachloride and tetrachloroethene. A Complimentary Metal-Oxide Semiconductor (CMOS compatible AlN/SiO2/Si based multilayer SAW resonator structure is taken into account for this purpose. In this study, first, the influence of AlN and SiO2 layers’ thicknesses over phase velocities and electromechanical coupling coefficients (k2 of two SAW modes (i.e., Rayleigh and Sezawa is analyzed and the optimal thicknesses of AlN and SiO2 layers are opted for best propagation characteristics. Next, the study is further extended to analyze the mass loading effect on resonance frequencies of SAW modes by coating a thin Polyisobutylene (PIB polymer film over the AlN surface. Finally, the sensitivity of the two SAW modes is examined for VOCs. This study concluded that the sensitivity of Sezawa wave mode for 1 ppm of selected volatile organic gases is twice that of the Rayleigh wave mode.

Si light-emitting device in integrated photonic CMOS ICs

Science.gov (United States)

Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

2017-07-01

The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

CMOS VLSI Active-Pixel Sensor for Tracking

Science.gov (United States)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

A study on the multiple dynamic wavelength distribution for gigabit capable passive optical networks

Directory of Open Access Journals (Sweden)

Gustavo Adolfo Puerto Leguizamón

2014-04-01

Full Text Available This paper presents a data traffic based study aiming at evaluating the impact of dynamic wavelength allocation on a Gigabit capable Passive Optical Network (GPON. In Passive Optical Networks (PON, an Optical Line Terminal (OLT feeds different PONs in such a way that a given wavelength channel is evenly distributed between the Optical Network Units (ONU at each PON. However, PONs do not specify any kind of dynamic behavior on the way the wavelengths are allocated in the network, a completely static distribution is implemented instead. In thispaper we evaluate the network performance in terms of packet losses and throughput for a number of ONUs being out-of-profile while featuring a given percentage of traffic in excess for a fixed wavelength distribution and for multiple dynamic wavelength allocation. Results show that for a multichannel operation with four wavelengths, the network throughput increases up to a rough value of 19% while the packet losses drop from 22 % to 1.8 % as compared with a static wavelength distribution.

Multiple scattering wavelength dependent backscattering of kaolin dust in the IR: Measurements and theory

Science.gov (United States)

Ben-David, Avishai

1992-01-01

Knowing the optical properties of aerosol dust is important for designing electro-optical systems and for modeling the effect on propagation of light in the atmosphere. As CO2 lidar technology becomes more advanced and is used for multiwavelength measurements, information on the wavelength dependent backscattering of aerosol dust particles is required. The volume backscattering coefficient of aerosols in the IR is relatively small. Thus, only a few field measurements of backscattering, usually at only a few wavelengths, are reported in the literature. We present spectral field measurements of backscattering of kaolin dust in the 9-11 micron wavelength range. As the quantity of dust increases, multiple scattering contributes more to the measured backscattered signal. The measurements show the effect of the dust quantity of the spectral backscatter measurements. A simple analytical two stream radiative transfer model is applied to confirm the measurements and to give insight to the multiple scattering spectra of backscattering.

Design and simulation of resistive SOI CMOS micro-heaters for high temperature gas sensors

International Nuclear Information System (INIS)

Iwaki, T; Covington, J A; Udrea, F; Ali, S Z; Guha, P K; Gardner, J W

2005-01-01

This paper describes the design of doped single crystal silicon (SCS) microhotplates for gas sensors. Resistive heaters are formed by an n+/p+ implantation into a Silicon-On-Insulator (SOI) wafer with a post-CMOS deep reactive ion etch to remove the silicon substrate. Hence they are fully compatible with CMOS technologies and allows for the integration of associated drive/detection circuitry. 2D electro-thermal models have been constructed and the results of numerical simulations using FEMLAB[reg] are given. Simulations show these micro-hotplates can operate at temperatures of 500 deg. C with a drive voltage of only 5 V and a power consumption of less than 100 mW

A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

Science.gov (United States)

Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

2017-04-01

The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors

CERN Document Server

Hervé, C

2002-01-01

This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of +-0.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 mu m BiCMOS technology. Time critical inputs are PECL compatible whereas other signals are CMOS compatible. A second application specific integrated circuit (ASIC) has been developed which translates NIM electrical levels to PECL ones. Both circuits are used to assemble board level TDCs complying with industry standards like VME, NIM and PCI.

Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

KAUST Repository

Ghoneim, Mohamed T.

2016-05-18

We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOₓ) high-κ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide-semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5-5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications.

CMOS Pixel Development for the ATLAS Experiment at HL-LHC

CERN Document Server

Ristic, Branislav; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on technologies that allow to use high depletion voltages (HV-MAPS) and high resistivity wafers (HR-MAPS) for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics to be embedded safely into the sensor substrate. We are investigating depleted CMOS pixels with monolithic or hybrid designs concerning their suitability for high rate, fast timing and high radiation operation at LHC. This paper will discuss recent results on the main candidate technologies and the current development towards a monolithic solution.

Evaluation of the upset risk in CMOS SRAM through full three dimensional simulation

International Nuclear Information System (INIS)

Moreau, Y.; Gasiot, J.; Duzellier, S.

1995-01-01

Upsets caused by incident heavy ion on CMOS static RAM are studied here. Three dimensional device simulations, based on a description of a full epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular influences of hit location and incidence angle are examined

Analysis of CMOS Compatible Cu-Based TM-Pass Optical Polarizer

KAUST Repository

Ng, Tien Khee

2012-02-10

A transverse-magnetic-pass (TM-pass) optical polarizer based on Cu complementary metal-oxide-semiconductor technology platform is proposed and analyzed using the 2-D method-of-lines numerical model. In designing the optimum configuration for the polarizer, it was found that the metal-insulator-metal (MIM) polarizer structure is superior compared to the insulator-metal-insulator polarizer structure due to its higher polarization extinction ratio (PER) and low insertion loss. An optimized MIM TM-pass polarizer exhibits simulated long wavelength pass filter characteristics of > ?1.2 ?m, with fundamental TM 0 and TE 0 mode transmissivity of >70% and <5%, respectively, and with PER ?11.5 dB in the wavelength range of 1.2-1.6 ?m. The subwavelength and submicrometer features of this TM-polarizer are potentially suitable for compact and low power photonics integrated circuit implementation on silicon-based substrates. © 1989-2012 IEEE.

Tailoring Chirped Moiré Fiber Bragg Gratings for Wavelength-Division-Multiplexing and Optical Code-Division Multiple-Access Applications

Science.gov (United States)

Chen, Lawrence R.; Smith, Peter W. E.

The design and fabrication of chirped Moiré fiber Bragg gratings (CMGs) are presented, which can be used in either (1) transmission as passband filters for providing wavelength selectivity in wavelength-division-multiplexed (WDM) systems or (2) reflection as encoding/decoding elements to decompose short broadband pulses in both wavelength and time in order to implement an optical code-division multiple-access (OCDMA) system. In transmission, the fabricated CMGs have single or multiple flattened passbands ( 12 dB isolation and near constant in-band group delay. It is shown that these filters do not produce any measurable dispersion-induced power penalties when used to provide wavelength selectivity in 2.5 Gbit/s systems. It is also demonstrated how CMGs can be used in reflection to encode/decode short pulses from a wavelength-tunable mode-locked Er-doped fiber laser.

Multiple wavelength X-ray monochromators

International Nuclear Information System (INIS)

Steinmeyer, P.A.

1992-01-01

An improved apparatus and method is provided for separating input x-ray radiation containing first and second x-ray wavelengths into spatially separate first and second output radiation which contain the first and second x-ray wavelengths, respectively. The apparatus includes a crystalline diffractor which includes a first set of parallel crystal planes, where each of the planes is spaced a predetermined first distance from one another. The crystalline diffractor also includes a second set of parallel crystal planes inclined at an angle with respect to the first set of crystal planes where each of the planes of the second set of parallel crystal planes is spaced a predetermined second distance from one another. In one embodiment, the crystalline diffractor is comprised of a single crystal. In a second embodiment, the crystalline diffractor is comprised of a stack of two crystals. In a third embodiment, the crystalline diffractor includes a single crystal that is bent for focusing the separate first and second output x-ray radiation wavelengths into separate focal points. 3 figs

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

Science.gov (United States)

Nan, Liu; Guoping, Chen; Zhiliang, Hong

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

International Nuclear Information System (INIS)

Liu Nan; Chen Guoping; Hong Zhiliang

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm 2 and consumes 37 mW.

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Risti{c}, Branislav; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

CMOS Pixel Development for the ATLAS Experiment at HL-LHC

CERN Document Server

Gaudiello, Andrea; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

Aligning of single and multiple wavelength chromatographic

DEFF Research Database (Denmark)

Nielsen, Niels-Peter Vest; Carstensen, Jens Michael; Smedsgaard, Jørn

1998-01-01

optimised warping (COW) using two input parameters which can be estimated from the observed peak width. COW is demonstrated on constructed single trace chromatograms and on single and multiple wavelength chromatograms obtained from HPLC diode detection analyses of fungal extractsA copy of the C program......The use of chemometric data processing is becoming an important part of modern chromatography. Most chemometric analyses are performed on reduced data sets using areas of selected peaks detected in the chromatograms, which means a loss of data and introduces the problem of extracting peak data from...... to utilise the entire data matrix or rely on peak detection, thus having the same limitations as the commonly used chemometric procedures. The method presented uses the entire chromatographic data matrices and does not require any preprocessing e.g., peak detection. It relies on piecewise linear correlation...

Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

International Nuclear Information System (INIS)

Holland, S.

1991-11-01

A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers are used in the process. The NMOS device is formed in a retrograde well while the PMOS device is fabricated directly in the high-resistivity silicon. Isolation characteristics are similar to a standard foundary CMOS process. Circuit performance using 3 μm design rules has been evaluated. The measured propagation delay and power-delay product for a 51-stage ring oscillator was 1.5 ns and 43 fJ, respectively. Measurements on a simple cascode amplifier results in a gain-bandwidth product of 200 MHz at a bias current of 15 μA. The input-referred noise of the cascode amplifier is 20 nV/√Hz at 1 MHz

Technology for the compatible integration of silicon detectors with readout electronics

International Nuclear Information System (INIS)

Zimmer, G.

1984-01-01

Compatible integration of detectors and readout electronics on the same silicon substrate is of growing interest. As the methods of microelectronics technology have already been adapted for detector fabrication, a common technology basis for detectors and readout electronics is available. CMOS technology exhibits most attractive features for the compatible realization of readout electronics when advanced LSI processing steps are combined with detector requirements. The essential requirements for compatible integration are the availability of high resistivity (100)-oriented single crystalline silicon substrate, the formation of suitably doped areas for MOS circuits and the isolation of the low voltage circuit from the detector operated at much higher supply voltage. Junction isolation as a first approach based on present production technology and dielectric isolation based on an advanced SOI-LSI technology are discussed as the most promising solutions for present and future applications, respectively. (orig.)

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

Science.gov (United States)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Directory of Open Access Journals (Sweden)

Mauro Olivieri

2013-01-01

Full Text Available Synchronous early-completion-prediction adders (ECPAs are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works.

Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

International Nuclear Information System (INIS)

Liu, Yu-Chia; Tsai, Ming-Han; Fang, Weileun; Tang, Tsung-Lin

2011-01-01

This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

Applications of Si/SiGe heterostructures to CMOS devices

International Nuclear Information System (INIS)

Sidek, R.M.

1999-03-01

For more than two decades, advances in MOSFETs used in CMOS VLSI applications have been made through scaling to ever smaller dimensions for higher packing density, faster circuit speed and lower power dissipation. As scaling now approaches nanometer regime, the challenge for further scaling becomes greater in terms of technology as well as device reliability. This work presents an alternative approach whereby non-selectively grown Si/SiGe heterostructure system is used to improve device performance or to relax the technological challenge. SiGe is considered to be of great potential because of its promising properties and its compatibility with Si, the present mainstream material in microelectronics. The advantages of introducing strained SiGe in CMOS technology are examined through two types of device structure. A novel structure has been fabricated in which strained SiGe is incorporated in the source/drain of P-MOSFETs. Several advantages of the Si/SiGe source/drain P-MOSFETs over Si devices are experimentally, demonstrated for the first time. These include reduction in off-state leakage and punchthrough susceptibility, degradation of parasitic bipolar transistor (PBT) action, suppression of CMOS latchup and suppression of PBT-induced breakdown. The improvements due to the Si/SiGe heterojunction are supported by numerical simulations. The second device structure makes use of Si/SiGe heterostructure as a buried channel to enhance the hole mobility of P-MOSFETs. The increase in the hole mobility will benefit the circuit speed and device packing density. Novel fabrication processes have been developed to integrate non-selective Si/SiGe MBE layers into self-aligned PMOS and CMOS processes based on Si substrate. Low temperature processes have been employed including the use of low-pressure chemical vapor deposition oxide and plasma anodic oxide. Low field mobilities, μ 0 are extracted from the transfer characteristics, Id-Vg of SiGe channel P-MOSFETs with various Ge

Optical readout of a triple-GEM detector by means of a CMOS sensor

Energy Technology Data Exchange (ETDEWEB)

Marafini, M. [INFN Sezione di Roma (Italy); Museo Storico della Fisica e Centro Studi e Ricerche “E. Fermi”, Roma (Italy); Patera, V. [INFN Sezione di Roma (Italy); Museo Storico della Fisica e Centro Studi e Ricerche “E. Fermi”, Roma (Italy); Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Pinci, D., E-mail: davide.pinci@roma1.infn.it [INFN Sezione di Roma (Italy); Sarti, A. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Dipartimento di Scienze di Base e Applicate per Ingegneria, Sapienza Università di Roma (Italy); Sciubba, A. [INFN Sezione di Roma (Italy); Museo Storico della Fisica e Centro Studi e Ricerche “E. Fermi”, Roma (Italy); Dipartimento di Scienze di Base e Applicate per Ingegneria, Sapienza Università di Roma (Italy); Spiriti, E. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy)

2016-07-11

In last years, the development of optical sensors has produced objects able to provide very interesting performance. Large granularity is offered along with a very high sensitivity. CMOS sensors with millions of pixels able to detect as few as two or three photons per pixel are commercially available and can be used to read-out the optical signals provided by tracking particle detectors. In this work the results obtained by optically reading-out a triple-GEM detector by a commercial CMOS sensor will be presented. A standard detector was assembled with a transparent window below the third GEM allowing the light to get out. The detector is supplied with an Ar/CF{sub 4} based gas mixture producing 650 nm wavelength photons matching the maximum quantum efficiency of the sensor.

Which Photodiode to Use: A Comparison of CMOS-Compatible Structures.

Science.gov (United States)

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2009-07-01

While great advances have been made in optimizing fabrication process technologies for solid state image sensors, the need remains to be able to fabricate high quality photosensors in standard CMOS processes. The quality metrics depend on both the pixel architecture and the photosensitive structure. This paper presents a comparison of three photodiode structures in terms of spectral sensitivity, noise and dark current. The three structures are n(+)/p-sub, n-well/p-sub and p(+)/n-well/p-sub. All structures were fabricated in a 0.5 mum 3-metal, 2-poly, n-well process and shared the same pixel and readout architectures. Two pixel structures were fabricated-the standard three transistor active pixel sensor, where the output depends on the photodiode capacitance, and one incorporating an in-pixel capacitive transimpedance amplifier where the output is dependent only on a designed feedback capacitor. The n-well/p-sub diode performed best in terms of sensitivity (an improvement of 3.5 x and 1.6 x over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) and signal-to-noise ratio (1.5 x and 1.2 x improvement over the n(+)/p-sub and p(+)/n-well/p-sub diodes, respectively) while the p(+)/n-well/p-sub diode had the minimum (33% compared to other two structures) dark current for a given sensitivity.

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.

Science.gov (United States)

Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

2012-07-01

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.

Threshold-Based Multiple Optical Signal Selection Scheme for Free-Space Optical Wavelength Division Multiplexing Systems

KAUST Repository

Nam, Sung Sik; Alouini, Mohamed-Slim; Zhang, Lin; Ko, Young-Chai

2017-01-01

We propose a threshold-based multiple optical signal selection scheme (TMOS) for free-space optical wavelength division multiplexing systems. With this scheme, we can obtain higher spectral efficiency while reducing the possible complexity

CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

Science.gov (United States)

Rimoldi, M.

2017-12-01

The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detectors based on CMOS technology. Such detectors can provide charge collection, analog amplification and digital processing in the same silicon wafer. The radiation hardness is improved thanks to multiple nested wells which give the embedded CMOS electronics sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC . A number of alternative solutions have been explored and characterised. In this document, test results of the sensors fabricated in different CMOS processes are reported.

BioCMOS Interfaces and Co-Design

CERN Document Server

Carrara, Sandro

2013-01-01

The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

Analysis of 3D stacked fully functional CMOS Active Pixel Sensor detectors

International Nuclear Information System (INIS)

Passeri, D; Servoli, L; Meroli, S

2009-01-01

The IC technology trend is to move from 3D flexible configurations (package on package, stacked dies) to real 3D ICs. This is mainly due to i) the increased electrical performances and ii) the cost of 3D integration which may be cheaper than to keep shrinking 2D circuits. Perspective advantages for particle tracking and vertex detectors applications in High Energy Physics can be envisaged: in this work, we will focus on the capabilities of the state-of-the-art vertical scale integration technologies, allowing for the fabrication of very compact, fully functional, multiple layers CMOS Active Pixel Sensor (APS) detectors. The main idea is to exploit the features of the 3D technologies for the fabrication of a ''stack'' of very thin and precisely aligned CMOS APS layers, leading to a single, integrated, multi-layers pixel sensor. The adoption of multiple-layers single detectors can dramatically reduce the mass of conventional, separated detectors (thus reducing multiple scattering issues), at the same time allowing for very precise measurements of particle trajectory and momentum. As a proof of concept, an extensive device and circuit simulation activity has been carried out, aiming at evaluate the suitability of such a kind of CMOS active pixel layers for particle tracking purposes.

Pulse patterning effect in optical pulse division multiplexing for flexible single wavelength multiple access optical network

Science.gov (United States)

Jung, Sun-Young; Kim, Chang-Hun; Han, Sang-Kook

2018-05-01

A demand for high spectral efficiency requires multiple access within a single wavelength, but the uplink signals are significantly degraded because of optical beat interference (OBI) in intensity modulation/direct detection system. An optical pulse division multiplexing (OPDM) technique was proposed that could effectively reduce the OBI via a simple method as long as near-orthogonality is satisfied, but the condition was strict, and thus, the number of multiplexing units was very limited. We propose pulse pattern enhanced OPDM (e-OPDM) to reduce the OBI and improve the flexibility in multiple access within a single wavelength. The performance of the e-OPDM and patterning effect are experimentally verified after 23-km single mode fiber transmission. By employing pulse patterning in OPDM, the tight requirement was relaxed by extending the optical delay dynamic range. This could support more number of access with reduced OBI, which could eventually enhance a multiple access function.

Quadratic Poisson brackets compatible with an algebra structure

OpenAIRE

Balinsky, A. A.; Burman, Yu.

1994-01-01

Quadratic Poisson brackets on a vector space equipped with a bilinear multiplication are studied. A notion of a bracket compatible with the multiplication is introduced and an effective criterion of such compatibility is given. Among compatible brackets, a subclass of coboundary brackets is described, and such brackets are enumerated in a number of examples.

Hybrid CMOS/Molecular Integrated Circuits

Science.gov (United States)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

Science.gov (United States)

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

Planar pixel sensors in commercial CMOS technologies

Energy Technology Data Exchange (ETDEWEB)

Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

2015-07-01

For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

A CMOS-compatible large-scale monolithic integration of heterogeneous multi-sensors on flexible silicon for IoT applications

KAUST Repository

Nassar, Joanna M.

2017-02-07

We report CMOS technology enabled fabrication and system level integration of flexible bulk silicon (100) based multi-sensors platform which can simultaneously sense pressure, temperature, strain and humidity under various physical deformations. We also show an advanced wearable version for body vital monitoring which can enable advanced healthcare for IoT applications.

A CMOS-compatible large-scale monolithic integration of heterogeneous multi-sensors on flexible silicon for IoT applications

KAUST Repository

Nassar, Joanna M.; Sevilla, Galo T.; Velling, Seneca J.; Cordero, Marlon D.; Hussain, Muhammad Mustafa

2017-01-01

We report CMOS technology enabled fabrication and system level integration of flexible bulk silicon (100) based multi-sensors platform which can simultaneously sense pressure, temperature, strain and humidity under various physical deformations. We also show an advanced wearable version for body vital monitoring which can enable advanced healthcare for IoT applications.

CMOS MEMS Fabrication Technologies and Devices

Directory of Open Access Journals (Sweden)

Hongwei Qu

2016-01-01

Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

Visible Wavelength Color Filters Using Dielectric Subwavelength Gratings for Backside-Illuminated CMOS Image Sensor Technologies.

Science.gov (United States)

Horie, Yu; Han, Seunghoon; Lee, Jeong-Yub; Kim, Jaekwan; Kim, Yongsung; Arbabi, Amir; Shin, Changgyun; Shi, Lilong; Arbabi, Ehsan; Kamali, Seyedeh Mahsa; Lee, Hong-Seok; Hwang, Sungwoo; Faraon, Andrei

2017-05-10

We report transmissive color filters based on subwavelength dielectric gratings that can replace conventional dye-based color filters used in backside-illuminated CMOS image sensor (BSI CIS) technologies. The filters are patterned in an 80 nm-thick poly silicon film on a 115 nm-thick SiO 2 spacer layer. They are optimized for operating at the primary RGB colors, exhibit peak transmittance of 60-80%, and have an almost insensitive response over a ± 20° angular range. This technology enables shrinking of the pixel sizes down to near a micrometer.

Optical Code-Division Multiple-Access and Wavelength Division Multiplexing: Hybrid Scheme Review

OpenAIRE

P. Susthitha Menon; Sahbudin Shaari; Isaac A.M. Ashour; Hesham A. Bakarman

2012-01-01

Problem statement: Hybrid Optical Code-Division Multiple-Access (OCDMA) and Wavelength-Division Multiplexing (WDM) have flourished as successful schemes for expanding the transmission capacity as well as enhancing the security for OCDMA. However, a comprehensive review related to this hybrid system are lacking currently. Approach: The purpose of this paper is to review the literature on OCDMA-WDM overlay systems, including our hybrid approach of one-dimensional coding of SAC OCDMA with WDM si...

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

Directory of Open Access Journals (Sweden)

Preethi Padmanabhan

2018-02-01

Full Text Available Gallium nitride (GaN and its alloys are becoming preferred materials for ultraviolet (UV detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs, implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

Science.gov (United States)

Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

2018-02-03

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

A 12 GHz wavelength spacing multi-wavelength laser source for wireless communication systems

Science.gov (United States)

Peng, P. C.; Shiu, R. K.; Bitew, M. A.; Chang, T. L.; Lai, C. H.; Junior, J. I.

2017-08-01

This paper presents a multi-wavelength laser source with 12 GHz wavelength spacing based on a single distributed feedback laser. A light wave generated from the distributed feedback laser is fed into a frequency shifter loop consisting of 50:50 coupler, dual-parallel Mach-Zehnder modulator, optical amplifier, optical filter, and polarization controller. The frequency of the input wavelength is shifted and then re-injected into the frequency shifter loop. By re-injecting the shifted wavelengths multiple times, we have generated 84 optical carriers with 12 GHz wavelength spacing and stable output power. For each channel, two wavelengths are modulated by a wireless data using the phase modulator and transmitted through a 25 km single mode fiber. In contrast to previously developed schemes, the proposed laser source does not incur DC bias drift problem. Moreover, it is a good candidate for radio-over-fiber systems to support multiple users using a single distributed feedback laser.

Development of a thinned back-illuminated CMOS active pixel sensor for extreme ultraviolet spectroscopy and imaging in space science

International Nuclear Information System (INIS)

Waltham, N.R.; Prydderch, M.; Mapson-Menard, H.; Pool, P.; Harris, A.

2007-01-01

We describe our programme to develop a large-format, science-grade, monolithic CMOS active pixel sensor for future space science missions, and in particular an extreme ultraviolet (EUV) spectrograph for solar physics studies on ESA's Solar Orbiter. Our route to EUV sensitivity relies on adapting the back-thinning and rear-illumination techniques first developed for CCD sensors. Our first large-format sensor consists of 4kx3k 5 μm pixels fabricated on a 0.25 μm CMOS imager process. Wafer samples of these sensors have been thinned by e2v technologies with the aim of obtaining good sensitivity at EUV wavelengths. We present results from both front- and back-illuminated versions of this sensor. We also present our plans to develop a new sensor of 2kx2k 10 μm pixels, which will be fabricated on a 0.35 μm CMOS process. In progress towards this goal, we have designed a test-structure consisting of six arrays of 512x512 10 μm pixels. Each of the arrays has been given a different pixel design to allow verification of our models, and our progress towards optimizing a design for minimal system readout noise and maximum dynamic range. These sensors will also be back-thinned for characterization at EUV wavelengths

A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

Science.gov (United States)

Lauxtermann, Stefan; Fisher, John; McDougal, Michael

2014-06-01

In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

'The More We Stand For - The More We Fight For': Compatibility and Legitimacy in the Effects of Multiple Social Identities.

Science.gov (United States)

Chayinska, Maria; Minescu, Anca; McGarty, Craig

2017-01-01

This paper explores the expression of multiple social identities through coordinated collective action. We propose that perceived compatibility between potentially contrasting identities and perceived legitimacy of protest serve as catalysts for collective action. The present paper maps the context of the "Euromaidan" anti-regime protests in Ukraine and reports data ( N = 996) collected through an online survey following legislation to ban protests (March-May, 2014). We measured participants' identification with three different groups (the Ukrainian nation, the online protest community, and the street movement), perception of compatibility between online protest and the street movement, perception of the legitimacy of protest, and intentions to take persuasive and confrontational collective action. We found evidence that the more social groups people "stood for," the more they "fought" for their cause and that identifications predicted both forms of collective action to the degree that people saw the protest and the online movement as compatible with each other and believed protest to be legitimate. Collective action can be interpreted as the congruent expression of multiple identities that are rendered ideologically compatible both in online settings and on the street.

Wavelength-encoding/temporal-spreading optical code division multiple-access system with in-fiber chirped moiré gratings.

Science.gov (United States)

Chen, L R; Smith, P W; de Sterke, C M

1999-07-20

We propose an optical code division multiple-access (OCDMA) system that uses in-fiber chirped moiré gratings (CMG's) for encoding and decoding of broadband pulses. In reflection the wavelength-selective and dispersive nature of CMG's can be used to implement wavelength-encoding/temporal-spreading OCDMA. We give examples of codes designed around the constraints imposed by the encoding devices and present numerical simulations that demonstrate the proposed concept.

Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

Directory of Open Access Journals (Sweden)

Shoji Kawahito

2016-11-01

Full Text Available This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs. This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC. The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median: 0.29 e−rms when compared with the CMS gain of two (2.4 e−rms, or 16 (1.1 e−rms.

Experimental demonstration of titanium nitride plasmonic interconnects

DEFF Research Database (Denmark)

Kinsey, N.; Ferrera, M.; Naik, G. V.

2014-01-01

An insulator-metal-insulator plasmonic interconnect using TiN, a CMOS-compatible material, is proposed and investigated experimentally at the telecommunication wavelength of 1.55 mu m. The TiN waveguide was shown to obtain propagation losses less than 0.8 dB/mm with a mode size of 9.8 mu m...

An integrated CMOS high data rate transceiver for video applications

International Nuclear Information System (INIS)

Liang Yaping; Sun Lingling; Che Dazhi; Liang Cheng

2012-01-01

This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at −3 dBm output power. (semiconductor integrated circuits)

Integrated Amorphous Silicon p-i-n Temperature Sensor for CMOS Photonics

Directory of Open Access Journals (Sweden)

Sandro Rao

2016-01-01

Full Text Available Hydrogenated amorphous silicon (a-Si:H shows interesting optoelectronic and technological properties that make it suitable for the fabrication of passive and active micro-photonic devices, compatible moreover with standard microelectronic devices on a microchip. A temperature sensor based on a hydrogenated amorphous silicon p-i-n diode integrated in an optical waveguide for silicon photonics applications is presented here. The linear dependence of the voltage drop across the forward-biased diode on temperature, in a range from 30 °C up to 170 °C, has been used for thermal sensing. A high sensitivity of 11.9 mV/°C in the bias current range of 34–40 nA has been measured. The proposed device is particularly suitable for the continuous temperature monitoring of CMOS-compatible photonic integrated circuits, where the behavior of the on-chip active and passive devices are strongly dependent on their operating temperature.

Rutin increases critical wavelength of systems containing a single UV filter and with good skin compatibility.

Science.gov (United States)

Peres, D A; de Oliveira, C A; da Costa, M S; Tokunaga, V K; Mota, J P; Rosado, C; Consiglieri, V O; Kaneko, T M; Velasco, M V R; Baby, A R

2016-08-01

Ultraviolet (UV) radiation is responsible for sunburns, skin cancer, photoaging, and the production of reactive oxygen species (ROS). The awareness on preventing these deleterious effects made the use of anti-UVB formulations an important part of population habits; however, despite the availability of several antioxidants capable of ROS scavenging, the pharmaceutical market lacks products associating UV filters with natural compounds of proven efficacy. Here, we investigated the effect of rutin, a flavonoid with antioxidant activity, associated with UVB filters in dermocosmetic preparations. Formulations were assessed through its antioxidant activity, in vitro photoprotective effectiveness, photostability, and in vivo skin tolerance (hydration, transepidermal water loss, and erythema). Samples containing rutin were compatible with the human skin and presented a pronounced antioxidant potential, with scavenging activity values 75% higher than the ones containing only UVB filters. Although rutin could not prevent the sunscreens photodegradation post-irradiation, the bioactive compound significantly increased the formulations critical wavelengths, showing a photoprotective gain, especially in the UVA range. In conclusion, the absorption in the UVA range, coupled with ROS scavenging potential, proved the positive effect of rutin applied to anti-UVB formulations, making this bioactive compound a promising candidate for photoprotection improvement. © 2015 John Wiley & Sons A/S. Published by John Wiley & Sons Ltd.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

Science.gov (United States)

Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

2018-01-01

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

Relative efficiency of joint-model and full-conditional-specification multiple imputation when conditional models are compatible: The general location model.

Science.gov (United States)

Seaman, Shaun R; Hughes, Rachael A

2018-06-01

Estimating the parameters of a regression model of interest is complicated by missing data on the variables in that model. Multiple imputation is commonly used to handle these missing data. Joint model multiple imputation and full-conditional specification multiple imputation are known to yield imputed data with the same asymptotic distribution when the conditional models of full-conditional specification are compatible with that joint model. We show that this asymptotic equivalence of imputation distributions does not imply that joint model multiple imputation and full-conditional specification multiple imputation will also yield asymptotically equally efficient inference about the parameters of the model of interest, nor that they will be equally robust to misspecification of the joint model. When the conditional models used by full-conditional specification multiple imputation are linear, logistic and multinomial regressions, these are compatible with a restricted general location joint model. We show that multiple imputation using the restricted general location joint model can be substantially more asymptotically efficient than full-conditional specification multiple imputation, but this typically requires very strong associations between variables. When associations are weaker, the efficiency gain is small. Moreover, full-conditional specification multiple imputation is shown to be potentially much more robust than joint model multiple imputation using the restricted general location model to mispecification of that model when there is substantial missingness in the outcome variable.

Microelectronic test structures for CMOS technology

CERN Document Server

Ketchen, Mark B

2011-01-01

Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

CERN Document Server

Rimoldi, Marco; The ATLAS collaboration

2017-01-01

The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

CERN Document Server

Wang, T.

2017-01-01

The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

Enhancing CIDOC-CRM and compatible models with the concept of multiple interpretation

Science.gov (United States)

Van Ruymbeke, M.; Hallot, P.; Billen, R.

2017-08-01

Modelling cultural heritage and archaeological objects is used as much for management as for research purposes. To ensure the sustainable benefit of digital data, models benefit from taking the data specificities of historical and archaeological domains into account. Starting from a conceptual model tailored to storing these specificities, we present, in this paper, an extended mapping to CIDOC-CRM and its compatible models. Offering an ideal framework to structure and highlight the best modelling practices, these ontologies are essentially dedicated to storing semantic data which provides information about cultural heritage objects. Based on this standard, our proposal focuses on multiple interpretation and sequential reality.

Inheritance of graft compatibility in Douglas fir.

Science.gov (United States)

D.L. Copes

1973-01-01

Graft compatibility of genetically related and unrelated rootstock-scion combinations was compared. Scion clones were 75% compatible when grafted on half-related rootstocks but only 56% compatible when grafted on unrelated rootstocks. Most variance associated with graft incompatibility in Douglas-fir appears to be caused by multiple genes.

3D monolithically stacked CMOS active pixel sensor detectors for particle tracking applications

International Nuclear Information System (INIS)

Passeri, D; Placidi, P; Servoli, L; Meroli, S; Magalotti, D; Marras, A

2012-01-01

In this work we propose an innovative approach to particle tracking based on CMOS Active Pixel Sensors layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle impact point and direction) within a single detector. This will results in a very low material detector, thus dramatically reducing multiple scattering issues. To this purpose, we rely on the capabilities of the CMOS vertical scale integration (3D IC) technology. A first chip prototype has been fabricated within a multi-project run using a 130 nm CMOS Chartered/Tezzaron technology, featuring two layers bonded face-to-face. Tests have been carried out on full 3D structures, providing the functionalities of both tiers. To this purpose, laser scans have been carried out using highly focussed spot size obtaining coincidence responses of the two layers. Tests have been made as well with X-ray sources in order to calibrate the response of the sensor. Encouraging results have been found, fostering the suitability of both the adopted 3D-IC vertical scale fabrication technology and the proposed approach for particle tracking applications.

The test beamline of the European Spallation Source - Instrumentation development and wavelength frame multiplication

DEFF Research Database (Denmark)

Woracek, R.; Hofmann, T.; Bulat, M.

2016-01-01

which, in contrast, are all providing short neutron pulses. In order to enable the development of methods and technology adapted to this novel type of source well in advance of the first instruments being constructed at ESS, a test beamline (TBL) was designed and built at the BER II research reactor...... wavelength band between 1.6 A and 10 A by a dedicated wavelength frame multiplication (WFM) chopper system. WFM is proposed for several ESS instruments to allow for flexible time-of-flight resolution. Hence, ESS will benefit from the TBL which offers unique possibilities for testing methods and components....... This article describes the main capabilities of the instrument, its performance as experimentally verified during the commissioning, and its relevance to currently starting ESS instrumentation projects....

Large area CMOS image sensors

International Nuclear Information System (INIS)

Turchetta, R; Guerrini, N; Sedgwick, I

2011-01-01

CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Science.gov (United States)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Study of laser-induced damage on the exit surface of silica components in the nanosecond regime in a multiple wavelengths configuration

International Nuclear Information System (INIS)

Chambonneau, Maxime

2014-01-01

In this thesis, laser-induced damage phenomenon on the surface of fused silica components is investigated in the nanosecond regime. This phenomenon consists in an irreversible modification of the material. In the nanosecond regime, laser damage is tightly correlated to the presence of non-detectable precursor defects which are a consequence of the synthesis and the polishing of the components. In this thesis, we investigate laser damage in a multiple wavelengths configuration. In order to better understand this phenomenon in these conditions of irradiation, three studies are conducted. The first one focuses on damage initiation. The results obtained in the single wavelength configurations highlight a coupling in the multiple wavelengths one. A comparison between the experiments and a model developed during this thesis enables us to improve the knowledge of the fundamental processes involved during this damage phase. Then, we show that post mortem characterizations of damage morphology coupled to an accurate metrology allow us to understand both the nature and also the chronology of the physical mechanisms involved during damage formation. The proposed theoretical scenario is confirmed through various experiments. Finally, we study damage growth in both the single and the multiple wavelengths cases. Once again, this last configuration highlights a coupling between the wavelengths. We show the necessity to account for the spatial characteristics of the laser beams during a growth session. (author) [fr

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

Science.gov (United States)

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2011-10-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

Sub-wavelength metamaterial cylinders with multiple dipole resonances

DEFF Research Database (Denmark)

Arslanagic, Samel; Breinbjerg, Olav

2009-01-01

It has been shown that the sub-wavelength resonances of the individual MTM cylinders also occur for electrically small configurations combining 2 or 4 cylinders. For the 2-and 4-cylinder configurations the overall size is 1/20 and 1/12.5 of the smallest wavelength, respectively. These MTM...... configuration thus offer the possibility for multi-resonant electrically small configurations....

CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

Directory of Open Access Journals (Sweden)

Pei-Zen Chang

2012-12-01

Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

Optoelectronic circuits in nanometer CMOS technology

CERN Document Server

Atef, Mohamed

2016-01-01

This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

CMOS test and evaluation a physical perspective

CERN Document Server

Bhushan, Manjul

2015-01-01

This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

‘The More We Stand For – The More We Fight For’: Compatibility and Legitimacy in the Effects of Multiple Social Identities

Science.gov (United States)

Chayinska, Maria; Minescu, Anca; McGarty, Craig

2017-01-01

This paper explores the expression of multiple social identities through coordinated collective action. We propose that perceived compatibility between potentially contrasting identities and perceived legitimacy of protest serve as catalysts for collective action. The present paper maps the context of the “Euromaidan” anti-regime protests in Ukraine and reports data (N = 996) collected through an online survey following legislation to ban protests (March–May, 2014). We measured participants’ identification with three different groups (the Ukrainian nation, the online protest community, and the street movement), perception of compatibility between online protest and the street movement, perception of the legitimacy of protest, and intentions to take persuasive and confrontational collective action. We found evidence that the more social groups people “stood for,” the more they “fought” for their cause and that identifications predicted both forms of collective action to the degree that people saw the protest and the online movement as compatible with each other and believed protest to be legitimate. Collective action can be interpreted as the congruent expression of multiple identities that are rendered ideologically compatible both in online settings and on the street. PMID:28491046

‘The More We Stand For – The More We Fight For’: Compatibility and Legitimacy in the Effects of Multiple Social Identities

Directory of Open Access Journals (Sweden)

Maria Chayinska

2017-04-01

Full Text Available This paper explores the expression of multiple social identities through coordinated collective action. We propose that perceived compatibility between potentially contrasting identities and perceived legitimacy of protest serve as catalysts for collective action. The present paper maps the context of the “Euromaidan” anti-regime protests in Ukraine and reports data (N = 996 collected through an online survey following legislation to ban protests (March–May, 2014. We measured participants’ identification with three different groups (the Ukrainian nation, the online protest community, and the street movement, perception of compatibility between online protest and the street movement, perception of the legitimacy of protest, and intentions to take persuasive and confrontational collective action. We found evidence that the more social groups people “stood for,” the more they “fought” for their cause and that identifications predicted both forms of collective action to the degree that people saw the protest and the online movement as compatible with each other and believed protest to be legitimate. Collective action can be interpreted as the congruent expression of multiple identities that are rendered ideologically compatible both in online settings and on the street.

Absorbed dose by a CMOS in radiotherapy

International Nuclear Information System (INIS)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

2011-10-01

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Hybrid CMOS-Graphene Sensor Array for Subsecond Dopamine Detection.

Science.gov (United States)

Nasri, Bayan; Wu, Ting; Alharbi, Abdullah; You, Kae-Dyi; Gupta, Mayank; Sebastian, Sunit P; Kiani, Roozbeh; Shahrjerdi, Davood

2017-12-01

We introduce a hybrid CMOS-graphene sensor array for subsecond measurement of dopamine via fast-scan cyclic voltammetry (FSCV). The prototype chip has four independent CMOS readout channels, fabricated in a 65-nm process. Using planar multilayer graphene as biologically compatible sensing material enables integration of miniaturized sensing electrodes directly above the readout channels. Taking advantage of the chemical specificity of FSCV, we introduce a region of interest technique, which subtracts a large portion of the background current using a programmable low-noise constant current at about the redox potentials. We demonstrate the utility of this feature for enhancing the sensitivity by measuring the sensor response to a known dopamine concentration in vitro at three different scan rates. This strategy further allows us to significantly reduce the dynamic range requirements of the analog-to-digital converter (ADC) without compromising the measurement accuracy. We show that an integrating dual-slope ADC is adequate for digitizing the background-subtracted current. The ADC operates at a sampling frequency of 5-10 kHz and has an effective resolution of about 60 pA, which corresponds to a theoretical dopamine detection limit of about 6 nM. Our hybrid sensing platform offers an effective solution for implementing next-generation FSCV devices that can enable precise recording of dopamine signaling in vivo on a large scale.

Neutron absorbed dose in a pacemaker CMOS

International Nuclear Information System (INIS)

Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

2012-01-01

The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

Neutron absorbed dose in a pacemaker CMOS

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2012-06-15

The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

Absorbed dose by a CMOS in radiotherapy

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2011-10-15

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Wideband CMOS receivers

CERN Document Server

Oliveira, Luis

2015-01-01

This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

SiGe BiCMOS manufacturing platform for mmWave applications

Science.gov (United States)

Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

2010-10-01

TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18μm and 0.13μm node CMOS processes along with high density 5.6fF/μm2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

Gun muzzle flash detection using a CMOS single photon avalanche diode

Science.gov (United States)

Merhav, Tomer; Savuskan, Vitali; Nemirovsky, Yael

2013-10-01

Si based sensors, in particular CMOS Image sensors, have revolutionized low cost imaging systems but to date have hardly been considered as possible candidates for gun muzzle flash detection, due to performance limitations, and low SNR in the visible spectrum. In this study, a CMOS Single Photon Avalanche Diode (SPAD) module is used to record and sample muzzle flash events in the visible spectrum, from representative weapons, common on the modern battlefield. SPADs possess two crucial properties for muzzle flash imaging - Namely, very high photon detection sensitivity, coupled with a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. This enables high sampling frequencies in the kilohertz range without SNR degradation, in contrast to regular CMOS image sensors. To date, the SPAD has not been utilized for flash detection in an uncontrolled environment, such as gun muzzle flash detection. Gun propellant manufacturers use alkali salts to suppress secondary flashes ignited during the muzzle flash event. Common alkali salts are compounds based on Potassium or Sodium, with spectral emission lines around 769nm and 589nm, respectively. A narrow band filter around the Potassium emission doublet is used in this study to favor the muzzle flash signal over solar radiation. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength under the specified imaging conditions. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics.

Post-CMOS FinFET integration of bismuth telluride and antimony telluride thin-film-based thermoelectric devices on SoI substrate

KAUST Repository

Aktakka, Ethem Erkan

2013-10-01

This letter reports, for the first time, heterogeneous integration of bismuth telluride (Bi2Te3) and antimony telluride (Sb 2Te3) thin-film-based thermoelectric ffect transistors) via a characterized TE-film coevaporationand shadow-mask patterning process using predeposition surface treatment methods for reduced TE-metal contact resistance. As a demonstration vehicle, a 2 × 2 mm2-sized integrated planar thermoelectric generator (TEG) is shown to harvest 0.7 μ W from 21-K temperature gradient. Transistor performance showed no significant change upon post-CMOS TEG integration, indicating, for the first time, the CMOS compatibility of the Bi2Te3 and Sb2Te3 thin films, which could be leveraged for realization of high-performance integrated micro-TE harvesters and coolers. © 2013 IEEE.

CMOS-compatible ruggedized high-temperature Lamb wave pressure sensor

International Nuclear Information System (INIS)

Kropelnicki, P; Mu, X J; Randles, A B; Cai, H; Ang, W C; Tsai, J M; Muckensturm, K-M; Vogt, H

2013-01-01

This paper describes the development of a novel ruggedized high-temperature pressure sensor operating in lateral field exited (LFE) Lamb wave mode. The comb-like structure electrodes on top of aluminum nitride (AlN) were used to generate the wave. A membrane was fabricated on SOI wafer with a 10 µm thick device layer. The sensor chip was mounted on a pressure test package and pressure was applied to the backside of the membrane, with a range of 20–100 psi. The temperature coefficient of frequency (TCF) was experimentally measured in the temperature range of −50 °C to 300 °C. By using the modified Butterworth–van Dyke model, coupling coefficients and quality factor were extracted. Temperature-dependent Young's modulus of composite structure was determined using resonance frequency and sensor interdigital transducer (IDT) wavelength which is mainly dominated by an AlN layer. Absolute sensor phase noise was measured at resonance to estimate the sensor pressure and temperature sensitivity. This paper demonstrates an AlN-based pressure sensor which can operate in harsh environment such as oil and gas exploration, automobile and aeronautic applications. (paper)

Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

Science.gov (United States)

Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

2017-06-01

Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

CERN Document Server

El-Khatib, Ziad; Mahmoud, Samy A

2012-01-01

This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

Experimental measurement of a high resolution CMOS detector coupled to CsI scintillators under X-ray radiation

International Nuclear Information System (INIS)

Michail, C.; Valais, I.; Seferis, I.; Kalyvas, N.; Fountos, G.; Kandarakis, I.

2015-01-01

The purpose of the present study was to assess the information content of structured CsI:Tl scintillating screens, specially treated to be compatible to a CMOS digital imaging optical sensor, in terms of the information capacity (IC), based on Shannon's mathematical communication theory. IC was assessed after the experimental determination of the Modulation Transfer Function (MTF) and the Normalized Noise Power Spectrum (NNPS) in the mammography and general radiography energy range. The CMOS sensor was coupled to three columnar CsI:Tl scintillator screens obtained from the same manufacturer with thicknesses of 130, 140 and 170 μm respectively, which were placed in direct contact with the optical sensor. The MTF was measured using the slanted-edge method while NNPS was determined by 2D Fourier transforming of uniformly exposed images. Both parameters were assessed by irradiation under the mammographic W/Rh (130, 140 and 170 μm CsI screens) and the RQA-5 (140 and 170 μm CsI screens) (IEC 62220-1) beam qualities. The detector response function was linear for the exposure range under investigation. At 70 kVp, under the RQA-5 conditions IC values were found to range between 2229 and 2340 bits/mm 2 . At 28 kVp the corresponding IC values were found to range between 2262 and 2968 bits/mm 2 . The information content of CsI:Tl scintillating screens in combination to the high resolution CMOS sensor, investigated in the present study, where found optimized for use in digital mammography imaging systems. - Highlights: • Three structured CsI:Tl screens (130,140 & 170 um) were coupled to a CMOS sensor. • MTF of the CsI/CMOS was higher than GOS:Tb and CsI based digital imaging systems. • IC of CsI:Tl/CMOS was found optimized for use in digital mammography systems

Design Considerations for CMOS Current Mode Operational Amplifiers and Current Conveyors

DEFF Research Database (Denmark)

Bruun, Erik

implementations of current mode opamps in CMOS technology are described. Also, current conveyor configurations with multiple outputs and flexible feedback connections from outputs to inputs are introduced. The dissertation includes several examples of circuit configurations ranging from simple class A and class......This dissertation is about CMOS current conveyors and current mode operational amplifiers (opamps). They are generic devices for continuous time signal processing in circuits and systems where signals are represented by currents.Substantial advancements are reported in the dissertation, both...... related to circuit implementations and system configurations and to an analysis of the fundamental limitations of the current mode technique.In the field of system configurations and circuit implementations different configurations of high gain current opamps are introduced and some of the first...

Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

KAUST Repository

Hussain, Aftab M.

2016-12-01

With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

A CMOS Morlet Wavelet Generator

Directory of Open Access Journals (Sweden)

A. I. Bautista-Castillo

2017-04-01

Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

CMOS image sensors: State-of-the-art

Science.gov (United States)

Theuwissen, Albert J. P.

2008-09-01

This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

All-CMOS night vision viewer with integrated microdisplay

Science.gov (United States)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology

Science.gov (United States)

Llobet, J.; Rius, G.; Chuquitarqui, A.; Borrisé, X.; Koops, R.; van Veghel, M.; Perez-Murano, F.

2018-04-01

We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

Beyond CMOS nanodevices 1

CERN Document Server

Balestra, Francis

2014-01-01

This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

Beyond CMOS nanodevices 2

CERN Document Server

Balestra, Francis

2014-01-01

This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

Gun muzzle flash detection using a single photon avalanche diode array in 0.18µm CMOS technology

Science.gov (United States)

Savuskan, Vitali; Jakobson, Claudio; Merhav, Tomer; Shoham, Avi; Brouk, Igor; Nemirovsky, Yael

2015-05-01

In this study, a CMOS Single Photon Avalanche Diode (SPAD) 2D array is used to record and sample muzzle flash events in the visible spectrum, from representative weapons. SPADs detect the emission peaks of alkali salts, potassium or sodium, with spectral emission lines around 769nm and 589nm, respectively. The alkali salts are included in the gunpowder to suppress secondary flashes ignited during the muzzle flash event. The SPADs possess two crucial properties for muzzle flash imaging: (i) very high photon detection sensitivity, (ii) a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. The sole noise sources are the ones prior to the readout circuitry (optical signal distribution, avalanche initiation distribution and nonphotonic generation). This enables high sampling frequencies in the kilohertz range without significant SNR degradation, in contrast to regular CMOS image sensors. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength, in the presence of sunlight. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics and signal processing, which will be reported. The frame rate of ~16 KHz was chosen as an optimum between SNR degradation and temporal profile recognition accuracy. In contrast to a single SPAD, the 2D array allows for multiple events to be processed simultaneously. Moreover, a significant field of view is covered, enabling comprehensive surveillance and imaging.

Variation-aware advanced CMOS devices and SRAM

CERN Document Server

Shin, Changhwan

2016-01-01

This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

Stochastic process variation in deep-submicron CMOS circuits and algorithms

CERN Document Server

Zjajo, Amir

2014-01-01

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and ne...

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

Science.gov (United States)

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

Design optimization of radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

1975-01-01

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

The Combined Quantification and Interpretation of Multiple Quantitative Magnetic Resonance Imaging Metrics Enlightens Longitudinal Changes Compatible with Brain Repair in Relapsing-Remitting Multiple Sclerosis Patients

Directory of Open Access Journals (Sweden)

Guillaume Bonnier

2017-09-01

Full Text Available ObjectiveQuantitative and semi-quantitative MRI (qMRI metrics provide complementary specificity and differential sensitivity to pathological brain changes compatible with brain inflammation, degeneration, and repair. Moreover, advanced magnetic resonance imaging (MRI metrics with overlapping elements amplify the true tissue-related information and limit measurement noise. In this work, we combined multiple advanced MRI parameters to assess focal and diffuse brain changes over 2 years in a group of early-stage relapsing-remitting MS patients.MethodsThirty relapsing-remitting MS patients with less than 5 years disease duration and nine healthy subjects underwent 3T MRI at baseline and after 2 years including T1, T2, T2* relaxometry, and magnetization transfer imaging. To assess longitudinal changes in normal-appearing (NA tissue and lesions, we used analyses of variance and Bonferroni correction for multiple comparisons. Multivariate linear regression was used to assess the correlation between clinical outcome and multiparametric MRI changes in lesions and NA tissue.ResultsIn patients, we measured a significant longitudinal decrease of mean T2 relaxation times in NA white matter (p = 0.005 and a decrease of T1 relaxation times in the pallidum (p < 0.05, which are compatible with edema reabsorption and/or iron deposition. No longitudinal changes in qMRI metrics were observed in controls. In MS lesions, we measured a decrease in T1 relaxation time (p-value < 2.2e−16 and a significant increase in MTR (p-value < 1e−6, suggesting repair mechanisms, such as remyelination, increased axonal density, and/or a gliosis. Last, the evolution of advanced MRI metrics—and not changes in lesions or brain volume—were correlated to motor and cognitive tests scores evolution (Adj-R2 > 0.4, p < 0.05. In summary, the combination of multiple advanced MRI provided evidence of changes compatible with focal and diffuse brain repair at

Mitigation of Beat Noise in Time Wavelength Optical Code-Division Multiple-Access Systems

Science.gov (United States)

Bazan, Taher M.; Harle, David; Andonovic, Ivan

2006-11-01

This paper presents an analysis of two methods for enhancing the performance of two-dimensional time wavelength Optical code-division multiple-access systems by mitigating the effects of beat noise. The first methodology makes use of an optical hard limiter (OHL) in the receiver prior to the optical correlator; a general formula for the error probability as a function of crosstalk level for systems adopting OHLs is given, and the implications of the OHL's nonideal transfer characteristics are then examined. The second approach adopts pulse position modulation, and system performance is estimated and compared to that associated with on off keying.

The Combined Quantification and Interpretation of Multiple Quantitative Magnetic Resonance Imaging Metrics Enlightens Longitudinal Changes Compatible with Brain Repair in Relapsing-Remitting Multiple Sclerosis Patients.

Science.gov (United States)

Bonnier, Guillaume; Maréchal, Benedicte; Fartaria, Mário João; Falkowskiy, Pavel; Marques, José P; Simioni, Samanta; Schluep, Myriam; Du Pasquier, Renaud; Thiran, Jean-Philippe; Krueger, Gunnar; Granziera, Cristina

2017-01-01

Quantitative and semi-quantitative MRI (qMRI) metrics provide complementary specificity and differential sensitivity to pathological brain changes compatible with brain inflammation, degeneration, and repair. Moreover, advanced magnetic resonance imaging (MRI) metrics with overlapping elements amplify the true tissue-related information and limit measurement noise. In this work, we combined multiple advanced MRI parameters to assess focal and diffuse brain changes over 2 years in a group of early-stage relapsing-remitting MS patients. Thirty relapsing-remitting MS patients with less than 5 years disease duration and nine healthy subjects underwent 3T MRI at baseline and after 2 years including T1, T2, T2* relaxometry, and magnetization transfer imaging. To assess longitudinal changes in normal-appearing (NA) tissue and lesions, we used analyses of variance and Bonferroni correction for multiple comparisons. Multivariate linear regression was used to assess the correlation between clinical outcome and multiparametric MRI changes in lesions and NA tissue. In patients, we measured a significant longitudinal decrease of mean T2 relaxation times in NA white matter ( p  = 0.005) and a decrease of T1 relaxation times in the pallidum ( p  decrease in T1 relaxation time ( p -value  0.4, p  < 0.05). In summary, the combination of multiple advanced MRI provided evidence of changes compatible with focal and diffuse brain repair at early MS stages as suggested by histopathological studies.

A Standard CMOS Humidity Sensor without Post-Processing

OpenAIRE

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023?10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

A 24 GHz CMOS oscillator transmitter with an inkjet printed on-chip antenna

KAUST Repository

Ghaffar, Farhan A.

2016-08-15

CMOS based RF circuits have demonstrated efficient performance over the decades. However, one bottle neck with this technology is its lossy nature for passive components such as inductors, antennas etc. Due to this drawback, passives are either implemented off chip or the designers work with the inefficient passives. This problem can be alleviated by using inkjet printing as a post process on CMOS chip. In this work, we demonstrate inkjet printing of a patterned polymer (SU8) layer on a 24 GHz oscillator chip to isolate the lossy Si substrate from the passives which are inkjet printed on top of the SU8 layer. As a proof of concept, a monopole antenna is printed on top of the SU8 layer integrating it with the oscillator through the exposed RF pads to realize an oscillator transmitter. The proposed hybrid fabrication technique can be extended to multiple dielectric and conductive printed layers to demonstrate complete RF systems on CMOS chips which are efficient, cost-effective and above all small in size. © 2016 IEEE.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

Directory of Open Access Journals (Sweden)

Mohammad Reza Shokrani

2014-01-01

Full Text Available This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

Science.gov (United States)

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Generation of synthetic time histories compatible with multiple-damping design response spectra

International Nuclear Information System (INIS)

Lilhanand, K.; Tseng, W.S.

1987-01-01

Seismic design of nuclear power plants as currently practiced requires time history analyses be performed to generate floor response spectra for seismic qualification of piping, equipment, and components. Since design response spectra are normally prescribed in the form of smooth spectra, the generation of synthetic time histories whose response spectra closely match the ''target'' design spectra of multiple damping values, is often required for the seismic time history analysis purpose. Various methods of generation of synthetic time histories compatible with target response spectra have been proposed in the literature. Since the mathematical problem of determining a time history from a given set of response spectral values is not unique, an exact solution is not possible, and all the proposed methods resort to some forms of approximate solutions. In this paper, a new iteration scheme, is described which effectively removes the difficulties encountered by the existing methods. This new iteration scheme can not only improve the accuracy of spectrum matching for a single-damping target spectrum, but also automate the spectrum matching for multiple-damping target spectra. The applicability and limitations as well as the method adopted to improve the numerical stability of this new iteration scheme are presented. The effectiveness of this new iteration scheme is illustrated by two example applications

Neutron absorbed dose in a pacemaker CMOS

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2011-11-15

The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

Frequency notching applicable to CMOS implementation of WLAN compatible IR-UWB pulse generators

DEFF Research Database (Denmark)

Shen, Ming; Mikkelsen, Jan H.; Jiang, Hao

2012-01-01

Due to overlapping frequency bands, IEEE 802.11a WLAN and Ultra Wide-Band systems potentially suffer from mutual interference problems. This paper proposes a method for inserting frequency notches into the IR-UWB power spectrum to ensure compatibility with WLAN systems. In contrast to conventional...... approaches where complicated waveform equations are used, the proposed method uses a dual-pulse frequency notching approach to achieve frequency suppression in selected bands. The proposed method offers a solution that is generically applicable to UWB pulse generators using different pulse waveforms...

Triangular metal wedges for subwavelength plasmon-polariton guiding at telecom wavelengths

DEFF Research Database (Denmark)

Boltasseva, Alexandra; Volkov, V.S.; Nielsen, Rasmus Bundgaard

2008-01-01

We report on subwavelength plasmon-polariton guiding by triangular metal wedges at telecom wavelengths. A high-quality fabrication procedure for making gold wedge waveguides, which is also mass- production compatible offering large-scale parallel fabrication of plasmonic components, is developed...

Nanometer CMOS ICs from basics to ASICs

CERN Document Server

J M Veendrick, Harry

2017-01-01

This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

A Multi-Wavelength Opto-Electronic Patch Sensor to Effectively Detect Physiological Changes against Human Skin Types.

Science.gov (United States)

Yan, Liangwen; Hu, Sijung; Alzahrani, Abdullah; Alharbi, Samah; Blanos, Panagiotis

2017-06-21

Different skin pigments among various ethnic group people have an impact on spectrometric illumination on skin surface. To effectively capture photoplethysmographic (PPG) signals, a multi-wavelength opto-electronic patch sensor (OEPS) together with a schematic architecture of electronics were developed to overcome the drawback of present PPG sensor. To perform a better in vivo physiological measurement against skin pigments, optimal illuminations in OEPS, whose wavelength is compatible with a specific skin type, were optimized to capture a reliable physiological sign of heart rate (HR). A protocol was designed to investigate an impact of five skin types in compliance with Von Luschan's chromatic scale. Thirty-three healthy male subjects between the ages of 18 and 41 were involved in the protocol implemented by means of the OEPS system. The results show that there is no significant difference ( p: 0.09, F = 3.0) in five group tests with the skin types across various activities throughout a series of consistent measurements. The outcome of the present study demonstrates that the OEPS, with its multi-wavelength illumination characteristics, could open a path in multiple applications of different ethnic groups with cost-effective health monitoring.

A Multi-Wavelength Opto-Electronic Patch Sensor to Effectively Detect Physiological Changes against Human Skin Types

Directory of Open Access Journals (Sweden)

Liangwen Yan

2017-06-01

Full Text Available Different skin pigments among various ethnic group people have an impact on spectrometric illumination on skin surface. To effectively capture photoplethysmographic (PPG signals, a multi-wavelength opto-electronic patch sensor (OEPS together with a schematic architecture of electronics were developed to overcome the drawback of present PPG sensor. To perform a better in vivo physiological measurement against skin pigments, optimal illuminations in OEPS, whose wavelength is compatible with a specific skin type, were optimized to capture a reliable physiological sign of heart rate (HR. A protocol was designed to investigate an impact of five skin types in compliance with Von Luschan’s chromatic scale. Thirty-three healthy male subjects between the ages of 18 and 41 were involved in the protocol implemented by means of the OEPS system. The results show that there is no significant difference (p: 0.09, F = 3.0 in five group tests with the skin types across various activities throughout a series of consistent measurements. The outcome of the present study demonstrates that the OEPS, with its multi-wavelength illumination characteristics, could open a path in multiple applications of different ethnic groups with cost-effective health monitoring.

CMOS-sensors for energy-resolved X-ray imaging

International Nuclear Information System (INIS)

Doering, D.; Amar-Youcef, S.; Deveaux, M.; Linnik, B.; Müntz, C.; Stroth, Joachim; Baudot, J.; Dulinski, W.; Kachel, M.

2016-01-01

Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ''color sensitive' X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors

32 x 16 CMOS smart pixel array for optical interconnects

Science.gov (United States)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

Characterizing Subpixel Spatial Resolution of a Hybrid CMOS Detector

Science.gov (United States)

Bray, Evan; Burrows, Dave; Chattopadhyay, Tanmoy; Falcone, Abraham; Hull, Samuel; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

The detection of X-rays is a unique process relative to other wavelengths, and allows for some novel features that increase the scientific yield of a single observation. Unlike lower photon energies, X-rays liberate a large number of electrons from the silicon absorber array of the detector. This number is usually on the order of several hundred to a thousand for moderate-energy X-rays. These electrons tend to diffuse outward into what is referred to as the charge cloud. This cloud can then be picked up by several pixels, forming a specific pattern based on the exact incident location. By conducting the first ever “mesh experiment" on a hybrid CMOS detector (HCD), we have experimentally determined the charge cloud shape and used it to characterize responsivity of the detector with subpixel spatial resolution.

High-speed nonvolatile CMOS/MNOS RAM

International Nuclear Information System (INIS)

Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

1979-01-01

A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

Noise analysis of a white-light supercontinuum light source for multiple wavelength confocal laser scanning fluorescence microscopy

Energy Technology Data Exchange (ETDEWEB)

McConnell, Gail [Centre for Biophotonics, Strathclyde Institute for Biomedical Sciences, University of Strathclyde, 27 Taylor Street, Glasgow, G4 0NR (United Kingdom)

2005-08-07

Intensity correlations of a Ti : sapphire, Kr/Ar and a white-light supercontinuum were performed to quantify the typical signal amplitude fluctuations and hence ascertain the comparative output stability of the white-light supercontinuum source for confocal laser scanning microscopy (CLSM). Intensity correlations across a two-pixel sample (n = 1000) of up to 98%, 95% and 94% were measured for the Ti : sapphire, Kr/Ar and white-light supercontinuum source, respectively. The white-light supercontinuum noise level is therefore acceptable for CLSM, with the added advantage of wider wavelength flexibility over traditional CLSM excitation sources. The relatively low-noise white-light supercontinuum was then used to perform multiple wavelength sequential CLSM of guinea pig detrusor to confirm the reliability of the system and to demonstrate system flexibility.

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

Science.gov (United States)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Multiple optical code-label processing using multi-wavelength frequency comb generator and multi-port optical spectrum synthesizer.

Science.gov (United States)

Moritsuka, Fumi; Wada, Naoya; Sakamoto, Takahide; Kawanishi, Tetsuya; Komai, Yuki; Anzai, Shimako; Izutsu, Masayuki; Kodate, Kashiko

2007-06-11

In optical packet switching (OPS) and optical code division multiple access (OCDMA) systems, label generation and processing are key technologies. Recently, several label processors have been proposed and demonstrated. However, in order to recognize N different labels, N separate devices are required. Here, we propose and experimentally demonstrate a large-scale, multiple optical code (OC)-label generation and processing technology based on multi-port, a fully tunable optical spectrum synthesizer (OSS) and a multi-wavelength electro-optic frequency comb generator. The OSS can generate 80 different OC-labels simultaneously and can perform 80-parallel matched filtering. We also demonstrated its application to OCDMA.

JPL CMOS Active Pixel Sensor Technology

Science.gov (United States)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

A Unified Framework of the Performance Evaluation of Optical Time-Wavelength Code-Division Multiple-Access Systems

Science.gov (United States)

Inaty, Elie

In this paper, we provide an analysis to the performance of optical time-wavelength code-division multiple-access (OTW-CDMA) network when the system is working above the nominal transmission rate limit imposed by the passive encoding-decoding operation. We address the problem of overlapping in such a system and how it can directly affect the bit error rate (BER). A unified mathematical framework is presented under the assumption of one coincidence sequences with non-repeating wavelengths. A closed form expression of the multiple access interference limited BER is provided as a function of different system parameters. Results show that the performance of OTW-CDMA system may be critically affected when working above the nominal limit; an event that may happen when the network operates at high transmission rate. In addition, the impact of the derived error probability on the performance of two newly proposed MAC protocols, the S-ALOHA and the R3T, is also investigated. It is shown that for low transmission rates, the S-ALOHA is better than the R3T; while the R3T is better at very high transmission rates. However, in general it is postulated that the R3T protocol suffers a higher delay mainly because of the presence of additional modes.

Pt silicide/poly-Si Schottky diodes as temperature sensors for bolometers

Energy Technology Data Exchange (ETDEWEB)

Yuryev, V. A., E-mail: vyuryev@kapella.gpi.ru; Chizh, K. V.; Chapnin, V. A.; Mironov, S. A.; Dubkov, V. P.; Uvarov, O. V.; Kalinushkin, V. P. [A. M. Prokhorov General Physics Institute of the Russian Academy of Sciences, 38 Vavilov Street, Moscow 119991 (Russian Federation); Senkov, V. M. [P. N. Lebedev Physical Institute of the Russian Academy of Sciences, 53 Leninskiy Avenue, Moscow 119991 (Russian Federation); Nalivaiko, O. Y. [JSC “Integral” – “Integral” Holding Management Company, 121A, Kazintsa I. P. Street, Minsk 220108 (Belarus); Novikau, A. G.; Gaiduk, P. I. [Belarusian State University, 4 Nezavisimosti Avenue, 220030 Minsk (Belarus)

2015-05-28

Platinum silicide Schottky diodes formed on films of polycrystalline Si doped by phosphorus are demonstrated to be efficient and manufacturable CMOS-compatible temperature sensors for microbolometer detectors of radiation. Thin-film platinum silicide/poly-Si diodes have been produced by a CMOS-compatible process on artificial Si{sub 3}N{sub 4}/SiO{sub 2}/Si(001) substrates simulating the bolometer cells. Layer structure and phase composition of the original Pt/poly-Si films and the Pt silicide/poly-Si films synthesized by a low-temperature process have been studied by means of the scanning transmission electron microscopy; they have also been explored by means of the two-wavelength X-ray structural phase analysis and the X-ray photoelectron spectroscopy. Temperature coefficient of voltage for the forward current of a single diode is shown to reach the value of about −2%/ °C in the temperature interval from 25 to 50 °C.

Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors.

Science.gov (United States)

Malinowski, Pawel E; Georgitzikis, Epimitheas; Maes, Jorick; Vamvaka, Ioanna; Frazzica, Fortunato; Van Olmen, Jan; De Moor, Piet; Heremans, Paul; Hens, Zeger; Cheyns, David

2017-12-10

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III-V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10 -6 A/cm² at -2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Science.gov (United States)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Technology CAD for germanium CMOS circuit

Energy Technology Data Exchange (ETDEWEB)

Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

2006-12-15

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

Technology CAD for germanium CMOS circuit

International Nuclear Information System (INIS)

Saha, A.R.; Maiti, C.K.

2006-01-01

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

Resistor Extends Life Of Battery In Clocked CMOS Circuit

Science.gov (United States)

Wells, George H., Jr.

1991-01-01

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Carbon Nanotube Integration with a CMOS Process

Science.gov (United States)

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

The test beamline of the European Spallation Source – Instrumentation development and wavelength frame multiplication

International Nuclear Information System (INIS)

Woracek, R.; Hofmann, T.; Bulat, M.; Sales, M.; Habicht, K.; Andersen, K.; Strobl, M.

2016-01-01

The European Spallation Source (ESS), scheduled to start operation in 2020, is aiming to deliver the most intense neutron beams for experimental research of any facility worldwide. Its long pulse time structure implies significant differences for instrumentation compared to other spallation sources which, in contrast, are all providing short neutron pulses. In order to enable the development of methods and technology adapted to this novel type of source well in advance of the first instruments being constructed at ESS, a test beamline (TBL) was designed and built at the BER II research reactor at Helmholtz-Zentrum Berlin (HZB). Operating the TBL shall provide valuable experience in order to allow for a smooth start of operations at ESS. The beamline is capable of mimicking the ESS pulse structure by a double chopper system and provides variable wavelength resolution as low as 0.5% over a wide wavelength band between 1.6 Å and 10 Å by a dedicated wavelength frame multiplication (WFM) chopper system. WFM is proposed for several ESS instruments to allow for flexible time-of-flight resolution. Hence, ESS will benefit from the TBL which offers unique possibilities for testing methods and components. This article describes the main capabilities of the instrument, its performance as experimentally verified during the commissioning, and its relevance to currently starting ESS instrumentation projects.

The test beamline of the European Spallation Source – Instrumentation development and wavelength frame multiplication

Energy Technology Data Exchange (ETDEWEB)

Woracek, R., E-mail: robin.woracek@esss.se [European Spallation Source ESS ERIC, P.O. Box 176, SE-22100 Lund (Sweden); Hofmann, T.; Bulat, M. [Helmholtz-Zentrum Berlin für Materialien und Energie, Hahn-Meitner Platz 1, 14109 Berlin (Germany); Sales, M. [Technical University of Denmark, Fysikvej, 2800 Kgs. Lyngby (Denmark); Habicht, K. [Helmholtz-Zentrum Berlin für Materialien und Energie, Hahn-Meitner Platz 1, 14109 Berlin (Germany); Andersen, K. [European Spallation Source ESS ERIC, P.O. Box 176, SE-22100 Lund (Sweden); Strobl, M. [European Spallation Source ESS ERIC, P.O. Box 176, SE-22100 Lund (Sweden); Technical University of Denmark, Fysikvej, 2800 Kgs. Lyngby (Denmark)

2016-12-11

The European Spallation Source (ESS), scheduled to start operation in 2020, is aiming to deliver the most intense neutron beams for experimental research of any facility worldwide. Its long pulse time structure implies significant differences for instrumentation compared to other spallation sources which, in contrast, are all providing short neutron pulses. In order to enable the development of methods and technology adapted to this novel type of source well in advance of the first instruments being constructed at ESS, a test beamline (TBL) was designed and built at the BER II research reactor at Helmholtz-Zentrum Berlin (HZB). Operating the TBL shall provide valuable experience in order to allow for a smooth start of operations at ESS. The beamline is capable of mimicking the ESS pulse structure by a double chopper system and provides variable wavelength resolution as low as 0.5% over a wide wavelength band between 1.6 Å and 10 Å by a dedicated wavelength frame multiplication (WFM) chopper system. WFM is proposed for several ESS instruments to allow for flexible time-of-flight resolution. Hence, ESS will benefit from the TBL which offers unique possibilities for testing methods and components. This article describes the main capabilities of the instrument, its performance as experimentally verified during the commissioning, and its relevance to currently starting ESS instrumentation projects.

Depleted CMOS pixels for LHC proton–proton experiments

International Nuclear Information System (INIS)

Wermes, N.

2016-01-01

While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

Single photon detection and localization accuracy with an ebCMOS camera

Energy Technology Data Exchange (ETDEWEB)

Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

2015-07-01

The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

Investigation of black and brown carbon multiple-wavelength-dependent light absorption from biomass and fossil fuel combustion source emissions

Science.gov (United States)

Michael R. Olson; Mercedes Victoria Garcia; Michael A. Robinson; Paul Van Rooy; Mark A. Dietenberger; Michael Bergin; James Jay Schauer

2015-01-01

Quantification of the black carbon (BC) and brown carbon (BrC) components of source emissions is critical to understanding the impact combustion aerosols have on atmospheric light absorption. Multiple-wavelength absorption was measured from fuels including wood, agricultural biomass, coals, plant matter, and petroleum distillates in controlled combustion settings....

Broadband image sensor array based on graphene-CMOS integration

Science.gov (United States)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

CMOS Cell Sensors for Point-of-Care Diagnostics

Science.gov (United States)

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

Directory of Open Access Journals (Sweden)

Drago Strle

2015-07-01

Full Text Available This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC. The DSP is currently implemented on FPGA.

Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

Science.gov (United States)

Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

2015-07-22

This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

OMNI: An optoelectronic multichannel network interface based on hybrid CMOS-SEED technology

Science.gov (United States)

Pinkston, Timothy M.

1996-11-01

This paper presents a hybrid CMOS-SEED multiprocessor network interface smart pixel design that implements a reservation-based channel control protocol for collisionless concurrent access to multiple optical interprocessor communication channels. An asynchronous optical token is used as the arbitration mechanism for reservation control instead of slotted access. This work demonstrates that complex network protocol functions can be implemented using optoelectronic smart pixel technology.

CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

CERN Document Server

Ghafar-Zadeh, Ebrahim

2010-01-01

The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

CMOS optimization for radiation hardness

International Nuclear Information System (INIS)

Derbenwick, G.F.; Fossum, J.G.

1975-01-01

Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

Characterisation results of the CMOS VISNIR spectral band detector for the METimage instrument

Science.gov (United States)

Pratlong, Jérôme; Schmuelling, Frank; Benitez, Victor; Breart De Boisanger, Michel; Skegg, Michael; Simpson, Robert; Bowring, Steve; Krzizok, Natalie

2017-09-01

The METimage instrument is part of the EPS-SG (EUMETSAT Polar System Second Generation) program. It will be situated on the MetOp-SG platform which in operation has an objective of collecting data for meteorology and climate monitoring as well as their forecasting. Teledyne e2v has developed and characterised the CMOS VISNIR detector flight module part of the METimage instrument. This paper will focus on the silicon results obtained from the CMOS VISNIR detector flight model. The detector is a large multi-linear device composed of 7 spectral bands covering a wavelength range from 428 nm to 923 nm (some bands are placed twice and added together to enhance the signal-to-noise performance). This detector uses a 4T pixel, with a size of 250μm square, presenting challenges to achieve good charge transfer efficiency with high conversion factor and good linearity for signal levels up to 2M electrons and with high line rates. Low noise has been achieved using correlated double sampling to suppress the read-out noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. The photodiode occupies a significant fraction of the large pixel area. This makes it possible to meet the detection efficiency when front illuminated. A thicker than standard epitaxial silicon is used to improve NIR response. However, the dielectric stack on top of the sensor produces Fabry-Perot étalon effects, which are problematic for narrow band illumination as this causes the detection efficiency to vary significantly over a small wavelength range. In order to reduce this effect and to meet the specification, the silicon manufacturing process has been modified. The flight model will have black coating deposited between each spectral channel, onto the active silicon regions.

Design of multi-wavelength tunable filter based on Lithium Niobate

Science.gov (United States)

Zhang, Ailing; Yao, Yuan; Zhang, Yue; Song, Hongyun

2018-05-01

A multi-wavelength tunable filter is designed. It consists of multiple waveguides among multiple waveguide gratings. A pair of electrodes were placed on both sides of each waveguide. The tunable filter uses the electro-optic effect of Lithium Niobate to tune the phase caused by each waveguide. Consequently, the wavelength and wavelength spacing of the filter are tuned by changing external voltages added on the electrode pairs. The tunable property of the filter is analyzed by phase matching condition and transfer-matrix method. Numerical results show that not only multiple wavelengths with narrow bandwidth are tuned with nearly equal spacing by synchronously changing the voltages added on all electrode pairs, but also the number of wavelengths is determined by the number of phase shifts caused by electrode pairs. Furthermore, due to the electro-optic effect of Lithium Niobate, the tuning speed of the filter can reach the order of ns.

Multi-Wavelength Photomagnetic Imaging for Oral Cancer

Science.gov (United States)

Marks, Michael

In this study, a multi-wavelength Photomagnetic Imaging (PMI) system is developed and evaluated with experimental studies.. PMI measures temperature increases in samples illuminated by near-infrared light sources using magnetic resonance thermometry. A multiphysics solver combining light and heat transfer models the spatiotemporal distribution of the temperature change. The PMI system develop in this work uses three lasers of varying wavelength (785 nm, 808 nm, 860 nm) to heat the sample. By using multiple wavelengths, we enable the PMI system to quantify the relative concentrations of optical contrast in turbid media and monitor their distribution, at a higher resolution than conventional diffuse optical imaging. The data collected from agarose phantoms with multiple embedded contrast agents designed to simulate the optical properties of oxy- and deoxy-hemoglobin is presented. The reconstructed images demonstrate that multi-wavelength PMI can resolve this complex inclusion structure with high resolution and recover the concentration of each contrast agent with high quantitative accuracy. The modified multi-wavelength PMI system operates under the maximum skin exposure limits defined by the American National Standards Institute, to enable future clinical applications.

A Single-Transistor Active Pixel CMOS Image Sensor Architecture

International Nuclear Information System (INIS)

Zhang Guo-An; He Jin; Zhang Dong-Wei; Su Yan-Mei; Wang Cheng; Chen Qin; Liang Hai-Lang; Ye Yun

2012-01-01

A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology

Backside illuminated CMOS-TDI line scan sensor for space applications

Science.gov (United States)

Cohen, Omer; Ofer, Oren; Abramovich, Gil; Ben-Ari, Nimrod; Gershon, Gal; Brumer, Maya; Shay, Adi; Shamay, Yaron

2018-05-01

A multi-spectral backside illuminated Time Delayed Integration Radiation Hardened line scan sensor utilizing CMOS technology was designed for continuous scanning Low Earth Orbit small satellite applications. The sensor comprises a single silicon chip with 4 independent arrays of pixels where each array is arranged in 2600 columns with 64 TDI levels. A multispectral optical filter whose spectral responses per array are adjustable per system requirement is assembled at the package level. A custom 4T Pixel design provides the required readout speed, low-noise, very low dark current, and high conversion gains. A 2-phase internally controlled exposure mechanism improves the sensor's dynamic MTF. The sensor high level of integration includes on-chip 12 bit per pixel analog to digital converters, on-chip controller, and CMOS compatible voltage levels. Thus, the power consumption and the weight of the supporting electronics are reduced, and a simple electrical interface is provided. An adjustable gain provides a Full Well Capacity ranging from 150,000 electrons up to 500,000 electrons per column and an overall readout noise per column of less than 120 electrons. The imager supports line rates ranging from 50 to 10,000 lines/sec, with power consumption of less than 0.5W per array. Thus, the sensor is characterized by a high pixel rate, a high dynamic range and a very low power. To meet a Latch-up free requirement RadHard architecture and design rules were utilized. In this paper recent electrical and electro-optical measurements of the sensor's Flight Models will be presented for the first time.

Self-calibrated humidity sensor in CMOS without post-processing.

Science.gov (United States)

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Self-Calibrated Humidity Sensor in CMOS without Post-Processing

OpenAIRE

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Radiation-hardened bulk CMOS technology

International Nuclear Information System (INIS)

Dawes, W.R. Jr.; Habing, D.H.

1979-01-01

The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

CMOS/SOS processing

Science.gov (United States)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

Directory of Open Access Journals (Sweden)

Jose Luis Muñoz-Gamarra

2016-02-01

Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

Simulations of depleted CMOS sensors for high-radiation environments

CERN Document Server

Liu, J.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Degerli, Y.; Godiot-Basolo, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Moustakas, K.; Pangaud, P.; Rozanov, A.; Rymaszewski, P.; Schwemling, P.; Wang, M.; Wang, T.; Wermes, N.; Zhang, L.

2017-01-01

After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications

KAUST Repository

Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

2018-01-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications

KAUST Repository

Khan, Sherjeel M.

2018-02-27

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

Determination of the zero in the Two theta angle and the wavelength in the neutron diffractometer for the Cyber computer of the ININ and for the IBM compatible microcomputers

International Nuclear Information System (INIS)

Macias B, L.R.

1991-05-01

The objective of this work consists on determining the calibration in the angular parameters and the neutron wavelength used in the neutron diffractometer of the TRIGA Mark III reactor, through some readings in that a well-known sample is used by means of a Fortran computer program that is used in the CYBER computer of the ININ in Mexico, and/or in micro computers compatible with IBM. The program was also designed to determine the zero of the 2 θ angle of the goniometer of the diffractometer. The generated data were proven by means of well-known data of the Powder Diffraction File of the Joint Committee on Powder Diffraction Standards (JCPDS). (Author)

Prevention of CMOS latch-up by gold doping

International Nuclear Information System (INIS)

Dawes, W.R.; Derbenwick, G.F.

1976-01-01

CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

Toward CMOS image sensor based glucose monitoring.

Science.gov (United States)

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2012-09-07

Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

High-voltage CMOS detectors

International Nuclear Information System (INIS)

Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

2016-01-01

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

High-voltage CMOS detectors

Energy Technology Data Exchange (ETDEWEB)

Ehrler, F., E-mail: felix.ehrler@student.kit.edu; Blanco, R.; Leys, R.; Perić, I.

2016-07-11

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

Large Format CMOS-based Detectors for Diffraction Studies

Science.gov (United States)

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

Large Format CMOS-based Detectors for Diffraction Studies

International Nuclear Information System (INIS)

Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

2013-01-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

Transmission of wireless neural signals through a 0.18 µm CMOS low-power amplifier.

Science.gov (United States)

Gazziro, M; Braga, C F R; Moreira, D A; Carvalho, A C P L F; Rodrigues, J F; Navarro, J S; Ardila, J C M; Mioni, D P; Pessatti, M; Fabbro, P; Freewin, C; Saddow, S E

2015-01-01

In the field of Brain Machine Interfaces (BMI) researchers still are not able to produce clinically viable solutions that meet the requirements of long-term operation without the use of wires or batteries. Another problem is neural compatibility with the electrode probes. One of the possible ways of approaching these problems is the use of semiconductor biocompatible materials (silicon carbide) combined with an integrated circuit designed to operate with low power consumption. This paper describes a low-power neural signal amplifier chip, named Cortex, fabricated using 0.18 μm CMOS process technology with all electronics integrated in an area of 0.40 mm(2). The chip has 4 channels, total power consumption of only 144 μW, and is impedance matched to silicon carbide biocompatible electrodes.

Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

NARCIS (Netherlands)

Dutta, Satadal

2017-01-01

Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

Design of CMOS imaging system based on FPGA

Science.gov (United States)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

Directory of Open Access Journals (Sweden)

Haitao Li

2016-12-01

Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

E-Beam Effects on CMOS Active Pixel Sensors

International Nuclear Information System (INIS)

Kang, Dong Ook; Jo, Gyu Seong; Kim, Hyeon Daek; Kim, Hyunk Taek; Kim, Jong Yeol; Kim, Chan Kyu

2011-01-01

Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co 60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

Optimizing image-based patterned defect inspection through FDTD simulations at multiple ultraviolet wavelengths

Science.gov (United States)

Barnes, Bryan M.; Zhou, Hui; Henn, Mark-Alexander; Sohn, Martin Y.; Silver, Richard M.

2017-06-01

The sizes of non-negligible defects in the patterning of a semiconductor device continue to decrease as the dimensions for these devices are reduced. These "killer defects" disrupt the performance of the device and must be adequately controlled during manufacturing, and new solutions are required to improve optics-based defect inspection. To this end, our group has reported [Barnes et al., Proc. SPIE 1014516 (2017)] our initial five-wavelength simulation study, evaluating the extensibility of defect inspection by reducing the inspection wavelength from a deep-ultraviolet wavelength to wavelengths in the vacuum ultraviolet and the extreme ultraviolet. In that study, a 47 nm wavelength yielded enhancements in the signal to noise (SNR) by a factor of five compared to longer wavelengths and in the differential intensities by as much as three orders-of-magnitude compared to 13 nm. This paper briefly reviews these recent findings and investigates the possible sources for these disparities between results at 13 nm and 47 nm wavelengths. Our in-house finite-difference time-domain code (FDTD) is tested in both two and three dimensions to determine how computational conditions contributed to the results. A modified geometry and materials stack is presented that offers a second viewpoint of defect detectability as functions of wavelength, polarization, and defect type. Reapplication of the initial SNR-based defect metric again yields no detection of a defect at λ = 13 nm, but additional image preprocessing now enables the computation of the SNR for λ = 13 nm simulated images and has led to a revised defect metric that allows comparisons at all five wavelengths.

Multi-wavelength lasers using AWGs

NARCIS (Netherlands)

Besten, den J.H.

2003-01-01

Multiwavelength lasers using AWGs can be used as digitally tunable lasers with simple channel selection, and for generating multiple wavelengths simultanously. In this paper a number of different configurations is reviewed.

Small Pixel Hybrid CMOS X-ray Detectors

Science.gov (United States)

Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

Investigation of silicon/silicon germanium multiple quantum well layers in silicon avalanche photodiodes

International Nuclear Information System (INIS)

Loudon, A.Y.

2002-01-01

Silicon single photon avalanche diodes (SPADs) are currently utilised in many single photon counting systems due to their high efficiency, fast response times, low voltage operation and potentially low cost. For fibre based applications however (at wavelengths 1.3 and 1.55μm) and eye-safe wavelength applications (>1.4μm), Si devices are not suitable due to their 1.1μm absorption edge and hence greatly reduced absorption above this wavelength. InGaAs/InP or Ge SPADs absorb at these longer wavelengths, but both require cryogenic cooling for low noise operation and III-V integration with conventional Si circuitry is difficult. Si/SiGe is currently attracting great interest for optoelectronic applications and attempts to combine Si avalanche photodiodes with Si/SiGe multiple quantum well absorbing layers have been successful. Here, an effort to utilise this material system has shown an improvement in photon counting efficiency above 1.1μm of more than 30 times compared to an all-Si control device. In addition to its longer wavelength response, this Si/SiGe device has room temperature operation, low cost fabrication and is compatible with conventional Si circuitry. (author)

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

Science.gov (United States)

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

CMOS serial link for fully duplexed data communication

Science.gov (United States)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.

Science.gov (United States)

Li, Guoliang; Zheng, Xuezhe; Yao, Jin; Thacker, Hiren; Shubin, Ivan; Luo, Ying; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

2011-10-10

We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 μm ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 μm2 footprint.

Decal electronics for printed high performance cmos electronic systems

KAUST Repository

Hussain, Muhammad Mustafa; Sevilla, Galo Torres; Cordero, Marlon Diaz; Kutbee, Arwa T.

2017-01-01

High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications

CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

Data.gov (United States)

Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

CMOS Compressed Imaging by Random Convolution

OpenAIRE

Jacques, Laurent; Vandergheynst, Pierre; Bibet, Alexandre; Majidzadeh, Vahid; Schmid, Alexandre; Leblebici, Yusuf

2009-01-01

We present a CMOS imager with built-in capability to perform Compressed Sensing. The adopted sensing strategy is the random Convolution due to J. Romberg. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to comp...

The challenge of sCMOS image sensor technology to EMCCD

Science.gov (United States)

Chang, Weijing; Dai, Fang; Na, Qiyue

2018-02-01

In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

Science.gov (United States)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

Variationen und ihre Kompensation in CMOS Digitalschaltungen

OpenAIRE

Baumann, Thomas

2010-01-01

Variationen bei der Herstellung und während des Betriebs von CMOS Schaltungen beeinflussen deren Geschwindigkeit und erschweren die Verifikation der in der Spezifikation zugesicherten Eigenschaften. In dieser Arbeit wird eine abstraktionsebenenübergreifende Vorgehensweise zur Abschätzung des Einflusses von Prozess- und betriebsbedingten Umgebungsvariationen auf die Geschwindigkeit einer Schaltung vorgestellt. Neben Untersuchungen der Laufzeitsensitivität in low-power CMOS Technologien von...

CMOS Image Sensor with a Built-in Lane Detector

Directory of Open Access Journals (Sweden)

Li-Chen Fu

2009-03-01

Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

CMOS Image Sensor with a Built-in Lane Detector.

Science.gov (United States)

Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

2009-01-01

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

Low-latency optical parallel adder based on a binary decision diagram with wavelength division multiplexing scheme

Science.gov (United States)

Shinya, A.; Ishihara, T.; Inoue, K.; Nozaki, K.; Kita, S.; Notomi, M.

2018-02-01

We propose an optical parallel adder based on a binary decision diagram that can calculate simply by propagating light through electrically controlled optical pass gates. The CARRY and CARRY operations are multiplexed in one circuit by a wavelength division multiplexing scheme to reduce the number of optical elements, and only a single gate constitutes the critical path for one digit calculation. The processing time reaches picoseconds per digit when we use a 100-μm-long optical path gates, which is ten times faster than a CMOS circuit.

An 80x80 microbolometer type thermal imaging sensor using the LWIR-band CMOS infrared (CIR) technology

Science.gov (United States)

Tankut, Firat; Cologlu, Mustafa H.; Askar, Hidir; Ozturk, Hande; Dumanli, Hilal K.; Oruc, Feyza; Tilkioglu, Bilge; Ugur, Beril; Akar, Orhan Sevket; Tepegoz, Murat; Akin, Tayfun

2017-02-01

This paper introduces an 80x80 microbolometer array with a 35 μm pixel pitch operating in the 8-12 μm wavelength range, where the detector is fabricated with the LWIR-band CMOS infrared technology, shortly named as CIR, which is a novel microbolometer implementation technique developed to reduce the detector cost in order to enable the use of microbolometer type sensors in high volume markets, such as the consumer market and IoT. Unlike the widely used conventional surface micromachined microbolometer approaches, MikroSens' CIR detector technology does not require the use of special high TCR materials like VOx or a-Si, instead, it allows to implement microbolometers with standard CMOS layers, where the suspended bulk micromachined structure is obtained by only few consecutive selective MEMS etching steps while protecting the wirebond pads with a simple lithograpy step. This approach not only reduces the fabrication cost but also increases the production yield. In addition, needing simple subtractive post-CMOS fabrication steps allows the CIR technology to be carried out in any CMOS and MEMS foundry in a truly fabless fashion, where industrially mature and Au-free wafer level vacuum packaging technologies can also be carried out, leading to cost advantage, simplicity, scalability, and flexibility. The CIR approach is used to implement an 80x80 FPA with 35 μm pixel pitch, namely MS0835A, using a 0.18 μm CMOS process. The fabricated sensor is measured to provide NETD (Noise Equivalent Temperature Difference) value of 163 mK at 17 fps (frames per second) and 71 mK at 4 fps with F/1.0 optics in a dewar environment. The measurement results of the wafer level vacuum packaged sensors with one side AR coating shows an NETD values of 112 mK at 4 fps with F/1.1 optics, i.e., demonstrates a good performance for high volume low-cost applications like advanced presence detection and human counting applications. The CIR approach of MikroSens is scalable and can be used to

CMOS Integrated Carbon Nanotube Sensor

International Nuclear Information System (INIS)

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

2009-01-01

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

CMOS analog circuit design

CERN Document Server

Allen, Phillip E

1987-01-01

This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

Characterization of active CMOS sensors for capacitively coupled pixel detectors

Energy Technology Data Exchange (ETDEWEB)

Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

2015-07-01

Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

Systematic wavelength selection for improved multivariate spectral analysis

Science.gov (United States)

Thomas, Edward V.; Robinson, Mark R.; Haaland, David M.

1995-01-01

Methods and apparatus for determining in a biological material one or more unknown values of at least one known characteristic (e.g. the concentration of an analyte such as glucose in blood or the concentration of one or more blood gas parameters) with a model based on a set of samples with known values of the known characteristics and a multivariate algorithm using several wavelength subsets. The method includes selecting multiple wavelength subsets, from the electromagnetic spectral region appropriate for determining the known characteristic, for use by an algorithm wherein the selection of wavelength subsets improves the model's fitness of the determination for the unknown values of the known characteristic. The selection process utilizes multivariate search methods that select both predictive and synergistic wavelengths within the range of wavelengths utilized. The fitness of the wavelength subsets is determined by the fitness function F=.function.(cost, performance). The method includes the steps of: (1) using one or more applications of a genetic algorithm to produce one or more count spectra, with multiple count spectra then combined to produce a combined count spectrum; (2) smoothing the count spectrum; (3) selecting a threshold count from a count spectrum to select these wavelength subsets which optimize the fitness function; and (4) eliminating a portion of the selected wavelength subsets. The determination of the unknown values can be made: (1) noninvasively and in vivo; (2) invasively and in vivo; or (3) in vitro.

Long term ionization response of several BiCMOS VLSIC technologies

International Nuclear Information System (INIS)

Pease, R.L.; Combs, W.; Clark, S.

1992-01-01

BiCMOS is emerging as a strong competitor to CMOS for gate arrays and memories because of its performance advantages for the same feature size. In this paper, the authors examine the long term ionization response of five BiCMOS technologies by characterizing test structures which emphasize the various failure modes of CMOS and bipolar. The primary failure modes are found to be associated with the recessed field oxide isolation; edge leakage in the n channel MOSFETs and buried layer to buried layer leakage in the bipolar. The ionization failure thresholds for worst case bias were in the range of 5-20 Krad(Si) for both failure modes in all five technologies

First principle leakage current reduction technique for CMOS devices

CSIR Research Space (South Africa)

Tsague, HD

2015-12-01

Full Text Available This paper presents a comprehensive study of leakage reduction techniques applicable to CMOS based devices. In the process, mathematical equations that model the power-performance trade-offs in CMOS logic circuits are presented. From those equations...

Bandgap-customizable germanium using lithographically determined biaxial tensile strain for silicon-compatible optoelectronics.

Science.gov (United States)

Sukhdeo, David S; Nam, Donguk; Kang, Ju-Hyung; Brongersma, Mark L; Saraswat, Krishna C

2015-06-29

Strain engineering has proven to be vital for germanium-based photonics, in particular light emission. However, applying a large permanent biaxial tensile strain to germanium has been a challenge. We present a simple, CMOS-compatible technique to conveniently induce a large, spatially homogenous strain in circular structures patterned within germanium nanomembranes. Our technique works by concentrating and amplifying a pre-existing small strain into a circular region. Biaxial tensile strains as large as 1.11% are observed by Raman spectroscopy and are further confirmed by photoluminescence measurements, which show enhanced and redshifted light emission from the strained germanium. Our technique allows the amount of biaxial strain to be customized lithographically, allowing the bandgaps of different germanium structures to be independently customized in a single mask process.

Ion traps fabricated in a CMOS foundry

Energy Technology Data Exchange (ETDEWEB)

Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

An algorithm and a Tool for Wavelength Allocation in OMS-SP Ring Architecture

DEFF Research Database (Denmark)

Riaz, Muhammad Tahir; Pedersen, Jens Myrup; Madsen, Ole Brun

2006-01-01

OMS-SP ring is one of the well known architectures in Wavelength Division Multiplexing based optical fiber networks. The architecture supports a restorable full mesh in an optical fiber ring using multiple light wavelengths. The paper presents an algorithm to allocate wavelengths in the OMS-SP ri...... architecture. A tool is also introduced which implements the algorithm and assigns wavelengths. The proposed algorithm uses fewer number of wavelengths than the classical allocation method. The algorithm is described and results are presented.......OMS-SP ring is one of the well known architectures in Wavelength Division Multiplexing based optical fiber networks. The architecture supports a restorable full mesh in an optical fiber ring using multiple light wavelengths. The paper presents an algorithm to allocate wavelengths in the OMS-SP ring...

Non-invasive, MRI-compatible fibreoptic device for functional near-IR reflectometry of human brain

International Nuclear Information System (INIS)

Sorvoja, H.S.S.; Myllylae, T S; Myllylae, Risto A; Kirillin, M Yu; Sergeeva, Ekaterina A; Elseoud, A A; Nikkinen, J; Tervonen, O; Kiviniemi, V

2011-01-01

A non-invasive device for measuring blood oxygen variations in human brain is designed, implemented, and tested for MRI compatibility. The device is based on principles of near-IR reflectometry; power LEDs serve as sources of probing radiation delivered to patient skin surface through optical fibres. Numerical Monte Carlo simulations of probing radiation propagation in a multilayer brain model are performed to evaluate signal levels at different source - detector separations at three operation wavelengths and an additional wavelength of 915 nm. It is shown that the device can be applied for brain activity studies using power LEDs operating at 830 and 915 nm, while employment of wavelength of 660 nm requires an increased probing power. Employment of the wavelength of 592 nm in the current configuration is unreasonable. (application of lasers and laser-optical methods in life sciences)

CMOS front ends for millimeter wave wireless communication systems

CERN Document Server

Deferm, Noël

2015-01-01

This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

Merits of CMOS/SIMOX technology for low-voltage SRAM macros

CERN Document Server

Kumagai, K; Yamada, T; Nakamura, H; Onishi, H; Matsubara, Y; Imai, K; Kurosawa, S

1999-01-01

A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs).

Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

International Nuclear Information System (INIS)

Liu, Q; Van Duzer, T; Fujiwara, K; Yoshikawa, N

2006-01-01

Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 μm CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm 2 technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory

CMOS Imaging Sensor Technology for Aerial Mapping Cameras

Science.gov (United States)

Neumann, Klaus; Welzenbach, Martin; Timm, Martin

2016-06-01

In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

NARCIS (Netherlands)

Patra, B; Incandela, R.M.; van Dijk, J.P.G.; Homulle, H.A.R.; Song, Lin; Shahmohammadi, M.; Staszewski, R.B.; Vladimirescu, A.; Babaie, M.; Sebastiano, F.; Charbon, E.E.E.

2018-01-01

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising

From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

DEFF Research Database (Denmark)

Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

2008-01-01

This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

Counting neutrons with a commercial S-CMOS camera

Science.gov (United States)

Patrick, Van Esch; Paolo, Mutti; Emilio, Ruiz-Martinez; Estefania, Abad Garcia; Marita, Mosconi; Jon, Ortega

2018-01-01

It is possible to detect individual flashes from thermal neutron impacts in a ZnS scintillator using a CMOS camera looking at the scintillator screen, and off line image processing. Some preliminary results indicated that the efficiency of recognition could be improved by optimizing the light collection and the image processing. We will report on this ongoing work which is a result from the collaboration between ESS Bilbao and the ILL. The main progress to be reported is situated on the level of the on-line treatment of the imaging data. If this technology is to work on a genuine scientific instrument, it is necessary that all the processing happens on line, to avoid the accumulation of large amounts of image data to be analyzed off line. An FPGA-based real-time full-deca mode VME-compatible CameraLink board has been developed at the SCI of the ILL, which is able to manage the data flow from the camera and convert it in a reasonable "neutron impact" data flow like from a usual neutron counting detector. The main challenge of the endeavor is the optical light collection from the scintillator. While the light yield of a ZnS scintillator is a priori rather important, the amount of light collected with a photographic objective is small. Different scintillators and different light collection techniques have been experimented with and results will be shown for different setups improving upon the light recuperation on the camera sensor. Improvements on the algorithm side will also be presented. The algorithms have to be at the same time efficient in their recognition of neutron signals, in their rejection of noise signals (internal and external to the camera) but also have to be simple enough to be easily implemented in the FPGA. The path from the idea of detecting individual neutron impacts with a CMOS camera to a practical working instrument detector is challenging, and in this paper we will give an overview of the part of the road that has already been walked.

Counting neutrons with a commercial S-CMOS camera

Directory of Open Access Journals (Sweden)

Patrick Van Esch

2018-01-01

Full Text Available It is possible to detect individual flashes from thermal neutron impacts in a ZnS scintillator using a CMOS camera looking at the scintillator screen, and off line image processing. Some preliminary results indicated that the efficiency of recognition could be improved by optimizing the light collection and the image processing. We will report on this ongoing work which is a result from the collaboration between ESS Bilbao and the ILL. The main progress to be reported is situated on the level of the on-line treatment of the imaging data. If this technology is to work on a genuine scientific instrument, it is necessary that all the processing happens on line, to avoid the accumulation of large amounts of image data to be analyzed off line. An FPGA-based real-time full-deca mode VME-compatible CameraLink board has been developed at the SCI of the ILL, which is able to manage the data flow from the camera and convert it in a reasonable “neutron impact” data flow like from a usual neutron counting detector. The main challenge of the endeavor is the optical light collection from the scintillator. While the light yield of a ZnS scintillator is a priori rather important, the amount of light collected with a photographic objective is small. Different scintillators and different light collection techniques have been experimented with and results will be shown for different setups improving upon the light recuperation on the camera sensor. Improvements on the algorithm side will also be presented. The algorithms have to be at the same time efficient in their recognition of neutron signals, in their rejection of noise signals (internal and external to the camera but also have to be simple enough to be easily implemented in the FPGA. The path from the idea of detecting individual neutron impacts with a CMOS camera to a practical working instrument detector is challenging, and in this paper we will give an overview of the part of the road that has

Wavelength encoding technique for particle analyses in hematology analyzer

Science.gov (United States)

Rongeat, Nelly; Brunel, Patrick; Gineys, Jean-Philippe; Cremien, Didier; Couderc, Vincent; Nérin, Philippe

2011-07-01

The aim of this study is to combine multiple excitation wavelengths in order to improve accuracy of fluorescence characterization of labeled cells. The experimental demonstration is realized with a hematology analyzer based on flow cytometry and a CW laser source emitting two visible wavelengths. A given optical encoding associated to each wavelength allows fluorescence identification coming from specific fluorochromes and avoiding the use of noisy compensation method.

IR sensitivity enhancement of CMOS Image Sensor with diffractive light trapping pixels.

Science.gov (United States)

Yokogawa, Sozo; Oshiyama, Itaru; Ikeda, Harumi; Ebiko, Yoshiki; Hirano, Tomoyuki; Saito, Suguru; Oinoue, Takashi; Hagimoto, Yoshiya; Iwamoto, Hayato

2017-06-19

We report on the IR sensitivity enhancement of back-illuminated CMOS Image Sensor (BI-CIS) with 2-dimensional diffractive inverted pyramid array structure (IPA) on crystalline silicon (c-Si) and deep trench isolation (DTI). FDTD simulations of semi-infinite thick c-Si having 2D IPAs on its surface whose pitches over 400 nm shows more than 30% improvement of light absorption at λ = 850 nm and the maximum enhancement of 43% with the 540 nm pitch at the wavelength is confirmed. A prototype BI-CIS sample with pixel size of 1.2 μm square containing 400 nm pitch IPAs shows 80% sensitivity enhancement at λ = 850 nm compared to the reference sample with flat surface. This is due to diffraction with the IPA and total reflection at the pixel boundary. The NIR images taken by the demo camera equip with a C-mount lens show 75% sensitivity enhancement in the λ = 700-1200 nm wavelength range with negligible spatial resolution degradation. Light trapping CIS pixel technology promises to improve NIR sensitivity and appears to be applicable to many different image sensor applications including security camera, personal authentication, and range finding Time-of-Flight camera with IR illuminations.

CMOS Image Sensors: Electronic Camera On A Chip

Science.gov (United States)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

CMOS image sensor-based immunodetection by refractive-index change.

Science.gov (United States)

Devadhasan, Jasmine P; Kim, Sanghyo

2012-01-01

A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

CMOS circuit design, layout and simulation

CERN Document Server

Baker, R Jacob

2010-01-01

The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

Photon detection with CMOS sensors for fast imaging

International Nuclear Information System (INIS)

Baudot, J.; Dulinski, W.; Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N.

2009-01-01

Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e - , and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100μs have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

Contact CMOS imaging of gaseous oxygen sensor array.

Science.gov (United States)

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

Single-chip RF communications systems in CMOS

DEFF Research Database (Denmark)

Olesen, Ole

1997-01-01

The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

CMOS sigma-delta converters practical design guide

CERN Document Server

De la Rosa, Jose M

2013-01-01

A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

High-Voltage-Input Level Translator Using Standard CMOS

Science.gov (United States)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

Application of Hilbert-Huang Transform in Generating Spectrum-Compatible Earthquake Time Histories

OpenAIRE

Ni, Shun-Hao; Xie, Wei-Chau; Pandey, Mahesh

2011-01-01

Spectrum-compatible earthquake time histories have been widely used for seismic analysis and design. In this paper, a data processing method, Hilbert-Huang transform, is applied to generate earthquake time histories compatible with the target seismic design spectra based on multiple actual earthquake records. Each actual earthquake record is decomposed into several components of time-dependent amplitude and frequency by Hilbert-Huang transform. The spectrum-compatible earthquake time history ...

Advancement of CMOS Doping Technology in an External Development Framework

Science.gov (United States)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Differentiation of ocular fundus fluorophores by fluorescence lifetime imaging using multiple excitation and emission wavelengths

Science.gov (United States)

Hammer, M.; Schweitzer, D.; Schenke, S.; Becker, W.; Bergmann, A.

2006-10-01

Ocular fundus autofluorescence imaging has been introduced into clinical diagnostics recently. It is in use for the observation of the age pigment lipofuscin, a precursor of age - related macular degeneration (AMD). But other fluorophores may be of interest too: The redox pair FAD - FADH II provides information on the retinal energy metabolism, advanced glycation end products (AGE) indicate protein glycation associated with pathologic processes in diabetes as well as AMD, and alterations in the fluorescence of collagen and elastin in connective tissue give us the opportunity to observe fibrosis by fluorescence imaging. This, however, needs techniques able to differentiate particular fluorophores despite limited permissible ocular exposure as well as excitation wavelength (limited by the transmission of the human ocular lens to >400 nm). We present an ophthalmic laser scanning system (SLO), equipped with picosecond laser diodes (FWHM 100 ps, 446 nm or 468 nm respectively) and time correlated single photon counting (TCSPC) in two emission bands (500 - 560 nm and 560 - 700 nm). The decays were fitted by a bi-exponential model. Fluorescence spectra were measured by a fluorescence spectrometer fluorolog. Upon excitation at 446 nm, the fluorescence of AGE, FAD, and lipofuscin were found to peak at 503 nm, 525 nm, and 600 nm respectively. Accordingly, the statistical distribution of the fluorescence decay times was found to depend on the different excitation wavelengths and emission bands used. The use of multiple excitation and emission wavelengths in conjunction with fluorescence lifetime imaging allows us to discriminate between intrinsic fluorophores of the ocular fundus. Taken together with our knowledge on the anatomical structure of the fundus, these findings suggest an association of the short, middle and long fluorescence decay time to the retinal pigment epithelium, the retina, and connective tissue respectively.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

Science.gov (United States)

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Transient-induced latchup in CMOS integrated circuits

CERN Document Server

Ker, Ming-Dou

2009-01-01

"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

Development of a CMOS process using high energy ion implantation

International Nuclear Information System (INIS)

Stolmeijer, A.

1986-01-01

The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

A novel multi-level IC-compatible surface microfabrication technology for MEMS with independently controlled lateral and vertical submicron transduction gaps

Science.gov (United States)

Cicek, Paul-Vahe; Elsayed, Mohannad; Nabki, Frederic; El-Gamal, Mourad

2017-11-01

An above-IC compatible multi-level MEMS surface microfabrication technology based on a silicon carbide structural layer is presented. The fabrication process flow provides optimal electrostatic transduction by allowing the creation of independently controlled submicron vertical and lateral gaps without the need for high resolution lithography. Adopting silicon carbide as the structural material, the technology ensures material, chemical and thermal compatibility with modern semiconductor nodes, reporting the lowest peak processing temperature (i.e. 200 °C) of all comparable works. This makes this process ideally suited for integrating capacitive-based MEMS directly above standard CMOS substrates. Process flow design and optimization are presented in the context of bulk-mode disk resonators, devices that are shown to exhibit improved performance with respect to previous generation flexural beam resonators, and that represent relatively complex MEMS structures. The impact of impending improvements to the fabrication technology is discussed.

A novel multi-level IC-compatible surface microfabrication technology for MEMS with independently controlled lateral and vertical submicron transduction gaps

International Nuclear Information System (INIS)

Cicek, Paul-Vahe; Elsayed, Mohannad; Nabki, Frederic; El-Gamal, Mourad

2017-01-01

An above-IC compatible multi-level MEMS surface microfabrication technology based on a silicon carbide structural layer is presented. The fabrication process flow provides optimal electrostatic transduction by allowing the creation of independently controlled submicron vertical and lateral gaps without the need for high resolution lithography. Adopting silicon carbide as the structural material, the technology ensures material, chemical and thermal compatibility with modern semiconductor nodes, reporting the lowest peak processing temperature (i.e. 200 °C) of all comparable works. This makes this process ideally suited for integrating capacitive-based MEMS directly above standard CMOS substrates. Process flow design and optimization are presented in the context of bulk-mode disk resonators, devices that are shown to exhibit improved performance with respect to previous generation flexural beam resonators, and that represent relatively complex MEMS structures. The impact of impending improvements to the fabrication technology is discussed. (paper)

Generate tri-directional spectra-compatible time histories using HHT method

Energy Technology Data Exchange (ETDEWEB)

Li, Bo; Xie, Wei-Chau, E-mail: xie@uwaterloo.ca; Pandey, Mahesh D.

2016-11-15

Highlights: • Hilbert–Huang Transform are applied to modify real earthquake records. • Generate tri-directional time histories compatible with target spectra. • Both GRS and FRS are considered as target spectra. • Target spectra with multiple damping ratios are considered. - Abstract: This paper proposes two algorithms to generate spectrum-compatible time histories based on two approaches recommended by USNRC Standard Review Plan 3.7.1. Hilbert–Huang Transform technique is used to analyze frequency contents and amplitudes of seed motions. Through adjusting the frequency contents and amplitudes of seed motions, spectrum-compatible time histories are obtained. The first algorithm is to generate tri-directional time histories compatible with multi-damping target design spectra (ground response spectra or floor response spectra). The second algorithm is to generate tri-directional time histories compatible with single-damping target design spectra. Examples are presented to demonstrate versatility of these two proposed algorithms to generate spectra-compatible time histories.

Generate tri-directional spectra-compatible time histories using HHT method

International Nuclear Information System (INIS)

Li, Bo; Xie, Wei-Chau; Pandey, Mahesh D.

2016-01-01

Highlights: • Hilbert–Huang Transform are applied to modify real earthquake records. • Generate tri-directional time histories compatible with target spectra. • Both GRS and FRS are considered as target spectra. • Target spectra with multiple damping ratios are considered. - Abstract: This paper proposes two algorithms to generate spectrum-compatible time histories based on two approaches recommended by USNRC Standard Review Plan 3.7.1. Hilbert–Huang Transform technique is used to analyze frequency contents and amplitudes of seed motions. Through adjusting the frequency contents and amplitudes of seed motions, spectrum-compatible time histories are obtained. The first algorithm is to generate tri-directional time histories compatible with multi-damping target design spectra (ground response spectra or floor response spectra). The second algorithm is to generate tri-directional time histories compatible with single-damping target design spectra. Examples are presented to demonstrate versatility of these two proposed algorithms to generate spectra-compatible time histories.

Broadband enhancement of local density of states using silicon-compatible hyperbolic metamaterials

Energy Technology Data Exchange (ETDEWEB)

Wang, Yu; Inampudi, Sandeep; Capretti, Antonio [Department of Electrical and Computer Engineering and Photonics Center, Boston University, 8 Saint Mary' s Street Boston, Massachusetts 02215 (United States); Sugimoto, Hiroshi [Department of Electrical and Computer Engineering and Photonics Center, Boston University, 8 Saint Mary' s Street Boston, Massachusetts 02215 (United States); Department of Electrical and Electronic Engineering, Graduate School of Engineering, Kobe University, Rokkodai, Nada, Kobe 657-8501 (Japan); Fujii, Minoru [Department of Electrical and Electronic Engineering, Graduate School of Engineering, Kobe University, Rokkodai, Nada, Kobe 657-8501 (Japan); Dal Negro, Luca, E-mail: dalnegro@bu.edu [Department of Electrical and Computer Engineering and Photonics Center, Boston University, 8 Saint Mary' s Street Boston, Massachusetts 02215 (United States); Division of Materials Science and Engineering, Boston University, 15 Saint Mary' s Street, Brookline, Massachusetts 02446 (United States)

2015-06-15

Light emitting silicon quantum dots by colloidal synthesis were uniformly spin-coated into a 20 nm-thick film and deposited atop a hyperbolic metamaterial of alternating TiN and SiO{sub 2} sub-wavelength layers. Using steady-state and time-resolved photoluminescence spectroscopy as a function of the emission wavelength in partnership with rigorous electromagnetic modeling of dipolar emission, we demonstrate enhanced Local Density of States and coupling to high-k modes in a broad spectral range. These findings provide an alternative approach for the engineering of novel Si-compatible broadband sources that leverage the control of radiative transitions in hyperbolic metamaterials and the flexibility of the widespread Si platform.

A CMOS transconductance-C filter technique for very high frequencies

NARCIS (Netherlands)

Nauta, Bram

1992-01-01

CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters

Automatic kelvin probe compatible with ultrahigh vacuum

NARCIS (Netherlands)

Baikie, I.D.; van der Werf, Kees; Oerbekke, H.; Broeze, J.; van Silfhout, Arend

1989-01-01

This article describes a new type of in situ ultrahigh‐vacuum compatible kelvin probe based on a voice‐coil driving mechanism. This design exhibits several advantages over conventional mechanical feed‐through and (in situ) piezoelectric devices in regard to the possibility of multiple probe

Nano-electromechanical switch-CMOS hybrid technology and its applications.

Science.gov (United States)

Lee, B H; Hwang, H J; Cho, C H; Lim, S K; Lee, S Y; Hwang, H

2011-01-01

Si-based CMOS technology is facing a serious challenge in terms of power consumption and variability. The increasing costs associated with physical scaling have motivated a search for alternative approaches. Hybridization of nano-electromechanical (NEM)-switch and Si-based CMOS devices has shown a theoretical feasibility for power management, but a huge technical gap must be bridged before a nanoscale NEM switch can be realized due to insufficient material development and the limited understanding of its reliability characteristics. These authors propose the use of a multilayer graphene as a nanoscale cantilever material for a nanoscale NEM switchwith dimensions comparable to those of the state-of-the-art Si-based CMOS devices. The optimal thickness for the multilayer graphene (about five layers) is suggested based on an analytical model. Multilayer graphene can provide the highest Young's modulus among the known electrode materials and a yielding strength that allows more than 15% bending. Further research on material screening and device integration is needed, however, to realize the promises of the hybridization of NEM-switch and Si-based CMOS devices.

Development of radiation hard CMOS active pixel sensors for HL-LHC

International Nuclear Information System (INIS)

Pernegger, Heinz

2016-01-01

New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

Science.gov (United States)

Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

2017-11-26

Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

Integrated 60GHz RF beamforming in CMOS

CERN Document Server

Yu, Yikun; van Roermund, Arthur H M

2011-01-01

""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

Challenges & Roadmap for Beyond CMOS Computing Simulation.

Energy Technology Data Exchange (ETDEWEB)

Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2017-12-01

Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Characterization of active CMOS pixel sensors on high resistive substrate

Energy Technology Data Exchange (ETDEWEB)

Hirono, Toko; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Bonn (Germany)

2016-07-01

Active CMOS pixel sensors are very attractive as radiation imaging pixel detector because they do not need cost-intensive fine pitch bump bonding. High radiation tolerance and time resolution are required to apply those sensors to upcoming particle physics experiments. To achieve these requirements, the active CMOS pixel sensors were developed on high resistive substrates. Signal charges are collected faster by drift in high resistive substrates than in standard low resistive substrates yielding also a higher radiation tolerance. A prototype of the active CMOS pixel sensor has been fabricated in the LFoundry 150 nm CMOS process on 2 kΩcm substrate. This prototype chip was thinned down to 300 μm and the backside has been processed and can contacted by an aluminum contact. The breakdown voltage is around -115 V, and the depletion width has been measured to be as large as 180 μm at a bias voltage of -110 V. Gain and noise of the readout circuitry agree with the designed values. Performance tests in the lab and test beam have been done before and after irradiation with X-rays and neutrons. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

Optical frequency-domain reflectometry using multiple wavelength-swept elements of a DFB laser array

Science.gov (United States)

DiLazaro, Tom; Nehmetallah, Georges

2017-02-01

Coherent optical frequency-domain reflectometry (C-OFDR) is a distance measurement technique with significant sensitivity and detector bandwidth advantages over normal time-of-flight methods. Although several swept-wavelength laser sources exist, many exhibit short coherence lengths, or require precision mechanical tuning components. Semiconductor distributed feedback lasers (DFBs) are advantageous as a mid-to-long range OFDR source because they exhibit a narrow linewidth and can be rapidly tuned simply via injection current. However, the sweep range of an individual DFB is thermally limited. Here, we present a novel high-resolution OFDR system that uses a compact, monolithic 12-element DFB array to create a continuous, gap-free sweep over a wide wavelength range. Wavelength registration is provided by the incorporation of a HCN gas cell and reference interferometer. The wavelength-swept spectra of the 12 DFBs are combined in post-processing to achieve a continuous total wavelength sweep of more than 40 nm (5.4 THz) in the telecommunications C-Band range.

Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination

Directory of Open Access Journals (Sweden)

Michele Grassi

2009-06-01

Full Text Available This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively.

Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

CERN Document Server

Nguyen, Cam

2017-01-01

This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

CERN Document Server

Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

2003-01-01

Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

Development of Gentle Slope Light Guide Structure in a 3.4 μm Pixel Pitch Global Shutter CMOS Image Sensor with Multiple Accumulation Shutter Technology.

Science.gov (United States)

Sekine, Hiroshi; Kobayashi, Masahiro; Onuki, Yusuke; Kawabata, Kazunari; Tsuboi, Toshiki; Matsuno, Yasushi; Takahashi, Hidekazu; Inoue, Shunsuke; Ichikawa, Takeshi

2017-12-09

CMOS image sensors (CISs) with global shutter (GS) function are strongly required in order to avoid image degradation. However, CISs with GS function have generally been inferior to the rolling shutter (RS) CIS in performance, because they have more components. This problem is remarkable in small pixel pitch. The newly developed 3.4 µm pitch GS CIS solves this problem by using multiple accumulation shutter technology and the gentle slope light guide structure. As a result, the developed GS pixel achieves 1.8 e - temporal noise and 16,200 e - full well capacity with charge domain memory in 120 fps operation. The sensitivity and parasitic light sensitivity are 28,000 e - /lx·s and -89 dB, respectively. Moreover, the incident light angle dependence of sensitivity and parasitic light sensitivity are improved by the gentle slope light guide structure.

Laser emission in Nd3+ doped barium–titanium–silicate microspheres under continuous and chopped wave pumping in a non-coupled pumping scheme

International Nuclear Information System (INIS)

Martín, L L; Pérez-Rodríguez, C; Martín, I R; Navarro-Urrios, D; Ferrarese-Lupi, F; Garrido, B; Montserrat, J; Dominguez, C; Capuj, N

2013-01-01

Laser action using non-coupled excitation and detection of microspheres made of Nd 3+ doped barium–titanium–silicate glass has been demonstrated and measured. The microspheres have also been successfully deposited over Si 3 N 4 strip waveguides with a SiO 2 separation layer, thus enabling the laser emission extraction onto a CMOS compatible photonic circuit. The dynamics of the lasing wavelength and intensity has been studied as a function of the pump power and interpreted in terms of thermal effects generated through non-radiative recombination of the excited ions. (paper)

Hybrid vertical-cavity laser with lateral emission into a silicon waveguide

DEFF Research Database (Denmark)

Park, Gyeong Cheol; Xue, Weiqi; Taghizadeh, Alireza

2015-01-01

into the waveguide integrated with the laser. This laser has the advantages of long-wavelength vertical-cavity surface-emitting lasers, such as low threshold and high side-mode suppression ratio, while allowing integration with silicon photonic circuits, and is fabricated using CMOS compatible processes. It has......We experimentally demonstrate an optically-pumped III-V/Si vertical-cavity laser with lateral emission into a silicon waveguide. This on-chip hybrid laser comprises a distributed Bragg reflector, a III-V active layer, and a high-contrast grating reflector, which simultaneously funnels light...

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

Science.gov (United States)

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

Recent developments with CMOS SSPM photodetectors

Energy Technology Data Exchange (ETDEWEB)

Stapels, Christopher J. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)], E-mail: CStapels@RMDInc.com; Barton, Paul [University of Michigan, Ann Arbor, MI (United States); Johnson, Erik B. [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Wehe, David K. [University of Michigan, Ann Arbor, MI (United States); Dokhale, Purushottam; Shah, Kanai [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Augustine, Frank L. [Augustine Engineering, Encinitas, CA (United States); Christian, James F. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)

2009-10-21

Experiments and simulations using various solid-state photomultiplier (SSPM) designs have been performed to evaluate pixel layouts and explore design choices. SPICE simulations of a design for position-sensing SSPMs showed charge division in the resistor network, and anticipated timing performance of the device. The simulation results predict good position information for resistances in the range of 1-5 k{omega} and 150-{omega} preamplifier input impedance. Back-thinning of CMOS devices can possibly increase the fill factor to 100%, improve spectral sensitivity, and allow for the deposition of anti-reflective coatings after fabrication. We report initial results from back illuminating a CMOS SSPM, and single Geiger-mode avalanche photodiode (GPD) pixels, thinned to 50 {mu}m.

Inundation downscaling for the development of a long-term and global inundation database compatible to SWOT mission

Science.gov (United States)

Aires, Filipe; Prigent, Catherine; Papa, Fabrice

2014-05-01

The Global Inundation Extent from Multi-Satellite (GIEMS) provides multi-year monthly variations of the global surface water extent at about 25 kmx25 km resolution, from 1993 to 2007. It is derived from multiple satellite observations. Its spatial resolution is usually compatible with climate model outputs and with global land surface model grids but is clearly not adequate for local applications that require the characterization of small individual water bodies. There is today a strong demand for high-resolution inundation extent datasets, for a large variety of applications such as water management, regional hydrological modeling, or for the analysis of mosquitos-related diseases. Even for climate applications, the GIEMS resolution might be limited given recent results on the key importance of the smallest ponds in the emission of CH4, as compared to the largest ones. If the inundation extent is combined to altimetry measurements to obtain water volume changes, and finally river discharge to the ocean (Frappart et al. 2011), then a better resolved inundation extent will also improve the accuracy of these estimates. In the context of the SWOT mission, the downscaling of GIEMS has multiple applications uses but a major one will be to use the SWOT retrievals to develop a downscaling of GIEMS. This SWOT-compatible downscaling could then be used to built a SWOT-compatible high-resolution database back in time from 1993 to the SWOT launch date. This extension of SWOT record is necessary to perform climate studies related to climate change. This paper present three approaches to do downscale GIEMS. Two basins will be considered for illustrative purpose, Amazon, Niger and Mekhong. - Aires, F., F. Papa, C. Prigent, J.-F. Cretaux and M. Berge-Nguyen, Characterization and downscaling of the inundation extent over the Inner Niger delta using a multi-wavelength retrievals and Modis data, J. of Hydrometeorology, in press, 2014. - Aires, F., F. Papa and C. Prigent, A long

Split Bull's eye shaped aluminum antenna for plasmon-enhanced nanometer scale germanium photodetector.

Science.gov (United States)

Ren, Fang-Fang; Ang, Kah-Wee; Ye, Jiandong; Yu, Mingbin; Lo, Guo-Qiang; Kwong, Dim-Lee

2011-03-09

Bull's eye antennas are capable of efficiently collecting and concentrating optical signals into an ultrasmall area, offering an excellent solution to break the bottleneck between speed and photoresponse in subwavelength photodetectors. Here, we exploit the idea of split bull's eye antenna for a nanometer germanium photodetector operating at a standard communication wavelength of 1310 nm. The nontraditional plasmonic metal aluminum has been implemented in the resonant antenna structure fabricated by standard complementary metal-oxide-semiconductor (CMOS) processing. A significant enhancement in photoresponse could be achieved over the conventional bull's eye scheme due to an increased optical near-field in the active region. Moreover, with this novel antenna design the effective grating area could be significantly reduced without sacrificing device performance. This work paves the way for the future development of low-cost, high-density, and high-speed CMOS-compatible germanium-based optoelectronic devices.

Second-order multiple-scattering theory associated with backscattering enhancement for a millimeter wavelength weather radar with a finite beam width

Science.gov (United States)

Kobayashi, Satoru; Tanelli, Simone; Im, Eastwood

2005-01-01

Effects of multiple scattering on reflectivity are studied for millimeter wavelength weather radars. A time-independent vector theory, including up to second-order scattering, is derived for a single layer of hydrometeors of a uniform density and a uniform diameter. In this theory, spherical waves with a Gaussian antenna pattern are used to calculate ladder and cross terms in the analytical scattering theory. The former terms represent the conventional multiple scattering, while the latter terms cause backscattering enhancement in both the copolarized and cross-polarized components. As the optical thickness of the hydrometeor layer increases, the differences from the conventional plane wave theory become more significant, and essentially, the reflectivity of multiple scattering depends on the ratio of mean free path to radar footprint radius. These results must be taken into account when analyzing radar reflectivity for use in remote sensing.

Feasibility evaluation of 3D photoacoustic imaging of blood vessel structure using multiple wavelengths with a handheld probe

Science.gov (United States)

Uchimoto, Yo; Namita, Takeshi; Kondo, Kengo; Yamakawa, Makoto; Shiina, Tsuyoshi

2018-02-01

Photoacoustic imaging is anticipated for use in portraying blood vessel structures (e.g. neovascularization in inflamed regions). To reduce invasiveness and enhance ease handling, we developed a handheld photoacoustic imaging system using multiple wavelengths. The usefulness of the proposed system was investigated in phantom experiments and in vivo measurements. A silicon tube was embedded into chicken breast meat to simulate the blood vessel. The tube was filled with ovine blood. Then laser light was guided to the phantom surface by an optical fiber bundle close to the linear ultrasound probe. Photoacoustic images were obtained at 750-950 nm wavelengths. Strong photoacoustic signals from the boundary between blood and silicon tube are observed in these images. The shape of photoacoustic spectrum at the boundary resembles that of the HbO2 absorption spectrum at 750-920 nm. In photoacoustic images, similarity between photoacoustic spectrum and HbO2 absorption spectrum was evaluated by calculating the normalized correlation coefficient. Results show high correlation in regions of strong photoacoustic signals in photoacoustic images. These analyses demonstrate the feasibility of portraying blood vessel structures under practical conditions. To evaluate the feasibility of three-dimensional vascular imaging, in vivo experiments were conducted using three wavelengths. A right hand and ultrasound probe were set in degassed water. By scanning a probe, cross-sectional ultrasound and photoacoustic images were obtained at each location. Then, all ultrasound or photoacoustic images were piled up respectively. Then three-dimensional images were constructed. Resultant images portrayed blood vessel-like structures three-dimensionally. Furthermore, to distinguish blood vessels from other tissues (e.g. skin), distinguishing images of them were constructed by comparing photoacoustic signal intensity among three wavelengths. The resultant image portrayed blood vessels as

The wavelength frame multiplication chopper system for the ESS test beamline at the BER II reactor—A concept study of a fundamental ESS instrument principle

International Nuclear Information System (INIS)

Strobl, M.; Bulat, M.; Habicht, K.

2013-01-01

Contributing to the design update phase of the European Spallation Source ESS–scheduled to start operation in 2019–a test beamline is under construction at the BER II research reactor at Helmholtz Zentrum Berlin (HZB). This beamline offers experimental test capabilities of instrument concepts viable for the ESS. The experiments envisaged at this dedicated beamline comprise testing of components as well as of novel experimental approaches and methods taking advantage of the long pulse characteristic of the ESS source. Therefore the test beamline will be equipped with a sophisticated chopper system that provides the specific time structure of the ESS and enables variable wavelength resolutions via wavelength frame multiplication (WFM), a fundamental instrument concept beneficial for a number of instruments at ESS. We describe the unique chopper system developed for these purposes, which allows constant wavelength resolution for a wide wavelength band. Furthermore we discuss the implications for the conceptual design for related instrumentation at the ESS

State-of-the-art photodetectors for optoelectronic integration at telecommunication wavelength

Directory of Open Access Journals (Sweden)

Eng Png Ching

2015-01-01

Full Text Available Photodetectors hold a critical position in optoelectronic integrated circuits, and they convert light into electricity. Over the past decades, high-performance photodetectors (PDs have been aggressively pursued to enable high-speed, large-bandwidth, and low-noise communication applications. Various material systems have been explored and different structures designed to improve photodetection capability as well as compatibility with CMOS circuits. In this paper, we review state-of-theart photodetection technologies in the telecommunications spectrum based on different material systems, including traditional semiconductors such as InGaAs, Si, Ge and HgCdTe, as well as recently developed systems such as low-dimensional materials (e.g. graphene, carbon nanotube, etc. and noble metal plasmons. The corresponding material properties, fundamental mechanisms, fabrication, theoretical modelling and performance of the typical PDs are presented, including the emerging directions and perspectives of the PDs for optoelectronic integration applications are discussed.

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

Science.gov (United States)

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

CMOS-based avalanche photodiodes for direct particle detection

International Nuclear Information System (INIS)

Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

2007-01-01

Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

Threshold-Based Multiple Optical Signal Selection Scheme for Free-Space Optical Wavelength Division Multiplexing Systems

KAUST Repository

Nam, Sung Sik

2017-11-13

We propose a threshold-based multiple optical signal selection scheme (TMOS) for free-space optical wavelength division multiplexing systems. With this scheme, we can obtain higher spectral efficiency while reducing the possible complexity of implementation caused by the beam-selection scheme and without a considerable performance loss. To characterize the performance of our scheme, we statistically analyze the operation characteristics under conventional detection conditions (i.e., heterodyne detection and intensity modulation/direct detection techniques) with log-normal turbulence while taking into consideration the impact of pointing error. More specifically, we derive exact closed-form expressions for the outage probability, the average bit error rate, and the average spectral efficiency while adopting an adaptive modulation. Some selected results show that TMOS increases the average spectral efficiency while maintaining a minimum average bit error rate requirement.

The total dose effects on the 1/f noise of deep submicron CMOS transistors

International Nuclear Information System (INIS)

Hu Rongbin; Wang Yuxin; Lu Wu

2014-01-01

Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

OpenAIRE

Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao

2011-01-01

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...

Multi-wavelength approach towards on-product overlay accuracy and robustness

Science.gov (United States)

Bhattacharyya, Kaustuve; Noot, Marc; Chang, Hammer; Liao, Sax; Chang, Ken; Gosali, Benny; Su, Eason; Wang, Cathy; den Boef, Arie; Fouquet, Christophe; Huang, Guo-Tsai; Chen, Kai-Hsiung; Cheng, Kevin; Lin, John

2018-03-01

Success of diffraction-based overlay (DBO) technique1,4,5 in the industry is not just for its good precision and low toolinduced shift, but also for the measurement accuracy2 and robustness that DBO can provide. Significant efforts are put in to capitalize on the potential that DBO has to address measurement accuracy and robustness. Introduction of many measurement wavelength choices (continuous wavelength) in DBO is one of the key new capabilities in this area. Along with the continuous choice of wavelengths, the algorithms (fueled by swing-curve physics) on how to use these wavelengths are of high importance for a robust recipe setup that can avoid the impact from process stack variations (symmetric as well as asymmetric). All these are discussed. Moreover, another aspect of boosting measurement accuracy and robustness is discussed that deploys the capability to combine overlay measurement data from multiple wavelength measurements. The goal is to provide a method to make overlay measurements immune from process stack variations and also to report health KPIs for every measurement. By combining measurements from multiple wavelengths, a final overlay measurement is generated. The results show a significant benefit in accuracy and robustness against process stack variation. These results are supported by both measurement data as well as simulation from many product stacks.

Compatible Lie Bialgebras

International Nuclear Information System (INIS)

Wu Ming-Zhong; Bai Cheng-Ming

2015-01-01

A compatible Lie algebra is a pair of Lie algebras such that any linear combination of the two Lie brackets is a Lie bracket. We construct a bialgebra theory of compatible Lie algebras as an analogue of a Lie bialgebra. They can also be regarded as a “compatible version” of Lie bialgebras, that is, a pair of Lie bialgebras such that any linear combination of the two Lie bialgebras is still a Lie bialgebra. Many properties of compatible Lie bialgebras as the “compatible version” of the corresponding properties of Lie bialgebras are presented. In particular, there is a coboundary compatible Lie bialgebra theory with a construction from the classical Yang–Baxter equation in compatible Lie algebras as a combination of two classical Yang–Baxter equations in Lie algebras. Furthermore, a notion of compatible pre-Lie algebra is introduced with an interpretation of its close relation with the classical Yang–Baxter equation in compatible Lie algebras which leads to a construction of the solutions of the latter. As a byproduct, the compatible Lie bialgebras fit into the framework to construct non-constant solutions of the classical Yang–Baxter equation given by Golubchik and Sokolov. (paper)

Optimizing wavelength choice for quantitative optoacoustic imaging using the Cramer-Rao lower bound

International Nuclear Information System (INIS)

Modgil, Dimple; La Riviere, Patrick J

2010-01-01

Several papers have recently addressed the issue of estimating chromophore concentration in optoacoustic imaging (OAI) using multiple wavelengths. The choice of wavelengths obviously affects the accuracy and precision of the estimates. One might assume that the wavelengths that maximize the extinction coefficients of the chromophores would be the most suitable. However, this may not always be the case since the distribution of light intensity in the medium is also wavelength dependent. In this paper, we explore a method for optimizing the choice of wavelengths based on the Cramer-Rao lower bound (CRLB) on the variance of the chromophore concentration. This lower bound on variance can be evaluated numerically for different wavelengths using the variation of the extinction coefficients and scattering coefficients with wavelength. The wavelengths that give the smallest variance will be considered optimal for multi-wavelength OAI to estimate the chromophore concentrations. The expression for the CRLB has been derived analytically for estimating the concentration of multiple chromophores for several simple phantom models for the case when the optoacoustic signal is proportional to the product of the optical absorption and the illumination function. This approach could be easily extended to other geometries.

Optimizing wavelength choice for quantitative optoacoustic imaging using the Cramer-Rao lower bound.

Science.gov (United States)

Modgil, Dimple; La Riviére, Patrick J

2010-12-07

Several papers have recently addressed the issue of estimating chromophore concentration in optoacoustic imaging (OAI) using multiple wavelengths. The choice of wavelengths obviously affects the accuracy and precision of the estimates. One might assume that the wavelengths that maximize the extinction coefficients of the chromophores would be the most suitable. However, this may not always be the case since the distribution of light intensity in the medium is also wavelength dependent. In this paper, we explore a method for optimizing the choice of wavelengths based on the Cramer-Rao lower bound (CRLB) on the variance of the chromophore concentration. This lower bound on variance can be evaluated numerically for different wavelengths using the variation of the extinction coefficients and scattering coefficients with wavelength. The wavelengths that give the smallest variance will be considered optimal for multi-wavelength OAI to estimate the chromophore concentrations. The expression for the CRLB has been derived analytically for estimating the concentration of multiple chromophores for several simple phantom models for the case when the optoacoustic signal is proportional to the product of the optical absorption and the illumination function. This approach could be easily extended to other geometries.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

Science.gov (United States)

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

Cascaded Mach-Zehnder wavelength filters in silicon photonics for low loss and flat pass-band WDM (de-)multiplexing.

Science.gov (United States)

Horst, Folkert; Green, William M J; Assefa, Solomon; Shank, Steven M; Vlasov, Yurii A; Offrein, Bert Jan

2013-05-20

We present 1-to-8 wavelength (de-)multiplexer devices based on a binary tree of cascaded Mach-Zehnder-like lattice filters, and manufactured using a 90 nm CMOS-integrated silicon photonics technology. We demonstrate that these devices combine a flat pass-band over more than 50% of the channel spacing with low insertion loss of less than 1.6 dB, and have a small device size of approximately 500 × 400 µm. This makes this type of filters well suited for application as WDM (de-)multiplexer in silicon photonics transceivers for optical data communication in large scale computer systems.

Research on Multiple-Split Load Sharing Characteristics of 2-Stage External Meshing Star Gear System in Consideration of Displacement Compatibility

Directory of Open Access Journals (Sweden)

Shuai Mo

2017-01-01

Full Text Available This paper studies the multiple-split load sharing mechanism of gears in two-stage external meshing planetary transmission system of aeroengine. According to the eccentric error, gear tooth thickness error, pitch error, installation error, and bearing manufacturing error, we performed the meshing error analysis of equivalent angles, respectively, and we also considered the floating meshing error caused by the variation of the meshing backlash, which is from the floating of all gears at the same time. Finally, we obtained the comprehensive angle meshing error of the two-stage meshing line, established a refined mathematical computational model of 2-stage external 3-split loading sharing coefficient in consideration of displacement compatibility, got the regular curves of the load sharing coefficient and load sharing characteristic curve of full floating multiple-split and multiple-stage system, and took the variation law of the floating track and the floating quantity of the center wheel. These provide a scientific theory to determine the load sharing coefficient, reasonable load distribution, and control tolerances in aviation design and manufacturing.

CMOS SPDT switch for WLAN applications

International Nuclear Information System (INIS)

Bhuiyan, M A S; Reaz, M B I; Rahman, L F; Minhad, K N

2015-01-01

WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal. (paper)

Cmos spdt switch for wlan applications

Science.gov (United States)

Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

2015-04-01

WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

A piezoresistive cantilever for lateral force detection fabricated by a monolithic post-CMOS process

International Nuclear Information System (INIS)

Ji Xu; Li Zhihong; Li Juan; Wang Yangyuan; Xi Jianzhong

2008-01-01

This paper presents a post-CMOS process to monolithically integrate a piezoresistive cantilever for lateral force detection and signal processing circuitry. The fabrication process includes a standard CMOS process and one more lithography step to micromachine the cantilever structure in the post-CMOS process. The piezoresistors are doped in the CMOS process but defined in the post-CMOS micromachining process without any extra process required. A partially split cantilever configuration is developed for the lateral force detection. The piezoresistors are self-aligned to the split cantilever, and therefore the width of the beam is only limited by lithography. Consequently, this kind of cantilever potentially has a high resolution. The preliminary experimental results show expected performances of the fabricated piezoresistors and electronic circuits

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

Directory of Open Access Journals (Sweden)

Jong-Ryul Yang

2016-03-01

Full Text Available A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

CMOS voltage references an analytical and practical perspective

CERN Document Server

Kok, Chi-Wah

2013-01-01

A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

International Nuclear Information System (INIS)

Estreich, D.B.

1978-11-01

A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

A low-power 802.11 AD compatible 60-GHz phase-locked loop in 65-NM CMOS

KAUST Repository

Cheema, Hammad M.; Arsalan, Muhammad; Salama, Khaled N.; Shamim, Atif

2015-01-01

A 60-GHz fundamental frequency phase locked loop (PLL) as part of a highly integrated system-on-chip transmitter with onchip memory and antenna is presented. As a result of localized optimization approach for each component, the PLL core components only consume 30.2 mW from a 1.2 V supply. A systematic design procedure to achieve high phase margin and wide locking range is presented. The reduction of parasitic and fixed capacitance contributions in the voltage controlled oscillator enables the coverage of the complete 802.11 ad frequency band from 57.2 to 65.8 GHz. A new 4-stage distribution network supplying the local oscillator (LO) signal to the mixer, the feedback loop and the external equipment is introduced. The prescaler based on the static frequency division approach is enhanced using shunt-peaking and asymmetric capacitive loading. The current mode logic based divider chain is optimized for low power and minimum silicon foot-print. A dead-zone free phase frequency detector, low leakage charge pump, and an integrated second-order passive filter completes the feedback loop. The PLL implemented in 65 nm CMOS process occupies only 0.6 mm2 of chip space and has a measured locking range from 56.8 to 66.5 GHz. The reference spurs are lower than -40 dBc and the in-band and out-of-band phase noise is -88.12 dBc/Hz and -117 dBc/Hz, respectively.

A low-power 802.11 AD compatible 60-GHz phase-locked loop in 65-NM CMOS

KAUST Repository

Cheema, Hammad M.

2015-01-23

A 60-GHz fundamental frequency phase locked loop (PLL) as part of a highly integrated system-on-chip transmitter with onchip memory and antenna is presented. As a result of localized optimization approach for each component, the PLL core components only consume 30.2 mW from a 1.2 V supply. A systematic design procedure to achieve high phase margin and wide locking range is presented. The reduction of parasitic and fixed capacitance contributions in the voltage controlled oscillator enables the coverage of the complete 802.11 ad frequency band from 57.2 to 65.8 GHz. A new 4-stage distribution network supplying the local oscillator (LO) signal to the mixer, the feedback loop and the external equipment is introduced. The prescaler based on the static frequency division approach is enhanced using shunt-peaking and asymmetric capacitive loading. The current mode logic based divider chain is optimized for low power and minimum silicon foot-print. A dead-zone free phase frequency detector, low leakage charge pump, and an integrated second-order passive filter completes the feedback loop. The PLL implemented in 65 nm CMOS process occupies only 0.6 mm2 of chip space and has a measured locking range from 56.8 to 66.5 GHz. The reference spurs are lower than -40 dBc and the in-band and out-of-band phase noise is -88.12 dBc/Hz and -117 dBc/Hz, respectively.

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

Science.gov (United States)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

The review of radiation effects of γ total dose in CMOS circuits

International Nuclear Information System (INIS)

Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

1992-01-01

Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

Science.gov (United States)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

An Implantable CMOS Amplifier for Nerve Signals

DEFF Research Database (Denmark)

Nielsen, Jannik Hammel; Lehmann, Torsten

2001-01-01

In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

Latch-up control in CMOS integrated circuits

International Nuclear Information System (INIS)

Ochoa, A. Jr.; Estreich, D.B.; Dawes, W.R. Jr.

1979-01-01

The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed

Laser-Bioplasma Interaction: The Blood Type Transmutation Induced by Multiple Ultrashort Wavelength Laser Beams

Science.gov (United States)

Stefan, V. Alexander

2015-11-01

The interaction of ultrashort wavelength multi laser beams with the flowing blood thin films leads to the transmutation of the blood types A, B, and AB into O type. This is a novel mechanism of importance for the transfusion medicine. Laser radiation is in resonance with the eigen-frequency modes of the antigen proteins and forces the proteins to parametrically oscillate until they get kicked out from the surface. The stripping away of antigens is done by the scanning-multiple-lasers of a high repetition rate in the blue-purple frequency domain. The guiding-lasers are in the red-green frequency domain. The laser force, (parametric interaction with the antigen eigen-oscillation), upon the antigen protein molecule must exceed its weight. The scanning laser beam is partially reflected as long as the antigen(s) is not eliminated. The process of the protein detachment can last a few minutes. Supported by Nikola Tesla Labs., Stefan University.

Monolithic Ge-on-Si lasers for large-scale electronic-photonic integration

Science.gov (United States)

Liu, Jifeng; Kimerling, Lionel C.; Michel, Jurgen

2012-09-01

A silicon-based monolithic laser source has long been envisioned as a key enabling component for large-scale electronic-photonic integration in future generations of high-performance computation and communication systems. In this paper we present a comprehensive review on the development of monolithic Ge-on-Si lasers for this application. Starting with a historical review of light emission from the direct gap transition of Ge dating back to the 1960s, we focus on the rapid progress in band-engineered Ge-on-Si lasers in the past five years after a nearly 30-year gap in this research field. Ge has become an interesting candidate for active devices in Si photonics in the past decade due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS) processing. In 2007, we proposed combing tensile strain with n-type doping to compensate the energy difference between the direct and indirect band gap of Ge, thereby achieving net optical gain for CMOS-compatible diode lasers. Here we systematically present theoretical modeling, material growth methods, spontaneous emission, optical gain, and lasing under optical and electrical pumping from band-engineered Ge-on-Si, culminated by recently demonstrated electrically pumped Ge-on-Si lasers with >1 mW output in the communication wavelength window of 1500-1700 nm. The broad gain spectrum enables on-chip wavelength division multiplexing. A unique feature of band-engineered pseudo-direct gap Ge light emitters is that the emission intensity increases with temperature, exactly opposite to conventional direct gap semiconductor light-emitting devices. This extraordinary thermal anti-quenching behavior greatly facilitates monolithic integration on Si microchips where temperatures can reach up to 80 °C during operation. The same band-engineering approach can be extended to other pseudo-direct gap semiconductors, allowing us to achieve efficient light emission at wavelengths previously

Monolithic Ge-on-Si lasers for large-scale electronic–photonic integration

International Nuclear Information System (INIS)

Liu, Jifeng; Kimerling, Lionel C; Michel, Jurgen

2012-01-01

A silicon-based monolithic laser source has long been envisioned as a key enabling component for large-scale electronic–photonic integration in future generations of high-performance computation and communication systems. In this paper we present a comprehensive review on the development of monolithic Ge-on-Si lasers for this application. Starting with a historical review of light emission from the direct gap transition of Ge dating back to the 1960s, we focus on the rapid progress in band-engineered Ge-on-Si lasers in the past five years after a nearly 30-year gap in this research field. Ge has become an interesting candidate for active devices in Si photonics in the past decade due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS) processing. In 2007, we proposed combing tensile strain with n-type doping to compensate the energy difference between the direct and indirect band gap of Ge, thereby achieving net optical gain for CMOS-compatible diode lasers. Here we systematically present theoretical modeling, material growth methods, spontaneous emission, optical gain, and lasing under optical and electrical pumping from band-engineered Ge-on-Si, culminated by recently demonstrated electrically pumped Ge-on-Si lasers with >1 mW output in the communication wavelength window of 1500–1700 nm. The broad gain spectrum enables on-chip wavelength division multiplexing. A unique feature of band-engineered pseudo-direct gap Ge light emitters is that the emission intensity increases with temperature, exactly opposite to conventional direct gap semiconductor light-emitting devices. This extraordinary thermal anti-quenching behavior greatly facilitates monolithic integration on Si microchips where temperatures can reach up to 80 °C during operation. The same band-engineering approach can be extended to other pseudo-direct gap semiconductors, allowing us to achieve efficient light emission at wavelengths previously

Interference with a quantum dot single-photon source and a laser at telecom wavelength

Energy Technology Data Exchange (ETDEWEB)

Felle, M. [Toshiba Research Europe Limited, Cambridge Research Laboratory, 208 Cambridge Science Park, Milton Road, Cambridge CB4 0GZ (United Kingdom); Centre for Advanced Photonics and Electronics, University of Cambridge, J.J. Thomson Avenue, Cambridge CB3 0FA (United Kingdom); Huwer, J., E-mail: jan.huwer@crl.toshiba.co.uk; Stevenson, R. M.; Skiba-Szymanska, J.; Ward, M. B.; Shields, A. J. [Toshiba Research Europe Limited, Cambridge Research Laboratory, 208 Cambridge Science Park, Milton Road, Cambridge CB4 0GZ (United Kingdom); Farrer, I.; Ritchie, D. A. [Cavendish Laboratory, University of Cambridge, J.J. Thomson Avenue, Cambridge CB3 0HE (United Kingdom); Penty, R. V. [Centre for Advanced Photonics and Electronics, University of Cambridge, J.J. Thomson Avenue, Cambridge CB3 0FA (United Kingdom)

2015-09-28

The interference of photons emitted by dissimilar sources is an essential requirement for a wide range of photonic quantum information applications. Many of these applications are in quantum communications and need to operate at standard telecommunication wavelengths to minimize the impact of photon losses and be compatible with existing infrastructure. Here, we demonstrate for the first time the quantum interference of telecom-wavelength photons from an InAs/GaAs quantum dot single-photon source and a laser; an important step towards such applications. The results are in good agreement with a theoretical model, indicating a high degree of indistinguishability for the interfering photons.

Interference with a quantum dot single-photon source and a laser at telecom wavelength

International Nuclear Information System (INIS)

Felle, M.; Huwer, J.; Stevenson, R. M.; Skiba-Szymanska, J.; Ward, M. B.; Shields, A. J.; Farrer, I.; Ritchie, D. A.; Penty, R. V.

2015-01-01

The interference of photons emitted by dissimilar sources is an essential requirement for a wide range of photonic quantum information applications. Many of these applications are in quantum communications and need to operate at standard telecommunication wavelengths to minimize the impact of photon losses and be compatible with existing infrastructure. Here, we demonstrate for the first time the quantum interference of telecom-wavelength photons from an InAs/GaAs quantum dot single-photon source and a laser; an important step towards such applications. The results are in good agreement with a theoretical model, indicating a high degree of indistinguishability for the interfering photons

A novel CMOS SRAM feedback element for SEU environments

International Nuclear Information System (INIS)

Verghese, S.; Wortman, J.J.; Kerns, S.E.

1987-01-01

A hardened CMOS SRAM has been proposed which utilizes a leaky polysilicon Schottky diode placed in the feedback path to attain the SEU immunity of resistor-coupled SRAMs while improving the access speed of the cell. Novel polysilicon hybrid Schottky-resistor structures which emulate the leaky diodes have been designed and fabricated. The elements' design criteria and methods of fulfilling them are presented along with a practical implementation scheme for CMOS SRAM cells

Materials Characterization of CIGS solar cells on Top of CMOS chips

NARCIS (Netherlands)

Lu, J.; Liu, W.; Kovalgin, A.Y.; Sun, Y.; Schmitz, J.; Venkatasubramanian, R.; Radousky, H.; Liang, H.

2011-01-01

In the current work, we present a detailed study on the material properties of the CIGS layers, fabricated on top of the CMOS chips, and compare the results with the fabrication on standard glass substrates. Almost identical elemental composition on both glass and CMOS chips (within measurement

Radiation imaging detectors made by wafer post-processing of CMOS chips

NARCIS (Netherlands)

Blanco Carballo, V.M.

2009-01-01

In this thesis several wafer post-processing steps have been applied to CMOS chips. Amplification gas strucutures are built on top of the microchips. A complete radiation imaging detector is obtained this way. Integrated Micromegas-like and GEM-like structures were fabricated on top of Timepix CMOS

Two CMOS BGR using CM and DTMOST techniques

International Nuclear Information System (INIS)

Mohd-Yasin, F.; Teh, Y.K.; Choong, F.; Reaz, M.B.I.

2009-06-01

Two CMOS BGR using current mode (0.044mm 2 ) and Dynamic Threshold MOST (0.017mm 2 ) techniques are designed on CMOS 0.18μm process. On-wafer measurement shows both circuits have minimum operating V DD 1.28V at 25 o C; taking 2.1μA and 0.5μA (maximum current 3.1μA and 1.1μA) and output voltage of 514mV and 457mV. Both circuits could support V DD range up to 4V required by passive UHF RFID. (author)

A CMOS silicon spin qubit

Science.gov (United States)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Analog filters in nanometer CMOS

CERN Document Server

Uhrmann, Heimo; Zimmermann, Horst

2014-01-01

Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors

International Nuclear Information System (INIS)

Kobayashi, T; Okada, H; Maeda, R; Itoh, T; Masuda, T

2011-01-01

The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal–oxide–semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO 2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s −2 as digital outputs of 111, 110, 100, and 000, respectively

Effect of beat noise on the performance of two-dimensional time-spreading/wavelength-hopping optical code-division multiple-access systems

Science.gov (United States)

Bazan, T.; Harle, D.; Andonovic, I.; Meenakshi, M.

2005-03-01

The effect of beat noise on optical code-division multiple-access (OCDMA) systems using a range of two-dimensional (2-D) time-spreading/wavelength-hopping (TW) code families is presented. A derivation of a general formula for the error probability of the system is given. The properties of the 2-D codes--namely, the structure, length, and cross-correlation characteristics--are found to have a great influence on system performance. Improved performance can be obtained by use of real-time dynamic thresholding.

Simple BiCMOS CCCTA design and resistorless analog function realization.

Science.gov (United States)

Tangsrirat, Worapong

2014-01-01

The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

Simple BiCMOS CCCTA Design and Resistorless Analog Function Realization

Directory of Open Access Journals (Sweden)

Worapong Tangsrirat

2014-01-01

Full Text Available The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (Rx and current transfer (io/iz, are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

An Ultra-Efficient Nonlinear Platform: AlGaAs-On-Insulator

DEFF Research Database (Denmark)

Pu, Minhao; Ottaviano, Luisa; Semenova, Elizaveta

The combination of nonlinear and integrated photonics enables applications including optical signal processing, multi-wavelength lasers, metrology, spectroscopy, and quantum information science. Silicon-on-insulator (SOI) has emerged as a promising platform [1, 2] due to its high material...... nonlinearity and its compatibility with the CMOS industry. However, silicon suffers two-photon absorption (TPA) in the telecommunication wavelength band around 1.55 µm, which hampers its applications. Different platforms have been proposed to avoid TPA in the telecom wavelength range such as Si3N4 and Hydex [3...... a nonlinear index (n2) on the order of 10−17 W/m2 and a high refractive index (n ≈3.3), a large transparency window (from near- to mid-infrared), and the ability to engineer the material bandgap to mitigate TPA [5]. In this presentation, we introduce AlGaAson-insulator (AlGaAsOI) platform which combines both...

Designing a ring-VCO for RFID transponders in 0.18 μm CMOS process.

Science.gov (United States)

Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 μm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5-2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of -126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

Long wavelength limit of evolution of nonlinear cosmological perturbations

International Nuclear Information System (INIS)

Hamazaki, Takashi

2008-01-01

In the general matter composition where the multiple scalar fields and the multiple perfect fluids coexist, in the leading order of the gradient expansion, we construct all of the solutions of the nonlinear evolutions of the locally homogeneous universe. From the momentum constraint, we derive the constraints which the solution constants of the locally homogeneous universe must satisfy. We construct the gauge invariant perturbation variables in the arbitrarily higher order nonlinear cosmological perturbation theory around the spatially flat Friedmann-Robertson-Walker universe. We construct the nonlinear long wavelength limit formula representing the long wavelength limit of the evolution of the nonlinear gauge invariant perturbation variables in terms of perturbations of the evolutions of the locally homogeneous universe. By using the long wavelength limit formula, we investigate the evolution of nonlinear cosmological perturbations in the universe dominated by the multiple slow rolling scalar fields with an arbitrary potential. The τ function and the N potential introduced in this paper make it possible to write the evolution of the multiple slow rolling scalar fields with an arbitrary interaction potential and the arbitrarily higher order nonlinear Bardeen parameter at the end of the slow rolling phase analytically. It is shown that the nonlinear parameters such as f NL and g NL are suppressed by the slow rolling expansion parameters.

Latch-up in CMOS integrated circuits

International Nuclear Information System (INIS)

Estreich, D.B.; Dutton, R.W.

1978-04-01

An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

Energy Technology Data Exchange (ETDEWEB)

Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

2000-08-10

In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

DEFF Research Database (Denmark)

Olesen, Ole

circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

A CMOS Humidity Sensor for Passive RFID Sensing Applications

Directory of Open Access Journals (Sweden)

Fangming Deng

2014-05-01

Full Text Available This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

A CMOS Humidity Sensor for Passive RFID Sensing Applications

Science.gov (United States)

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-01-01

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

A CMOS humidity sensor for passive RFID sensing applications.

Science.gov (United States)

Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

2014-05-16

This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

CMOS cassette for digital upgrade of film-based mammography systems

Science.gov (United States)

Baysal, Mehmet A.; Toker, Emre

2006-03-01

While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

Desenvolvimento de uma matriz de portas CMOS

OpenAIRE

Jose Geraldo Mendes Taveira

1991-01-01

Resumo: É apresentado o projeto de uma matriz deportas CMOS. O capítulo 11 descreve as etapas de projeto, incluindo desde a escolha da topologia das células internas e de interface, o projeto e a simulação elétrica, até a geração do lay-out. Ocaprtulo III apresenta o projeto dos circuitos de aplicação, incluídos para permitir a validação da matriz. Os circuitos de apl icação são : Oscilador em anel e comparador de códigos. A matriz foi difundida no Primeiro Projeto Multi-Usuário CMOS Brasile...

CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

International Nuclear Information System (INIS)

Ginet, Patrick; Akiyama, Sho; Takama, Nobuyuki; Fujita, Hiroyuki; Kim, Beomjoon

2011-01-01

Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL −1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

Science.gov (United States)

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

Feasibility Study of Multi-Wavelength Differential Absorption LIDAR for CO2 Monitoring

Directory of Open Access Journals (Sweden)

Chengzhi Xiang

2016-06-01

Full Text Available To obtain a better understanding of carbon cycle and accurate climate prediction models, highly accurate and temporal resolution observation of atmospheric CO2 is necessary. Differential absorption LIDAR (DIAL remote sensing is a promising technology to detect atmospheric CO2. However, the traditional DIAL system is the dual-wavelength DIAL (DW-DIAL, which has strict requirements for wavelength accuracy and stability. Moreover, for on-line and off-line wavelengths, the system’s optical efficiency and the change of atmospheric parameters are assumed to be the same in the DW-DIAL system. This assumption inevitably produces measurement errors, especially under rapid aerosol changes. In this study, a multi-wavelength DIAL (MW-DIAL is proposed to map atmospheric CO2 concentration. The MW-DIAL conducts inversion with one on-line and multiple off-line wavelengths. Multiple concentrations of CO2 are then obtained through difference processing between the single on-line and each of the off-line wavelengths. In addition, the least square method is adopted to optimize inversion results. Consequently, the inversion concentration of CO2 in the MW-DIAL system is found to be the weighted average of the multiple concentrations. Simulation analysis and laboratory experiments were conducted to evaluate the inversion precision of MW-DIAL. For comparison, traditional DW-DIAL simulations were also conducted. Simulation analysis demonstrated that, given the drifting wavelengths of the laser, the detection accuracy of CO2 when using MW-DIAL is higher than that when using DW-DIAL, especially when the drift is large. A laboratory experiment was also performed to verify the simulation analysis.

The impact transconductance parameter and threshold voltage of MOSFET’s in static characteristics of CMOS inverter

Directory of Open Access Journals (Sweden)

Milaim Zabeli

2017-11-01

Full Text Available The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors in the CMOS inverter for static mode of operation. In addition to this, the paper also aims at exploring the directives that are to be followed during the design phase of the CMOS inverters that enable designers to design the CMOS inverters with the best possible performance, depending on operation conditions. The CMOS inverter designed with the best possible features also enables the designing of the CMOS logic circuits with the best possible performance, according to the operation conditions and designers’ requirements.

High-quality asynchronous heralded single-photon source at telecom wavelength

International Nuclear Information System (INIS)

Fasel, Sylvain; Alibart, Olivier; Tanzilli, Sebastien; Baldi, Pascal; Beveratos, Alexios; Gisin, Nicolas; Zbinden, Hugo

2004-01-01

We report on the experimental realization and characterization of an asynchronous heralded single-photon source based on spontaneous parametric down-conversion. Photons at 1550 nm are heralded as being inside a single-mode fibre with more than 60% probability, and the multi-photon emission probability is reduced by a factor of up to more than 500 compared to Poissonian light sources. These figures of merit, together with the choice of telecom wavelength for the heralded photons, are compatible with practical applications needing very efficient and robust single-photon sources

Incentive Compatibility

OpenAIRE

Ledyard, John O.

1987-01-01

Incentive compatibility is described and discussed. A summary of the current state of understanding is provided. Key words are: incentive compatibility, game theory, implementation, mechanism, Bayes, Nash, and revelation.

Improved Space Object Orbit Determination Using CMOS Detectors

Science.gov (United States)

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

A Fully Integrated Dual-Channel On-Coil CMOS Receiver for Array Coils in 1.5-10.5 T MRI.

Science.gov (United States)

Sporrer, Benjamin; Wu, Lianbo; Bettini, Luca; Vogt, Christian; Reber, Jonas; Marjanovic, Josip; Burger, Thomas; Brunner, David O; Pruessmann, Klaas P; Troster, Gerhard; Huang, Qiuting

2017-12-01

Magnetic resonance imaging (MRI) is among the most important medical imaging modalities. Coil arrays and receivers with high channel counts (16 and more) have to be deployed to obtain the image quality and acquisition speed required by modern clinical protocols. In this paper, we report the theoretical analysis, the system-level design, and the circuit implementation of the first receiver IC (RXIC) for clinical MRI fully integrated in a modern CMOS technology. The dual-channel RXIC sits directly on the sensor coil, thus eliminating any RF cable otherwise required to transport the information out of the magnetic field. The first stage LNA was implemented using a noise-canceling architecture providing a highly reflective input used to decouple the individual channels of the array. Digitization is performed directly on-chip at base-band by means of a delta-sigma modulator, allowing the subsequent optical transmission of data. The presented receiver, implemented in a CMOS technology, is compatible with MRI scanners up to . It reaches sub- noise figure for MRI units and features a dynamic range up to at a power consumption below per channel, with an area occupation of . Mounted on a small-sized printed circuit board (PCB), the receiver IC has been employed in a commercial MRI scanner to acquire in-vivo images matching the quality of traditional systems, demonstrating the first step toward multichannel wearable MRI array coils.

Low-voltage CMOS operational amplifiers theory, design and implementation

CERN Document Server

Sakurai, Satoshi

1995-01-01

Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

Multi-target electrochemical biosensing enabled by integrated CMOS electronics

International Nuclear Information System (INIS)

Rothe, J; Lewandowska, M K; Heer, F; Frey, O; Hierlemann, A

2011-01-01

An integrated electrochemical measurement system, based on CMOS technology, is presented, which allows the detection of several analytes in parallel (multi-analyte) and enables simultaneous monitoring at different locations (multi-site). The system comprises a 576-electrode CMOS sensor chip, an FPGA module for chip control and data processing, and the measurement laptop. The advantages of the highly versatile system are demonstrated by two applications. First, a label-free, hybridization-based DNA sensor is enabled by the possibility of large-scale integration in CMOS technology. Second, the detection of the neurotransmitter choline is presented by assembling the chip with biosensor microprobe arrays. The low noise level enables a limit of detection of, e.g., 0.3 µM choline. The fully integrated system is self-contained: it features cleaning, functionalization and measurement functions without the need for additional electrical equipment. With the power supplied by the laptop, the system is very suitable for on-site measurements

A scalable neural chip with synaptic electronics using CMOS integrated memristors

International Nuclear Information System (INIS)

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-01-01

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

Science.gov (United States)

Seco, Joao; Depauw, Nicolas

2011-02-01

Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The

CMOS Imaging of Pin-Printed Xerogel-Based Luminescent Sensor Microarrays.

Science.gov (United States)

Yao, Lei; Yung, Ka Yi; Khan, Rifat; Chodavarapu, Vamsy P; Bright, Frank V

2010-12-01

We present the design and implementation of a luminescence-based miniaturized multisensor system using pin-printed xerogel materials which act as host media for chemical recognition elements. We developed a CMOS imager integrated circuit (IC) to image the luminescence response of the xerogel-based sensor array. The imager IC uses a 26 × 20 (520 elements) array of active pixel sensors and each active pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. The imager includes a correlated double sampling circuit and pixel address/digital control circuit; the image data is read-out as coded serial signal. The sensor system uses a light-emitting diode (LED) to excite the target analyte responsive luminophores doped within discrete xerogel-based sensor elements. As a prototype, we developed a 4 × 4 (16 elements) array of oxygen (O 2 ) sensors. Each group of 4 sensor elements in the array (arranged in a row) is designed to provide a different and specific sensitivity to the target gaseous O 2 concentration. This property of multiple sensitivities is achieved by using a strategic mix of two oxygen sensitive luminophores ([Ru(dpp) 3 ] 2+ and ([Ru(bpy) 3 ] 2+ ) in each pin-printed xerogel sensor element. The CMOS imager consumes an average power of 8 mW operating at 1 kHz sampling frequency driven at 5 V. The developed prototype system demonstrates a low cost and miniaturized luminescence multisensor system.

77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

Science.gov (United States)

2012-05-07

... INTERNATIONAL TRADE COMMISSION [Docket No. 2895] Certain CMOS Image Sensors and Products.... International Trade Commission has received a complaint entitled Certain CMOS Image Sensors and Products... importation, and the sale within the United States after importation of certain CMOS image sensors and...

Above-CMOS a-Si and CIGS Solar Cells for Powering Autonomous Microsystems

NARCIS (Netherlands)

Lu, J.; Liu, W.; van der Werf, C.H.M.; Kovalgin, A.Y.; Sun, Y.; Schropp, R.E.I.; Schmitz, J.

2010-01-01

Two types of solar cells are successfully grown on chips from two CMOS generations. The efficiency of amorphous-silicon (a-Si) solar cells reaches 5.2%, copperindium-gallium-selenide (CIGS) cells 7.1%. CMOS functionality is unaffected. The main integration issues: adhesion, surface topography, metal

CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

Directory of Open Access Journals (Sweden)

Nan Guo

2014-10-01

Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

Science.gov (United States)

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

Science.gov (United States)

Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

2017-05-01

In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

CERN Document Server

Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

2014-01-01

CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

A 205GHz Amplifier in 90nm CMOS Technology

Science.gov (United States)

2017-03-01

10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...other advantages, such as low- cost , reliability, and mixed-mode analog/digital chips, intensifying its usage in the mm-wave band [5]. CMOS has several... disadvantages at the higher frequency range with the worst case scenario happening when the device operates near its fmax. This is chiefly due to

An introduction to deep submicron CMOS for vertex applications

CERN Document Server

Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

2001-01-01

Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

Linear CMOS RF power amplifiers a complete design workflow

CERN Document Server

Ruiz, Hector Solar

2013-01-01

The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

Science.gov (United States)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Research-grade CMOS image sensors for demanding space applications

Science.gov (United States)

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2017-11-01

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

Development of CMOS Imager Block for Capsule Endoscope

International Nuclear Information System (INIS)

Shafie, S; Fodzi, F A M; Tung, L Q; Lioe, D X; Halin, I A; Hasan, W Z W; Jaafar, H

2014-01-01

This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5 V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5 V to 3.3 V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5 V to 3.3 V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier

OpenAIRE

Hassan Jassim Motlak

2015-01-01

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to...

Determination of the zero in the Two theta angle and the wavelength in the neutron diffractometer for the Cyber computer of the ININ and for the IBM compatible microcomputers; Determinacion del cero en el angulo Dos teta y la longitud de onda en el difractometro de neutrones para la computadora Cyber del ININ y para microcomputadoras compatibles con IBM

Energy Technology Data Exchange (ETDEWEB)

Macias B, L R

1991-05-15

The objective of this work consists on determining the calibration in the angular parameters and the neutron wavelength used in the neutron diffractometer of the TRIGA Mark III reactor, through some readings in that a well-known sample is used by means of a Fortran computer program that is used in the CYBER computer of the ININ in Mexico, and/or in micro computers compatible with IBM. The program was also designed to determine the zero of the 2 {theta} angle of the goniometer of the diffractometer. The generated data were proven by means of well-known data of the Powder Diffraction File of the Joint Committee on Powder Diffraction Standards (JCPDS). (Author)

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

Science.gov (United States)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

CMOS technology: a critical enabler for free-form electronics-based killer applications

Science.gov (United States)

Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

2016-05-01

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

Multiple-wavelength Variability and Quasi-periodic Oscillation of PMN J0948+0022

Energy Technology Data Exchange (ETDEWEB)

Zhang, Jin [Key Laboratory of Space Astronomy and Technology, National Astronomical Observatories, Chinese Academy of Sciences, Beijing 100012 (China); Zhang, Hai-Ming; Zhu, Yong-Kai; Lu, Rui-Jing; Liang, En-Wei [Guangxi Key Laboratory for Relativistic Astrophysics, Department of Physics, Guangxi University, Nanning 530004 (China); Yi, Ting-Feng [Department of Physics, Yunnan Normal University, Kunming 650500 (China); Yao, Su, E-mail: jinzhang@bao.ac.cn [Kavli Institute for Astronomy and Astrophysics, Peking University, Beijing 100871 (China)

2017-11-01

We present a comprehensive analysis of multiple-wavelength observational data of the first GeV-selected narrow-line Seyfert 1 galaxy PMN J0948+0022. We derive its light curves in the γ -ray and X-ray bands from the data observed with Fermi /LAT and Swift /XRT, and generate the optical and radio light curves by collecting the data from the literature. These light curves show significant flux variations. With the LAT data we show that this source is analogous to typical flat spectrum radio quasars in the L {sub γ} –Γ {sub γ} plane, where L {sub γ} and Γ {sub γ} are the luminosity and spectral index in the LAT energy band. The γ -ray flux is correlated with the V-band flux with a lag of ∼44 days, and a moderate quasi-periodic oscillation (QPO) with a periodicity of ∼490 days observed in the LAT light curve. A similar QPO signature is also found in the V-band light curve. The γ -ray flux is not correlated with the radio flux in 15 GHz, and no similar QPO signature is found at a confidence level of 95%. Possible mechanisms of the QPO are discussed. We propose that gravitational-wave observations in the future may clarify the current plausible models for the QPO.

Analysis of the resistive network in a bio-inspired CMOS vision chip

Science.gov (United States)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

CMOS VHF transconductance-C lowpass filter

NARCIS (Netherlands)

Nauta, Bram

1990-01-01

Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response

Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

International Nuclear Information System (INIS)

Cheng, Chao-Lin; Fang, Weileun; Tsai, Ming-Han

2015-01-01

Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli. (paper)

77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

Science.gov (United States)

2012-12-14

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-846] Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations, Modifications and Rulings AGENCY: U.S... United States after importation of certain CMOS image sensors and products containing the same based on...

Performance simulation and analysis of a CMOS/nano hybrid nanoprocessor system

International Nuclear Information System (INIS)

Cabe, Adam C; Das, Shamik

2009-01-01

This paper provides detailed simulation results and analysis of the prospective performance of hybrid CMOS/nanoelectronic processor systems based upon the field-programmable nanowire interconnect (FPNI) architecture. To evaluate this architecture, a complete design was developed for an FPNI implementation using 90 nm CMOS with 15 nm wide nanowire interconnects. Detailed simulations of this design illustrate that critical design choices and tradeoffs exist beyond those specified by the architecture. This includes the selection of the types of junction nanodevices, as well as the implementation of low-level circuits. In particular, the simulation results presented here show that only nanodevices with an 'on/off' current ratio of 200 or more are suitable to produce correct system-level behaviour. Furthermore, the design of the CMOS logic gates in the FPNI system must be customized to accommodate the resistances of both 'on'-state and 'off'-state nanodevices. Using these customized designs together with models of suitable nanodevices, additional simulations demonstrate that, relative to conventional 90 nm CMOS FPGA systems, performance gains can be obtained of up to 70% greater speed or up to a ninefold reduction in energy consumption.

Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

Science.gov (United States)

Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

2013-03-06

The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

CMOS analog integrated circuits high-speed and power-efficient design

CERN Document Server

Ndjountche, Tertulien

2011-01-01

High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

All-silicon-based nano-antennas for wavelength and polarization demultiplexing.

Science.gov (United States)

Panmai, Mingcheng; Xiang, Jin; Sun, Zhibo; Peng, Yuanyuan; Liu, Hongfeng; Liu, Haiying; Dai, Qiaofeng; Tie, Shaolong; Lan, Sheng

2018-05-14

We propose an all-silicon-based nano-antenna that functions as not only a wavelength demultiplexer but also a polarization one. The nano-antenna is composed of two silicon cuboids with the same length and height but with different widths. The asymmetric structure of the nano-antenna with respect to the electric field of the incident light induced an electric dipole component in the propagation direction of the incident light. The interference between this electric dipole and the magnetic dipole induced by the magnetic field parallel to the long side of the cuboids is exploited to manipulate the radiation direction of the nano-antenna. The radiation direction of the nano-antenna at a certain wavelength depends strongly on the phase difference between the electric and magnetic dipoles interacting coherently, offering us the opportunity to realize wavelength demultiplexing. By varying the polarization of the incident light, the interference of the magnetic dipole induced by the asymmetry of the nano-antenna and the electric dipole induced by the electric field parallel to the long side of the cuboids can also be used to realize polarization demultiplexing in a certain wavelength range. More interestingly, the interference between the dipole and quadrupole modes of the nano-antenna can be utilized to shape the radiation directivity of the nano-antenna. We demonstrate numerically that radiation with adjustable direction and high directivity can be realized in such a nano-antenna which is compatible with the current fabrication technology of silicon chips.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

Science.gov (United States)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

RF Circuit Design in Nanometer CMOS

NARCIS (Netherlands)

Nauta, Bram

2007-01-01

With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

Science.gov (United States)

Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

2005-04-01

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs

Directory of Open Access Journals (Sweden)

Maxim Adrian

2006-01-01

Full Text Available This paper presents circuit techniques and power supply partitioning, filtering, and regulation methods aimed at reducing the phase noise and spurious tones in frequency synthesizers operating in large mixed analog-digital system-on-chip (SOC. The different noise and spur coupling mechanisms are presented together with solutions to minimize their impact on the overall PLL phase noise performance. Challenges specific to deep-submicron CMOS integration of multi-GHz PLLs are revealed, while new architectures that address these issues are presented. Layout techniques that help reducing the parasitic noise and spur coupling between digital and analog blocks are described. Combining system-level and circuit-level low noise design methods, low phase noise frequency synthesizers were achieved which are compatible with the demanding nowadays wireless communication standards.

A Biologically Inspired CMOS Image Sensor

CERN Document Server

Sarkar, Mukul

2013-01-01

Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

Science.gov (United States)

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

CMOS technology: a critical enabler for free-form electronics-based killer applications

KAUST Repository

Hussain, Muhammad Mustafa

2016-05-17

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

Two-dimensional optical simulation on a visible ray passing through inter-metal dielectric layers of CMOS image sensor device

International Nuclear Information System (INIS)

Lee, Wan-Gyu; Kim, Jun-Seok; Kim, Hee-Jeen; Kim, Sang-Young; Hwang, Sung-Bo; Lee, Jeong-Gun

2005-01-01

Two-dimensional optical simulation has been performed for investigating light propagation through a micro lens and inter-metal dielectric (IMD) layers in an Al and Cu back-end of line (BEOL) onto a Si photodiode, and its effects on the wave power, as well as optical carriers generated by a visible ray in the silicon substrate area, i.e. photodiode of a CMOS image sensor pixel. The number of optically generated carriers in an Al-BEOL has been compared to a Cu-BEOL. It is shown that more optical carriers are generated in the Cu-BEOL for the red color because a higher permittivity dielectric material like SiC is used in the Cu-BEOL to prevent Cu from diffusing into the dielectric material, resulting in higher optical loss in the higher- permittivity dielectric layers. Thus, the optical power density arriving in the silicon substrate is higher in the Al-BEOL than in the Cu-BEOL when the wavelength is blue (470 nm) or green (550 nm) in the visible ray spectrum. In conclusion, the structure of a Cu-BEOL in a CMOS image sensor has to be optimized for generating more optical carriers through lower-permittivity IMD materials or by reducing the permittivity difference between SiC (or SiN) and IMD materials, without deteriorating the capability as a barrier to Cu diffusion.

Power Amplifiers in CMOS Technology: A contribution to power amplifier theory and techniques

NARCIS (Netherlands)

Acar, M.

2011-01-01

In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers in the mainstream CMOS technology is essential. In general, CMOS Power Amplifiers (PAs) require high voltage to decrease the matching network losses and for high

Nanocantilever based mass sensor integrated with cmos circuitry

DEFF Research Database (Denmark)

Davis, Zachary James; Abadal, G.; Campabadal, F.

2003-01-01

We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... of the mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The design of the readout circuitry used for the first electrical characterization of an integrated cantilever...... with CMOS circuitry is demonstrated. The electrical characterization of the device shows that the resonant behavior of the cantilever depends on the applied voltages, which corresponds to theory....

Optimization Design Method for the CMOS-type Capacitive Micro-Machined Ultrasonic Transducer

Directory of Open Access Journals (Sweden)

D. Y. Chiou

2011-12-01

Full Text Available In this study, an integrated modeling technique for characterization and optimization design of the complementary metal-oxide-semiconductor (CMOS capacitive micro-arrayed ultrasonic transducer (pCMOS-CMUT is presented. Electromechanical finite element simulations are performed to investigate its operational characteristics, such as the collapse voltage and the resonant frequency. Both the numerical and experimental results are in good agreement. In order to simultaneously customize the resonant frequency and minimize the collapse voltage, the genetic algorithm (GA is applied to optimize dimensional parameters of the transducer. From the present results, it is concluded that the FE/GA coupling approach provides another efficient numerical tool for multi-objective design of the pCMOS-CMUT.

Single Photon Counting Performance and Noise Analysis of CMOS SPAD-Based Image Sensors

Science.gov (United States)

Dutton, Neale A. W.; Gyongy, Istvan; Parmesan, Luca; Henderson, Robert K.

2016-01-01

SPAD-based solid state CMOS image sensors utilising analogue integrators have attained deep sub-electron read noise (DSERN) permitting single photon counting (SPC) imaging. A new method is proposed to determine the read noise in DSERN image sensors by evaluating the peak separation and width (PSW) of single photon peaks in a photon counting histogram (PCH). The technique is used to identify and analyse cumulative noise in analogue integrating SPC SPAD-based pixels. The DSERN of our SPAD image sensor is exploited to confirm recent multi-photon threshold quanta image sensor (QIS) theory. Finally, various single and multiple photon spatio-temporal oversampling techniques are reviewed. PMID:27447643

Long-wavelength photonic integrated circuits and avalanche photodetectors

Science.gov (United States)

Tsou, Yi-Jen D.; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

2001-10-01

Fast-growing internet traffic volume require high data communication bandwidth over longer distances. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low-cost, high-speed laser modules at 1310 to 1550 nm wavelengths and avalanche photodetectors are required. The great success of GaAs 850nm VCSEls for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits (PICs), which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform of InP-based PICs compatible with surface-emitting laser technology, as well as a high data rate externally modulated laser module. Avalanche photodetectors (APDs) are the key component in the receiver to achieve high data rate over long transmission distance because of their high sensitivity and large gain- bandwidth product. We have used wafer fusion technology to achieve In

Radiation hardness of CMOS monolithic active pixel sensors manufactured in a 0.18 μm CMOS process

Energy Technology Data Exchange (ETDEWEB)

Linnik, Benjamin [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

2015-07-01

CMOS Monolithic Active Pixels Sensors (MAPS) are considered as the technology of choice for various vertex detectors in particle and heavy-ion physics including the STAR HFT, the upgrade of the ALICE ITS, the future ILC detectors and the CBM experiment at FAIR. To match the requirements of those detectors, their hardness to radiation is being improved, among others in a joined research activity of the Goethe University Frankfurt and the IPHC Strasbourg. It was assumed that combining an improved high resistivity (1-8 kΩcm) sensitive medium with the features of a 0.18 μm CMOS process, is suited to reach substantial improvements in terms of radiation hardness as compared to earlier sensor designs. This strategy was tested with a novel generation of sensor prototypes named MIMOSA-32 and MIMOSA-34. We show results on the radiation hardness of those sensors and discuss its impact on the design of future vertex detectors.

Nanosecond-laser induced crosstalk of CMOS image sensor

Science.gov (United States)

Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

2018-02-01

The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications

CERN Document Server

Aznar, Francisco; Calvo Lopez, Belén

2013-01-01

This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints.  These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip.  The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length.  This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level. Reviews optical communications, including long-haul transmission systems and emerging applications focused on short-range; Explains necessary fundamentals, such as characteristics of a data signal, system requirements affecting receiver design and key par...

From vertex detectors to inner trackers with CMOS pixel sensors

CERN Document Server

Besson, A.

2017-01-01

The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

Designing a robust high-speed CMOS-MEMS capacitive humidity sensor

International Nuclear Information System (INIS)

Lazarus, N; Fedder, G K

2012-01-01

In our previous work (Lazarus and Fedder 2011 J. Micromech. Microeng. 21 0650281), we demonstrated a CMOS-MEMS capacitive humidity sensor with a 72% improvement in sensitivity over the highest previously integrated on a CMOS die. This paper explores a series of methods for creating a faster and more manufacturable high-sensitivity capacitive humidity sensor. These techniques include adding oxide pillars to hold the plates apart, spin coating polymer to allow sensors to be fabricated more cheaply, adding a polysilicon heater and etching away excess polymer in the release holes. In most cases a tradeoff was found between sensitivity and other factors such as response time or robustness. A robust high-speed sensor was designed with a sensitivity of 0.21% change in capacitance per per cent relative humidity, while dropping the response time constant from 70 to 4s. Although less sensitive than our design, the sensor remains 17% more sensitive than the most sensitive interdigitated designs successfully integrated with CMOS. (paper)

Wavelength-Hopping Time-Spreading Optical CDMA With Bipolar Codes

Science.gov (United States)

Kwong, Wing C.; Yang, Guu-Chang; Chang, Cheng-Yuan

2005-01-01

Two-dimensional wavelength-hopping time-spreading coding schemes have been studied recently for supporting greater numbers of subscribers and simultaneous users than conventional one-dimensional approaches in optical code-division multiple-access (OCDMA) systems. To further improve both numbers without sacrificing performance, a new code design utilizing bipolar codes for both wavelength hopping and time spreading is studied and analyzed in this paper. A rapidly programmable, integratable hardware design for this new coding scheme, based on arrayed-waveguide gratings, is also discussed.

Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

Science.gov (United States)

Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

2016-01-01

In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

Development of a lens-coupled CMOS detector for an X-ray inspection system

International Nuclear Information System (INIS)

Kim, Ho Kyung; Ahn, Jung Keun; Cho, Gyuseong

2005-01-01

A digital X-ray imaging detector based on a complementary metal-oxide-semiconductor (CMOS) image sensor has been developed for X-ray non-destructive inspection applications. This is a cost-effective solution because of the availability of cheap commercial standard CMOS image sensors. The detector configuration adopts an indirect X-ray detection method by using scintillation material and lens assembly. As a feasibility test of the developed lens-coupled CMOS detector as an X-ray inspection system, we have acquired X-ray projection images under a variety of imaging conditions. The results show that the projected image is reasonably acceptable in typical non-destructive testing (NDT). However, the developed detector may not be appropriate for laminography due to a low light-collection efficiency of lens assembly. In this paper, construction of the lens-coupled CMOS detector and its specifications are described, and the experimental results are presented. Using the analysis of quantum accounting diagram, inefficiency of the lens-coupling method is discussed

Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

NARCIS (Netherlands)

Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

2011-01-01

We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

Monolithic CMOS imaging x-ray spectrometers

Science.gov (United States)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

Site-Controlled Growth of Monolithic InGaAs/InP Quantum Well Nanopillar Lasers on Silicon.

Science.gov (United States)

Schuster, Fabian; Kapraun, Jonas; Malheiros-Silveira, Gilliard N; Deshpande, Saniya; Chang-Hasnain, Connie J

2017-04-12

In this Letter, we report the site-controlled growth of InP nanolasers on a silicon substrate with patterned SiO 2 nanomasks by low-temperature metal-organic chemical vapor deposition, compatible with silicon complementary metal-oxide-semiconductor (CMOS) post-processing. A two-step growth procedure is presented to achieve smooth wurtzite faceting of vertical nanopillars. By incorporating InGaAs multiquantum wells, the nanopillar emission can be tuned over a wide spectral range. Enhanced quality factors of the intrinsic InP nanopillar cavities promote lasing at 0.87 and 1.21 μm, located within two important optical telecommunication bands. This is the first demonstration of a site-controlled III-V nanolaser monolithically integrated on silicon with a silicon-transparent emission wavelength, paving the way for energy-efficient on-chip optical links at typical telecommunication wavelengths.

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

Science.gov (United States)

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

MIT wavelength tables. Volume 2. Wavelengths by element

International Nuclear Information System (INIS)

Phelps, F.M. III.

1982-01-01

This volume is the first stage of a project to expand and update the MIT wavelength tables first compiled in the 1930's. For 109,325 atomic emission lines, arranged by element, it presents wavelength in air, wavelength in vacuum, wave number and intensity. All data are stored on computer-readable magnetic tape

Radiation effects of protons and 60Co γ rays on CMOS operational amplifier

International Nuclear Information System (INIS)

Lu Wu; Ren Diyuan; Guo Qi; Yu Xuefeng; Yan Rongliang

1997-01-01

Radiation effects of 60 Co γ ray and 4,7 and 30 MeV protons on LF 7650 CMOS operational amplifier were investigated. The damage mechanism of LF7650 was discussed. It is indicated that the mobility reduction of major carrier caused by ionizing and displacement damage is the chief mechanism causing the failure of CMOS operational amplifier irradiated by protons, and that is why the degradation of LF 7650 caused by protons is much more serious than that caused by 60 Co γ ray. In addition, a comparison of proton radiation effects on CMOS operational amplifier and MOSFET showed a significant difference in mechanism

Behavior equivalence and compatibility of business process models with complex correspondences

NARCIS (Netherlands)

Weidlich, M.; Dijkman, R.M.; Weske, M.H.

2012-01-01

Once multiple models of a business process are created for different purposes or to capture different variants, verification of behaviour equivalence or compatibility is needed. Equivalence verification ensures that two business process models specify the same behaviour. Since different process

LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

Energy Technology Data Exchange (ETDEWEB)

MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

2000-01-01

This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation hardened CMOS devices and circuits - LDRD Project (FY99)

International Nuclear Information System (INIS)

Myers, David R.; Jessing, Jeffrey R.; Spahn, Olga B.; Shaneyfelt, Marty R.

2000-01-01

This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds

Wavelength converter technology

DEFF Research Database (Denmark)

Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov

1999-01-01

Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers.......Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers....

CMOS switched current phase-locked loop

NARCIS (Netherlands)

Leenaerts, D.M.W.; Persoon, G.G.; Putter, B.M.

1997-01-01

The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes

Wavelength-encoded OCDMA system using opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Single-wavelength functional photoacoustic microscopy in biological tissue.

Science.gov (United States)

Danielli, Amos; Favazza, Christopher P; Maslov, Konstantin; Wang, Lihong V

2011-03-01

Recently, we developed a reflection-mode relaxation photoacoustic microscope, based on saturation intensity, to measure picosecond relaxation times using a nanosecond laser. Here, using the different relaxation times of oxygenated and deoxygenated hemoglobin molecules, both possessing extremely low fluorescence quantum yields, the oxygen saturation was quantified in vivo with single-wavelength photoacoustic microscopy. All previous functional photoacoustic microscopy measurements required imaging with multiple-laser-wavelength measurements to quantify oxygen saturation. Eliminating the need for multiwavelength measurements removes the influence of spectral properties on oxygenation calculations and improves the portability and cost-effectiveness of functional or molecular photoacoustic microscopy.

Wavelength-encoded OCDMA system using opto-VLSI processors

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

First result on biased CMOS MAPs-on-diamond devices

Energy Technology Data Exchange (ETDEWEB)

Kanxheri, K., E-mail: keida.kanxheri@pg.infn.it [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Citroni, M.; Fanetti, S. [LENS Firenze, Florence (Italy); Lagomarsino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Morozzi, A. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Parrini, G. [Università degli Studi di Firenze, Florence (Italy); Passeri, D. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Sciortino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Servoli, L. [INFN Perugia, Perugia (Italy)

2015-10-01

Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

Silicon-Nitride-based Integrated Optofluidic Biochemical Sensors using a Coupled-Resonator Optical Waveguide

Directory of Open Access Journals (Sweden)

Jiawei eWANG

2015-04-01

Full Text Available Silicon nitride (SiN is a promising material platform for integrating photonic components and microfluidic channels on a chip for label-free, optical biochemical sensing applications in the visible to near-infrared wavelengths. The chip-scale SiN-based optofluidic sensors can be compact due to a relatively high refractive index contrast between SiN and the fluidic medium, and low-cost due to the complementary metal-oxide-semiconductor (CMOS-compatible fabrication process. Here, we demonstrate SiN-based integrated optofluidic biochemical sensors using a coupled-resonator optical waveguide (CROW in the visible wavelengths. The working principle is based on imaging in the far field the out-of-plane elastic-light-scattering patterns of the CROW sensor at a fixed probe wavelength. We correlate the imaged pattern with reference patterns at the CROW eigenstates. Our sensing algorithm maps the correlation coefficients of the imaged pattern with a library of calibrated correlation coefficients to extract a minute change in the cladding refractive index. Given a calibrated CROW, our sensing mechanism in the spatial domain only requires a fixed-wavelength laser in the visible wavelengths as a light source, with the probe wavelength located within the CROW transmission band, and a silicon digital charge-coupled device (CCD / CMOS camera for recording the light scattering patterns. This is in sharp contrast with the conventional optical microcavity-based sensing methods that impose a strict requirement of spectral alignment with a high-quality cavity resonance using a wavelength-tunable laser. Our experimental results using a SiN CROW sensor with eight coupled microrings in the 680nm wavelength reveal a cladding refractive index change of ~1.3 × 10^-4 refractive index unit (RIU, with an average sensitivity of ~281 ± 271 RIU-1 and a noise-equivalent detection limit (NEDL of 1.8 ×10^-8 RIU ~ 1.0 ×10^-4 RIU across the CROW bandwidth of ~1 nm.

Proton-counting radiography for proton therapy: a proof of principle using CMOS APS technology

International Nuclear Information System (INIS)

Poludniowski, G; Esposito, M; Evans, P M; Allinson, N M; Anaxagoras, T; Green, S; Parker, D J; Price, T; Manolopoulos, S; Nieto-Camero, J

2014-01-01

Despite the early recognition of the potential of proton imaging to assist proton therapy (Cormack 1963 J. Appl. Phys. 34 2722), the modality is still removed from clinical practice, with various approaches in development. For proton-counting radiography applications such as computed tomography (CT), the water-equivalent-path-length that each proton has travelled through an imaged object must be inferred. Typically, scintillator-based technology has been used in various energy/range telescope designs. Here we propose a very different alternative of using radiation-hard CMOS active pixel sensor technology. The ability of such a sensor to resolve the passage of individual protons in a therapy beam has not been previously shown. Here, such capability is demonstrated using a 36 MeV cyclotron beam (University of Birmingham Cyclotron, Birmingham, UK) and a 200 MeV clinical radiotherapy beam (iThemba LABS, Cape Town, SA). The feasibility of tracking individual protons through multiple CMOS layers is also demonstrated using a two-layer stack of sensors. The chief advantages of this solution are the spatial discrimination of events intrinsic to pixelated sensors, combined with the potential provision of information on both the range and residual energy of a proton. The challenges in developing a practical system are discussed. (paper)

Proton-counting radiography for proton therapy: a proof of principle using CMOS APS technology.

Science.gov (United States)

Poludniowski, G; Allinson, N M; Anaxagoras, T; Esposito, M; Green, S; Manolopoulos, S; Nieto-Camero, J; Parker, D J; Price, T; Evans, P M

2014-06-07

Despite the early recognition of the potential of proton imaging to assist proton therapy (Cormack 1963 J. Appl. Phys. 34 2722), the modality is still removed from clinical practice, with various approaches in development. For proton-counting radiography applications such as computed tomography (CT), the water-equivalent-path-length that each proton has travelled through an imaged object must be inferred. Typically, scintillator-based technology has been used in various energy/range telescope designs. Here we propose a very different alternative of using radiation-hard CMOS active pixel sensor technology. The ability of such a sensor to resolve the passage of individual protons in a therapy beam has not been previously shown. Here, such capability is demonstrated using a 36 MeV cyclotron beam (University of Birmingham Cyclotron, Birmingham, UK) and a 200 MeV clinical radiotherapy beam (iThemba LABS, Cape Town, SA). The feasibility of tracking individual protons through multiple CMOS layers is also demonstrated using a two-layer stack of sensors. The chief advantages of this solution are the spatial discrimination of events intrinsic to pixelated sensors, combined with the potential provision of information on both the range and residual energy of a proton. The challenges in developing a practical system are discussed.

High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

Science.gov (United States)

Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

2017-02-01

Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

Geant4-based simulations of charge collection in CMOS Active Pixel Sensors

International Nuclear Information System (INIS)

Esposito, M.; Allinson, N.M.; Price, T.; Anaxagoras, T.

2017-01-01

Geant4 is an object-oriented toolkit for the simulation of the interaction of particles and radiation with matter. It provides a snapshot of the state of a simulated particle in time, as it travels through a specified geometry. One important area of application is the modelling of radiation detector systems. Here, we extend the abilities of such modelling to include charge transport and sharing in pixelated CMOS Active Pixel Sensors (APSs); though similar effects occur in other pixel detectors. The CMOS APSs discussed were developed in the framework of the PRaVDA consortium to assist the design of custom sensors to be used in an energy-range detector for proton Computed Tomography (pCT). The development of ad-hoc classes, providing a charge transport model for a CMOS APS and its integration into the standard Geant4 toolkit, is described. The proposed charge transport model includes, charge generation, diffusion, collection, and sharing across adjacent pixels, as well as the full electronic chain for a CMOS APS. The proposed model is validated against experimental data acquired with protons in an energy range relevant for pCT.

Custom high-reliability radiation-hard CMOS-LSI circuit design

International Nuclear Information System (INIS)

Barnard, W.J.

1981-01-01

Sandia has developed a custom CMOS-LSI design capability to provide high reliability radiation-hardened circuits. This capability relies on (1) proven design practices to enhance reliability, (2) use of well characterized cells and logic modules, (3) computer-aided design tools to reduce design time and errors and to standardize design definition, and (4) close working relationships with the system designer and technology fabrication personnel. Trade-offs are made during the design between circuit complexity/performance and technology/producibility for high reliability and radiation-hardened designs to result. Sandia has developed and is maintaining a radiation-hardened bulk CMOS technology fabrication line for production of prototype and small production volume parts

Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

Science.gov (United States)

Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

International Nuclear Information System (INIS)

Duzer, Theodore van; Feng Yijun; Meng Xiaofan; Whiteley, Stephen R; Yoshikawa, Nobuyuki

2002-01-01

The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented

Effect of CMOS Technology Scaling on Fully-Integrated Power Supply Efficiency

OpenAIRE

Pillonnet , Gaël; Jeanniot , Nicolas

2016-01-01

International audience; Integrating a power supply in the same die as the powered circuits is an appropriate solution for granular, fine and fast power management. To allow same-die co-integration, fully integrated DC-DC converters designed in the latest CMOS technologies have been greatly studied by academics and industrialists in the last decade. However, there is little study concerning the effects of the CMOS scaling on these particular circuits. To show the trends, this paper compares th...

A new method of preventing bulk-Si CMOS devices from latchup

International Nuclear Information System (INIS)

Xu Xianguo; Xu Xi

2004-01-01

A new method, pseudo-latchup path method, has been put forward that is based on latchup effects of bulk-Si CMOS devices. After we study the design of pseudo-latchup path method in detail, a practice and the corresponding simulation result by computer are given in this text. Pseudo-latchup path method can be used to prevent permanent latchup, but it cannot be used to eliminate the dose rate upset of bulk-Si CMOS devices. (authors)

Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

International Nuclear Information System (INIS)

Wang, Zujun; Huang, Shaoyan; Liu, Minbo; Xiao, Zhigang; He, Baoping; Yao, Zhibin; Sheng, Jiangkun

2014-01-01

The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 10 8 n/cm 2 s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10 11 , 5 × 10 11 , and 1 × 10 12 n/cm 2 , respectively. The mean dark signal (K D ), dark signal spike, dark signal non-uniformity (DSNU), noise (V N ), saturation output signal voltage (V S ), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike

CMOS Pixel Sensors for High Precision Beam Telescopes and Vertex Detectors

International Nuclear Information System (INIS)

Masi, R. de; Baudot, J.; Fontaine, J.-Ch.

2009-01-01

CMOS sensors of the MIMOSA (standing for Minimum Ionising particle MOS Active pixel sensor) series are developed at IPHC since a decade and have ended up with full scale devices used in beam telescopes and in demonstrators of future vertex detectors. The sensors deliver analogue, unfiltered, signals and are therefore limited to read-out frequencies of ∼ 1 kframe/s. Since a few years, a fast architecture is being developed in collaboration with IRFU, which aims to speed up the read-out by 1-2 orders of magnitude. The first full scale sensor based on this architecture was fabricated recently and is being tested. Made of 660,000 pixels (18 μm pitch) covering an active area of ∼ 2 cm 2 , it delivers zero-suppressed binary signals, which allow running at ∼ 10 kframes/s. It will equip the beam telescope of the E.U. project EUDET and serve as a forerunner of the sensor equipping the 2 layers of the PIXEL detector of the STAR experiment at RHIC. The contribution to the conference will overview the main features and test results of this pioneering sensor. It will next describe its evolution towards read-out frequencies approaching 100 kframes/s, as required for the vertex detectors of the CBM experiment at FAIR and at the ILC. Finally, the issue of radiation tolerance will be addressed, in the context of a newly available CMOS process using a depleted substrate. A prototype sensor was fabricated in a such CMOS process. The talk will summarise beam test results showing, for the first time, that fluences of 10 14 n eq /cm 2 may be tolerable for CMOS sensors. Overall, the talk provides an overview of the status and plans of CMOS pixel sensors at the frontier of their achievements and outreach. (author)

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

Science.gov (United States)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

Science.gov (United States)

Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

2015-05-07

In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.

Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

Science.gov (United States)

Berdalovic, I.; Bates, R.; Buttar, C.; Cardella, R.; Egidos Plaja, N.; Hemperek, T.; Hiti, B.; van Hoorne, J. W.; Kugathasan, T.; Mandic, I.; Maneuski, D.; Marin Tobon, C. A.; Moustakas, K.; Musa, L.; Pernegger, H.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E. J.; Sharma, A.; Snoeys, W.; Solans Sanchez, C.; Wang, T.; Wermes, N.

2018-01-01

The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

DEFF Research Database (Denmark)

Olesen, Ole

1997-01-01

circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...... of including good off-chip components in the design by use of innovative, inexpensive package technology.To achieve a higher level of integration, the project will use a novel codesign approach to the design strategy. Rather than making specifications based on a purely architectural approach, the work uses...

''Normal'' tissues from humans exposed to radium contain an alteration in the c-mos locus

International Nuclear Information System (INIS)

Huberman, E.; Schlenker, R.A.; Hardwick, J.P.

1989-01-01

The structures of a number of human proto-oncogenes from persons with internal systemic exposure to radium were analyzed by restriction enzyme digestion and southern blotting of their DNA. Two extra c-mos Eco R1 restriction-fragment-length bands of 5.0 kb and 5.5 kb were found in tissue DNA from six of seven individuals. The extra c-mos bands were detected in DNA from many, but not all, of the tissues of the individuals exposed to radium. Our results suggest that the c-mos restriction-fragment-length alterations (RFLA) found in individuals exposed to radium were induced rather than inherited, are epigenetic in origin, and most likely result from changes in the methylation of bases surrounding the single exon of the c-mos proto-oncogene. 7 refs., 3 figs., 2 tabs

Integration of near infrared and visible organic photodiodes on a complementary metal–oxide–semiconductor compatible backplane

Energy Technology Data Exchange (ETDEWEB)

Jahnel, M.; Thomschke, M.; Fehse, K.; Vogel, U. [Fraunhofer-Institute for Organische Elektronik, Elektronenstrahl-und Plasmatechnik FEP, 01199 Dresden (Germany); An, J.D.; Park, H. [Konkuk University-Fraunhofer Next Generation Solar Cell Research Center (KFnSC), Konkuk University, 120 Neungdong-ro, Gwangjin-gu, Seoul 143-701 (Korea, Republic of); Leo, K. [Fraunhofer-Institute for Organische Elektronik, Elektronenstrahl-und Plasmatechnik FEP, 01199 Dresden (Germany); Institut für Angewandte Photophysik, Technische Universität Dresden (TUD), 01062 Dresden (Germany); Im, C. [Konkuk University-Fraunhofer Next Generation Solar Cell Research Center (KFnSC), Konkuk University, 120 Neungdong-ro, Gwangjin-gu, Seoul 143-701 (Korea, Republic of)

2015-10-01

This paper reports about the integration of polymer-based bulk heterojunction organic photo diodes (OPDs) onto complementary metal–oxide–semiconductor (CMOS) compatible electrode materials. The fabrication and performance of four absorber systems in indium tin oxide-free OPDs for sensing applications have been studied. These are based on the following polymer–fullerene blends: Poly(3-hexylthiophene-2,5-diyl):[6,6]Phenyl C{sub 61} Butyric Acid Methyl Ester and Poly(3-hexylthiophene-2,5 diyl):Di[1,4] methanonaphthaleno [1,2:2′,3′;56,60:2″,3″] [5,6]fullerene-C60-Ih, 1′,1″,4′,4″-tetrahydro-, indene-C60 bisadduct to detect light in the visible range and Poly[[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b′]dithiophene-2,6-diyl] [3-fluoro-2-[(2-ethylhexyl)carbonyl] thieno[3,4-b]thiophenediyl

Integration of near infrared and visible organic photodiodes on a complementary metal–oxide–semiconductor compatible backplane

International Nuclear Information System (INIS)

Jahnel, M.; Thomschke, M.; Fehse, K.; Vogel, U.; An, J.D.; Park, H.; Leo, K.; Im, C.

2015-01-01

This paper reports about the integration of polymer-based bulk heterojunction organic photo diodes (OPDs) onto complementary metal–oxide–semiconductor (CMOS) compatible electrode materials. The fabrication and performance of four absorber systems in indium tin oxide-free OPDs for sensing applications have been studied. These are based on the following polymer–fullerene blends: Poly(3-hexylthiophene-2,5-diyl):[6,6]Phenyl C_6_1 Butyric Acid Methyl Ester and Poly(3-hexylthiophene-2,5 diyl):Di[1,4] methanonaphthaleno [1,2:2′,3′;56,60:2″,3″] [5,6]fullerene-C60-Ih, 1′,1″,4′,4″-tetrahydro-, indene-C60 bisadduct to detect light in the visible range and Poly[[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b′]dithiophene-2,6-diyl] [3-fluoro-2-[(2-ethylhexyl)carbonyl] thieno[3,4-b]thiophenediyl

An Analytical Model for Spectral Peak Frequency Prediction of Substrate Noise in CMOS Substrates

DEFF Research Database (Denmark)

Shen, Ming; Mikkelsen, Jan H.

2013-01-01

This paper proposes an analytical model describing the generation of switching current noise in CMOS substrates. The model eliminates the need for SPICE simulations in existing methods by conducting a transient analysis on a generic CMOS inverter and approximating the switching current waveform us...