A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

Science.gov (United States)

Huang, Haiyun; Wang, Dejun; Xu, Yue

2015-10-27

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

Directory of Open Access Journals (Sweden)

Haiyun Huang

2015-10-01

Full Text Available This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

Science.gov (United States)

Lauxtermann, Stefan; Fisher, John; McDougal, Michael

2014-06-01

In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

Science.gov (United States)

Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

2018-03-01

Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

Characterization of SOI monolithic detector system

Science.gov (United States)

Álvarez-Rengifo, P. L.; Soung Yee, L.; Martin, E.; Cortina, E.; Ferrer, C.

2013-12-01

A monolithic active pixel sensor for charged particle tracking was developed. This research is performed within the framework of an R&D project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology) whose aim is to evaluate the feasibility of developing a Monolithic Active Pixel Sensor (MAPS) with Silicon-on-Insulator (SOI) technology. Two chips were fabricated: TRAPPISTe-1 and TRAPPISTe-2. TRAPPISTe-1 was produced at the WINFAB facility at the Université catholique de Louvain (UCL), Belgium, in a 2 μm fully depleted (FD-SOI) CMOS process. TRAPPISTe-2 was fabricated with the LAPIS 0.2 μm FD-SOI CMOS process. The electrical characterization on single transistor test structures and of the electronic readout for the TRAPPISTe series of monolithic pixel detectors was carried out. The behavior of the prototypes’ electronics as a function of the back voltage was studied. Results showed that both readout circuits exhibited sensitivity to the back voltage. Despite this unwanted secondary effect, the responses of TRAPPISTe-2 amplifiers can be improved by a variation in the circuit parameters.

Advancing the technology of monolithic CMOS detectors for use as x-ray imaging spectrometers

Science.gov (United States)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Amato, Stephen

2017-08-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff has been engaged in a multi year effort to advance the technology of monolithic back-thinned CMOS detectors for use as X-ray imaging spectrometers. The long term goal of this campaign is to produce X-ray Active Pixel Sensor (APS) detectors with Fano limited performance over the 0.1-10keV band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Such devices would be ideal for candidate post 2020 decadal missions such as LYNX and for smaller more immediate applications such as CubeX. Devices from a recent fabrication have been back-thinned, packaged and tested for soft X-ray response. These devices have 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels with ˜135μV/electron sensitivity and a highly parallel signal chain. These new detectors are fabricated on 10μm epitaxial silicon and have a 1k by 1k format. We present details of our camera design and device performance with particular emphasis on those aspects of interest to single photon counting X-ray astronomy. These features include read noise, X-ray spectral response and quantum efficiency.

Pitch dependence of the tolerance of CMOS monolithic active pixel sensors to non-ionizing radiation

International Nuclear Information System (INIS)

Doering, D.; Deveaux, M.; Domachowski, M.; Fröhlich, I.; Koziel, M.; Müntz, C.; Scharrer, P.; Stroth, J.

2013-01-01

CMOS monolithic active pixel sensors (MAPS) have demonstrated excellent performance as tracking detectors for charged particles. They provide an outstanding spatial resolution (a few μm), a detection efficiency of ≳99.9%, very low material budget (0.05%X 0 ) and good radiation tolerance (≳1Mrad, ≳10 13 n eq /cm 2 ) (Deveaux et al. [1]). This makes them an interesting technology for various applications in heavy ion and particle physics. Their tolerance to bulk damage was recently improved by using high-resistivity (∼1kΩcm) epitaxial layers as sensitive volume (Deveaux et al. [1], Dorokhov et al. [2]). The radiation tolerance of conventional MAPS is known to depend on the pixel pitch. This is as a higher pitch extends the distance, which signal electrons have to travel by thermal diffusion before being collected. Increased diffusion paths turn into a higher probability of loosing signal charge due to recombination. Provided that a similar effect exists in MAPS with high-resistivity epitaxial layer, it could be used to extend their radiation tolerance further. We addressed this question with MIMOSA-18AHR prototypes, which were provided by the IPHC Strasbourg and irradiated with reactor neutrons. We report about the results of this study and provide evidences that MAPS with 10μm pixel pitch tolerate doses of ≳3×10 14 n eq /cm 2

Depleted CMOS pixels for LHC proton–proton experiments

International Nuclear Information System (INIS)

Wermes, N.

2016-01-01

While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

OpenAIRE

Kim, D; Rinella, G Aglieri; Cavicchioli, C; Chanlek, N; Collu, A; Degerli, Y; Dorokhov, A; Flouzat, C; Gajanana, D; Gao, C; Guilloux, F; Hillemanns, H; Hristozkov, S; Junique, A; Keil, M

2016-01-01

ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m(2) tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the ...

Monolithically Integrated Ge-on-Si Active Photonics

Directory of Open Access Journals (Sweden)

Jifeng Liu

2014-07-01

Full Text Available Monolithically integrated, active photonic devices on Si are key components in Si-based large-scale electronic-photonic integration for future generations of high-performance, low-power computation and communication systems. Ge has become an interesting candidate for active photonic devices in Si photonics due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS processing. In this paper, we present a review of the recent progress in Ge-on-Si active photonics materials and devices for photon detection, modulation, and generation. We first discuss the band engineering of Ge using tensile strain, n-type doping, Sn alloying, and separate confinement of Γ vs. L electrons in quantum well (QW structures to transform the material towards a direct band gap semiconductor for enhancing optoelectronic properties. We then give a brief overview of epitaxial Ge-on-Si materials growth, followed by a summary of recent investigations towards low-temperature, direct growth of high crystallinity Ge and GeSn alloys on dielectric layers for 3D photonic integration. Finally, we review the most recent studies on waveguide-integrated Ge-on-Si photodetectors (PDs, electroabsorption modulators (EAMs, and laser diodes (LDs, and suggest possible future research directions for large-scale monolithic electronic-photonic integrated circuits on a Si platform.

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

Energy Technology Data Exchange (ETDEWEB)

Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng, E-mail: xxd@tju.edu.c [School of Electronic Information Engineering, Tianjin University, Tianjin 300072 (China)

2009-12-15

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 {mu}m EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10{sup -9}. The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

International Nuclear Information System (INIS)

Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng

2009-01-01

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10 -9 . The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

Recent progress in the development of 3D deep n-well CMOS MAPS

International Nuclear Information System (INIS)

Traversi, G; Manghisoni, M; Re, V; Gaioni, L; Manazza, A; Ratti, L; Zucca, S

2012-01-01

In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

A column level, low power, 1 M sample/s double ramp A/D converter for monolithic active pixel sensors in high energy physics

International Nuclear Information System (INIS)

Pillet, N.; Heini, S.; Hu, Y.

2010-01-01

Monolithic active pixel sensors (MAPS) using standard low cost CMOS technologies available from industrial manufacturers have demonstrated excellent tracking performances for minimum ionizing particles. The need for highly granular, fast, thin sensors with a full digital output drives an R and D effort, aiming to design and optimize a low power high speed A/D converter integrated at the column level. Following this main issue, a double digital ramp A/D converter has been proposed for CMOS monolithic active pixel sensors in this paper. This A/D converter responds to the constraints of size, power dissipation and precision for CMOS sensors for particle detection. It also represents a first step in order to reach the high speed of conversion needed for this kind of application. The A/D converter has a resolution of 4 bits for conversion speed of 1 M sample/s with only 264 μW of static consumption in a very particular pitch of 25 μmx900 μm.

First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

Science.gov (United States)

Pernegger, H.; Bates, R.; Buttar, C.; Dalla, M.; van Hoorne, J. W.; Kugathasan, T.; Maneuski, D.; Musa, L.; Riedler, P.; Riegel, C.; Sbarra, C.; Schaefer, D.; Schioppa, E. J.; Snoeys, W.

2017-06-01

The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 1015neq/cm2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

First tests of a novel radiation hard CMOS sensor process for Depleted Monolithic Active Pixel Sensors

International Nuclear Information System (INIS)

Pernegger, H.; Hoorne, J.W. van; Kugathasan, T.; Musa, L.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E.J.; Snoeys, W.; Bates, R.; Buttar, C.; Maneuski, D.; Dalla, M.; Sbarra, C.

2017-01-01

The upgrade of the ATLAS [1] tracking detector for the High-Luminosity Large Hadron Collider (LHC) at CERN requires novel radiation hard silicon sensor technologies. Significant effort has been put into the development of monolithic CMOS sensors but it has been a challenge to combine a low capacitance of the sensing node with full depletion of the sensitive layer. Low capacitance brings low analog power. Depletion of the sensitive layer causes the signal charge to be collected by drift sufficiently fast to separate hits from consecutive bunch crossings (25 ns at the LHC) and to avoid losing the charge by trapping. This paper focuses on the characterization of charge collection properties and detection efficiency of prototype sensors originally designed in the framework of the ALICE Inner Tracking System (ITS) upgrade [2]. The prototypes are fabricated both in the standard TowerJazz 180nm CMOS imager process [3] and in an innovative modification of this process developed in collaboration with the foundry, aimed to fully deplete the sensitive epitaxial layer and enhance the tolerance to non-ionizing energy loss. Sensors fabricated in standard and modified process variants were characterized using radioactive sources, focused X-ray beam and test beams before and after irradiation. Contrary to sensors manufactured in the standard process, sensors from the modified process remain fully functional even after a dose of 10"1"5 n _e_q/cm"2, which is the the expected NIEL radiation fluence for the outer pixel layers in the future ATLAS Inner Tracker (ITk) [4].

Large area CMOS image sensors

International Nuclear Information System (INIS)

Turchetta, R; Guerrini, N; Sedgwick, I

2011-01-01

CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

Directory of Open Access Journals (Sweden)

Hongyi Mi

2017-03-01

Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

Science.gov (United States)

Kenter, Almus

The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various

Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

International Nuclear Information System (INIS)

Kim, D.; Rinella, G. Aglieri; Cavicchioli, C.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kofarago, M.; Kugathasan, T.; Mager, M.; Chanlek, N.; Collu, A.; Degerli, Y.; Flouzat, C.; Guilloux, F.; Dorokhov, A.; Gajanana, D.; Gao, C.; Kwon, Y.; Lattuca, A.

2016-01-01

ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m 2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented

Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

Science.gov (United States)

Kim, D.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Lattuca, A.; Mager, M.; Sielewicz, K. M.; Marin Tobon, C. A.; Marras, D.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Pham, T. H.; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. W.; Yang, P.

2016-02-01

ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented.

Technology development for SOI monolithic pixel detectors

International Nuclear Information System (INIS)

Marczewski, J.; Domanski, K.; Grabiec, P.; Grodner, M.; Jaroszewicz, B.; Kociubinski, A.; Kucharski, K.; Tomaszewski, D.; Caccia, M.; Kucewicz, W.; Niemiec, H.

2006-01-01

A monolithic detector of ionizing radiation has been manufactured using silicon on insulator (SOI) wafers with a high-resistivity substrate. In our paper the integration of a standard 3 μm CMOS technology, originally designed for bulk devices, with fabrication of pixels in the bottom wafer of a SOI substrate is described. Both technological sequences have been merged minimizing thermal budget and providing suitable properties of all the technological layers. The achieved performance proves that fully depleted monolithic active pixel matrix might be a viable option for a wide spectrum of future applications

A novel CMOS sensor with in-pixel auto-zeroed discrimination for charged particle tracking

International Nuclear Information System (INIS)

Degerli, Y; Guilloux, F; Orsini, F

2014-01-01

With the aim of developing fast and granular Monolithic Active Pixels Sensors (MAPS) as new charged particle tracking detectors for high energy physics experiments, a new rolling shutter binary pixel architecture concept (RSBPix) with in-pixel correlated double sampling, amplification and discrimination is presented. The discriminator features auto-zeroing in order to compensate process-related transistor mismatches. In order to validate the pixel, a first monolithic CMOS sensor prototype, including a pixel array of 96 × 64 pixels, has been designed and fabricated in the Tower-Jazz 0.18 μm CMOS Image Sensor (CIS) process. Results of laboratory tests are presented

First result on biased CMOS MAPs-on-diamond devices

Energy Technology Data Exchange (ETDEWEB)

Kanxheri, K., E-mail: keida.kanxheri@pg.infn.it [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Citroni, M.; Fanetti, S. [LENS Firenze, Florence (Italy); Lagomarsino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Morozzi, A. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Parrini, G. [Università degli Studi di Firenze, Florence (Italy); Passeri, D. [Università degli Studi di Perugia, Perugia (Italy); INFN Perugia, Perugia (Italy); Sciortino, S. [Università degli Studi di Firenze, Florence (Italy); INFN Firenze, Pisa (Italy); Servoli, L. [INFN Perugia, Perugia (Italy)

2015-10-01

Recently a new type of device, the MAPS-on-diamond, obtained bonding a thinned to 25 μm CMOS Monolithic Active Pixel Sensor to a standard 500 μm pCVD diamond substrate, has been proposed and fabricated, allowing a highly segmented readout (10×10 μm pixel size) of the signal produced in the diamond substrate. The bonding between the two materials has been obtained using a new laser technique to deliver the needed energy at the interface. A biasing scheme has been adopted to polarize the diamond substrate to allow the charge transport inside the diamond without disrupting the functionalities of the CMOS Monolithic Active Pixel Sensor. The main concept of this class of devices is the capability of the charges generated in the diamond by ionizing radiation to cross the silicon–diamond interface and to be collected by the MAPS photodiodes. In this work we demonstrate that such passage occurs and measure its overall efficiency. This study has been carried out first calibrating the CMOS MAPS with monochromatic X-rays, and then testing the device with charged particles (electrons) either with and without biasing the diamond substrate, to compare the amount of signal collected.

ALPIDE, the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

Science.gov (United States)

Mager, M.; ALICE Collaboration

2016-07-01

A new 10 m2 inner tracking system based on seven concentric layers of Monolithic Active Pixel Sensors will be installed in the ALICE experiment during the second long shutdown of LHC in 2019-2020. The monolithic pixel sensors will be fabricated in the 180 nm CMOS Imaging Sensor process of TowerJazz. The ALPIDE design takes full advantage of a particular process feature, the deep p-well, which allows for full CMOS circuitry within the pixel matrix, while at the same time retaining the full charge collection efficiency. Together with the small feature size and the availability of six metal layers, this allowed a continuously active low-power front-end to be placed into each pixel and an in-matrix sparsification circuit to be used that sends only the addresses of hit pixels to the periphery. This approach led to a power consumption of less than 40 mWcm-2, a spatial resolution of around 5 μm, a peaking time of around 2 μs, while being radiation hard to some 1013 1 MeVneq /cm2, fulfilling or exceeding the ALICE requirements. Over the last years of R & D, several prototype circuits have been used to verify radiation hardness, and to optimize pixel geometry and in-pixel front-end circuitry. The positive results led to a submission of full-scale (3 cm×1.5 cm) sensor prototypes in 2014. They are being characterized in a comprehensive campaign that also involves several irradiation and beam tests. A summary of the results obtained and prospects towards the final sensor to instrument the ALICE Inner Tracking System are given.

First Results from Cherwell, a Monolithic Active Pixel Sensor for Particle Physics

CERN Document Server

Nooney, Tamsin; Borri, Marcello; Crooks, Jamie; Headspith, Jon; Inguglia, Gianluca; Kolya, Scott; Lazarus, Ian; Lemmon, Roy; Mylroie-Smith, James; Turchetta, Renato; Velthuis, Jaap; Wilson, Fergus

2014-01-01

Cherwell is a CMOS Monolithic Active Pixel Sensor (MAPS) developed for digital calorimetry and charged particle tracking applications. Here, we outline the initial tests carried out to charac- terise the performance of Cherwell, give details of the test beam carried out at CERN and include the first results from this analysis. Three variations of the chip were tested; Type A, a high re- sistivity, low noise sensor, Type B, a standard resisivity, low noise sensor and Type C, a standard resistivity, standard noise sensor. The sensors yield an average RMS noise value per pixel of 9.6 e

LePIX: First results from a novel monolithic pixel sensor

International Nuclear Information System (INIS)

Mattiazzo, S.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rivetti, A.; Rousset, J.; Silvestrin, L.; Snoeys, W.; Wyss, J.

2013-01-01

We present a monolithic pixel sensor developed in the framework of the LePIX project aimed at tracking/triggering tasks where high granularity, low power consumption, material budget, radiation hardness and production costs are a concern. The detector is built in a 90 nm CMOS process on a substrate of moderate resistivity. This maintains the advantages usually offered by Monolithic Active Pixel Sensors (MAPS), like a low input capacitance, having a single piece detector and using a standard CMOS production line, but offers charge collection by drift from a depleted region and therefore an excellent signal to noise ratio and a radiation tolerance superior to conventional undepleted MAPS. Measurement results obtained with the first prototypes from laser, radioactive source and beam test experiments are described. The excellent signal-to-noise performance is demonstrated by the capability of the device to separate the peaks in the spectrum of a 55 Fe source. We will also highlight the interaction between pixel cell design and architecture which points toward a very precise direction in the development of such depleted monolithic pixel devices for high energy physics

Design of a 2.4-GHz CMOS monolithic fractional-N frequency synthesizer

Science.gov (United States)

Shu, Keliu

The wireless communication technology and market have been growing rapidly since a decade ago. The high demand market is a driving need for higher integration in the wireless transceivers. The trend is to achieve low-cost, small form factor and low power consumption. With the ever-reducing feature size, it is becoming feasible to integrate the RF front-end together with the baseband in the low-cost CMOS technology. The frequency synthesizer is a key building block in the RF front-end of the transceivers. It is used as a local oscillator for frequency translation and channel selection. The design of a 2.4-GHz low-power frequency synthesizer in 0.35mum CMOS is a challenging task mainly due to the high-speed prescaler. In this dissertation, a brief review of conventional PLL and frequency synthesizers is provided. Design techniques of a 2.4-GHz monolithic SigmaDelta fractional-N frequency synthesizer are investigated. Novel techniques are proposed to tackle the speed and integration bottlenecks of high-frequency PLL. A low-power and inherently glitch-free phase-switching prescaler and an on-chip loop filter with capacitance multiplier are developed. Compared with the existing and popular dual-path topology, the proposed loop filter reduces circuit complexity and its power consumption and noise are negligible. Furthermore, a third-order three-level digital SigmaDelta modulator topology is employed to reduce the phase noise generated by the modulator. Suitable PFD and charge-pump designs are employed to reduce their nonlinearity effects and thus minimize the folding of the SigmaDelta modulator-shaped phase noise. A prototype of the fractional-N synthesizer together with some standalone building blocks is designed and fabricated in TSMC 0.35mum CMOS through MOSIS. The prototype frequency synthesizer and standalone prescaler and loop filter are characterized. The feasibility and practicality of the proposed prescaler and loop filter are experimentally verified.

A monolithic 180 nm CMOS dosimeter for wireless In Vivo Dosimetry

International Nuclear Information System (INIS)

Villani, E.G.; Crepaldi, M.; DeMarchi, D.; Gabrielli, A.; Khan, A.; Pikhay, E.; Roizin, Y.; Rosenfeld, A.; Zhang, Z.

2016-01-01

The design, fabrication and testing of a novel monolithic system-on-chip dosimeter fabricated in a standard 180 nm CMOS technology is described. The device, implementing a radiation sensor and an RF transmitter, is proposed to address the need for real-time In Vivo Dosimetry (IVD) of radiation during Linac radiotherapy sessions. Owing to its small size, of approximately 1 mm"3, such solution could be made in-body implantable and, as such, provide a much-enhanced high-resolution, real-time dose measurement to improve Quality Assurance (QA) in radiation therapy. The device transmits the related information on dose of radiation wirelessly to a remote receiver operating in the Medical Implant Communication Service (MICS) band. Comprehensive description of the various phases of this project, including the development of the radiation sensors and integrated RF transmitter to perform the readout, along with the final test results using a radiation beam, will be given. - Highlights: • A Monolithic Dosimeter for real time dosimetry during radiotherapy is proposed. • The proposed device is 1 mm3 in size and could potentially be body implantable. • The device includes a radiation sensor and RF readout, operating in the MICS band. • Detailed tests have been performed under radiation beam in a clinical environment. • Reported sensitivity is 1 cGy over 50 Gy, with an accuracy of better than 3%.

CMOS Pixel Development for the ATLAS Experiment at HL-LHC

CERN Document Server

Ristic, Branislav; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on technologies that allow to use high depletion voltages (HV-MAPS) and high resistivity wafers (HR-MAPS) for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics to be embedded safely into the sensor substrate. We are investigating depleted CMOS pixels with monolithic or hybrid designs concerning their suitability for high rate, fast timing and high radiation operation at LHC. This paper will discuss recent results on the main candidate technologies and the current development towards a monolithic solution.

Application-specific architectures of CMOS monolithic active pixel sensors

Energy Technology Data Exchange (ETDEWEB)

Szelezniak, Michal [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]. E-mail: michal.szelezniak@ires.in2p3.fr; Besson, Auguste [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Claus, Gilles; Colledani, Claude; [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Degerli, Yavuz [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Deptuch, Grzegorz [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Deveaux, Michael [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); GSI, Planckstrasse 1, Darmstadt 64291 (Germany); Dorokhov, Andrei [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Dulinski, Wojciech [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Fourches, Nicolas [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Goffe, Mathieu [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Grandjean, Damien; Guilloux, Fabrice [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Heini, Sebastien [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]|[GSI, Planckstrasse 1, Darmstadt 64291 (Germany); Himmi, Abdelkader [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Hu, Christine [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Jaaskelainen, Kimmo; Li, Yan; Lutz, Pierre; Orsini, Fabienne [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Pellicioli, Michel; Shabetai, Alexandre; Valin, Isabelle; Winter, Marc [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)

2006-11-30

Several development directions intended to adapt and optimize monolithic active pixel sensors for specific applications are presented in this work. The first example, compatible with the STAR microvertex upgrade, is based on a simple two-transistor pixel circuitry. It is suited for a long integration time, room-temperature operation and minimum power dissipation. In another approach for this application, a specific readout method is proposed, allowing optimization of the integration time independently of the full frame-readout time. The circuit consists of an in-pixel front-end voltage amplifier, with a gain on the order of five, followed by two analog memory cells. The extended version of this scheme, based on the implementation of more memory cells per pixel, is the solution considered for the outer layers of a microvertex detector at the international linear collider. For the two innermost layers, a circuit allowing fast frame scans together with on-line, on-chip data sparsification is proposed. The first results of this prototype demonstrate that the fixed pattern dispersion is reduced below a noise level of 15 e{sup -}, allowing the use of a single comparator or a low-resolution ADC per pixel column. A common element for most of the mentioned readout schemes is a low-noise, low power consumption, layout efficient in-pixel amplifier. A review of possible solutions for this element together with some experimental results is presented.

Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

International Nuclear Information System (INIS)

Obermann, Theresa

2017-06-01

The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 μm thickness, were characterized. The prototypes have 352 square pixels of 40 μm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n + -implantation size: 5 μm x 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e - to 3000 e - while the noise is 30 e - due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5 x 10 14 neutrons/cm 2 the performance suffers from the radiation damage leading to a signal of 1000 e - and a higher noise of 60 e - due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5 x 10 14 particles/cm 2 . Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (< 1 x 10 14 particles/cm 2 ). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC) experiments and B-factories where the low material budget

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

Science.gov (United States)

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

LePix-A high resistivity, fully depleted monolithic pixel detector

CERN Document Server

Giubilato, P; Mugnier, H; Bisello, D; Marchioro, A; Snoeys, W; Denes, P; Pantano, D; Rousset, J; Mattiazzo, S; Kloukinas, K; Potenza, A; Rivetti, A; Chalmet, P

2013-01-01

The LePix project explores monolithic pixel sensors fabricated in a 90 nm CMOS technology built over a lightly doped substrate. This approach keeps the advantages usually offered by Monolithic Active Pixel Sensors (MAPS), like a low input capacitance, having a single piece detector and using a standard CMOS production line, and adds the benefit of charge collection by drift from a depleted region several tens of microns deep into the substrate, therefore providing an excellent signal to noise ratio and a radiation tolerance superior to conventional un-depleted MAPS. Such sensors are expected to offer significant cost savings and reduction of power consumption for the same performance, leading to the use of much less material in the detector (less cooling and less copper), addressing one of the main limitations of present day particle tracking systems. The latest evolution of the project uses detectors thinned down to 50 mu m to obtain back illuminated sensors operated in full depletion mode. By back processin...

CMOS-sensors for energy-resolved X-ray imaging

International Nuclear Information System (INIS)

Doering, D.; Amar-Youcef, S.; Deveaux, M.; Linnik, B.; Müntz, C.; Stroth, Joachim; Baudot, J.; Dulinski, W.; Kachel, M.

2016-01-01

Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ''color sensitive' X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors

From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

DEFF Research Database (Denmark)

Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

2008-01-01

This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

CMOS MEMS Fabrication Technologies and Devices

Directory of Open Access Journals (Sweden)

Hongwei Qu

2016-01-01

Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

NARCIS (Netherlands)

Dutta, Satadal

2017-01-01

Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers

International Nuclear Information System (INIS)

Ratti, L.; Gaioni, L.; Manghisoni, M.; Re, V.; Traversi, G.

2010-01-01

A fine pitch, deep N-well CMOS monolithic active pixel sensor (DNW CMOS MAPS) with sparsified readout architecture and time stamping capabilities has been designed in a vertical integration (3D) technology. In this process, two 130 nm CMOS wafers are face-to-face bonded by means of thermo-compression techniques ensuring both the mechanical stability of the structure and the electrical interconnection between circuits belonging to different layers. This 3D design represents the evolution of a DNW monolithic sensor already fabricated in a planar 130 nm CMOS technology in view of applications to the vertex detector of the International Linear Collider (ILC). The paper is devoted to discussing the main design features and expected performance of the 3D DNW MAPS. Besides describing the front-end circuits and the general architecture of the detector, the work also provides some results from calculations and Monte Carlo device simulations comparing the old 2D solution with the new 3D one and illustrating the attainable detection efficiency improvements.

Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers

Energy Technology Data Exchange (ETDEWEB)

Ratti, L., E-mail: lodovico.ratti@unipv.i [Universita di Pavia, Dipartimento di Elettronica, Via Ferrata 1, I-27100 Pavia (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy); Gaioni, L. [Universita di Pavia, Dipartimento di Elettronica, Via Ferrata 1, I-27100 Pavia (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy); Manghisoni, M.; Re, V.; Traversi, G. [Universita di Bergamo, Dipartimento di Ingegneria Industriale, Via Marconi 5, I-24044 Dalmine (Bulgaria) (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy)

2010-12-11

A fine pitch, deep N-well CMOS monolithic active pixel sensor (DNW CMOS MAPS) with sparsified readout architecture and time stamping capabilities has been designed in a vertical integration (3D) technology. In this process, two 130 nm CMOS wafers are face-to-face bonded by means of thermo-compression techniques ensuring both the mechanical stability of the structure and the electrical interconnection between circuits belonging to different layers. This 3D design represents the evolution of a DNW monolithic sensor already fabricated in a planar 130 nm CMOS technology in view of applications to the vertex detector of the International Linear Collider (ILC). The paper is devoted to discussing the main design features and expected performance of the 3D DNW MAPS. Besides describing the front-end circuits and the general architecture of the detector, the work also provides some results from calculations and Monte Carlo device simulations comparing the old 2D solution with the new 3D one and illustrating the attainable detection efficiency improvements.

CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

Directory of Open Access Journals (Sweden)

Jose Luis Muñoz-Gamarra

2016-02-01

Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

Test beam results of a depleted monolithic active pixel sensor (DMAPS) prototype

Energy Technology Data Exchange (ETDEWEB)

Obermann, Theresa; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Bonn Univ. (Germany); Schwenker, Benjamin [Goettingen Univ. (Germany); Collaboration: ATLAS Pixel-Collaboration

2016-07-01

New monolithic detector concepts are currently being explored for future particle physics experiments, in particular for the upgrade of the ATLAS detector. Common to monolithic pixel detectors is the integration of the front-end circuitry and the sensor on the same silicon substrate. The DMAPS concept makes use of high resistive silicon as substrate. It enables the application of a high bias voltage to create a drift field for the charge collection in the sensor part as well as the full usage of CMOS logic in the same piece of silicon. DMAPS prototypes from several foundries are available since three years and have been extensively characterized in the lab. In this talk, results of test beam campaigns, with neutron irradiated prototypes implemented in the ESPROS process, are presented.

Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

Energy Technology Data Exchange (ETDEWEB)

Obermann, Theresa

2017-06-15

The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 μm thickness, were characterized. The prototypes have 352 square pixels of 40 μm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n{sup +}-implantation size: 5 μm x 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e{sup -} to 3000 e{sup -} while the noise is 30 e{sup -} due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5 x 10{sup 14} neutrons/cm{sup 2} the performance suffers from the radiation damage leading to a signal of 1000 e{sup -} and a higher noise of 60 e{sup -} due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5 x 10{sup 14} particles/cm{sup 2}. Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (< 1 x 10{sup 14} particles/cm{sup 2}). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Risti{c}, Branislav; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

CMOS Pixel Development for the ATLAS Experiment at HL-LHC

CERN Document Server

Gaudiello, Andrea; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

NARCIS (Netherlands)

Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

2011-01-01

We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

Micromachined high-performance RF passives in CMOS substrate

International Nuclear Information System (INIS)

Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

2016-01-01

This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

Monolithic pixels on moderate resistivity substrate and sparsifying readout architecture

CERN Document Server

Giubilato, P; Snoeys, W; Bisello, D; Marchioro, A; Battaglia, M; Demaria, L; Mansuy, S C; Pantano, D; Rousset, J; Mattiazzo, S; Kloukinas, K; Potenza, A; Ikemoto, Y; Rivetti, A; Chalmet, P; Mugnier, H; Silvestrin, L

2013-01-01

The LePix projects aim realizing a new generation monolithic pixel detectors with improved performances at lesser cost with respect to both current state of the art monolithic and hybrid pixel sensors. The detector is built in a 90 nm CMOS process on a substrate of moderate resistivity. This allows charge collection by drift while maintaining the other advantages usually offered by MAPS, like having a single piece detector and using a standard CMOS production line. The collection by drift mechanism, coupled to the low capacitance design of the collecting node made possible by the monolithic approach, provides an excellent signal to noise ratio straight at the pixel cell together with a radiation tolerance far superior to conventional un-depleted MAPS. The excellent signal-to-noise performance is demonstrated by the device ability to separate the 6 keV Fe-55 double peak at room temperature. To achieve high granularity (10-20 mu m pitch pixels) over large detector areas maintaining high readout speed, a complet...

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

Science.gov (United States)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

NARCIS (Netherlands)

Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

2011-01-01

We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

Depleted Monolithic Pixels (DMAPS) in a 150 nm technology: lab and beam results

International Nuclear Information System (INIS)

Obermann, T.; Hemperek, T.; Hügging, F.; Krüger, H.; Pohl, D.-L.; Wermes, N.; Schwenker, B.

2017-01-01

The fully depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a fully depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and high resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, were developed in a 150 nm process on a high resistive n-type wafer of 50 μm thickness. The prototypes have 352 square pixels of 40 μm pitch and small n-well charge collection node with very low capacitance (n + -implantation size: 5 μm by 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part).

Monolithic active pixel sensor development for the upgrade of the ALICE inner tracking system

Science.gov (United States)

Aglieri, G.; Cavicchioli, C.; Chalmet, P. L.; Chanlek, N.; Collu, A.; Giubilato, P.; Hillemanns, H.; Junique, A.; Keil, M.; Kim, D.; Kim, J.; Kugathasan, T.; Lattuca, A.; Mager, M.; Marin Tobon, C. A.; Marras, D.; Martinengo, P.; Mattiazzo, S.; Mazza, G.; Mugnier, H.; Musa, L.; Pantano, D.; Puggioni, C.; Rousset, J.; Reidt, F.; Riedler, P.; Siddhanta, S.; Snoeys, W.; Usai, G.; van Hoorne, J. W.; Yang, P.; Yi, J.

2013-12-01

ALICE plans an upgrade of its Inner Tracking System for 2018. The development of a monolithic active pixel sensor for this upgrade is described. The TowerJazz 180 nm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel due to the offering of a deep pwell and also to use different starting materials. The ALPIDE development is an alternative to approaches based on a rolling shutter architecture, and aims to reduce power consumption and integration time by an order of magnitude below the ALICE specifications, which would be quite beneficial in terms of material budget and background. The approach is based on an in-pixel binary front-end combined with a hit-driven architecture. Several prototypes have already been designed, submitted for fabrication and some of them tested with X-ray sources and particles in a beam. Analog power consumption has been limited by optimizing the Q/C of the sensor using Explorer chips. Promising but preliminary first results have also been obtained with a prototype ALPIDE. Radiation tolerance up to the ALICE requirements has also been verified.

Monolithic active pixel sensor development for the upgrade of the ALICE inner tracking system

International Nuclear Information System (INIS)

Aglieri, G; Cavicchioli, C; Hillemanns, H; Junique, A; Keil, M; Kugathasan, T; Mager, M; Tobon, C A Marin; Martinengo, P; Chalmet, P L; Mugnier, H; Chanlek, N; Collu, A; Marras, D; Giubilato, P; Mattiazzo, S; Kim, D; Kim, J; Lattuca, A; Mazza, G

2013-01-01

ALICE plans an upgrade of its Inner Tracking System for 2018. The development of a monolithic active pixel sensor for this upgrade is described. The TowerJazz 180 nm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel due to the offering of a deep pwell and also to use different starting materials. The ALPIDE development is an alternative to approaches based on a rolling shutter architecture, and aims to reduce power consumption and integration time by an order of magnitude below the ALICE specifications, which would be quite beneficial in terms of material budget and background. The approach is based on an in-pixel binary front-end combined with a hit-driven architecture. Several prototypes have already been designed, submitted for fabrication and some of them tested with X-ray sources and particles in a beam. Analog power consumption has been limited by optimizing the Q/C of the sensor using Explorer chips. Promising but preliminary first results have also been obtained with a prototype ALPIDE. Radiation tolerance up to the ALICE requirements has also been verified

Poly-SiGe for MEMS-above-CMOS sensors

CERN Document Server

Gonzalez Ruiz, Pilar; Witvrouw, Ann

2014-01-01

Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

CMOS-based avalanche photodiodes for direct particle detection

International Nuclear Information System (INIS)

Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

2007-01-01

Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

Device Simulation of Monolithic Active Pixel Sensors: Radiation Damage Effects

International Nuclear Information System (INIS)

Fourches, N.T.

2009-01-01

Vertexing for the future International Linear Collider represents a challenging goal because of the high spatial resolution required with low material budget and high ionizing radiation tolerance. CMOS Monolithic Active Pixel Sensors (MAPS) represent a good potential solution for this purpose. Up to now many MAPS sensors have been developed. They are based on various architectures and manufactured in different processes. However, up so far, the sensor diode has not been the subject of extensive modelization and simulation. Published simulation studies of sensor-signal formation have been less numerous than measurements on real sensors. This is a cause for concern because such sensor is physically based on the partially depleted diode, in the vicinity of which the electric field collects the minority carriers generated by an incident MIP (minimum ionizing particle). Although the microscopic mechanisms are well known and modelled, the global physical mechanisms for signal formation are not very rigorously established. This is partly due to the presence of a predominant diffusion component in the charge transport. We present here simulations mainly based on the S-PISCES code, in which physical mechanisms affecting transport are taken into account. Diffusion, influence of residual carrier concentration due to the doping level in the sensitive volume, and more importantly charge trapping due to deep levels in the active (detecting) layer are studied together with geometric aspects. The effect of neutron irradiation is studied to assess the effects of deep traps. A comparison with available experimental data, obtained on processed MAPS before or after neutron irradiation will be introduced. Simulated reconstruction of the Minimum Ionizing Particle (MIP) point of impact in two dimensions is also investigated. For further steps, guidelines for process choices of next Monolithic Active Pixel Sensors are introduced. (authors)

Low noise monolithic CMOS front end electronics

International Nuclear Information System (INIS)

Lutz, G.; Bergmann, H.; Holl, P.; Manfredi, P.F.

1987-01-01

Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

JPL CMOS Active Pixel Sensor Technology

Science.gov (United States)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

InGaAsP Mach-Zehnder interferometer optical modulator monolithically integrated with InGaAs driver MOSFET on a III-V CMOS photonics platform.

Science.gov (United States)

Park, Jin-Kown; Takagi, Shinichi; Takenaka, Mitsuru

2018-02-19

We demonstrated the monolithic integration of a carrier-injection InGaAsP Mach-Zehnder interferometer (MZI) optical modulator and InGaAs metal-oxide-semiconductor field-effect transistor (MOSFET) on a III-V-on-insulator (III-V-OI) wafer. A low-resistivity lateral PIN junction was formed along an InGaAsP rib waveguide by Zn diffusion and Ni-InGaAsP alloy, enabling direct driving of the InGaAsP optical modulator by the InGaAs MOSFET. A π phase shift of the InGaAsP optical modulator was obtained through the injection of a drain current from the InGaAs MOSFET with a gate voltage of approximately 1 V. This proof-of-concept demonstration of the monolithic integration of the InGaAsP optical modulator and InGaAs driver MOSFET will enable us to develop high-performance and low-power electronic-photonic integrated circuits on a III-V CMOS photonics platform.

Photon imaging using post-processed CMOS chips

NARCIS (Netherlands)

Melai, J.

2010-01-01

This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic

Broadband image sensor array based on graphene-CMOS integration

Science.gov (United States)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

International Nuclear Information System (INIS)

Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

2014-01-01

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

Science.gov (United States)

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

LePix—A high resistivity, fully depleted monolithic pixel detector

International Nuclear Information System (INIS)

Giubilato, P.; Bisello, D.; Chalmet, P.; Denes, P.; Kloukinas, K.; Mattiazzo, S.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rivetti, A.; Rousset, J.; Snoeys, W.; Tindall, C.

2013-01-01

The LePix project explores monolithic pixel sensors fabricated in a 90 nm CMOS technology built over a lightly doped substrate. This approach keeps the advantages usually offered by Monolithic Active Pixel Sensors (MAPS), like a low input capacitance, having a single piece detector and using a standard CMOS production line, and adds the benefit of charge collection by drift from a depleted region several tens of microns deep into the substrate, therefore providing an excellent signal to noise ratio and a radiation tolerance superior to conventional un-depleted MAPS. Such sensors are expected to offer significant cost savings and reduction of power consumption for the same performance, leading to the use of much less material in the detector (less cooling and less copper), addressing one of the main limitations of present day particle tracking systems. The latest evolution of the project uses detectors thinned down to 50 μm to obtain back illuminated sensors operated in full depletion mode. By back-processing the chip and collecting the charge from the full substrate it is hence possible to efficiently detect soft X-rays up to 10 keV. Test results from first successfully processed detectors will be presented and discussed

Integration trends in monolithic power ICs: Application and technology challenges

NARCIS (Netherlands)

Rose, M.; Bergveld, H.J.

2016-01-01

This paper highlights the general trend towards further monolithic integration in power applications by enabling power management and interfacing solutions in advanced CMOS nodes. The need to combine high-density digital circuits, power-management circuits, and robust interfaces in a single

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

International Nuclear Information System (INIS)

Zheng Renliang; Jiang Xudong; Yao Wang; Yang Guang; Yin Jiangwei; Zheng Jianqin; Ren Junyan; Li Wei; Li Ning

2010-01-01

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented. The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA, a I/Q merged quadrature mixer, a fifth-order Gm-C bi-quad Chebyshev LPF/VGA, a fast-settling frequency synthesizer with a poly-phase filter, a linear broadband up-conversion quadrature modulator, an active D2S converter and a variable-gain power amplifier. The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm 2 and draws a total current of 221 mA from 1.8-V supply. The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step, noise figures of 5.5-8.8 dB for three sub-bands, and an in-band/out-band IIP3 better than -4 dBm/+9 dBm. The transmitter achieves an output power ranging from -10.7 to -3 dBm with gain control, an output P 1dB better than -7.7 dBm, a sideband rejection about 32.4 dBc, and LO suppression of 31.1 dBc. The hopping time among sub-bands is less than 2.05 ns. (semiconductor integrated circuits)

Radiation hardness of two CMOS prototypes for the ATLAS HL-LHC upgrade project

CERN Document Server

Huffman, B T; Arndt, K; Bates, R; Benoit, M; Di Bello, F; Blue, A; Bortoletto, D; Buckland, M; Buttar, C; Caragiulo, P; Das, D; Dopke, J; Dragone, A; Ehrler, F; Fadeyev, V; Galloway, Z; Grabas, H; Gregor, I M; Grenier, P; Grillo, A; Hoeferkamp, M; Hommels, L B A; John, J; Kanisauskas, K; Kenney, C; Kramberger, J; Liang, Z; Mandic, I; Maneuski, D; Martinez-McKinney, F; McMahon, S; Meng, L; Mikuž, M; Muenstermann, D; Nickerson, R; Peric, I; Phillips, P; Plackett, R; Rubbo, F; Segal, J; Seidel, S; Seiden, A; Shipsey, I; Song, W; Stanitzki, M; Su, D; Tamma, C; Turchetta, R; Vigani, L; olk, J; Wang, R; Warren, M; Wilson, F; Worm, S; Xiu, Q; Zhang, J; Zhu, H

2016-01-01

The LHC luminosity upgrade, known as the High Luminosity LHC (HL-LHC), will require the replacement of the existing silicon strip tracker and the transistion radiation tracker. Although a baseline design for this tracker exists the ATLAS collaboration and other non-ATLAS groups are exploring the feasibility of using CMOS Monolithic Active Pixel Sensors (MAPS) which would be arranged in a strip-like fashion and would take advantage of the service and support structure already being developed for the upgrade. Two test devices made with theAMSH35 process (a High voltage or HV CMOS process) have been subjected to various radiation environments and have performed well. The results of these tests are presented in this paper.

Activated Carbon Fiber Monoliths as Supercapacitor Electrodes

Directory of Open Access Journals (Sweden)

Gelines Moreno-Fernandez

2017-01-01

Full Text Available Activated carbon fibers (ACF are interesting candidates for electrodes in electrochemical energy storage devices; however, one major drawback for practical application is their low density. In the present work, monoliths were synthesized from two different ACFs, reaching 3 times higher densities than the original ACFs’ apparent densities. The porosity of the monoliths was only slightly decreased with respect to the pristine ACFs, the employed PVDC binder developing additional porosity upon carbonization. The ACF monoliths are essentially microporous and reach BET surface areas of up to 1838 m2 g−1. SEM analysis reveals that the ACFs are well embedded into the monolith structure and that their length was significantly reduced due to the monolith preparation process. The carbonized monoliths were studied as supercapacitor electrodes in two- and three-electrode cells having 2 M H2SO4 as electrolyte. Maximum capacitances of around 200 F g−1 were reached. The results confirm that the capacitance of the bisulfate anions essentially originates from the double layer, while hydronium cations contribute with a mixture of both, double layer capacitance and pseudocapacitance.

Characterization of active CMOS sensors for capacitively coupled pixel detectors

Energy Technology Data Exchange (ETDEWEB)

Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

2015-07-01

Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

Research and Development of Monolithic Active Pixel Sensors for the Detection of the Elementary Particles; Recherche et developpement de capteurs actifs monolithiques CMOS pour la detection de particules elementaires

Energy Technology Data Exchange (ETDEWEB)

Li, Y

2007-09-15

In order to develop high spatial resolution and readout speed vertex detectors for the future International Linear Collider (ILC), fast CMOS Monolithic Active Pixel Sensors (MAPS) are studied on this work. Two prototypes of MAPS, MIMOSA 8 and MIMOSA 16, based on the same micro-electronic architecture were developed in CMOS processes with different thickness of epitaxial layer. The size of pixel matrix is 32 x 128: 8 columns of the pixel array are readout directly with analog outputs and the other 24 columns are connected to the column level auto-zero discriminators. The Correlated Double Sampling (CDS) structures are successfully implemented inside pixel and discriminator. The photo diode type pixels with different diode sizes are used in these prototypes. With a {sup 55}Fe X-ray radioactive source, the important parameters, such as Temporal Noise, Fixed Pattern Noise (FPN), Signal-to-Noise Ratio (SNR), Charge-to-Voltage conversion Factor (CVF) and Charge Collection Efficiency (CCE), are studied as function of readout speed and diode size. For MIMOSA 8, the effect of fast neutrons irradiation is also. Two beam tests campaigns were made: at DESY with a 5 GeV electrons beam and at CERN with a 180 GeV pions beam. Detection Efficiency and Spatial Resolution are studied in function of the discriminator threshold. For these two parameters, the influences of diode size and SNR of the central pixel of a cluster are also discussed. In order to improve the spatial resolution of the digital outputs, a very compact (25 {mu}m x 1 mm) and low consumption (300 {mu}W) column level ADC is designed in AMS 0.35 {mu}m OPTO process. Based on successive approximation architecture, the auto-offset cancellation structure is integrated. A new column level auto-zero discriminator using static latch is also designed. (author)

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

Science.gov (United States)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

A 60-GHz rectenna for monolithic wireless sensor tags

NARCIS (Netherlands)

Gao, H.; Johannsen, U.; Matters - Kammerer, M.; Milosevic, D.; Smolders, A.B.; Roermund, van A.H.M.; Baltus, P.G.M.

2013-01-01

This paper presents the design of a 60-GHz rectenna with an on-chip antenna and rectifier in 65nm CMOS technology. The rectenna is often the bottleneck in realizing a fully-integrated monolithic wireless sensor tag. In this paper, problems of the mm-wave rectifier are discussed, and the

Recent progress in the development of a B-factory monolithic active pixel detector

International Nuclear Information System (INIS)

Stanic, S.; Aihara, H.; Barbero, M.; Bozek, A.; Browder, T.; Hazumi, M.; Kennedy, J.; Kent, N.; Olsen, S.; Palka, H.; Rosen, M.; Ruckman, L.; Trabelsi, K.; Tsuboyama, T.; Uchida, K.; Varner, G.; Yang, Q.

2006-01-01

Due to the need for precise vertexing at future higher luminosity B-factories with the expectedly increasing track densities and radiation exposures, upgrade of present silicon strip detectors with thin, radiation resistant pixel detectors is highly desired. Considerable progress in the technological development of thin CMOS based Monolithic Active Pixel Sensors (MAPS) in the last years makes them a realistic upgrade option and the feasibility studies of their application in Belle are actively pursued. The most serious concerns are their radiation hardness and their read-out speed. To address them, several prototypes denoted as Continuous Acquisition Pixel (CAP) sensors have been developed and tested. The latest of the CAP sensor prototypes is CAP3, designed in the TSMC 0.25μm process with a 5-deep sample pair pipeline in each pixel. A setup with several CAP3 sensors will be used to assess the performance of a full scale pixel read-out system running at realistic read-out speed. The results and plans for the next stages of R and D towards a full Pixel Vertex Detector (PVD) are presented

ALPIDE: the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

International Nuclear Information System (INIS)

Šuljić, M.

2016-01-01

The upgrade of the ALICE vertex detector, the Inner Tracking System (ITS), is scheduled to be installed during the next long shutdown period (2019-2020) of the CERN Large Hadron Collider (LHC) . The current ITS will be replaced by seven concentric layers of Monolithic Active Pixel Sensors (MAPS) with total active surface of ∼10 m 2 , thus making ALICE the first LHC experiment implementing MAPS detector technology on a large scale. The ALPIDE chip, based on TowerJazz 180 nm CMOS Imaging Process, is being developed for this purpose. A particular process feature, the deep p-well, is exploited so the full CMOS logic can be implemented over the active sensor area without impinging on the deposited charge collection. ALPIDE is implemented on silicon wafers with a high resistivity epitaxial layer. A single chip measures 15 mm by 30 mm and contains half a million pixels distributed in 512 rows and 1024 columns. In-pixel circuitry features amplification, shaping, discrimination and multi-event buffering. The readout is hit driven i.e. only addresses of hit pixels are sent to the periphery. The upgrade of the ITS presents two different sets of requirements for sensors of the inner and of the outer layers due to the significantly different track density, radiation level and active detector surface. The ALPIDE chip fulfils the stringent requirements in both cases. The detection efficiency is higher than 99%, fake-hit probability is orders of magnitude lower than the required 10 −6 and spatial resolution within the required 5 μm. This performance is to be maintained even after a total ionising does (TID) of 2.7 Mrad and a non-ionising energy loss (NIEL) fluence of 1.7 × 10 13 1 MeV n eq /cm 2 , which is above what is expected during the detector lifetime. Readout rate of 100 kHz is provided and the power density of ALPIDE is less than 40 mW/cm 2 . This contribution will provide a summary of the ALPIDE features and main test results.

ALPIDE: the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

Science.gov (United States)

Šuljić, M.

2016-11-01

The upgrade of the ALICE vertex detector, the Inner Tracking System (ITS), is scheduled to be installed during the next long shutdown period (2019-2020) of the CERN Large Hadron Collider (LHC) . The current ITS will be replaced by seven concentric layers of Monolithic Active Pixel Sensors (MAPS) with total active surface of ~10 m2, thus making ALICE the first LHC experiment implementing MAPS detector technology on a large scale. The ALPIDE chip, based on TowerJazz 180 nm CMOS Imaging Process, is being developed for this purpose. A particular process feature, the deep p-well, is exploited so the full CMOS logic can be implemented over the active sensor area without impinging on the deposited charge collection. ALPIDE is implemented on silicon wafers with a high resistivity epitaxial layer. A single chip measures 15 mm by 30 mm and contains half a million pixels distributed in 512 rows and 1024 columns. In-pixel circuitry features amplification, shaping, discrimination and multi-event buffering. The readout is hit driven i.e. only addresses of hit pixels are sent to the periphery. The upgrade of the ITS presents two different sets of requirements for sensors of the inner and of the outer layers due to the significantly different track density, radiation level and active detector surface. The ALPIDE chip fulfils the stringent requirements in both cases. The detection efficiency is higher than 99%, fake-hit probability is orders of magnitude lower than the required 10-6 and spatial resolution within the required 5 μm. This performance is to be maintained even after a total ionising does (TID) of 2.7 Mrad and a non-ionising energy loss (NIEL) fluence of 1.7 × 1013 1 MeV neq/cm2, which is above what is expected during the detector lifetime. Readout rate of 100 kHz is provided and the power density of ALPIDE is less than 40 mW/cm2. This contribution will provide a summary of the ALPIDE features and main test results.

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

Science.gov (United States)

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process

Energy Technology Data Exchange (ETDEWEB)

Hemperek, Tomasz, E-mail: hemperek@uni-bonn.de; Kishishita, Tetsuichi; Krüger, Hans; Wermes, Norbert

2015-10-01

An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.

Monolithic pixels on moderate resistivity substrate and sparsifying readout architecture

International Nuclear Information System (INIS)

Giubilato, P.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Demaria, L.; Ikemoto, Y.; Kloukinas, K.; Mansuy, S.C.; Mattiazzo, S.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rivetti, A.; Rousset, J.; Silvestrin, L.; Snoeys, W.

2013-01-01

The LePix projects aim realizing a new generation monolithic pixel detectors with improved performances at lesser cost with respect to both current state of the art monolithic and hybrid pixel sensors. The detector is built in a 90 nm CMOS process on a substrate of moderate resistivity. This allows charge collection by drift while maintaining the other advantages usually offered by MAPS, like having a single piece detector and using a standard CMOS production line. The collection by drift mechanism, coupled to the low capacitance design of the collecting node made possible by the monolithic approach, provides an excellent signal to noise ratio straight at the pixel cell together with a radiation tolerance far superior to conventional un-depleted MAPS. The excellent signal-to-noise performance is demonstrated by the device ability to separate the 6 keV 55 Fe double peak at room temperature. To achieve high granularity (10–20 µm pitch pixels) over large detector areas maintaining high readout speed, a completely new compressing architecture has been devised. This architecture departs from the mainstream hybrid pixel sparsification approach, which uses in-pixel logic to reduce data, by using topological compression to minimize pixel area and power consumption

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-{mu}m CMOS

Energy Technology Data Exchange (ETDEWEB)

Zheng Renliang; Jiang Xudong; Yao Wang; Yang Guang; Yin Jiangwei; Zheng Jianqin; Ren Junyan; Li Wei; Li Ning, E-mail: jyren@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

2010-06-15

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented. The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA, a I/Q merged quadrature mixer, a fifth-order Gm-C bi-quad Chebyshev LPF/VGA, a fast-settling frequency synthesizer with a poly-phase filter, a linear broadband up-conversion quadrature modulator, an active D2S converter and a variable-gain power amplifier. The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-{mu}m RF CMOS with an area of 6.1 mm{sup 2} and draws a total current of 221 mA from 1.8-V supply. The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step, noise figures of 5.5-8.8 dB for three sub-bands, and an in-band/out-band IIP3 better than -4 dBm/+9 dBm. The transmitter achieves an output power ranging from -10.7 to -3 dBm with gain control, an output P{sub 1dB} better than -7.7 dBm, a sideband rejection about 32.4 dBc, and LO suppression of 31.1 dBc. The hopping time among sub-bands is less than 2.05 ns. (semiconductor integrated circuits)

Development of a thinned back-illuminated CMOS active pixel sensor for extreme ultraviolet spectroscopy and imaging in space science

International Nuclear Information System (INIS)

Waltham, N.R.; Prydderch, M.; Mapson-Menard, H.; Pool, P.; Harris, A.

2007-01-01

We describe our programme to develop a large-format, science-grade, monolithic CMOS active pixel sensor for future space science missions, and in particular an extreme ultraviolet (EUV) spectrograph for solar physics studies on ESA's Solar Orbiter. Our route to EUV sensitivity relies on adapting the back-thinning and rear-illumination techniques first developed for CCD sensors. Our first large-format sensor consists of 4kx3k 5 μm pixels fabricated on a 0.25 μm CMOS imager process. Wafer samples of these sensors have been thinned by e2v technologies with the aim of obtaining good sensitivity at EUV wavelengths. We present results from both front- and back-illuminated versions of this sensor. We also present our plans to develop a new sensor of 2kx2k 10 μm pixels, which will be fabricated on a 0.35 μm CMOS process. In progress towards this goal, we have designed a test-structure consisting of six arrays of 512x512 10 μm pixels. Each of the arrays has been given a different pixel design to allow verification of our models, and our progress towards optimizing a design for minimal system readout noise and maximum dynamic range. These sensors will also be back-thinned for characterization at EUV wavelengths

New generation of monolithic active pixel sensors for charged particle detection

International Nuclear Information System (INIS)

Deptuch, G.

2002-09-01

Vertex detectors are of great importance in particle physics experiments, as the knowledge of the event flavour is becoming an issue for the physics programme at Future Linear Colliders. Monolithic Active Pixel Sensors (MAPS) based on a novel detector structure have been proposed. Their fabrication is compatible with a standard CMOS process. The sensor is inseparable from the readout electronics, since both of them are integrated on the same, low-resistivity silicon wafer. The basic pixel configuration comprises only three MOS transistors and a diode collecting the charge through thermal diffusion. The charge is generated in the thin non-depleted epitaxial layer underneath the readout electronics. This approach provides, at low cost, a high resolution and thin device with the whole area sensitive to radiation. Device simulations using the ISE-TCAD package have been carried out to study the charge collection mechanism. In order to demonstrate the viability of the technique, four prototype chips have been fabricated using different submicrometer CMOS processes. The pixel gain has been calibrated using a 55 Fe source and the Poisson sequence method. The prototypes have been exposed to high-energy particle beams at CERN. The tests proved excellent detection performances expressed in a single-track spatial resolution of 1.5 μm and detection efficiency close to 100%, resulting from a SNR ratio of more than 30. Irradiation tests showed immunity of MAPS to a level of a few times 10 12 n/cm 2 and a few hundred kRad of ionising radiation. The ideas for future work, including on-pixel signal amplification, double sampling operation and current mode pixel design are present as well. (author)

A Single-Transistor Active Pixel CMOS Image Sensor Architecture

International Nuclear Information System (INIS)

Zhang Guo-An; He Jin; Zhang Dong-Wei; Su Yan-Mei; Wang Cheng; Chen Qin; Liang Hai-Lang; Ye Yun

2012-01-01

A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology

CMOS MAPS in a Homogeneous 3D Process for Charged Particle Tracking

CERN Document Server

Manazza, A; Manghisoni, M; Re, V; Traversi, G; Bettarini, S; Forti, F; Morsani, F; Rizzo, G; 10.1109/TNS.2014.2299341

2014-01-01

This work presents the characterization of deep n-well (DNW) CMOS monolithic active pixel sensors (MAPS) fabricated in a 130 nm homogeneous, vertically integrated technology. An evaluation of the 3D MAPS device performance, designed for application of the experiments at the future high luminosity colliders, is provided through the characterization of the prototypes, including tests with infrared (IR) laser, 55Fe and 90Sr sources. The radiation hardness study of the technology will also be presented together with its impact on 3D DNW MAPS performance.

Characterization of active CMOS pixel sensors on high resistive substrate

Energy Technology Data Exchange (ETDEWEB)

Hirono, Toko; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Bonn (Germany)

2016-07-01

Active CMOS pixel sensors are very attractive as radiation imaging pixel detector because they do not need cost-intensive fine pitch bump bonding. High radiation tolerance and time resolution are required to apply those sensors to upcoming particle physics experiments. To achieve these requirements, the active CMOS pixel sensors were developed on high resistive substrates. Signal charges are collected faster by drift in high resistive substrates than in standard low resistive substrates yielding also a higher radiation tolerance. A prototype of the active CMOS pixel sensor has been fabricated in the LFoundry 150 nm CMOS process on 2 kΩcm substrate. This prototype chip was thinned down to 300 μm and the backside has been processed and can contacted by an aluminum contact. The breakdown voltage is around -115 V, and the depletion width has been measured to be as large as 180 μm at a bias voltage of -110 V. Gain and noise of the readout circuitry agree with the designed values. Performance tests in the lab and test beam have been done before and after irradiation with X-rays and neutrons. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

Electromagnetic Investigation of a CMOS MEMS Inductive Microphone

Directory of Open Access Journals (Sweden)

Farès TOUNSI

2009-09-01

Full Text Available This paper presents a detailed electromagnetic modeling for a new structure of a monolithic CMOS micromachined inductive microphone. We have shown, that the use of an alternative current (AC in the primary fixed inductor results in a substantially higher induced voltage in the secondary inductor comparing to the case when a direct current (DC is used. The expected increase of the induced voltage can be expressed by a voltage ratio of AC and DC solutions that is in the range of 3 to 6. A prototype fabrication of this microphone has been realized using a combination of standard CMOS 0.6 µm process with a CMOS-compatible post-process consisting in a bulk micromachining technology. The output voltage of the electrodynamic microphone that achieves the µV range can be increased by the use of the symmetric dual-layer spiral inductor structure.

Surface characteristics and antibacterial activity of a silver-doped carbon monolith

Directory of Open Access Journals (Sweden)

Marija Vukčević et al

2008-01-01

Full Text Available A carbon monolith with a silver coating was prepared and its antimicrobial behaviour in a flow system was examined. The functional groups on the surface of the carbon monolith were determined by temperature-programmed desorption and Boehm's method, and the point of zero charge was determined by mass titration. The specific surface area was examined by N2 adsorption using the Brunauer, Emmett and Teller (BET method. As a test for the surface activity, the deposition of silver from an aqueous solution of a silver salt was used. The morphology and structure of the silver coatings were characterized by scanning electron microscopy and x-ray diffraction. The resistance to the attrition of the silver deposited on the carbon monolith was tested. The antimicrobial activity of the carbon monolith with a silver coating was determined using standard microbiological methods. Carbon monolith samples with a silver coating showed good antimicrobial activity against Escherichia coli, Staphylococcus aureus and Candida albicans, and are therefore suitable for water purification, particularly as personal disposable water filters with a limited capacity.

A monolithic active pixel sensor for ionizing radiation using a 180 nm HV-SOI process

Energy Technology Data Exchange (ETDEWEB)

Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn, Bonn (Germany)

2016-07-01

An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-180 nm High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. Standard FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to trapped charge in the buried oxide layer and charged interface states created at the silicon oxide boundaries (back gate effect). The X-FAB 180 nm HV-SOI technology offers an additional isolation using a deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection. The design and measurement results from first prototypes are presented including radiation tolerance to total ionizing dose and charge collection properties of neutron irradiated samples.

A monolithic pixel sensor (TRAPPISTe-2) for particle physics instrumentation in OKI 0.2μm SOI technology

Science.gov (United States)

Soung Yee, L.; Alvarez, P.; Martin, E.; Cortina, E.; Ferrer, C.

2012-12-01

A monolithic active pixel sensor for charged particle tracking has been developed within the frame of a research and development project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology). TRAPPISTe aims to study the feasibility of developing a monolithic pixel sensor with SOI technology. TRAPPISTe-2 is the second prototype in this series and was fabricated with an OKI 0.20μm fully depleted (FD-SOI) CMOS process. This device contains test transistors and amplifiers, as well as two pixel matrices with integrated 3-transistor and amplifier readout electronics. The results presented are based on the first electrical measurements performed on the test structures and laser measurements on the pixel matrices.

Monolithic Ge-on-Si lasers for large-scale electronic-photonic integration

Science.gov (United States)

Liu, Jifeng; Kimerling, Lionel C.; Michel, Jurgen

2012-09-01

A silicon-based monolithic laser source has long been envisioned as a key enabling component for large-scale electronic-photonic integration in future generations of high-performance computation and communication systems. In this paper we present a comprehensive review on the development of monolithic Ge-on-Si lasers for this application. Starting with a historical review of light emission from the direct gap transition of Ge dating back to the 1960s, we focus on the rapid progress in band-engineered Ge-on-Si lasers in the past five years after a nearly 30-year gap in this research field. Ge has become an interesting candidate for active devices in Si photonics in the past decade due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS) processing. In 2007, we proposed combing tensile strain with n-type doping to compensate the energy difference between the direct and indirect band gap of Ge, thereby achieving net optical gain for CMOS-compatible diode lasers. Here we systematically present theoretical modeling, material growth methods, spontaneous emission, optical gain, and lasing under optical and electrical pumping from band-engineered Ge-on-Si, culminated by recently demonstrated electrically pumped Ge-on-Si lasers with >1 mW output in the communication wavelength window of 1500-1700 nm. The broad gain spectrum enables on-chip wavelength division multiplexing. A unique feature of band-engineered pseudo-direct gap Ge light emitters is that the emission intensity increases with temperature, exactly opposite to conventional direct gap semiconductor light-emitting devices. This extraordinary thermal anti-quenching behavior greatly facilitates monolithic integration on Si microchips where temperatures can reach up to 80 °C during operation. The same band-engineering approach can be extended to other pseudo-direct gap semiconductors, allowing us to achieve efficient light emission at wavelengths previously

Monolithic Ge-on-Si lasers for large-scale electronic–photonic integration

International Nuclear Information System (INIS)

Liu, Jifeng; Kimerling, Lionel C; Michel, Jurgen

2012-01-01

A silicon-based monolithic laser source has long been envisioned as a key enabling component for large-scale electronic–photonic integration in future generations of high-performance computation and communication systems. In this paper we present a comprehensive review on the development of monolithic Ge-on-Si lasers for this application. Starting with a historical review of light emission from the direct gap transition of Ge dating back to the 1960s, we focus on the rapid progress in band-engineered Ge-on-Si lasers in the past five years after a nearly 30-year gap in this research field. Ge has become an interesting candidate for active devices in Si photonics in the past decade due to its pseudo-direct gap behavior and compatibility with Si complementary metal oxide semiconductor (CMOS) processing. In 2007, we proposed combing tensile strain with n-type doping to compensate the energy difference between the direct and indirect band gap of Ge, thereby achieving net optical gain for CMOS-compatible diode lasers. Here we systematically present theoretical modeling, material growth methods, spontaneous emission, optical gain, and lasing under optical and electrical pumping from band-engineered Ge-on-Si, culminated by recently demonstrated electrically pumped Ge-on-Si lasers with >1 mW output in the communication wavelength window of 1500–1700 nm. The broad gain spectrum enables on-chip wavelength division multiplexing. A unique feature of band-engineered pseudo-direct gap Ge light emitters is that the emission intensity increases with temperature, exactly opposite to conventional direct gap semiconductor light-emitting devices. This extraordinary thermal anti-quenching behavior greatly facilitates monolithic integration on Si microchips where temperatures can reach up to 80 °C during operation. The same band-engineering approach can be extended to other pseudo-direct gap semiconductors, allowing us to achieve efficient light emission at wavelengths previously

Low power wide spectrum optical transmitter using avalanche mode LEDs in SOI CMOS technology

NARCIS (Netherlands)

Agarwal, V.; Dutta, S; Annema, AJ; Hueting, RJE; Steeneken, P.G.; Nauta, B

2017-01-01

This paper presents a low power monolithically integrated optical transmitter with avalanche mode light emitting diodes in a 140 nm silicon-on-insulator CMOS technology. Avalanche mode LEDs in silicon exhibit wide-spectrum electroluminescence (400 nm < λ < 850 nm), which has a significant

CMOS MEMS capacitive absolute pressure sensor

International Nuclear Information System (INIS)

Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

2013-01-01

This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

Energy Technology Data Exchange (ETDEWEB)

Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica; Tisa, Simone; Zappa, Franco [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy)

2013-12-15

We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

E-Beam Effects on CMOS Active Pixel Sensors

International Nuclear Information System (INIS)

Kang, Dong Ook; Jo, Gyu Seong; Kim, Hyeon Daek; Kim, Hyunk Taek; Kim, Jong Yeol; Kim, Chan Kyu

2011-01-01

Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co 60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

Vertically integrated monolithic pixel sensors for charged particle tracking and biomedical imaging

International Nuclear Information System (INIS)

Ratti, L.; Gaioni, L.; Manghisoni, M.; Re, V.; Traversi, G.

2011-01-01

Three-dimensional monolithic pixel sensors have been designed following the same approach that was exploited for the development of the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous layers fabricated in a 130 nm CMOS technology. One of the two tiers, which are face-to-face bonded, has to be thinned down to about 12μm to expose the through silicon vias connecting the circuits to the back-metal bond pads. As a consequence of the way the two parts of each single chip are designed and fabricated, the prototypes of the 3D monolithic detector will include both samples with a thick substrate underneath the collecting DNW electrode, suitable for charged particle tracking, and samples with a very thin (about 6μm) sensitive volume, which may be used to detect low energy particles in biomedical imaging applications. Device physics simulations have been performed to evaluate the collection properties and detection efficiency of the proposed vertically integrated structures.

Vertically integrated monolithic pixel sensors for charged particle tracking and biomedical imaging

Energy Technology Data Exchange (ETDEWEB)

Ratti, L., E-mail: lodovico.ratti@unipv.it [Universita di Pavia, Dipartimento di Elettronica, Via Ferrata 1, I-27100 Pavia (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy); Gaioni, L. [INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy); Manghisoni, M.; Re, V.; Traversi, G. [Universita di Bergamo, Dipartimento di Ingegneria Industriale, Via Marconi 5, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy)

2011-10-01

Three-dimensional monolithic pixel sensors have been designed following the same approach that was exploited for the development of the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous layers fabricated in a 130 nm CMOS technology. One of the two tiers, which are face-to-face bonded, has to be thinned down to about 12{mu}m to expose the through silicon vias connecting the circuits to the back-metal bond pads. As a consequence of the way the two parts of each single chip are designed and fabricated, the prototypes of the 3D monolithic detector will include both samples with a thick substrate underneath the collecting DNW electrode, suitable for charged particle tracking, and samples with a very thin (about 6{mu}m) sensitive volume, which may be used to detect low energy particles in biomedical imaging applications. Device physics simulations have been performed to evaluate the collection properties and detection efficiency of the proposed vertically integrated structures.

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

International Nuclear Information System (INIS)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.; Todd, R.A.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beam Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF 2 ) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF 2 detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented

Development of readout electronics for monolithic integration with diode strip detectors

International Nuclear Information System (INIS)

Hosticka, B.J.; Wrede, M.; Zimmer, G.; Kemmer, J.; Hofmann, R.; Lutz, G.

1984-03-01

Parallel in - serial out analog readout electronics integrated with silicon strip detectors will bring a reduction of two orders of magnitude in external electronics. The readout concept and the chosen CMOS technology solve the basic problem of low noise and low power requirements. A hybrid solution is an intermediate step towards the final goal of monolithic integration of detector and electronics. (orig.)

Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

KAUST Repository

Lechuga Aranda, Jesus Javier

2016-05-01

Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

Innovative monolithic detector for tri-spectral (THz, IR, Vis) imaging

Science.gov (United States)

Pocas, S.; Perenzoni, M.; Massari, N.; Simoens, F.; Meilhan, J.; Rabaud, W.; Martin, S.; Delplanque, B.; Imperinetti, P.; Goudon, V.; Vialle, C.; Arnaud, A.

2012-10-01

Fusion of multispectral images has been explored for many years for security and used in a number of commercial products. CEA-Leti and FBK have developed an innovative sensor technology that gathers monolithically on a unique focal plane arrays, pixels sensitive to radiation in three spectral ranges that are terahertz (THz), infrared (IR) and visible. This technology benefits of many assets for volume market: compactness, full CMOS compatibility on 200mm wafers, advanced functions of the CMOS read-out integrated circuit (ROIC), and operation at room temperature. The ROIC houses visible APS diodes while IR and THz detections are carried out by microbolometers collectively processed above the CMOS substrate. Standard IR bolometric microbridges (160x160 pixels) are surrounding antenna-coupled bolometers (32X32 pixels) built on a resonant cavity customized to THz sensing. This paper presents the different technological challenges achieved in this development and first electrical and sensitivity experimental tests.

Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

International Nuclear Information System (INIS)

Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P.L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C.A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.

2015-01-01

Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented

Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

Energy Technology Data Exchange (ETDEWEB)

Yang, P., E-mail: yangping0710@126.com [Central China Normal University, Wuhan (China); Aglieri, G.; Cavicchioli, C. [CERN, 1210 Geneva 23 (Switzerland); Chalmet, P.L. [MIND, Archamps (France); Chanlek, N. [Suranaree University of Technology, Nakhon Ratchasima (Thailand); Collu, A. [University of Cagliari, Cagliari (Italy); INFN (Italy); Gao, C. [Central China Normal University, Wuhan (China); Hillemanns, H.; Junique, A. [CERN, 1210 Geneva 23 (Switzerland); Kofarago, M. [CERN, 1210 Geneva 23 (Switzerland); University of Utrecht, Utrecht (Netherlands); Keil, M.; Kugathasan, T. [CERN, 1210 Geneva 23 (Switzerland); Kim, D. [Dongguk and Yonsei University, Seoul (Korea, Republic of); Kim, J. [Pusan National University, Busan (Korea, Republic of); Lattuca, A. [University of Torino, Torino (Italy); INFN (Italy); Marin Tobon, C.A. [CERN, 1210 Geneva 23 (Switzerland); Marras, D. [University of Cagliari, Cagliari (Italy); INFN (Italy); Mager, M.; Martinengo, P. [CERN, 1210 Geneva 23 (Switzerland); Mazza, G. [University of Torino, Torino (Italy); INFN (Italy); and others

2015-06-11

Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented.

Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

Science.gov (United States)

Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P. L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C. A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Puggioni, C.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Siddhanta, S.; Usai, G.; van Hoorne, J. W.; Yi, J.

2015-06-01

Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented.

CMOS Imaging Sensor Technology for Aerial Mapping Cameras

Science.gov (United States)

Neumann, Klaus; Welzenbach, Martin; Timm, Martin

2016-06-01

In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

International Nuclear Information System (INIS)

Traversi, G; Manghisoni, M; Re, V; Gaioni, L; Ratti, L

2011-01-01

Deep N-Well (DNW) Monolithic Active Pixel Sensors (MAPS) have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. In these devices the triple well option, available in deep submicron processes, is exploited to implement analog and digital signal processing at the pixel level. Many prototypes have been fabricated in a planar (2D) 130nm CMOS technology. A new kind of DNW-MAPS, namely Apsel5 3 D, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. The impact of 3D processes on the design and performance of DNW pixel sensors could be large, with significant advantages in terms of detection efficiency, pixel cell size and immunity to cross-talk, therefore complying with the severe constraints set by future HEP experiments.

Experimental observation of the improvement in MTF from backthinning a CMOS direct electron detector

International Nuclear Information System (INIS)

McMullan, G.; Faruqi, A.R.; Henderson, R.; Guerrini, N.; Turchetta, R.; Jacobs, A.; Hoften, G. van

2009-01-01

The advantages of backthinning monolithic active pixel sensors (MAPS) based on complementary metal oxide semiconductor (CMOS) direct electron detectors for electron microscopy have been discussed previously; they include better spatial resolution (modulation transfer function or MTF) and efficiency at all spatial frequencies (detective quantum efficiency or DQE). It was suggested that a 'thin' CMOS detector would have the most outstanding properties because of a reduction in the proportion of backscattered electrons. In this paper we show, theoretically (using Monte Carlo simulations of electron trajectories) and experimentally that this is indeed the case. The modulation transfer functions of prototype backthinned CMOS direct electron detectors have been measured at 300 keV. At zero spatial frequency, in non-backthinned 700-μm-thick detectors, the backscattered component makes up over 40% of the total signal but, by backthinning to 100, 50 or 35 μm, this can be reduced to 25%, 15% and 10%, respectively. For the 35 μm backthinned detector, this reduction in backscatter increases the MTF by 40% for spatial frequencies between 0.1 and 1.0 Nyquist. As discussed in the main text, reducing backscattering in backthinned detectors should also improve DQE.

Development of radiation hard CMOS active pixel sensors for HL-LHC

International Nuclear Information System (INIS)

Pernegger, Heinz

2016-01-01

New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

Directory of Open Access Journals (Sweden)

Mostafa Chakir

2017-01-01

Full Text Available The CMOS Monolithic Active Pixel Sensor (MAPS for the International Linear Collider (ILC vertex detector (VXD expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC. This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor.

Science.gov (United States)

Chakir, Mostafa; Akhamal, Hicham; Qjidaa, Hassan

2017-01-01

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18  μ m CMOS process with a pixel pitch of 35  μ m. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76  μ m 2 . The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/-0.0787 LSB and 0.0811/-0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

Science.gov (United States)

Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

1993-01-01

A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

Power pulsing of the CMOS sensor Mimosa 26

International Nuclear Information System (INIS)

Kuprash, Oleg

2013-01-01

Mimosa 26 is a monolithic active pixel sensor developed by IPHC (Strasbourg) and IRFU (Saclay) as a prototype for the ILC vertex detector studies. The resolution requirements for the ILC tracking detector are very extreme, demanding very low material in the detector, thus only air cooling can be considered. Power consumption has to be reduced as far as possible. The beam structure of the ILC allows the possibility of power pulsing: only for about the 1 ms long bunch train full power is required, and during the 199 ms long pauses between the bunch trains the power can be reduced to a minimum. Not being adapted for the power pulsing, the sensor shows in laboratory tests a good performance under power pulsing. The power pulsing allows to significantly reduce the heating of the chip and divides power consumption approximately by a factor of 6. In this report a summary of power pulsing studies using the digital readout of Mimosa 26 is given. -- Highlights: • First power pulsing studies using digital readout of Mimosa 26 CMOS sensor were done. • Fake hit rates under power pulsing conditions and under normal conditions were compared. • The measurements demonstrate that there is so far no showstopper to operate CMOS pixel sensors in power pulsing mode

Monoliths of activated carbon from coconut shell and impregnation with nickel and copper

International Nuclear Information System (INIS)

Giraldo, Liliana; Moreno, Juan

2008-01-01

A series of different monoliths of activated carbon were prepared from coconut shell By means of chemical activation with phosphoric acid at different concentrations Without using binders or plastics. The monolith that developed the biggest surface area was impregnated by humidic route with solutions of Ni and Cu at different molar relations. The structures were characterized by N2 adsorption at 77 K, and the morphology was explored by means of scanning electron microscopy. The carbonaceous materials obtained, Nickel-Copper-Monolith, were analyzed by Thermal Programmed Reduction (TPR). The experimental results indicated that the activation with the acid generated a micro porosity, with micropores volume between 0.40 and 0.81 cm 3 g-1 and surface areas between 703 and 1450 m 2 g-1, and a good mechanical properties. It shows that, both the copper and the nickel, are fixed to the monolith and TPR's results are interpreted when these molar relation are modified.

Photon detection with CMOS sensors for fast imaging

International Nuclear Information System (INIS)

Baudot, J.; Dulinski, W.; Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N.

2009-01-01

Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e - , and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100μs have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

Science.gov (United States)

Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

2006-01-01

This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

Energy Technology Data Exchange (ETDEWEB)

Traversi, G; Manghisoni, M; Re, V [University of Bergamo, Via Marconi 5, 24044 Dalmine (Italy); Gaioni, L; Ratti, L, E-mail: gianluca.traversi@unibg.it [INFN Pavia, Via Bassi 6, 27100 Pavia (Italy)

2011-01-15

Deep N-Well (DNW) Monolithic Active Pixel Sensors (MAPS) have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. In these devices the triple well option, available in deep submicron processes, is exploited to implement analog and digital signal processing at the pixel level. Many prototypes have been fabricated in a planar (2D) 130nm CMOS technology. A new kind of DNW-MAPS, namely Apsel5{sub 3}D, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. The impact of 3D processes on the design and performance of DNW pixel sensors could be large, with significant advantages in terms of detection efficiency, pixel cell size and immunity to cross-talk, therefore complying with the severe constraints set by future HEP experiments.

CMOS VLSI Active-Pixel Sensor for Tracking

Science.gov (United States)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

First tests of CHERWELL, a Monolithic Active Pixel Sensor: A CMOS Image Sensor (CIS) using 180 nm technology

Energy Technology Data Exchange (ETDEWEB)

Mylroie-Smith, James, E-mail: j.mylroie-smith@qmul.ac.uk [Queen Mary, University of London (United Kingdom); Kolya, Scott; Velthuis, Jaap [University of Bristol (United Kingdom); Bevan, Adrian; Inguglia, Gianluca [Queen Mary, University of London (United Kingdom); Headspith, Jon; Lazarus, Ian; Lemon, Roy [Daresbury Laboratory, STFC (United Kingdom); Crooks, Jamie; Turchetta, Renato; Wilson, Fergus [Rutherford Appleton Laboratory, STFC (United Kingdom)

2013-12-11

The Cherwell is a 4T CMOS sensor in 180 nm technology developed for the detection of charged particles. Here, the different test structures on the sensor will be described and first results from tests on the reference pixel variant are shown. The sensors were shown to have a noise of 12 e{sup −} and a signal to noise up to 150 in {sup 55}Fe.

Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

Energy Technology Data Exchange (ETDEWEB)

Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

2012-11-15

Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

International Nuclear Information System (INIS)

Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

2012-01-01

Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

International Nuclear Information System (INIS)

Rivetti, A.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Costa, M.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rousset, J.; Silvestrin, L.; Wyss, J.

2013-01-01

The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400Ωcm, which is at least one order of magnitude greater than the typical value (1–10Ωcm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported

Empirical electro-optical and x-ray performance evaluation of CMOS active pixels sensor for low dose, high resolution x-ray medical imaging

International Nuclear Information System (INIS)

Arvanitis, C. D.; Bohndiek, S. E.; Royle, G.; Blue, A.; Liang, H. X.; Clark, A.; Prydderch, M.; Turchetta, R.; Speller, R.

2007-01-01

Monolithic complementary metal oxide semiconductor (CMOS) active pixel sensors with high performance have gained attention in the last few years in many scientific and space applications. In order to evaluate the increasing capabilities of this technology, in particular where low dose high resolution x-ray medical imaging is required, critical electro-optical and physical x-ray performance evaluation was determined. The electro-optical performance includes read noise, full well capacity, interacting quantum efficiency, and pixels cross talk. The x-ray performance, including x-ray sensitivity, modulation transfer function, noise power spectrum, and detection quantum efficiency, has been evaluated in the mammographic energy range. The sensor is a 525x525 standard three transistor CMOS active pixel sensor array with more than 75% fill factor and 25x25 μm pixel pitch. Reading at 10 f/s, it is found that the sensor has 114 electrons total additive noise, 10 5 electrons full well capacity with shot noise limited operation, and 34% interacting quantum efficiency at 530 nm. Two different structured CsI:Tl phosphors with thickness 95 and 115 μm, respectively, have been optically coupled via a fiber optic plate to the array resulting in two different system configurations. The sensitivity of the two different system configurations was 43 and 47 electrons per x-ray incident on the sensor. The MTF at 10% of the two different system configurations was 9.5 and 9 cycles/mm with detective quantum efficiency of 0.45 and 0.48, respectively, close to zero frequency at ∼0.44 μC/kg (1.72 mR) detector entrance exposure. The detector was quantum limited at low spatial frequencies and its performance was comparable with high resolution a:Si and charge coupled device based x-ray imagers. The detector also demonstrates almost an order of magnitude lower noise than active matrix flat panel imagers. The results suggest that CMOS active pixel sensors when coupled to structured CsI:Tl can

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

Science.gov (United States)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

Prospects for charge sensitive amplifiers in scaled CMOS

Science.gov (United States)

O'Connor, Paul; De Geronimo, Gianluigi

2002-03-01

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

Prospects for charge sensitive amplifiers in scaled CMOS

International Nuclear Information System (INIS)

O'Connor, Paul; De Geronimo, Gianluigi

2002-01-01

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006

Research and Development of Monolithic Active Pixel Sensors for the Detection of the Elementary Particles

International Nuclear Information System (INIS)

Li, Y.

2007-09-01

In order to develop high spatial resolution and readout speed vertex detectors for the future International Linear Collider (ILC), fast CMOS Monolithic Active Pixel Sensors (MAPS) are studied on this work. Two prototypes of MAPS, MIMOSA 8 and MIMOSA 16, based on the same micro-electronic architecture were developed in CMOS processes with different thickness of epitaxial layer. The size of pixel matrix is 32 x 128: 8 columns of the pixel array are readout directly with analog outputs and the other 24 columns are connected to the column level auto-zero discriminators. The Correlated Double Sampling (CDS) structures are successfully implemented inside pixel and discriminator. The photo diode type pixels with different diode sizes are used in these prototypes. With a 55 Fe X-ray radioactive source, the important parameters, such as Temporal Noise, Fixed Pattern Noise (FPN), Signal-to-Noise Ratio (SNR), Charge-to-Voltage conversion Factor (CVF) and Charge Collection Efficiency (CCE), are studied as function of readout speed and diode size. For MIMOSA 8, the effect of fast neutrons irradiation is also. Two beam tests campaigns were made: at DESY with a 5 GeV electrons beam and at CERN with a 180 GeV pions beam. Detection Efficiency and Spatial Resolution are studied in function of the discriminator threshold. For these two parameters, the influences of diode size and SNR of the central pixel of a cluster are also discussed. In order to improve the spatial resolution of the digital outputs, a very compact (25 μm x 1 mm) and low consumption (300 μW) column level ADC is designed in AMS 0.35 μm OPTO process. Based on successive approximation architecture, the auto-offset cancellation structure is integrated. A new column level auto-zero discriminator using static latch is also designed. (author)

A novel source–drain follower for monolithic active pixel sensors

Energy Technology Data Exchange (ETDEWEB)

Gao, C., E-mail: chaosong.gao@mails.ccnu.edu.cn [Central China Normal University, Wuhan (China); Aglieri, G.; Hillemanns, H. [CERN, Geneva (Switzerland); Huang, G., E-mail: gmhuang@phy.ccnu.edu.cn [Central China Normal University, Wuhan (China); Junique, A.; Keil, M. [CERN, Geneva (Switzerland); Kim, D. [Dongguk University, Seoul (Korea, Republic of); Yonsei University, Seoul (Korea, Republic of); Kofarago, M.; Kugathasan, T.; Mager, M.; Marin Tobon, C.A.; Martinengo, P. [CERN, Geneva (Switzerland); Mugnier, H. [Mind, Archamps (France); Musa, L. [CERN, Geneva (Switzerland); Lee, S. [Dongguk University, Seoul (Korea, Republic of); Yonsei University, Seoul (Korea, Republic of); Reidt, F. [CERN, Geneva (Switzerland); Ruprecht-Karls-Universitat Heidelberg, Heidelberg (Germany); Riedler, P. [CERN, Geneva (Switzerland); Rousset, J. [Mind, Archamps (France); Sielewicz, K.M. [CERN, Geneva (Switzerland); Warsaw University of Technology, Warsaw (Poland); Snoeys, W. [CERN, Geneva (Switzerland); and others

2016-09-21

Monolithic active pixel sensors (MAPS) receive interest in tracking applications in high energy physics as they integrate sensor and readout electronics in one silicon die with potential for lower material budget and cost, and better performance. Source followers (SFs) are widely used for MAPS readout: they increase charge conversion gain 1/C{sub eff} or decrease the effective sensing node capacitance C{sub eff} because the follower action compensates part of the input capacitance. Charge conversion gain is critical for analog power consumption and therefore for material budget in tracking applications, and also has direct system impact. This paper presents a novel source–drain follower (SDF), where both source and drain follow the gate potential improving charge conversion gain. For the inner tracking system (ITS) upgrade of the ALICE experiment at CERN, low material budget is a primary requirement. The SDF circuit was studied as part of the effort to optimize the effective capacitance of the sensing node. The collection electrode, input transistor and routing metal all contribute to C{sub eff}. Reverse sensor bias reduces the collection electrode capacitance. The novel SDF circuit eliminates the contribution of the input transistor to C{sub eff}, reduces the routing contribution if additional shielding is introduced, provides a way to estimate the capacitance of the sensor itself, and has a voltage gain closer to unity than the standard SF. The SDF circuit has a somewhat larger area with a somewhat smaller bandwidth, but this is acceptable in most cases. A test chip, manufactured in a 180 nm CMOS image sensor process, implements small prototype pixel matrices in different flavors to compare the standard SF to the novel SF and to the novel SF with additional shielding. The effective sensing node capacitance was measured using a {sup 55}Fe source. Increasing reverse substrate bias from −1 V to −6 V reduces C{sub eff} by 38% and the equivalent noise charge

A novel source–drain follower for monolithic active pixel sensors

International Nuclear Information System (INIS)

Gao, C.; Aglieri, G.; Hillemanns, H.; Huang, G.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Mager, M.; Marin Tobon, C.A.; Martinengo, P.; Mugnier, H.; Musa, L.; Lee, S.; Reidt, F.; Riedler, P.; Rousset, J.; Sielewicz, K.M.; Snoeys, W.

2016-01-01

Monolithic active pixel sensors (MAPS) receive interest in tracking applications in high energy physics as they integrate sensor and readout electronics in one silicon die with potential for lower material budget and cost, and better performance. Source followers (SFs) are widely used for MAPS readout: they increase charge conversion gain 1/C_e_f_f or decrease the effective sensing node capacitance C_e_f_f because the follower action compensates part of the input capacitance. Charge conversion gain is critical for analog power consumption and therefore for material budget in tracking applications, and also has direct system impact. This paper presents a novel source–drain follower (SDF), where both source and drain follow the gate potential improving charge conversion gain. For the inner tracking system (ITS) upgrade of the ALICE experiment at CERN, low material budget is a primary requirement. The SDF circuit was studied as part of the effort to optimize the effective capacitance of the sensing node. The collection electrode, input transistor and routing metal all contribute to C_e_f_f. Reverse sensor bias reduces the collection electrode capacitance. The novel SDF circuit eliminates the contribution of the input transistor to C_e_f_f, reduces the routing contribution if additional shielding is introduced, provides a way to estimate the capacitance of the sensor itself, and has a voltage gain closer to unity than the standard SF. The SDF circuit has a somewhat larger area with a somewhat smaller bandwidth, but this is acceptable in most cases. A test chip, manufactured in a 180 nm CMOS image sensor process, implements small prototype pixel matrices in different flavors to compare the standard SF to the novel SF and to the novel SF with additional shielding. The effective sensing node capacitance was measured using a "5"5Fe source. Increasing reverse substrate bias from −1 V to −6 V reduces C_e_f_f by 38% and the equivalent noise charge (ENC) by 22% for the

Optimization of CMOS active pixels for high resolution digital radiography

International Nuclear Information System (INIS)

Kim, Young Soo

2007-02-01

CMOS image sensors have poorer performance compared to conventional charge coupled devices (CCDs). Since CMOS Active Pixel Sensors (APSs) in general have higher temporal noise, higher dark current, smaller full well charge capacitance, and lower spectral response, they cannot provide the same wide dynamic range and superior signal-to-noise ratio as CCDs. In view of electronic noise, the main source for the CMOS APS is the pixel, along with other signal processing blocks such as row and column decoder, analog signal processor (ASP), analog-to-digital converter (ADC), and timing and control logic circuitry. Therefore, it is important and necessary to characterize noise of the active pixels in CMOS APSs. We developed our theoretical noise model to account for the temporal noise in active pixels, and then found out the optimum design parameters such as fill actor, each size of the three transistors (source follower, row selection transistor, bias transistor) comprising active pixels, bias current, and load capacitance that can have the maximum signal-to-noise ratio. To develop the theoretical noise model in active pixels, we considered the integration noise of the photodiode and the readout noise of the transistors related to readout. During integration, the shot noise due to the dark current and photocurrent, during readout, the thermal and flicker noise were considered. The developed model can take the input variables such as photocurrent, capacitance of the photodiode, integration time, transconductance of the transistors, channel resistance of the transistors, gate-to-source capacitance of the follower, and load capacitance etc. To validate our noise model, two types of test structures have been realized. Firstly, four types of photodiodes (n_d_i_f_f_u_s_i_o_n/p_s_u_b_s_t_r_a_t_e, n_w_e_l_l/p_s_u_b_s_t_r_a_t_e, n_d_i_f_f_u_s_i_o_n/p_e_p_i_t_a_x_i_a_l/p_s_u_b_s_t_r_a_t_e, n_w_e_l_l/p_e_p_i_t_a_x_i_a_l/p_s_u_b_s_t_r_a_t_e) used in CMOS active pixels were fabricated

Design of fundamental building blocks for fast binary readout CMOS sensors used in high-energy physics experiments

Energy Technology Data Exchange (ETDEWEB)

Degerli, Yavuz [CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette Cedex (France)], E-mail: degerli@cea.fr

2009-04-21

In this paper, design details of key building blocks for fast binary readout CMOS monolithic active pixel sensors developed for charged particle detection are presented. Firstly, an all-NMOS pixel architecture with in-pixel amplification and reset noise suppression which allows fast readout is presented. This pixel achieves high charge-to-voltage conversion factors (CVF) using a few number of transistors inside the pixel. It uses a pre-amplifying stage close to the detector and a simple double sampling (DS) circuitry to store the reset level of the detector. The DS removes the offset mismatches of amplifiers and the reset noise of the detector. Offset mismatches of the source follower are also corrected by a second column-level DS stage. The second important building block of these sensors, a low-power auto-zeroed column-level discriminator, is also presented. These two blocks transform the charge of the impinging particle into binary data. Finally, some experimental results obtained on CMOS chips designed using these blocks are presented.

Novel design of low-jitter 10 GHz all-active monolithic mode-locked lasers

DEFF Research Database (Denmark)

Larsson, David; Yvind, Kresten; Christiansen, Lotte Jin

2004-01-01

Using a novel design, we have fabricated 10 GHz all-active monolithic mode-locked semiconductor lasers that generate 1.4 ps pulses with record-low timing jitter. The dynamical properties of lasers with 1 and 2 QWs are compared.......Using a novel design, we have fabricated 10 GHz all-active monolithic mode-locked semiconductor lasers that generate 1.4 ps pulses with record-low timing jitter. The dynamical properties of lasers with 1 and 2 QWs are compared....

CMOS Active-Pixel Image Sensor With Simple Floating Gates

Science.gov (United States)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

A monolithic charge multiplexer with 0.5% accuracy

International Nuclear Information System (INIS)

Lewis, J.; McPherson, G.M.; Morrissey, M.C.; Thompson, J.C.; Tucker, A.W.

1990-01-01

This paper describes a 16 channel monolithic charge multiplexer providing a close tolerance, low cost, low power solution to the problem of handling the signals from detectors with large numbers of channels. Outputs may be wire-orred to increase the degree of multiplexing. A system designed with this chip and with suitable close tolerance processing downstream will have a gain match of ±0.5% and a front end chip cost of approximately $1 per channel. The chip is fabricated in CMOS technology and the test of a 1500 channel system has demonstrated the feasibility of CMOS in this context. The chip produces a prompt sum of the charges from the 16 signal sources and integrates and stores the individual charges for later serial readout. A single network provides amplifier bias and releases area to facilitate optimum noise performance and signal handling. Amplifier and bias network design together with p-well screens to isolate storage capacitors from the substrate provide the power line rejection essential in systems generating a trigger from large numbers of channels. (orig.)

A 3D deep n-well CMOS MAPS for the ILC vertex detector

Energy Technology Data Exchange (ETDEWEB)

Gaioni, L., E-mail: luigi.gaioni@unipv.i [Universita di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Manghisoni, M. [Universita di Bergamo, I-24044 Dalmine (Bulgaria) (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Ratti, L. [Universita di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Re, V.; Traversi, G. [Universita di Bergamo, I-24044 Dalmine (Bulgaria) (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy)

2010-05-21

This work presents the features of a new kind of deep n-well monolithic active pixel sensor (DNW-MAPS), called SDR1 (Sparsified Data Readout), which exploits the capabilities of vertical integration (3D) processing in view of the design of a high granularity detector for vertexing applications at the International Linear Collider (ILC). SDR1 inherits and extends the functional capabilities of DNW-MAPS fabricated in planar (2D) CMOS technology and is expected to show better collection efficiency with respect to 2D versions. The aim of the paper is to outline the features of analog and digital architecture of the SDR1 chip, together with circuit simulations data. Also some device simulation results concerning detection efficiency will be discussed.

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier

International Nuclear Information System (INIS)

Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

2010-01-01

The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

Characteristics of an activated carbon monolith for a helium adsorption compressor

NARCIS (Netherlands)

Lozano-Castello, D.; Jorda-Beneyto, M.; Cazorla-Amoros, D.; Linares-Solano, A.; Burger, Johannes Faas; ter Brake, Hermanus J.M.; Holland, Herman J.

2010-01-01

An activated carbon monolith (ACM) with a high helium adsorption/desorption capacity, high density, low pressure drop, low thermal expansion and good mechanical properties was prepared and applied successfully in a helium adsorption compressor as a part of a 4.5 K sorption cooler. The activated

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

Science.gov (United States)

Seco, Joao; Depauw, Nicolas

2011-02-01

Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The

Chiral monolithic absorbent constructed by optically active helical-substituted polyacetylene and graphene oxide: preparation and chiral absorption capacity.

Science.gov (United States)

Li, Weifei; Wang, Bo; Yang, Wantai; Deng, Jianping

2015-02-01

Chiral monolithic absorbent is successfully constructed for the first time by using optically active helical-substituted polyacetylene and graphene oxide (GO). The preparative strategy is facile and straightforward, in which chiral-substituted acetylene monomer (Ma), cross-linker (Mb), and alkynylated GO (Mc) undergo copolymerization to form the desired monolithic absorbent in quantitative yield. The resulting monoliths are characterized by circular dichroism, UV-vis absorption, scanning electron microscopy (SEM), FT-IR, Raman, energy-dispersive spectrometer (EDS), X-ray diffraction (XRD), Brunauer-Emmett-Teller (BET), XPS, and thermogravimetric analysis (TGA) techniques. The polymer chains derived from Ma form chiral helical structures and thus provide optical activity to the monoliths, while GO sheets contribute to the formation of porous structures. The porous structure enables the monolithic absorbents to demonstrate a large swelling ratio in organic solvents, and more remarkably, the helical polymer chains provide optical activity and further enantio-differentiating absorption ability. The present study establishes an efficient and versatile methodology for preparing novel functional materials, in particular monolithic chiral materials based on substituted polyacetylene and GO. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Monolithic integration of a micromachined piezoresistive flow sensor

International Nuclear Information System (INIS)

Li, Dan; Zhao, Tao; Yang, Zhenchuan; Zhang, Dacheng

2010-01-01

In this paper, a monolithic integrated piezoresistive flow sensor is presented, which was fabricated with an intermediate CMOS (complementary metal-oxide semiconductor) MEMS (micro electro mechanical system) process compatible with integrated pressure sensors. Four symmetrically arranged silicon diaphragms with piezoresistors on them were used to sense the drag force induced by the input gas flow. A signal conditioning CMOS circuit with a temperature compensation module was designed and fabricated simultaneously on the same chip with an increase of the total chip area by only 35%. An extra step of boron implantation and annealing was inserted into the standard CMOS process to form the piezoresistors. KOH anisotropic etching from the backside and deep reactive ion etching (DRIE) from the front side were combined to realize the silicon diaphragms. The integrated flow sensor was packaged and tested. The testing results indicated that the addition of piezoresistor formation and structure releasing did not significantly change any of the circuitry characteristics. The measured sensor output has a quadratic relation with the input flow rate of the fluid as predicted. The tested resolution of the sensor is less than 0.1 L min −1 with a measurement range of 0.1–5 L min −1 and the sensitivity is better than 40 mV per (L min −1 ) with a measurement range of 4–5 L min −1 . The measured noise floor of the sensor is 21.7 µV rtHz −1 .

Analysis of 3D stacked fully functional CMOS Active Pixel Sensor detectors

International Nuclear Information System (INIS)

Passeri, D; Servoli, L; Meroli, S

2009-01-01

The IC technology trend is to move from 3D flexible configurations (package on package, stacked dies) to real 3D ICs. This is mainly due to i) the increased electrical performances and ii) the cost of 3D integration which may be cheaper than to keep shrinking 2D circuits. Perspective advantages for particle tracking and vertex detectors applications in High Energy Physics can be envisaged: in this work, we will focus on the capabilities of the state-of-the-art vertical scale integration technologies, allowing for the fabrication of very compact, fully functional, multiple layers CMOS Active Pixel Sensor (APS) detectors. The main idea is to exploit the features of the 3D technologies for the fabrication of a ''stack'' of very thin and precisely aligned CMOS APS layers, leading to a single, integrated, multi-layers pixel sensor. The adoption of multiple-layers single detectors can dramatically reduce the mass of conventional, separated detectors (thus reducing multiple scattering issues), at the same time allowing for very precise measurements of particle trajectory and momentum. As a proof of concept, an extensive device and circuit simulation activity has been carried out, aiming at evaluate the suitability of such a kind of CMOS active pixel layers for particle tracking purposes.

Geant4-based simulations of charge collection in CMOS Active Pixel Sensors

International Nuclear Information System (INIS)

Esposito, M.; Allinson, N.M.; Price, T.; Anaxagoras, T.

2017-01-01

Geant4 is an object-oriented toolkit for the simulation of the interaction of particles and radiation with matter. It provides a snapshot of the state of a simulated particle in time, as it travels through a specified geometry. One important area of application is the modelling of radiation detector systems. Here, we extend the abilities of such modelling to include charge transport and sharing in pixelated CMOS Active Pixel Sensors (APSs); though similar effects occur in other pixel detectors. The CMOS APSs discussed were developed in the framework of the PRaVDA consortium to assist the design of custom sensors to be used in an energy-range detector for proton Computed Tomography (pCT). The development of ad-hoc classes, providing a charge transport model for a CMOS APS and its integration into the standard Geant4 toolkit, is described. The proposed charge transport model includes, charge generation, diffusion, collection, and sharing across adjacent pixels, as well as the full electronic chain for a CMOS APS. The proposed model is validated against experimental data acquired with protons in an energy range relevant for pCT.

High-ratio voltage conversion in CMOS for efficient mains-connected standby

CERN Document Server

Meyvaert, Hans

2016-01-01

This book describes synergetic innovation opportunities offered by combining the field of power conversion with the field of integrated circuit (IC) design. The authors demonstrate how integrating circuits enables increased operation frequency, which can be exploited in power converters to reduce drastically the size of the discrete passive components. The authors introduce multiple power converter circuits, which are very compact as result of their high level of integration. First, the limits of high-power-density low-voltage monolithic switched-capacitor DC-DC conversion are investigated to enable on-chip power granularization. AC-DC conversion from the mains to a low voltage DC is discussed, enabling an efficient and compact, lower-power auxiliary power supply to take over the power delivery during the standby mode of mains-connected appliances, allowing the main power converter of these devices to be shut down fully. Discusses high-power-density monolithic switched-capacitor DC-DC conversion in bulk CMOS,...

Voltage-to-frequency converters CMOS design and implementation

CERN Document Server

Azcona Murillo, Cristina; Pueyo, Santiago Celma

2013-01-01

This book develops voltage-to-frequency converter (VFC) solutions integrated in standard CMOS technology to be used as a part of a microcontroller-based, multisensor interface in the environment of portable applications, particularly within a WSN node.  Coverage includes the total design flow of monolithic VFCs, according to the target application, as well as the analysis, design and implementation of the main VFC blocks, revealing the main challenges and solutions encountered during the design of such high performance cells. Four complete VFCs, each temperature compensated, are fully designed and evaluated: a programmable VFC that includes an offset frequency and a sleep/mode enable terminal; a low power rail-to-rail VFC; and two rail-to-rail differential VFCs.

Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

Directory of Open Access Journals (Sweden)

Ler Chun Lee

2008-01-01

Full Text Available A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA. A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

The multichannel amplifier/discriminator CMOS ASIC for visual light photon counters

International Nuclear Information System (INIS)

Baturitsky, M.A.; Yurenya, Yu.P.Yu.P.

2002-01-01

The 18-channel CMOS custom monolithic amplifier/discriminator ASIC was designed as a front-end electronics chip for Visual Light Photon Counters which convert photons from scintillation fibre/strip detectors to electrical signals. One ASICs channel contains a charge-sensitive preamplifier, a discriminator to mark the arrival time of signals, and a charge divider to provide analog outputs for analog-to-digital conversion being performed by SVX2. The ASIC is proposed as one of the variants for possible future front-end electronics upgrading the D0 Central Fibre Tracker, Central and Forward Pre-Showers (Fermilab, Batavia, USA)

Study of prototypes of LFoundry active CMOS pixels sensors for the ATLAS detector

Science.gov (United States)

Vigani, L.; Bortoletto, D.; Ambroz, L.; Plackett, R.; Hemperek, T.; Rymaszewski, P.; Wang, T.; Krueger, H.; Hirono, T.; Caicedo Sierra, I.; Wermes, N.; Barbero, M.; Bhat, S.; Breugnon, P.; Chen, Z.; Godiot, S.; Pangaud, P.; Rozanov, A.

2018-02-01

Current high energy particle physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip configurations, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in depleted CMOS silicon detectors, which could achieve a similar performance at lower cost of production. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, are shown.

Study of prototypes of LFoundry active CMOS pixels sensors for the ATLAS detector

CERN Document Server

Vigani, L.; Ambroz, L.; Plackett, R.; Hemperek, T.; Rymaszewski, P.; Wang, T.; Krueger, H.; Hirono, T.; Caicedo Sierra, I.; Wermes, N.; Barbero, M.; Bhat, S.; Breugnon, P.; Chen, Z.; Godiot, S.; Pangaud, P.; Rozanov, A.

2018-01-01

Current high energy particle physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip configurations, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in depleted CMOS silicon detectors, which could achieve a similar performance at lower cost of production. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, are shown.

PIXEL 2010 - A Resume

International Nuclear Information System (INIS)

Wermes, N.

2011-01-01

The Pixel 2010 conference focused on semiconductor pixel detectors for particle tracking/vertexing as well as for imaging, in particular for synchrotron light sources and XFELs. The big LHC hybrid pixel detectors have impressively started showing their capabilities. X-ray imaging detectors, also using the hybrid pixel technology, have greatly advanced the experimental possibilities for diffraction experiments. Monolithic or semi-monolithic devices like CMOS active pixels and DEPFET pixels have now reached a state such that complete vertex detectors for RHIC and superKEKB are being built with these technologies. Finally, new advances towards fully monolithic active pixel detectors, featuring full CMOS electronics merged with efficient signal charge collection, exploiting standard CMOS technologies, SOI and/or 3D integration, show the path for the future. This resume attempts to extract the main statements of the results and developments presented at this conference.

Continuous-Flow Monolithic Silica Microreactors with Arenesulphonic Acid Groups: Structure–Catalytic Activity Relationships

Directory of Open Access Journals (Sweden)

Agnieszka Ciemięga

2017-08-01

Full Text Available The performance of monolithic silica microreactors activated with sulphonic acid groups and a packed bed reactor with Amberlyst 15 resin were compared in the esterification of acetic acid with n-butanol. The monolithic microreactors were made of single silica rods with complex pore architecture, differing in the size of mesopores, and in particular, flow-through macropores which significantly affected the flow characteristic of the continuous system. The highest ester productivity of 105.2 mol·molH+−1·h−1 was achieved in microreactor M1 with the largest porosity, characterized by a total pore volume of 4 cm3·g−1, mesopores with 20 nm diameter, and large flow-through macropores 30–50 μm in size. The strong impact of the permeability of the monoliths on a reaction kinetics was shown.

A 1.2 Gb/s Data Transmission Unit in CMOS 0.18 μm technology for the ALICE Inner Tracking System front-end ASIC

Science.gov (United States)

Mazza, G.; Aglieri Rinella, G.; Benotto, F.; Corrales Morales, Y.; Kugathasan, T.; Lattuca, A.; Lupi, M.; Ravasenga, I.

2017-02-01

The upgrade of the ALICE Inner Tracking System is based on a Monolithic Active Pixel Sensor and ASIC designed in a CMOS 0.18 μ m process. In order to provide the required output bandwidth (1.2 Gb/s for the inner layers and 400 Mb/s for the outer ones) on a single high speed serial link, a custom Data Transmission Unit (DTU) has been developed in the same process. The DTU includes a clock multiplier PLL, a double data rate serializer and a pseudo-LVDS driver with pre-emphasis and is designed to be SEU tolerant.

Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly.

Science.gov (United States)

Gall, Oren Z; Zhong, Xiahua; Schulman, Daniel S; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S

2017-06-30

Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO 2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

Analog front-end for pixel sensors in a 3D CMOS technology for the SuperB Layer0

International Nuclear Information System (INIS)

Manazza, A.; Gaioni, L.; Re, V.

2011-01-01

This work is concerned with the design of two different analog channels for hybrid and monolithic pixels readout in view of applications to the SVT at the SuperB Factory. The circuits have been designed in a 130nm CMOS, vertically integrated technology, which, among others, may provide some advantages in terms of functional density and electrical isolation between the analog and the digital sections of the front-end.

CMOS Silicon-on-Sapphire RF Tunable Matching Networks

Directory of Open Access Journals (Sweden)

Chamseddine Ahmad

2006-01-01

Full Text Available This paper describes the design and optimization of an RF tunable network capable of matching highly mismatched loads to 50 at 1.9 GHz. Tuning was achieved using switched capacitors with low-loss, single-transistor switches. Simulations show that the performance of the matching network depends strongly on the switch performances and on the inductor losses. A 0.5 m silicon-on-sapphire (SOS CMOS technology was chosen for network implementation because of the relatively high-quality monolithic inductors achievable in the process. The matching network provides very good matching for inductive loads, and acceptable matching for highly capacitive loads. A 1 dB compression point greater than dBm was obtained for a wide range of load impedances.

CMOS Active Pixel Sensors for Low Power, Highly Miniaturized Imaging Systems

Science.gov (United States)

Fossum, Eric R.

1996-01-01

The complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology has been developed over the past three years by NASA at the Jet Propulsion Laboratory, and has reached a level of performance comparable to CCDs with greatly increased functionality but at a very reduced power level.

All-CMOS night vision viewer with integrated microdisplay

Science.gov (United States)

Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

2014-02-01

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

CMOS circuits manual

CERN Document Server

Marston, R M

1995-01-01

CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

Pixel 2010: A résumé

CERN Document Server

Wermes, Norbert

2011-01-01

The Pixel 2010 conference focused on semiconductor pixel detectors for particle tracking/vertexing as well as for imaging, in particular for synchrotron light sources and XFELs. The big LHC hybrid pixel detectors have impressively started showing their capabilities. X-ray imaging detectors, also using the hybrid pixel technology, have greatly advanced the experimental possibilities for diffraction experiments. Monolithic or semi-monolithic devices like CMOS active pixels and DEPFET pixels have now reached a state such that complete vertex detectors for RHIC and superKEKB are being built with these technologies. Finally, new advances towards fully monolithic active pixel detectors, featuring full CMOS electronics merged with efficient signal charge collection, exploiting standard CMOS technologies, SOI and/or 3D integration, show the path for the future. This résumé attempts to extract the main statements of the results and developments presented at this conference.

Probing the Effects of Templating on the UV and Visible Light Photocatalytic Activity of Porous Nitrogen-Modified Titania Monoliths for Dye Removal.

Science.gov (United States)

Nursam, Natalita M; Wang, Xingdong; Tan, Jeannie Z Y; Caruso, Rachel A

2016-07-13

Porous nitrogen-modified titania (N-titania) monoliths with tailored morphologies were prepared using phase separation and agarose gel templating techniques. The doping and templating process were simultaneously carried out in a one-pot step using alcohol amine-assisted sol-gel chemistry. The amount of polymer used in the monoliths that were prepared using phase separation was shown to affect both the physical and optical properties: higher poly(ethylene glycol) content increased the specific surface area, porosity, and visible light absorption of the final materials. For the agarose-templated monoliths, the infiltration conditions affected the monolith morphology. A porous monolith with high surface area and the least shrinkage was obtained when the N containing alkoxide precursor was infiltrated into the agarose scaffolds at 60 °C. The effect of the diverse porous morphologies on the photocatalytic activity of N-titania was studied for the decomposition of methylene blue (MB) under visible and UV light irradiation. The highest visible light activity was achieved by the agarose-templated N-titania monolith, in part due to higher N incorporation. This sample also showed better UV activity, partly because of the higher specific surface area (up to 112 m(2) g(-1)) compared to the phase separation-induced monoliths (up to 103 m(2) g(-1)). Overall, agarose-templated, porous N-titania monoliths provided better features for effectively removing the MB contaminant.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

Science.gov (United States)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Photon small-field measurements with a CMOS active pixel sensor.

Science.gov (United States)

Spang, F Jiménez; Rosenberg, I; Hedin, E; Royle, G

2015-06-07

In this work the dosimetric performance of CMOS active pixel sensors for the measurement of small photon beams is presented. The detector used consisted of an array of 520  × 520 pixels on a 25 µm pitch. Dosimetric parameters measured with this sensor were compared with data collected with an ionization chamber, a film detector and GEANT4 Monte Carlo simulations. The sensor performance for beam profiles measurements was evaluated for field sizes of 0.5  × 0.5 cm(2). The high spatial resolution achieved with this sensor allowed the accurate measurement of profiles, beam penumbrae and field size under lateral electronic disequilibrium. Field size and penumbrae agreed within 5.4% and 2.2% respectively with film measurements. Agreements with ionization chambers better than 1.0% were obtained when measuring tissue-phantom ratios. Output factor measurements were in good agreement with ionization chamber and Monte Carlo simulation. The data obtained from this imaging sensor can be easily analyzed to extract dosimetric information. The results presented in this work are promising for the development and implementation of CMOS active pixel sensors for dosimetry applications.

Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 µm CMOS MEMS process

International Nuclear Information System (INIS)

Tseng, Sheng-Hsiang; Lu, Michael S-C; Wu, Po-Chang; Teng, Yu-Chen; Tsai, Hann-Huei; Juang, Ying-Zong

2012-01-01

This paper describes the design, fabrication and characterization of a complementary metal-oxide-semiconductor (CMOS) micro-electro-mechanical-system (MEMS) accelerometer implemented in a 0.18 µm multi-project wafer (MPW) CMOS MEMS process. In addition to the standard CMOS process, an additional aluminum layer and a thick photoresist masking layer are employed to achieve etching and microstructural release. The structural thickness of the accelerometer is up to 9 µm and the minimum structural spacing is 2.3 µm. The out-of-plane deflection resulted from the vertical stress gradient over the whole device is controlled to be under 0.2 µm. The chip area containing the micromechanical structure and switched-capacitor sensing circuit is 1.18 × 0.9 mm 2 , and the total power consumption is only 0.7 mW. Within the sensing range of ±6 G, the measured nonlinearity is 1.07% and the cross-axis sensitivities with respect to the in-plane and out-of-plane are 0.5% and 5.8%, respectively. The average sensitivity of five tested accelerometers is 191.4 mV G −1 with a standard deviation of 2.5 mV G −1 . The measured output noise floor is 354 µG Hz −1/2 , corresponding to a 100 Hz 1 G sinusoidal acceleration. The measured output offset voltage is about 100 mV at 27 °C, and the zero-G temperature coefficient of the accelerometer output is 0.94 mV °C −1 below 85 °C. (paper)

Development of Pixel Front-End Electronics using Advanced Deep Submicron CMOS Technologies

CERN Document Server

Havránek, Miroslav; Dingfelder, Jochen

The content of this thesis is oriented on the R&D; of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore’s laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key pa...

Influence of different carbon monolith preparation parameters on pesticide adsorption

Directory of Open Access Journals (Sweden)

Vukčević Marija

2013-01-01

Full Text Available The capacity of carbon monolith for pesticide removal from water, and the mechanism of pesticide interaction with carbon surface were examined. Different carbon monolith samples were obtained by varying the carbonization and activation parameters. In order to examine the role of surface oxygen groups in pesticide adsorption, carbon monolith surface was functionalized by chemical treatment in HNO3, H2O2 and KOH. The surface properties of the obtained samples were investigated by BET surface area, pore size distribution and temperature-programmed desorption. Adsorption of pesticides from aqueous solution onto activated carbon monolith samples was studied by using five pesticides belonging to different chemical groups (acetamiprid, dimethoate, nicosulfuron, carbofuran and atrazine. Presented results show that higher temperature of carbonization and the amount of activating agent allow obtaining microporous carbon monolith with higher amount of surface functional groups. Adsorption properties of the activated carbon monolith were more readily affected by the amount of the surface functional groups than by specific surface area. Results obtained by carbon monolith functionalisation showed that π-π interactions were the main force for adsorption of pesticides with aromatic structure, while acidic groups play an important role in adsorption of pesticides with no aromatic ring in the chemical structure.

Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

International Nuclear Information System (INIS)

Miucci, A; Gonzalez-Sevilla, S; Ferrere, D; Iacobucci, G; Rosa, A La; Muenstermann, D; Gonella, L; Hemperek, T; Hügging, F; Krüger, H; Obermann, T; Wermes, N; Garcia-Sciveres, M; Backhaus, M; Capeans, M; Feigl, S; Nessi, M; Pernegger, H; Ristic, B; George, M

2014-01-01

Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

CMOS Active Pixel Sensors as energy-range detectors for proton Computed Tomography

International Nuclear Information System (INIS)

Esposito, M.; Waltham, C.; Allinson, N.M.; Anaxagoras, T.; Evans, P.M.; Poludniowski, G.; Green, S.; Parker, D.J.; Price, T.; Manolopoulos, S.; Nieto-Camero, J.

2015-01-01

Since the first proof of concept in the early 70s, a number of technologies has been proposed to perform proton CT (pCT), as a means of mapping tissue stopping power for accurate treatment planning in proton therapy. Previous prototypes of energy-range detectors for pCT have been mainly based on the use of scintillator-based calorimeters, to measure proton residual energy after passing through the patient. However, such an approach is limited by the need for only a single proton passing through the energy-range detector in a read-out cycle. A novel approach to this problem could be the use of pixelated detectors, where the independent read-out of each pixel allows to measure simultaneously the residual energy of a number of protons in the same read-out cycle, facilitating a faster and more efficient pCT scan. This paper investigates the suitability of CMOS Active Pixel Sensors (APSs) to track individual protons as they go through a number of CMOS layers, forming an energy-range telescope. Measurements performed at the iThemba Laboratories will be presented and analysed in terms of correlation, to confirm capability of proton tracking for CMOS APSs

CMOS Active Pixel Sensors as energy-range detectors for proton Computed Tomography.

Science.gov (United States)

Esposito, M; Anaxagoras, T; Evans, P M; Green, S; Manolopoulos, S; Nieto-Camero, J; Parker, D J; Poludniowski, G; Price, T; Waltham, C; Allinson, N M

2015-06-03

Since the first proof of concept in the early 70s, a number of technologies has been proposed to perform proton CT (pCT), as a means of mapping tissue stopping power for accurate treatment planning in proton therapy. Previous prototypes of energy-range detectors for pCT have been mainly based on the use of scintillator-based calorimeters, to measure proton residual energy after passing through the patient. However, such an approach is limited by the need for only a single proton passing through the energy-range detector in a read-out cycle. A novel approach to this problem could be the use of pixelated detectors, where the independent read-out of each pixel allows to measure simultaneously the residual energy of a number of protons in the same read-out cycle, facilitating a faster and more efficient pCT scan. This paper investigates the suitability of CMOS Active Pixel Sensors (APSs) to track individual protons as they go through a number of CMOS layers, forming an energy-range telescope. Measurements performed at the iThemba Laboratories will be presented and analysed in terms of correlation, to confirm capability of proton tracking for CMOS APSs.

Brief review: Preparation techniques of biomass based activated carbon monolith electrode for supercapacitor applications

Science.gov (United States)

Taer, Erman; Taslim, Rika

2018-02-01

The synthesis of activated carbon monolith electrode made from a biomass material using the hydrolytic pressure or the pelletization technique of pre-carbonized materials is one of standard reported methods. Several steps such as pre-carbonization, milling, chemical activation, hydraulic press, carbonization, physical activation, polishing and washing need to be accomplished in the production of electrodes by this method. This is relatively a long process that need to be simplified. In this paper we present the standard method and proceed with the introduction to several alternative methods in the synthesis of activated carbon monolith electrodes. The alternative methods were emphasized on the selection of suitable biomass materials. All of carbon electrodes prepared by different methods will be analyzed for physical and electrochemical properties. The density, degree of crystallinity, surface morphology are examples for physical study and specific capacitance was an electrochemical properties that has been analysed. This alternative method has offered a specific capacitance in the range of 10 to 171 F/g.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

Science.gov (United States)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Monolithic approach for solid-state detector electronics: Design implications

International Nuclear Information System (INIS)

Vanstraelen, G.

1990-01-01

The monolithic integration is obtained using a p-well CMOS technology in which the p-channel devices are located in the high-resistivity silicon. The latter has enormous implications on their behavior, as compared to standard devices. In this paper it is shown for pMOS transistors on HR-Si that a real saturation operation is never reached, but that they keep operating in a quasi-linear mode, due to the 2-D nature of the potential profile. Based on an analytical current model for the quasi-linear mode, it is shown that if the p-channel length is not carefully chosen, the active operation of the device in analog circuits is lost completely due to the low output resistance. The second topic investigated is the p-channel noise behavior. Experiments lead to the conclusion that a low 1/f noise in on mode is only guaranteed if the surface current is much larger than the punch-through current. In off mode the device can be used as a low noise resistor. Furthermore it is found that the white noise is due to the substrate resistance, instead of the channel resistance

Extended Leach Testing of Simulated LAW Cast Stone Monoliths

Energy Technology Data Exchange (ETDEWEB)

Serne, R. Jeffrey [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Westsik, Joseph H. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Williams, Benjamin D. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Jung, H. B. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Wang, Guohui [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2015-07-09

This report describes the results from long-term laboratory leach tests performed at Pacific Northwest National Laboratory (PNNL) for Washington River Protection Solutions (WRPS) to evaluate the release of key constituents from monoliths of Cast Stone prepared with four simulated low-activity waste (LAW) liquid waste streams. Specific objectives of the Cast Stone long-term leach tests described in this report focused on four activities: 1. Extending the leaching times for selected ongoing EPA-1315 tests on monoliths made with LAW simulants beyond the conventional 63-day time period up to 609 days reported herein (with some tests continuing that will be documented later) in an effort to evaluate long-term leaching properties of Cast Stone to support future performance assessment activities. 2. Starting new EPA-1315 leach tests on archived Cast Stone monoliths made with four LAW simulants using two leachants (deionized water [DIW] and simulated Hanford Integrated Disposal Facility (IDF) Site vadose zone pore water [VZP]). 3. Evaluating the impacts of varying the iodide loading (starting iodide concentrations) in one LAW simulant (7.8 M Na Hanford Tank Waste Operations Simulator (HTWOS) Average) by manufacturing new Cast Stone monoliths and repeating the EPA-1315 leach tests using DIW and the VZP leachants. 4. Evaluating the impacts of using a non-pertechnetate form of Tc that is present in some Hanford tanks. In this activity one LAW simulant (7.8 M Na HTWOS Average) was spiked with a Tc(I)-tricarbonyl gluconate species and then solidified into Cast Stone monoliths. Cured monoliths were leached using the EPA-1315 leach protocol with DIW and VZP. The leach results for the Tc-Gluconate Cast Stone monoliths were compared to Cast Stone monoliths pertechnetate.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Synthesis of Porous Carbon Monoliths Using Hard Templates.

Science.gov (United States)

Klepel, Olaf; Danneberg, Nina; Dräger, Matti; Erlitz, Marcel; Taubert, Michael

2016-03-21

The preparation of porous carbon monoliths with a defined shape via template-assisted routes is reported. Monoliths made from porous concrete and zeolite were each used as the template. The porous concrete-derived carbon monoliths exhibited high gravimetric specific surface areas up to 2000 m²·g -1 . The pore system comprised macro-, meso-, and micropores. These pores were hierarchically arranged. The pore system was created by the complex interplay of the actions of both the template and the activating agent as well. On the other hand, zeolite-made template shapes allowed for the preparation of microporous carbon monoliths with a high volumetric specific surface area. This feature could be beneficial if carbon monoliths must be integrated into technical systems under space-limited conditions.

Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors.

Science.gov (United States)

Malinowski, Pawel E; Georgitzikis, Epimitheas; Maes, Jorick; Vamvaka, Ioanna; Frazzica, Fortunato; Van Olmen, Jan; De Moor, Piet; Heremans, Paul; Hens, Zeger; Cheyns, David

2017-12-10

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III-V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10 -6 A/cm² at -2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors.

Monoliths in Bioprocess Technology

Directory of Open Access Journals (Sweden)

Vignesh Rajamanickam

2015-04-01

Full Text Available Monolithic columns are a special type of chromatography column, which can be used for the purification of different biomolecules. They have become popular due to their high mass transfer properties and short purification times. Several articles have already discussed monolith manufacturing, as well as monolith characteristics. In contrast, this review focuses on the applied aspect of monoliths and discusses the most relevant biomolecules that can be successfully purified by them. We describe success stories for viruses, nucleic acids and proteins and compare them to conventional purification methods. Furthermore, the advantages of monolithic columns over particle-based resins, as well as the limitations of monoliths are discussed. With a compilation of commercially available monolithic columns, this review aims at serving as a ‘yellow pages’ for bioprocess engineers who face the challenge of purifying a certain biomolecule using monoliths.

Development of fast and radiation hard Monolithic Active Pixel Sensors (MAPS) optimized for open charm meson detection with the CBM experiment

International Nuclear Information System (INIS)

Deveaux, M.

2008-03-01

The adequacy of CMOS MAPS (Monolithic Active Pixel Sensors) to provide high spatial resolution while submitted to high particle flux and radiation level is assessed in this work. A 55 Fe-source and minimum ionizing particle beams were used to study the performances of MAPS being irradiated either with neutrons and X-rays. As expected, ionizing radiation dominantly causes an increase of the leakage current of the pixels, which translates into increased shot noise. Non-ionizing radiation generates increases in terms of leakage currents but can reduce substantially the lifetime of the signal electrons in the pixel. The latter was found to cause a dramatic drop of the signal if the lifetime of the electrons shrinks below the time required for charge collection. The performances of irradiated detectors were studied as a function of the operation conditions, i.e. in terms of temperature and integration time of the pixel. It was demonstrated that running the detectors at low temperature ( 7 collisions per second, would shrink the lifetime of the detector to a few days. It was however demonstrated that a balanced configuration exists where, for lower beam interaction rate, enough D 0 -mesons can be collected and analyzed to investigate their production properties with a satisfactory sensitivity. (A.C.)

Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

International Nuclear Information System (INIS)

Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.

2010-01-01

Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC 2 shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using μ-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 (micro)m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

Monolithic array of 32 SPAD pixels for single-photon imaging at high frame rates

International Nuclear Information System (INIS)

Tisa, Simone; Guerrieri, Fabrizio; Zappa, Franco

2009-01-01

We present a single-chip monolithic array of 32 Single-Photon Avalanche Diodes (SPAD) and associated electronics for imaging at high frame rates and high sensitivity. Photodetectors, front-end circuitry and control electronics used to manage the array are monolithically integrated on the same chip in a standard 0.35 μm CMOS high-voltage technology. The array is composed of 32 'smart' pixels working in photon counting mode and functioning in a parallel fashion. Every cell comprises of an integrated SPAD photodetector, a novel quenching circuit named as Variable Load Quenching Circuit (VLQC), counting electronics and a buffer memory. Proper ancillary electronics that perform the arbitration of photon counts between two consecutive frames is integrated as well. Thanks to the presence of in-pixel memory registers, the inter-frame dead time between subsequent frames is limited to few nanoseconds. Since integration and download are performed simultaneously and the array can be addressed like a standard digital memory, the achievable maximum frame rate is very high in the order of hundreds of thousands of frame/s.

A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation

Energy Technology Data Exchange (ETDEWEB)

Zhou Qianneng; Wang Yongsheng; Lai Fengchang, E-mail: qianneng@hit.edu.c [Microelectronics Center, Harbin Institute of Technology, Harbin 150001 (China)

2009-04-15

A capacitor-free CMOS low-dropout (LDO) regulator for system-on-chip (SoC) applications is presented. By adopting AC-boosting and active-feedback frequency compensation (ACB-AFFC), the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 mum CMOS process. The active silicon area is only 770 x 472 mum{sup 2}. Experimental results show that the total error of the output voltage due to line variation is less than +-0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

Science.gov (United States)

Fossum, E. R.

1995-01-01

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

Selective oxidation of cyclohexene through gold functionalized silica monolith microreactors

Science.gov (United States)

Alotaibi, Mohammed T.; Taylor, Martin J.; Liu, Dan; Beaumont, Simon K.; Kyriakou, Georgios

2016-04-01

Two simple, reproducible methods of preparing evenly distributed Au nanoparticle containing mesoporous silica monoliths are investigated. These Au nanoparticle containing monoliths are subsequently investigated as flow reactors for the selective oxidation of cyclohexene. In the first strategy, the silica monolith was directly impregnated with Au nanoparticles during the formation of the monolith. The second approach was to pre-functionalize the monolith with thiol groups tethered within the silica mesostructure. These can act as evenly distributed anchors for the Au nanoparticles to be incorporated by flowing a Au nanoparticle solution through the thiol functionalized monolith. Both methods led to successfully achieving even distribution of Au nanoparticles along the length of the monolith as demonstrated by ICP-OES. However, the impregnation method led to strong agglomeration of the Au nanoparticles during subsequent heating steps while the thiol anchoring procedure maintained the nanoparticles in the range of 6.8 ± 1.4 nm. Both Au nanoparticle containing monoliths as well as samples with no Au incorporated were tested for the selective oxidation of cyclohexene under constant flow at 30 °C. The Au free materials were found to be catalytically inactive with Au being the minimum necessary requirement for the reaction to proceed. The impregnated Au-containing monolith was found to be less active than the thiol functionalized Au-containing material, attributable to the low metal surface area of the Au nanoparticles. The reaction on the thiol functionalized Au-containing monolith was found to depend strongly on the type of oxidant used: tert-butyl hydroperoxide (TBHP) was more active than H2O2, likely due to the thiol induced hydrophobicity in the monolith.

Design and characterization of novel monolithic pixel sensors for the ALICE ITS upgrade

CERN Document Server

Cavicchioli, C; Giubilato, P; Hillemanns, H; Junique, A; Kugathasan, T; Mager, M; Marin Tobon, C A; Martinengo, P; Mattiazzo, S; Mugnier, H; Musa, L; Pantano, D; Rousset, J; Reidt, F; Riedler, P; Snoeys, W; Van Hoorne, J W; Yang, P

2014-01-01

Within the R&D activities for the upgrade of the ALICE Inner Tracking System (ITS), Monolithic Active Pixel Sensors (MAPS) are being developed and studied, due to their lower material budget (~0.3%X0~0.3%X0 in total for each inner layer) and higher granularity (View the MathML source~20μm×20μm pixels) with respect to the present pixel detector. This paper presents the design and characterization results of the Explorer0 chip, manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a wafer with high-resistivity View the MathML source(ρ>1kΩcm) and 18 μm thick epitaxial layer. The chip is organized in two sub-matrices with different pixel pitches (20 μm and 30 μm), each of them containing several pixel designs. The collection electrode size and shape, as well as the distance between the electrode and the surrounding electronics, are varied; the chip also offers the possibility to decouple the charge integration time from the readout time, and to change the sensor bias. The charge c...

Linear analysis of signal and noise characteristics of a nonlinear CMOS active-pixel detector for mammography

Energy Technology Data Exchange (ETDEWEB)

Yun, Seungman [School of Mechanical Engineering, Pusan National University, Busan 46241 (Korea, Republic of); Kim, Ho Kyung, E-mail: hokyung@pusan.ac.kr [School of Mechanical Engineering, Pusan National University, Busan 46241 (Korea, Republic of); Center for Advanced Medical Engineering Research, Pusan National University, Busan 46241 (Korea, Republic of); Han, Jong Chul; Kam, Soohwa [School of Mechanical Engineering, Pusan National University, Busan 46241 (Korea, Republic of); Youn, Hanbean [Department of Radiation Oncology, Pusan National University Yangsan Hospital, Yangsan, Gyeongsangnam-do 50612 (Korea, Republic of); Cunningham, Ian A. [Robarts Research Institute, Western University, London, Ontario N6A 5C1 (Canada)

2017-03-01

The imaging properties of a complementary metal-oxide-semiconductor (CMOS) active-pixel photodiode array coupled to a thin gadolinium-based granular phosphor screen with a fiber-optic faceplate are investigated. It is shown that this system has a nonlinear response at low detector exposure levels (<10 mR), resulting in an over-estimation of the detective quantum efficiency (DQE) by a factor of two in some cases. Errors in performance metrics on this scale make it difficult to compare new technologies with established systems and predict performance benchmarks that can be achieved in practice and help understand performance bottlenecks. It is shown the CMOS response is described by a power-law model that can be used to linearize image data. Linearization removed an unexpected dependence of the DQE on detector exposure level. - Highlights: • A nonlinear response of a CMOS detector at low exposure levels can overestimate DQE. • A power-law form can model the response of a CMOS detector at low exposure levels, and can be used to linearize image data. • Performance evaluation of nonlinear imaging systems must incorporate adequate linearizations.

Enhanced activity and stability of La-doped CeO2 monolithic catalysts for lean-oxygen methane combustion.

Science.gov (United States)

Zhu, Wenjun; Jin, Jianhui; Chen, Xiao; Li, Chuang; Wang, Tonghua; Tsang, Chi-Wing; Liang, Changhai

2018-02-01

Effective utilization of coal bed methane is very significant for energy utilization and environment protection. Catalytic combustion of methane is a promising way to eliminate trace amounts of oxygen in the coal bed methane and the key to this technology is the development of high-efficiency catalysts. Herein, we report a series of Ce 1-x La x O 2-δ (x = 0-0.8) monolithic catalysts for the catalytic combustion of methane, which are prepared by citric acid method. The structural characterization shows that the substitution of La enhance the oxygen vacancy concentration and reducibility of the supports and promote the migration of the surface oxygen, as a result improve the catalytic activity of CeO 2 . M-Ce 0.8 La 0.2 O 2-δ (monolithic catalyst, Ce 0.8 La 0.2 O 2-δ coated on cordierite honeycomb) exhibits outstanding activity for methane combustion, and the temperature for 10 and 90% methane conversion are 495 and 580 °C, respectively. Additionally, Ce 0.8 La 0.2 O 2-δ monolithic catalyst presents excellent stability at high temperature. These Ce 1-x La x O 2-δ monolithic materials with a small amount of La incorporation therefore show promises as highly efficient solid solution catalysts for lean-oxygen methane combustion. Graphical abstract ᅟ.

Beam test results of a monolithic pixel sensor in the 0.18 μm tower-jazz technology with high resistivity epitaxial layer

Energy Technology Data Exchange (ETDEWEB)

Mattiazzo, S., E-mail: serena.mattiazzo@pd.infn.it [Università degli Studi di Padova, Padova IT 35131 (Italy); Aimo, I. [Politecnico di Torino and Istituto Nazionale di Fisica Nucleare (INFN) Sezione di Torino, Torino IT 10129 (Italy); Baudot, J. [Universitè de Strasbourg, IPHC, Strasbourg F67037 (France); CNRS, MMR7178, Strasbourg F67037 (France); Bedda, C. [Politecnico di Torino and Istituto Nazionale di Fisica Nucleare (INFN) Sezione di Torino, Torino IT 10129 (Italy); La Rocca, P. [Università di Catania and Istituto Nazionale di Fisica Nucleare (INFN) Sezione di Catania, Catania IT 95123 (Italy); Perez, A. [Universitè de Strasbourg, IPHC, Strasbourg F67037 (France); CNRS, MMR7178, Strasbourg F67037 (France); Riggi, F. [Università di Catania and Istituto Nazionale di Fisica Nucleare (INFN) Sezione di Catania, Catania IT 95123 (Italy); Spiriti, E. [Istituto Nazionale di Fisica Nucleare (INFN) Laboratori Nazionali di Frascati and Sezione di Roma 3, Roma IT 00146 (Italy)

2015-10-01

The ALICE experiment at CERN will undergo a major upgrade in the second Long LHC Shutdown in the years 2018–2019; this upgrade includes the full replacement of the Inner Tracking System (ITS), deploying seven layers of Monolithic Active Pixel Sensors (MAPS). For the development of the new ALICE ITS, the Tower-Jazz 0.18 μm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel and different silicon wafers (including high resistivity epitaxial layers). A large test campaign has been carried out on several small prototype chips, designed to optimize the pixel sensor layout and the front-end electronics. Results match the target requirements both in terms of performance and of radiation hardness. Following this development, the first full scale chips have been designed, submitted and are currently under test, with promising results. A telescope composed of 4 planes of Mimosa-28 and 2 planes of Mimosa-18 chips is under development at the DAFNE Beam Test Facility (BTF) at the INFN Laboratori Nazionali di Frascati (LNF) in Italy with the final goal to perform a comparative test of the full scale prototypes. The telescope has been recently used to test a Mimosa-22THRb chip (a monolithic pixel sensor built in the 0.18 μm Tower-Jazz process) and we foresee to perform tests on the full scale chips for the ALICE ITS upgrade at the beginning of 2015. In this contribution we will describe some first measurements of spatial resolution, fake hit rate and detection efficiency of the Mimosa-22THRb chip obtained at the BTF facility in June 2014 with an electron beam of 500 MeV.

Beam test results of a monolithic pixel sensor in the 0.18 μm tower-jazz technology with high resistivity epitaxial layer

International Nuclear Information System (INIS)

Mattiazzo, S.; Aimo, I.; Baudot, J.; Bedda, C.; La Rocca, P.; Perez, A.; Riggi, F.; Spiriti, E.

2015-01-01

The ALICE experiment at CERN will undergo a major upgrade in the second Long LHC Shutdown in the years 2018–2019; this upgrade includes the full replacement of the Inner Tracking System (ITS), deploying seven layers of Monolithic Active Pixel Sensors (MAPS). For the development of the new ALICE ITS, the Tower-Jazz 0.18 μm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel and different silicon wafers (including high resistivity epitaxial layers). A large test campaign has been carried out on several small prototype chips, designed to optimize the pixel sensor layout and the front-end electronics. Results match the target requirements both in terms of performance and of radiation hardness. Following this development, the first full scale chips have been designed, submitted and are currently under test, with promising results. A telescope composed of 4 planes of Mimosa-28 and 2 planes of Mimosa-18 chips is under development at the DAFNE Beam Test Facility (BTF) at the INFN Laboratori Nazionali di Frascati (LNF) in Italy with the final goal to perform a comparative test of the full scale prototypes. The telescope has been recently used to test a Mimosa-22THRb chip (a monolithic pixel sensor built in the 0.18 μm Tower-Jazz process) and we foresee to perform tests on the full scale chips for the ALICE ITS upgrade at the beginning of 2015. In this contribution we will describe some first measurements of spatial resolution, fake hit rate and detection efficiency of the Mimosa-22THRb chip obtained at the BTF facility in June 2014 with an electron beam of 500 MeV

Beam test results of a monolithic pixel sensor in the 0.18 μm tower-jazz technology with high resistivity epitaxial layer

Science.gov (United States)

Mattiazzo, S.; Aimo, I.; Baudot, J.; Bedda, C.; La Rocca, P.; Perez, A.; Riggi, F.; Spiriti, E.

2015-10-01

The ALICE experiment at CERN will undergo a major upgrade in the second Long LHC Shutdown in the years 2018-2019; this upgrade includes the full replacement of the Inner Tracking System (ITS), deploying seven layers of Monolithic Active Pixel Sensors (MAPS). For the development of the new ALICE ITS, the Tower-Jazz 0.18 μm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel and different silicon wafers (including high resistivity epitaxial layers). A large test campaign has been carried out on several small prototype chips, designed to optimize the pixel sensor layout and the front-end electronics. Results match the target requirements both in terms of performance and of radiation hardness. Following this development, the first full scale chips have been designed, submitted and are currently under test, with promising results. A telescope composed of 4 planes of Mimosa-28 and 2 planes of Mimosa-18 chips is under development at the DAFNE Beam Test Facility (BTF) at the INFN Laboratori Nazionali di Frascati (LNF) in Italy with the final goal to perform a comparative test of the full scale prototypes. The telescope has been recently used to test a Mimosa-22THRb chip (a monolithic pixel sensor built in the 0.18 μm Tower-Jazz process) and we foresee to perform tests on the full scale chips for the ALICE ITS upgrade at the beginning of 2015. In this contribution we will describe some first measurements of spatial resolution, fake hit rate and detection efficiency of the Mimosa-22THRb chip obtained at the BTF facility in June 2014 with an electron beam of 500 MeV.

Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

Energy Technology Data Exchange (ETDEWEB)

Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

2010-11-01

Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

New generation of monolithic active pixel sensors for charged particle detection; Developpement d'un capteur de nouvelle generation et son electronique integree pour les collisionneurs futurs

Energy Technology Data Exchange (ETDEWEB)

Deptuch, G

2002-09-01

Vertex detectors are of great importance in particle physics experiments, as the knowledge of the event flavour is becoming an issue for the physics programme at Future Linear Colliders. Monolithic Active Pixel Sensors (MAPS) based on a novel detector structure have been proposed. Their fabrication is compatible with a standard CMOS process. The sensor is inseparable from the readout electronics, since both of them are integrated on the same, low-resistivity silicon wafer. The basic pixel configuration comprises only three MOS transistors and a diode collecting the charge through thermal diffusion. The charge is generated in the thin non-depleted epitaxial layer underneath the readout electronics. This approach provides, at low cost, a high resolution and thin device with the whole area sensitive to radiation. Device simulations using the ISE-TCAD package have been carried out to study the charge collection mechanism. In order to demonstrate the viability of the technique, four prototype chips have been fabricated using different submicrometer CMOS processes. The pixel gain has been calibrated using a {sup 55}Fe source and the Poisson sequence method. The prototypes have been exposed to high-energy particle beams at CERN. The tests proved excellent detection performances expressed in a single-track spatial resolution of 1.5 {mu}m and detection efficiency close to 100%, resulting from a SNR ratio of more than 30. Irradiation tests showed immunity of MAPS to a level of a few times 10{sup 12} n/cm{sup 2} and a few hundred kRad of ionising radiation. The ideas for future work, including on-pixel signal amplification, double sampling operation and current mode pixel design are present as well. (author)

Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

Energy Technology Data Exchange (ETDEWEB)

Liang, Z., E-mail: zhijun.liang@cern.ch [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Institute of High Energy Physics, Beijing (China); Affolder, A. [University of Liverpool (United Kingdom); Arndt, K. [University of Oxford (United Kingdom); Bates, R. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Benoit, M.; Di Bello, F. [University of Geneva (Switzerland); Blue, A. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Bortoletto, D. [University of Oxford (United Kingdom); Buckland, M. [University of Liverpool (United Kingdom); CERN, European Center for Nuclear Research (Switzerland); Buttar, C. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Caragiulo, P. [SLAC National Accelerator Laboratory (United States); Das, D.; Dopke, J. [Rutherford Appleton Laboratory, Didcot (United Kingdom); Dragone, A. [SLAC National Accelerator Laboratory (United States); Ehrler, F. [Karlsruhe Institute of Technology (Germany); Fadeyev, V.; Galloway, Z.; Grabas, H. [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Gregor, I.M. [Deutsches Elektronen-Synchrotron (Germany); Grenier, P. [SLAC National Accelerator Laboratory (United States); and others

2016-09-21

This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

Science.gov (United States)

Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

2014-06-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

New generation of monolithic active pixel sensors for charged particle detection; Developpement d'un capteur de nouvelle generation et son electronique integree pour les collisionneurs futurs

Energy Technology Data Exchange (ETDEWEB)

Deptuch, G

2002-09-01

Vertex detectors are of great importance in particle physics experiments, as the knowledge of the event flavour is becoming an issue for the physics programme at Future Linear Colliders. Monolithic Active Pixel Sensors (MAPS) based on a novel detector structure have been proposed. Their fabrication is compatible with a standard CMOS process. The sensor is inseparable from the readout electronics, since both of them are integrated on the same, low-resistivity silicon wafer. The basic pixel configuration comprises only three MOS transistors and a diode collecting the charge through thermal diffusion. The charge is generated in the thin non-depleted epitaxial layer underneath the readout electronics. This approach provides, at low cost, a high resolution and thin device with the whole area sensitive to radiation. Device simulations using the ISE-TCAD package have been carried out to study the charge collection mechanism. In order to demonstrate the viability of the technique, four prototype chips have been fabricated using different submicrometer CMOS processes. The pixel gain has been calibrated using a {sup 55}Fe source and the Poisson sequence method. The prototypes have been exposed to high-energy particle beams at CERN. The tests proved excellent detection performances expressed in a single-track spatial resolution of 1.5 {mu}m and detection efficiency close to 100%, resulting from a SNR ratio of more than 30. Irradiation tests showed immunity of MAPS to a level of a few times 10{sup 12} n/cm{sup 2} and a few hundred kRad of ionising radiation. The ideas for future work, including on-pixel signal amplification, double sampling operation and current mode pixel design are present as well. (author)

50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

Science.gov (United States)

Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

2015-12-07

Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

Acoustic of monolithic dome structures

Directory of Open Access Journals (Sweden)

Mostafa Refat Ismail

2018-03-01

The interior of monolithic domes have perfect, concave shapes to ensure that sound travels through the dome and perfectly collected at different vocal points. These dome structures are utilized for domestic use because the scale allows the focal points to be positioned across daily life activities, thereby affecting the sonic comfort of the internal space. This study examines the various acoustic treatments and parametric configurations of monolithic dome sizes. A geometric relationship of acoustic treatment and dome radius is established to provide architects guidelines on the correct selection of absorption needed to maintain the acoustic comfort of these special spaces.

Nano-Doped Monolithic Materials for Molecular Separation

Directory of Open Access Journals (Sweden)

Caleb Acquah

2017-01-01

Full Text Available Monoliths are continuous adsorbents that can easily be synthesised to possess tuneable meso-/macropores, convective fluid transport, and a plethora of chemistries for ligand immobilisation. They are grouped into three main classes: organic, inorganic, and hybrid, based on their chemical composition. These classes may also be differentiated by their unique morphological and physicochemical properties which are significantly relevant to their specific separation applications. The potential applications of monoliths for molecular separation have created the need to enhance their characteristic properties including mechanical strength, electrical conductivity, and chemical and thermal stability. An effective approach towards monolith enhancement has been the doping and/or hybridization with miniaturized molecular species of desirable functionalities and characteristics. Nanoparticles are usually preferred as dopants due to their high solid phase dispersion features which are associated with improved intermolecular adsorptive interactions. Examples of such nanomaterials include, but are not limited to, carbon-based, silica-based, gold-based, and alumina nanoparticles. The incorporation of these nanoparticles into monoliths via in situ polymerisation and/or post-modification enhances surface adsorption for activation and ligand immobilisation. Herein, insights into the performance enhancement of monoliths as chromatographic supports by nanoparticles doping are presented. In addition, the potential and characteristics of less common nanoparticle materials such as hydroxyapatite, ceria, hafnia, and germania are discussed. The advantages and challenges of nanoparticle doping of monoliths are also discussed.

Monolithic active pixel radiation detector with shielding techniques

Energy Technology Data Exchange (ETDEWEB)

Deptuch, Grzegorz W.

2018-03-20

A monolithic active pixel radiation detector including a method of fabricating thereof. The disclosed radiation detector can include a substrate comprising a silicon layer upon which electronics are configured. A plurality of channels can be formed on the silicon layer, wherein the plurality of channels are connected to sources of signals located in a bulk part of the substrate, and wherein the signals flow through electrically conducting vias established in an isolation oxide on the substrate. One or more nested wells can be configured from the substrate, wherein the nested wells assist in collecting charge carriers released in interaction with radiation and wherein the nested wells further separate the electronics from the sensing portion of the detector substrate. The detector can also be configured according to a thick SOA method of fabrication.

A CMOS-compatible large-scale monolithic integration of heterogeneous multi-sensors on flexible silicon for IoT applications

KAUST Repository

Nassar, Joanna M.

2017-02-07

We report CMOS technology enabled fabrication and system level integration of flexible bulk silicon (100) based multi-sensors platform which can simultaneously sense pressure, temperature, strain and humidity under various physical deformations. We also show an advanced wearable version for body vital monitoring which can enable advanced healthcare for IoT applications.

A CMOS-compatible large-scale monolithic integration of heterogeneous multi-sensors on flexible silicon for IoT applications

KAUST Repository

Nassar, Joanna M.; Sevilla, Galo T.; Velling, Seneca J.; Cordero, Marlon D.; Hussain, Muhammad Mustafa

2017-01-01

We report CMOS technology enabled fabrication and system level integration of flexible bulk silicon (100) based multi-sensors platform which can simultaneously sense pressure, temperature, strain and humidity under various physical deformations. We also show an advanced wearable version for body vital monitoring which can enable advanced healthcare for IoT applications.

Monolithic microwave integrated circuit devices for active array antennas

Science.gov (United States)

Mittra, R.

1984-01-01

Two different aspects of active antenna array design were investigated. The transition between monolithic microwave integrated circuits and rectangular waveguides was studied along with crosstalk in multiconductor transmission lines. The boundary value problem associated with a discontinuity in a microstrip line is formulated. This entailed, as a first step, the derivation of the propagating as well as evanescent modes of a microstrip line. The solution is derived to a simple discontinuity problem: change in width of the center strip. As for the multiconductor transmission line problem. A computer algorithm was developed for computing the crosstalk noise from the signal to the sense lines. The computation is based on the assumption that these lines are terminated in passive loads.

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

Science.gov (United States)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

Performance of a Fast Binary Readout CMOS Active Pixel Sensor Chip Designed for Charged Particle Detection

Science.gov (United States)

Deerli, Yavuz; Besanon, Marc; Besson, Auguste; Claus, Gilles; Deptuch, Grzegorz; Dulinski, Wojciech; Fourches, Nicolas; Goffe, Mathieu; Himmi, Abdelkader; Li, Yan; Lutz, Pierre; Orsini, Fabienne; Szelezniak, Michal

2006-12-01

We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

Development of CMOS pixel sensors for the upgrade of the ALICE Inner Tracking System

International Nuclear Information System (INIS)

Molnar, L.

2014-01-01

The ALICE Collaboration is preparing a major upgrade of the current detector, planned for installation during the second long LHC shutdown in the years 2018-19, in order to enhance its low-momentum vertexing and tracking capability, and exploit the planned increase of the LHC luminosity with Pb beams. One of the cornerstones of the ALICE upgrade strategy is to replace the current Inner Tracking System in its entirety with a new, high resolution, low-material ITS detector. The new ITS will consist of seven concentric layers equipped with Monolithic Active Pixel Sensors (MAPS) implemented using the 0.18 μm CMOS technology of TowerJazz. In this contribution, the main key features of the ITS upgrade will be illustrated with emphasis on the functionality of the pixel chip. The ongoing developments on the readout architectures, which have been implemented in several fabricated prototypes, will be discussed. The operational features of these prototypes as well as the results of the characterisation tests before and after irradiation will also be presented

Development of CMOS pixel sensors for the upgrade of the ALICE Inner Tracking System

Science.gov (United States)

Molnar, L.

2014-12-01

The ALICE Collaboration is preparing a major upgrade of the current detector, planned for installation during the second long LHC shutdown in the years 2018-19, in order to enhance its low-momentum vertexing and tracking capability, and exploit the planned increase of the LHC luminosity with Pb beams. One of the cornerstones of the ALICE upgrade strategy is to replace the current Inner Tracking System in its entirety with a new, high resolution, low-material ITS detector. The new ITS will consist of seven concentric layers equipped with Monolithic Active Pixel Sensors (MAPS) implemented using the 0.18 μm CMOS technology of TowerJazz. In this contribution, the main key features of the ITS upgrade will be illustrated with emphasis on the functionality of the pixel chip. The ongoing developments on the readout architectures, which have been implemented in several fabricated prototypes, will be discussed. The operational features of these prototypes as well as the results of the characterisation tests before and after irradiation will also be presented.

CMOS Image Sensors: Electronic Camera On A Chip

Science.gov (United States)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

International Nuclear Information System (INIS)

Liu, Yu-Chia; Tsai, Ming-Han; Fang, Weileun; Tang, Tsung-Lin

2011-01-01

This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

Large Format CMOS-based Detectors for Diffraction Studies

Science.gov (United States)

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

Large Format CMOS-based Detectors for Diffraction Studies

International Nuclear Information System (INIS)

Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

2013-01-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

Science.gov (United States)

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

International Nuclear Information System (INIS)

Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

2014-01-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

Développement d'un capteur à pixels CMOS pour un dosimètre spatial embarqué de faible poids et avec une dissipation de puissance minimale

OpenAIRE

Zhou , Yang

2014-01-01

This thesis focuses on the development of a CMOS monolithic pixel sensor used for space ionizingparticles identification and counting in high flux. A new concept for single particle identification isproposed in this study, which is based on the analysis of particle triggered clusters. To validate thisnew concept, a full size sensor including the sensitive pixel matrix, an analogue signal processingchain, a 3-bit analogue to digital converter, and a digital processing stage was designed in a 0...

Towards real-time VMAT verification using a prototype, high-speed CMOS active pixel sensor.

Science.gov (United States)

Zin, Hafiz M; Harris, Emma J; Osmond, John P F; Allinson, Nigel M; Evans, Philip M

2013-05-21

This work investigates the feasibility of using a prototype complementary metal oxide semiconductor active pixel sensor (CMOS APS) for real-time verification of volumetric modulated arc therapy (VMAT) treatment. The prototype CMOS APS used region of interest read out on the chip to allow fast imaging of up to 403.6 frames per second (f/s). The sensor was made larger (5.4 cm × 5.4 cm) using recent advances in photolithographic technique but retains fast imaging speed with the sensor's regional read out. There is a paradigm shift in radiotherapy treatment verification with the advent of advanced treatment techniques such as VMAT. This work has demonstrated that the APS can track multi leaf collimator (MLC) leaves moving at 18 mm s(-1) with an automatic edge tracking algorithm at accuracy better than 1.0 mm even at the fastest imaging speed. Evaluation of the measured fluence distribution for an example VMAT delivery sampled at 50.4 f/s was shown to agree well with the planned fluence distribution, with an average gamma pass rate of 96% at 3%/3 mm. The MLC leaves motion and linac pulse rate variation delivered throughout the VMAT treatment can also be measured. The results demonstrate the potential of CMOS APS technology as a real-time radiotherapy dosimeter for delivery of complex treatments such as VMAT.

Unique battery with a multi-functional, physicochemically active membrane separator/electrolyte-electrode monolith and a method making the same

Science.gov (United States)

Gerald II, Rex E.; Ruscic, Katarina J.; Sears, Devin N.; Smith, Luis J.; Klingler, Robert J.; Rathke, Jerome W.

2012-07-24

The invention relates to a unique battery having a physicochemically active membrane separator/electrolyte-electrode monolith and method of making the same. The Applicant's invented battery employs a physicochemically active membrane separator/electrolyte-electrode that acts as a separator, electrolyte, and electrode, within the same monolithic structure. The chemical composition, physical arrangement of molecules, and physical geometry of the pores play a role in the sequestration and conduction of ions. In one preferred embodiment, ions are transported via the ion-hoping mechanism where the oxygens of the Al2O3 wall are available for positive ion coordination (i.e. Li+). This active membrane-electrode composite can be adjusted to a desired level of ion conductivity by manipulating the chemical composition and structure of the pore wall to either increase or decrease ion conduction.

Fully integrated CMOS pixel detector for high energy particles

International Nuclear Information System (INIS)

Vanstraelen, G.; Debusschere, I.; Claeys, C.; Declerck, G.

1989-01-01

A novel type of position and energy sensitive, monolithic pixel array with integrated readout electronics is proposed. Special features of the design are a reduction of the number of output channels and of the amount of output data, and the use of transistors on the high resistivity silicon. The number of output channels for the detector array is reduced by handling in parallel a number of pixels, chosen as a function of the time resolution required for the system, and by the use of an address decoder. A further reduction of data is achieved by reading out only those pixels which have been activated. The pixel detector circuit will be realized in a 3 μm p-well CMOS process, which is optimized for the full integration of readout electronics and detector diodes on high resistivity Si. A retrograde well is formed by means of a high energy implantation, followed by the appropriate temperature steps. The optimization of the well shape takes into account the high substrate bias applied during the detector operation. The design is largely based on the use of MOS transistors on the high resistivity silicon itself. These have proven to perform as well as transistors on standard doped substrate. The basic building elements as well as the design strategy of the integrated pixel detector are presented in detail. (orig.)

BioCMOS Interfaces and Co-Design

CERN Document Server

Carrara, Sandro

2013-01-01

The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

Science.gov (United States)

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

A CMOS ASIC Design for SiPM Arrays.

Science.gov (United States)

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

2011-12-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization.

Science.gov (United States)

Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C; Patel, Tushita

2015-11-01

Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50-300 e-) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). In this study, imaging performance of a large area (29×23 cm2) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165-400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. The LFW mode shows better DQE at low air kerma (Ka<10 μGy) and should be used for DBT. At current DBT applications, air kerma (Ka∼10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165-400 μm in size can be resolved using a MGD range of 0.3-1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at MGD of 2.5 mGy), an increased CNR (by ∼10) for

High-voltage CMOS detectors

International Nuclear Information System (INIS)

Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

2016-01-01

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

High-voltage CMOS detectors

Energy Technology Data Exchange (ETDEWEB)

Ehrler, F., E-mail: felix.ehrler@student.kit.edu; Blanco, R.; Leys, R.; Perić, I.

2016-07-11

High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

Hybrid CMOS/Molecular Integrated Circuits

Science.gov (United States)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

CMOS pixel development for the ATLAS experiment at HL-LHC

CERN Document Server

Rimoldi, Marco; The ATLAS collaboration

2017-01-01

To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

A CMOS pressure sensor tag chip for passive wireless applications.

Science.gov (United States)

Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

2015-03-23

This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

Ion traps fabricated in a CMOS foundry

Energy Technology Data Exchange (ETDEWEB)

Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Integrated 60GHz RF beamforming in CMOS

CERN Document Server

Yu, Yikun; van Roermund, Arthur H M

2011-01-01

""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

CMOS front ends for millimeter wave wireless communication systems

CERN Document Server

Deferm, Noël

2015-01-01

This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

KAUST Repository

Saffih, Faycal; Elshurafa, Amro M.; Mohammad, Mohammad Ali; Nelson-Fitzpatrick, Nathan E.; Evoy, S.

2012-01-01

. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly

Analog filters in nanometer CMOS

CERN Document Server

Uhrmann, Heimo; Zimmermann, Horst

2014-01-01

Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

Microwaves integrated circuits: hybrids and monolithics - fabrication technology

International Nuclear Information System (INIS)

Cunha Pinto, J.K. da

1983-01-01

Several types of microwave integrated circuits are presented together with comments about technologies and fabrication processes; advantages and disadvantages in their utilization are analysed. Basic structures, propagation modes, materials used and major steps in the construction of hybrid thin film and monolithic microwave integrated circuits are described. Important technological applications are revised and main activities of the microelectronics lab. of the University of Sao Paulo (Brazil) in the field of hybrid and monolithic microwave integrated circuits are summarized. (C.L.B.) [pt

Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

Energy Technology Data Exchange (ETDEWEB)

Zhao, Chumin; Kanicki, Jerzy, E-mail: kanicki@eecs.umich.edu [Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109 (United States); Konstantinidis, Anastasios C. [Department of Medical Physics and Biomedical Engineering, University College London, London WC1E 6BT, United Kingdom and Diagnostic Radiology and Radiation Protection, Christie Medical Physics and Engineering, The Christie NHS Foundation Trust, Manchester M20 4BX (United Kingdom); Patel, Tushita [Department of Physics, University of Virginia, Charlottesville, Virginia 22908 (United States)

2015-11-15

Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e{sup −}) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm{sup 2}) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K{sub a} < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K{sub a} ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at

Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

International Nuclear Information System (INIS)

Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C.; Patel, Tushita

2015-01-01

Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e − ) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm 2 ) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K a < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K a ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at MGD of 2.5 m

Compressible and Recyclable Monolithic g-C3N4/Melamine Sponge: A Facile Ultrasonic-coating Approach and Enhanced Visible-light Photocatalytic Activity

Science.gov (United States)

Yang, Ye; Zhang, Qian; Zhang, Ruiyang; Ran, Tao; Wan, Wenchao; Zhou, Ying

2018-05-01

Powdery photocatalysts seriously restrict their practical application due to the difficult recycle and low photocatalytic activity. In this work, a monolithic g-C3N4/melamine sponge (g-C3N4/MS) was successfully fabricated by a cost-effective ultrasonic-coating route, which is easy to achieve the uniform dispersion and firm loading of g-C3N4 on MS skeleton. The monolithic g-C3N4/MS entirely inherits the porous structure of MS and results in a larger specific surface area (SSA) than its powdery counterpart. Benefit from this monolithic structure, g-C3N4/MS gains more exposed active sites, enhanced visible-light absorption and separation of photogenerated carriers, thus achieving noticeable photocatalytic activity on nitric oxide (NO) removal, rhodamine B (RhB) degradation and CO2 reduction. Specifically, NO removal ratio is as high as 78.6% which is 4.5 times higher than that of the powdery g-C3N4, while RhB degradation rate reaches 97.88%, and yield rate of CO and CH4 attains 7.48 and 3.93 μmol g-1 h-1. Importantly, the features of low-density, high porosity, good elasticity and firmness, not only endow g-C3N4/MS with flexibility in various environmental applications, but also make it easy to recycle and stable for long-time application. Our work provides a feasible approach to fabricate novel monolithic photocatalysts with large-scale production and application.

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

International Nuclear Information System (INIS)

Havranek, Miroslav

2014-09-01

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

Energy Technology Data Exchange (ETDEWEB)

Havranek, Miroslav

2014-09-15

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

CERN Document Server

Ristic, Branislav

2016-09-21

Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

Fibrous monolithic ceramics

International Nuclear Information System (INIS)

Kovar, D.; King, B.H.; Trice, R.W.; Halloran, J.W.

1997-01-01

Fibrous monolithic ceramics are an example of a laminate in which a controlled, three-dimensional structure has been introduced on a submillimeter scale. This unique structure allows this all-ceramic material to fail in a nonbrittle manner. Materials have been fabricated and tested with a variety of architectures. The influence on mechanical properties at room temperature and at high temperature of the structure of the constituent phases and the architecture in which they are arranged are discussed. The elastic properties of these materials can be effectively predicted using existing models. These models also can be extended to predict the strength of fibrous monoliths with an arbitrary orientation and architecture. However, the mechanisms that govern the energy absorption capacity of fibrous monoliths are unique, and experimental results do not follow existing models. Energy dissipation occurs through two dominant mechanisms--delamination of the weak interphases and then frictional sliding after cracking occurs. The properties of the constituent phases that maximize energy absorption are discussed. In this article, the authors examine the structure of Si 3 N 4 -BN fibrous monoliths from the submillimeter scale of the crack-deflecting cell-cell boundary features to the nanometer scale of the BN cell boundaries

Photodiode area effect on performance of X-ray CMOS active pixel sensors

Science.gov (United States)

Kim, M. S.; Kim, Y.; Kim, G.; Lim, K. T.; Cho, G.; Kim, D.

2018-02-01

Compared to conventional TFT-based X-ray imaging devices, CMOS-based X-ray imaging sensors are considered next generation because they can be manufactured in very small pixel pitches and can acquire high-speed images. In addition, CMOS-based sensors have the advantage of integration of various functional circuits within the sensor. The image quality can also be improved by the high fill-factor in large pixels. If the size of the subject is small, the size of the pixel must be reduced as a consequence. In addition, the fill factor must be reduced to aggregate various functional circuits within the pixel. In this study, 3T-APS (active pixel sensor) with photodiodes of four different sizes were fabricated and evaluated. It is well known that a larger photodiode leads to improved overall performance. Nonetheless, if the size of the photodiode is > 1000 μm2, the degree to which the sensor performance increases as the photodiode size increases, is reduced. As a result, considering the fill factor, pixel-pitch > 32 μm is not necessary to achieve high-efficiency image quality. In addition, poor image quality is to be expected unless special sensor-design techniques are included for sensors with a pixel pitch of 25 μm or less.

The upgrade of the ALICE Inner Tracking System - Status of the R&D; on monolithic silicon pixel sensors

CERN Document Server

Van Hoorne, Jacobus Willem

2014-01-01

s a major part of its upgrade plans, the ALICE experiment schedules the installation of a novel Inner Tracking System (ITS) during the Long Shutdown 2 (LS2) of the LHC in 2018/19. It will replace the present silicon tracker with seven layers of Monolithic Active Pixel Sensors (MAPS) and significantly improve the detector performance in terms of tracking and rate capabilities. The choice of technology has been guided by the tight requirements on the material budget of 0 : 3 % X = X 0 /layer for the three innermost layers and backed by the significant progress in the field of MAPS in recent years. The pixel chips are manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with a high resistivity epitaxial layer. Within the ongoing R&D; phase, several sensor chip prototypes have been developed and produced on different epitaxial layer thicknesses and resistivities. These chips are being characterized for their performance before and after irradiation using source tests, test beam and measu...

Characterization of 13 and 30 mum thick hydrogenated amorphous silicon diodes deposited over CMOS integrated circuits for particle detection application

CERN Document Server

Despeisse, M; Commichau, S C; Dissertori, G; Garrigos, A; Jarron, P; Miazza, C; Moraes, D; Shah, A; Wyrsch, N; Viertel, Gert M; 10.1016/j.nima.2003.11.022

2004-01-01

We present the experimental results obtained with a novel monolithic silicon pixel detector which consists in depositing a n-i-p hydrogenated amorphous silicon (a-Si:H) diode straight above the readout ASIC (this technology is called Thin Film on ASIC, TFA). The characterization has been performed on 13 and 30mum thick a-Si:H films deposited on top of an ASIC containing a linear array of high- speed low-noise transimpedance amplifiers designed in a 0.25mum CMOS technology. Experimental results presented have been obtained with a 600nm pulsed laser. The results of charge collection efficiency and charge collection speed of these structures are discussed.

Advanced Gasification Mercury/Trace Metal Control with Monolith Traps

Energy Technology Data Exchange (ETDEWEB)

Musich, Mark; Swanson, Michael; Dunham, Grant; Stanislowski, Joshua

2010-10-05

Two Corning monoliths and a non-carbon-based material have been identified as potential additives for mercury capture in syngas at temperatures above 400°F and pressure of 600 psig. A new Corning monolith formulation, GR-F1-2189, described as an active sample appeared to be the best monolith tested to date. The Corning SR Liquid monolith concept continues to be a strong candidate for mercury capture. Both monolith types allowed mercury reduction to below 5-μg/m{sup 3} (~5 ppb), a current U.S. Department of Energy (DOE) goal for trace metal control. Preparation methods for formulating the SR Liquid monolith impacted the ability of the monolith to capture mercury. The Energy & Environmental Research Center (EERC)-prepared Noncarbon Sorbents 1 and 2 appeared to offer potential for sustained and significant reduction of mercury concentration in the simulated fuel gas. The Noncarbon Sorbent 1 allowed sustained mercury reduction to below 5-μg/m{sup 3} (~5 ppb). The non-carbon-based sorbent appeared to offer the potential for regeneration, that is, desorption of mercury by temperature swing (using nitrogen and steam at temperatures above where adsorption takes place). A Corning cordierite monolith treated with a Group IB metal offered limited potential as a mercury sorbent. However, a Corning carbon-based monolith containing prereduced metallic species similar to those found on the noncarbon sorbents did not exhibit significant or sustained mercury reduction. EERC sorbents prepared with Group IB and IIB selenide appeared to have some promise for mercury capture. Unfortunately, these sorbents also released Se, as was evidenced by the measurement of H2Se in the effluent gas. All sorbents tested with arsine or hydrogen selenide, including Corning monoliths and the Group IB and IIB metal-based materials, showed an ability to capture arsine or hydrogen selenide at 400°F and 600 psig. Based on current testing, the noncarbon metal-based sorbents appear to be the most

ADVANCED GASIFICATION MERCURY/TRACE METAL CONTROL WITH MONOLITH TRAPS

Energy Technology Data Exchange (ETDEWEB)

Mark A. Musich; Michael L. Swanson; Grant E. Dunham; Joshua J. Stanislowski

2010-07-31

Two Corning monoliths and a non-carbon-based material have been identified as potential additives for mercury capture in syngas at temperatures above 400°F and pressure of 600 psig. A new Corning monolith formulation, GR-F1-2189, described as an active sample appeared to be the best monolith tested to date. The Corning SR Liquid monolith concept continues to be a strong candidate for mercury capture. Both monolith types allowed mercury reduction to below 5-μg/m3 (~5 ppb), a current U.S. Department of Energy (DOE) goal for trace metal control. Preparation methods for formulating the SR Liquid monolith impacted the ability of the monolith to capture mercury. The Energy & Environmental Research Center (EERC)-prepared Noncarbon Sorbents 1 and 2 appeared to offer potential for sustained and significant reduction of mercury concentration in the simulated fuel gas. The Noncarbon Sorbent 1 allowed sustained mercury reduction to below 5-μg/m3 (~5 ppb). The non-carbon-based sorbent appeared to offer the potential for regeneration, that is, desorption of mercury by temperature swing (using nitrogen and steam at temperatures above where adsorption takes place). A Corning cordierite monolith treated with a Group IB metal offered limited potential as a mercury sorbent. However, a Corning carbon-based monolith containing prereduced metallic species similar to those found on the noncarbon sorbents did not exhibit significant or sustained mercury reduction. EERC sorbents prepared with Group IB and IIB selenide appeared to have some promise for mercury capture. Unfortunately, these sorbents also released Se, as was evidenced by the measurement of H2Se in the effluent gas. All sorbents tested with arsine or hydrogen selenide, including Corning monoliths and the Group IB and IIB metal-based materials, showed an ability to capture arsine or hydrogen selenide at 400°F and 600 psig. Based on current testing, the noncarbon metal-based sorbents appear to be the most effective arsine

FLUIDIZED BED STEAM REFORMER MONOLITH FORMATION

International Nuclear Information System (INIS)

Jantzen, C

2006-01-01

Fluidized Bed Steam Reforming (FBSR) is being considered as an alternative technology for the immobilization of a wide variety of aqueous high sodium containing radioactive wastes at various DOE facilities in the United States. The addition of clay, charcoal, and a catalyst as co-reactants converts aqueous Low Activity Wastes (LAW) to a granular or ''mineralized'' waste form while converting organic components to CO 2 and steam, and nitrate/nitrite components, if any, to N 2 . The waste form produced is a multiphase mineral assemblage of Na-Al-Si (NAS) feldspathoid minerals with cage-like structures that atomically bond radionuclides like Tc-99 and anions such as SO 4 , I, F, and Cl. The granular product has been shown to be as durable as LAW glass. Shallow land burial requires that the mineralized waste form be able to sustain the weight of soil overburden and potential intrusion by future generations. The strength requirement necessitates binding the granular product into a monolith. FBSR mineral products were formulated into a variety of monoliths including various cements, Ceramicrete, and hydroceramics. All but one of the nine monoliths tested met the 2 durability specification for Na and Re (simulant for Tc-99) when tested using the Product Consistency Test (PCT; ASTM C1285). Of the nine monoliths tested the cements produced with 80-87 wt% FBSR product, the Ceramicrete, and the hydroceramic produced with 83.3 wt% FBSR product, met the compressive strength and durability requirements for an LAW waste form

CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

Science.gov (United States)

Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

1996-01-01

Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

International Nuclear Information System (INIS)

Zhao, C; Kanicki, J; Konstantinidis, A C; Zheng, Y; Speller, R D; Anaxagoras, T

2015-01-01

Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm −1 and a DQE of around 0.5 at spatial frequencies  <1 mm −1 . In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNR i ) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (∼1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered. (paper)

Monolithic exploding foil initiator

Science.gov (United States)

Welle, Eric J; Vianco, Paul T; Headley, Paul S; Jarrell, Jason A; Garrity, J. Emmett; Shelton, Keegan P; Marley, Stephen K

2012-10-23

A monolithic exploding foil initiator (EFI) or slapper detonator and the method for making the monolithic EFI wherein the exploding bridge and the dielectric from which the flyer will be generated are integrated directly onto the header. In some embodiments, the barrel is directly integrated directly onto the header.

Microelectronic test structures for CMOS technology

CERN Document Server

Ketchen, Mark B

2011-01-01

Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

A monolithic constant-fraction discriminator using distributed R-C delay-line shaping

International Nuclear Information System (INIS)

Simpson, M.L.; Young, G.R.; Xu, M.

1995-01-01

A monolithic, CMOS, constant-fraction discriminator (CFD) was fabricated in the Orbit Semiconductor, 1.2 μ N-well process. This circuit uses an on-chip, distributed, R-C delay-line to realize the constant-fraction shaping. The delay-line is constructed from a narrow, 500-μ serpentine layer of polysilicon above a wide, grounded, second layer of polysilicon. This R-C delay-line generates about 1.1 ns of delay for 5 ns risetime signals with a slope degradation of only ≅ 15% and an amplitude reduction of about 6.1%. The CFD also features an automatic walk adjustment. The entire circuit, including the delay line, has a 200 μ pitch and is 950 μ long. The walk for a 5 ns risetime signal was measured as ± 100 ps over the 100:1 dynamic range from -15 mV to -1.5 mV. to -1.5 V. The CFD consumes 15 mW

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

Science.gov (United States)

Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2018-01-01

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

Solid-phase microextraction of phthalate esters in water sample using different activated carbon-polymer monoliths as adsorbents.

Science.gov (United States)

Lirio, Stephen; Fu, Chung-Wei; Lin, Jhih-Yun; Hsu, Meng-Ju; Huang, Hsi-Ya

2016-07-13

In this study, the application of different activated carbon-polymer (AC-polymer) monoliths as adsorbents for the solid-phase microextraction (SPME) of phthalate esters (PAEs) in water sample were investigated. The activated carbon (AC) was embedded in organic polymers, poly(butyl methacrylate-co-ethylene dimethacrylate) (poly(BMA-EDMA)) or poly(styrene-co-divinylbenzene) (poly(STY-DVB)), via a 5-min microwave-assisted or a 15-min water bath heating polymerization. Preliminary investigation on the performance of the native poly(BMA-EDMA) and poly(STY-DVB) demonstrated remarkable adsorption efficiencies for PAEs. However, due to the strong hydrophobic, π-π, and hydrogen bonding interactions between the analytes and polymers, low extraction recoveries were achieved. In contrast, the presence of AC in native polymers not only enhanced the adsorption efficiencies but also assisted the PAE desorption, especially for AC-poly(STY-DVB) with extraction recovery ranged of 76.2-99.3%. Under the optimized conditions, the extraction recoveries for intra-, inter-day and column-to-column were in the range of 76.5-100.8% (<3.7% RSDs), 77.2-97.6% (<5.6% RSDs) and 75.5-99.7% (<6.2% RSDs), respectively. The developed AC-poly(STY-DVB) monolithic column showed good mechanical stability, which can be reused for more than 30 extraction times without any significant loss in the extraction recoveries of PAEs. The AC-poly(STY-DVB) monolithic column was successfully applied in SPME of PAEs in water sample with extraction recovery ranged of 78.8%-104.6% (<5.5% RSDs). Copyright © 2016 Elsevier B.V. All rights reserved.

Characterization of 13 and 30 μm thick hydrogenated amorphous silicon diodes deposited over CMOS integrated circuits for particle detection application

International Nuclear Information System (INIS)

Despeisse, M.; Anelli, G.; Commichau, S.; Dissertori, G.; Garrigos, A.; Jarron, P.; Miazza, C.; Moraes, D.; Shah, A.; Wyrsch, N.; Viertel, G.

2004-01-01

We present the experimental results obtained with a novel monolithic silicon pixel detector which consists in depositing a n-i-p hydrogenated amorphous silicon (a-Si:H) diode straight above the readout ASIC (this technology is called Thin Film on ASIC, TFA). The characterization has been performed on 13 and 30 μm thick a-Si:H films deposited on top of an ASIC containing a linear array of high-speed low-noise transimpedance amplifiers designed in a 0.25 μm CMOS technology. Experimental results presented have been obtained with a 600 nm pulsed laser. The results of charge collection efficiency and charge collection speed of these structures are discussed

FLUIDIZED BED STEAM REFORMER MONOLITH FORMATION

Energy Technology Data Exchange (ETDEWEB)

Jantzen, C

2006-12-22

Fluidized Bed Steam Reforming (FBSR) is being considered as an alternative technology for the immobilization of a wide variety of aqueous high sodium containing radioactive wastes at various DOE facilities in the United States. The addition of clay, charcoal, and a catalyst as co-reactants converts aqueous Low Activity Wastes (LAW) to a granular or ''mineralized'' waste form while converting organic components to CO{sub 2} and steam, and nitrate/nitrite components, if any, to N{sub 2}. The waste form produced is a multiphase mineral assemblage of Na-Al-Si (NAS) feldspathoid minerals with cage-like structures that atomically bond radionuclides like Tc-99 and anions such as SO{sub 4}, I, F, and Cl. The granular product has been shown to be as durable as LAW glass. Shallow land burial requires that the mineralized waste form be able to sustain the weight of soil overburden and potential intrusion by future generations. The strength requirement necessitates binding the granular product into a monolith. FBSR mineral products were formulated into a variety of monoliths including various cements, Ceramicrete, and hydroceramics. All but one of the nine monoliths tested met the <2g/m{sup 2} durability specification for Na and Re (simulant for Tc-99) when tested using the Product Consistency Test (PCT; ASTM C1285). Of the nine monoliths tested the cements produced with 80-87 wt% FBSR product, the Ceramicrete, and the hydroceramic produced with 83.3 wt% FBSR product, met the compressive strength and durability requirements for an LAW waste form.

Development of a Large-Format Science-Grade CMOS Active Pixel Sensor, for Extreme Ultra Violet Spectroscopy and Imaging in Space Science

National Research Council Canada - National Science Library

Waltham, N. R; Prydderch, M; Mapson-Menard, H; Morrissey, Q; Turchetta, R; Pool, P; Harris, A

2005-01-01

We describe our programme to develop a large-format science-grade CMOS active pixel sensor for future space science missions, and in particular an extreme ultra-violet spectrograph for solar physics...

Integrated imaging sensor systems with CMOS active pixel sensor technology

Science.gov (United States)

Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

2002-01-01

This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-{mu}m CMOS

Energy Technology Data Exchange (ETDEWEB)

Zhang Changchun; Wang Zhigong; Shi Si; Guo Yufeng, E-mail: zgwang@seu.edu.c [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

2010-03-15

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-{mu}m CMOS technology. The Pottbaecker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 x 440 {mu}m{sup 2}, and consumes apower of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV It has a pull-in range of 800 MHz, and a phase noise of -111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components. (semiconductor integrated circuits)

Latest results of the R and D on CMOS MAPS for the Layer0 of the SuperB SVT

Energy Technology Data Exchange (ETDEWEB)

Balestri, G. [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Batignani, G. [Università degli Studi di Pisa (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Beck, G. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); Bernardelli, A. [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Berra, A. [Università dell' Insubria, Como (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Milano Bicocca (Italy); Bettarini, S. [Università degli Studi di Pisa (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Bevan, A. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); Bombelli, L. [Politecnico di Milano (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Milano (Italy); Bosi, F. [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Bosisio, L. [Università degli Studi di Trieste (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Trieste (Italy); Casarosa, G., E-mail: giulia.casarosa@pi.infn.it [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Ceccanti, M. [Istituto Nazionale di Fisica Nucleare, Sezione di Pisa (Italy); Cenci, R. [University of Maryland (United States); Citterio, M.; Coelli, S. [Istituto Nazionale di Fisica Nucleare, Sezione di Milano (Italy); Comotti, D. [Università degli Studi di Bergamo (Italy); Dalla Betta, G.-F. [Università degli Studi di Trento (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Padova (Italy); Fabbri, L. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); and others

2013-12-21

Physics and high background conditions set very challenging requirements on readout speed, material budget and resolution for the innermost layer of the SuperB Silicon Vertex Tracker operated at the full luminosity. Monolithic Active Pixel Sensors (MAPS) are very appealing in this application since the thin sensitive region allows grinding the substrate to tens of microns. Deep N-Well MAPS, developed in the ST 130 nm CMOS technology, achieved in-pixel sparsification and fast time stamping. Further improvements are being explored with an intense R and D program, including both vertical integration and 2D MAPS with the INMAPS quadruple well. We present the results of the characterization with IR laser, radioactive sources and beam of several chips produced with the 3D (Chartered/Tezzaron) process. We have also studied prototypes exploiting the features of the quadruple well and the high resistivity epitaxial layer of the INMAPS 180 nm process. Promising results from an irradiation campaign with neutrons on small matrices and other test-structures, as well as the response of the sensors to high energy charged tracks are presented.

High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

Science.gov (United States)

Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

2010-12-15

A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

Optoelectronic circuits in nanometer CMOS technology

CERN Document Server

Atef, Mohamed

2016-01-01

This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

Simple BiCMOS CCCTA design and resistorless analog function realization.

Science.gov (United States)

Tangsrirat, Worapong

2014-01-01

The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

Simple BiCMOS CCCTA Design and Resistorless Analog Function Realization

Directory of Open Access Journals (Sweden)

Worapong Tangsrirat

2014-01-01

Full Text Available The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (Rx and current transfer (io/iz, are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

Electrical Interconnections Through CMOS Wafers

DEFF Research Database (Denmark)

Rasmussen, Frank Engel

2003-01-01

Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

CMOS test and evaluation a physical perspective

CERN Document Server

Bhushan, Manjul

2015-01-01

This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

Investigation of Toshiba 130nm CMOS process as a possible candidate for active silicon sensors in HEP and X-ray experiments

Energy Technology Data Exchange (ETDEWEB)

Fu, Yunan; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany); Peric, Ivan [Karlsruhe Institute of Technology, Karlsruhe (Germany)

2015-07-01

Following the advances of commercial semiconductor manufacturing technologies there has recently been an increased interest within experimental physics community in applying CMOS manufacturing processes to developing active silicon sensors. Possibility of applying high voltage bias combined with high resistivity substrate allows for better depletion of sensor and therefore quicker and more efficient charge collection. One of processes that accommodates those features is Toshiba 130 nm CMOS technology (CMOS3E). Within our group a test chip was designed to examine the suitability of this technology for physics experiment (both for HEP and X-ray imaging). Design consisted of 4 pixel matrices with total of 12 different pixel flavors allowing for evaluation of various pixel geometries and architectures in terms of depletion depth, noise performance, charge collection efficiency, etc. During this talk initial outcome of this evaluation is presented, starting with brief introduction to technology itself, followed by results of TCAD simulations, description of final design and first measurements results.

Contact CMOS imaging of gaseous oxygen sensor array.

Science.gov (United States)

Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

2011-10-01

We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

Absorbed dose by a CMOS in radiotherapy

International Nuclear Information System (INIS)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

2011-10-01

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

Science.gov (United States)

Riegel, C.; Backhaus, M.; Van Hoorne, J. W.; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

2017-01-01

A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 1015 n/cm2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

Neutron absorbed dose in a pacemaker CMOS

International Nuclear Information System (INIS)

Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

2012-01-01

The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

Neutron absorbed dose in a pacemaker CMOS

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2012-06-15

The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

Microfluidic devices and methods including porous polymer monoliths

Science.gov (United States)

Hatch, Anson V; Sommer, Gregory J; Singh, Anup K; Wang, Ying-Chih; Abhyankar, Vinay V

2014-04-22

Microfluidic devices and methods including porous polymer monoliths are described. Polymerization techniques may be used to generate porous polymer monoliths having pores defined by a liquid component of a fluid mixture. The fluid mixture may contain iniferters and the resulting porous polymer monolith may include surfaces terminated with iniferter species. Capture molecules may then be grafted to the monolith pores.

A monolithic RF transceiver for DC-OFDM UWB

International Nuclear Information System (INIS)

Chen Yunfeng; Li Wei; Fu Haipeng; Gao Ting; Chen Danfeng; Zhou Feng; Cai Deyun; Li Dan; Niu Yangyang; Zhou Hanchao; Zhu Ning; Li Ning; Ren Junyan

2012-01-01

This paper presents a first monolithic RF transceiver for DC-OFDM UWB applications. The proposed direct-conversion transceiver integrates all the building blocks including two receiver (Rx) cores, two transmitter (Tx) cores and a dual-carrier frequency synthesizer (DC-FS) as well as a 3-wire serial peripheral interface (SPI) to set the operating status of the transceiver. The ESD-protected chip is fabricated by a TSMC 0.13-μm RF CMOS process with a die size of 4.5 × 3.6 mm 2 . The measurement results show that the wideband Rx achieves an NF of 5–6.2 dB, a max gain of 76–84 dB with 64-dB variable gain, an in-/out-of-band IIP3 of −6/+4 dBm and an input loss S 11 of < −10 in all bands. The Tx achieves an LOLRR/IMGRR of −34/-33 dBc, a typical OIP3 of +6 dBm and a maximum output power of −5 dBm. The DC-FS outputs two separate carriers simultaneously with an inter-band hopping time of < 1.2 ns. The full chip consumes a maximum current of 420 mA under a 1.2-V supply. (semiconductor integrated circuits)

Absorbed dose by a CMOS in radiotherapy

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2011-10-15

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Wideband CMOS receivers

CERN Document Server

Oliveira, Luis

2015-01-01

This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

Site-Controlled Growth of Monolithic InGaAs/InP Quantum Well Nanopillar Lasers on Silicon.

Science.gov (United States)

Schuster, Fabian; Kapraun, Jonas; Malheiros-Silveira, Gilliard N; Deshpande, Saniya; Chang-Hasnain, Connie J

2017-04-12

In this Letter, we report the site-controlled growth of InP nanolasers on a silicon substrate with patterned SiO 2 nanomasks by low-temperature metal-organic chemical vapor deposition, compatible with silicon complementary metal-oxide-semiconductor (CMOS) post-processing. A two-step growth procedure is presented to achieve smooth wurtzite faceting of vertical nanopillars. By incorporating InGaAs multiquantum wells, the nanopillar emission can be tuned over a wide spectral range. Enhanced quality factors of the intrinsic InP nanopillar cavities promote lasing at 0.87 and 1.21 μm, located within two important optical telecommunication bands. This is the first demonstration of a site-controlled III-V nanolaser monolithically integrated on silicon with a silicon-transparent emission wavelength, paving the way for energy-efficient on-chip optical links at typical telecommunication wavelengths.

CMOS-based active RC sinusoidal oscillator with four-phase quadrature outputs and single-resistance-controlled (SRC) tuning laws

OpenAIRE

Lahiri, Abhirup; Herencsár, Norbert

2012-01-01

This paper proposes a very compact CMOS realization of active RC sinusoidal oscillator capable of generating four quadrature voltage outputs. The oscillator is based on the cascade of lossless and lossy integrators in loop. The governing laws for the condition of oscillation (CO) and the frequency of oscillation (FO) are single-resistance-controlled (SRC) and which allow independent FO tuning. Unlike previously reported SRC-based sinusoidal oscillators based on the active building block (ABB)...

Study on the correlation between the surface active species of Pd/cordierite monolithic catalyst and its catalytic activity

International Nuclear Information System (INIS)

Liao, Hengcheng; Zuo, Peiyuan; Liu, Miaomiao

2016-01-01

Two Pd-loading routes and three Pd-precursor matters were adopted to prepare Pd/(Ce,Y)O_2/γ-Al_2O_3/cordierite monolithic catalyst. The surface active species on the catalyst were characterized by XPS, and its catalytic activity for methane combustion was tested, and the dynamics of the catalytic combustion reaction was also discussed. Pd-loading route and Pd-precursor mass have a significant influence on the catalytic activity and surface active species. The sol dipping method is more advanced than the aqueous solution impregnating method. PN-sol catalyst, by sol dipping combined with Pd(NO_3)_2-precursor, has the best catalytic activity. The physical reason is the unique active Pd phase coexisting with active PdO phase on the surface, and thus the Pd3d_5_/_2 binding energy of surface species and apparent activation energy of combustion reaction are considerably decreased. The catalytic activity index, Pd3d_5_/_2 binding energy and apparent activation energy are highly tied each other with exponential relations.

RAPS: an innovative active pixel for particle detection integrated in CMOS technology

International Nuclear Information System (INIS)

Passeri, Daniele; Placidi, Pisana; Verducci, Leonardo; Ciampolini, Paolo; Matrella, Guido; Marras, Alessandro; Bilei, G.M.

2004-01-01

In this paper we discuss some design, implementation and test issues, with respect to the development of the RAPS01 chip in the framework of the Radiation Active Pixel Sensors (RAPS) INFN project. The project aimed at verifying feasibility of smart, high-resolution pixel arrays with a fully standard, submicron CMOS technology for particle detection purposes. Layout optimization of the pixel, including sensitive element and local read and amplification circuits has been carried out. Different basic pixel schemes and read-out options have been proposed and devised. Chip fabrication has been completed and test phase is now under way: to this purpose a suitable test environment has been devised and test strategies have been planned

MAPS development for the ALICE ITS upgrade

OpenAIRE

Yang, P; Aglieri, G; Cavicchioli, C; Chalmet, P L; Chanlek, N; Collu, A; Gao, C; Hillemanns, H; Junique, A; Kofarago, M; Keil, M; Kugathasan, T; Kim, D; Kim, J; Lattuca, A

2015-01-01

Monolithic Active Pixel Sensors (MAPS) offer the possibility to build pixel detectors and tracking layers with high spatial resolution and low material budget in commercial CMOS processes. Significant progress has been made in the field of MAPS in recent years, and they are now considered for the upgrades of the LHC experiments. This contribution will focus on MAPS detectors developed for the ALICE Inner Tracking System (ITS) upgrade and manufactured in the TowerJazz 180 nm CMOS imaging senso...

Microfabrication and Characterization of an Integrated 3-Axis CMOS-MEMS Accelerometer

Directory of Open Access Journals (Sweden)

Hongwei QU

2007-10-01

Full Text Available This paper reports the fabrication and characterization of a monolithically integrated 3-axis CMOS-MEMS accelerometer with a single proof mass. An improved microfabrication process has been developed to solve the structure overheating and particle contamination problems in the plasma etching processes of device fabrication. The whole device is made of bulk silicon except for some short thin films for electrical isolation, allowing large sensing capacitance and flat device structure. A low-noise, low-power amplifier is designed for each axis, which provides 40 dB on-chip amplification and consumes only 1 mW power. Quasi-static and dynamic characterization of the fabricated device has been performed. The measured sensitivities of the lateral- and z-axis accelerometers are 560 mV/g and 320 mV/g, respectively, which can be tuned by simply varying the amplitude of the modulation signal. The over-all noise floors of the lateral- and z-axis are 12 μg/ÖHz and 110 μg/ÖHz, respectively when tested at 200 Hz.

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

CERN Document Server

Bronuzzi, J.; Moll, M.; Sallese, J.M.

2016-01-01

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

CERN Document Server

El-Khatib, Ziad; Mahmoud, Samy A

2012-01-01

This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

Monolithic spectrometer

Energy Technology Data Exchange (ETDEWEB)

Rajic, Slobodan (Knoxville, TN); Egert, Charles M. (Oak Ridge, TN); Kahl, William K. (Knoxville, TN); Snyder, Jr., William B. (Knoxville, TN); Evans, III, Boyd M. (Oak Ridge, TN); Marlar, Troy A. (Knoxville, TN); Cunningham, Joseph P. (Oak Ridge, TN)

1998-01-01

A monolithic spectrometer is disclosed for use in spectroscopy. The spectrometer is a single body of translucent material with positioned surfaces for the transmission, reflection and spectral analysis of light rays.

Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

Science.gov (United States)

Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

2017-05-01

In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

Preparation of Highly Porous Binderless Active Carbon Monoliths from Waste Aspen Sawdust

Directory of Open Access Journals (Sweden)

Dawei Li

2014-01-01

Full Text Available Waste aspen sawdust was used as a precursor to prepare binderless active carbon monoliths (ACMs with high porosities. The ACMs were prepared by activation with H3PO4 at different activation temperatures (500 to 700 °C and retention times (1 to 3 h. Their morphologies, yields, textural properties, and microcrystalline structures were investigated using scanning electron microscopy (SEM, an analytical balance, N2 adsorption/desorption techniques, and X-ray diffraction (XRD. The results indicated that waste aspen sawdust could be successfully converted into highly porous binderless ACMs. The apparent specific surface area (SSA and yield of ACMs were in the range of 688 to 951 m2/g and 26.6 to 36.2%, respectively. Highly microporous ACMs with a micropore percentage of 91.1%, apparent specific surface area of 951 m2/g, pore volume of 0.481 mL/g, and bulk density of 0.56 g/mL could be produced by activation at 700 °C for 1 h. Increasing the activation temperature or retention time increased the specific surface area, pore volume, and turbostratic degree, but decreased the yield.

A CMOS Morlet Wavelet Generator

Directory of Open Access Journals (Sweden)

A. I. Bautista-Castillo

2017-04-01

Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

CMOS image sensors: State-of-the-art

Science.gov (United States)

Theuwissen, Albert J. P.

2008-09-01

This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

Recent progress in low-temperature-process monolithic three dimension technology

Science.gov (United States)

Yang, Chih-Chao; Hsieh, Tung-Ying; Huang, Wen-Hsien; Shen, Chang-Hong; Shieh, Jia-Min; Yeh, Wen-Kuan; Wu, Meng-Chyi

2018-04-01

Monolithic three-dimension (3D) integration is an ultimate alternative method of fabricating high density, high performance, and multi-functional integrated circuits. It offers the promise of being a new approach to increase system performance. How to manage the thermal impact of multi-tiered processes, such as dopant activation, source/drain silicidation, and channel formation, and to prevent the degradation of pre-existing devices/circuits become key challenges. In this paper, we provide updates on several important monolithic 3D works, particularly in sequentially stackable channels, and our recent achievements in monolithic 3D integrated circuit (3D-IC). These results indicate that the advanced 3D architecture with novel design tools enables ultrahigh-density stackable circuits to have superior performance and low power consumption for future artificial intelligence (AI) and internet of things (IoTs) application.

The implementation of CMOS sensors within a real time digital mammography intelligent imaging system: The I-ImaS System

Science.gov (United States)

Esbrand, C.; Royle, G.; Griffiths, J.; Speller, R.

2009-07-01

The integration of technology with healthcare has undoubtedly propelled the medical imaging sector well into the twenty first century. The concept of digital imaging introduced during the 1970s has since paved the way for established imaging techniques where digital mammography, phase contrast imaging and CT imaging are just a few examples. This paper presents a prototype intelligent digital mammography system designed and developed by a European consortium. The final system, the I-ImaS system, utilises CMOS monolithic active pixel sensor (MAPS) technology promoting on-chip data processing, enabling the acts of data processing and image acquisition to be achieved simultaneously; consequently, statistical analysis of tissue is achievable in real-time for the purpose of x-ray beam modulation via a feedback mechanism during the image acquisition procedure. The imager implements a dual array of twenty 520 pixel × 40 pixel CMOS MAPS sensing devices with a 32μm pixel size, each individually coupled to a 100μm thick thallium doped structured CsI scintillator. This paper presents the first intelligent images of real breast tissue obtained from the prototype system of real excised breast tissue where the x-ray exposure was modulated via the statistical information extracted from the breast tissue itself. Conventional images were experimentally acquired where the statistical analysis of the data was done off-line, resulting in the production of simulated real-time intelligently optimised images. The results obtained indicate real-time image optimisation using the statistical information extracted from the breast as a means of a feedback mechanisms is beneficial and foreseeable in the near future.

Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology

Science.gov (United States)

Muhamad, M.; Soin, N.; Ramiah, H.

2018-03-01

This paper presents about design and optimization of CMOS active inductor integrated circuit. This active inductor implements using Silterra 0.13μm technology and simulated using Cadence Virtuoso and Spectre RF. The center frequency for this active inductor is at 2.4 GHz which follow IEEE 802.11 b/g/n standard. To reduce the chip size of silicon, active inductor is used instead of passive inductor at low noise amplifier LNA circuit. This inductor test and analyse by low noise amplifier circuit. Comparison between active with passive inductor based on LNA circuit has been performed. Result shown that the active inductor has significantly reduce the chip size with 73 % area without sacrificing the noise figure and gain of LNA which is the most important criteria in LNA. The best low noise amplifier provides a power gain (S21) of 20.7 dB with noise figure (NF) of 2.1dB.

Beyond CMOS nanodevices 1

CERN Document Server

Balestra, Francis

2014-01-01

This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

Beyond CMOS nanodevices 2

CERN Document Server

Balestra, Francis

2014-01-01

This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

Design and characterization of novel monolithic pixel sensors for the ALICE ITS upgrade

Science.gov (United States)

Cavicchioli, C.; Chalmet, P. L.; Giubilato, P.; Hillemanns, H.; Junique, A.; Kugathasan, T.; Mager, M.; Marin Tobon, C. A.; Martinengo, P.; Mattiazzo, S.; Mugnier, H.; Musa, L.; Pantano, D.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Van Hoorne, J. W.; Yang, P.

2014-11-01

Within the R&D activities for the upgrade of the ALICE Inner Tracking System (ITS), Monolithic Active Pixel Sensors (MAPS) are being developed and studied, due to their lower material budget ( 0.3 %X0 in total for each inner layer) and higher granularity ( 20 μm × 20 μm pixels) with respect to the present pixel detector. This paper presents the design and characterization results of the Explorer0 chip, manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a wafer with high-resistivity (ρ > 1 kΩ cm) and 18 μm thick epitaxial layer. The chip is organized in two sub-matrices with different pixel pitches (20 μm and 30 μm), each of them containing several pixel designs. The collection electrode size and shape, as well as the distance between the electrode and the surrounding electronics, are varied; the chip also offers the possibility to decouple the charge integration time from the readout time, and to change the sensor bias. The charge collection properties of the different pixel variants implemented in Explorer0 have been studied using a 55Fe X-ray source and 1-5 GeV/c electrons and positrons. The sensor capacitance has been estimated, and the effect of the sensor bias has also been examined in detail. A second version of the Explorer0 chip (called Explorer1) has been submitted for production in March 2013, together with a novel circuit with in-pixel discrimination and a sparsified readout. Results from these submissions are also presented.

Monolithic solid-state lasers for spaceflight

Science.gov (United States)

Krainak, Michael A.; Yu, Anthony W.; Stephen, Mark A.; Merritt, Scott; Glebov, Leonid; Glebova, Larissa; Ryasnyanskiy, Aleksandr; Smirnov, Vadim; Mu, Xiaodong; Meissner, Stephanie; Meissner, Helmuth

2015-02-01

A new solution for building high power, solid state lasers for space flight is to fabricate the whole laser resonator in a single (monolithic) structure or alternatively to build a contiguous diffusion bonded or welded structure. Monolithic lasers provide numerous advantages for space flight solid-state lasers by minimizing misalignment concerns. The closed cavity is immune to contamination. The number of components is minimized thus increasing reliability. Bragg mirrors serve as the high reflector and output coupler thus minimizing optical coatings and coating damage. The Bragg mirrors also provide spectral and spatial mode selection for high fidelity. The monolithic structure allows short cavities resulting in short pulses. Passive saturable absorber Q-switches provide a soft aperture for spatial mode filtering and improved pointing stability. We will review our recent commercial and in-house developments toward fully monolithic solid-state lasers.

Methacrylate monolithic columns functionalized with epinephrine for capillary electrochromatography applications.

Science.gov (United States)

Carrasco-Correa, Enrique Javier; Ramis-Ramos, Guillermo; Herrero-Martínez, José Manuel

2013-07-12

Epinephrine-bonded polymeric monoliths for capillary electrochromatography (CEC) were developed by nucleophilic substitution reaction of epoxide groups of poly(glycidyl-methacrylate-co-ethylenedimethacrylate) (poly(GMA-co-EDMA)) monoliths using epinephrine as nucleophilic reagent. The ring opening reaction under dynamic conditions was optimized. Successful chemical modification of the monolith surface was ascertained by in situ Raman spectroscopy characterization. In addition, the amount of epinephrine groups that was bound to the monolith surface was evaluated by oxidation of the catechol groups with Ce(IV), followed by spectrophotometric measurement of unreacted Ce(IV). About 9% of all theoretical epoxide groups of the parent monolith were bonded to epinephrine. The chromatographic behavior of the epinephrine-bonded monolith in CEC conditions was assessed with test mixtures of alkyl benzenes, aniline derivatives and substituted phenols. In comparison to the poly(GMA-co-EDMA) monoliths, the epinephrine-bonded monoliths exhibited a much higher retention and slight differences in selectivity. The epinephrine-bonded monolith was further modified by oxidation with a Ce(IV) solution and compared with the epinephrine-bonded monoliths. The resulting monolithic stationary phases were evaluated in terms of reproducibility, giving RSD values below 9% in the parameters investigated. Copyright © 2013 Elsevier B.V. All rights reserved.

Variation-aware advanced CMOS devices and SRAM

CERN Document Server

Shin, Changhwan

2016-01-01

This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

Relation between textural and energetic parameters of activated carbon monoliths from coconut shells

International Nuclear Information System (INIS)

Vargas, Diana Paola; Giraldo, Liliana; Moreno, Juan C.

2009-01-01

Structural characteristics and the energetic parameters of five monoliths of activated carbon were compared. The samples were obtained from coconut shells by means of chemical activation using different concentrations of phosphoric acid. The samples are characterized by means of physical adsorption of N 2 at 77K, CO 2 at 273K, and immersion calorimetry in benzene. From the data obtained the volumes of micropore, mesopore, narrow micro porosity and energy parameters of immersion enthalpy were calculated. Also were calculated, K of the Langmuir model and characteristic energies, Eo, of the Dubinin-Radushkevich model. The experimental results show that the activation with phosphoric acid develops micro porosity, giving a micropore volume between 0,36 and 0,45 cm 3 g-1, area BET between 975 and 1320 m 2 g-1 and immersion enthalpy between 112,9 and 147,7 Jg-1. It was found that for higher BET area, there is a greater immersion enthalpy in benzene, lower characteristic energy and smaller value of K.

Test beam measurement of the first prototype of the fast silicon pixel monolithic detector for the TT-PET project

Science.gov (United States)

Paolozzi, L.; Bandi, Y.; Benoit, M.; Cardarelli, R.; Débieux, S.; Forshaw, D.; Hayakawa, D.; Iacobucci, G.; Kaynak, M.; Miucci, A.; Nessi, M.; Ratib, O.; Ripiccini, E.; Rücker, H.; Valerio, P.; Weber, M.

2018-04-01

The TT-PET collaboration is developing a PET scanner for small animals with 30 ps time-of-flight resolution and sub-millimetre 3D detection granularity. The sensitive element of the scanner is a monolithic silicon pixel detector based on state-of-the-art SiGe BiCMOS technology. The first ASIC prototype for the TT-PET was produced and tested in the laboratory and with minimum ionizing particles. The electronics exhibit an equivalent noise charge below 600 e‑ RMS and a pulse rise time of less than 2 ns , in accordance with the simulations. The pixels with a capacitance of 0.8 pF were measured to have a detection efficiency greater than 99% and, although in the absence of the post-processing, a time resolution of approximately 200 ps .

Mechanically stable, hierarchically porous Cu3(btc)2 (HKUST-1) monoliths via direct conversion of copper(II) hydroxide-based monoliths.

Science.gov (United States)

Moitra, Nirmalya; Fukumoto, Shotaro; Reboul, Julien; Sumida, Kenji; Zhu, Yang; Nakanishi, Kazuki; Furukawa, Shuhei; Kitagawa, Susumu; Kanamori, Kazuyoshi

2015-02-28

The synthesis of highly crystalline macro-meso-microporous monolithic Cu3(btc)2 (HKUST-1; btc(3-) = benzene-1,3,5-tricarboxylate) is demonstrated by direct conversion of Cu(OH)2-based monoliths while preserving the characteristic macroporous structure. The high mechanical strength of the monoliths is promising for possible applications to continuous flow reactors.

Design optimization of radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

1975-01-01

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

CMOS dot matrix microdisplay

Science.gov (United States)

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

A CMOS Image Sensor With In-Pixel Buried-Channel Source Follower and Optimized Row Selector

NARCIS (Netherlands)

Chen, Y.; Wang, X.; Mierop, A.J.; Theuwissen, A.J.P.

2009-01-01

This paper presents a CMOS imager sensor with pinned-photodiode 4T active pixels which use in-pixel buried-channel source followers (SFs) and optimized row selectors. The test sensor has been fabricated in a 0.18-mum CMOS process. The sensor characterization was carried out successfully, and the

An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

Science.gov (United States)

DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

2016-01-01

This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

Monolithic microwave integrated circuit with integral array antenna

International Nuclear Information System (INIS)

Stockton, R.J.; Munson, R.E.

1984-01-01

A monolithic microwave integrated circuit including an integral array antenna. The system includes radiating elements, feed network, phasing network, active and/or passive semiconductor devices, digital logic interface circuits and a microcomputer controller simultaneously incorporated on a single substrate by means of a controlled fabrication process sequence

Time-resolved optical spectrometer based on a monolithic array of high-precision TDCs and SPADs

Science.gov (United States)

Tamborini, Davide; Markovic, Bojan; Di Sieno, Laura; Contini, Davide; Bassi, Andrea; Tisa, Simone; Tosi, Alberto; Zappa, Franco

2013-12-01

We present a compact time-resolved spectrometer suitable for optical spectroscopy from 400 nm to 1 μm wavelengths. The detector consists of a monolithic array of 16 high-precision Time-to-Digital Converters (TDC) and Single-Photon Avalanche Diodes (SPAD). The instrument has 10 ps resolution and reaches 70 ps (FWHM) timing precision over a 160 ns full-scale range with a Differential Non-Linearity (DNL) better than 1.5 % LSB. The core of the spectrometer is the application-specific integrated chip composed of 16 pixels with 250 μm pitch, containing a 20 μm diameter SPAD and an independent TDC each, fabricated in a 0.35 μm CMOS technology. In front of this array a monochromator is used to focus different wavelengths into different pixels. The spectrometer has been used for fluorescence lifetime spectroscopy: 5 nm spectral resolution over an 80 nm bandwidth is achieved. Lifetime spectroscopy of Nile blue is demonstrated.

A monolithic integrated photonic microwave filter

Science.gov (United States)

Fandiño, Javier S.; Muñoz, Pascual; Doménech, David; Capmany, José

2017-02-01

Meeting the increasing demand for capacity in wireless networks requires the harnessing of higher regions in the radiofrequency spectrum, reducing cell size, as well as more compact, agile and power-efficient base stations that are capable of smoothly interfacing the radio and fibre segments. Fully functional microwave photonic chips are promising candidates in attempts to meet these goals. In recent years, many integrated microwave photonic chips have been reported in different technologies. To the best of our knowledge, none has monolithically integrated all the main active and passive optoelectronic components. Here, we report the first demonstration of a tunable microwave photonics filter that is monolithically integrated into an indium phosphide chip. The reconfigurable radiofrequency photonic filter includes all the necessary elements (for example, lasers, modulators and photodetectors), and its response can be tuned by means of control electric currents. This is an important step in demonstrating the feasibility of integrated and programmable microwave photonic processors.

Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

International Nuclear Information System (INIS)

Riegel, C.; Backhaus, M.; Hoorne, J.W. Van; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

2017-01-01

A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 10 15 n/cm 2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

Science.gov (United States)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Silicon monolithic microchannel-cooled laser diode array

International Nuclear Information System (INIS)

Skidmore, J. A.; Freitas, B. L.; Crawford, J.; Satariano, J.; Utterback, E.; DiMercurio, L.; Cutter, K.; Sutton, S.

2000-01-01

A monolithic microchannel-cooled laser diode array is demonstrated that allows multiple diode-bar mounting with negligible thermal cross talk. The heat sink comprises two main components: a wet-etched Si layer that is anodically bonded to a machined glass block. The continuous wave (cw) thermal resistance of the 10 bar diode array is 0.032 degree sign C/W, which matches the performance of discrete microchannel-cooled arrays. Up to 1.5 kW/cm 2 is achieved cw at an emission wavelength of ∼808 nm. Collimation of a diode array using a monolithic lens frame produced a 7.5 mrad divergence angle by a single active alignment. This diode array offers high average power/brightness in a simple, rugged, scalable architecture that is suitable for large two-dimensional areas. (c) 2000 American Institute of Physics

Polymethacrylate-based monoliths as stationary phases for separation of biopolymers and immobilization of enzymes.

Science.gov (United States)

Martinović, Tamara; Josić, Djuro

2017-11-01

The experiences in the production and application of polymethacrylate-based monolithic supports, since their development almost thirty years ago, are presented. The main driving force for the development of new chromatographic supports was the necessity for the isolation and separation of physiologically active biopolymers and their use for therapeutic purposes. For this sake, a development of a method for fast separation, preventing denaturation and preserving their biological activity was necessary. Development of polysaccharide-based supports, followed by the introduction of polymer-based chromatographic media, is shortly described. This development was followed by the advances in monolithic media that are now used for both large- and small-scale separation of biopolymers and nanoparticles. Finally, a short overview is given about the applications of monoliths for sample displacement chromatography, resulting in isolation of physiologically active biomolecules, such as proteins, protein complexes, and nucleic acid, as well as high-throughput sample preparation for proteomic investigations. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

CMOS Pixel Sensors for High Precision Beam Telescopes and Vertex Detectors

International Nuclear Information System (INIS)

Masi, R. de; Baudot, J.; Fontaine, J.-Ch.

2009-01-01

CMOS sensors of the MIMOSA (standing for Minimum Ionising particle MOS Active pixel sensor) series are developed at IPHC since a decade and have ended up with full scale devices used in beam telescopes and in demonstrators of future vertex detectors. The sensors deliver analogue, unfiltered, signals and are therefore limited to read-out frequencies of ∼ 1 kframe/s. Since a few years, a fast architecture is being developed in collaboration with IRFU, which aims to speed up the read-out by 1-2 orders of magnitude. The first full scale sensor based on this architecture was fabricated recently and is being tested. Made of 660,000 pixels (18 μm pitch) covering an active area of ∼ 2 cm 2 , it delivers zero-suppressed binary signals, which allow running at ∼ 10 kframes/s. It will equip the beam telescope of the E.U. project EUDET and serve as a forerunner of the sensor equipping the 2 layers of the PIXEL detector of the STAR experiment at RHIC. The contribution to the conference will overview the main features and test results of this pioneering sensor. It will next describe its evolution towards read-out frequencies approaching 100 kframes/s, as required for the vertex detectors of the CBM experiment at FAIR and at the ILC. Finally, the issue of radiation tolerance will be addressed, in the context of a newly available CMOS process using a depleted substrate. A prototype sensor was fabricated in a such CMOS process. The talk will summarise beam test results showing, for the first time, that fluences of 10 14 n eq /cm 2 may be tolerable for CMOS sensors. Overall, the talk provides an overview of the status and plans of CMOS pixel sensors at the frontier of their achievements and outreach. (author)

Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

KAUST Repository

Saffih, Faycal

2012-06-01

In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

Method for making a single-step etch mask for 3D monolithic nanostructures

International Nuclear Information System (INIS)

Grishina, D A; Harteveld, C A M; Vos, W L; Woldering, L A

2015-01-01

Current nanostructure fabrication by etching is usually limited to planar structures as they are defined by a planar mask. The realization of three-dimensional (3D) nanostructures by etching requires technologies beyond planar masks. We present a method for fabricating a 3D mask that allows one to etch three-dimensional monolithic nanostructures using only CMOS-compatible processes. The mask is written in a hard-mask layer that is deposited on two adjacent inclined surfaces of a Si wafer. By projecting in a single step two different 2D patterns within one 3D mask on the two inclined surfaces, the mutual alignment between the patterns is ensured. Thereby after the mask pattern is defined, the etching of deep pores in two oblique directions yields a three-dimensional structure in Si. As a proof of concept we demonstrate 3D mask fabrication for three-dimensional diamond-like photonic band gap crystals in silicon. The fabricated crystals reveal a broad stop gap in optical reflectivity measurements. We propose how 3D nanostructures with five different Bravais lattices can be realized, namely cubic, tetragonal, orthorhombic, monoclinic and hexagonal, and demonstrate a mask for a 3D hexagonal crystal. We also demonstrate the mask for a diamond-structure crystal with a 3D array of cavities. In general, the 2D patterns on the different surfaces can be completely independently structured and still be in perfect mutual alignment. Indeed, we observe an alignment accuracy of better than 3.0 nm between the 2D mask patterns on the inclined surfaces, which permits one to etch well-defined monolithic 3D nanostructures. (paper)

Monolith electroplating process

Science.gov (United States)

Agarrwal, Rajev R.

2001-01-01

An electroplating process for preparing a monolith metal layer over a polycrystalline base metal and the plated monolith product. A monolith layer has a variable thickness of one crystal. The process is typically carried in molten salts electrolytes, such as the halide salts under an inert atmosphere at an elevated temperature, and over deposition time periods and film thickness sufficient to sinter and recrystallize completely the nucleating metal particles into one single crystal or crystals having very large grains. In the process, a close-packed film of submicron particle (20) is formed on a suitable substrate at an elevated temperature. The temperature has the significance of annealing particles as they are formed, and substrates on which the particles can populate are desirable. As the packed bed thickens, the submicron particles develop necks (21) and as they merge into each other shrinkage (22) occurs. Then as micropores also close (23) by surface tension, metal density is reached and the film consists of unstable metal grain (24) that at high enough temperature recrystallize (25) and recrystallized grains grow into an annealed single crystal over the electroplating time span. While cadmium was used in the experimental work, other soft metals may be used.

A Standard CMOS Humidity Sensor without Post-Processing

OpenAIRE

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023?10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

Fully CMOS-compatible titanium nitride nanoantennas

Energy Technology Data Exchange (ETDEWEB)

Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

2016-02-01

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

A 13.56 MHz CMOS Active Rectifier With Switched-Offset and Compensated Biasing for Biomedical Wireless Power Transfer Systems.

Science.gov (United States)

Yan Lu; Wing-Hung Ki

2014-06-01

A full-wave active rectifier switching at 13.56 MHz with compensated bias current for a wide input range for wirelessly powered high-current biomedical implants is presented. The four diodes of a conventional passive rectifier are replaced by two cross-coupled PMOS transistors and two comparator- controlled NMOS switches to eliminate diode voltage drops such that high voltage conversion ratio and power conversion efficiency could be achieved even at low AC input amplitude |VAC|. The comparators are implemented with switched-offset biasing to compensate for the delays of active diodes and to eliminate multiple pulsing and reverse current. The proposed rectifier uses a modified CMOS peaking current source with bias current that is quasi-inversely proportional to the supply voltage to better control the reverse current over a wide AC input range (1.5 to 4 V). The rectifier was fabricated in a standard 0.35 μm CMOS N-well process with active area of 0.0651 mm(2). For the proposed rectifier measured at |VAC| = 3.0 V, the voltage conversion ratios are 0.89 and 0.93 for RL=500 Ω and 5 kΩ, respectively, and the measured power conversion efficiencies are 82.2% to 90.1% with |VAC| ranges from 1.5 to 4 V for RL=500 Ω.

A 0.13 μm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers

International Nuclear Information System (INIS)

Chu Xiaojie; Jia Hailong; Lin Min; Shi Yin; Foster, Dai Fa

2011-01-01

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers. A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor. The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) ΔΣ modulator with noise-shaped dithering techniques. Measurement results show that in all channels, phase noise of the synthesizer achieves −93 dBc/Hz and −118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz. The integrated RMS phase error is no more than 0.8°. The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm 2 . (semiconductor integrated circuits)

A 0.13 μm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers

Science.gov (United States)

Xiaojie, Chu; Hailong, Jia; Min, Lin; Yin, Shi; Foster, Dai Fa

2011-10-01

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers. A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor. The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) ΔΣ modulator with noise-shaped dithering techniques. Measurement results show that in all channels, phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz. The integrated RMS phase error is no more than 0.8°. The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.

III–Vs on Si for photonic applications—A monolithic approach

International Nuclear Information System (INIS)

Wang, Zhechao; Junesand, Carl; Metaferia, Wondwosen; Hu, Chen; Wosinski, Lech; Lourdudoss, Sebastian

2012-01-01

Highlights: ► Monolithic evanescently coupled silicon laser (MECSL) structure treated. ► Optical mode profiles and thermal resistivity of MECSL optimized by simulation. ► MECSL through epitaxial lateral overgrowth (ELOG) of InP on Si exemplified. ► Passive waveguide in MECSL also acts as the defect filtering mask in ELOG. ► Growth of dislocation free thin InP layer on Si by ELOG for MECSL demonstrated. - Abstract: Epitaxial lateral overgrowth (ELOG) technology is demonstrated as a viable technology to realize monolithic integration of III-Vs on silicon. As an alternative to wafer-to-wafer bonding and die-to-wafer bonding, ELOG provides an attractive platform for fabricating discrete and integrated components in high volume at low cost. A possible route for monolithic integration of III–Vs on silicon for silicon photonics is exemplified by the case of a monolithic evanescently coupled silicon laser (MECSL) by combining InP on Si/SiO 2 through ELOG. Passive waveguide in MECSL also acts as the defect filtering mask in ELOG. The structural design of a monolithic evanescently coupled silicon laser (MECSL) and its thermal resistivity are established through simulations. Material studies to realize the above laser through ELOG are undertaken by studying appropriate ELOG pattern designs to achieve InP on narrow regions of silicon. We show that defect-free InP can be obtained on SiO 2 as the first step which paves the way for realizing active photonic devices on Si/SiO 2 waveguides, e.g. an MECSL.

Translucency and Strength of High-Translucency Monolithic Zirconium-Oxide Materials

Science.gov (United States)

2016-05-12

Capt Todd D. Church APPROVED: Translucency and Strength of High-Translucency Monolithic Zirconium -Oxide Materials C~t) Kraig/[ Vandewalle Date...copyrighted material in the thesis/dissertation manuscript entitled: "Translucency arid Strength of High-Translucency Monolithic Zirconium -Oxide...Translucency Monolithic Zirconium -Oxide Materials Abstract Dental materials manufacturers have developed more translucent monolithic zirconium oxide

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

Directory of Open Access Journals (Sweden)

Mohammad Reza Shokrani

2014-01-01

Full Text Available This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

Science.gov (United States)

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Neutron absorbed dose in a pacemaker CMOS

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2011-11-15

The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

CMOS cassette for digital upgrade of film-based mammography systems

Science.gov (United States)

Baysal, Mehmet A.; Toker, Emre

2006-03-01

While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

A MONOLITHIC PREAMPLIFIER-SHAPER FOR MEASUREMENT LOSS AND TRANSITION RADIATION.

Energy Technology Data Exchange (ETDEWEB)

KANDASAMY,A.

1999-11-08

A custom monolithic circuit has been developed for the Time Expansion Chamber (TEC) of the PHENIX detector at the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory (BNL). This detector identifies particles by sampling their ionization energy loss (dE/dx) over a 3 cm drift space and by detecting associated transition radiation (TR) photons. The requirement of being simultaneously sensitive to dE/dx and TR events requires a dual-gain system. We have developed a compact solution featuring an octal preamplifier/shaper (P/S) IC with a split gain stage. The circuit, fabricated in 1.2 {micro}m CMOS process, incorporates a trans-impedance preamplifier and a 70 ns unipolar CR-RC{sup 4} shaper with ion tail compensation and active DC offset cancellation. Digitally selectable gain, peaking time, and tail cancellation as well as channel-by-channel charge injection and disable can be configured in the system via a 3-wire interface. The 3.5 x 5 mm{sup 2} die is packaged in a fine-pitch 64-pin PQFP. Equivalent input noise is less than 1500 rms electrons at a power dissipation of 30 mW per channel. On a sample of 2400 chips, the DC offset was 2.3 {+-} 3 mV rms without trimming. A chamber-mounted TEC-PS Printed Circuit Board (PCB) houses four PIS chips, on-board calibration circuit, and 64 analog differential line drivers which transmit the shaped pulses to crate-mounted flash ADC's. 7 m apart An RS-422 link provides digital configuration downloading and read back, and supplies the calibration strobe. The 24.6 cm x 9.5 cm board dissipates 8.5 W.

A MONOLITHIC PREAMPLIFIER-SHAPER FOR MEASUREMENT LOSS AND TRANSITION RADIATION

International Nuclear Information System (INIS)

KANDASAMY, A.

1999-01-01

A custom monolithic circuit has been developed for the Time Expansion Chamber (TEC) of the PHENIX detector at the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory (BNL). This detector identifies particles by sampling their ionization energy loss (dE/dx) over a 3 cm drift space and by detecting associated transition radiation (TR) photons. The requirement of being simultaneously sensitive to dE/dx and TR events requires a dual-gain system. We have developed a compact solution featuring an octal preamplifier/shaper (P/S) IC with a split gain stage. The circuit, fabricated in 1.2 microm CMOS process, incorporates a trans-impedance preamplifier and a 70 ns unipolar CR-RC 4 shaper with ion tail compensation and active DC offset cancellation. Digitally selectable gain, peaking time, and tail cancellation as well as channel-by-channel charge injection and disable can be configured in the system via a 3-wire interface. The 3.5 x 5 mm 2 die is packaged in a fine-pitch 64-pin PQFP. Equivalent input noise is less than 1500 rms electrons at a power dissipation of 30 mW per channel. On a sample of 2400 chips, the DC offset was 2.3 ± 3 mV rms without trimming. A chamber-mounted TEC-PS Printed Circuit Board (PCB) houses four PIS chips, on-board calibration circuit, and 64 analog differential line drivers which transmit the shaped pulses to crate-mounted flash ADC's. 7 m apart An RS-422 link provides digital configuration downloading and read back, and supplies the calibration strobe. The 24.6 cm x 9.5 cm board dissipates 8.5 W

Nanometer CMOS ICs from basics to ASICs

CERN Document Server

J M Veendrick, Harry

2017-01-01

This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

Science.gov (United States)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

Monolitni katalizatori i reaktori: osnovne značajke, priprava i primjena (Monolith catalysts and reactors: preparation and applications

Directory of Open Access Journals (Sweden)

Tomašić, V.

2004-12-01

Full Text Available Monolithic (honeycomb catalysts are continuous unitary structures containing many narrow, parallel and usually straight channels (or passages. Catalytically active components are dispersed uniformly over the whole porous ceramic monolith structure (so-called incorporated monolithic catalysts or are in a layer of porous material that is deposited on the walls of channels in the monolith's structure (washcoated monolithic catalysts. The material of the main monolithic construction is not limited to ceramics but includes metals, as well. Monolithic catalysts are commonly used in gas phase catalytic processes, such as treatment of automotive exhaust gases, selective catalytic reduction of nitrogen oxides, catalytic removal of volatile organic compounds from industrial processes, etc. Monoliths continue to be the preferred support for environmental applications due to their high geometric surface area, different design options, low pressure drop, high temperature durability, mechanical strength, ease of orientation in a reactor and effectiveness as a support for a catalytic washcoat. As known, monolithic catalysts belong to the class of the structured catalysts and/or reactors (in some cases the distinction between "catalyst" and "reactor" has vanished. Structured catalysts can greatly intensify chemical processes, resulting in smaller, safer, cleaner and more energy efficient technologies. Monolith reactors can be considered as multifunctional reactors, in which chemical conversion is advantageously integrated with another unit operation, such as separation, heat exchange, a secondary reaction, etc. Finally, structured catalysts and/or reactors appear to be one of the most significant and promising developments in the field of heterogeneous catalysis and chemical engineering of the recent years. This paper gives a description of the background and perspectives for application and development of monolithic materials. Different methods and techniques

Test of the TRAPPISTe monolithic detector system

Science.gov (United States)

Soung Yee, L.; Álvarez, P.; Martin, E.; Cortina, E.; Ferrer, C.

2013-12-01

A monolithic pixel detector named TRAPPISTe-2 has been developed in Silicon-on-Insulator (SOI) technology. A p-n junction is implanted in the bottom handle wafer and connected to readout electronics integrated in the top active layer. The two parts are insulated from each other by a buried oxide layer resulting in a monolithic detector. Two small pixel matrices have been fabricated: one containing a 3-transistor readout and a second containing a charge sensitive amplifier readout. These two readout structures have been characterized and the pixel matrices were tested with an infrared laser source. The readout circuits are adversely affected by the backgate effect, which limits the voltage that can be applied to the metal back plane to deplete the sensor, thus narrowing the depletion width of the sensor. Despite the low depletion voltages, the integrated pixel matrices were able to respond to and track a laser source.

Monolithic Active Pixel Matrix with Binary Counters ASIC with nested wells

International Nuclear Information System (INIS)

Fahim, F; Deptuch, G; Holm, S; Shenai, A; Lipton, R

2013-01-01

Monolithic Active Matrix with Binary Counters (MAMBO) V ASIC has been designed for detecting and measuring low energy X-rays. A nested well structure with a buried n-well (BNW) and a deeper buried p-well (BPW) is used to electrically isolate the detector from the electronics. BNW acts as an AC ground to electrical signals and behaves as a shield. BPW allows for a homogenous electric field in the entire detector volume. The ASIC consists of a matrix of 50 × 52 pixels, each of 105x105μm 2 . Each pixel contains analog functionality accomplished by a charge preamplifier, CR-RC 2 shaper and a baseline restorer. It also contains a window comparator with Upper and Lower thresholds which can be individually trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit counter which is reconfigured as a shift register to serially output the data from the entire ASIC.

A CMOS 128-APS linear array integrated with a LVOF for highsensitivity and high-resolution micro-spectrophotometry

NARCIS (Netherlands)

Liu, C.; Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

2010-01-01

A linear array of 128 Active Pixel Sensors has been developed in standard CMOS technology and a Linear Variable Optical Filter (LVOF) is added using CMOS-compatible post-process, resulting in a single chip highly-integrated highresolution microspectrometer. The optical requirements imposed by the

A monolithic lipase reactor for biodiesel production by transesterification of triacylglycerides into fatty acid methyl esters

KAUST Repository

Urban, Jiří T.

2011-09-26

An enzymatic reactor with lipase immobilized on a monolithic polymer support has been prepared and used to catalyze the transesterification of triacylglycerides into the fatty acid methyl esters commonly used for biodiesel. A design of experiments procedure was used to optimize the monolithic reactor with variables including control of the surface polarity of the monolith via variations in the length of the hydrocarbon chain in alkyl methacrylate monomer, time of grafting of 1-vinyl-4,4-dimethylazlactone used to activate the monolith, and time used for the immobilization of porcine lipase. Optimal conditions involved the use of a poly(stearyl methacrylate-co-ethylene dimethacrylate) monolith, grafted first with vinylazlactone, then treated with lipase for 2h to carry out the immobilization of the enzyme. Best conditions for the transesterification of glyceryl tributyrate included a temperature of 37°C and a 10min residence time of the substrate in the bioreactor. The reactor did not lose its activity even after pumping through it a solution of substrate equaling 1,000 reactor volumes. This enzymatic reactor was also used for the transesterification of triacylglycerides from soybean oil to fatty acid methyl esters thus demonstrating the ability of the reactor to produce biodiesel. © 2011 Wiley Periodicals, Inc.

A monolithic lipase reactor for biodiesel production by transesterification of triacylglycerides into fatty acid methyl esters

KAUST Repository

Urban, Jiří T.; Švec, František; Frechet, Jean

2011-01-01

An enzymatic reactor with lipase immobilized on a monolithic polymer support has been prepared and used to catalyze the transesterification of triacylglycerides into the fatty acid methyl esters commonly used for biodiesel. A design of experiments procedure was used to optimize the monolithic reactor with variables including control of the surface polarity of the monolith via variations in the length of the hydrocarbon chain in alkyl methacrylate monomer, time of grafting of 1-vinyl-4,4-dimethylazlactone used to activate the monolith, and time used for the immobilization of porcine lipase. Optimal conditions involved the use of a poly(stearyl methacrylate-co-ethylene dimethacrylate) monolith, grafted first with vinylazlactone, then treated with lipase for 2h to carry out the immobilization of the enzyme. Best conditions for the transesterification of glyceryl tributyrate included a temperature of 37°C and a 10min residence time of the substrate in the bioreactor. The reactor did not lose its activity even after pumping through it a solution of substrate equaling 1,000 reactor volumes. This enzymatic reactor was also used for the transesterification of triacylglycerides from soybean oil to fatty acid methyl esters thus demonstrating the ability of the reactor to produce biodiesel. © 2011 Wiley Periodicals, Inc.

A monolithic lipase reactor for biodiesel production by transesterification of triacylglycerides into fatty acid methyl esters.

Science.gov (United States)

Urban, Jiri; Svec, Frantisek; Fréchet, Jean M J

2012-02-01

An enzymatic reactor with lipase immobilized on a monolithic polymer support has been prepared and used to catalyze the transesterification of triacylglycerides into the fatty acid methyl esters commonly used for biodiesel. A design of experiments procedure was used to optimize the monolithic reactor with variables including control of the surface polarity of the monolith via variations in the length of the hydrocarbon chain in alkyl methacrylate monomer, time of grafting of 1-vinyl-4,4-dimethylazlactone used to activate the monolith, and time used for the immobilization of porcine lipase. Optimal conditions involved the use of a poly(stearyl methacrylate-co-ethylene dimethacrylate) monolith, grafted first with vinylazlactone, then treated with lipase for 2 h to carry out the immobilization of the enzyme. Best conditions for the transesterification of glyceryl tributyrate included a temperature of 37°C and a 10 min residence time of the substrate in the bioreactor. The reactor did not lose its activity even after pumping through it a solution of substrate equaling 1,000 reactor volumes. This enzymatic reactor was also used for the transesterification of triacylglycerides from soybean oil to fatty acid methyl esters thus demonstrating the ability of the reactor to produce biodiesel. Copyright © 2011 Wiley Periodicals, Inc.

Preparation of polyhedral oligomeric silsesquioxane based imprinted monolith.

Science.gov (United States)

Li, Fang; Chen, Xiu-Xiu; Huang, Yan-Ping; Liu, Zhao-Sheng

2015-12-18

Polyhedral oligomeric silsesquioxane (POSS) was successfully applied, for the first time, to prepare imprinted monolithic column with high porosity and good permeability. The imprinted monolithic column was synthesized with a mixture of PSS-(1-Propylmethacrylate)-heptaisobutyl substituted (MA 0702), naproxon (template), 4-vinylpyridine, and ethylene glycol dimethacrylate, in ionic liquid 1-butyl-3-methylimidazolium tetrafluoroborate ([BMIM]BF4). The influence of synthesis parameters on the retention factor and imprinting effect, including the amount of MA 0702, the ratio of template to monomer, and the ratio of monomer to crosslinker, was investigated. The greatest imprinting factor on the imprinted monolithic column prepared with MA 0702 was 22, about 10 times higher than that prepared in absence of POSS. The comparisons between MIP monoliths synthesized with POSS and without POSS were made in terms of permeability, column efficiency, surface morphology and pore size distribution. In addition, thermodynamic and Van Deemter analysis were used to evaluate the POSS-based MIP monolith. Copyright © 2015 Elsevier B.V. All rights reserved.

Design and characterization of novel monolithic pixel sensors for the ALICE ITS upgrade

International Nuclear Information System (INIS)

Cavicchioli, C.; Chalmet, P.L.; Giubilato, P.; Hillemanns, H.; Junique, A.; Kugathasan, T.; Mager, M.; Marin Tobon, C.A.; Martinengo, P.; Mattiazzo, S.; Mugnier, H.; Musa, L.; Pantano, D.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Van Hoorne, J.W.; Yang, P.

2014-01-01

Within the R and D activities for the upgrade of the ALICE Inner Tracking System (ITS), Monolithic Active Pixel Sensors (MAPS) are being developed and studied, due to their lower material budget (∼0.3%X 0 in total for each inner layer) and higher granularity (∼20μm×20μm pixels) with respect to the present pixel detector. This paper presents the design and characterization results of the Explorer0 chip, manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a wafer with high-resistivity (ρ>1kΩcm) and 18 μm thick epitaxial layer. The chip is organized in two sub-matrices with different pixel pitches (20 μm and 30 μm), each of them containing several pixel designs. The collection electrode size and shape, as well as the distance between the electrode and the surrounding electronics, are varied; the chip also offers the possibility to decouple the charge integration time from the readout time, and to change the sensor bias. The charge collection properties of the different pixel variants implemented in Explorer0 have been studied using a 55 Fe X-ray source and 1–5 GeV/c electrons and positrons. The sensor capacitance has been estimated, and the effect of the sensor bias has also been examined in detail. A second version of the Explorer0 chip (called Explorer1) has been submitted for production in March 2013, together with a novel circuit with in-pixel discrimination and a sparsified readout. Results from these submissions are also presented

Design and characterization of novel monolithic pixel sensors for the ALICE ITS upgrade

Energy Technology Data Exchange (ETDEWEB)

Cavicchioli, C., E-mail: costanza.cavicchioli@cern.ch [CERN European Organization for Nuclear Research, CH-1211 Genève 23 (Switzerland); Chalmet, P.L. [MIND, Archamps Technopole, Saint-Julien-en-Genevois, Cedex 74166 (France); Giubilato, P. [Università and INFN, Padova (Italy); Hillemanns, H.; Junique, A.; Kugathasan, T.; Mager, M. [CERN European Organization for Nuclear Research, CH-1211 Genève 23 (Switzerland); Marin Tobon, C.A. [Valencia Polytechnic University, Valencia (Spain); Martinengo, P. [CERN European Organization for Nuclear Research, CH-1211 Genève 23 (Switzerland); Mattiazzo, S. [Università and INFN, Padova (Italy); Mugnier, H. [MIND, Archamps Technopole, Saint-Julien-en-Genevois, Cedex 74166 (France); Musa, L. [CERN European Organization for Nuclear Research, CH-1211 Genève 23 (Switzerland); Pantano, D. [Università and INFN, Padova (Italy); Rousset, J. [MIND, Archamps Technopole, Saint-Julien-en-Genevois, Cedex 74166 (France); Reidt, F. [CERN European Organization for Nuclear Research, CH-1211 Genève 23 (Switzerland); Physikalisches Institut, Ruprecht-Karls-Universitaet Heidelberg, Heidelberg (Germany); Riedler, P.; Snoeys, W. [CERN European Organization for Nuclear Research, CH-1211 Genève 23 (Switzerland); Van Hoorne, J.W. [CERN European Organization for Nuclear Research, CH-1211 Genève 23 (Switzerland); Technische Universitaet Wien, Vienna (Austria); Yang, P. [Central China Normal University CCNU, Wuhan (China)

2014-11-21

Within the R and D activities for the upgrade of the ALICE Inner Tracking System (ITS), Monolithic Active Pixel Sensors (MAPS) are being developed and studied, due to their lower material budget (∼0.3%X{sub 0} in total for each inner layer) and higher granularity (∼20μm×20μm pixels) with respect to the present pixel detector. This paper presents the design and characterization results of the Explorer0 chip, manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a wafer with high-resistivity (ρ>1kΩcm) and 18 μm thick epitaxial layer. The chip is organized in two sub-matrices with different pixel pitches (20 μm and 30 μm), each of them containing several pixel designs. The collection electrode size and shape, as well as the distance between the electrode and the surrounding electronics, are varied; the chip also offers the possibility to decouple the charge integration time from the readout time, and to change the sensor bias. The charge collection properties of the different pixel variants implemented in Explorer0 have been studied using a {sup 55}Fe X-ray source and 1–5 GeV/c electrons and positrons. The sensor capacitance has been estimated, and the effect of the sensor bias has also been examined in detail. A second version of the Explorer0 chip (called Explorer1) has been submitted for production in March 2013, together with a novel circuit with in-pixel discrimination and a sparsified readout. Results from these submissions are also presented.

Protective Skins for Aerogel Monoliths

Science.gov (United States)

Leventis, Nicholas; Johnston, James C.; Kuczmarski, Maria A.; Meador, Ann B.

2007-01-01

A method of imparting relatively hard protective outer skins to aerogel monoliths has been developed. Even more than aerogel beads, aerogel monoliths are attractive as thermal-insulation materials, but the commercial utilization of aerogel monoliths in thermal-insulation panels has been inhibited by their fragility and the consequent difficulty of handling them. Therefore, there is a need to afford sufficient protection to aerogel monoliths to facilitate handling, without compromising the attractive bulk properties (low density, high porosity, low thermal conductivity, high surface area, and low permittivity) of aerogel materials. The present method was devised to satisfy this need. The essence of the present method is to coat an aerogel monolith with an outer polymeric skin, by painting or spraying. Apparently, the reason spraying and painting were not attempted until now is that it is well known in the aerogel industry that aerogels collapse in contact with liquids. In the present method, one prevents such collapse through the proper choice of coating liquid and process conditions: In particular, one uses a viscous polymer precursor liquid and (a) carefully controls the amount of liquid applied and/or (b) causes the liquid to become cured to the desired hard polymeric layer rapidly enough that there is not sufficient time for the liquid to percolate into the aerogel bulk. The method has been demonstrated by use of isocyanates, which, upon exposure to atmospheric moisture, become cured to polyurethane/polyurea-type coats. The method has also been demonstrated by use of commercial epoxy resins. The method could also be implemented by use of a variety of other resins, including polyimide precursors (for forming high-temperature-resistant protective skins) or perfluorinated monomers (for forming coats that impart hydrophobicity and some increase in strength).

High-speed nonvolatile CMOS/MNOS RAM

International Nuclear Information System (INIS)

Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

1979-01-01

A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

III-Vs on Si for photonic applications-A monolithic approach

Energy Technology Data Exchange (ETDEWEB)

Wang, Zhechao, E-mail: Zhechao.Wang@intec.ugent.be [School of ICT, Royal Institute of Technology, Electrum 229, Isafjordsgatan 22, 164 40 Kista (Sweden); Junesand, Carl; Metaferia, Wondwosen; Hu, Chen; Wosinski, Lech [School of ICT, Royal Institute of Technology, Electrum 229, Isafjordsgatan 22, 164 40 Kista (Sweden); Lourdudoss, Sebastian, E-mail: slo@kth.se [School of ICT, Royal Institute of Technology, Electrum 229, Isafjordsgatan 22, 164 40 Kista (Sweden)

2012-10-01

Highlights: Black-Right-Pointing-Pointer Monolithic evanescently coupled silicon laser (MECSL) structure treated. Black-Right-Pointing-Pointer Optical mode profiles and thermal resistivity of MECSL optimized by simulation. Black-Right-Pointing-Pointer MECSL through epitaxial lateral overgrowth (ELOG) of InP on Si exemplified. Black-Right-Pointing-Pointer Passive waveguide in MECSL also acts as the defect filtering mask in ELOG. Black-Right-Pointing-Pointer Growth of dislocation free thin InP layer on Si by ELOG for MECSL demonstrated. - Abstract: Epitaxial lateral overgrowth (ELOG) technology is demonstrated as a viable technology to realize monolithic integration of III-Vs on silicon. As an alternative to wafer-to-wafer bonding and die-to-wafer bonding, ELOG provides an attractive platform for fabricating discrete and integrated components in high volume at low cost. A possible route for monolithic integration of III-Vs on silicon for silicon photonics is exemplified by the case of a monolithic evanescently coupled silicon laser (MECSL) by combining InP on Si/SiO{sub 2} through ELOG. Passive waveguide in MECSL also acts as the defect filtering mask in ELOG. The structural design of a monolithic evanescently coupled silicon laser (MECSL) and its thermal resistivity are established through simulations. Material studies to realize the above laser through ELOG are undertaken by studying appropriate ELOG pattern designs to achieve InP on narrow regions of silicon. We show that defect-free InP can be obtained on SiO{sub 2} as the first step which paves the way for realizing active photonic devices on Si/SiO{sub 2} waveguides, e.g. an MECSL.

An investigation into the use of CMOS active pixel technology in image-guided radiotherapy

International Nuclear Information System (INIS)

Osmond, J P F; Holland, A D; Harris, E J; Ott, R J; Evans, P M; Clark, A T

2008-01-01

The increased intelligence, read-out speed, radiation hardness and potential large size of CMOS active pixel sensors (APS) gives them a potential advantage over systems currently used for verification of complex treatments such as IMRT and the tracking of moving tumours. The aim of this work is to investigate the feasibility of using an APS-based system to image the megavoltage treatment beam produced by a linear accelerator (Linac), and to demonstrate the logic which may ultimately be incorporated into future sensor and FPGA design to evaluate treatment and track motion. A CMOS APS was developed by the MI 3 consortium and incorporated into a megavoltage imaging system using the standard lens and mirror configuration employed in camera-based EPIDs. The ability to resolve anatomical structure was evaluated using an Alderson RANDO head phantom, resolution evaluated using a quality control (QC3) phantom and contrast using an in-house developed phantom. A complex intensity-modulated radiotherapy (IMRT) treatment was imaged and two algorithms were used to determine the field-area and delivered dose, and the position of multi-leaf collimator (MLC) leaves off-line. Results were compared with prediction from the prescription and found to agree within a single image frame time for dose delivery and 0.02-0.03 cm for the position of collimator leaves. Such a system therefore shows potential as the basis for an on-line verification system capable of treatment verification and monitoring patient motion

A Differential Monolithically Integrated Inductive Linear Displacement Measurement Microsystem

Directory of Open Access Journals (Sweden)

Matija Podhraški

2016-03-01

Full Text Available An inductive linear displacement measurement microsystem realized as a monolithic Application-Specific Integrated Circuit (ASIC is presented. The system comprises integrated microtransformers as sensing elements, and analog front-end electronics for signal processing and demodulation, both jointly fabricated in a conventional commercially available four-metal 350-nm CMOS process. The key novelty of the presented system is its full integration, straightforward fabrication, and ease of application, requiring no external light or magnetic field source. Such systems therefore have the possibility of substituting certain conventional position encoder types. The microtransformers are excited by an AC signal in MHz range. The displacement information is modulated into the AC signal by a metal grating scale placed over the microsystem, employing a differential measurement principle. Homodyne mixing is used for the demodulation of the scale displacement information, returned by the ASIC as a DC signal in two quadrature channels allowing the determination of linear position of the target scale. The microsystem design, simulations, and characterization are presented. Various system operating conditions such as frequency, phase, target scale material and distance have been experimentally evaluated. The best results have been achieved at 4 MHz, demonstrating a linear resolution of 20 µm with steel and copper scale, having respective sensitivities of 0.71 V/mm and 0.99 V/mm.

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2014-01-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

Study of plasma charging-induced white pixel defect increase in CMOS active pixel sensor

International Nuclear Information System (INIS)

Tokashiki, Ken; Bai, KeunHee; Baek, KyeHyun; Kim, Yongjin; Min, Gyungjin; Kang, Changjin; Cho, Hanku; Moon, Jootae

2007-01-01

Plasma process-induced 'white pixel defect' (WPD) of CMOS active pixel sensor (APS) is studied for Si3N4 spacer etch back process by using a magnetically enhanced reactive ion etching (MERIE) system. WPD preferably takes place at the wafer edge region when the magnetized plasma is applied to Si3N4 etch. Plasma charging analysis reveals that the plasma charge-up characteristic is well matching the edge-intensive WPD generation, rather than the UV radiation. Plasma charging on APS transfer gate might lead to a gate leakage, which could play a role in generation of signal noise or WPD. In this article the WPD generation mechanism will be discussed from plasma charging point of view

Decal electronics for printed high performance cmos electronic systems

KAUST Repository

Hussain, Muhammad Mustafa

2017-11-23

High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

Batch Processing of CMOS Compatible Feedthroughs

DEFF Research Database (Denmark)

Rasmussen, F.E.; Heschel, M.; Hansen, Ole

2003-01-01

. The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...... of 2.5 pF. (C) 2003 Elsevier Science B.V. All rights reserved....

Integrated X-ray and charged particle active pixel CMOS sensor arrays using an epitaxial silicon sensitive region

International Nuclear Information System (INIS)

Kleinfelder, Stuart; Bichsel, Hans; Bieser, Fred; Matis, Howard S.; Rai, Gulshan; Retiere, Fabrice; Weiman, Howard; Yamamoto, Eugene

2002-01-01

Integrated CMOS Active Pixel Sensor (APS) arrays have been fabricated and tested using X-ray and electron sources. The 128 by 128 pixel arrays, designed in a standard 0.25 micron process, use a ∼10 micron epitaxial silicon layer as a deep detection region. The epitaxial layer has a much greater thickness than the surface features used by standard CMOS APS, leading to stronger signals and potentially better signal-to-noise ratio (SNR). On the other hand, minority carriers confined within the epitaxial region may diffuse to neighboring pixels, blur images and reduce peak signal intensity. But for low-rate, sparse-event images, centroid analysis of this diffusion may be used to increase position resolution. Careful trade-offs involving pixel size and sense-node area verses capacitance must be made to optimize overall performance. The prototype sensor arrays, therefore, include a range of different pixel designs, including different APS circuits and a range of different epitaxial layer contact structures. The fabricated arrays were tested with 1.5 GeV electrons and Fe-55 X-ray sources, yielding a measured noise of 13 electrons RMS and an SNR for single Fe-55 X-rays of greater than 38

Technology CAD for germanium CMOS circuit

Energy Technology Data Exchange (ETDEWEB)

Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

2006-12-15

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

Technology CAD for germanium CMOS circuit

International Nuclear Information System (INIS)

Saha, A.R.; Maiti, C.K.

2006-01-01

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

Dopamine-imprinted monolithic column for capillary electrochromatography.

Science.gov (United States)

Aşır, Süleyman; Sarı, Duygu; Derazshamshir, Ali; Yılmaz, Fatma; Şarkaya, Koray; Denizli, Adil

2017-11-01

A dopamine-imprinted monolithic column was prepared and used in capillary electrochromatography as stationary phase for the first time. Dopamine was selectively separated from aqueous solution containing the competitor molecule norepinephrine, which is similar in size and shape to the template molecule. Morphology of the dopamine-imprinted column was observed by scanning electron microscopy. The influence of the organic solvent content of mobile phase, applied pressure and pH of the mobile phase on the recognition of dopamine by the imprinted monolithic column has been evaluated, and the imprinting effect in the dopamine-imprinted monolithic polymer was verified. Developed dopamine-imprinted monolithic column resulted in excellent separation of dopamine from structurally related competitor molecule, norepinephrine. Separation was achieved in a short period of 10 min, with the electrophoretic mobility of 5.81 × 10 -5  m 2 V -1 s -1 at pH 5.0 and 500 mbar pressure. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Resistor Extends Life Of Battery In Clocked CMOS Circuit

Science.gov (United States)

Wells, George H., Jr.

1991-01-01

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Carbon Nanotube Integration with a CMOS Process

Science.gov (United States)

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

Preparation of epoxy-based macroporous monolithic columns for the fast and efficient immunofiltration of Staphylococcus aureus.

Science.gov (United States)

Ott, Sonja; Niessner, Reinhard; Seidel, Michael

2011-08-01

Macroporous epoxy-based monolithic columns were used for immunofiltration of bacteria. The prepared monolithic polymer support is hydrophilic and has large pore sizes of 21 μm without mesopores. A surface chemistry usually applied for immobilization of antibodies on glass slides is successfully transferred to monolithic columns. Step-by-step, the surface of the epoxy-based monolith is hydrolyzed, silanized, coated with poly(ethylene glycol diamine) and activated with the homobifunctional crosslinker di(N-succinimidyl)carbonate for immobilization of antibodies on the monolithic columns. The functionalization steps are characterized to ensure the coating of each monolayer. The prepared antibody-immobilized monolithic column is optimized for immunofiltration to enrich Staphylococcus aureus as an important food contaminant. Different kinds of geometries of monolithic columns, flow rates and elution buffers are tested with the goal to get high recoveries in the shortest enrichment time as possible. An effective capture of S. aureus was achieved at a flow rate of 7.0 mL/min with low backpressures of 20.1±5.4 mbar enabling a volumetric enrichment of 1000 within 145 min. The bacteria were quantified by flow cytometry using a double-labeling approach. After immunofiltration the sensitivity was significantly increased and a detection limit of the total system of 42 S. aureus/mL was reached. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Single photon detection and localization accuracy with an ebCMOS camera

Energy Technology Data Exchange (ETDEWEB)

Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

2015-07-01

The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

CMOS Cell Sensors for Point-of-Care Diagnostics

Science.gov (United States)

Adiguzel, Yekbun; Kulah, Haluk

2012-01-01

The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

CERN Document Server

Ghafar-Zadeh, Ebrahim

2010-01-01

The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

TCAD simulations of High-Voltage-CMOS Pixel structures for the CLIC vertex detector

CERN Document Server

Buckland, Matthew Daniel

2016-01-01

The requirements for precision physics and the experimental conditions at CLIC result in stringent constraints for the vertex detector. Capacitively coupled active pixel sensors with 25 μm pitch implemented in a commercial 180 nm High-Voltage CMOS (HV-CMOS) process are currently under study as a candidate technology for the CLIC vertex detector. Laboratory calibration measurements and beam tests with prototypes are complemented by detailed TCAD and electronic circuit simulations, aiming for a comprehensive understanding of the signal formation in the HV-CMOS sensors and subsequent readout stages. In this note 2D and 3D TCAD simulation results of the prototype sensor, the Capacitively Coupled Pixel Detector version three (CCPDv3), will be presented. These include the electric field distribution, leakage current, well capacitance, transient response to minimum ionising particles and charge-collection.

CMOS optimization for radiation hardness

International Nuclear Information System (INIS)

Derbenwick, G.F.; Fossum, J.G.

1975-01-01

Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

Biomimetic small peptide functionalized affinity monoliths for monoclonal antibody purification.

Science.gov (United States)

Wang, Xiangyu; Xia, Donghai; Han, Hai; Peng, Kun; Zhu, Peijie; Crommen, Jacques; Wang, Qiqin; Jiang, Zhengjin

2018-08-09

The rapid development of monoclonal antibodies (mAbs) in therapeutic and diagnostic applications has necessitated the advancement of mAbs purification technologies. In this study, a biomimetic small peptide ligand 3,5-di-tert-butyl-4-hydroxybenzoic acid-Arg-Arg-Gly (DAAG) functionalized monolith was fabricated through a metal ion chelation-based multi-step approach. The resulting monolith showed good chromatographic performance. Compared with the Ni 2+ based IMAC monolith, the DAAG functionalized monolith exhibited not only excellent specificity but also higher dynamic binding capacity (DBC). The 10% DBC and 50% DBC for hIgG reached as high values as 26.0 and 34.6 mg/mL, respectively, at a ligand density of 8.8 μmol/mL, due to the high porosity and accessibility of the monolithic matrix. Moreover, the stability of the DAAG functionalized monolith in successive breakthrough experiments indicates that it has a promising potential for long-term use in mAbs purification. Finally, the DAAG functionalized monolith was successfully applied to the purification of trastuzumab or human immunoglobulin G (hIgG) from biological samples. Copyright © 2018 Elsevier B.V. All rights reserved.

The effect of CO2 activation temperature on the physical and electrochemical properties of activated carbon monolith from banana stem waste

Science.gov (United States)

Taer, E.; Susanti, Y.; Awitdrus, Sugianto, Taslim, R.; Setiadi, R. N.; Bahri, S.; Agustino, Dewi, P.; Kurniasih, B.

2018-02-01

The effect of CO2 activation on the synthesis of activated carbon monolith from banana stem waste has been studied. Physical characteristics such as density, degree of crystallinity, surface morphology and elemental content has been analyzed, supporting the finding of an excellent electrochemical properties for the supercapacitor. The synthesis of activated carbon electrode began with pre-carbonization process at temperature of 250°C for 2.5 h. Then the process was continued by chemical activation using KOH as activating agent with a concentration of 0.4 M. The pellets were formed with 8 ton hydrolic pressure. All the samples were carbonized at a temperature of 600°C, followed by physical activation using CO2 gas at a various temperatures ranging from 800°C, 850°C, 900°C and 950°C for 2 h. The carbon content was increased with increasing temperature and the optimum temperature was 900°C. The specific capacitance depends on the activation temperature with the highest specific capacitance of 104.2 F/g at the activation temperature of 900°C.

Three-dimensional cascaded system analysis of a 50 µm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

Science.gov (United States)

Zhao, C; Vassiljev, N; Konstantinidis, A C; Speller, R D; Kanicki, J

2017-03-07

High-resolution, low-noise x-ray detectors based on the complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been developed and proposed for digital breast tomosynthesis (DBT). In this study, we evaluated the three-dimensional (3D) imaging performance of a 50 µm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). The two-dimensional (2D) angle-dependent modulation transfer function (MTF), normalized noise power spectrum (NNPS), and detective quantum efficiency (DQE) were experimentally characterized and modeled using the cascaded system analysis at oblique incident angles up to 30°. The cascaded system model was extended to the 3D spatial frequency space in combination with the filtered back-projection (FBP) reconstruction method to calculate the 3D and in-plane MTF, NNPS and DQE parameters. The results demonstrate that the beam obliquity blurs the 2D MTF and DQE in the high spatial frequency range. However, this effect can be eliminated after FBP image reconstruction. In addition, impacts of the image acquisition geometry and detector parameters were evaluated using the 3D cascaded system analysis for DBT. The result shows that a wider projection angle range (e.g.  ±30°) improves the low spatial frequency (below 5 mm -1 ) performance of the CMOS APS detector. In addition, to maintain a high spatial resolution for DBT, a focal spot size of smaller than 0.3 mm should be used. Theoretical analysis suggests that a pixelated scintillator in combination with the 50 µm pixel pitch CMOS APS detector could further improve the 3D image resolution. Finally, the 3D imaging performance of the CMOS APS and an indirect amorphous silicon (a-Si:H) thin-film transistor (TFT) passive pixel sensor (PPS) detector was simulated and compared.

TiO2 on magnesium silicate monolith: effects of different preparation techniques on the photocatalytic oxidation of chlorinated hydrocarbons

International Nuclear Information System (INIS)

Cardona, Ana I.; Candal, Roberto; Sanchez, Benigno; Avila, Pedro; Rebollar, Moises

2004-01-01

In this article, the comparative results of the photocatalytic oxidation of trichloroethylene (TCE) alone and a mixture of chlorinated hydrocarbons (trichloroethylene, perchloroethylene and chloroform) in gas phase, obtained with three different monolithic catalysts in a flat reactor frontally illuminated with a Xenon lamp are presented. The three catalysts incorporate titanium dioxide (TiO 2 ) as active phase on a magnesium silicate support, by means of different procedures: (i) incorporation of commercial TiO 2 powder into the silicate matrix ('massic monolith'); (ii) sol-gel coating of the silicate support; (iii) impregnation with a commercial TiO 2 aqueous suspension of the same silicate support. In the first case, the massic monolith was made from a 50:50 w/w mixture of magnesium silicate and 'Titafrance G5' TiO 2 powder. In the second case, a magnesium silicate monolith was coated with several layers of an aqueous TiO 2 sol prepared from hydrolysis and condensation of titanium tetra-isopropoxide (Ti(OC 3 H 7 ) 4 ) in excess of acidified water (acid catalysis). The third catalyst was prepared by impregnating the same silicate support with several layers of 'Titafrance G5' TiO 2 powder water suspension. All the catalysts were thermal treated under comparable conditions in order to fix the TiO 2 active phase to the silicate support. Although the performance of the massic monolith was better than the sol-gel monolith, the latter is of great interest because this technique allows the chemical composition of the active films to be easily modified

The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

International Nuclear Information System (INIS)

Traversi, G.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Ratti, L.; Re, V.

2013-01-01

This work presents the characterization of Deep N-well (DNW) active pixel sensors fabricated in a vertically integrated technology. The DNW approach takes advantage of the triple well structure to lay out a sensor with relatively large charge collecting area (as compared to standard three transistor MAPS), while the readout is performed by a classical signal processing chain for capacitive detectors. This new 3D design relies upon stacking two homogeneous tiers fabricated in a 130 nm CMOS process where the top tier is thinned down to about 12μm to expose through silicon vias (TSV), therefore making connection to the buried circuits possible. This technology has been used to design a fine pitch 3D CMOS sensor with sparsification capabilities, in view of vertexing applications to the International Linear Collider (ILC) experiments. Results from the characterization of different kind of test structures, including single pixels, 3×3 and 8×8 matrices, are presented

Self-calibrated humidity sensor in CMOS without post-processing.

Science.gov (United States)

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2012-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Self-Calibrated Humidity Sensor in CMOS without Post-Processing

OpenAIRE

Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

2011-01-01

A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

Aspartic acid incorporated monolithic columns for affinity glycoprotein purification.

Science.gov (United States)

Armutcu, Canan; Bereli, Nilay; Bayram, Engin; Uzun, Lokman; Say, Rıdvan; Denizli, Adil

2014-02-01

Novel aspartic acid incorporated monolithic columns were prepared to efficiently affinity purify immunoglobulin G (IgG) from human plasma. The monolithic columns were synthesised in a stainless steel HPLC column (20 cm × 5 mm id) by in situ bulk polymerisation of N-methacryloyl-L-aspartic acid (MAAsp), a polymerisable derivative of L-aspartic acid, and 2-hydroxyethyl methacrylate (HEMA). Monolithic columns [poly(2-hydroxyethyl methacrylate-N-methacryloyl-L-aspartic acid) (PHEMAsp)] were characterised by swelling studies, Fourier transform infrared spectroscopy (FTIR) and scanning electron microscopy (SEM). The monolithic columns were used for IgG adsorption/desorption from aqueous solutions and human plasma. The IgG adsorption depended on the buffer type, and the maximum IgG adsorption from aqueous solution in phosphate buffer was 0.085 mg/g at pH 6.0. The monolithic columns allowed for one-step IgG purification with a negligible capacity decrease after ten adsorption-desorption cycles. Copyright © 2013 Elsevier B.V. All rights reserved.

Fire resistance of prefabricated monolithic slab

Directory of Open Access Journals (Sweden)

Gravit Marina

2017-01-01

Full Text Available A prefabricated monolithic slab (PMS has a number of valuable advantages, they allow to significantly decrease the weight of construction keeping the necessary structural-load capacity, to speed up and cheapen work conduction, to increase the heat isolating properties of an enclosure structure [1]. In order to create a design method of prefabricated monolithic slab fire-resistance, it's necessary to perform a series of PMS testing, one of which is being described in this article. Subjected to the test is a fragment of prefabricated monolithic slab with polystyrene concrete inserts along the beams with bent metal profile 250 mm thick, with a 2.7 m span loaded with evenly spread load equal to 600 kg/m2. After 3 hour testing for fire-resistance [2] no signs of construction ultimate behavior were detected.

Radiation-hardened bulk CMOS technology

International Nuclear Information System (INIS)

Dawes, W.R. Jr.; Habing, D.H.

1979-01-01

The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

CMOS/SOS processing

Science.gov (United States)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Development of high-throughput analysis system using highly-functional organic polymer monoliths

International Nuclear Information System (INIS)

Umemura, Tomonari; Kojima, Norihisa; Ueki, Yuji

2008-01-01

The growing demand for high-throughput analysis in the current competitive life sciences and industries has promoted the development of high-speed HPLC techniques and tools. As one of such tools, monolithic columns have attracted increasing attention and interest in the last decade due to the low flow-resistance and excellent mass transfer, allowing for rapid separations and reactions at high flow rates with minimal loss of column efficiency. Monolithic materials are classified into two main groups: silica- and organic polymer-based monoliths, each with their own advantages and disadvantages. Organic polymer monoliths have several distinct advantages in life-science research, including wide pH stability, less irreversible adsorption, facile preparation and modification. Thus, we have so far tried to develop organic polymer monoliths for various chemical operations, such as separation, extraction, preconcentration, and reaction. In the present paper, recent progress in the development of organic polymer monoliths is discussed. Especially, the procedure for the preparation of methacrylate-based monoliths with various functional groups is described, where the influence of different compositional and processing parameters on the monolithic structure is also addressed. Furthermore, the performance of the produced monoliths is demonstrated through the results for (1) rapid separations of alklybenzenes at high flow rates, (2) flow-through enzymatic digestion of cytochrome c on a trypsin-immobilized monolithic column, and (3) separation of the tryptic digest on a reversed-phase monolithic column. The flexibility and versatility of organic polymer monoliths will be beneficial for further enhancing analytical performance, and will open the way for new applications and opportunities both in scientific and industrial research. (author)

Improved Space Object Orbit Determination Using CMOS Detectors

Science.gov (United States)

Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

2014-09-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

A poly(vinyl alcohol)/sodium alginate blend monolith with nanoscale porous structure.

Science.gov (United States)

Sun, Xiaoxia; Uyama, Hiroshi

2013-10-04

A stimuli-responsive poly(vinyl alcohol) (PVA)/sodium alginate (SA) blend monolith with nanoscale porous (mesoporous) structure is successfully fabricated by thermally impacted non-solvent induced phase separation (TINIPS) method. The PVA/SA blend monolith with different SA contents is conveniently fabricated in an aqueous methanol without any templates. The solvent suitable for the fabrication of the present blend monolith by TINIPS is different with that of the PVA monolith. The nanostructural control of the blend monolith is readily achieved by optimizing the fabrication conditions. Brunauer Emmett Teller measurement shows that the obtained blend monolith has a large surface area. Pore size distribution plot for the blend monolith obtained by the non-local density functional theory method reveals the existence of the nanoscale porous structure. Fourier transform infrared analysis reveals the strong interactions between PVA and SA. The pH-responsive property of the blend monolith is investigated on the basis of swelling ratio in different pH solutions. The present blend monolith of biocompatible and biodegradable PVA and SA with nanoscale porous structure has large potential for applications in biomedical and environmental fields.

Simulations of depleted CMOS sensors for high-radiation environments

CERN Document Server

Liu, J.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Degerli, Y.; Godiot-Basolo, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Moustakas, K.; Pangaud, P.; Rozanov, A.; Rymaszewski, P.; Schwemling, P.; Wang, M.; Wang, T.; Wermes, N.; Zhang, L.

2017-01-01

After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications

KAUST Repository

Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

2018-01-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

CMOS Enabled Microfluidic Systems for Healthcare Based Applications

KAUST Repository

Khan, Sherjeel M.

2018-02-27

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

Prevention of CMOS latch-up by gold doping

International Nuclear Information System (INIS)

Dawes, W.R.; Derbenwick, G.F.

1976-01-01

CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

High performance flexible CMOS SOI FinFETs

KAUST Repository

Fahad, Hossain M.

2014-06-01

We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

Toward CMOS image sensor based glucose monitoring.

Science.gov (United States)

Devadhasan, Jasmine Pramila; Kim, Sanghyo

2012-09-07

Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

Analysis of test beam data of ALPIDE, the Monolithic Active Pixel Sensor (MAPS) for the ALICE ITS upgrade

CERN Document Server

Lazareva, Tatiana

2017-01-01

The ALICE experiment has scheduled a major upgrade of its experimen- tal apparatus for the Long Shutdown 2 of LHC in 2019-2020. Within this enterprise, CERN is strongly involved in the development of a novel Inner Tracking System (ITS). The ITS will be based on Monolithic Active Pixel Sensors (MAPS), a cutting-edge technology that will allow to improve the detector performance signicantly. The nal sensor, called ALPIDE, is in production since December 2016. This project is focused on the characterization of irradiated ALPIDE sensors.

Preparation and characterization of Au/CeO{sub 2}-Al{sub 2}O{sub 3} monoliths

Energy Technology Data Exchange (ETDEWEB)

Gawel, Bartlomiej; Lambrechts, Kalle [Ugelstad Laboratory, Department of Chemical Engineering, Norwegian University of Science and Technology (NTNU), N-7491 Trondheim (Norway); Oye, Gisle, E-mail: gisle.oye@chemeng.ntnu.no [Ugelstad Laboratory, Department of Chemical Engineering, Norwegian University of Science and Technology (NTNU), N-7491 Trondheim (Norway)

2012-05-15

Highlights: Black-Right-Pointing-Pointer A facile method for preparing Au/CeO{sub 2}-Al{sub 2}O{sub 3} monoliths with hierarchical porosity. Black-Right-Pointing-Pointer Continuous-flow testing of the monoliths in liquid-phase oxidation of glucose. Black-Right-Pointing-Pointer Increased catalytic activity in the presence of cerium oxide (stirred-batch tests). - Abstract: Porous CeO{sub 2}-Al{sub 2}O{sub 3} monoliths with hierarchical pore structure were prepared by mixing boehmite particles with solutions containing different amounts of cerium chloride and aluminum nitrate. The monoliths were functionalized with gold nanoparticles using the incipient wetness method. The resulting materials were characterized by X-ray diffraction, nitrogen sorption, mercury porosimetry, UV-vis spectroscopy and transmission electron microscopy. The catalysts were tested in liquid phase glucose oxidation, comparing continuously stirred batch reactor and continuous-flow fix-bed reactor setups.

45% power saving in a 0.25μm BiCMOS 10Gb/s 50Ω-terminated packaged active-load laser driver

DEFF Research Database (Denmark)

Ayranci, E.; Christensen, K.; Andreani, Pietro

2007-01-01

A 0.25μm BiCMOS laser driver based on active loads allows operation at 10Gb/s while drawing 5mA from a 1.8V supply. The design guarantees the correct matching of the driver outputs without the use of physical 50Ω load resistors. This enables a theoretical current consumption reduction of 50% (45...

Media Presentation Synchronisation for Non-monolithic Rendering Architectures

NARCIS (Netherlands)

I. Vaishnavi (Ishan); D.C.A. Bulterman (Dick); P.S. Cesar Garcia (Pablo Santiago); B. Gao (Bo)

2007-01-01

htmlabstractNon-monolithic renderers are physically distributed media playback engines. Non-monolithic renderers may use a number of different underlying network connection types to transmit media items belonging to a presentation. There is therefore a need for a media based and inter-network- type

AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY

Directory of Open Access Journals (Sweden)

N. B. ROMLI

2015-03-01

Full Text Available Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power. The exponential growth of both static and dynamic power dissipations in any CMOS process technology option has increased the cost and efficiency of the system. Technology options are used for the execution specifications and usually it depends on the optimisation and the performance constraints over the chip. This article reviews the relevant researches of the source or power dissipation, the mechanism to reduce the dynamic power dissipation as well as static power dissipation and an overview of various circuit techniques to control them. Important device parameters including voltage threshold and switching capacitance impact to the circuit performance in lowering both dynamic and static power dissipation are presented. The demand for the reduction of power dissipation in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on power dissipation and control techniques.

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

Science.gov (United States)

Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

2013-03-01

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

Design of CMOS imaging system based on FPGA

Science.gov (United States)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

Directory of Open Access Journals (Sweden)

Haitao Li

2016-12-01

Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

Fabrication and characterisation of gold nano-particle modified polymer monoliths for flow-through catalytic reactions and their application in the reduction of hexacyanoferrate

International Nuclear Information System (INIS)

Floris, Patrick; Twamley, Brendan; Nesterenko, Pavel N.; Paull, Brett; Connolly, Damian

2014-01-01

Polymer monoliths in capillary (100 μm i.d.) and polypropylene pipette tip formats (vol: 20 μL) were modified with gold nano-particles (AuNP) and subsequently used for flow-through catalytic reactions. Specifically, methacrylate monoliths were modified with amine-reactive monomers using a two-step photografting method and then reacted with ethylenediamine to provide amine attachment sites for the subsequent immobilisation of 4 nm, 7 nm or 16 nm AuNP. This was achieved by flushing colloidal suspensions of gold nano-particles through each aminated polymer monolith which resulted in a multi-point covalent attachment of gold via the lone pair of electrons on the nitrogen of the free amine groups. Field emission scanning electron microscopy and scanning capacitively coupled conductivity detection was used to characterise the surface coverage of AuNP on the monoliths. The catalytic activity of AuNP immobilised on the polymer monoliths in both formats was then demonstrated using the reduction of Fe(III) to Fe(II) by sodium borohydride as a model reaction by monitoring the reduction in absorbance of the hexacyanoferrate (III) complex at 420 nm. Catalytic activity was significantly enhanced on monoliths modified with smaller AuNP with almost complete reduction (95 %) observed when using monoliths agglomerated with 7 nm AuNPs. (author)

Edge chipping and flexural resistance of monolithic ceramics☆

Science.gov (United States)

Zhang, Yu; Lee, James J.-W.; Srikanth, Ramanathan; Lawn, Brian R.

2014-01-01

Objective Test the hypothesis that monolithic ceramics can be developed with combined esthetics and superior fracture resistance to circumvent processing and performance drawbacks of traditional all-ceramic crowns and fixed-dental-prostheses consisting of a hard and strong core with an esthetic porcelain veneer. Specifically, to demonstrate that monolithic prostheses can be produced with a much reduced susceptibility to fracture. Methods Protocols were applied for quantifying resistance to chipping as well as resistance to flexural failure in two classes of dental ceramic, microstructurally-modified zirconias and lithium disilicate glass–ceramics. A sharp indenter was used to induce chips near the edges of flat-layer specimens, and the results compared with predictions from a critical load equation. The critical loads required to produce cementation surface failure in monolithic specimens bonded to dentin were computed from established flexural strength relations and the predictions validated with experimental data. Results Monolithic zirconias have superior chipping and flexural fracture resistance relative to their veneered counterparts. While they have superior esthetics, glass–ceramics exhibit lower strength but higher chip fracture resistance relative to porcelain-veneered zirconias. Significance The study suggests a promising future for new and improved monolithic ceramic restorations, with combined durability and acceptable esthetics. PMID:24139756

Safety characteristics of the monolithic CFC divertor

International Nuclear Information System (INIS)

Zucchetti, M.; Merola, M.; Matera, R.

1994-01-01

The main distinguishing feature of the monolithic CFC divertor is the use of a single material, a carbon fibre reinforced carbon, for the protective armour, the heat sink and the cooling channels. This removes joint interface problems which are one of the most important concerns related to the reference solutions of the ITER CDA divertor. An activation analysis of the different coolant options for this concept is presented. It turns out that neither short-term nor long-term activation are a concern for any coolants investigated. Therefore the proposed concept proves to be attractive from a safety stand-point also. ((orig.))

Safety characteristics of the monolithic CFC divertor

Science.gov (United States)

Zucchetti, M.; Merola, M.; Matera, R.

1994-09-01

The main distinguishing feature of the monolithic CFC divertor is the use of a single material, a carbon fibre reinforced carbon, for the protective armour, the heat sink and the cooling channels. This removes joint interface problems which are one of the most important concerns related to the reference solutions of the ITER CDA divertor. An activation analysis of the different coolant options for this concept is presented. It turns out that neither short-term nor long-term activation are a concern for any coolants investigated. Therefore the proposed concept proves to be attractive from a safety stand-point also.

CMOS-compatible spintronic devices: a review

Science.gov (United States)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

SEU-hardened design for shift register in CMOS APS

International Nuclear Information System (INIS)

Meng Liya; Liu Zedong; Hu Dajiang; Wang Qingxiang

2012-01-01

The inverter-based quasi-static shift register in CMOS APS, which is used in ionizing radiation environment, is susceptible to single event upset (SEU), thus affecting the CMOS active pixel sensor (APS) working. The analysis of the SEU for inverter-based quasi-static shift register concludes that the most sensitive node to single event transient (SET) exists in the input of inverter, and the threshold voltage and capacitance of input node of inverter determine the capability of anti-SEU. A new method was proposed, which replaced the inverter with Schmitt trigger in shift register. Because there is a hysteresis on voltage transfer characteristic of Schmitt trigger, there is high flip threshold, thus better capability of anti-SEU can be achieved. Simulation results show that the anti-SEU capability of Schmitt trigger is 10 times more than that of inverter. (authors)

MEMS based monolithic Phased array using 3-bit Switched-line Phase Shifter

Directory of Open Access Journals (Sweden)

A. Karmakr

2017-10-01

Full Text Available This article details the design of an electronically scanning phased array antenna with proposed fabrication process steps. Structure is based upon RF micro-electromechanical system (MEMS technology. Capacitive type shunt switches have been implemented here to cater high frequency operation. The architecture, which is deigned at 30 GHz, consists of 3-bit (11.25º, 22.5º and 45º integrated Switched-line phase shifter and a linearly polarized microstrip patch antenna. Detailed design tricks of the Ka-band phase shifter is outlined here. The whole design is targeted for future monolithic integration. So, the substrate of choice is High Resistive Silicon (ρ > 8kΩ-cm, tan δ =0.01 and ϵr =11.8. The overall circuit occupies an cross-sectional area of 20 × 5 mm2. The simulated results show that the phase shifter can provide nearly 11.25º/22.5º/45º phase shifts and their combinations at the expense of 1dB average insertion loss at 30 GHz for eight combinations. Practical fabrication process flow using surface micromachining is proposed here. Critical dimensions of the phased array structure is governed by the deign rules of the standard CMOS/MEMS foundry.

Proximity gettering technology for advanced CMOS image sensors using carbon cluster ion-implantation technique. A review

Energy Technology Data Exchange (ETDEWEB)

Kurita, Kazunari; Kadono, Takeshi; Okuyama, Ryousuke; Shigemastu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Koga, Yoshihiro; Okuda, Hidehiko [SUMCO Corporation, Saga (Japan)

2017-07-15

A new technique is described for manufacturing advanced silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication processes. Carbon and hydrogen elements are localized in the projection range of the silicon wafer by implantation of ion clusters from a hydrocarbon molecular gas source. Furthermore, these wafers can getter oxygen impurities out-diffused to device active regions from a Czochralski grown silicon wafer substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as the dark current, white spot defects, pn-junction leakage current, and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly improve electrical devices performance characteristics in advanced CMOS image sensors. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Small Pixel Hybrid CMOS X-ray Detectors

Science.gov (United States)

Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

Science.gov (United States)

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

CMOS serial link for fully duplexed data communication

Science.gov (United States)

Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

1995-04-01

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

arXiv Test beam measurement of the first prototype of the fast silicon pixel monolithic detector for the TT-PET project

CERN Document Server

Paolozzi, L.; Benoit, M.; Cardarelli, R.; Débieux, S.; Forshaw, D.; Hayakawa, D.; Iacobucci, G.; Kaynak, M.; Miucci, A.; Nessi, M.; Ratib, O.; Ripiccini, E.; Rücker, H.; Valerio, P.; Weber, M.

2018-04-12

The TT-PET collaboration is developing a PET scanner for small animals with  30 ps  time-of-flight resolution and sub-millimetre 3D detection granularity. The sensitive element of the scanner is a monolithic silicon pixel detector based on state-of-the-art SiGe BiCMOS technology. The first ASIC prototype for the TT-PET was produced and tested in the laboratory and with minimum ionizing particles. The electronics exhibit an equivalent noise charge below  600 e− RMS  and a pulse rise time of less than  2 ns , in accordance with the simulations. The pixels with a capacitance of  0.8 pF  were measured to have a detection efficiency greater than  99%  and, although in the absence of the post-processing, a time resolution of approximately  200 ps .

Determination of imidazole derivatives by micellar electrokinetic chromatography combined with solid-phase microextraction using activated carbon-polymer monolith as adsorbent.

Science.gov (United States)

Shih, Yung-Han; Lirio, Stephen; Li, Chih-Keng; Liu, Wan-Ling; Huang, Hsi-Ya

2016-01-08

In this study, an effective method for the separation of imidazole derivatives 2-methylimidazole (2-MEI), 4- methylimidazole (4-MEI) and 2-acetyl-4-tetrahydroxybutylimidazole (THI) in caramel colors using cation-selective exhaustive injection and sweeping micellar electrokinetic chromatography (CSEI-sweeping-MEKC) was developed. The limits of detection (LOD) and quantitation (LOQ) for the CSEI-sweeping-MEKC method were in the range of 4.3-80μgL(-1) and 14-270μgL(-1), respectively. Meanwhile, a rapid fabrication activated carbon-polymer (AC-polymer) monolithic column as adsorbent for solid-phase microextraction (SPME) of imidazole colors was developed. Under the optimized SPME condition, the extraction recoveries for intra-day, inter-day and column-to-column were in the range of 84.5-95.1% (<6.3% RSDs), 85.6-96.1% (<4.9% RSDs), and 81.3-96.1% (<7.1% RSDs), respectively. The LODs and LOQs of AC-polymer monolithic column combined with CSEI-sweeping-MEKC method were in the range of 33.4-60.4μgL(-1) and 111.7-201.2μgL(-1), respectively. The use of AC-polymer as SPME adsorbent demonstrated the reduction of matrix effect in food samples such as soft drink and alcoholic beverage thereby benefiting successful determination of trace-level caramel colors residues using CSEI-sweeping-MEKC method. The developed AC-polymer monolithic column can be reused for more than 30 times without any significant loss in the extraction recovery for imidazole derivatives. Copyright © 2015 Elsevier B.V. All rights reserved.

Decal electronics for printed high performance cmos electronic systems

KAUST Repository

Hussain, Muhammad Mustafa; Sevilla, Galo Torres; Cordero, Marlon Diaz; Kutbee, Arwa T.

2017-01-01

High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications

CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

Data.gov (United States)

Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

CMOS Compressed Imaging by Random Convolution

OpenAIRE

Jacques, Laurent; Vandergheynst, Pierre; Bibet, Alexandre; Majidzadeh, Vahid; Schmid, Alexandre; Leblebici, Yusuf

2009-01-01

We present a CMOS imager with built-in capability to perform Compressed Sensing. The adopted sensing strategy is the random Convolution due to J. Romberg. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to comp...

The challenge of sCMOS image sensor technology to EMCCD

Science.gov (United States)

Chang, Weijing; Dai, Fang; Na, Qiyue

2018-02-01

In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

Creating deep soil core monoliths: Beyond the solum

Science.gov (United States)

Soil monoliths serve as useful teaching aids in the study of the Earth’s critical zone where rock, soil, water, air, and organisms interact. Typical monolith preparation has so far been confined to the 1 to 2-m depth of the solum. Critical ecosystem services provided by soils include materials from ...

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

Science.gov (United States)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

Science.gov (United States)

Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

2011-04-01

In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

CMOS integrated avalanche photodiodes and frequency-mixing optical sensor front end for portable NIR spectroscopy instruments.

Science.gov (United States)

Yun, Ruida; Sthalekar, Chirag; Joyner, Valencia M

2011-01-01

This paper presents the design and measurement results of two avalanche photodiode structures (APDs) and a novel frequency-mixing transimpedance amplifier (TIA), which are key building blocks towards a monolithically integrated optical sensor front end for near-infrared (NIR) spectroscopy applications. Two different APD structures are fabricated in an unmodified 0.18 \\im CMOS process, one with a shallow trench isolation (STI) guard ring and the other with a P-well guard ring. The APDs are characterized in linear mode. The STI bounded APD demonstrates better performance and exhibits 3.78 A/W responsivity at a wavelength of 690 nm and bias voltage of 10.55 V. The frequency-mixing TIA (FM-TIA) employs a T-feedback network incorporating gate-controlled transistors for resistance modulation, enabling the simultaneous down-conversion and amplification of the high frequency modulated photodiode (PD) current. The TIA achieves 92 dS Ω conversion gain with 0.5 V modulating voltage. The measured IIP(3) is 10.6/M. The amplifier together with the 50 Ω output buffer draws 23 mA from a1.8 V power supply.

Variationen und ihre Kompensation in CMOS Digitalschaltungen

OpenAIRE

Baumann, Thomas

2010-01-01

Variationen bei der Herstellung und während des Betriebs von CMOS Schaltungen beeinflussen deren Geschwindigkeit und erschweren die Verifikation der in der Spezifikation zugesicherten Eigenschaften. In dieser Arbeit wird eine abstraktionsebenenübergreifende Vorgehensweise zur Abschätzung des Einflusses von Prozess- und betriebsbedingten Umgebungsvariationen auf die Geschwindigkeit einer Schaltung vorgestellt. Neben Untersuchungen der Laufzeitsensitivität in low-power CMOS Technologien von...

Study of Monolithic Active Pixel Sensors for the Upgrade of the ALICE Inner Tracking System

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00531401

The upgrade of the ALICE vertex detector, the Inner Tracking System (ITS), is scheduled to be installed during the next long shutdown period (LS2 in 2019-2020) of the CERN Large Hadron Collider (LHC). The current ITS will be replaced by seven concentric layers of Monolithic Active Pixel Sensors (MAPS) with total active surface of $\\sim$10 m$^2$, thus making ALICE the first LHC experiment implementing MAPS detector technology on a large scale. The scope of this thesis is twofold; to report on the activity on the development and the characterisation of a MAPS for the ITS upgrade and to study the charge collection process using a first-principles Monte Carlo simulation. The performance of a MAPS depends on a large number of design and operational parameters, such as collection diode geometry, reverse bias voltage, and epitaxial layer thickness. I have studied this dependence by measuring the INVESTIGATOR chip response to X-rays emitted by an $^{55}$Fe source and to minimum ionising particles. In particular, I ha...

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

Science.gov (United States)

Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

2017-05-01

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

TiO{sub 2} on magnesium silicate monolith: effects of different preparation techniques on the photocatalytic oxidation of chlorinated hydrocarbons

Energy Technology Data Exchange (ETDEWEB)

Cardona, Ana I.; Candal, Roberto; Sanchez, Benigno; Avila, Pedro; Rebollar, Moises

2004-05-01

In this article, the comparative results of the photocatalytic oxidation of trichloroethylene (TCE) alone and a mixture of chlorinated hydrocarbons (trichloroethylene, perchloroethylene and chloroform) in gas phase, obtained with three different monolithic catalysts in a flat reactor frontally illuminated with a Xenon lamp are presented. The three catalysts incorporate titanium dioxide (TiO{sub 2}) as active phase on a magnesium silicate support, by means of different procedures: (i) incorporation of commercial TiO{sub 2} powder into the silicate matrix ('massic monolith'); (ii) sol-gel coating of the silicate support; (iii) impregnation with a commercial TiO{sub 2} aqueous suspension of the same silicate support. In the first case, the massic monolith was made from a 50:50 w/w mixture of magnesium silicate and 'Titafrance G5' TiO{sub 2} powder. In the second case, a magnesium silicate monolith was coated with several layers of an aqueous TiO{sub 2} sol prepared from hydrolysis and condensation of titanium tetra-isopropoxide (Ti(OC{sub 3}H{sub 7}){sub 4}) in excess of acidified water (acid catalysis). The third catalyst was prepared by impregnating the same silicate support with several layers of 'Titafrance G5' TiO{sub 2} powder water suspension. All the catalysts were thermal treated under comparable conditions in order to fix the TiO{sub 2} active phase to the silicate support. Although the performance of the massic monolith was better than the sol-gel monolith, the latter is of great interest because this technique allows the chemical composition of the active films to be easily modified.

Plant oil-based shape memory polymer using acrylic monolith

Directory of Open Access Journals (Sweden)

T. Tsujimoto

2015-09-01

Full Text Available This article deals with the synthesis of a plant oil-based material using acrylic monolith. An acrylic monolith bearing oxirane groups was prepared via simple technique that involved the dissolution of poly(glycidyl methacrylate-comethyl methacrylate (PGMA in ethanolic – aqueous solution by heating and subsequent cooling. The PGMA monolith had topologically porous structure, which was attributed to the phase separation of the polymer solution. The PGMA monolith was impregnated by epoxidized soybean oil (ESO containing thermally-latent catalyst, and the subsequent curing produced a crosslinked material with relatively good transparency. The Young’s modulus and the tensile strength of polyESO/PGMA increased compared with the ESO homopolymer. The strain at break of polyESO/PGMA was larger than that of the ESO homopolymer and crosslinked PGMA. Furthermore, polyESO/PGMA exhibited good shape memory-recovery behavior.

14C autoradiography with a novel wafer scale CMOS Active Pixel Sensor

International Nuclear Information System (INIS)

Esposito, M; Wells, K; Anaxagoras, T; Allinson, N M; Larner, J

2013-01-01

14 C autoradiography is a well established technique for structural and metabolic analysis of cells and tissues. The most common detection medium for this application is film emulsion, which offers unbeatable spatial resolution due to its fine granularity but at the same time has some limiting drawbacks such as poor linearity and rapid saturation. In recent years several digital detectors have been developed, following the technological transition from analog to digital-based detection systems in the medical and biological field. Even so such digital systems have been greatly limited by the size of their active area (a few square centimeters), which have made them unsuitable for routine use in many biological applications where sample areas are typically ∼ 10–100 cm 2 . The Multidimensional Integrated Intelligent Imaging (MI3-Plus) consortium has recently developed a new large area CMOS Active Pixel Sensor (12.8 cm × 13.1 cm). This detector, based on the use of two different pixel resolutions, is capable of providing simultaneously low noise and high dynamic range on a wafer scale. In this paper we will demonstrate the suitability of this detector for routine beta autoradiography in a comparative approach with widely used film emulsion.

CMOS Integrated Carbon Nanotube Sensor

International Nuclear Information System (INIS)

Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

2009-01-01

Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

CERN Document Server

Benoit, M.

2016-07-21

Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

CMOS analog circuit design

CERN Document Server

Allen, Phillip E

1987-01-01

This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

Data quality objectives summary report for the 105-N monolith off-gas issue

International Nuclear Information System (INIS)

Pisarcik, D.J.

1997-01-01

The 105-N Basin hardware waste with radiation exposure rates high enough to make above-water handling and packaging impractical has been designated high exposure rate hardware (HERH) waste. This material, consisting primarily of irradiated reactor components, is packaged underwater for subsequent disposal as a grout-encapsulated solid monolith. The third HERH waste package that was created (Monolith No. 3) was not immediately removed from the basin because of administrative delays. During a routine facility walkdown, Monolith No. 3 was observed to be emitting bubbles. Mass spectroscopic analysis of a gas sample from Monolith No. 3 indicated that the gas was 85.2% hydrogen along with a trace of fission gases (stable isotopes of xenon). Gamma energy analysis of a gas sample from Monolith No. 3 also identified trace quantities of 85 Kr. The monolith off-gas Data Quality Objective (DQO) process concluded the following: Monolith No. 3 and similar monoliths can be safely transported following installation of spacers between the lids of the L3-181 transport cask to vent the hydrogen gas; The 85 Kr does not challenge personnel or environmental safety; Fumaroles in the surface of gassing monoliths renders them incompatible with Hanford Site Solid Waste Acceptance Criteria requirements unless placed in a qualified high integrity container overpack; and Gassing monoliths do meet Environmental Restoration Disposal Facility Waste Acceptance Criteria requirements. This DQO Summary Report is both an account of the Monolith Off-Gas DQO Process and a means of documenting the concurrence of each of the stakeholder organizations

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias.

Science.gov (United States)

Stefanov, Konstantin D; Clarke, Andrew S; Ivory, James; Holland, Andrew D

2018-01-03

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

A poly(vinyl alcohol)/sodium alginate blend monolith with nanoscale porous structure

OpenAIRE

Sun, Xiaoxia; Uyama, Hiroshi

2013-01-01

A stimuli-responsive poly(vinyl alcohol) (PVA)/sodium alginate (SA) blend monolith with nanoscale porous (mesoporous) structure is successfully fabricated by thermally impacted non-solvent induced phase separation (TINIPS) method. The PVA/SA blend monolith with different SA contents is conveniently fabricated in an aqueous methanol without any templates. The solvent suitable for the fabrication of the present blend monolith by TINIPS is different with that of the PVA monolith. The nanostructu...

Energy Absorption of Monolithic and Fibre Reinforced Aluminium Cylinders

NARCIS (Netherlands)

De Kanter, J.L.C.G.

2006-01-01

Summary accompanying the thesis: Energy Absorption of Monolithic and Fibre Reinforced Aluminium Cylinders by Jens de Kanter This thesis presents the investigation of the crush behaviour of both monolithic aluminium cylinders and externally fibre reinforced aluminium cylinders. The research is based

Development of double chain phosphatidylcholine functionalized polymeric monoliths for immobilized artificial membrane chromatography.

Science.gov (United States)

Wang, Qiqin; Peng, Kun; Chen, Weijia; Cao, Zhen; Zhu, Peijie; Zhao, Yumei; Wang, Yuqiang; Zhou, Haibo; Jiang, Zhengjin

2017-01-06

This study described a simple synthetic methodology for preparing biomembrane mimicking monolithic column. The suggested approach not only simplifies the preparation procedure but also improves the stability of double chain phosphatidylcholine (PC) functionalized monolithic column. The physicochemical properties of the optimized monolithic column were characterized by scanning electron microscopy, energy-dispersive X-ray spectrometry, and nano-LC. Satisfactory column permeability, efficiency, stability and reproducibility were obtained on this double chain PC functionalized monolithic column. It is worth noting that the resulting polymeric monolith exhibits great potential as a useful alternative of commercial immobilized artificial membrane (IAM) columns for in vitro predication of drug-membrane interactions. Furthermore, the comparative study of both double chain and single chain PC functionalized monoliths indicates that the presence or absence of glycerol backbone and the number of acyl chains are not decisive for the predictive ability of IAM monoliths on drug-membrane interactions. This novel PC functionalized monolithic column also exhibited good selectivity for a protein mixture and a set of pharmaceutical compounds. Copyright © 2016 Elsevier B.V. All rights reserved.

Long term ionization response of several BiCMOS VLSIC technologies

International Nuclear Information System (INIS)

Pease, R.L.; Combs, W.; Clark, S.

1992-01-01

BiCMOS is emerging as a strong competitor to CMOS for gate arrays and memories because of its performance advantages for the same feature size. In this paper, the authors examine the long term ionization response of five BiCMOS technologies by characterizing test structures which emphasize the various failure modes of CMOS and bipolar. The primary failure modes are found to be associated with the recessed field oxide isolation; edge leakage in the n channel MOSFETs and buried layer to buried layer leakage in the bipolar. The ionization failure thresholds for worst case bias were in the range of 5-20 Krad(Si) for both failure modes in all five technologies

First principle leakage current reduction technique for CMOS devices

CSIR Research Space (South Africa)

Tsague, HD

2015-12-01

Full Text Available This paper presents a comprehensive study of leakage reduction techniques applicable to CMOS based devices. In the process, mathematical equations that model the power-performance trade-offs in CMOS logic circuits are presented. From those equations...

A monolithic glass chip for active single-cell sorting based on mechanical phenotyping.

Science.gov (United States)

Faigle, Christoph; Lautenschläger, Franziska; Whyte, Graeme; Homewood, Philip; Martín-Badosa, Estela; Guck, Jochen

2015-03-07

The mechanical properties of biological cells have long been considered as inherent markers of biological function and disease. However, the screening and active sorting of heterogeneous populations based on serial single-cell mechanical measurements has not been demonstrated. Here we present a novel monolithic glass chip for combined fluorescence detection and mechanical phenotyping using an optical stretcher. A new design and manufacturing process, involving the bonding of two asymmetrically etched glass plates, combines exact optical fiber alignment, low laser damage threshold and high imaging quality with the possibility of several microfluidic inlet and outlet channels. We show the utility of such a custom-built optical stretcher glass chip by measuring and sorting single cells in a heterogeneous population based on their different mechanical properties and verify sorting accuracy by simultaneous fluorescence detection. This offers new possibilities of exact characterization and sorting of small populations based on rheological properties for biological and biomedical applications.

Advantages of a vertical integration process in the design of DNW MAPS

International Nuclear Information System (INIS)

Ratti, L.; Gaioni, L.; Manazza, A.; Manghisoni, M.; Re, V.; Traversi, G.

2015-01-01

This work discusses the main features of a CMOS Deep N-well (DNW) monolithic active pixel sensor (MAPS) fabricated in a vertically integrated technology, where two 130 nm CMOS homogeneous tiers are processed to obtain a 3D integrated circuit (3D-IC). The 3D CMOS MAPS, which was designed in view of vertexing applications to experiments at high luminosity colliders, features a 20 μm pitch for a point resolution of about 5 μm and data sparsification capabilities for high data rate systems. Results from the characterization of different test structures, including single pixels, 3×3 and 8×8 matrices, are presented. In particular, measurements have been performed with an infrared laser source to evaluate the charge collection properties of the proposed vertically integrated sensors

Advantages of a vertical integration process in the design of DNW MAPS

Energy Technology Data Exchange (ETDEWEB)

Ratti, L. [Università di Pavia, Dipartimento di Elettronica, Via Ferrata 1, I-27100 Pavia (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy); Gaioni, L. [Università di Bergamo, Dipartimento di Ingegneria Industriale, Via Marconi 5, I-24044 Dalmine (Italy); Manazza, A. [INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy); Manghisoni, M.; Re, V.; Traversi, G. [Università di Bergamo, Dipartimento di Ingegneria Industriale, Via Marconi 5, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy)

2015-06-01

This work discusses the main features of a CMOS Deep N-well (DNW) monolithic active pixel sensor (MAPS) fabricated in a vertically integrated technology, where two 130 nm CMOS homogeneous tiers are processed to obtain a 3D integrated circuit (3D-IC). The 3D CMOS MAPS, which was designed in view of vertexing applications to experiments at high luminosity colliders, features a 20 μm pitch for a point resolution of about 5 μm and data sparsification capabilities for high data rate systems. Results from the characterization of different test structures, including single pixels, 3×3 and 8×8 matrices, are presented. In particular, measurements have been performed with an infrared laser source to evaluate the charge collection properties of the proposed vertically integrated sensors.

Monolithic multinozzle emitters for nanoelectrospray mass spectrometry

Science.gov (United States)

Wang, Daojing [Daly City, CA; Yang, Peidong [Kensington, CA; Kim, Woong [Seoul, KR; Fan, Rong [Pasadena, CA

2011-09-20

Novel and significantly simplified procedures for fabrication of fully integrated nanoelectrospray emitters have been described. For nanofabricated monolithic multinozzle emitters (NM.sup.2 emitters), a bottom up approach using silicon nanowires on a silicon sliver is used. For microfabricated monolithic multinozzle emitters (M.sup.3 emitters), a top down approach using MEMS techniques on silicon wafers is used. The emitters have performance comparable to that of commercially-available silica capillary emitters for nanoelectrospray mass spectrometry.

Decomposition of monolithic web application to microservices

OpenAIRE

Zaymus, Mikulas

2017-01-01

Solteq Oyj has an internal Wellbeing project for massage reservations. The task of this thesis was to transform the monolithic architecture of this application to microservices. The thesis starts with a detailed comparison between microservices and monolithic application. It points out the benefits and disadvantages microservice architecture can bring to the project. Next, it describes the theory and possible strategies that can be used in the process of decomposition of an existing monoli...

Fracture-resistant monolithic dental crowns.

Science.gov (United States)

Zhang, Yu; Mai, Zhisong; Barani, Amir; Bush, Mark; Lawn, Brian

2016-03-01

To quantify the splitting resistance of monolithic zirconia, lithium disilicate and nanoparticle-composite dental crowns. Fracture experiments were conducted on anatomically-correct monolithic crown structures cemented to standard dental composite dies, by axial loading of a hard sphere placed between the cusps. The structures were observed in situ during fracture testing, and critical loads to split the structures were measured. Extended finite element modeling (XFEM), with provision for step-by-step extension of embedded cracks, was employed to simulate full failure evolution. Experimental measurements and XFEM predictions were self-consistent within data scatter. In conjunction with a fracture mechanics equation for critical splitting load, the data were used to predict load-sustaining capacity for crowns on actual dentin substrates and for loading with a sphere of different size. Stages of crack propagation within the crown and support substrate were quantified. Zirconia crowns showed the highest fracture loads, lithium disilicate intermediate, and dental nanocomposite lowest. Dental nanocomposite crowns have comparable fracture resistance to natural enamel. The results confirm that monolithic crowns are able to sustain high bite forces. The analysis indicates what material and geometrical properties are important in optimizing crown performance and longevity. Copyright © 2015 Academy of Dental Materials. All rights reserved.

Development of monolithic pixel detector with SOI technology for the ILC vertex detector

Science.gov (United States)

Yamada, M.; Ono, S.; Tsuboyama, T.; Arai, Y.; Haba, J.; Ikegami, Y.; Kurachi, I.; Togawa, M.; Mori, T.; Aoyagi, W.; Endo, S.; Hara, K.; Honda, S.; Sekigawa, D.

2018-01-01

We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

Science.gov (United States)

Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

2012-04-01

In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

Agglomerated polymer monoliths with bimetallic nano-particles as flow-through micro-reactors

International Nuclear Information System (INIS)

Floris, P.; Twamley, B.; Nesterenko, P.N.; Paull, B.; Connolly, D.

2012-01-01

Polymer monoliths in capillary format have been prepared as solid supports for the immobilisation of platinum/palladium bimetallic nano-flowers. Optimum surface coverage of nano-flowers was realised by photografting the monoliths with vinyl azlactone followed by amination with ethylenediamine prior to nano-particle immobilisation. Field emission SEM imaging was used as a characterisation tool for evaluating nano-particle coverage, together with BET surface area analysis to probe the effect of nano-particle immobilisation upon monolith morphology. Ion exchange chromatography was also used to confirm the nature of the covalent attachment of nano-flowers on the monolithic surface. In addition, EDX and ICP analyses were used to quantify platinum and palladium on modified polymer monoliths. Finally the catalytic properties of immobilised bimetallic Pd/Pt nano-flowers were evaluated in flow-through mode, exploiting the porous interconnected flow-paths present in the prepared monoliths (pore diameter ∼ 1-2 μm). Specifically, the reduction of Fe (III) to Fe (II) and the oxidation of NADH to NAD+ were selected as model redox reactions. The use of a porous polymer monolith as an immobilisation substrate (rather than aminated micro-spheres) eliminated the need for a centrifugation step after the reaction. (author)

Merits of CMOS/SIMOX technology for low-voltage SRAM macros

CERN Document Server

Kumagai, K; Yamada, T; Nakamura, H; Onishi, H; Matsubara, Y; Imai, K; Kurosawa, S

1999-01-01

A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs).

Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

International Nuclear Information System (INIS)

Liu, Q; Van Duzer, T; Fujiwara, K; Yoshikawa, N

2006-01-01

Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 μm CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm 2 technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory

A novel simulation method to evaluate the collection performance of a monolithic active pixel sensor

International Nuclear Information System (INIS)

Fu Min; Tang Zhen'an

2011-01-01

A novel simulation method is presented in this paper to evaluate the collection performance of monolithic active pixel sensor (MAPS) devices for minimum ionizing particle tracking. A simplified 3D matrix pixel structure is built using the computer aided design software Sentaurus. The virtual device is then divided into hundreds of parts and an independent customized X photon model is involved in each part to simulate the conditions under 55 Fe radiation. After data processing and analysis, charge collection efficiency, collection time and diffusion conditions can be estimated in detail. In order to verify the reliability of the method, comparisons are made between the simulations and experiments. Although there are some defects, it can be concluded that the proposed idea is a feasible method for the evaluation of the MAPS collection performance. (authors)

A radiation-hardened two transistor memory cell for monolithic active pixel sensors in STAR experiment

International Nuclear Information System (INIS)

Wei, X; Dorokhov, A; Hu, Y; Gao, D

2011-01-01

Radiation tolerance of Monolithic Active Pixel Sensors (MAPS) is dramatically decreased when intellectual property (IP) memories are integrated for fast readout application. This paper presents a new solution to improve radiation hardness and avoid latch-up for memory cell design. The tradeoffs among radiation tolerance, area and speed are significantly considered and analyzed. The cell designed in 0.35 μm process satisfies the radiation tolerance requirements of STAR experiment. The cell size is 4.55 x 5.45 μm 2 . This cell is smaller than the IP memory cell based on the same process and is only 26% of a radiation tolerant 6T SRAM cell used in previous contribution. The write access time of the cell is less than 2 ns, while the read access time is 80 ns.

Immobilisation of shredded soft waste in cement monolith

International Nuclear Information System (INIS)

Brown, D.J.; Dalton, M.J.; Smith, D.L.

1983-04-01

A grouting process for the immobilisation of shredded contaminated laboratory waste in a cement monolith is being developed at the Atomic Energy Establishment Winfrith. The objective is to produce a 'monolithic' type package which is acceptable both for sea and land disposal. The work carried out on this project in the period April 1982 - March 1983 is summarised in this report. (author)

Cryo-CMOS Circuits and Systems for Quantum Computing Applications

NARCIS (Netherlands)

Patra, B; Incandela, R.M.; van Dijk, J.P.G.; Homulle, H.A.R.; Song, Lin; Shahmohammadi, M.; Staszewski, R.B.; Vladimirescu, A.; Babaie, M.; Sebastiano, F.; Charbon, E.E.E.

2018-01-01

A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising

CMOS-compatible high-voltage integrated circuits

Energy Technology Data Exchange (ETDEWEB)

Parpia, Z

1988-01-01

Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

Preparation of organic monolithic columns in polytetrafluoroethylene tubes for reversed-phase liquid chromatography

International Nuclear Information System (INIS)

Catalá-Icardo, M.; Torres-Cartas, S.; Meseguer-Lloret, S.; Gómez-Benito, C.; Carrasco-Correa, E.; Simó-Alfonso, E.F.; Ramis-Ramos, G.; Herrero-Martínez, J.M.

2017-01-01

In this work, a method for the preparation and anchoring of polymeric monoliths in a polytetrafluoroethylene (PTFE) tubing as a column housing for microbore HPLC is described. In order to assure a covalent attachment of the monolith to the inner wall of the PTFE tube, a two-step procedure was developed. Two surface etching reagents, a commercial sodium naphthalene solution (Fluoroetch"®), or mixtures of H_2O_2 and H_2SO_4, were tried and compared. Then, the obtained hydroxyl groups on the PTFE surface were modified by methacryloylation. Attenuated total reflectance Fourier-transform infrared (ATR-FTIR) spectroscopy and scanning electron microscopy (SEM) confirmed the successful modification of the tubing wall and the stable anchorage of monolith to the wall, respectively. Special emphasis was also put on the reduction of the unwanted effects of shrinking of monolith during polymerization, by using an external proper mold and by selecting the adequate monomers in order to increase the flexibility of the polymer. Poly(glycidyl methacrylate-co-divinylbenzene) monoliths were in situ synthesized by thermal polymerization within the confines of surface-vinylized PTFE tubes. The modified PTFE tubing tightly held the monolith, and the monolithic column exhibited good pressure resistance up to 20 MPa. The column performance was also evaluated via the isocratic separation of a series of alkylbenzenes in the reversed-phase mode. The optimized monolithic columns gave plate heights ranged between 70 and 80 μm. The resulting monoliths were also satisfactorily applied to the separation of proteins. - Highlights: • Successful surface etching of PTFE inner wall tubing was done. • The modified PTFE support was next methacryloylated with GMA. • Organic polymeric monolith was in situ prepared in the functionalized PTFE tube. • The monolithic columns gave suitable pressure resistance and separation of proteins.

Preparation of organic monolithic columns in polytetrafluoroethylene tubes for reversed-phase liquid chromatography

Energy Technology Data Exchange (ETDEWEB)

Catalá-Icardo, M., E-mail: mocaic@qim.upv.es [Research Institute for Integrated Management of Coastal Areas, Universitat Politècnica de València, Paranimf 1, 46730, Grao de Gandía, Valencia (Spain); Torres-Cartas, S.; Meseguer-Lloret, S.; Gómez-Benito, C. [Research Institute for Integrated Management of Coastal Areas, Universitat Politècnica de València, Paranimf 1, 46730, Grao de Gandía, Valencia (Spain); Carrasco-Correa, E.; Simó-Alfonso, E.F.; Ramis-Ramos, G. [Department of Analytical Chemistry, Universitat de València, Dr. Moliner 50, 46100, Burjassot, Valencia (Spain); Herrero-Martínez, J.M., E-mail: jmherrer@uv.es [Department of Analytical Chemistry, Universitat de València, Dr. Moliner 50, 46100, Burjassot, Valencia (Spain)

2017-04-01

In this work, a method for the preparation and anchoring of polymeric monoliths in a polytetrafluoroethylene (PTFE) tubing as a column housing for microbore HPLC is described. In order to assure a covalent attachment of the monolith to the inner wall of the PTFE tube, a two-step procedure was developed. Two surface etching reagents, a commercial sodium naphthalene solution (Fluoroetch{sup ®}), or mixtures of H{sub 2}O{sub 2} and H{sub 2}SO{sub 4}, were tried and compared. Then, the obtained hydroxyl groups on the PTFE surface were modified by methacryloylation. Attenuated total reflectance Fourier-transform infrared (ATR-FTIR) spectroscopy and scanning electron microscopy (SEM) confirmed the successful modification of the tubing wall and the stable anchorage of monolith to the wall, respectively. Special emphasis was also put on the reduction of the unwanted effects of shrinking of monolith during polymerization, by using an external proper mold and by selecting the adequate monomers in order to increase the flexibility of the polymer. Poly(glycidyl methacrylate-co-divinylbenzene) monoliths were in situ synthesized by thermal polymerization within the confines of surface-vinylized PTFE tubes. The modified PTFE tubing tightly held the monolith, and the monolithic column exhibited good pressure resistance up to 20 MPa. The column performance was also evaluated via the isocratic separation of a series of alkylbenzenes in the reversed-phase mode. The optimized monolithic columns gave plate heights ranged between 70 and 80 μm. The resulting monoliths were also satisfactorily applied to the separation of proteins. - Highlights: • Successful surface etching of PTFE inner wall tubing was done. • The modified PTFE support was next methacryloylated with GMA. • Organic polymeric monolith was in situ prepared in the functionalized PTFE tube. • The monolithic columns gave suitable pressure resistance and separation of proteins.

Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders — from Optical Triangulation to the Automotive Field

Directory of Open Access Journals (Sweden)

Joe-Air Jiang

2008-03-01

Full Text Available With their significant features, the applications of complementary metal-oxidesemiconductor (CMOS image sensors covers a very extensive range, from industrialautomation to traffic applications such as aiming systems, blind guidance, active/passiverange finders, etc. In this paper CMOS image sensor-based active and passive rangefinders are presented. The measurement scheme of the proposed active/passive rangefinders is based on a simple triangulation method. The designed range finders chieflyconsist of a CMOS image sensor and some light sources such as lasers or LEDs. Theimplementation cost of our range finders is quite low. Image processing software to adjustthe exposure time (ET of the CMOS image sensor to enhance the performance oftriangulation-based range finders was also developed. An extensive series of experimentswere conducted to evaluate the performance of the designed range finders. From theexperimental results, the distance measurement resolutions achieved by the active rangefinder and the passive range finder can be better than 0.6% and 0.25% within themeasurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests onapplications of the developed CMOS image sensor-based range finders to the automotivefield were also conducted. The experimental results demonstrated that our range finders arewell-suited for distance measurements in this field.

Increased thermal conductivity monolithic zeolite structures

Science.gov (United States)

Klett, James; Klett, Lynn; Kaufman, Jonathan

2008-11-25

A monolith comprises a zeolite, a thermally conductive carbon, and a binder. The zeolite is included in the form of beads, pellets, powders and mixtures thereof. The thermally conductive carbon can be carbon nano-fibers, diamond or graphite which provide thermal conductivities in excess of about 100 W/mK to more than 1,000 W/mK. A method of preparing a zeolite monolith includes the steps of mixing a zeolite dispersion in an aqueous colloidal silica binder with a dispersion of carbon nano-fibers in water followed by dehydration and curing of the binder is given.

Development and characterization of methacrylate-based hydrazide monoliths for oriented immobilization of antibodies.

Science.gov (United States)

Brne, P; Lim, Y-P; Podgornik, A; Barut, M; Pihlar, B; Strancar, A

2009-03-27

Convective interaction media (CIM; BIA Separations) monoliths are attractive stationary phases for use in affinity chromatography because they enable fast affinity binding, which is a consequence of convectively enhanced mass transport. This work focuses on the development of novel CIM hydrazide (HZ) monoliths for the oriented immobilization of antibodies. Adipic acid dihydrazide (AADH) was covalently bound to CIM epoxy monoliths to gain hydrazide groups on the monolith surface. Two different antibodies were afterwards immobilized to hydrazide functionalized monolithic columns and prepared columns were tested for their selectivity. One column was further tested for the dynamic binding capacity.

A Monolithically-Integrated μGC Chemical Sensor System

Directory of Open Access Journals (Sweden)

Davor Copic

2011-06-01

Full Text Available Gas chromatography (GC is used for organic and inorganic gas detection with a range of applications including screening for chemical warfare agents (CWA, breath analysis for diagnostics or law enforcement purposes, and air pollutants/indoor air quality monitoring of homes and commercial buildings. A field-portable, light weight, low power, rapid response, micro-gas chromatography (μGC system is essential for such applications. We describe the design, fabrication and packaging of mGC on monolithically-integrated Si dies, comprised of a preconcentrator (PC, μGC column, detector and coatings for each of these components. An important feature of our system is that the same mechanical micro resonator design is used for the PC and detector. We demonstrate system performance by detecting four different CWA simulants within 2 min. We present theoretical analyses for cost/power comparisons of monolithic versus hybrid μGC systems. We discuss thermal isolation in monolithic systems to improve overall performance. Our monolithically-integrated μGC, relative to its hybrid cousin, will afford equal or slightly lower cost, a footprint that is 1/2 to 1/3 the size and an improved resolution of 4 to 25%.

A novel photocatalytic monolith reactor for multiphase heterogeneous photocatalysis

NARCIS (Netherlands)

Du, P.; Carneiro, J.T.; Moulijn, J.A.; Mul, Guido

2008-01-01

A novel reactor for multi-phase photocatalysis is presented, the so-called internally illuminated monolith reactor (IIMR). In the concept of the IIMR, side light emitting fibers are placed inside the channels of a ceramic monolith, equipped with a TiO2 photocatalyst coated on the wall of each

CMOS image sensor-based immunodetection by refractive-index change.

Science.gov (United States)

Devadhasan, Jasmine P; Kim, Sanghyo

2012-01-01

A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

Monolithic JFET preamplifier for ionization chamber calorimeter

International Nuclear Information System (INIS)

Radeka, V.; Rescia, S.; Manfredi, P.F.; Speziali, V.

1990-10-01

A monolithic charge sensitive preamplifier using exclusively n-channel diffused JFETs has been designed and is now being fabricated by INTERFET Corp. by means of a dielectrically isolated process which allows preserving as much as possible the technology upon which discrete JFETs are based. A first prototype built by means of junction isolated process has been delivered. The characteristics of monolithically integrated JFETs compare favorably with discrete devices. First results of tests of a preamplifier which uses these devices are reported. 4 refs

CMOS circuit design, layout and simulation

CERN Document Server

Baker, R Jacob

2010-01-01

The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

CMOS foveal image sensor chip

Science.gov (United States)

Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

2002-01-01

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

CMOS sensors for atmospheric imaging

Science.gov (United States)

Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

2017-09-01

Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

Active Pixel Sensors for electron microscopy

Energy Technology Data Exchange (ETDEWEB)

Denes, P. [Engineering Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)], E-mail: pdenes@lbl.gov; Bussat, J.-M. [Engineering Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Lee, Z.; Radmillovic, V. [National Center for Electron Microscopy, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)

2007-09-01

The technology used for monolithic CMOS imagers, popular for cell phone cameras and other photographic applications, has been explored for charged particle tracking by the high-energy physics community for several years. This technology also lends itself to certain imaging detector applications in electron microscopy. We have been developing such detectors for several years at Lawrence Berkeley National Laboratory, and we and others have shown that this technology can offer excellent point-spread function, direct detection and high readout speed. In this paper, we describe some of the design constraints peculiar to electron microscopy and summarize where such detectors could play a useful role.

An overview of monolithic zirconia in dentistry

Directory of Open Access Journals (Sweden)

Özlem Malkondu

2016-07-01

Full Text Available Zirconia restorations have been used successfully for years in dentistry owing to their biocompatibility and good mechanical properties. Because of their lack of translucency, zirconia cores are generally veneered with porcelain, which makes restorations weaker due to failure of the adhesion between the two materials. In recent years, all-ceramic zirconia restorations have been introduced in the dental sector with the intent to solve this problem. Besides the elimination of chipping, the reduced occlusal space requirement seems to be a clear advantage of monolithic zirconia restorations. However, scientific evidence is needed to recommend this relatively new application for clinical use. This mini-review discusses the current scientific literature on monolithic zirconia restorations. The results of in vitro studies suggested that monolithic zirconia may be the best choice for posterior fixed partial dentures in the presence of high occlusal loads and minimal occlusal restoration space. The results should be supported with much more in vitro and particularly in vivo studies to obtain a final conclusion.

Fracture Strength of Aged Monolithic and Bilayer Zirconia-Based Crowns

Directory of Open Access Journals (Sweden)

Deborah Pacheco Lameira

2015-01-01

Full Text Available The purpose of this study was to evaluate the effect of design and surface finishing on fracture strength of yttria-tetragonal zirconia polycrystal (Y-TZP crowns in monolithic (1.5 mm thickness and bilayer (0.8 mm zirconia coping and 0.7 mm porcelain veneer configuration after artificial aging. Bovine incisors received crown preparation and Y-TZP crowns were manufactured using CAD/CAM technique, according to the following groups (n=10: Polished monolithic zirconia crowns (PM; Glazed monolithic zirconia crowns (GM; Bi-layer crowns (BL. Crowns were cemented with resin cement, submitted to artificial aging in a chewing simulator (2.5 million cycles/80 N/artificial saliva/37°C, and tested for fracture strength. Two remaining crowns referring to PM and GM groups were submitted to a chemical composition analysis to measure the level of yttrium after aging. One-way ANOVA and Tukey’s test (P=.05 indicated that monolithic zirconia crowns presented similar fracture strength (PM=3476.2 N ± 791.7; GM=3561.5 N ± 991.6, which was higher than bilayer crowns (2060.4 N ± 810.6. There was no difference in the yttrium content among the three surfaces evaluated in the monolithic crowns. Thus, monolithic zirconia crowns present higher fracture strength than bilayer veneered zirconia after artificial aging and surface finishing does not affect their fracture strength.

Single-chip RF communications systems in CMOS

DEFF Research Database (Denmark)

Olesen, Ole

1997-01-01

The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

CMOS sigma-delta converters practical design guide

CERN Document Server

De la Rosa, Jose M

2013-01-01

A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

International Nuclear Information System (INIS)

Bronuzzi, J.; Mapelli, A.; Moll, M.; Sallese, J.M.

2016-01-01

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

Tannin-based monoliths from emulsion-templating

International Nuclear Information System (INIS)

Szczurek, A.; Martinez de Yuso, A.; Fierro, V.; Pizzi, A.; Celzard, A.

2015-01-01

Highlights: • Efficient preparation procedures are presented for new and “green” tannin-based organic polyHIPEs. • Highest homogeneity and strength are obtained at an oil fraction near the close-packing value. • Structural and mechanical properties abruptly change above such critical value. - Abstract: Highly porous monoliths prepared by emulsion-templating, frequently called polymerised High Internal Phase Emulsions (polyHIPEs) in the literature, were prepared from “green” precursors such as Mimosa bark extract, sunflower oil and ethoxylated castor oil. Various oil fractions, ranging from 43 to 80 vol.%, were used and shown to have a dramatic impact on the resultant porous structure. A critical oil fraction around 70 vol.% was found to exist, close to the theoretical values of 64% and 74% for random and compact sphere packing, respectively, at which the properties of both emulsions and derived porous monoliths changed. Such change of behaviour was observed by many different techniques such as viscosity, electron microscopy, mercury intrusion, and mechanical studies. We show and explain why this critical oil fraction is the one leading to the strongest and most homogeneous porous monoliths

High-Voltage-Input Level Translator Using Standard CMOS

Science.gov (United States)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

Advancement of CMOS Doping Technology in an External Development Framework

Science.gov (United States)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.