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Sample records for cmos integrated low-noise

  1. A low-noise, wideband, integrated CMOS transimpedance preamplifier for photodiode applications

    International Nuclear Information System (INIS)

    Binkley, D.M.; Paulus, M.J.; Casey, M.E.; Rochelle, J.M.

    1992-01-01

    In this paper, a low-noise, wideband, integrated CMOS transimpedance preamplifier is presented for silicon avalanche photodiode (APD) applications. The preamplifier, fabricated in a standard 2μ CMOS technology, features a transimpedance gain of 45 kΩ, a risetime of 22 ns, a series noise of 1.6nV/Hz 1/2 , and a wideband equivalent input-noise current of 12 nA for a source capacitance of 12 pF. The measured 22 Na timing resolution of 9.2-ns FWHM and energy resolution of 22.4% FWHM for the RCA C30994 BGO/APD detector module coupled to the preamplifier is comparable to the performance reported using charge-sensitive preamplifiers. This illustrates that transimpedance preamplifiers should be considered for APD applications, especially where APD noise current dominates noise from feedback resistors in the 1--kΩ to 50-kΩ range

  2. Low noise monolithic CMOS front end electronics

    International Nuclear Information System (INIS)

    Lutz, G.; Bergmann, H.; Holl, P.; Manfredi, P.F.

    1987-01-01

    Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

  3. Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

    Directory of Open Access Journals (Sweden)

    Ler Chun Lee

    2008-01-01

    Full Text Available A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA. A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

  4. A wideband CMOS inductorless low noise amplifier employing noise cancellation for digital TV tuner applications

    International Nuclear Information System (INIS)

    Zhang Jihong; Bai Xuefei; Huang Lu

    2013-01-01

    A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2–15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point (IP1dB) is − 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5 × 0.35 mm 2 . (semiconductor integrated circuits)

  5. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

    Directory of Open Access Journals (Sweden)

    Cheng-Chun Wu

    2016-10-01

    Full Text Available An electronic nose (E-Nose is one of the applications for surface acoustic wave (SAW sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS readout application-specific integrated circuit (ASIC based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

  6. A Baseband Ultra-Low Noise SiGe:C BiCMOS 0.25 µm Amplifier And Its Application For An On-Chip Phase-Noise Measurement Circuit

    OpenAIRE

    Godet , Sylvain; Tournier , Éric; Llopis , Olivier; Cathelin , Andreia; Juyon , Julien

    2009-01-01

    4 pages; International audience; The design and realization of an ultra-low noise operational amplifier is presented. Its applications are integrated low-frequency noise measurements in electronic devices and on-chip phase-noise measurement circuit. This paper discusses the SiGe:C BiCMOS 0.25 µm design improvements used for low noise applications. The proposed three-stage operational amplifier uses parallel bipolar transistor connection as input differential pair for low noise behavior. This ...

  7. Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

    Directory of Open Access Journals (Sweden)

    Min Yoon

    2016-01-01

    Full Text Available We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency CMOS (fT/fmax=120/140 GHz technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to reduce parasitic capacitance at the band of 24 GHz. The proposed sensor has low cost and low power dissipation since it is realized using CMOS process. The proposed sensor showed the lowest noise figure of 2.9 dB and the highest conversion gain of 40.2 dB as compared to recently reported research results. It also showed small chip size of 0.56 mm2, low power dissipation of 39.5 mW, and wide operating temperature range of −40 to +125°C.

  8. A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters

    International Nuclear Information System (INIS)

    Chen Mingyi; Chu Xiaojie; Yu Peng; Yan Jun; Shi Yin

    2013-01-01

    A fully integrated ΔΣ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network (WLAN) transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm 2 excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves −99 dBc/Hz and −119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6°. The proposed synthesizer consumes a total power of 15.6 mW. (semiconductor integrated circuits)

  9. Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

    Science.gov (United States)

    Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

    2009-05-01

    This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

  10. An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

    International Nuclear Information System (INIS)

    Fiorini, C.; Porro, M.

    2006-01-01

    We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

  11. Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors

    NARCIS (Netherlands)

    Chen, Y.; Theuwissen, A.J.P.; Chae, Y.

    2011-01-01

    This paper presents a low noise CMOS image sensor (CIS) using 10/12 bit configurable column-parallel single slope ADCs (SS-ADCs) and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with a pinned-photodiode as photon detector. The test sensor was

  12. Low-Power Low-Noise CMOS Imager Design : In Micro-Digital Sun Sensor Application

    NARCIS (Netherlands)

    Xie, N.

    2012-01-01

    A digital sun sensor is superior to an analog sun sensor in aspects of resolution, albedo immunity, and integration. The proposed Micro-Digital Sun Sensor (µDSS) is an autonomous digital sun sensor which is implemented by means of a CMOS image sensor, which is named APS+. The µDSS is designed

  13. CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

    International Nuclear Information System (INIS)

    Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

    1996-01-01

    In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

  14. Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    J. Sturm

    2014-04-01

    Full Text Available The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends.

  15. Design and analysis of high gain and low noise figure CMOS low noise amplifier for Q-band nano-sensor application

    Science.gov (United States)

    Suganthi, K.; Malarvizhi, S.

    2018-03-01

    A high gain, low power, low Noise figure (NF) and wide band of milli-meter Wave (mmW) circuits design at 50 GHz are used for Radio Frequency (RF) front end. The fundamental necessity of a receiver front-end includes perfect output and input impedance matching and port-to-port isolation with high gain and low noise over the entire band of interest. In this paper, a design of Cascade-Cascode CMOS LNA circuit at 50 GHz for Q-band application is proposed. The design of Low noise amplifier at 50 GHz using Agilent ADS tool with microstrip lines which provides simplicity in fabrication and less chip area. The low off-leakage current Ioff can be maintained with high K-dielectrics CMOS structure. Nano-scale electronics can be achieved with increased robustness. The design has overall gain of 11.091 dB and noise figure of 2.673 dB for the Q-band of 48.3 GHz to 51.3 GHz. Impedance matching is done by T matching network and the obtained input and output reflection coefficients are S11 = <-10 dB and S22 = <-10 dB. Compared to Silicon (Si) material, Wide Band Gap semiconductor materials used attains higher junction temperatures which is well matched to ceramics used in packaging technology, the protection and reliability also can be achieved with the electronic packaging. The reverse transmission coefficient S21 is less than -21 dB has shown that LNA has better isolation between input and output, Stability factor greater than 1 and Power is also optimized in this design. Layout is designed, power gain of 4.6 dB is achieved and area is optimized which is nearly equal to 502 740 μm2. The observed results show that the proposed Cascade-Cascode LNA design can find its suitability in future milli-meter Wave Radar application.

  16. A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

    Science.gov (United States)

    Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

    2016-03-03

    This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

  17. A high-speed low-noise transimpedance amplifier in a 025 mum CMOS technology

    CERN Document Server

    Anelli, G; Casagrande, L; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4fC, an input capacitance of 4pF and a transresistance of 135kOmega, we have measured an output pulse fall time of 3ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the constructio...

  18. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Shoji Kawahito

    2016-11-01

    Full Text Available This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs. This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC. The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median: 0.29 e−rms when compared with the CMS gain of two (2.4 e−rms, or 16 (1.1 e−rms.

  19. Effect of drain current on appearance probability and amplitude of random telegraph noise in low-noise CMOS image sensors

    Science.gov (United States)

    Ichino, Shinya; Mawaki, Takezo; Teramoto, Akinobu; Kuroda, Rihito; Park, Hyeonwoo; Wakashima, Shunichi; Goto, Tetsuya; Suwa, Tomoyuki; Sugawa, Shigetoshi

    2018-04-01

    Random telegraph noise (RTN), which occurs in in-pixel source follower (SF) transistors, has become one of the most critical problems in high-sensitivity CMOS image sensors (CIS) because it is a limiting factor of dark random noise. In this paper, the behaviors of RTN toward changes in SF drain current conditions were analyzed using a low-noise array test circuit measurement system with a floor noise of 35 µV rms. In addition to statistical analysis by measuring a large number of transistors (18048 transistors), we also analyzed the behaviors of RTN parameters such as amplitude and time constants in the individual transistors. It is demonstrated that the appearance probability of RTN becomes small under a small drain current condition, although large-amplitude RTN tends to appear in a very small number of cells.

  20. A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

    Directory of Open Access Journals (Sweden)

    Min-Kyu Kim

    2015-12-01

    Full Text Available This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs. The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

  1. A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

    Science.gov (United States)

    Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

    2016-01-01

    This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz. PMID:26950131

  2. Low-Gain, Low-Noise Integrated Neuronal Amplifier for Implantable Artifact-Reduction Recording System

    Directory of Open Access Journals (Sweden)

    Abdelhamid Benazzouz

    2013-09-01

    Full Text Available Brain neuroprostheses for neuromodulation are being designed to monitor the neural activity of the brain in the vicinity of the region being stimulated using a single macro-electrode. Using a single macro-electrode, recent neuromodulation studies show that recording systems with a low gain neuronal amplifier and successive amplifier stages can reduce or reject stimulation artifacts. These systems were made with off-the-shelf components that are not amendable for future implant design. A low-gain, low-noise integrated neuronal amplifier (NA with the capability of recording local field potentials (LFP and spike activity is presented. In vitro and in vivo characterizations of the tissue/electrode interface, with equivalent impedance as an electrical model for recording in the LFP band using macro-electrodes for rodents, contribute to the NA design constraints. The NA occupies 0.15 mm2 and dissipates 6.73 µW, and was fabricated using a 0.35 µm CMOS process. Test-bench validation indicates that the NA provides a mid-band gain of 20 dB and achieves a low input-referred noise of 4 µVRMS. Ability of the NA to perform spike recording in test-bench experiments is presented. Additionally, an awake and freely moving rodent setup was used to illustrate the integrated NA ability to record LFPs, paving the pathway for future implantable systems for neuromodulation.

  3. Low-Noise CMOS Circuits for On-Chip Signal Processing in Focal-Plane Arrays

    Science.gov (United States)

    Pain, Bedabrata

    The performance of focal-plane arrays can be significantly enhanced through the use of on-chip signal processing. Novel, in-pixel, on-focal-plane, analog signal-processing circuits for high-performance imaging are presented in this thesis. The presence of a high background-radiation is a major impediment for infrared focal-plane array design. An in-pixel, background-suppression scheme, using dynamic analog current memory circuit, is described. The scheme also suppresses spatial noise that results from response non-uniformities of photo-detectors, leading to background limited infrared detector readout performance. Two new, low-power, compact, current memory circuits, optimized for operation at ultra-low current levels required in infrared-detection, are presented. The first one is a self-cascading current memory that increases the output impedance, and the second one is a novel, switch feed-through reducing current memory, implemented using error-current feedback. This circuit can operate with a residual absolute -error of less than 0.1%. The storage-time of the memory is long enough to also find applications in neural network circuits. In addition, a voltage-mode, accurate, low-offset, low-power, high-uniformity, random-access sample-and-hold cell, implemented using a CCD with feedback, is also presented for use in background-suppression and neural network applications. A new, low noise, ultra-low level signal readout technique, implemented by individually counting photo-electrons within the detection pixel, is presented. The output of each unit-cell is a digital word corresponding to the intensity of the photon flux, and the readout is noise free. This technique requires the use of unit-cell amplifiers that feature ultra-high-gain, low-power, self-biasing capability and noise in sub-electron levels. Both single-input and differential-input implementations of such amplifiers are investigated. A noise analysis technique is presented for analyzing sampled

  4. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    Science.gov (United States)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  5. Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

    2015-10-14

    Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

  6. Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-10-01

    Full Text Available Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

  7. A Two-Step A/D Conversion and Column Self-Calibration Technique for Low Noise CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Jaeyoung Bae

    2014-07-01

    Full Text Available In this paper, a 120 frames per second (fps low noise CMOS Image Sensor (CIS based on a Two-Step Single Slope ADC (TS SS ADC and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times than that of the Single Slope ADC (SS ADC. However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS. The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB.

  8. A CMOS power-efficient low-noise current-mode front-end amplifier for neural signal recording.

    Science.gov (United States)

    Wu, Chung-Yu; Chen, Wei-Ming; Kuo, Liang-Ting

    2013-04-01

    In this paper, a new current-mode front-end amplifier (CMFEA) for neural signal recording systems is proposed. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency below 0.5 Hz. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. The proposed CMFEA is designed and fabricated in 0.18-μm CMOS technology and the area of the core circuit is 0.076 mm(2). The measured high-pass cutoff frequency is as low as 0.3 Hz and the low-pass cutoff frequency is adjustable from 1 kHz to 10 kHz. The measured maximum current gain is 55.9 dB. The measured input-referred current noise density is 153 fA /√Hz , and the power consumption is 13 μW at 1-V power supply. The fabricated CMFEA has been successfully applied to the animal test for recording the seizure ECoG of Long-Evan rats.

  9. ALDO: A radiation-tolerant, low-noise, adjustable low drop-out linear regulator in 0.35 μm CMOS technology

    International Nuclear Information System (INIS)

    Carniti, P.; Cassina, L.; Gotti, C.; Maino, M.; Pessina, G.

    2016-01-01

    In this work we present ALDO, an adjustable low drop-out linear regulator designed in AMS 0.35 μm CMOS technology. It is specifically tailored for use in the upgraded LHCb RICH detector in order to improve the power supply noise for the front end readout chip (CLARO). ALDO is designed with radiation-tolerant solutions such as an all-MOS band-gap voltage reference and layout techniques aiming to make it able to operate in harsh environments like High Energy Physics accelerators. It is capable of driving up to 200 mA while keeping an adequate power supply filtering capability in a very wide frequency range from 10 Hz up to 100 MHz. This property allows us to suppress the noise and high frequency spikes that could be generated by a DC/DC regulator, for example. ALDO also shows a very low noise of 11.6 μV RMS in the same frequency range. Its output is protected with over-current and short detection circuits for a safe integration in tightly packed environments. Design solutions and measurements of the first prototype are presented.

  10. ALDO: A radiation-tolerant, low-noise, adjustable low drop-out linear regulator in 0.35 μm CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Carniti, P., E-mail: paolo.carniti@mib.infn.it [INFN, Sezione di Milano Bicocca, I-20126 Milano (Italy); Dipartimento di Fisica, Università di Milano Bicocca, I-20126 Milano (Italy); Cassina, L.; Gotti, C.; Maino, M.; Pessina, G. [INFN, Sezione di Milano Bicocca, I-20126 Milano (Italy); Dipartimento di Fisica, Università di Milano Bicocca, I-20126 Milano (Italy)

    2016-07-11

    In this work we present ALDO, an adjustable low drop-out linear regulator designed in AMS 0.35 μm CMOS technology. It is specifically tailored for use in the upgraded LHCb RICH detector in order to improve the power supply noise for the front end readout chip (CLARO). ALDO is designed with radiation-tolerant solutions such as an all-MOS band-gap voltage reference and layout techniques aiming to make it able to operate in harsh environments like High Energy Physics accelerators. It is capable of driving up to 200 mA while keeping an adequate power supply filtering capability in a very wide frequency range from 10 Hz up to 100 MHz. This property allows us to suppress the noise and high frequency spikes that could be generated by a DC/DC regulator, for example. ALDO also shows a very low noise of 11.6 μV RMS in the same frequency range. Its output is protected with over-current and short detection circuits for a safe integration in tightly packed environments. Design solutions and measurements of the first prototype are presented.

  11. ALDO: A radiation-tolerant, low-noise, adjustable low drop-out linear regulator in 0.35 μm CMOS technology

    Science.gov (United States)

    Carniti, P.; Cassina, L.; Gotti, C.; Maino, M.; Pessina, G.

    2016-07-01

    In this work we present ALDO, an adjustable low drop-out linear regulator designed in AMS 0.35 μm CMOS technology. It is specifically tailored for use in the upgraded LHCb RICH detector in order to improve the power supply noise for the front end readout chip (CLARO). ALDO is designed with radiation-tolerant solutions such as an all-MOS band-gap voltage reference and layout techniques aiming to make it able to operate in harsh environments like High Energy Physics accelerators. It is capable of driving up to 200 mA while keeping an adequate power supply filtering capability in a very wide frequency range from 10 Hz up to 100 MHz. This property allows us to suppress the noise and high frequency spikes that could be generated by a DC/DC regulator, for example. ALDO also shows a very low noise of 11.6 μV RMS in the same frequency range. Its output is protected with over-current and short detection circuits for a safe integration in tightly packed environments. Design solutions and measurements of the first prototype are presented.

  12. Designing charge-sensitive preamplifiers based on low-noise analog integrated circuits

    International Nuclear Information System (INIS)

    Agakhanyan, T.M.

    1998-01-01

    The methodology for designing charge-sensitive preamplifiers on the low-noise analog integral circuits, including all the stages: the mathematical synthesis with optimization of the intermediate function; the scheme-technical synthesis with parametric optimization of the scheme and analysis of draft projects with the parameter verification is presented. The designing is conducted on the basis of requirements for signal parameters and noise indices of the preamplifier. The system of automated designing of the charge-sensitive preamplifiers on the low-noise analog integral circuits is developed [ru

  13. A high-speed low-noise transimpedance amplifier in a 0.25 μm CMOS technology

    International Nuclear Information System (INIS)

    Anelli, Giovanni; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 kΩ, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO 2 ) without any degradation in the performance

  14. A high-speed low-noise transimpedance amplifier in a 0.25 {mu}m CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Anelli, Giovanni E-mail: giovanni.anelli@cern.ch; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-10-11

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 k{omega}, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO{sub 2}) without any degradation in the performance.

  15. Integrated low noise low power interface for neural bio-potentials recording and conditioning

    Science.gov (United States)

    Bottino, Emanuele; Martinoia, Sergio; Valle, Maurizio

    2005-06-01

    The recent progress in both neurobiology and microelectronics suggests the creation of new, powerful tools to investigate the basic mechanisms of brain functionality. In particular, a lot of efforts are spent by scientific community to define new frameworks devoted to the analysis of in-vitro cultured neurons. One possible approach is recording their spiking activity to monitor the coordinated cellular behaviour and get insights about neural plasticity. Due to the nature of neurons action-potentials, when considering the design of an integrated microelectronic-based recording system, a number of problems arise. First, one would desire to have a high number of recording sites (i.e. several hundreds): this poses constraints on silicon area and power consumption. In this regard, our aim is to integrate-through on-chip post-processing techniques-hundreds of bio-compatible microsensors together with CMOS standard-process low-power (i.e. some tenths of uW per channel) conditioning electronics. Each recording channel is provided with sampling electronics to insure synchronous recording so that, for example, cross-correlation between signals coming from different sites can be performed. Extra-cellular potentials are in the range of [50-150] uV, so a comparison in terms of noise-efficiency was carried out among different architectures and very low-noise pre-amplification electronics (i.e. less than 5 uVrms) was designed. As spikes measurements are made with respect to the voltage of a reference electrode, we opted for an AC-coupled differential-input preamplifier provided with band-pass filtering capability. To achieve this, we implemented large time-constant (up to seconds) integrated components in the preamp feedback path. Thus, we got rid also of random slow-drifting DC-offsets and common mode signals. The paper will present our achievements in the design and implementation of a fully integrated bio-abio interface to record neural spiking activity. In particular

  16. CMOS Integrated Carbon Nanotube Sensor

    International Nuclear Information System (INIS)

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-01-01

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  17. Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

    International Nuclear Information System (INIS)

    Zhang Mingming; Chen Zhongjian; Zhang Yacong; Lu Wengao; Ji Lijiu

    2010-01-01

    A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration. Continuous-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%. (authors)

  18. Multi-target electrochemical biosensing enabled by integrated CMOS electronics

    International Nuclear Information System (INIS)

    Rothe, J; Lewandowska, M K; Heer, F; Frey, O; Hierlemann, A

    2011-01-01

    An integrated electrochemical measurement system, based on CMOS technology, is presented, which allows the detection of several analytes in parallel (multi-analyte) and enables simultaneous monitoring at different locations (multi-site). The system comprises a 576-electrode CMOS sensor chip, an FPGA module for chip control and data processing, and the measurement laptop. The advantages of the highly versatile system are demonstrated by two applications. First, a label-free, hybridization-based DNA sensor is enabled by the possibility of large-scale integration in CMOS technology. Second, the detection of the neurotransmitter choline is presented by assembling the chip with biosensor microprobe arrays. The low noise level enables a limit of detection of, e.g., 0.3 µM choline. The fully integrated system is self-contained: it features cleaning, functionalization and measurement functions without the need for additional electrical equipment. With the power supplied by the laptop, the system is very suitable for on-site measurements

  19. Design of low noise class D amplifiers using an integrated filter

    International Nuclear Information System (INIS)

    Wang Haishi; Zhang Bo

    2012-01-01

    This paper investigates the noise sources in a single-ended class D amplifier (SECDA) and suggests corresponding ways to lower the noise. The total output noise could be expressed as a function of the gain and noises from different sources. According to the function, the bias voltage (V B ) is a primary noise source, especially for a SECDA with a large gain. A low noise SECDA is obtained by integrating a filter into the SECDA to lower the noise of the V B . The filter utilizes an active resister and an 80 pF capacitance to get a 3 Hz pole. A noise test and fast Fourier transform analysis show that the noise performance of this SECDA is the same as that of a SECDA with an external filter. (semiconductor integrated circuits)

  20. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  1. Latch-up in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Estreich, D.B.; Dutton, R.W.

    1978-04-01

    An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

  2. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  3. The CMOS Integration of a Power Inverter

    OpenAIRE

    Mannarino, Eric Francis

    2016-01-01

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this proce...

  4. CMOS integrated switching power converters

    CERN Document Server

    Villar-Pique, Gerard

    2011-01-01

    This book describes the structured design and optimization of efficient, energy processing integrated circuits. The approach is multidisciplinary, covering the monolithic integration of IC design techniques, power electronics and control theory. In particular, this book enables readers to conceive, synthesize, design and implement integrated circuits with high-density high-efficiency on-chip switching power regulators. Topics covered encompass the structured design of the on-chip power supply, efficiency optimization, IC-compatible power inductors and capacitors, power MOSFET switches and effi

  5. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Pikor, A.; Reiss, E.M.

    1980-01-01

    Substantial effort has been directed at radiation-hardening CMOS integrated circuits using various oxide processes. While most of these integrated circuits have been successful in demonstrating megarad hardness, further investigations have shown that the 'wet-oxide process' is most compatible with the RCA CD4000 Series process. This article describes advances in the wet-oxide process that have resulted in multimegarad hardness and yield to MIL-M-38510 screening requirements. The implementation of these advances into volume manufacturing is geared towards supplying devices for aerospace requirements such as the Defense Meterological Satellite program (DMSP) and the Global Positioning Satellite (GPS). (author)

  6. On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

    Directory of Open Access Journals (Sweden)

    Hongyi Mi

    2017-03-01

    Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

  7. Broadband image sensor array based on graphene-CMOS integration

    Science.gov (United States)

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  8. A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

    Science.gov (United States)

    2014-01-01

    ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

  9. Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

    Energy Technology Data Exchange (ETDEWEB)

    Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica; Tisa, Simone; Zappa, Franco [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy)

    2013-12-15

    We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

  10. The CMOS integration of a power inverter

    Science.gov (United States)

    Mannarino, Eric Francis

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this process using two topologies. The first is a cell-based switched-capacitor topology first presented by Ke Zou. The second is a novel topology that explores the advantage of using a bused input-output system, as in digital electronics. Simulations run on both topologies confirm the high-efficiency demonstrated in Zou’s process as well as the advantage the bus-based system has in output voltage levels.

  11. A 0.1-1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

    Science.gov (United States)

    Guo, Benqing; Chen, Jun; Chen, Hongpeng; Wang, Xuebing

    2018-01-01

    An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 μm CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8-3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13-18.9 and 24-40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

  12. Hybrid CMOS/Molecular Integrated Circuits

    Science.gov (United States)

    Stan, M. R.; Rose, G. S.; Ziegler, M. M.

    CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

  13. A GEM-TPC prototype with low-Noise highly integrated front-end electronics for linear collider studies

    CERN Document Server

    Kappler, Steffen; Kaminski, Jochen; Ledermann, Bernhard; Müller, Thomas; Ronan, Michael T; Ropelewski, Leszek; Sauli, Fabio; Settles, Ronald

    2004-01-01

    Connected to the linear collider project, studies on the readout of time projection chambers (TPCs) based on the gas electron multiplier (GEM) are ongoing. Higher granularity and intrinsically suppressed ion feedback are the major advantages of this technology. After a short discussion of these issues, we present the design of a small and very flexible TPC prototype, whose cylindrical drift volume can be equipped with endcaps of different gas detector types. An endcap with multi-GEM readout is currently set up and successfully operated with a low-noise highly integrated front-end electronics. We discuss results of measurements with this system in high intensity particle beams at CERN, where 99.3 plus or minus 0.2% single-pad-row efficiency could be achieved at an effective gain of 2.5 multiplied by 10**3 only, and spatial resolutions down to 63 plus or minus 3 mum could be demonstrated. Finally, these results are extrapolated to the high magnetic field in a linear collider TPC. 5 Refs.

  14. All-CMOS night vision viewer with integrated microdisplay

    Science.gov (United States)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  15. Low noise SQUIDS

    International Nuclear Information System (INIS)

    Waal, V.J. de.

    1983-01-01

    The design, fabrication and limitations of very sensitive SQUID magnetometers are described. The SQUID magnetometer is based on the Josephson effect. A very low-noise niobium SQUID is described. It is fabricated with ultra-small niobium junctions with an overlapping area smaller than 1 μm 2 . The photolithographic technique developed for its fabrication, is described. Also an integrated system with a SQUID and a first-order gradiometer on a single substrate is presented. Calculations of the resolution of a dc SQUID containing ideal Josephson junctions according to the RSJ model are presented including a parasitic capacitance. The usefulness of the fabricated SQUIDS as well as some remarks on their performance is considered. (Auth.)

  16. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    Science.gov (United States)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  17. CMOS and BiCMOS process integration and device characterization

    CERN Document Server

    El-Kareh, Badih

    2009-01-01

    Covers both the theoretical and practical aspects of modern silicon devices and the relationship between their electrical properties and processing conditions. This book also covers silicon devices and integrated process technologies. It discusses modern silicon devices, their characteristics, and interactions with process parameters.

  18. Design optimization of radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    1975-01-01

    Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

  19. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  20. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  1. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  2. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  3. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  4. Radiation response of high speed CMOS integrated circuits

    International Nuclear Information System (INIS)

    Yue, H.; Davison, D.; Jennings, R.F.; Lothongkam, P.; Rinerson, D.; Wyland, D.

    1987-01-01

    This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis

  5. A toroidal inductor integrated in a standard CMOS process

    DEFF Research Database (Denmark)

    Vandi, Luca; Andreani, Pietro; Temporiti, Enrico

    2007-01-01

    This paper presents a toroidal inductor integrated in a standard 0.13 um CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches...

  6. Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

    Science.gov (United States)

    Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

    2013-01-01

    The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

  7. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  8. A CMOS integrated timing discriminator circuit for fast scintillation counters

    International Nuclear Information System (INIS)

    Jochmann, M.W.

    1998-01-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t r ≥ 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal's amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range

  9. A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

    Science.gov (United States)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-01-01

    This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

  10. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  11. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design...... of the mass detector are presented showing that miniaturization of such cantilever based resonant devices leads to highly sensitive mass sensors, which have the potential to detect single molecules. The design of the readout circuitry used for the first electrical characterization of an integrated cantilever...... with CMOS circuitry is demonstrated. The electrical characterization of the device shows that the resonant behavior of the cantilever depends on the applied voltages, which corresponds to theory....

  12. Integrated CMOS sensor technologies for the CLIC tracker

    CERN Document Server

    AUTHOR|(SzGeCERN)754303

    2017-01-01

    Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear e+e- collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

  13. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Hughes, R.C.

    1977-01-01

    Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

  14. Transient-induced latchup in CMOS integrated circuits

    CERN Document Server

    Ker, Ming-Dou

    2009-01-01

    "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

  15. Microfabrication and Characterization of an Integrated 3-Axis CMOS-MEMS Accelerometer

    Directory of Open Access Journals (Sweden)

    Hongwei QU

    2007-10-01

    Full Text Available This paper reports the fabrication and characterization of a monolithically integrated 3-axis CMOS-MEMS accelerometer with a single proof mass. An improved microfabrication process has been developed to solve the structure overheating and particle contamination problems in the plasma etching processes of device fabrication. The whole device is made of bulk silicon except for some short thin films for electrical isolation, allowing large sensing capacitance and flat device structure. A low-noise, low-power amplifier is designed for each axis, which provides 40 dB on-chip amplification and consumes only 1 mW power. Quasi-static and dynamic characterization of the fabricated device has been performed. The measured sensitivities of the lateral- and z-axis accelerometers are 560 mV/g and 320 mV/g, respectively, which can be tuned by simply varying the amplitude of the modulation signal. The over-all noise floors of the lateral- and z-axis are 12 μg/ÖHz and 110 μg/ÖHz, respectively when tested at 200 Hz.

  16. Si light-emitting device in integrated photonic CMOS ICs

    Science.gov (United States)

    Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

    2017-07-01

    The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

  17. Precise Characterization and Multiobjective Optimization of Low Noise Amplifiers

    Directory of Open Access Journals (Sweden)

    J. Dobes

    2015-09-01

    Full Text Available Although practically all function blocks of the satellite navigation receivers are realized using the CMOS digital integrated circuits, it is appropriate to create a separate low noise antenna preamplifier based on a low noise pHEMT. Such an RF front end can be strongly optimized to attain a suitable tradeoff between the noise figure and transducer power gain. Further, as all the four principal navigation systems (GPS, GLONASS, Galileo, and COMPASS work in similar frequency bands (roughly from 1.1 to 1.7 GHz, it is reasonable to create the low noise preamplifier for all of them. In the paper, a sophisticated method of the amplifier design is suggested based on multiobjective optimization. A substantial improvement of a standard optimization method is also outlined to satisfy a uniform coverage of Pareto front. Moreover, for enhancing efficiency of many times repeated solutions of large linear systems during the optimization, a new modification of the Markowitz criterion is suggested compatible with fast modes of the LU factorization. Extraordinary attention was also given to the accuracy of modeling. First, an extraction of pHEMT model parameters was performed including its noise part, and several models were compared. The extraction was carried out by an original identification procedure based on a combination of metaheuristic and direct methods. Second, the equations of the passive elements (including transmission lines and T-splitters were carefully defined using frequency dispersion of their parameters as Q, ESR, etc. Third, an optimal selection of the operating point and essential passive elements was performed using the improved optimization method. Finally, the s-parameters and noise figure of the amplifier were measured, and stability and third-order intermodulation products were also checked.

  18. Post-irradiation effects in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Zietlow, T.C.; Barnes, C.E.; Morse, T.C.; Grusynski, J.S.; Nakamura, K.; Amram, A.; Wilson, K.T.

    1988-01-01

    The post-irradiation response of CMOS integrated circuits from three vendors has been measured as a function of temperature and irradiation bias. The author's have found that a worst-case anneal temperature for rebound testing is highly process dependent. At an anneal temperature of 80 0 C, the timing parameters of a 16K SRAM from vendor A quickly saturate at maximum values, and display no further changes at this temperature. At higher temperature, evidence for the anneal of interface state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is longer. CMOS/SOS integrated circuits (vendor B) were also examined, and showed similar behavior, except that the saturation value for the timing parameters was stable up to 105 0 C. After irradiation to 10 Mrad(Si), a 16K SRAM (vendor C) was annealed at 80 0 C. In contrast to the results from the vendor A SRAM, the access time decreased toward prerad values during the anneal. Another part irradiated in the same manner but annealed at room temperature showed a slight increase during the anneal

  19. Latch-up control in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Ochoa, A.; Dawes, W.; Estreich, D.; Packard, H.

    1979-01-01

    The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 μm p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 μm p-well) CMOS and indicates the extent of their applicability to VLSI designs

  20. An integrated CMOS high data rate transceiver for video applications

    International Nuclear Information System (INIS)

    Liang Yaping; Sun Lingling; Che Dazhi; Liang Cheng

    2012-01-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at −3 dBm output power. (semiconductor integrated circuits)

  1. Ultra-Low Noise Vertical Takeoff and Landing, or Development of an Uber Self-Flying, Helipad-Capable, Quiet V-ESTOL Personal Transporter Integrated Flight Demonstrator

    Data.gov (United States)

    National Aeronautics and Space Administration — Several aspects of this research are completely unique compared to prior attempts to achieve low noise vertical lift solutions, and are an artifact of the incredible...

  2. A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording

    Directory of Open Access Journals (Sweden)

    Marco Crescentini

    2016-05-01

    Full Text Available High-throughput screening (HTS using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i design of scalable microfluidic devices; (ii design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter.

  3. A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording.

    Science.gov (United States)

    Crescentini, Marco; Bennati, Marco; Saha, Shimul Chandra; Ivica, Josip; de Planque, Maurits; Morgan, Hywel; Tartagni, Marco

    2016-05-19

    High-throughput screening (HTS) using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM) is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i) design of scalable microfluidic devices; (ii) design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii) design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter.

  4. Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

    International Nuclear Information System (INIS)

    Takano, H.; Hosogi, K.; Kato, T.

    1995-01-01

    A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs

  5. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  6. Effect of CMOS Technology Scaling on Fully-Integrated Power Supply Efficiency

    OpenAIRE

    Pillonnet , Gaël; Jeanniot , Nicolas

    2016-01-01

    International audience; Integrating a power supply in the same die as the powered circuits is an appropriate solution for granular, fine and fast power management. To allow same-die co-integration, fully integrated DC-DC converters designed in the latest CMOS technologies have been greatly studied by academics and industrialists in the last decade. However, there is little study concerning the effects of the CMOS scaling on these particular circuits. To show the trends, this paper compares th...

  7. Fully integrated CMOS pixel detector for high energy particles

    International Nuclear Information System (INIS)

    Vanstraelen, G.; Debusschere, I.; Claeys, C.; Declerck, G.

    1989-01-01

    A novel type of position and energy sensitive, monolithic pixel array with integrated readout electronics is proposed. Special features of the design are a reduction of the number of output channels and of the amount of output data, and the use of transistors on the high resistivity silicon. The number of output channels for the detector array is reduced by handling in parallel a number of pixels, chosen as a function of the time resolution required for the system, and by the use of an address decoder. A further reduction of data is achieved by reading out only those pixels which have been activated. The pixel detector circuit will be realized in a 3 μm p-well CMOS process, which is optimized for the full integration of readout electronics and detector diodes on high resistivity Si. A retrograde well is formed by means of a high energy implantation, followed by the appropriate temperature steps. The optimization of the well shape takes into account the high substrate bias applied during the detector operation. The design is largely based on the use of MOS transistors on the high resistivity silicon itself. These have proven to perform as well as transistors on standard doped substrate. The basic building elements as well as the design strategy of the integrated pixel detector are presented in detail. (orig.)

  8. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

  9. Design of low noise imaging system

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for low noise imaging system under the mode of global shutter, a complete imaging system is designed based on the SCMOS (Scientific CMOS) image sensor CIS2521F. The paper introduces hardware circuit and software system design. Based on the analysis of key indexes and technologies about the imaging system, the paper makes chips selection and decides SCMOS + FPGA+ DDRII+ Camera Link as processing architecture. Then it introduces the entire system workflow and power supply and distribution unit design. As for the software system, which consists of the SCMOS control module, image acquisition module, data cache control module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The imaging experimental results show that the imaging system exhibits a 2560*2160 pixel resolution, has a maximum frame frequency of 50 fps. The imaging quality of the system satisfies the requirement of the index.

  10. Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

    Science.gov (United States)

    Li, Lin; Yin, Heyu; Mason, Andrew J

    2018-04-01

    The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

  11. 1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

    Science.gov (United States)

    Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

    2018-04-01

    In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

  12. Integrated CMOS dew point sensors for relative humidity measurement

    Science.gov (United States)

    Savalli, Nicolo; Baglio, Salvatore; Castorina, Salvatore; Sacco, Vincenzo; Tringali, Cristina

    2004-07-01

    This work deals with the development of integrated relative humidity dew point sensors realized by adopting standard CMOS technology for applications in various fields. The proposed system is composed by a suspended plate that is cooled by exploiting integrated Peltier cells. The cold junctions of the cells have been spread over the plate surface to improve the homogeneity of the temperature distribution over its surface, where cooling will cause the water condensation. The temperature at which water drops occur, named dew point temperature, is a function of the air humidity. Measurement of such dew point temperature and the ambient temperature allows to know the relative humidity. The detection of water drops is achieved by adopting a capacitive sensing strategy realized by interdigited fixed combs, composed by the upper layer of the adopted process. Such a capacitive sensor, together with its conditioning circuit, drives a trigger that stops the cooling of the plate and enables the reading of the dew point temperature. Temperature measurements are achieved by means of suitably integrated thermocouples. The analytical model of the proposed system has been developed and has been used to design a prototype device and to estimate its performances. In such a prototype, the thermoelectric cooler is composed by 56 Peltier cells, made by metal 1/poly 1 junctions. The plate has a square shape with 200 μm side, and it is realized by exploiting the oxide layers. Starting from the ambient temperature a temperature variation of ΔT = 15 K can be reached in 10 ms thus allowing to measure a relative humidity greater than 40%.

  13. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  14. A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

    Science.gov (United States)

    Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

    2013-03-01

    Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

  15. A Low Noise Electronic Circuit

    NARCIS (Netherlands)

    Annema, Anne J.; Leenaerts, Dominicus M.W.; de Vreede, Petrus W.H.

    2002-01-01

    An electronic circuit, which can be used as a Low Noise Amplifier (LNA), comprises two complementary Field Effect Transistors (M1, M2; M5, M6), each having a gate, a source and a drain. The gates are connected together as a common input terminal, and the drains are connected together as a

  16. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

    Science.gov (United States)

    Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

    2017-02-14

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  17. Integrated imaging sensor systems with CMOS active pixel sensor technology

    Science.gov (United States)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  18. First experimental results on CMOS Integrated Nickel Electroplated Resonators

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Hansen, Ole

    2004-01-01

    This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation of the electri...

  19. Temperature Sensors Integrated into a CMOS Image Sensor

    NARCIS (Netherlands)

    Abarca Prouza, A.N.; Xie, S.; Markenhof, Jules; Theuwissen, A.J.P.

    2017-01-01

    In this work, a novel approach is presented for measuring relative temperature variations inside the pixel array of a CMOS image sensor itself. This approach can give important information when compensation for dark (current) fixed pattern noise (FPN) is needed. The test image sensor consists of

  20. A scalable neural chip with synaptic electronics using CMOS integrated memristors

    International Nuclear Information System (INIS)

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-01-01

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

  1. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

    Science.gov (United States)

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-12-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

  2. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Science.gov (United States)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  3. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  4. Latch-up control in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Ochoa, A. Jr.; Estreich, D.B.; Dawes, W.R. Jr.

    1979-01-01

    The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed

  5. An analysis of latch-up characteristics and latch-up windows in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Xu Xianguo; Yang Huaimin

    2004-01-01

    Because of topology's complexity, there may be several potential parasitic latch-up paths in a CMOS integrated circuit. All of the latch-up paths may have an effect on each other or one another due to different triggering dose rate, holding voltage and holding current and then one or more latch-up windows may appear. After we analyze the latch-up characteristic of CMOS integrated circuits in detail, a 'three-path' latch-up model is developed and used to explain the latch-up window phenomena reasonably. (authors)

  6. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  7. CMOS-compatible high-voltage integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Parpia, Z

    1988-01-01

    Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

  8. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    International Nuclear Information System (INIS)

    Gao Tongqiang; Zhang Chun; Chi Baoyong; Wang Zhihua

    2009-01-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  9. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Energy Technology Data Exchange (ETDEWEB)

    Gao Tongqiang [Department of Electronics, Tsinghua University, Beijing 100084 (China); Zhang Chun; Chi Baoyong; Wang Zhihua, E-mail: gtq03@mails.tsinghua.edu.c [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2009-06-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-mum CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  10. A high rate, low noise, x-ray silicon strip detector system

    International Nuclear Information System (INIS)

    Ludewigt, B.; Jaklevic, J.; Kipnis, I.; Rossington, C.; Spieler, H.

    1993-11-01

    An x-ray detector system, based on a silicon strip detector wire-bonded to a low noise charge-senstive amplifier integrated circuit, has been developed for synchrotron radiation experiments which require very high count rates and good energy resolution. Noise measurements and x-ray spectra were taken using a 6 mm long, 55 μm pitch strip detector in conjunction with a prototype 16-channel charge-sensitive preamplifier, both fabricated using standard 1.2 μm CMOS technology. The detector system currently achieves an energy resolution of 350 eV FWHM at 5.9 key, 2 μs peaking time, when cooled to -5 degree C

  11. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    Science.gov (United States)

    Aull, Brian

    2016-04-08

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  12. A CMOS integrated pulse mode alpha-particle counter for application in radon monitoring

    International Nuclear Information System (INIS)

    Ahmed, A.; Walkey, D.J.; Tarr, N.G.

    1997-01-01

    A custom integrated circuit for detecting alpha particles for application in the monitoring of radon has been designed and tested. The design uses the reverse-biased well to a substrate capacitance of a p-n junction in a conventional CMOS process as a sense capacitor for incident alpha particles. A simple CMOS inverter is used as an analog amplifier to detect the small potential change induced by an alpha-particle strike on the sense capacitor. The design was implemented in a 1.2-microm conventional CMOS process with a sense capacitor area of 110 microm 2 . Tests carried out under vacuum conditions using a calibrated 241 Am alpha-particle source showed an output voltage swing of ≥2.0 V for an alpha event. The detector is also shown to have good immunity to noise and high-quantum efficiency for alpha particles

  13. A CMOS 128-APS linear array integrated with a LVOF for highsensitivity and high-resolution micro-spectrophotometry

    NARCIS (Netherlands)

    Liu, C.; Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

    2010-01-01

    A linear array of 128 Active Pixel Sensors has been developed in standard CMOS technology and a Linear Variable Optical Filter (LVOF) is added using CMOS-compatible post-process, resulting in a single chip highly-integrated highresolution microspectrometer. The optical requirements imposed by the

  14. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    International Nuclear Information System (INIS)

    Contopanagos, Harry

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  15. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    Energy Technology Data Exchange (ETDEWEB)

    Contopanagos, Harry [Institute for Microelectronics, NCSR ' Demokritos' , PO Box 60228, GR-153 10 Aghia Paraskevi, Athens (Greece)

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 {mu}m. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  16. Integrated X-band FMCW front-end in SiGe BiCMOS

    NARCIS (Netherlands)

    Suijker, Erwin; de Boer, Lex; Visser, Guido; van Dijk, Raymond; Poschmann, Michael; van Vliet, Frank Edward

    2010-01-01

    An integrated X-band FMCW front-end is reported. The front-end unites the core functionality of an FMCW transmitter and receiver in a 0.25 μm SiGe BiCMOS process. The chip integrates a PLL for the carrier generation, and single-side band and image-reject mixers for up- and down-conversion of the

  17. Wideband CMOS low noise amplifier including an active balun

    NARCIS (Netherlands)

    Blaakmeer, S.C.; Klumperink, Eric A.M.; Leenaerts, D.M.W.; Nauta, Bram

    2007-01-01

    An inductorless LNA with active balun is proposed for multi-standard radio applications between 100MHz and 6GHz [1]. It exploits a combination of a common-gate (CG) stage and an common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and

  18. 3D integration of planar crossbar memristive devices with CMOS substrate

    International Nuclear Information System (INIS)

    Lin, Peng; Pi, Shuang; Xia, Qiangfei

    2014-01-01

    Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moiré pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing. (paper)

  19. Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

    Science.gov (United States)

    Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

    Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

  20. Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

    International Nuclear Information System (INIS)

    Estreich, D.B.

    1978-11-01

    A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

  1. Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

    Science.gov (United States)

    Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

    2014-03-01

    We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

  2. Superconducting low-noise oscillator

    International Nuclear Information System (INIS)

    Riebman, L.

    1992-01-01

    This patent describes a cryogenic oscillator having low phase noise and low noise. It comprises resonant circuit means formed of superconducting material for generating a signal at a desired frequency; linear amplifier means electrically connected to the resonant circuit means at first and second locations thereon; limiter means electrically connected to the resonant circuit means at a third location thereon; and buffer amplifier means for applying the signal generated by the resonant circuit means to a load and electrically connected to the resonant circuit means at a fourth location thereon. This patent also describes a method of minimizing phase noise and 1/f noise in an oscillator circuit of the type having a resonant circuit driving a load and at least a linear amplifier connected to the resonant circuit defining a closed loop having a loop gain greater than unity, and having a limiter for stabilizing the oscillator. It comprises connecting between the resonant circuit and the load a buffer amplifier and connecting the linear amplifier and the buffer amplifier to the resonant circuit

  3. A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

    International Nuclear Information System (INIS)

    Lei Qianqian; Lin Min; Shi Yin

    2013-01-01

    A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with an integrated automatic gain control (AGC) loop for a short-distance receiver are implemented in SMIC 0.13 μm CMOS technology. The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within ±0.5 dB for an input power from −65 to −8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA (I and Q paths) from a 1.2 V supply. Auto LNA gain mode selection with a combined RSSI function is also presented. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics. (semiconductor integrated circuits)

  4. Ultra-low crosstalk, CMOS compatible waveguide crossings for densely integrated photonic interconnection networks.

    Science.gov (United States)

    Jones, Adam M; DeRose, Christopher T; Lentine, Anthony L; Trotter, Douglas C; Starbuck, Andrew L; Norwood, Robert A

    2013-05-20

    We explore the design space for optimizing CMOS compatible waveguide crossings on a silicon photonics platform. This paper presents simulated and experimental excess loss and crosstalk suppression data for vertically integrated silicon nitride over silicon-on-insulator waveguide crossings. Experimental results show crosstalk suppression exceeding -49/-44 dB with simulation results as low as -65/-60 dB for the TE/TM mode in a waveguide crossing with a 410 nm vertical gap.

  5. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  6. 3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer

    Directory of Open Access Journals (Sweden)

    Sho Asano

    2017-10-01

    Full Text Available This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS with capacitive sensing circuits on a low temperature cofired ceramic (LTCC interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

  7. 3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

    Science.gov (United States)

    Asano, Sho; Muroyama, Masanori; Nakayama, Takahiro; Hata, Yoshiyuki; Nonomura, Yutaka; Tanaka, Shuji

    2017-10-25

    This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

  8. Titanium dioxide nanowire sensor array integration on CMOS platform using deterministic assembly.

    Science.gov (United States)

    Gall, Oren Z; Zhong, Xiahua; Schulman, Daniel S; Kang, Myungkoo; Razavieh, Ali; Mayer, Theresa S

    2017-06-30

    Nanosensor arrays have recently received significant attention due to their utility in a wide range of applications, including gas sensing, fuel cells, internet of things, and portable health monitoring systems. Less attention has been given to the production of sensor platforms in the μW range for ultra-low power applications. Here, we discuss how to scale the nanosensor energy demand by developing a process for integration of nanowire sensing arrays on a monolithic CMOS chip. This work demonstrates an off-chip nanowire fabrication method; subsequently nanowires link to a fused SiO 2 substrate using electric-field assisted directed assembly. The nanowire resistances shown in this work have the highest resistance uniformity reported to date of 18%, which enables a practical roadmap towards the coupling of nanosensors to CMOS circuits and signal processing systems. The article also presents the utility of optimizing annealing conditions of the off-chip metal-oxides prior to CMOS integration to avoid limitations of thermal budget and process incompatibility. In the context of the platform demonstrated here, directed assembly is a powerful tool that can realize highly uniform, cross-reactive arrays of different types of metal-oxide nanosensors suited for gas discrimination and signal processing systems.

  9. Integration issues of high-k and metal gate into conventional CMOS technology

    International Nuclear Information System (INIS)

    Song, S.C.; Zhang, Z.; Huffman, C.; Bae, S.H.; Sim, J.H.; Kirsch, P.; Majhi, P.; Moumen, N.; Lee, B.H.

    2006-01-01

    Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO 2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility

  10. CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

    International Nuclear Information System (INIS)

    Sawadsaringkarn, Y; Kimura, H; Maezawa, Y; Nakajima, A; Kobayashi, T; Sasagawa, K; Noda, T; Tokuda, T; Ohta, J

    2012-01-01

    A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

  11. A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng, E-mail: xxd@tju.edu.c [School of Electronic Information Engineering, Tianjin University, Tianjin 300072 (China)

    2009-12-15

    A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 {mu}m EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10{sup -9}. The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

  12. A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

    International Nuclear Information System (INIS)

    Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng

    2009-01-01

    A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10 -9 . The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

  13. Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

    International Nuclear Information System (INIS)

    Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.; Tinel, F.

    1998-01-01

    Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC

  14. A CMOS Integrating Amplifier for the PHENIX Ring Imaging Cherenkov detector

    International Nuclear Information System (INIS)

    Wintenberg, A.L.; Jones, J.P. Jr.; Young, G.R.; Moscone, C.G.

    1997-11-01

    A CMOS integrating amplifier has been developed for use in the PHENIX Ring Imaging Cherenkov (RICH) detector. The amplifier, consisting of a charge-integrating amplifier followed by a variable gain amplifier (VGA), is an element of a photon measurement system comprising a photomultiplier tube, a wideband, gain of 10 amplifier, the integrating amplifier, and an analog memory followed by an ADC and double correlated sampling implemented in software. The integrating amplifier is designed for a nominal full scale input of 160 pC with a gain of 20 mV/pC and a dynamic range of 1000:1. The VGA is used for equalizing gains prior to forming analog sums for trigger purposes. The gain of the VGA is variable over a 3:1 range using a 5 bits digital control, and the risetime is held to approximately 20 ns using switched compensation in the VGA. Details of the design and results from several prototype devices fabricated in 1.2 microm Orbit CMOS are presented. A complete noise analysis of the integrating amplifier and the correlated sampling process is included as well as a comparison of calculated, simulated and measured results

  15. A CMOS Integrating Amplifier for the PHENIX Ring Imaging Cherenkov detector

    Energy Technology Data Exchange (ETDEWEB)

    Wintenberg, A.L.; Jones, J.P. Jr.; Young, G.R. [Oak Ridge National Lab., TN (United States); Moscone, C.G. [Tennessee Univ., Knoxville, TN (United States)

    1997-11-01

    A CMOS integrating amplifier has been developed for use in the PHENIX Ring Imaging Cherenkov (RICH) detector. The amplifier, consisting of a charge-integrating amplifier followed by a variable gain amplifier (VGA), is an element of a photon measurement system comprising a photomultiplier tube, a wideband, gain of 10 amplifier, the integrating amplifier, and an analog memory followed by an ADC and double correlated sampling implemented in software. The integrating amplifier is designed for a nominal full scale input of 160 pC with a gain of 20 mV/pC and a dynamic range of 1000:1. The VGA is used for equalizing gains prior to forming analog sums for trigger purposes. The gain of the VGA is variable over a 3:1 range using a 5 bits digital control, and the risetime is held to approximately 20 ns using switched compensation in the VGA. Details of the design and results from several prototype devices fabricated in 1.2 {micro}m Orbit CMOS are presented. A complete noise analysis of the integrating amplifier and the correlated sampling process is included as well as a comparison of calculated, simulated and measured results.

  16. Characterization of 13 and 30 mum thick hydrogenated amorphous silicon diodes deposited over CMOS integrated circuits for particle detection application

    CERN Document Server

    Despeisse, M; Commichau, S C; Dissertori, G; Garrigos, A; Jarron, P; Miazza, C; Moraes, D; Shah, A; Wyrsch, N; Viertel, Gert M; 10.1016/j.nima.2003.11.022

    2004-01-01

    We present the experimental results obtained with a novel monolithic silicon pixel detector which consists in depositing a n-i-p hydrogenated amorphous silicon (a-Si:H) diode straight above the readout ASIC (this technology is called Thin Film on ASIC, TFA). The characterization has been performed on 13 and 30mum thick a-Si:H films deposited on top of an ASIC containing a linear array of high- speed low-noise transimpedance amplifiers designed in a 0.25mum CMOS technology. Experimental results presented have been obtained with a 600nm pulsed laser. The results of charge collection efficiency and charge collection speed of these structures are discussed.

  17. Low noise InP-based MMIC receivers for W-band

    Science.gov (United States)

    Leonard, Regis F.

    1991-01-01

    A program to develop a monolithic W-band low noise amplifier (a critical element in any W-band communications, sensors, or radar application) is described. Goals of the program include a completely monolithic low noise amplifier, less than a 3.5 dB noise figure, and a monolithic mixer suitable for integration with the LNA.

  18. Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology

    Science.gov (United States)

    Muhamad, M.; Soin, N.; Ramiah, H.

    2018-03-01

    This paper presents about design and optimization of CMOS active inductor integrated circuit. This active inductor implements using Silterra 0.13μm technology and simulated using Cadence Virtuoso and Spectre RF. The center frequency for this active inductor is at 2.4 GHz which follow IEEE 802.11 b/g/n standard. To reduce the chip size of silicon, active inductor is used instead of passive inductor at low noise amplifier LNA circuit. This inductor test and analyse by low noise amplifier circuit. Comparison between active with passive inductor based on LNA circuit has been performed. Result shown that the active inductor has significantly reduce the chip size with 73 % area without sacrificing the noise figure and gain of LNA which is the most important criteria in LNA. The best low noise amplifier provides a power gain (S21) of 20.7 dB with noise figure (NF) of 2.1dB.

  19. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Directory of Open Access Journals (Sweden)

    Chris R. Bowen

    2011-05-01

    Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  20. Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

    2018-05-01

    Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

  1. Detecting single-abasic residues within a DNA strand immobilized in a biological nanopore using an integrated CMOS sensor.

    Science.gov (United States)

    Kim, Jungsuk; Maitra, Raj D; Pedrotti, Ken; Dunbar, William B

    2013-02-01

    In this paper, we demonstrate the application of a novel current-measuring sensor (CMS) customized for nanopore applications. The low-noise CMS is fabricated in a 0.35μm CMOS process and is implemented in experiments involving DNA captured in an α-hemolysin (α-HL) nanopore. Specifically, the CMS is used to build a current amplitude map as a function of varying positions of a single-abasic residue within a homopolymer cytosine single-stranded DNA (ssDNA) that is captured and held in the pore. Each ssDNA is immobilized using a biotin-streptavidin linkage. Five different DNA templates are measured and compared: one all-cytosine ssDNA, and four with a single-abasic residue substitution that resides in or near the ~1.5nm aperture of the α-HL channel when the strand is immobilized. The CMOS CMS is shown to resolves the ~5Å displacements of the abasic residue within the varying templates. The demonstration represents an advance in application-specific circuitry that is optimized for small-footprint nanopore applications, including genomic sequencing.

  2. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

    NARCIS (Netherlands)

    Lee, M.J.; Youn, J.S.; Park, K.Y.; Choi, W.Y.

    2014-01-01

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche

  3. Nonlinearly stacked low noise turbofan stator

    Science.gov (United States)

    Schuster, William B. (Inventor); Nolcheff, Nick A. (Inventor); Gunaraj, John A. (Inventor); Kontos, Karen B. (Inventor); Weir, Donald S. (Inventor)

    2009-01-01

    A nonlinearly stacked low noise turbofan stator vane having a characteristic curve that is characterized by a nonlinear sweep and a nonlinear lean is provided. The stator is in an axial fan or compressor turbomachinery stage that is comprised of a collection of vanes whose highly three-dimensional shape is selected to reduce rotor-stator and rotor-strut interaction noise while maintaining the aerodynamic and mechanical performance of the vane. The nonlinearly stacked low noise turbofan stator vane reduces noise associated with the fan stage of turbomachinery to improve environmental compatibility.

  4. A CMOS pressure sensor with integrated interface for passive RFID applications

    International Nuclear Information System (INIS)

    Deng, Fangming; He, Yigang; Wu, Xiang; Fu, Zhihui

    2014-01-01

    This paper presents a CMOS pressure sensor with integrated interface for passive RFID sensing applications. The pressure sensor consists of three parts: top electrode, dielectric layer and bottom electrode. The dielectric layer consists of silicon oxide and an air gap. The bottom electrode is made of polysilicon. The gap is formed by sacrificial layer release and the Al vapor process is used to seal the gap and form the top electrode. The sensor interface is based on phase-locked architecture, which allows the use of fully digital blocks. The proposed pressure sensor and interface is fabricated in a 0.18 μm CMOS process. The measurement results show the pressure sensor achieves excellent linearity with a sensitivity of 1.2 fF kPa −1 . The sensor interface consumes only 1.1 µW of power at 0.5 V voltage supply, which is at least an order of magnitude better than state-of-the-art designs. (paper)

  5. A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    Directory of Open Access Journals (Sweden)

    Daniel Pacheco Bautista

    2007-09-01

    Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

  6. A CMOS integrated voltage and power efficient AC/DC converter for energy harvesting applications

    International Nuclear Information System (INIS)

    Peters, Christian; Ortmanns, Maurits; Manoli, Yiannos; Spreemann, Dirk

    2008-01-01

    In this paper, a fully CMOS integrated active AC/DC converter for energy harvesting applications is presented. The rectifier is realized in a standard 0.35 µm CMOS process without special process options. It works as a full wave rectifier and can be separated into two stages—one passive and one active. The active part is powered from the storage capacitor and consumes about 600 nA at 2 V supply. The input voltage amplitude range is between 1.25 and 3.75 V, and the operating frequency range is from 1 Hz to as much as several 100 kHz. The series voltage drop over the rectifier is less than 20 mV. Measurements in combination with an electromagnetic harvester show a significant increase in the achievable output voltage and power compared to a common, discrete Schottky diode rectifier. The measured efficiency of the rectifier is over 95%. Measurements show a negligible temperature influence on the output voltage between −40 °C and +125 °C

  7. A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

    Science.gov (United States)

    Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

    2014-10-01

    This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

  8. Programmable, very low noise current source

    Science.gov (United States)

    Scandurra, G.; Cannatà, G.; Giusi, G.; Ciofi, C.

    2014-12-01

    We propose a new approach for the realization of very low noise programmable current sources mainly intended for application in the field of low frequency noise measurements. The design is based on a low noise Junction Field Effect Transistor (JFET) acting as a high impedance current source and programmability is obtained by resorting to a low noise, programmable floating voltage source that allows to set the sourced current at the desired value. The floating voltage source is obtained by exploiting the properties of a standard photovoltaic MOSFET driver. Proper filtering and a control network employing super-capacitors allow to reduce the low frequency output noise to that due to the low noise JFET down to frequencies as low as 100 mHz while allowing, at the same time, to set the desired current by means of a standard DA converter with an accuracy better than 1%. A prototype of the system capable of supplying currents from a few hundreds of μA up to a few mA demonstrates the effectiveness of the approach we propose. When delivering a DC current of about 2 mA, the power spectral density of the current fluctuations at the output is found to be less than 25 pA/√Hz at 100 mHz and less than 6 pA/√Hz for f > 1 Hz, resulting in an RMS noise in the bandwidth from 0.1 to 10 Hz of less than 14 pA.

  9. Development of readout electronics for monolithic integration with diode strip detectors

    International Nuclear Information System (INIS)

    Hosticka, B.J.; Wrede, M.; Zimmer, G.; Kemmer, J.; Hofmann, R.; Lutz, G.

    1984-03-01

    Parallel in - serial out analog readout electronics integrated with silicon strip detectors will bring a reduction of two orders of magnitude in external electronics. The readout concept and the chosen CMOS technology solve the basic problem of low noise and low power requirements. A hybrid solution is an intermediate step towards the final goal of monolithic integration of detector and electronics. (orig.)

  10. Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

    International Nuclear Information System (INIS)

    Kim, Y; Pham, C; Chang, J P

    2015-01-01

    This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal–oxide–semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the

  11. W-band InP based HEMT MMIC low noise amplifiers

    Science.gov (United States)

    Lin, K. Y.; Tang, Y. L.; Wang, H.; Gaier, T.; Gough, R. G.; Sinclair, M.

    2002-01-01

    This paper presents the designs and measurement results of a three-stage and a four-stage W-band monolithic microwave integrated circuits (MMIC) including a three-stage and a four-stage low noise amplifiers.

  12. Effects of plasma-deposited silicon nitride passivation on the radiation hardness of CMOS integrated circuits

    International Nuclear Information System (INIS)

    Clement, J.J.

    1980-01-01

    The use of plasma-deposited silicon nitride as a final passivation over metal-gate CMOS integrated circuits degrades the radiation hardness of these devices. The hardness degradation is manifested by increased radiation-induced threshold voltage shifts caused principally by the charging of new interface states and, to a lesser extent, by the trapping of holes created upon exposure to ionizing radiation. The threshold voltage shifts are a strong function of the deposition temperature, and show very little dependence on thickness for films deposited at 300 0 C. There is some correlation between the threshold voltage shifts and the hydrogen content of the PECVD silicon nitride films used as the final passivation layer as a function of deposition temperature. The mechanism by which the hydrogen contained in these films may react with the Si/SiO 2 interface is not clear at this point

  13. Integrating Metal-Oxide-Decorated CNT Networks with a CMOS Readout in a Gas Sensor

    Directory of Open Access Journals (Sweden)

    Suhwan Kim

    2012-02-01

    Full Text Available We have implemented a tin-oxide-decorated carbon nanotube (CNT network gas sensor system on a single die. We have also demonstrated the deposition of metallic tin on the CNT network, its subsequent oxidation in air, and the improvement of the lifetime of the sensors. The fabricated array of CNT sensors contains 128 sensor cells for added redundancy and increased accuracy. The read-out integrated circuit (ROIC was combined with coarse and fine time-to-digital converters to extend its resolution in a power-efficient way. The ROIC is fabricated using a 0.35 µm CMOS process, and the whole sensor system consumes 30 mA at 5 V. The sensor system was successfully tested in the detection of ammonia gas at elevated temperatures.

  14. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

    Science.gov (United States)

    Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

    2014-02-10

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

  15. Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

    Science.gov (United States)

    Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

    2017-05-01

    Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive

  16. EUDP Project: Low Noise Airfoil - Final Report

    DEFF Research Database (Denmark)

    This document summarizes the scientific results achieved during the EUDP-funded project `Low-Noise Airfoil'. The goals of this project are, on one side to develop a measurement technique that permits the evaluation of trailing edge noise in a classical aerodynamic wind tunnel, and on the other side...... to develop and implement a design procedure to manufacture airfoil profiles with low noise emission. The project involved two experimental campaigns: one in the LM Wind Power wind tunnel, a classical aerodynamic wind tunnel, in Lunderskov (DK), the second one in the Virginia Tech Stability Wind Tunnel....... In particular, the so-called TNO trailing edge noise model could be significantly improved by introducing turbulence anisotropy in its formulation, as well as the influence of the boundary layer mean pressure gradient. This two characteristics are inherent to airfoil flows but were neglected in the original...

  17. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Drago Strle

    2015-07-01

    Full Text Available This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC. The DSP is currently implemented on FPGA.

  18. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

    Science.gov (United States)

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-07-22

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

  19. A Low Noise Amplifier for Neural Spike Recording Interfaces

    Directory of Open Access Journals (Sweden)

    Jesus Ruiz-Amaya

    2015-09-01

    Full Text Available This paper presents a Low Noise Amplifier (LNA for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz–7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.

  20. Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

    Science.gov (United States)

    Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

    2018-04-01

    The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

  1. Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom

    Directory of Open Access Journals (Sweden)

    Hang Song

    2017-01-01

    Full Text Available A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

  2. Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers

    International Nuclear Information System (INIS)

    Ratti, L.; Gaioni, L.; Manghisoni, M.; Re, V.; Traversi, G.

    2010-01-01

    A fine pitch, deep N-well CMOS monolithic active pixel sensor (DNW CMOS MAPS) with sparsified readout architecture and time stamping capabilities has been designed in a vertical integration (3D) technology. In this process, two 130 nm CMOS wafers are face-to-face bonded by means of thermo-compression techniques ensuring both the mechanical stability of the structure and the electrical interconnection between circuits belonging to different layers. This 3D design represents the evolution of a DNW monolithic sensor already fabricated in a planar 130 nm CMOS technology in view of applications to the vertex detector of the International Linear Collider (ILC). The paper is devoted to discussing the main design features and expected performance of the 3D DNW MAPS. Besides describing the front-end circuits and the general architecture of the detector, the work also provides some results from calculations and Monte Carlo device simulations comparing the old 2D solution with the new 3D one and illustrating the attainable detection efficiency improvements.

  3. Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers

    Energy Technology Data Exchange (ETDEWEB)

    Ratti, L., E-mail: lodovico.ratti@unipv.i [Universita di Pavia, Dipartimento di Elettronica, Via Ferrata 1, I-27100 Pavia (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy); Gaioni, L. [Universita di Pavia, Dipartimento di Elettronica, Via Ferrata 1, I-27100 Pavia (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy); Manghisoni, M.; Re, V.; Traversi, G. [Universita di Bergamo, Dipartimento di Ingegneria Industriale, Via Marconi 5, I-24044 Dalmine (Bulgaria) (Italy); INFN, Sezione di Pavia, Via Bassi 6, I-27100 Pavia (Italy)

    2010-12-11

    A fine pitch, deep N-well CMOS monolithic active pixel sensor (DNW CMOS MAPS) with sparsified readout architecture and time stamping capabilities has been designed in a vertical integration (3D) technology. In this process, two 130 nm CMOS wafers are face-to-face bonded by means of thermo-compression techniques ensuring both the mechanical stability of the structure and the electrical interconnection between circuits belonging to different layers. This 3D design represents the evolution of a DNW monolithic sensor already fabricated in a planar 130 nm CMOS technology in view of applications to the vertex detector of the International Linear Collider (ILC). The paper is devoted to discussing the main design features and expected performance of the 3D DNW MAPS. Besides describing the front-end circuits and the general architecture of the detector, the work also provides some results from calculations and Monte Carlo device simulations comparing the old 2D solution with the new 3D one and illustrating the attainable detection efficiency improvements.

  4. Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit

    Institute of Scientific and Technical Information of China (English)

    Ding Lili; Guo Hongxia; Chen Wei; Fan Ruyu

    2012-01-01

    Radiation-induced inter-device leakage is studied using an analytical model and TCAD simulation.There were some different opinions in understanding the process of defect build-up in trench oxide and parasitic leakage path turning on from earlier studies.To reanalyze this problem and make it beyond argument,every possible variable is considered using theoretical analysis,not just the change of electric field or oxide thickness independently.Among all possible inter-device leakage paths,parasitic structures with N-well as both drain and source are comparatively more sensitive to the total dose effect when a voltage discrepancy exists between the drain and source region.Since N-well regions are commonly connected to the same power supply,these kinds of structures will not be a problem in a real CMOS integrated circuit.Generally speaking,conduction paths of inter-device leakage existing in a real integrated circuit and under real electrical circumstances are not very sensitive to the total ionizing dose effect.

  5. A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

    Directory of Open Access Journals (Sweden)

    Chang-Hung Lee

    2014-05-01

    Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

  6. A low-power integrated humidity CMOS sensor by printing-on-chip technology.

    Science.gov (United States)

    Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

    2014-05-23

    A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

  7. Integrated Amorphous Silicon p-i-n Temperature Sensor for CMOS Photonics

    Directory of Open Access Journals (Sweden)

    Sandro Rao

    2016-01-01

    Full Text Available Hydrogenated amorphous silicon (a-Si:H shows interesting optoelectronic and technological properties that make it suitable for the fabrication of passive and active micro-photonic devices, compatible moreover with standard microelectronic devices on a microchip. A temperature sensor based on a hydrogenated amorphous silicon p-i-n diode integrated in an optical waveguide for silicon photonics applications is presented here. The linear dependence of the voltage drop across the forward-biased diode on temperature, in a range from 30 °C up to 170 °C, has been used for thermal sensing. A high sensitivity of 11.9 mV/°C in the bias current range of 34–40 nA has been measured. The proposed device is particularly suitable for the continuous temperature monitoring of CMOS-compatible photonic integrated circuits, where the behavior of the on-chip active and passive devices are strongly dependent on their operating temperature.

  8. Low noise electronics for experiments at LHC

    International Nuclear Information System (INIS)

    Manfredi, P.F.

    1984-01-01

    The need of reducing the collection times of solid state detectors will lead to thin layers, 150 to 200 μm thickness. Consequently, the charge made available by minimum ionizing particles will be rather small, between 1.2 x 10 4 and 1.6 x 10 4 electrons for unity muliplicity. Front-end electronics with adequately low noise must be designed to detect such small amounts of charge and the problem looks to be harder if the short times available to process the signals are accounted for. (orig.)

  9. SEMICONDUCTOR INTEGRATED CIRCUITS: A high performance 90 nm CMOS SAR ADC with hybrid architecture

    Science.gov (United States)

    Xingyuan, Tong; Jianming, Chen; Zhangming, Zhu; Yintang, Yang

    2010-01-01

    A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238 × 214 μm2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

  10. Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

    Science.gov (United States)

    Roever, Stefan

    2012-01-01

    A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

  11. Mechanical characterization of poly-SiGe layers for CMOS-MEMS integrated application

    Science.gov (United States)

    Modlinski, Robert; Witvrouw, Ann; Verbist, Agnes; Puers, Robert; De Wolf, Ingrid

    2010-01-01

    Measuring mechanical properties at the microscale is essential to understand and to fabricate reliable MEMS. In this paper a tensile testing system and matching microscale test samples are presented. The test samples have a dog-bone-like structure. They are designed to mimic standard macro-tensile test samples. The micro-tensile tests are used to characterize 0.9 µm thick polycrystalline silicon germanium (poly-SiGe) films. The poly-SiGe film, that can be considered as a close equivalent to polycrystalline silicon (poly-Si), is studied as a very promising material for use in CMOS/MEMS integration in a single chip due to its low-temperature LPCVD deposition (T < 450 °C). The fabrication process of the poly-SiGe micro-tensile test structure is explained in detail: the design, the processing and post-processing, the testing and finally the results' discussion. The poly-SiGe micro-tensile results are also compared with nanoindentation data obtained on the same poly-SiGe films as well as with results obtained by other research groups.

  12. Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

    Science.gov (United States)

    Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

    2017-11-26

    Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

  13. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    Science.gov (United States)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  14. Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

    Science.gov (United States)

    Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

    2018-01-01

    Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

  15. 3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer †

    Science.gov (United States)

    Asano, Sho; Nakayama, Takahiro; Hata, Yoshiyuki; Tanaka, Shuji

    2017-01-01

    This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively. PMID:29068429

  16. Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

    Science.gov (United States)

    Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

    2016-12-21

    One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

  17. A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

    Science.gov (United States)

    Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

    2013-01-01

    One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

  18. A low noise ASIC for two dimensional neutron gas detector with performance of high spatial resolution (Contract research)

    International Nuclear Information System (INIS)

    Yamagishi, Hideshi; Toh, Kentaro; Nakamura, Tatsuya; Sakasai, Kaoru; Soyama, Kazuhiko

    2012-02-01

    An ASD-ASIC (Amplifier-Shaper-Discriminator ASIC) with fast response and low noise performances has been designed for two-dimensional position sensitive neutron gas detectors (InSPaD). The InSPaD is a 2D neutron detector system with 3 He gas and provides a high spatial resolution by making distinction between proton and triton particles generated in the gas chamber. The new ASD-ASIC is required to have very low noise, a wide dynamic range, good output linearity and high counting rate. The new ASD-ASIC has been designed by using CMOS and consisted of 64-channel ASDs, a 16-channel multiplexer with LVTTL drivers and sum amplifier system for summing all analog signals. The performances were evaluated by the Spice simulation. It was confirmed that the new ASD-ASIC had very low noise performance, wide dynamic range and fast signal processing functions. (author)

  19. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  20. Changed of the working capacity of CMOS integrated circuits under ionizing radiations effect of low and high dose rate; Izmeneniya rabotosposobnosti KMOP integral`nykh mikroskhem pri vozdejstvii ioniziruyushchikh izluchenij s nizkoj i vysokoj intensivnost`yu

    Energy Technology Data Exchange (ETDEWEB)

    Bogatyrev, Yu V; Korshunov, F P

    1994-12-31

    Results of experimental investigations into the working capacity of different types of integrated CMOS circuits under effect of electron and gamma radiation are presented. Methods for evaluating IC CMOS under low irradiation intensity using the microcircuit testing under hugh intensity or at increased temperature with regard to the processes of parameter reconstruction after irradiation are proposed.

  1. Well coupled, low noise, dc SQUIDS

    International Nuclear Information System (INIS)

    Muhlfelder, B.; Beall, J.A.; Cromar, M.W.; Johnson, W.W.; Ono, R.H.

    1985-01-01

    The authors have designed, fabricated, and tested a Double Transformer (DT) coupled dc SQUID (Superconducting Quantum Interference Device) with low noise, an input inductance of 1μH and a smooth input-output characteristic. A transmission line model is presented to explain a resonance in the input-output characteristic of early versions of this device. Guided by the results of numerical simulations a new version of this device has been built and tested. Experimental results are presented that show that the resonance can be moved to a higher voltage by reducing the area of the SQUID loop. The voltage-external flux characteristic of some of these new devices agrees to within 10% with computer simulations. The minimum detectable energy per unit bandwidth (MDE) referred to the SQUID loop, is 10h, where h is Planck's constant. Computer simulations indicate an MDE of 6h

  2. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    International Nuclear Information System (INIS)

    Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

    2014-01-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

  3. Design and characterization of radiation resistant integrated circuits for the LHC particle detectors using deep sub-micron CMOS technologies

    International Nuclear Information System (INIS)

    Anelli, Giovanni Maria

    2000-01-01

    The electronic circuits associated with the particle detectors of the CERN Large Hadron Collider (LHC) have to work in a highly radioactive environment. This work proposes a methodology allowing the design of radiation resistant integrated circuits using the commercial sub-micron CMOS technology. This method uses the intrinsic radiation resistance of ultra-thin grid oxides, the technology of enclosed layout transistors (ELT), and the protection rings to avoid the radio-induced creation of leakage currents. In order to check the radiation tolerance level, several test structures have been designed and tested with different radiation sources. These tests have permitted to study the physical phenomena responsible for the damages induced by the radiations and the possible remedies. Then, the particular characteristics of ELT transistors and their influence on the design of complex integrated circuits has been explored. The modeling of the W/L ratio, the asymmetries (for instance in the output conductance) and the performance of ELT couplings have never been studied yet. The noise performance of the 0.25 μ CMOS technology, used in the design of several integrated circuits of the LHC detectors, has been characterized before and after irradiation. Finally, two integrated circuits designed using the proposed method are presented. The first one is an analogic memory and the other is a circuit used for the reading of the signals of one of the LHC detectors. Both circuits were irradiated and have endured very high doses practically without any sign of performance degradation. (J.S.)

  4. Characterization of 13 and 30 μm thick hydrogenated amorphous silicon diodes deposited over CMOS integrated circuits for particle detection application

    International Nuclear Information System (INIS)

    Despeisse, M.; Anelli, G.; Commichau, S.; Dissertori, G.; Garrigos, A.; Jarron, P.; Miazza, C.; Moraes, D.; Shah, A.; Wyrsch, N.; Viertel, G.

    2004-01-01

    We present the experimental results obtained with a novel monolithic silicon pixel detector which consists in depositing a n-i-p hydrogenated amorphous silicon (a-Si:H) diode straight above the readout ASIC (this technology is called Thin Film on ASIC, TFA). The characterization has been performed on 13 and 30 μm thick a-Si:H films deposited on top of an ASIC containing a linear array of high-speed low-noise transimpedance amplifiers designed in a 0.25 μm CMOS technology. Experimental results presented have been obtained with a 600 nm pulsed laser. The results of charge collection efficiency and charge collection speed of these structures are discussed

  5. Ultra Low Noise Poroelastic Road Surfaces

    Directory of Open Access Journals (Sweden)

    Jerzy A. Ejsmont

    2016-04-01

    Full Text Available Noise is one of the most important environmental problems related to road traffic. During the last decades, the noise emitted by the engines and powertrains of vehicles was greatly reduced and tires became a clearly dominant noise source. The article describes the concept of low noise poroelastic road surfaces that are composed of mineral and rubber aggregate bound by polyurethane resin. Those surfaces have a porous structure and are much more flexible than standard asphalt or cement concrete pavements due to high content of rubber aggregate and elastic binder. Measurements performed in several European countries indicate that such surfaces decrease tire/road noise between 7 dB and 12 dB with respect to reference surfaces such as dense asphalt concrete or stone matrix asphalt. Furthermore, poroelastic road surfaces ascertain the rolling resistance of car tires, which is comparable to classic pavements. One of the unforeseen properties of the poroelastic road surfaces is their ability to decrease the risks related to car fires with fuel spills. The article presents the road and laboratory results of noise, rolling resistance, and fire tests performed on a few types of poroelastic road surfaces.

  6. Physical and electrical bandwidths of integrated photodiodes in standard CMOS technology

    NARCIS (Netherlands)

    Radovanovic, S.; Annema, Anne J.; Nauta, Bram

    2003-01-01

    The influence of different geometries (layouts) and structures of high-speed photodiodes in fully standard 0.18 μm CMOS technology on their intrinsic (physical) and electrical bandwidths is analyzed. Three photodiode structures are studied: nwell/p-substrate, p+/nwell/p-substrate and p+/nwell. The

  7. Broadband sub-THz spectroscopy modules integrated in 65-nm CMOS technology

    NARCIS (Netherlands)

    Matters-Kammerer, M.K.; van Goor, D.; Tripodi, L.

    2017-01-01

    The design and characterization of a broadband 20-480 GHz continuously tuneable on-chip spectrometer based on non-linear transmission lines in 65-nm CMOS technology is presented. The design procedure of the sampler that detects the ultra-broadband signal from the transmitter in time and frequency

  8. A high-efficiency, low-noise power solution for a dual-channel GNSS RF receiver

    International Nuclear Information System (INIS)

    Shi Jian; Mo Taishan; Gan Yebing; Ma Chengyan; Ye Tianchun; Le Jianlian

    2012-01-01

    A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented. The power solution involves a DC—DC buck converter and a followed low-dropout regulator (LDO). The pulse-width-modulation (PWM) control method is adopted for better noise performance. An improved low-power high-frequency PWM control circuit is proposed, which halves the average quiescent current of the buck converter to 80 μA by periodically shutting down the OTA. The size of the output stage has also been optimized to achieve high efficiency under a light load condition. In addition, a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current. Fabricated with commercial 180-nm CMOS technology, the DC—DC converter achieves a peak efficiency of 93.1% under a 2 MHz working frequency. The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB. (semiconductor integrated circuits)

  9. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    Science.gov (United States)

    Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

    2014-06-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

  10. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2012-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

  11. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  12. Low Noise Research Fan Stage Design

    Science.gov (United States)

    Hobbs, David E.; Neubert, Robert J.; Malmborg, Eric W.; Philbrick, Daniel H.; Spear, David A.

    1995-01-01

    This report describes the design of a Low Noise ADP Research Fan stage. The fan is a variable pitch design which is designed at the cruise pitch condition. Relative to the cruise setting, the blade is closed at takeoff and opened for reverse thrust operation. The fan stage is a split flow design with fan exit guide vanes and core stators. This fan stage design was combined with a nacelle and engine core duct to form a powered fan/nacelle, subscale model. This model is intended for use in aerodynamic performance, acoustic and structural testing in a wind tunnel. The model has a 22-inch outer fan diameter and a hub-to-top ratio of 0.426 which permits the use of existing NASA fan and cowl force balance designs and rig drive system. The design parameters were selected to permit valid acoustic and aerodynamic comparisons with the PW 17-inch rig previously tested under NASA contract. The fan stage design is described in detail. The results of the design axisymmetric analysis at aerodynamic design condition are included. The structural analysis of the fan rotor and attachment is described including the material selections and stress analysis. The blade and attachment are predicted to have adequate low cycle fatigue life, and an acceptable operating range without resonant stress or flutter. The stage was acoustically designed with airfoil counts in the fan exit guide vane and core stator to minimize noise. A fan-FEGV tone analysis developed separately under NASA contract was used to determine these airfoil counts. The fan stage design was matched to a nacelle design to form a fan/nacelle model for wind tunnel testing. The nacelle design was developed under a separate NASA contract. The nacelle was designed with an axisymmetric inlet, cowl and nozzle for convenience in testing and fabrication. Aerodynamic analysis of the nacelle confirmed the required performance at various aircraft operating conditions.

  13. Wideband Low Noise Amplifiers Exploiting Thermal Noise Cancellation

    NARCIS (Netherlands)

    Bruccoleri, F.; Klumperink, Eric A.M.; Nauta, Bram

    2005-01-01

    Low Noise Amplifiers (LNAs) are commonly used to amplify signals that are too weak for direct processing for example in radio or cable receivers. Traditionally, low noise amplifiers are implemented via tuned amplifiers, exploiting inductors and capacitors in resonating LC-circuits. This can render

  14. Large area CMOS image sensors

    International Nuclear Information System (INIS)

    Turchetta, R; Guerrini, N; Sedgwick, I

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  15. Single event upset test structures for digital CMOS application specific integrated circuits

    International Nuclear Information System (INIS)

    Baze, M.P.; Bartholet, W.G.; Braatz, J.C.; Dao, T.A.

    1993-01-01

    An approach has been developed for the design and utilization of SEU test structures for digital CMOS ASICs. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU response and designing a structure to characterize each response for each category. Critical SEU response parameters extracted from these structures are used to evaluate the SEU hardness of ASIC libraries and predict the hardness of ASIC chips

  16. Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

    Science.gov (United States)

    Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

    2003-06-01

    We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

  17. CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

    Science.gov (United States)

    Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

    2011-04-01

    In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

  18. Low noise Nb-SIS mixers at far above the gap frequency

    NARCIS (Netherlands)

    Gao, [No Value; vandeStadt, H; Jegers, JBM; Kovtonyuk, S; Hulshoff, W; Whyborn, ND; Klapwijk, TM; deGraauw, T; Liao, FJ; Liu, JY

    1996-01-01

    There are great interests in developing Nb SIS mixers because of the extremely low noise temperatures and because of the need of low local oscillator (LO) power. Several groups have demonstrated experimentally that Nb SIS mixers with integrated tuning elements can perform near the quantum noise

  19. Integrated X-ray and charged particle active pixel CMOS sensor arrays using an epitaxial silicon sensitive region

    International Nuclear Information System (INIS)

    Kleinfelder, Stuart; Bichsel, Hans; Bieser, Fred; Matis, Howard S.; Rai, Gulshan; Retiere, Fabrice; Weiman, Howard; Yamamoto, Eugene

    2002-01-01

    Integrated CMOS Active Pixel Sensor (APS) arrays have been fabricated and tested using X-ray and electron sources. The 128 by 128 pixel arrays, designed in a standard 0.25 micron process, use a ∼10 micron epitaxial silicon layer as a deep detection region. The epitaxial layer has a much greater thickness than the surface features used by standard CMOS APS, leading to stronger signals and potentially better signal-to-noise ratio (SNR). On the other hand, minority carriers confined within the epitaxial region may diffuse to neighboring pixels, blur images and reduce peak signal intensity. But for low-rate, sparse-event images, centroid analysis of this diffusion may be used to increase position resolution. Careful trade-offs involving pixel size and sense-node area verses capacitance must be made to optimize overall performance. The prototype sensor arrays, therefore, include a range of different pixel designs, including different APS circuits and a range of different epitaxial layer contact structures. The fabricated arrays were tested with 1.5 GeV electrons and Fe-55 X-ray sources, yielding a measured noise of 13 electrons RMS and an SNR for single Fe-55 X-rays of greater than 38

  20. System-in Package of Integrated Humidity Sensor Using CMOS-MEMS Technology.

    Science.gov (United States)

    Lee, Sung Pil

    2015-10-01

    Temperature/humidity microchips with micropump were fabricated using a CMOS-MEMS process and combined with ZigBee modules to implement a sensor system in package (SIP) for a ubiquitous sensor network (USN) and/or a wireless communication system. The current of a diode temperature sensor to temperature and a normalized current of FET humidity sensor to relative humidity showed linear characteristics, respectively, and the use of the micropump has enabled a faster response. A wireless reception module using the same protocol as that in transmission systems processed the received data within 10 m and showed temperature and humidity values in the display.

  1. BiCMOS amplifier-discriminator integrated circuit for gas-filled detector readout

    International Nuclear Information System (INIS)

    Herve, C.; Dzahini, D.; Le Caer, T.; Richer, J.-P.; Torki, K.

    2005-01-01

    The paper presents a 16-channel amplifier-discriminator designed in BiCMOS technology. It will be used for the binary parallel readout of gas-filled detectors being designed at the European Synchrotron Radiation Facility. The circuit (named AMS211) has been manufactured. The measured transimpedance gain (400 KΩ), bandwidth (25 MHz) and noise (1570 e - +95 e - /pF ENC) well match the simulated results. The discriminator thresholds are individually controlled by built-in Digital to Analogue Converter. The experience gained with a first prototype of readout electronics indicates that the AMS211 should meet our requirements

  2. BiCMOS amplifier-discriminator integrated circuit for gas-filled detector readout

    Energy Technology Data Exchange (ETDEWEB)

    Herve, C. [European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex (France)]. E-mail: herve@esrf.fr; Dzahini, D. [Laboratoire de Physique Subatomique et de Cosmologie, Grenoble (France); Le Caer, T. [European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex (France); Richer, J.-P. [Laboratoire de Physique Subatomique et de Cosmologie, Grenoble (France); Torki, K. [Laboratoire TIMA, Grenoble (France)

    2005-03-21

    The paper presents a 16-channel amplifier-discriminator designed in BiCMOS technology. It will be used for the binary parallel readout of gas-filled detectors being designed at the European Synchrotron Radiation Facility. The circuit (named AMS211) has been manufactured. The measured transimpedance gain (400 K{omega}), bandwidth (25 MHz) and noise (1570 e{sup -}+95 e{sup -}/pF ENC) well match the simulated results. The discriminator thresholds are individually controlled by built-in Digital to Analogue Converter. The experience gained with a first prototype of readout electronics indicates that the AMS211 should meet our requirements.

  3. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L. [INFN, Pavia; Braga, D. [Fermilab; Christian, D. [Fermilab; Deptuch, G. [Fermilab; Fahim. F., Fahim. F. [Fermilab; Nodari, B. [Lyon, IPN; Ratti, L. [INFN, Pavia; Re, V. [INFN, Pavia; Zimmerman, T. [Fermilab

    2017-09-01

    This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

  4. A CMOS-compatible large-scale monolithic integration of heterogeneous multi-sensors on flexible silicon for IoT applications

    KAUST Repository

    Nassar, Joanna M.

    2017-02-07

    We report CMOS technology enabled fabrication and system level integration of flexible bulk silicon (100) based multi-sensors platform which can simultaneously sense pressure, temperature, strain and humidity under various physical deformations. We also show an advanced wearable version for body vital monitoring which can enable advanced healthcare for IoT applications.

  5. A CMOS-compatible large-scale monolithic integration of heterogeneous multi-sensors on flexible silicon for IoT applications

    KAUST Repository

    Nassar, Joanna M.; Sevilla, Galo T.; Velling, Seneca J.; Cordero, Marlon D.; Hussain, Muhammad Mustafa

    2017-01-01

    We report CMOS technology enabled fabrication and system level integration of flexible bulk silicon (100) based multi-sensors platform which can simultaneously sense pressure, temperature, strain and humidity under various physical deformations. We also show an advanced wearable version for body vital monitoring which can enable advanced healthcare for IoT applications.

  6. Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

    Science.gov (United States)

    Malits, Maria; Brouk, Igor; Nemirovsky, Yael

    2018-05-19

    This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

  7. Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.

    Science.gov (United States)

    Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon

    2017-08-25

    The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

  8. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  9. A Multipurpose CMOS Platform for Nanosensing.

    Science.gov (United States)

    Bonanno, Alberto; Sanginario, Alessandro; Marasso, Simone L; Miccoli, Beatrice; Bejtka, Katarzyna; Benetto, Simone; Demarchi, Danilo

    2016-11-30

    This paper presents a customizable sensing system based on functionalized nanowires (NWs) assembled onto complementary metal oxide semiconductor (CMOS) technology. The Micro-for-Nano (M4N) chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP) generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC) that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW-229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  10. A High-Linearity Low-Noise Amplifier with Variable Bandwidth for Neural Recoding Systems

    Science.gov (United States)

    Yoshida, Takeshi; Sueishi, Katsuya; Iwata, Atsushi; Matsushita, Kojiro; Hirata, Masayuki; Suzuki, Takafumi

    2011-04-01

    This paper describes a low-noise amplifier with multiple adjustable parameters for neural recording applications. An adjustable pseudo-resistor implemented by cascade metal-oxide-silicon field-effect transistors (MOSFETs) is proposed to achieve low-signal distortion and wide variable bandwidth range. The amplifier has been implemented in 0.18 µm standard complementary metal-oxide-semiconductor (CMOS) process and occupies 0.09 mm2 on chip. The amplifier achieved a selectable voltage gain of 28 and 40 dB, variable bandwidth from 0.04 to 2.6 Hz, total harmonic distortion (THD) of 0.2% with 200 mV output swing, input referred noise of 2.5 µVrms over 0.1-100 Hz and 18.7 µW power consumption at a supply voltage of 1.8 V.

  11. Monolithic CMOS imaging x-ray spectrometers

    Science.gov (United States)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  12. A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

    International Nuclear Information System (INIS)

    Traversi, G; Manghisoni, M; Re, V; Gaioni, L; Ratti, L

    2011-01-01

    Deep N-Well (DNW) Monolithic Active Pixel Sensors (MAPS) have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. In these devices the triple well option, available in deep submicron processes, is exploited to implement analog and digital signal processing at the pixel level. Many prototypes have been fabricated in a planar (2D) 130nm CMOS technology. A new kind of DNW-MAPS, namely Apsel5 3 D, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. The impact of 3D processes on the design and performance of DNW pixel sensors could be large, with significant advantages in terms of detection efficiency, pixel cell size and immunity to cross-talk, therefore complying with the severe constraints set by future HEP experiments.

  13. Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2009-02-01

    Full Text Available This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature

  14. A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0

    Energy Technology Data Exchange (ETDEWEB)

    Traversi, G; Manghisoni, M; Re, V [University of Bergamo, Via Marconi 5, 24044 Dalmine (Italy); Gaioni, L; Ratti, L, E-mail: gianluca.traversi@unibg.it [INFN Pavia, Via Bassi 6, 27100 Pavia (Italy)

    2011-01-15

    Deep N-Well (DNW) Monolithic Active Pixel Sensors (MAPS) have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. In these devices the triple well option, available in deep submicron processes, is exploited to implement analog and digital signal processing at the pixel level. Many prototypes have been fabricated in a planar (2D) 130nm CMOS technology. A new kind of DNW-MAPS, namely Apsel5{sub 3}D, which exploits the capabilities of vertical integration (3D) processes, is presented and discussed in this paper. The impact of 3D processes on the design and performance of DNW pixel sensors could be large, with significant advantages in terms of detection efficiency, pixel cell size and immunity to cross-talk, therefore complying with the severe constraints set by future HEP experiments.

  15. 5-Gb/s 0.18-{mu}m CMOS 2:1 multiplexer with integrated clock extraction

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Changchun; Wang Zhigong; Shi Si; Miao Peng [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China); Tian Ling, E-mail: zgwang@seu.edu.c [School of Science and Engineering, Southeast University, Nanjing 210096 (China)

    2009-09-15

    A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 {mu}m CMOS technology. The chip area is 670 x 780 {mu}m{sup 2}. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

  16. 5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

    International Nuclear Information System (INIS)

    Zhang Changchun; Wang Zhigong; Shi Si; Miao Peng; Tian Ling

    2009-01-01

    A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 x 780 μm 2 . At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

  17. 5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

    Science.gov (United States)

    Changchun, Zhang; Zhigong, Wang; Si, Shi; Peng, Miao; Ling, Tian

    2009-09-01

    A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

  18. Sticker-type ECG/PPG concurrent monitoring system hybrid integration of CMOS SoC and organic sensor device.

    Science.gov (United States)

    Yongsu Lee; Hyeonwoo Lee; Seunghyup Yoo; Hoi-Jun Yoo

    2016-08-01

    The sticker-type sensor system is proposed targeting ECG/PPG concurrent monitoring for cardiovascular diseases. The stickers are composed of two types: Hub and Sensor-node (SN) sticker. Low-power CMOS SoC for measuring ECG and PPG signal is hybrid integrated with organic light emitting diodes (OLEDs) and organic photo detector (OPD). The sticker has only 2g weight and only consumes 141μW. The optical calibration loop is adopted for maintaining SNR of PPG signal higher than 30dB. The pulse arrival time (PAT) and SpO2 value can be extracted from various body parts and verified comparing with the reference device from 20 people in-vivo experiments.

  19. Cross Linked Metal Particles for Low Noise Bolometer Materials

    Science.gov (United States)

    2016-12-12

    Our results indicate that the CLMPs can simultaneously have a high temperature coefficient of resistivity and a low noise, and therefore have a...indicate that the CLMPs can simultaneously have a high temperature co- efficient of resistivity and a low noise, and therefore have a great potential...current as a function of the inverse of applied bias for CLMP films at different temperatures. It is seen that the I-V curves are highly nonlinear as 7 0

  20. Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

    Science.gov (United States)

    Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

    2017-05-01

    A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

  1. Qualitative criteria and thresholds for low noise asphalt mixture design

    Science.gov (United States)

    Vaitkus, A.; Andriejauskas, T.; Gražulytė, J.; Šernas, O.; Vorobjovas, V.; Kleizienė, R.

    2018-05-01

    Low noise asphalt pavements are cost efficient and cost effective alternative for road traffic noise mitigation comparing with noise barriers, façade insulation and other known noise mitigation measures. However, design of low noise asphalt mixtures strongly depends on climate and traffic peculiarities of different regions. Severe climate regions face problems related with short durability of low noise asphalt mixtures in terms of considerable negative impact of harsh climate conditions (frost-thaw, large temperature fluctuations, hydrological behaviour, etc.) and traffic (traffic loads, traffic volumes, studded tyres, etc.). Thus there is a need to find balance between mechanical and acoustical durability as well as to ensure adequate pavement skid resistance for road safety purposes. Paper presents analysis of the qualitative criteria and design parameters thresholds of low noise asphalt mixtures. Different asphalt mixture composition materials (grading, aggregate, binder, additives, etc.) and relevant asphalt layer properties (air void content, texture, evenness, degree of compaction, etc.) were investigated and assessed according their suitability for durable and effective low noise pavements. Paper concluded with the overview of requirements, qualitative criteria and thresholds for low noise asphalt mixture design for severe climate regions.

  2. Development of a low-noise, two-dimensional amplifier array

    International Nuclear Information System (INIS)

    Kishishita, Tetsuichi; Ikeda, Hirokazu; Sakumura, Takuto; Tamura, Ken-ichi; Takahashi, Tadayuki

    2009-01-01

    This paper describes the recent development of a low-noise, two-dimensional analog front-end ASIC for hybrid pixel imaging detectors. Based on the Open-IP LSI project, the ASIC is designed to meet a low-noise requirement of better than 100e - (rms) with self-triggering capability. The ASIC is intended for the readout of pixel sensors utilizing silicon (Si) and cadmium telluride (CdTe) as detector materials for spectroscopic imaging observations in the X-ray and gamma-ray regions. The readout chip consists of a 4x4 matrix of identical 270μmx270μm pixel cells and was implemented with TSMC 0.35-μm CMOS technology. Each pixel cell contains a charge-sensitive amplifier, pole-zero cancellation circuit, shaper, comparator, and peak hold circuit. Preliminary testing of the ASIC achieved an 88e - (rms) equivalent noise charge and a 25e - /pF noise slope with power consumption of 150μW per pixel.

  3. Integrated Cu-based TM-pass polarizer using CMOS technology platform

    KAUST Repository

    Ng, Tien Khee

    2010-01-01

    A transverse-magnetic-pass (TM-pass) copper (Cu) polarizer is proposed and analyzed using the previously published two-dimensional Method-of-Lines beam-propagation model. The proposed polarizer exhibits a simulated high-pass filter characteristics, with TM0 and TE0 mode transmissivity of >70% and <5%, respectively, in the wavelength regime of 1.2-1.6 μm. The polarization extinction ratio (PER) given by 10 log10 (PTM0)/(PTE0) is +11.5 dB across the high-pass wavelength regime. To the best of the authors\\' knowledge, we report here the smallest footprint CMOS-platform compatible TM-polarizer.

  4. RAPS: an innovative active pixel for particle detection integrated in CMOS technology

    International Nuclear Information System (INIS)

    Passeri, Daniele; Placidi, Pisana; Verducci, Leonardo; Ciampolini, Paolo; Matrella, Guido; Marras, Alessandro; Bilei, G.M.

    2004-01-01

    In this paper we discuss some design, implementation and test issues, with respect to the development of the RAPS01 chip in the framework of the Radiation Active Pixel Sensors (RAPS) INFN project. The project aimed at verifying feasibility of smart, high-resolution pixel arrays with a fully standard, submicron CMOS technology for particle detection purposes. Layout optimization of the pixel, including sensitive element and local read and amplification circuits has been carried out. Different basic pixel schemes and read-out options have been proposed and devised. Chip fabrication has been completed and test phase is now under way: to this purpose a suitable test environment has been devised and test strategies have been planned

  5. 25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.

    Science.gov (United States)

    Li, Guoliang; Zheng, Xuezhe; Yao, Jin; Thacker, Hiren; Shubin, Ivan; Luo, Ying; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2011-10-10

    We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 μm ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 μm2 footprint.

  6. Hybrid CMOS-Graphene Sensor Array for Subsecond Dopamine Detection.

    Science.gov (United States)

    Nasri, Bayan; Wu, Ting; Alharbi, Abdullah; You, Kae-Dyi; Gupta, Mayank; Sebastian, Sunit P; Kiani, Roozbeh; Shahrjerdi, Davood

    2017-12-01

    We introduce a hybrid CMOS-graphene sensor array for subsecond measurement of dopamine via fast-scan cyclic voltammetry (FSCV). The prototype chip has four independent CMOS readout channels, fabricated in a 65-nm process. Using planar multilayer graphene as biologically compatible sensing material enables integration of miniaturized sensing electrodes directly above the readout channels. Taking advantage of the chemical specificity of FSCV, we introduce a region of interest technique, which subtracts a large portion of the background current using a programmable low-noise constant current at about the redox potentials. We demonstrate the utility of this feature for enhancing the sensitivity by measuring the sensor response to a known dopamine concentration in vitro at three different scan rates. This strategy further allows us to significantly reduce the dynamic range requirements of the analog-to-digital converter (ADC) without compromising the measurement accuracy. We show that an integrating dual-slope ADC is adequate for digitizing the background-subtracted current. The ADC operates at a sampling frequency of 5-10 kHz and has an effective resolution of about 60 pA, which corresponds to a theoretical dopamine detection limit of about 6 nM. Our hybrid sensing platform offers an effective solution for implementing next-generation FSCV devices that can enable precise recording of dopamine signaling in vivo on a large scale.

  7. Post-CMOS FinFET integration of bismuth telluride and antimony telluride thin-film-based thermoelectric devices on SoI substrate

    KAUST Repository

    Aktakka, Ethem Erkan

    2013-10-01

    This letter reports, for the first time, heterogeneous integration of bismuth telluride (Bi2Te3) and antimony telluride (Sb 2Te3) thin-film-based thermoelectric ffect transistors) via a characterized TE-film coevaporationand shadow-mask patterning process using predeposition surface treatment methods for reduced TE-metal contact resistance. As a demonstration vehicle, a 2 × 2 mm2-sized integrated planar thermoelectric generator (TEG) is shown to harvest 0.7 μ W from 21-K temperature gradient. Transistor performance showed no significant change upon post-CMOS TEG integration, indicating, for the first time, the CMOS compatibility of the Bi2Te3 and Sb2Te3 thin films, which could be leveraged for realization of high-performance integrated micro-TE harvesters and coolers. © 2013 IEEE.

  8. Design of 5.8 GHz Integrated Antenna on 180nm Complementary Metal Oxide Semiconductor (CMOS) Technology

    Science.gov (United States)

    Razak, A. H. A.; Shamsuddin, M. I. A.; Idros, M. F. M.; Halim, A. K.; Ahmad, A.; Junid, S. A. M. Al

    2018-03-01

    This project discusses the design and simulation performances of integrated loop antenna. Antenna is one of the main parts in any wireless radio frequency integrated circuit (RFIC). Naturally, antenna is the bulk in any RFIC design. Thus, this project aims to implement an integrated antenna on a single chip making the end product more compact. This project targets 5.8 GHz as the operating frequency of the integrated antenna for a transceiver module based on Silterra CMOS 180nm technology. The simulation of the antenna was done by using High Frequency Structure Simulator (HFSS). This software is industrial standard software that been used to simulate all electromagnetic effect including antenna simulation. This software has ability to simulate frequency at range of 100 MHz to 4 THz. The simulation set up in 3 dimension structure with driven terminal. The designed antenna has 1400um of diameter and placed on top metal layer. Loop configuration of the antenna has been chosen as the antenna design. From the configuration, it is able to make the chip more compact. The simulation shows that the antenna has single frequency band at center frequency 5.8 GHz with -48.93dB. The antenna radiation patterns shows, the antenna radiate at omnidirectional. From the simulation result, it could be concluded that the antenna have a good radiation pattern and propagation for wireless communication.

  9. Low noise PWC cathode readout system

    International Nuclear Information System (INIS)

    Cisneros, E.; Hutchinson, D.; McShurley, D.; Richter, R.; Shapiro, S.

    1980-10-01

    A system has been developed, primarily to detect the induced charge deposited on PWC cathodes, which is versatile, fast and has a good signal to noise ratio for signals of greater than or equal to 10 -14 Coulomb input. The amplifier system, which is completely separated from the detector by 95 Ω coaxial cables, is followed by a new charge integrating, version of the SHAM/BADC system developed at SLAC. This SHAM IV system is CAMAC based, allowing for computer calibration of the entire system from amplifier through ADC

  10. CMOS/SOS processing

    Science.gov (United States)

    Ramondetta, P.

    1980-01-01

    Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

  11. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  12. CMOS dot matrix microdisplay

    Science.gov (United States)

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  13. CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

    Science.gov (United States)

    Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

    2018-04-01

    Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

  14. SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

    International Nuclear Information System (INIS)

    Gao, W.; Liu, H.; Gao, D.; Gan, B.; Wei, T.; Hu, Y.

    2013-06-01

    In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

  15. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  16. Design of CMOS analog integrated fractional-order circuits applications in medicine and biology

    CERN Document Server

    Tsirimokou, Georgia; Elwakil, Ahmed

    2017-01-01

    This book describes the design and realization of analog fractional-order circuits, which are suitable for on-chip implementation, capable of low-voltage operation and electronic adjustment of their characteristics. The authors provide a brief introduction to fractional-order calculus, followed by design issues for fractional-order circuits of various orders and types. The benefits of this approach are demonstrated with current-mode and voltage-mode filter designs. Electronically tunable emulators of fractional-order capacitors and inductors are presented, where the behavior of the corresponding chips fabricated using the AMS 0.35um CMOS process has been experimentally verified. Applications of fractional-order circuits are demonstrated, including a pre-processing stage suitable for the implementation of the Pan-Tompkins algorithm for detecting the QRS complexes of an electrocardiogram (ECG), a fully tunable implementation of the Cole-Cole model used for the modeling of biological tissues, and a simple, non-i...

  17. Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

    Science.gov (United States)

    Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2012-01-01

    Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

  18. A low noise charge sensitive amplifier for use in vacuum photo diode readout

    International Nuclear Information System (INIS)

    Stephenson, R.

    1982-08-01

    The amplifier described consists of a charge sensitive pre-amplifier optimised for low noise with low values of input shunt capacitance, and a shaping amplifier providing both differentiation and integration. Amplifier gain is adjustable up to a maximum of approximately 100 μV/electron with a rise time of 2 μS to the peak of the output voltage, and with an open circuit input noise level of 150 electrons RMS. (author)

  19. Quantum and Private Capacities of Low-Noise Channels

    Science.gov (United States)

    Leditzky, Felix; Leung, Debbie; Smith, Graeme

    2018-04-01

    We determine both the quantum and the private capacities of low-noise quantum channels to leading orders in the channel's distance to the perfect channel. It has been an open problem for more than 20 yr to determine the capacities of some of these low-noise channels such as the depolarizing channel. We also show that both capacities are equal to the single-letter coherent information of the channel, again to leading orders. We thus find that, in the low-noise regime, superadditivity and degenerate codes have a negligible benefit for the quantum capacity, and shielding does not improve the private capacity beyond the quantum capacity, in stark contrast to the situation when noisier channels are considered.

  20. Low noise constant current source for bias dependent noise measurements

    International Nuclear Information System (INIS)

    Talukdar, D.; Bose, Suvendu; Bardhan, K. K.; Chakraborty, R. K.

    2011-01-01

    A low noise constant current source used for measuring the 1/f noise in disordered systems in ohmic as well as nonohmic regime is described. The source can supply low noise constant current starting from as low as 1 μA to a few tens of milliampere with a high voltage compliance limit of around 20 V. The constant current source has several stages, which can work in a standalone manner or together to supply the desired value of load current. The noise contributed by the current source is very low in the entire current range. The fabrication of a low noise voltage preamplifier modified for bias dependent noise measurements and based on the existing design available in the MAT04 data sheet is also described.

  1. Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

    NARCIS (Netherlands)

    Bruccoleri, F.; Klumperink, Eric A.M.; Nauta, Bram

    Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In

  2. Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

    OpenAIRE

    Bruccoleri, F.; Klumperink, Eric A.M.; Nauta, Bram

    2004-01-01

    Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching d...

  3. 116 dB dynamic range CMOS readout circuit for MEMS capacitive accelerometer

    International Nuclear Information System (INIS)

    Long Shanli; Liu Yan; He Kejun; Tang Xinggang; Chen Qian

    2014-01-01

    A high stability in-circuit reprogrammable technique control system for a capacitive MEMS accelerometer is presented. Modulation and demodulation are used to separate the signal from the low frequency noise. A low-noise low-offset charge integrator is employed in this circuit to implement a capacitance-to-voltage converter and minimize the noise and offset. The application-specific integrated circuit (ASIC) is fabricated in a 0.5 μm one-ploy three-metal CMOS process. The measured results of the proposed circuit show that the noise floor of the ASIC is −116 dBV, the sensitivity of the accelerometer is 66 mV/g with a nonlinearity of 0.5%. The chip occupies 3.5 × 2.5 mm 2 and the current is 3.5 mA. (semiconductor integrated circuits)

  4. A programmable ultra-low noise X-band exciter.

    Science.gov (United States)

    MacMullen, A; Hoover, L R; Justice, R D; Callahan, B S

    2001-07-01

    A programmable ultra-low noise X-band exciter has been developed using commercial off-the-shelf components. Its phase noise is more than 10 dB below the best available microwave synthesizers. It covers a 7% frequency band with 0.1-Hz resolution. The X-band output at +23 dBm is a combination of signals from an X-band sapphire-loaded cavity oscillator (SLCO), a low noise UHF frequency synthesizer, and special-purpose frequency translation and up-conversion circuitry.

  5. Transistor design considerations for low-noise preamplifiers

    International Nuclear Information System (INIS)

    Fair, R.B.

    1976-01-01

    A review is presented of design considerations for GaAs Schottky-barrier FETs and other types of transistors in low-noise amplifiers for capacitive sources which are used in nuclear radiation detectors and high speed fiber-optic communication systems. Ultimate limits on performance are evaluated in terms of the g/sub m//C/sub i/ ratio and the gate leakage current to minimize the noise sources. Si bipolar transistors and the future prospects of GaAs, Si and InAs MISFETs are discussed, and performance is compared to FETs currently being used in low-noise preamplifiers

  6. A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

    Directory of Open Access Journals (Sweden)

    Abdulaziz Alhoshany

    2017-08-01

    Full Text Available This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

  7. A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection.

    Science.gov (United States)

    Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N

    2017-08-23

    This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

  8. A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

    KAUST Repository

    Alhoshany, Abdulaziz

    2017-08-23

    This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

  9. A Biosensor-CMOS Platform and Integrated Readout Circuit in 0.18-μm CMOS Technology for Cancer Biomarker Detection

    KAUST Repository

    Alhoshany, Abdulaziz; Sivashankar, Shilpa; Mashraei, Yousof; Omran, Hesham; Salama, Khaled N.

    2017-01-01

    This paper presents a biosensor-CMOS platform for measuring the capacitive coupling of biorecognition elements. The biosensor is designed, fabricated, and tested for the detection and quantification of a protein that reveals the presence of early-stage cancer. For the first time, the spermidine/spermine N1 acetyltransferase (SSAT) enzyme has been screened and quantified on the surface of a capacitive sensor. The sensor surface is treated to immobilize antibodies, and the baseline capacitance of the biosensor is reduced by connecting an array of capacitors in series for fixed exposure area to the analyte. A large sensing area with small baseline capacitance is implemented to achieve a high sensitivity to SSAT enzyme concentrations. The sensed capacitance value is digitized by using a 12-bit highly digital successive-approximation capacitance-to-digital converter that is implemented in a 0.18 μm CMOS technology. The readout circuit operates in the near-subthreshold regime and provides power and area efficient operation. The capacitance range is 16.137 pF with a 4.5 fF absolute resolution, which adequately covers the concentrations of 10 mg/L, 5 mg/L, 2.5 mg/L, and 1.25 mg/L of the SSAT enzyme. The concentrations were selected as a pilot study, and the platform was shown to demonstrate high sensitivity for SSAT enzymes on the surface of the capacitive sensor. The tested prototype demonstrated 42.5 μS of measurement time and a total power consumption of 2.1 μW.

  10. A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18 μm CMOS

    International Nuclear Information System (INIS)

    Bao Kuan; Fan Xiangning; Li Wei; Zhang Li; Wang Zhigong

    2012-01-01

    This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate-inductive-peaking technique. High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band. Fabricated in 0.18 μm CMOS process, the LNA achieves 2.5 GHz of −3 dB bandwidth and 16 dB of gain. The gain variation is within ±0.8 dB from 300 MHz to 2.2 GHz. The measured noise figure (NF) and average IIP3 are 3.4 dB and −2 dBm, respectively. The proposed LNA occupies 0.39 mm 2 core chip area. Operating at 1.8 V, the LNA drains a current of 11.7 mA. (semiconductor integrated circuits)

  11. InP-DHBT-on-BiCMOS technology with fT/fmax of 400/350 GHz for heterogeneous integrated millimeter-wave sources

    DEFF Research Database (Denmark)

    Kraemer, Tomas; Ostermay, Ina; Jensen, Thomas

    2013-01-01

    -100 GHz. The 0.8 × 5 μm2 InP DHBTs show fT/fmax of 400/350 GHz with an output power of more than 26 mW at 96 GHz. These are record values for a heterogeneously integrated transistor on silicon. As a circuit example, a 164-GHz signal source is presented. It features a voltage-controlled oscillator in Bi......This paper presents a novel InP-SiGe BiCMOS technology using wafer-scale heterogeneous integration. The vertical stacking of the InP double heterojunction bipolar transistor (DHBT) circuitry directly on top of the BiCMOS wafer enables ultra-broadband interconnects with

  12. Fabrication and Characterisation of Low-noise Monolithic Mode-locked Lasers

    DEFF Research Database (Denmark)

    Larsson, David

    2007-01-01

    This thesis deals with the fabrication and characterisation of monolithic semiconductor mode-locked lasers for use in optical communication systems. Other foreseeable applications may be as sources in microwave photonics and optical sampling. The thesis also deals with the design and fabrication...... of intracavity monolithically integrated filters. The common dnominator among the diffrent parts of the thesis is how to achieve and measure the lowest possible noise. Achieving low noise has been pinpointed as one of the most important and difficult challenges for semiconductor mode-locked lasers. The main...... result of this thesis are a fabrication process of a monolithic and deeply etched distributed Bragg reflector and a characterisation system for measurement of quantum limitid timing noise at high repetition rates. The Bragg reflector is a key component in achieving transform limited pulses with low noise...

  13. External Peltier Cooler For Low-Noise Amplifier

    Science.gov (United States)

    Soper, Terry A.

    1990-01-01

    Inexpensive Peltier-effect cooling module made of few commercially available parts used to reduce thermal noise in microwave amplifier. Retrofitted to almost any microwave low-noise amplifier or receiver preamplifier used in communication, telemetry, or radar. Includes copper or aluminum cold plate held tightly against unit to be cooled by strap-type worm-gear clamps.

  14. CMOS integrated avalanche photodiodes and frequency-mixing optical sensor front end for portable NIR spectroscopy instruments.

    Science.gov (United States)

    Yun, Ruida; Sthalekar, Chirag; Joyner, Valencia M

    2011-01-01

    This paper presents the design and measurement results of two avalanche photodiode structures (APDs) and a novel frequency-mixing transimpedance amplifier (TIA), which are key building blocks towards a monolithically integrated optical sensor front end for near-infrared (NIR) spectroscopy applications. Two different APD structures are fabricated in an unmodified 0.18 \\im CMOS process, one with a shallow trench isolation (STI) guard ring and the other with a P-well guard ring. The APDs are characterized in linear mode. The STI bounded APD demonstrates better performance and exhibits 3.78 A/W responsivity at a wavelength of 690 nm and bias voltage of 10.55 V. The frequency-mixing TIA (FM-TIA) employs a T-feedback network incorporating gate-controlled transistors for resistance modulation, enabling the simultaneous down-conversion and amplification of the high frequency modulated photodiode (PD) current. The TIA achieves 92 dS Ω conversion gain with 0.5 V modulating voltage. The measured IIP(3) is 10.6/M. The amplifier together with the 50 Ω output buffer draws 23 mA from a1.8 V power supply.

  15. An High Performance Integrated Balun for 60 GHz Application in 65nm CMOS Technology

    OpenAIRE

    Ercoli , Mariano; Kraemer , Michael; Dragomirescu , Daniela; Plana , Robert

    2010-01-01

    International audience; This paper shows a new design approach that allows to integrate an efficient balun into mm-wave radio frequency integrated circuits (RFIC). The proposed device is an evolution of the simple transformer. Thanks to the modification on the device's shape, the performance increases considerably, maintaining limited dimensions. The proposed balun shows a very good power division with only 0.5 dB of maximum amplitude imbalance within the whole band of interest and less than ...

  16. Contamination aspects in integrating high dielectric constant and ferroelectric materials into CMOS processes

    OpenAIRE

    Boubekeur, Hocine

    2004-01-01

    n memory technology, new materials are being intensively investigated to overcome the integration limits of conventional dielectrics for Giga-bit scale integration, or to be able to produce new types of non-volatile low power memories such as FeRAM. Perovskite type high dielectric constant films for use in Giga-bit scale memories or layered perovskite films for use in non-volatile memories involve materials to semiconductor process flows, which entail a high risk of contamination. The introdu...

  17. Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier

    International Nuclear Information System (INIS)

    Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

    2010-01-01

    The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

  18. Single-Chip Fully Integrated Direct-Modulation CMOS RF Transmitters for Short-Range Wireless Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2013-08-01

    Full Text Available Ultra-low power radio frequency (RF transceivers used in short-range application such as wireless sensor networks (WSNs require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs in addition to a 2.0 GHz phase-locked loop (PLL based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of −122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of −120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

  19. Rapid immuno-analytical system physically integrated with lens-free CMOS image sensor for food-borne pathogens.

    Science.gov (United States)

    Jeon, Jin-Woo; Kim, Jee-Hyun; Lee, Jong-Mook; Lee, Won-Ho; Lee, Do-Young; Paek, Se-Hwan

    2014-02-15

    To realize an inexpensive, pocket-sized immunosensor system, a rapid test devise based on cross-flow immuno-chromatography was physically combined with a lens-free CMOS image sensor (CIS), which was then applied to the detection of the food-borne pathogen, Salmonella typhimurium (S. typhimurium). Two CISs, each retaining 1.3 mega pixel array, were mounted on a printed circuit board to fabricate a disposable sensing module, being connectable with a signal detection system. For the bacterial analysis, a cellulose membrane-based immunosensing platform, ELISA-on-a-chip (EOC), was employed, being integrated with the CIS module, and the antigen-antibody reaction sites were aligned with the respective sensor. In such sensor construction, the chemiluminescent signals produced from the EOC are transferred directly into the sensors and are converted to electric signals on the detector. The EOC-CIS integrated sensor was capable of detecting a traceable amount of the bacterium (4.22 × 10(3)CFU/mL), nearly comparable to that adopting a sophisticated detector such as cooled-charge-coupled device, while having greatly reduced dimensions and cost. Upon coupling with immuno-magnetic separation, the sensor showed an additional 67-fold enhancement in the detection limit. Furthermore, a real sample test was carried out for fish muscles inoculated with a sample of 3.3CFU S. typhimurium per 10 g, which was able to be detected earlier than 6h after the onset of pre-enrichment by culture. © 2013 Elsevier B.V. All rights reserved.

  20. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    low noise figure. Especially, an energy resolution of about 400 eV for 5 keV X-rays was obtained for single pixels. The prototypes have then been exposed to gradually increased fluences of neutrons, from 10{sup 13} to 5x10{sup 14} neq/cm{sup 2}. Again laboratory tests allowed to evaluate the signal over noise persistence on the different pixels implemented. Currently our development mostly targets the detection of soft X-rays, with the ambition to develop a pixel sensor matching counting rates as affordable with hybrid pixel sensors, but with an extended sensitivity to low energy and finer pixel about 25 x 25 μm{sup 2}. The original readout architecture proposed relies on a two tiers chip. The first tier consists of a sensor with a modest dynamic in order to insure low noise performances required by sensitivity. The interconnected second tier chip enhances the read-out speed by introducing massive parallelization. Performances reachable with this strategy combining counting and integration will be detailed. (authors)

  1. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Science.gov (United States)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  2. An ultra low noise AC beam transformer for deceleration and diagnostics of low intensity beams

    CERN Document Server

    González, C

    1999-01-01

    The design of a broad band ultra-low noise ferrite loaded AC beam transformer is presented. It is designed for use in the CERN Antiproton Decelerator (AD), where beams of a few 107 charges must be decelerated from 3.5 GeV/c to 100 MeV/c. It is used in the RF beam-phase loop, and for intensity and bunch shape measurements during deceleration. When the beam is debunched for cooling on magnetic flat tops, the pick-up is used for measurements of intensity and momentum distribution by means of longitudinal Schottky scans. When used as Schottky pick-up, the signal to noise ratio should be better by about 40 dB than the existing stripline based longitudinal Schottky pick-up. The integrated design of pick-up and associated low-noise amplifier is presented. The achieved noise performance of a few from 1 to 3 MHz is obtained by attaching a low-noise, high-impedance silicon JFET (junction field effect transistor) amplifier to a high-Q resonant ferrite loaded cavity, and then eliminating the resonant response by low-nois...

  3. Integrated hybrid switched-capacitor converter for LED drivers in 180 nm CMOS

    NARCIS (Netherlands)

    Castellanos Rodriguez, J.; Delos, J.; Hendrix, M.A.M.; Van Roermund, A.; Cantatore, E.

    2016-01-01

    This paper presents a LED driver based on a new Hybrid-Switched Capacitor Converter (H-SCC) operating in the MHz range, which uses the internal pulsed nodes of a Dickson converter and an LC output network to provide output current dimming. The converter is implemented using 5V integrated capacitors

  4. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  5. LNA A 1.9 GHZ low noise amplifier

    Directory of Open Access Journals (Sweden)

    Jorge Julián Moreno-Rubio

    2006-12-01

    Full Text Available This paper shows the design, the simulation, and the layout from a low noise amplifier (LNA, designed with and approximate band from 25 to 80 MHz. The design results of the matching neworks are shown, its noise figure, its available and transduced gain according to its non lineal model (TOM, the DC network, crash inductors and matching capacitors with the large impedance transmission lines.

  6. Integration of Radiation-Hard Magnetic Random Access Memory with CMOS ICs

    CERN Document Server

    Cerjan, C J

    2000-01-01

    The research undertaken in this LDRD-funded project addressed the joint development of magnetic material-based nonvolatile, radiation-hard memory cells with Sandia National Laboratory. Specifically, the goal of this project was to demonstrate the intrinsic radiation-hardness of Giant Magneto-Resistive (GMR) materials by depositing representative alloy combinations upon radiation-hardened silicon-based integrated circuits. All of the stated goals of the project were achieved successfully. The necessary films were successfully deposited upon typical integrated circuits; the materials retained their magnetic field response at the highest radiation doses; and a patterning approach was developed that did not degrade the as-fabricated properties of the underlying circuitry. These results establish the feasibility of building radiation-hard magnetic memory cells.

  7. Micromachined thin-film sensors for SOI-CMOS co-integration

    CERN Document Server

    Laconte, Jean; Raskin, Jean-Pierre

    2006-01-01

    Co-integration of MEMS and MOS in SOI technology is promising and well demonstrated hereThe impact of Micromachining on SOI devices is deeply analyzed for the first timeInclude extensive TMAH etching, residual stress, microheaters, gas-flow sensors reviewResidual stresses in thin films need to be more and more monitored in MEMS designsTMAH micromachining is an attractive alternative to KOH.

  8. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Liang, Z., E-mail: zhijun.liang@cern.ch [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Institute of High Energy Physics, Beijing (China); Affolder, A. [University of Liverpool (United Kingdom); Arndt, K. [University of Oxford (United Kingdom); Bates, R. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Benoit, M.; Di Bello, F. [University of Geneva (Switzerland); Blue, A. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Bortoletto, D. [University of Oxford (United Kingdom); Buckland, M. [University of Liverpool (United Kingdom); CERN, European Center for Nuclear Research (Switzerland); Buttar, C. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Caragiulo, P. [SLAC National Accelerator Laboratory (United States); Das, D.; Dopke, J. [Rutherford Appleton Laboratory, Didcot (United Kingdom); Dragone, A. [SLAC National Accelerator Laboratory (United States); Ehrler, F. [Karlsruhe Institute of Technology (Germany); Fadeyev, V.; Galloway, Z.; Grabas, H. [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Gregor, I.M. [Deutsches Elektronen-Synchrotron (Germany); Grenier, P. [SLAC National Accelerator Laboratory (United States); and others

    2016-09-21

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  9. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  10. CMOS-based carbon nanotube pass-transistor logic integrated circuits

    Science.gov (United States)

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-01-01

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

  11. Low-power low-noise mixed-mode VLSI ASIC for infinite dynamic range imaging applications

    Science.gov (United States)

    Turchetta, Renato; Hu, Y.; Zinzius, Y.; Colledani, C.; Loge, A.

    1998-11-01

    Solid state solutions for imaging are mainly represented by CCDs and, more recently, by CMOS imagers. Both devices are based on the integration of the total charge generated by the impinging radiation, with no processing of the single photon information. The dynamic range of these devices is intrinsically limited by the finite value of noise. Here we present the design of an architecture which allows efficient, in-pixel, noise reduction to a practically zero level, thus allowing infinite dynamic range imaging. A detailed calculation of the dynamic range is worked out, showing that noise is efficiently suppressed. This architecture is based on the concept of single-photon counting. In each pixel, we integrate both the front-end, low-noise, low-power analog part and the digital part. The former consists of a charge preamplifier, an active filter for optimal noise bandwidth reduction, a buffer and a threshold comparator, and the latter is simply a counter, which can be programmed to act as a normal shift register for the readout of the counters' contents. Two different ASIC's based on this concept have been designed for different applications. The first one has been optimized for silicon edge-on microstrips detectors, used in a digital mammography R and D project. It is a 32-channel circuit, with a 16-bit binary static counter.It has been optimized for a relatively large detector capacitance of 5 pF. Noise has been measured to be equal to 100 + 7*Cd (pF) electron rms with the digital part, showing no degradation of the noise performances with respect to the design values. The power consumption is 3.8mW/channel for a peaking time of about 1 microsecond(s) . The second circuit is a prototype for pixel imaging. The total active area is about (250 micrometers )**2. The main differences of the electronic architecture with respect to the first prototype are: i) different optimization of the analog front-end part for low-capacitance detectors, ii) in- pixel 4-bit comparator

  12. Interface Design for CMOS-Integrated Electrochemical Impedance Spectroscopy (EIS Biosensors

    Directory of Open Access Journals (Sweden)

    Arjang Hassibi

    2012-10-01

    Full Text Available Electrochemical Impedance Spectroscopy (EIS is a powerful electrochemical technique to detect biomolecules. EIS has the potential of carrying out label-free and real-time detection, and in addition, can be easily implemented using electronic integrated circuits (ICs that are built through standard semiconductor fabrication processes. This paper focuses on the various design and optimization aspects of EIS ICs, particularly the bio-to-semiconductor interface design. We discuss, in detail, considerations such as the choice of the electrode surface in view of IC manufacturing, surface linkers, and development of optimal bio-molecular detection protocols. We also report experimental results, using both macro- and micro-electrodes to demonstrate the design trade-offs and ultimately validate our optimization procedures.

  13. Interface design for CMOS-integrated Electrochemical Impedance Spectroscopy (EIS) biosensors.

    Science.gov (United States)

    Manickam, Arun; Johnson, Christopher Andrew; Kavusi, Sam; Hassibi, Arjang

    2012-10-29

    Electrochemical Impedance Spectroscopy (EIS) is a powerful electrochemical technique to detect biomolecules. EIS has the potential of carrying out label-free and real-time detection, and in addition, can be easily implemented using electronic integrated circuits (ICs) that are built through standard semiconductor fabrication processes. This paper focuses on the various design and optimization aspects of EIS ICs, particularly the bio-to-semiconductor interface design. We discuss, in detail, considerations such as the choice of the electrode surface in view of IC manufacturing, surface linkers, and development of optimal bio-molecular detection protocols. We also report experimental results, using both macro- and micro-electrodes to demonstrate the design trade-offs and ultimately validate our optimization procedures.

  14. Neutron absorbed dose in a pacemaker CMOS

    International Nuclear Information System (INIS)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

    2012-01-01

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

  15. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  16. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  17. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  18. Design, Characterization and Analysis of a 0.35 μm CMOS SPAD

    Directory of Open Access Journals (Sweden)

    Khalil Jradi

    2014-12-01

    Full Text Available Most of the works about single-photon detectors rely on Single Photon Avalanche Diodes (SPADs designed with dedicated technological processes in order to achieve single-photon sensitivity and excellent timing resolution. Instead, this paper focuses on the implementation of high-performance SPADs detectors manufactured in a standard 0.35-micron opto-CMOS technology provided by AMS. We propose a series of low-noise SPADs designed with a variable pitch from 20 µm down to 5 µm. This opens the further way to the integration of large arrays of optimized SPAD pixels with pitch of a few micrometers in order to provide high-resolution single-photon imagers. We experimentally demonstrate that a 20-micron SPAD appears as the most relevant detector in terms of Signal-to-Noise ratio, enabling emergence of large arrays of SPAD.

  19. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2003-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved....... A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0...

  20. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-03-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  1. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa; Smith, Casey Eben; Harris, Harlan Rusty; Young, Chadwin; Tseng, Hsinghuang; Jammy, Rajarao

    2010-01-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  2. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    International Nuclear Information System (INIS)

    Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan

    2009-01-01

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm 2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  3. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    Energy Technology Data Exchange (ETDEWEB)

    Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-01-15

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 mum RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm{sup 2} and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  4. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  5. Obtaining and Estimating Low Noise Floors in Vibration Sensors

    DEFF Research Database (Denmark)

    Brincker, Rune; Larsen, Jesper Abildgaard

    2007-01-01

    For some applications like seismic applications and measuring ambient vibrations in structures, it is essential that the noise floors of the sensors and other system components are low and known to the user. Some of the most important noise sources are reviewed and it is discussed how the sensor...... can be designed in order to obtain a low noise floor. Techniques to estimate the noise floors for sensors are reviewed and are demonstrated on a commercial commonly used sensor for vibration testing. It is illustrated how the noise floor can be calculated using the coherence between simultaneous...

  6. High dynamic range low-noise focal plane readout for VLWIR applications implemented with current mode background subtraction

    Science.gov (United States)

    Yang, Guang; Sun, Chao; Shaw, Timothy; Wrigley, Chris; Peddada, Pavani; Blazejewski, Edward R.; Pain, Bedabrata

    1998-09-01

    Design and operation of a low noise CMOS focal pa;ne readout circuit with ultra-high charge handling capacity is presented. Designed for high-background, VLWIR detector readout, each readout unit cell use an accurate dynamic current memory for automatic subtraction of the dark pedestal in current domain enabling measurement of small signals 85 dB below the dark level. The redout circuit operates with low-power dissipation, high linearity, and is capable of handling pedestal currents up to 300 nA. Measurements indicate an effective charge handling capacity of over 5 X 10(superscript 9) charges/pixel with less than 10(superscript 5) electrons of input referred noise.

  7. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  8. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    International Nuclear Information System (INIS)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

    2012-01-01

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

  9. A 60-GHz energy harvesting module with on-chip antenna and switch for co-integration with ULP radios in 65-nm CMOS with fully wireless mm-wave power transfer measurement

    NARCIS (Netherlands)

    Gao, H.; Matters - Kammerer, M.; Harpe, P.J.A.; Milosevic, D.; Roermund, van A.H.M.; Linnartz, J.P.M.G.; Baltus, P.G.M.

    2014-01-01

    In this paper the architecture and performance of a co-integrated 60 GHz on-chip wireless energy harvester and ultra-low power (ULP) radio in 65-nm CMOS are discussed. Integration of an on-chip antenna with wireless power receiver and wireless data transfer module is the crucial next step to achieve

  10. Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

    Science.gov (United States)

    Manghisoni, M.; Comotti, D.; Gaioni, L.; Lodola, L.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.

    2015-04-01

    This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

  11. 5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

    Science.gov (United States)

    Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

  12. A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

    Directory of Open Access Journals (Sweden)

    Ming-Zhi Yang

    2013-03-01

    Full Text Available The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

  13. Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gan, Bo; Wei, Tingcun; Gao, Wu; Liu, Hui; Hu, Yann [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an (China)

    2015-07-01

    Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of the whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a

  14. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  15. Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

    Science.gov (United States)

    Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

    2012-07-01

    In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

  16. Investigation on thermodynamics of ion-slicing of GaN and heterogeneously integrating high-quality GaN films on CMOS compatible Si(100) substrates.

    Science.gov (United States)

    Huang, Kai; Jia, Qi; You, Tiangui; Zhang, Runchun; Lin, Jiajie; Zhang, Shibin; Zhou, Min; Zhang, Bo; Yu, Wenjie; Ou, Xin; Wang, Xi

    2017-11-08

    Die-to-wafer heterogeneous integration of single-crystalline GaN film with CMOS compatible Si(100) substrate using the ion-cutting technique has been demonstrated. The thermodynamics of GaN surface blistering is in-situ investigated via a thermal-stage optical microscopy, which indicates that the large activation energy (2.5 eV) and low H ions utilization ratio (~6%) might result in the extremely high H fluence required for the ion-slicing of GaN. The crystalline quality, surface topography and the microstructure of the GaN films are characterized in detail. The full width at half maximum (FWHM) for GaN (002) X-ray rocking curves is as low as 163 arcsec, corresponding to a density of threading dislocation of 5 × 10 7  cm -2 . Different evolution of the implantation-induced damage was observed and a relationship between the damage evolution and implantation-induced damage is demonstrated. This work would be beneficial to understand the mechanism of ion-slicing of GaN and to provide a platform for the hybrid integration of GaN devices with standard Si CMOS process.

  17. UV lithography-based protein patterning on silicon: Towards the integration of bioactive surfaces and CMOS electronics

    Energy Technology Data Exchange (ETDEWEB)

    Lenci, S., E-mail: silvia.lenci@iet.unipi.it [Dipartimento di Ingegneria dell' Informazione, via G.Caruso 16, Pisa I-56122 (Italy); Tedeschi, L. [Istituto di Fisiologia Clinica - CNR, via G. Moruzzi 1, Pisa I-56124 (Italy); Pieri, F. [Dipartimento di Ingegneria dell' Informazione, via G.Caruso 16, Pisa I-56122 (Italy); Domenici, C. [Istituto di Fisiologia Clinica - CNR, via G. Moruzzi 1, Pisa I-56124 (Italy)

    2011-08-01

    A simple and fast methodology for protein patterning on silicon substrates is presented, providing an insight into possible issues related to the interaction between biological and microelectronic technologies. The method makes use of standard photoresist lithography and is oriented towards the implementation of biosensors containing Complementary Metal-Oxide-Semiconductor (CMOS) conditioning circuitry. Silicon surfaces with photoresist patterns were prepared and hydroxylated by means of resist- and CMOS backend-compatible solutions. Subsequent aminosilane deposition and resist lift-off in organic solvents resulted into well-controlled amino-terminated geometries. The discussion is focused on resist- and CMOS-compatibility problems related to the used chemicals. Some samples underwent gold nanoparticle (Au NP) labeling and Scanning Electron Microscopy (SEM) observation, in order to investigate the quality of the silane layer. Antibodies were immobilized on other samples, which were subsequently exposed to a fluorescently labeled antigen. Fluorescence microscopy observation showed that this method provides spatially selective immobilization of protein layers onto APTES-patterned silicon samples, while preserving protein reactivity inside the desired areas and low non-specific adsorption elsewhere. Strong covalent biomolecule binding was achieved, giving stable protein layers, which allows stringent binding conditions and a good binding specificity, really useful for biosensing.

  18. A Wireless Fiber Photometry System Based on a High-Precision CMOS Biosensor With Embedded Continuous-Time Modulation.

    Science.gov (United States)

    Khiarak, Mehdi Noormohammadi; Martianova, Ekaterina; Bories, Cyril; Martel, Sylvain; Proulx, Christophe D; De Koninck, Yves; Gosselin, Benoit

    2018-06-01

    Fluorescence biophotometry measurements require wide dynamic range (DR) and high-sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of noise and high-background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new biophotometry sensor merging two individual building blocks, namely a low-noise sensing front-end and a order continuous-time modulator (CTSDM), into a single module for enabling high-sensitivity and high energy-efficiency photo-sensing. In particular, a differential CMOS photodetector associated with a differential capacitive transimpedance amplifier-based sensing front-end is merged with an incremental order 1-bit CTSDM to achieve a large DR, low hardware complexity, and high-energy efficiency. The sensor leverages a hardware sharing strategy to simplify the implementation and reduce power consumption. The proposed CMOS biosensor is integrated within a miniature wireless head mountable prototype for enabling biophotometry with a single implantable fiber in the brain of live mice. The proposed biophotometry sensor is implemented in a 0.18- CMOS technology, consuming from a 1.8- supply voltage, while achieving a peak dynamic range of over a 50- input bandwidth, a sensitivity of 24 mV/nW, and a minimum detectable current of 2.46- at a 20- sampling rate.

  19. An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

    Science.gov (United States)

    Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

    2012-12-17

    An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

  20. Low noise amplifier for ZnS(Ag) scintillation chamber

    International Nuclear Information System (INIS)

    Do Hoang Cuong

    1998-01-01

    A new pulse amplifier that can be used with standard photomultiplier tubes coupled with Zn(Ag) scintillation chamber is presented. The amplifier based on an IC operational amplifier LF 356N consists of a low-noise charge sensitive preamplifier and pulse shaping circuits for optimization of signal to noise ratio. Temperature instability is ≤ 0.05%/ o C. Dynamic range for linear output signals is equal +7 V. The presented amplifier is used in a measuring head for 0.17 L Lucas chambers developed in Department of Nuclear Instruments and Methods of the INCT in laboratory investigations aimed to develop methods and instruments for measurement of radon concentration in the air. The amplifier can also be employed for measurement of ionizing radiation by means of other scintillators coupled to PM tube. The amplifier is followed by a pulse discriminator with adjustable discrimination level. The amplifier output signal and discriminator output pulses are fed to external devices. (author)

  1. Advanced Low-Noise Research Fan Stage Design

    Science.gov (United States)

    Neubert, Robert; Bock, Larry; Malmborg, Eric; Owen-Peer, William

    1997-01-01

    This report describes the design of the Advanced Low-Noise Research Fan stage. The fan is a variable pitch design, which is designed at the cruise pitch condition. Relative to the cruise setting, the blade is closed at takeoff and opened for reverse thrust operation. The fan stage is a split flow design with fan exit guide vanes (FEGVs) and core stators. The fan stage design is combined with a nacelle and engine core duct to form a powered fan/nacelle subscale model. This model is intended for use in combined aerodynamic, acoustic, and structural testing in a wind tunnel. The fan has an outer diameter of 22 in. and a hub-to-tip of 0.426 in., which allows the use of existing NASA fan and cowl force balance and rig drive systems. The design parameters were selected to permit valid acoustic and aerodynamic comparisons with the Pratt & Whitney (P&W) 17- and 22-in. rigs previously tested under NASA contract. The fan stage design is described in detail. The results of the design axisymmetric and Navier-Stokes aerodynamic analysis are presented at the critical design conditions. The structural analysis of the fan rotor and attachment is included. The blade and attachment are predicted to have adequate low-cycle fatigue life and an acceptable operating range without resonant stress or flutter. The stage was acoustically designed with airfoil counts in the FEGV and core stator to minimize noise. A fan/FEGV tone analysis developed separately under NASA contract was used to determine the optimum airfoil counts. The fan stage was matched to the existing nacelle, designed under the previous P&W low-noise contract, to form a fan/nacelle model for wind tunnel testing. It is an axisymmetric nacelle for convenience in testing and analysis. Previous testing confirmed that the nacelle performed as required at various aircraft operating conditions.

  2. Fully Integrated On-Chip Coil in 0.13 μm CMOS for Wireless Power Transfer Through Biological Media.

    Science.gov (United States)

    Zargham, Meysam; Gulak, P Glenn

    2015-04-01

    Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.

  3. A Physics-Based Engineering Methodology for Calculating Soft Error Rates of Bulk CMOS and SiGe Heterojunction Bipolar Transistor Integrated Circuits

    Science.gov (United States)

    Fulkerson, David E.

    2010-02-01

    This paper describes a new methodology for characterizing the electrical behavior and soft error rate (SER) of CMOS and SiGe HBT integrated circuits that are struck by ions. A typical engineering design problem is to calculate the SER of a critical path that commonly includes several circuits such as an input buffer, several logic gates, logic storage, clock tree circuitry, and an output buffer. Using multiple 3D TCAD simulations to solve this problem is too costly and time-consuming for general engineering use. The new and simple methodology handles the problem with ease by simple SPICE simulations. The methodology accurately predicts the measured threshold linear energy transfer (LET) of a bulk CMOS SRAM. It solves for circuit currents and voltage spikes that are close to those predicted by expensive 3D TCAD simulations. It accurately predicts the measured event cross-section vs. LET curve of an experimental SiGe HBT flip-flop. The experimental cross section vs. frequency behavior and other subtle effects are also accurately predicted.

  4. A Fully Integrated Dual-Channel On-Coil CMOS Receiver for Array Coils in 1.5-10.5 T MRI.

    Science.gov (United States)

    Sporrer, Benjamin; Wu, Lianbo; Bettini, Luca; Vogt, Christian; Reber, Jonas; Marjanovic, Josip; Burger, Thomas; Brunner, David O; Pruessmann, Klaas P; Troster, Gerhard; Huang, Qiuting

    2017-12-01

    Magnetic resonance imaging (MRI) is among the most important medical imaging modalities. Coil arrays and receivers with high channel counts (16 and more) have to be deployed to obtain the image quality and acquisition speed required by modern clinical protocols. In this paper, we report the theoretical analysis, the system-level design, and the circuit implementation of the first receiver IC (RXIC) for clinical MRI fully integrated in a modern CMOS technology. The dual-channel RXIC sits directly on the sensor coil, thus eliminating any RF cable otherwise required to transport the information out of the magnetic field. The first stage LNA was implemented using a noise-canceling architecture providing a highly reflective input used to decouple the individual channels of the array. Digitization is performed directly on-chip at base-band by means of a delta-sigma modulator, allowing the subsequent optical transmission of data. The presented receiver, implemented in a CMOS technology, is compatible with MRI scanners up to . It reaches sub- noise figure for MRI units and features a dynamic range up to at a power consumption below per channel, with an area occupation of . Mounted on a small-sized printed circuit board (PCB), the receiver IC has been employed in a commercial MRI scanner to acquire in-vivo images matching the quality of traditional systems, demonstrating the first step toward multichannel wearable MRI array coils.

  5. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  6. Input Stage for Low-Voltage, Low-Noise Preamplifiers Based on a Floating-Gate MOS Transistor

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe degradat......A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe...... degradation of the performance of the circuit and without the need for a repeating programming. In this way the noise originating from any resistance previously used for the definition of the operating point is avoided completely and, moreover, by avoiding the input high-pass filter both the saturation...

  7. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal; Elshurafa, Amro M.; Mohammad, Mohammad Ali; Nelson-Fitzpatrick, Nathan E.; Evoy, S.

    2012-01-01

    . The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly

  8. Development of CMOS MEMS inductive type tactile sensor with the integration of chrome steel ball force interface

    Science.gov (United States)

    Yeh, Sheng-Kai; Chang, Heng-Chung; Fang, Weileun

    2018-04-01

    This study presents an inductive tactile sensor with a chrome steel ball sensing interface based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC 0.18 µm 1P6M CMOS process). The tactile senor has a deformable polymer layer as the spring of the device and no fragile suspended thin film structures are required. As a tactile force is applied on the chrome steel ball, the polymer would deform. The distance between the chrome steel ball and the sensing coil would changed. Thus, the tactile force can be detected by the inductance change of the sensing coil. In short, the chrome steel ball acts as a tactile bump as well as the sensing interface. Experimental results show that the proposed inductive tactile sensor has a sensing range of 0-1.4 N with a sensitivity of 9.22(%/N) and nonlinearity of 2%. Preliminary wireless sensing test is also demonstrated. Moreover, the influence of the process and material issues on the sensor performances have also been investigated.

  9. Evaluation of 320x240 pixel LEC GaAs Schottky barrier X-ray imaging arrays, hybridized to CMOS readout circuit based on charge integration

    CERN Document Server

    Irsigler, R; Alverbro, J; Borglind, J; Froejdh, C; Helander, P; Manolopoulos, S; O'Shea, V; Smith, K

    1999-01-01

    320x240 pixels GaAs Schottky barrier detector arrays were fabricated, hybridized to silicon readout circuits, and subsequently evaluated. The detector chip was based on semi-insulating LEC GaAs material. The square shaped pixel detector elements were of the Schottky barrier type and had a pitch of 38 mu m. The GaAs wafers were thinned down prior to the fabrication of the ohmic back contact. After dicing, the chips were indium bump, flip-chip bonded to CMOS readout circuits based on charge integration, and finally evaluated. A bias voltage between 50 and 100 V was sufficient to operate the detector. Results on I-V characteristics, noise behaviour and response to X-ray radiation are presented. Images of various objects and slit patterns were acquired by using a standard dental imaging X-ray source. The work done was a part of the XIMAGE project financed by the European Community (Brite-Euram). (author)

  10. Ultra-low noise miniaturized neural amplifier with hardware averaging.

    Science.gov (United States)

    Dweiri, Yazan M; Eggers, Thomas; McCallum, Grant; Durand, Dominique M

    2015-08-01

    Peripheral nerves carry neural signals that could be used to control hybrid bionic systems. Cuff electrodes provide a robust and stable interface but the recorded signal amplitude is small (concept of hardware averaging to nerve recordings obtained with cuff electrodes. An optimization procedure is developed to minimize noise and power simultaneously. The novel design was based on existing neural amplifiers (Intan Technologies, LLC) and is validated with signals obtained from the FINE in chronic dog experiments. We showed that hardware averaging leads to a reduction in the total recording noise by a factor of 1/√N or less depending on the source resistance. Chronic recording of physiological activity with FINE using the presented design showed significant improvement on the recorded baseline noise with at least two parallel operation transconductance amplifiers leading to a 46.1% reduction at N = 8. The functionality of these recordings was quantified by the SNR improvement and shown to be significant for N = 3 or more. The present design was shown to be capable of generating hardware averaging on noise improvement for neural recording with cuff electrodes, and can accommodate the presence of high source impedances that are associated with the miniaturized contacts and the high channel count in electrode arrays. This technique can be adopted for other applications where miniaturized and implantable multichannel acquisition systems with ultra-low noise and low power are required.

  11. Wide Band Low Noise Love Wave Magnetic Field Sensor System.

    Science.gov (United States)

    Kittmann, Anne; Durdaut, Phillip; Zabel, Sebastian; Reermann, Jens; Schmalz, Julius; Spetzler, Benjamin; Meyners, Dirk; Sun, Nian X; McCord, Jeffrey; Gerken, Martina; Schmidt, Gerhard; Höft, Michael; Knöchel, Reinhard; Faupel, Franz; Quandt, Eckhard

    2018-01-10

    We present a comprehensive study of a magnetic sensor system that benefits from a new technique to substantially increase the magnetoelastic coupling of surface acoustic waves (SAW). The device uses shear horizontal acoustic surface waves that are guided by a fused silica layer with an amorphous magnetostrictive FeCoSiB thin film on top. The velocity of these so-called Love waves follows the magnetoelastically-induced changes of the shear modulus according to the magnetic field present. The SAW sensor is operated in a delay line configuration at approximately 150 MHz and translates the magnetic field to a time delay and a related phase shift. The fundamentals of this sensor concept are motivated by magnetic and mechanical simulations. They are experimentally verified using customized low-noise readout electronics. With an extremely low magnetic noise level of ≈100 pT/[Formula: see text], a bandwidth of 50 kHz and a dynamic range of 120 dB, this magnetic field sensor system shows outstanding characteristics. A range of additional measures to further increase the sensitivity are investigated with simulations.

  12. A compact, multichannel, and low noise arbitrary waveform generator.

    Science.gov (United States)

    Govorkov, S; Ivanov, B I; Il'ichev, E; Meyer, H-G

    2014-05-01

    A new type of high functionality, fast, compact, and easy programmable arbitrary waveform generator for low noise physical measurements is presented. The generator provides 7 fast differential waveform channels with a maximum bandwidth up to 200 MHz frequency. There are 6 fast pulse generators on the generator board with 78 ps time resolution in both duration and delay, 3 of them with amplitude control. The arbitrary waveform generator is additionally equipped with two auxiliary slow 16 bit analog-to-digital converters and four 16 bit digital-to-analog converters for low frequency applications. Electromagnetic shields are introduced to the power supply, digital, and analog compartments and with a proper filter design perform more than 110 dB digital noise isolation to the output signals. All the output channels of the board have 50 Ω SubMiniature version A termination. The generator board is suitable for use as a part of a high sensitive physical equipment, e.g., fast read out and manipulation of nuclear magnetic resonance or superconducting quantum systems and any other application, which requires electromagnetic interference free fast pulse and arbitrary waveform generation.

  13. A high and low noise model for strong motion accelerometers

    Science.gov (United States)

    Clinton, J. F.; Cauzzi, C.; Olivieri, M.

    2010-12-01

    We present reference noise models for high-quality strong motion accelerometer installations. We use continuous accelerometer data acquired by the Swiss Seismological Service (SED) since 2006 and other international high-quality accelerometer network data to derive very broadband (50Hz-100s) high and low noise models. The proposed noise models are compared to the Peterson (1993) low and high noise models designed for broadband seismometers; the datalogger self-noise; background noise levels at existing Swiss strong motion stations; and typical earthquake signals recorded in Switzerland and worldwide. The standard strong motion station operated by the SED consists of a Kinemetrics Episensor (2g clip level; flat acceleration response from 200 Hz to DC; insulated sensor / datalogger systems placed in vault quality sites. At all frequencies, there is at least one order of magnitude between the ALNM and the AHNM; at high frequencies (> 1Hz) this extends to 2 orders of magnitude. This study provides remarkable confirmation of the capability of modern strong motion accelerometers to record low-amplitude ground motions with seismic observation quality. In particular, an accelerometric station operating at the ALNM is capable of recording the full spectrum of near source earthquakes, out to 100 km, down to M2. Of particular interest for the SED, this study provides acceptable noise limits for candidate sites for the on-going Strong Motion Network modernisation.

  14. A compact, multichannel, and low noise arbitrary waveform generator

    International Nuclear Information System (INIS)

    Govorkov, S.; Ivanov, B. I.; Il'ichev, E.; Meyer, H.-G.

    2014-01-01

    A new type of high functionality, fast, compact, and easy programmable arbitrary waveform generator for low noise physical measurements is presented. The generator provides 7 fast differential waveform channels with a maximum bandwidth up to 200 MHz frequency. There are 6 fast pulse generators on the generator board with 78 ps time resolution in both duration and delay, 3 of them with amplitude control. The arbitrary waveform generator is additionally equipped with two auxiliary slow 16 bit analog-to-digital converters and four 16 bit digital-to-analog converters for low frequency applications. Electromagnetic shields are introduced to the power supply, digital, and analog compartments and with a proper filter design perform more than 110 dB digital noise isolation to the output signals. All the output channels of the board have 50 Ω SubMiniature version A termination. The generator board is suitable for use as a part of a high sensitive physical equipment, e.g., fast read out and manipulation of nuclear magnetic resonance or superconducting quantum systems and any other application, which requires electromagnetic interference free fast pulse and arbitrary waveform generation

  15. Low-noise humidity controller for imaging water mediated processes in atomic force microscopy

    Energy Technology Data Exchange (ETDEWEB)

    Gaponenko, I., E-mail: iaroslav.gaponenko@unige.ch; Gamperle, L.; Herberg, K.; Muller, S. C.; Paruch, P. [DQMP, University of Geneva, 24 Quai E. Ansermet, 1211 Geneva 4 (Switzerland)

    2016-06-15

    We demonstrate the construction of a novel low-noise continuous flow humidity controller and its integration with a commercial variable-temperature atomic force microscope fluid cell, allowing precise control of humidity and temperature at the sample during nanoscale measurements. Based on wet and dry gas mixing, the design allows a high mechanical stability to be achieved by means of an ultrasonic atomiser for the generation of water-saturated gas, improving upon previous bubbler-based architectures. Water content in the flow is measured both at the inflow and outflow of the fluid cell, enabling the monitoring of water condensation and icing, and allowing controlled variation of the sample temperature independently of the humidity. To benchmark the performance of the controller, the results of detailed noise studies and time-based imaging of the formation of ice layers on highly oriented pyrolytic graphite are shown.

  16. A single-to-differential low-noise amplifier with low differential output imbalance

    International Nuclear Information System (INIS)

    Duan Lian; Ma Chengyan; He Xiaofeng; Ye Tianchun; Huang Wei; Jin Yuhua

    2012-01-01

    This paper presents a single-ended input differential output low-noise amplifier intended for GPS applications. We propose a method to reduce the gain/amplitude and phase imbalance of a differential output exploiting the inductive coupling of a transformer or center-tapped differential inductor. A detailed analysis of the theory of imbalance reduction, as well as a discussion on the principle of choosing the dimensions of a transformer, are given. An LNA has been implemented using TSMC 0.18 μm technology with ESD-protected. Measurement on board shows a voltage gain of 24.6 dB at 1.575 GHz and a noise figure of 3.2 dB. The gain imbalance is below 0.2 dB and phase imbalance is less than 2 degrees. The LNA consumes 5.2 mA from a 1.8 V supply. (semiconductor integrated circuits)

  17. Low-noise humidity controller for imaging water mediated processes in atomic force microscopy

    Science.gov (United States)

    Gaponenko, I.; Gamperle, L.; Herberg, K.; Muller, S. C.; Paruch, P.

    2016-06-01

    We demonstrate the construction of a novel low-noise continuous flow humidity controller and its integration with a commercial variable-temperature atomic force microscope fluid cell, allowing precise control of humidity and temperature at the sample during nanoscale measurements. Based on wet and dry gas mixing, the design allows a high mechanical stability to be achieved by means of an ultrasonic atomiser for the generation of water-saturated gas, improving upon previous bubbler-based architectures. Water content in the flow is measured both at the inflow and outflow of the fluid cell, enabling the monitoring of water condensation and icing, and allowing controlled variation of the sample temperature independently of the humidity. To benchmark the performance of the controller, the results of detailed noise studies and time-based imaging of the formation of ice layers on highly oriented pyrolytic graphite are shown.

  18. Low-noise humidity controller for imaging water mediated processes in atomic force microscopy

    International Nuclear Information System (INIS)

    Gaponenko, I.; Gamperle, L.; Herberg, K.; Muller, S. C.; Paruch, P.

    2016-01-01

    We demonstrate the construction of a novel low-noise continuous flow humidity controller and its integration with a commercial variable-temperature atomic force microscope fluid cell, allowing precise control of humidity and temperature at the sample during nanoscale measurements. Based on wet and dry gas mixing, the design allows a high mechanical stability to be achieved by means of an ultrasonic atomiser for the generation of water-saturated gas, improving upon previous bubbler-based architectures. Water content in the flow is measured both at the inflow and outflow of the fluid cell, enabling the monitoring of water condensation and icing, and allowing controlled variation of the sample temperature independently of the humidity. To benchmark the performance of the controller, the results of detailed noise studies and time-based imaging of the formation of ice layers on highly oriented pyrolytic graphite are shown.

  19. Studies of the LBL CMOS integrated amplifier/discriminator for randomly timed inputs from fixed target experiments

    International Nuclear Information System (INIS)

    Russ, J.S.; Yarema, R.J.; Zimmerman, T.

    1988-12-01

    A group at Lawrence Berkeley Laboratory has reported an elegant CMOS VLSI circuit for amplifying, discriminating, and encoding the signals from highly-segmented charge output devices, e.g., silicon strip detectors or pad readout structures in gaseous detectors. The design exploits switched capacitor circuits and the well-known time structure of data acquisition in colliding beam accelerators to cancel leakage effects and switching noise. For random inputs, these methods are not directly applicable. However, the high speed of the reset switches makes possible a mode of operation for fixed target experiments that uses fast resets to erase unwanted data from random triggers. Data acquisition in this mode has been performed. Details of operation and measurements of noise and rate capability will be presented. 8 refs., 6 figs

  20. A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

    International Nuclear Information System (INIS)

    Wang Jingchao; Zhang Chun; Wang Zhihua

    2010-01-01

    A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks-including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU-in a 0.18 μm CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 x 3.8 mm 2 including pads. (semiconductor integrated circuits)

  1. A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 {mu}m CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Wang Jingchao; Zhang Chun; Wang Zhihua, E-mail: wangjc@gmail.co [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2010-08-15

    A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks-including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU-in a 0.18 {mu}m CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 x 3.8 mm{sup 2} including pads. (semiconductor integrated circuits)

  2. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  3. Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

    CERN Document Server

    Gromov, V; van der Graaf, H

    2007-01-01

    The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise.

  4. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  5. InGaAsP Mach-Zehnder interferometer optical modulator monolithically integrated with InGaAs driver MOSFET on a III-V CMOS photonics platform.

    Science.gov (United States)

    Park, Jin-Kown; Takagi, Shinichi; Takenaka, Mitsuru

    2018-02-19

    We demonstrated the monolithic integration of a carrier-injection InGaAsP Mach-Zehnder interferometer (MZI) optical modulator and InGaAs metal-oxide-semiconductor field-effect transistor (MOSFET) on a III-V-on-insulator (III-V-OI) wafer. A low-resistivity lateral PIN junction was formed along an InGaAsP rib waveguide by Zn diffusion and Ni-InGaAsP alloy, enabling direct driving of the InGaAsP optical modulator by the InGaAs MOSFET. A π phase shift of the InGaAsP optical modulator was obtained through the injection of a drain current from the InGaAs MOSFET with a gate voltage of approximately 1 V. This proof-of-concept demonstration of the monolithic integration of the InGaAsP optical modulator and InGaAs driver MOSFET will enable us to develop high-performance and low-power electronic-photonic integrated circuits on a III-V CMOS photonics platform.

  6. A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

    International Nuclear Information System (INIS)

    Wang Riyan; Li Zhengping; Zhang Weifeng; Zeng Longyue; Huang Jiwei

    2012-01-01

    A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, −7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply. (semiconductor integrated circuits)

  7. Low-noise readout circuit for SWIR focal plane arrays

    Science.gov (United States)

    Altun, Oguz; Tasdemir, Ferhat; Nuzumlali, Omer Lutfi; Kepenek, Reha; Inceturkmen, Ercihan; Akyurek, Fatih; Tunca, Can; Akbulut, Mehmet

    2017-02-01

    This paper reports a 640x512 SWIR ROIC with 15um pixel pitch that is designed and fabricated using 0.18um CMOS process. Main challenge of SWIR ROIC design is related to input circuit due to pixel area and noise limitations. In this design, CTIA with single stage amplifier is utilized as input stage. The pixel design has three pixel gain options; High Gain (HG), Medium Gain (MG), and Low Gain (LG) with corresponding Full-Well-Capacities of 18.7ké, 190ké and 1.56Mé, respectively. According to extracted simulation results, 5.9é noise is achieved at HG mode and 200é is achieved at LG mode of operation. The ROIC can be programmed through an SPI interface. It supports 1, 2 and 4 output modes which enables the user to configure the detector to work at 30, 60 and 120fps frame rates. In the 4 output mode, the total power consumption of the ROIC is less than 120mW. The ROIC is powered from a 3.3V analog supply and allows for an output swing range in excess of 2V. Anti-blooming feature is added to prevent any unwanted blooming effect during readout.

  8. CMOS sensors for atmospheric imaging

    Science.gov (United States)

    Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

    2017-09-01

    Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

  9. GaAs Wideband Low Noise Amplifier Design for Breast Cancer Detection System

    DEFF Research Database (Denmark)

    Yan, Lei; Krozer, Viktor; Delcourt, Sebastien

    2009-01-01

    Modern wideband systems require low-noise receivers with bandwidth approaching 10 GHz. This paper presents ultra-wideband stable low-noise amplifier MMIC with cascode and source follower buffer configuration using GaAs technology. Source degeneration, gate and shunt peaking inductors are used...

  10. Dual-Polarized Antenna Arrays with CMOS Power Amplifiers for SiP Integration at W-Band

    Science.gov (United States)

    Giese, Malte; Vehring, Sönke; Böck, Georg; Jacob, Arne F.

    2017-09-01

    This paper presents requirements and front-end solutions for low-cost communication systems with data rates of 100 Gbit/s. Link budget analyses in different mass-market applications are conducted for that purpose. It proposes an implementation of the front-end as an active antenna array with support for beam steering and polarization multiplexing over the full W-band. The critical system components are investigated and presented. This applies to a transformer coupled power amplifier (PA) in 40 nm bulk CMOS. It shows saturated output power of more than 10 dBm and power-added-efficiency of more than 10 % over the full W-band. Furthermore, the performance of microstrip-to-waveguide transitions is shown exemplarily as an important part of the active antenna as it interfaces active circuitry and antenna in a polymer-and-metal process. The transition test design shows less than 0.9 dB insertion loss and more than 12 dB return loss for the differential transition over the full W-band.

  11. Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Zheng Xie

    2013-01-01

    Full Text Available The intrinsic variability of nanoscale VLSI technology must be taken into account when analyzing circuit designs to predict likely yield. Monte-Carlo- (MC- and quasi-MC- (QMC- based statistical techniques do this by analysing many randomised or quasirandomised copies of circuits. The randomisation must model forms of variability that occur in nano-CMOS technology, including “atomistic” effects without intradie correlation and effects with intradie correlation between neighbouring devices. A major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. The use of principal components analysis, behavioural modeling, and an implementation of “Statistical Blockade” (SB is shown to be capable of achieving significant reduction in the computational costs. A computation time reduction of 98.7% was achieved for a commonly used asynchronous circuit element. Replacing MC by QMC analysis can achieve further computation reduction, and this is illustrated for more complex circuits, with the results being compared with those of transistor-level simulations. The “yield prediction” analysis of SRAM arrays is taken as a case study, where the arrays contain up to 1536 transistors modelled using parameters appropriate to 35 nm technology. It is reported that savings of up to 99.85% in computation time were obtained.

  12. Fully Integrated Linear Single Photon Avalanche Diode (SPAD) Array with Parallel Readout Circuit in a Standard 180 nm CMOS Process

    Science.gov (United States)

    Isaak, S.; Bull, S.; Pitter, M. C.; Harrison, Ian.

    2011-05-01

    This paper reports on the development of a SPAD device and its subsequent use in an actively quenched single photon counting imaging system, and was fabricated in a UMC 0.18 μm CMOS process. A low-doped p- guard ring (t-well layer) encircling the active area to prevent the premature reverse breakdown. The array is a 16×1 parallel output SPAD array, which comprises of an active quenched SPAD circuit in each pixel with the current value being set by an external resistor RRef = 300 kΩ. The SPAD I-V response, ID was found to slowly increase until VBD was reached at excess bias voltage, Ve = 11.03 V, and then rapidly increase due to avalanche multiplication. Digital circuitry to control the SPAD array and perform the necessary data processing was designed in VHDL and implemented on a FPGA chip. At room temperature, the dark count was found to be approximately 13 KHz for most of the 16 SPAD pixels and the dead time was estimated to be 40 ns.

  13. CMOS Analog IC Design: Fundamentals

    OpenAIRE

    Bruun, Erik

    2018-01-01

    This book is intended for use as the main textbook for an introductory course in CMOS analog integrated circuit design. It is aimed at electronics engineering students who have followed basic courses in mathematics, physics, circuit theory, electronics and signal processing. It takes the students directly from a basic level to a level where they can start working on simple analog IC design projects or continue their studies using more advanced textbooks in the field. A distinct feature of thi...

  14. Integration of an optical CMOS sensor with a microfluidic channel allows a sensitive readout for biological assays in point-of-care tests.

    Science.gov (United States)

    Van Dorst, Bieke; Brivio, Monica; Van Der Sar, Elfried; Blom, Marko; Reuvekamp, Simon; Tanzi, Simone; Groenhuis, Roelf; Adojutelegan, Adewole; Lous, Erik-Jan; Frederix, Filip; Stuyver, Lieven J

    2016-04-15

    In this manuscript, a microfluidic detection module, which allows a sensitive readout of biological assays in point-of-care (POC) tests, is presented. The proposed detection module consists of a microfluidic flow cell with an integrated Complementary Metal-Oxide-Semiconductor (CMOS)-based single photon counting optical sensor. Due to the integrated sensor-based readout, the detection module could be implemented as the core technology in stand-alone POC tests, for use in mobile or rural settings. The performance of the detection module was demonstrated in three assays: a peptide, a protein and an antibody detection assay. The antibody detection assay with readout in the detection module proved to be 7-fold more sensitive that the traditional colorimetric plate-based ELISA. The protein and peptide assay showed a lower limit of detection (LLOD) of 200 fM and 460 fM respectively. Results demonstrate that the sensitivity of the immunoassays is comparable with lab-based immunoassays and at least equal or better than current mainstream POC devices. This sensitive readout holds the potential to develop POC tests, which are able to detect low concentrations of biomarkers. This will broaden the diagnostic capabilities at the clinician's office and at patient's home, where currently only the less sensitive lateral flow and dipstick POC tests are implemented. Copyright © 2015 Elsevier B.V. All rights reserved.

  15. CMOS optimization for radiation hardness

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Fossum, J.G.

    1975-01-01

    Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

  16. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-11-15

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

  17. Design of low noise front-end ASIC and DAQ system for CdZnTe detector

    International Nuclear Information System (INIS)

    Luo Jie; Deng Zhi; Liu Yinong

    2012-01-01

    A low noise front-end ASIC has been designed for CdZnTe detector. This chip contains 16 channels and each channel consists of a dual-stage charge sensitive preamplifier, 4th order semi-Gaussian shaper, leakage current compensation (LCC) circuit, discriminator and output buffer. This chip has been fabricated in Chartered 0.35 μm CMOS process, the preliminary results show that it works well. The total channel charge gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μs to 4 μs. The minimum measured ENC at zero input capacitance is 70 e and minimum noise slope is 20 e/pF. The peak detector and derandomizer (PDD) ASIC developed by BNL and an associated USB DAQ board are also introduced in this paper. Two front-end ASICs can be connected to the PDD ASIC on the USB DAQ board and compose a 32 channels DAQ system for CdZnTe detector. (authors)

  18. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation hardened CMOS devices and circuits - LDRD Project (FY99)

    International Nuclear Information System (INIS)

    Myers, David R.; Jessing, Jeffrey R.; Spahn, Olga B.; Shaneyfelt, Marty R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds

  19. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  20. CMOS image sensors: State-of-the-art

    Science.gov (United States)

    Theuwissen, Albert J. P.

    2008-09-01

    This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

  1. Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs

    Directory of Open Access Journals (Sweden)

    Maxim Adrian

    2006-01-01

    Full Text Available This paper presents circuit techniques and power supply partitioning, filtering, and regulation methods aimed at reducing the phase noise and spurious tones in frequency synthesizers operating in large mixed analog-digital system-on-chip (SOC. The different noise and spur coupling mechanisms are presented together with solutions to minimize their impact on the overall PLL phase noise performance. Challenges specific to deep-submicron CMOS integration of multi-GHz PLLs are revealed, while new architectures that address these issues are presented. Layout techniques that help reducing the parasitic noise and spur coupling between digital and analog blocks are described. Combining system-level and circuit-level low noise design methods, low phase noise frequency synthesizers were achieved which are compatible with the demanding nowadays wireless communication standards.

  2. Readout electronics for low dark count pixel detectors based on Geiger mode avalanche photodiodes fabricated in conventional CMOS technologies for future linear colliders

    International Nuclear Information System (INIS)

    Vilella, E.; Arbat, A.; Comerma, A.; Trenado, J.; Alonso, O.; Gascon, D.; Vila, A.; Garrido, L.; Dieguez, A.

    2011-01-01

    High sensitivity and excellent timing accuracy of the Geiger mode avalanche photodiodes make them ideal sensors as pixel detectors for particle tracking in high energy physics experiments to be performed in future linear colliders. Nevertheless, it is well known that these sensors suffer from dark counts and afterpulsing noise, which induce false hits (indistinguishable from event detection) as well as an increase in the necessary area of the readout system. In this work, we present a comparison between APDs fabricated in a high voltage 0.35 μm and a high integration 0.13 μm commercially available CMOS technologies that has been performed to determine which of them best fits the particle collider requirements. In addition, a readout circuit that allows low noise operation is introduced. Experimental characterization of the proposed pixel is also presented in this work.

  3. A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-{mu}m CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Changchun; Wang Zhigong; Shi Si; Guo Yufeng, E-mail: zgwang@seu.edu.c [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

    2010-03-15

    Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-{mu}m CMOS technology. The Pottbaecker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 x 440 {mu}m{sup 2}, and consumes apower of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV It has a pull-in range of 800 MHz, and a phase noise of -111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components. (semiconductor integrated circuits)

  4. A 24 GHz integrated SiGe BiCMOS vital signs detection radar front-end

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Johansen, Tom K.; Zhurbenko, Vitaliy

    2013-01-01

    In this paper a 24 GHz integrated front-end transceiver for vital signs detection (VSD) radars is described. The heterodyne radar transceiver integrates LO buffering and quadrature splitting circuits, up- and down-conversion SSB mixers and two cascaded receiver LNA's. The chip has been manufactured...

  5. Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies

    DEFF Research Database (Denmark)

    Rossi, P.; Svelto, F.; Mazzanti, A.

    2005-01-01

    Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out...... that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used....

  6. Cryo-CMOS Circuits and Systems for Quantum Computing Applications

    NARCIS (Netherlands)

    Patra, B; Incandela, R.M.; van Dijk, J.P.G.; Homulle, H.A.R.; Song, Lin; Shahmohammadi, M.; Staszewski, R.B.; Vladimirescu, A.; Babaie, M.; Sebastiano, F.; Charbon, E.E.E.

    2018-01-01

    A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising

  7. Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

    NARCIS (Netherlands)

    Dutta, Satadal

    2017-01-01

    Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

  8. Development of a low-noise, 4th-order readout ASIC for CdZnTe detectors in gamma spectrometer applications

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Jia, E-mail: jwang@nwpu.edu.cn [School of Computer Science and Engineering, Northwestern Polytechnical University, 127 West Youyixi Road, 710072 Xi' an (China); Su, Lin; Wei, Xiaomin; Zheng, Ran [School of Computer Science and Engineering, Northwestern Polytechnical University, 127 West Youyixi Road, 710072 Xi' an (China); Hu, Yann [IPHC, University of Strasbourg, 23 rue du loess, 67037 Strasbourg Cedex 02 (France)

    2016-09-21

    This paper presents an ASIC readout circuit development, which aims to achieve low noise. In order to compensate the leakage current and improve gain, a dual-stage CSA has been utilized. A 4th-order high-linearity shaper is proposed to obtain a Semi-Gaussian wave and further decrease the noise induced by the leakage current. The ASIC has been designed and fabricated in a standard commercial 2P4M 0.35 μm CMOS process. Die area of one channel is about 1190 μm×147 μm. The input charge range is 1.8 fC. The peaking time can be adjusted from 1 μs to 3 μs. Measured ENC is about 55e{sup −} (rms) at input capacitor of 0 F. The gain is 271 mV/fC at the peaking time of 1 μs.

  9. Evaluation of Low-Noise, Improved-Bearing-Contact Spiral Bevel Gears

    National Research Council Canada - National Science Library

    Lewicki, Davide

    2003-01-01

    .... Experimental tests were performed on the OH-58D helicopter main-rotor transmission in the NASA Glenn 500-hp Helicopter Transmission Test Stand Low-noise, improved-bearing- contact spiral-bevel gears...

  10. Low Cost/Low Noise Variable Pitch Ducted Fan, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — ACI proposes a design for a Propulsor (Low Cost/Low Noise Variable Pitch Ducted Fan) that has wide application in all sectors of Aviation. Propulsor hardware of this...

  11. Low-noise Collision Operators for Particle-in-cell Simulations

    International Nuclear Information System (INIS)

    Lewandowski, J.L.V.

    2005-01-01

    A new method to implement low-noise collision operators in particle-in-cell simulations is presented. The method is based on the fact that relevant collision operators can be included naturally in the Lagrangian formulation that exemplifies the particle-in-cell simulation method. Numerical simulations show that the momentum and energy conservation properties of the simulated plasma associated with the low-noise collision operator are improved as compared with standard collision algorithms based on random numbers

  12. Theoretical analysis of quantum dot amplifiers with high saturation power and low noise figure

    DEFF Research Database (Denmark)

    Berg, Tommy Winther; Mørk, Jesper

    2002-01-01

    Semiconductor quantum dot amplifiers are predicted to exhibit superior characteristics such as high gain, and output power and low noise. The analysis provides criteria and design guidelines for the realization of high quality amplifiers.......Semiconductor quantum dot amplifiers are predicted to exhibit superior characteristics such as high gain, and output power and low noise. The analysis provides criteria and design guidelines for the realization of high quality amplifiers....

  13. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  14. Backside illuminated CMOS-TDI line scan sensor for space applications

    Science.gov (United States)

    Cohen, Omer; Ofer, Oren; Abramovich, Gil; Ben-Ari, Nimrod; Gershon, Gal; Brumer, Maya; Shay, Adi; Shamay, Yaron

    2018-05-01

    A multi-spectral backside illuminated Time Delayed Integration Radiation Hardened line scan sensor utilizing CMOS technology was designed for continuous scanning Low Earth Orbit small satellite applications. The sensor comprises a single silicon chip with 4 independent arrays of pixels where each array is arranged in 2600 columns with 64 TDI levels. A multispectral optical filter whose spectral responses per array are adjustable per system requirement is assembled at the package level. A custom 4T Pixel design provides the required readout speed, low-noise, very low dark current, and high conversion gains. A 2-phase internally controlled exposure mechanism improves the sensor's dynamic MTF. The sensor high level of integration includes on-chip 12 bit per pixel analog to digital converters, on-chip controller, and CMOS compatible voltage levels. Thus, the power consumption and the weight of the supporting electronics are reduced, and a simple electrical interface is provided. An adjustable gain provides a Full Well Capacity ranging from 150,000 electrons up to 500,000 electrons per column and an overall readout noise per column of less than 120 electrons. The imager supports line rates ranging from 50 to 10,000 lines/sec, with power consumption of less than 0.5W per array. Thus, the sensor is characterized by a high pixel rate, a high dynamic range and a very low power. To meet a Latch-up free requirement RadHard architecture and design rules were utilized. In this paper recent electrical and electro-optical measurements of the sensor's Flight Models will be presented for the first time.

  15. Low-noise kinetic inductance traveling-wave amplifier using three-wave mixing

    Energy Technology Data Exchange (ETDEWEB)

    Vissers, M. R.; Erickson, R. P.; Ku, H.-S.; Vale, Leila; Wu, Xian; Hilton, G. C.; Pappas, D. P., E-mail: David.Pappas@NIST.gov [National Institute of Standards and Technology, Boulder, Colorado 80305 (United States)

    2016-01-04

    We have fabricated a wide-bandwidth, high dynamic range, low-noise cryogenic amplifier based on a superconducting kinetic inductance traveling-wave device. The device was made from NbTiN and consisted of a long, coplanar waveguide on a silicon chip. By adding a DC current and an RF pump tone, we are able to generate parametric amplification using three-wave mixing (3WM). The devices exhibit gain of more than 15 dB across an instantaneous bandwidth from 4 to 8 GHz. The total usable gain bandwidth, including both sides of the signal-idler gain region, is more than 6 GHz. The noise referred to the input of the devices approaches the quantum limit, with less than 1 photon excess noise. We compare these results directly to the four-wave mixing amplification mode, i.e., without DC-biasing. We find that the 3WM mode allows operation with the pump at lower RF power and at frequencies far from the signal. We have used this knowledge to redesign the amplifiers to utilize primarily 3WM amplification, thereby allowing for direct integration into large scale qubit and detector applications.

  16. Novel matched amplifiers with low noise positive feedback. Part II: Resistive-capacitive feedback

    Science.gov (United States)

    Bruck, Y.; Zakharenko, V.

    2010-02-01

    This article is a continuation of consideration for an amplifier with resistive positive feedback (RPF) (Bruck (2008), 'Novel Matched LNA with Low Noise Positive Feedback. Part 1: General Features and Resistive Feedback', International Journal of Electronics, 95, 441-456). We propose here new configuration schematics of a transformer-less selective LNA with resistive-capacitive positive feedback (RCPF). A circuit of an amplifier with a transistor connected into a circuit with a common base (CB) configuration is analysed in detail. RCPF and RPF circuits are compared. It is shown that the LNA RCPF provides any pass-band, a good level of input and output matching, a minimum noise temperature which is significantly lower than that of the LNA RPF, a rather high linearity, and stability of amplification. The simulation results and some experimental data for the amplifiers intended for use in the LOFAR radiotelescope (Konovalenko et al. (2003), 'Thirty Element Array Antenna as a Prototype of a Huge Low-Frequency Radio Telescope,' Experimental Astronomy, 16, 149-164; Konovalenko (2007), 'Ukrainian Contribution to LOFAR', A scientific workshop, organised by LOFAR/ASTRON' Emmen, Netherlands, 23-27. http://www.lofar.org/workshop) are given. It is assumed that such devices are of a special interest for high-frequency integral circuits (IC).

  17. Low-noise kinetic inductance traveling-wave amplifier using three-wave mixing

    Science.gov (United States)

    Vissers, M. R.; Erickson, R. P.; Ku, H.-S.; Vale, Leila; Wu, Xian; Hilton, G. C.; Pappas, D. P.

    2016-01-01

    We have fabricated a wide-bandwidth, high dynamic range, low-noise cryogenic amplifier based on a superconducting kinetic inductance traveling-wave device. The device was made from NbTiN and consisted of a long, coplanar waveguide on a silicon chip. By adding a DC current and an RF pump tone, we are able to generate parametric amplification using three-wave mixing (3WM). The devices exhibit gain of more than 15 dB across an instantaneous bandwidth from 4 to 8 GHz. The total usable gain bandwidth, including both sides of the signal-idler gain region, is more than 6 GHz. The noise referred to the input of the devices approaches the quantum limit, with less than 1 photon excess noise. We compare these results directly to the four-wave mixing amplification mode, i.e., without DC-biasing. We find that the 3WM mode allows operation with the pump at lower RF power and at frequencies far from the signal. We have used this knowledge to redesign the amplifiers to utilize primarily 3WM amplification, thereby allowing for direct integration into large scale qubit and detector applications.

  18. Self Oscillating Mixer with Dielectric Resonator for Low Noise Block Application

    Directory of Open Access Journals (Sweden)

    Endon Bharata

    2011-08-01

    Full Text Available In this paper, the development of a self oscillating mixer (SOM as part of a low noise block (LNB for a satellite television receiver is investigated numerically and experimentally. In contrast to other mixers, the developed SOM requires no separate local oscillator as it generates own local oscillator signal. The SOM is developed using a monolithic microwave integrated circuit (MMIC comprised of two bipolar transistors coupled as a Darlington pair and a dielectric resonator to establish a local oscillator signal. The SOM is designed to oscillate at 3.62GHz driven from 50W signal generator. The prototype of SOM is fabricated on a dielectric substrate of glass-reinforced hydrocarbon/ceramic lamination (RO4350B board which has a thickness of 0.762mm and relative permittivity of 3.66. The prototype is then characterized experimentally and exhibits a conversion gain of 8dB with the input and output voltage standing wave ratio (VSWR less than 2 across the 2520MHz to 2670MHz operating frequency band.

  19. A low-noise ac-bridge amplifier for ballistocardiogram measurement on an electronic weighing scale

    International Nuclear Information System (INIS)

    Inan, O T; Kovacs, G T A

    2010-01-01

    Ballistocardiography is a non-invasive technique for evaluating cardiovascular health. This note presents an ac-bridge amplifier for low-noise ballistocardiogram (BCG) recording from a modified weighing scale. The strain gauges in a commercial scale were excited by an ac source—square or sine wave—and the differential output voltage resulting from the BCG was amplified and demodulated synchronously with the excitation waveform. A standard BCG amplifier, with a simple dc-bridge excitation, was also built and the performance was compared to both the square- and sine-wave excited ac-bridge amplifiers. The total input-referred voltage noise (rms) integrated over the relevant BCG bandwidth of 0.3–10 Hz was found to be 30 nV (square wave source) or 25 nV (sine-wave source) for the ac-bridge amplifier and 52 nV for the standard amplifier: an improvement of 4.8 dB or 6 dB, respectively. These correspond to input-referred force noise (rms) values of 5 mN, 4 mN and 8.3 mN. The improvement in SNR was also observed in recorded waveforms from a seated subject whose BCG signal was measured with both dc- and ac-bridge circuits. (note)

  20. Instrumentation for low noise nanopore-based ionic current recording under laser illumination

    Science.gov (United States)

    Roelen, Zachary; Bustamante, José A.; Carlsen, Autumn; Baker-Murray, Aidan; Tabard-Cossa, Vincent

    2018-01-01

    We describe a nanopore-based optofluidic instrument capable of performing low-noise ionic current recordings of individual biomolecules under laser illumination. In such systems, simultaneous optical measurements generally introduce significant parasitic noise in the electrical signal, which can severely reduce the instrument sensitivity, critically hindering the monitoring of single-molecule events in the ionic current traces. Here, we present design rules and describe simple adjustments to the experimental setup to mitigate the different noise sources encountered when integrating optical components to an electrical nanopore system. In particular, we address the contributions to the electrical noise spectra from illuminating the nanopore during ionic current recording and mitigate those effects through control of the illumination source and the use of a PDMS layer on the SiNx membrane. We demonstrate the effectiveness of our noise minimization strategies by showing the detection of DNA translocation events during membrane illumination with a signal-to-noise ratio of ˜10 at 10 kHz bandwidth. The instrumental guidelines for noise minimization that we report are applicable to a wide range of nanopore-based optofluidic systems and offer the possibility of enhancing the quality of synchronous optical and electrical signals obtained during single-molecule nanopore-based analysis.

  1. Applications of the Integrated High-Performance CMOS Image Sensor to Range Finders — from Optical Triangulation to the Automotive Field

    Directory of Open Access Journals (Sweden)

    Joe-Air Jiang

    2008-03-01

    Full Text Available With their significant features, the applications of complementary metal-oxidesemiconductor (CMOS image sensors covers a very extensive range, from industrialautomation to traffic applications such as aiming systems, blind guidance, active/passiverange finders, etc. In this paper CMOS image sensor-based active and passive rangefinders are presented. The measurement scheme of the proposed active/passive rangefinders is based on a simple triangulation method. The designed range finders chieflyconsist of a CMOS image sensor and some light sources such as lasers or LEDs. Theimplementation cost of our range finders is quite low. Image processing software to adjustthe exposure time (ET of the CMOS image sensor to enhance the performance oftriangulation-based range finders was also developed. An extensive series of experimentswere conducted to evaluate the performance of the designed range finders. From theexperimental results, the distance measurement resolutions achieved by the active rangefinder and the passive range finder can be better than 0.6% and 0.25% within themeasurement ranges of 1 to 8 m and 5 to 45 m, respectively. Feasibility tests onapplications of the developed CMOS image sensor-based range finders to the automotivefield were also conducted. The experimental results demonstrated that our range finders arewell-suited for distance measurements in this field.

  2. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  3. A CMOS transconductance-C filter technique for very high frequencies

    NARCIS (Netherlands)

    Nauta, Bram

    1992-01-01

    CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters

  4. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  5. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  6. CMOS foveal image sensor chip

    Science.gov (United States)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  7. CMOS switched current phase-locked loop

    NARCIS (Netherlands)

    Leenaerts, D.M.W.; Persoon, G.G.; Putter, B.M.

    1997-01-01

    The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes

  8. Challenges & Roadmap for Beyond CMOS Computing Simulation.

    Energy Technology Data Exchange (ETDEWEB)

    Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-12-01

    Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

  9. Versatile quantitative phase imaging system applied to high-speed, low noise and multimodal imaging (Conference Presentation)

    Science.gov (United States)

    Federici, Antoine; Aknoun, Sherazade; Savatier, Julien; Wattellier, Benoit F.

    2017-02-01

    Quadriwave lateral shearing interferometry (QWLSI) is a well-established quantitative phase imaging (QPI) technique based on the analysis of interference patterns of four diffraction orders by an optical grating set in front of an array detector [1]. As a QPI modality, this is a non-invasive imaging technique which allow to measure the optical path difference (OPD) of semi-transparent samples. We present a system enabling QWLSI with high-performance sCMOS cameras [2] and apply it to perform high-speed imaging, low noise as well as multimodal imaging. This modified QWLSI system contains a versatile optomechanical device which images the optical grating near the detector plane. Such a device is coupled with any kind of camera by varying its magnification. In this paper, we study the use of a sCMOS Zyla5.5 camera from Andor along with our modified QWLSI system. We will present high-speed live cell imaging, up to 200Hz frame rate, in order to follow intracellular fast motions while measuring the quantitative phase information. The structural and density information extracted from the OPD signal is complementary to the specific and localized fluorescence signal [2]. In addition, QPI detects cells even when the fluorophore is not expressed. This is very useful to follow a protein expression with time. The 10 µm spatial pixel resolution of our modified QWLSI associated to the high sensitivity of the Zyla5.5 enabling to perform high quality fluorescence imaging, we have carried out multimodal imaging revealing fine structures cells, like actin filaments, merged with the morphological information of the phase. References [1]. P. Bon, G. Maucort, B. Wattellier, and S. Monneret, "Quadriwave lateral shearing interferometry for quantitative phase microscopy of living cells," Opt. Express, vol. 17, pp. 13080-13094, 2009. [2] P. Bon, S. Lécart, E. Fort and S. Lévêque-Fort, "Fast label-free cytoskeletal network imaging in living mammalian cells," Biophysical journal, 106

  10. A Discrete Component Low-Noise Preamplifier Readout for a Linear (1x16) SiC Photodiode Array

    Science.gov (United States)

    Kahle, Duncan; Aslam, Shahid; Herrero, Frederico A.; Waczynski, Augustyn

    2016-01-01

    A compact, low-noise and inexpensive preamplifier circuit has been designed and fabricated to optimally readout a common cathode (1x16) channel 4H-SiC Schottky photodiode array for use in ultraviolet experiments. The readout uses an operational amplifier with 10 pF capacitor in the feedback loop in parallel with a low leakage switch for each of the channels. This circuit configuration allows for reiterative sample, integrate and reset. A sampling technique is given to remove Johnson noise, enabling a femtoampere level readout noise performance. Commercial-off-the-shelf acquisition electronics are used to digitize the preamplifier analogue signals. The data logging acquisition electronics has a different integration circuit, which allows the bandwidth and gain to be independently adjusted. Using this readout, photoresponse measurements across the array between spectral wavelengths 200 nm and 370 nm are made to establish the array pixels external quantum efficiency, current responsivity and noise equivalent power.

  11. A discrete component low-noise preamplifier readout for a linear (1×16) SiC photodiode array

    Energy Technology Data Exchange (ETDEWEB)

    Kahle, Duncan [NASA, Goddard Space Flight Center, Detector Systems Branch, Greenbelt, MD 20771 (United States); Aslam, Shahid, E-mail: shahid.aslam-1@nasa.gov [NASA, Goddard Space Flight Center, Planetary Systems Laboratory, Greenbelt, MD 20771 (United States); Herrero, Federico A.; Waczynski, Augustyn [NASA, Goddard Space Flight Center, Detector Systems Branch, Greenbelt, MD 20771 (United States)

    2016-09-11

    A compact, low-noise and inexpensive preamplifier circuit has been designed and fabricated to optimally readout a common cathode (1×16) channel 4H-SiC Schottky photodiode array for use in ultraviolet experiments. The readout uses an operational amplifier with 10 pF capacitor in the feedback loop in parallel with a low leakage switch for each of the channels. This circuit configuration allows for reiterative sample, integrate and reset. A sampling technique is given to remove Johnson noise, enabling a femtoampere level readout noise performance. Commercial-off-the-shelf acquisition electronics are used to digitize the preamplifier analog signals. The data logging acquisition electronics has a different integration circuit, which allows the bandwidth and gain to be independently adjusted. Using this readout, photoresponse measurements across the array between spectral wavelengths 200 nm and 370 nm are made to establish the array pixels external quantum efficiency, current responsivity and noise equivalent power.

  12. Ion traps fabricated in a CMOS foundry

    Energy Technology Data Exchange (ETDEWEB)

    Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  13. Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

    Science.gov (United States)

    Gao, Pingqi; Zhang, Qing

    2014-02-14

    Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

  14. Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film

    International Nuclear Information System (INIS)

    Gao, Pingqi; Zhang, Qing

    2014-01-01

    Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm 2  V −1  s −1 , a subthreshold slope as low as 150 mV  dec −1 , operating gate voltages less than 2 V, on/off ratios larger than 10 4 and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc. (paper)

  15. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  16. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    Energy Technology Data Exchange (ETDEWEB)

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  17. A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

    NARCIS (Netherlands)

    Babaie, M.; Kuo, F.W.; Chen, H; Cho, L.C.; Jou, C.P.; Hsueh, F.L.; Shahmohammadi, M.; Staszewski, R.B.

    2016-01-01

    We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply

  18. Design of low power common-gate low noise amplifier for 2.4 GHz wireless sensor network applications

    International Nuclear Information System (INIS)

    Zhang Meng; Li Zhiqun

    2012-01-01

    This paper presents a differential low power low noise amplifier designed for the wireless sensor network (WSN) in a TSMC 0.18 μm RF CMOS process. A two-stage cross-coupling cascaded common-gate (CG) topology has been designed as the amplifier. The first stage is a capacitive cross-coupling topology. It can reduce the power and noise simultaneously. The second stage is a positive feedback cross-coupling topology, used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA. A differential inductor has been designed as the load to achieve reasonable gain. This inductor has been simulated by the means of momentum electromagnetic simulation in ADS. A 'π' circuit model has been built as the inductor model by iteration in ADS. The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured. The LNA works well centered at 2.44 GHz. The measured gain S 21 is variable with high gain at 16.8 dB and low gain at 1 dB. The NF (noise figure) at high gain mode is 3.6 dB, the input referenced 1 dB compression point (IP1dB) is about −8 dBm and the IIP3 is 2 dBm at low gain mode. The LNA consumes about 1.2 mA current from 1.8 V power supply.

  19. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  20. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  1. Design and validation of the high performance and low noise CQU-DTU-LN1 airfoils

    DEFF Research Database (Denmark)

    Cheng, Jiangtao; Zhu, Wei Jun; Fischer, Andreas

    2014-01-01

    with the blade element momentum theory, the viscous-inviscid XFOIL code and an airfoil self-noise prediction model, an optimization algorithm has been developed for designing the high performance and low noise CQU-DTU-LN1 series of airfoils with targets of maximum power coefficient and low noise emission...... emission between the CQU-DTU-LN118 airfoil and the National Advisory Committee for Aeronautics (NACA) 64618 airfoil, which is used in modern wind turbine blades, are carried out. Copyright © 2013 John Wiley & Sons, Ltd....

  2. Performance of a fast low noise front-end preamplifier for the MAGIC imaging Cherenkov telescope

    International Nuclear Information System (INIS)

    Blanch, O.; Blanchot, G.; Bosman, M.

    1999-01-01

    The observation of high energy cosmic gamma rays with an energy threshold of 15 GeV using the proposed MAGIC ground based air imaging Cherenkov telescope requires the development of new low noise fast preamplifiers for the camera photosensors. The speed and noise performance of a transimpedance preamplifier that resolves the multi photoelectron peaks from a hybrid photomultiplier with a peaking time below 7 ns is presented. The new front-end circuit is designed with RF low noise bipolar transistors and provides fast output pulses that allow for fast trigger settings

  3. 14C autoradiography with a novel wafer scale CMOS Active Pixel Sensor

    International Nuclear Information System (INIS)

    Esposito, M; Wells, K; Anaxagoras, T; Allinson, N M; Larner, J

    2013-01-01

    14 C autoradiography is a well established technique for structural and metabolic analysis of cells and tissues. The most common detection medium for this application is film emulsion, which offers unbeatable spatial resolution due to its fine granularity but at the same time has some limiting drawbacks such as poor linearity and rapid saturation. In recent years several digital detectors have been developed, following the technological transition from analog to digital-based detection systems in the medical and biological field. Even so such digital systems have been greatly limited by the size of their active area (a few square centimeters), which have made them unsuitable for routine use in many biological applications where sample areas are typically ∼ 10–100 cm 2 . The Multidimensional Integrated Intelligent Imaging (MI3-Plus) consortium has recently developed a new large area CMOS Active Pixel Sensor (12.8 cm × 13.1 cm). This detector, based on the use of two different pixel resolutions, is capable of providing simultaneously low noise and high dynamic range on a wafer scale. In this paper we will demonstrate the suitability of this detector for routine beta autoradiography in a comparative approach with widely used film emulsion.

  4. A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

    Science.gov (United States)

    Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

    2016-08-01

    This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

  5. Ultra-low-noise transition edge sensors for the SAFARI L-band on SPICA

    Science.gov (United States)

    Goldie, D. J.; Gao, J. R.; Glowacka, D. M.; Griffin, D. K.; Hijmering, R.; Khosropanah, P.; Jackson, B. D.; Mauskopf, P. D.; Morozov, D.; Murphy, J. A.; Ridder, M.; Trappe, N.; O'Sullivan, C.; Withington, S.

    2012-09-01

    The Far-Infrared Fourier transform spectrometer instrument SAFARI-SPICA which will operate with cooled optics in a low-background space environment requires ultra-sensitive detector arrays with high optical coupling efficiencies over extremely wide bandwidths. In earlier papers we described the design, fabrication and performance of ultra-low-noise Transition Edge Sensors (TESs) operated close to 100mk having dark Noise Equivalent Powers (NEPs) of order 4 × 10-19W/√Hz close to the phonon noise limit and an improvement of two orders of magnitude over TESs for ground-based applications. Here we describe the design, fabrication and testing of 388-element arrays of MoAu TESs integrated with far-infrared absorbers and optical coupling structures in a geometry appropriate for the SAFARI L-band (110 - 210 μm). The measured performance shows intrinsic response time τ ~ 11ms and saturation powers of order 10 fW, and a dark noise equivalent powers of order 7 × 10-19W/√Hz. The 100 × 100μm2 MoAu TESs have transition temperatures of order 110mK and are coupled to 320×320μm2 thin-film β-phase Ta absorbers to provide impedance matching to the incoming fields. We describe results of dark tests (i.e without optical power) to determine intrinsic pixel characteristics and their uniformity, and measurements of the optical performance of representative pixels operated with flat back-shorts coupled to pyramidal horn arrays. The measured and modeled optical efficiency is dominated by the 95Ω sheet resistance of the Ta absorbers, indicating a clear route to achieve the required performance in these ultra-sensitive detectors.

  6. Low noise 874 GHz receivers for the International Submillimetre Airborne Radiometer (ISMAR)

    Science.gov (United States)

    Hammar, A.; Sobis, P.; Drakinskiy, V.; Emrich, A.; Wadefalk, N.; Schleeh, J.; Stake, J.

    2018-05-01

    We report on the development of two 874 GHz receiver channels with orthogonal polarizations for the International Submillimetre Airborne Radiometer. A spline horn antenna and dielectric lens, a Schottky diode mixer circuit, and an intermediate frequency (IF) low noise amplifier circuit were integrated in the same metallic split block housing. This resulted in a receiver mean double sideband (DSB) noise temperature of 3300 K (minimum 2770 K, maximum 3400 K), achieved at an operation temperature of 40 °C and across a 10 GHz wide IF band. A minimum DSB noise temperature of 2260 K at 20 °C was measured without the lens. Three different dielectric lens materials were tested and compared with respect to the radiation pattern and noise temperature. All three lenses were compliant in terms of radiation pattern, but one of the materials led to a reduction in noise temperature of approximately 200 K compared to the others. The loss in this lens was estimated to be 0.42 dB. The local oscillator chains have a power consumption of 24 W and consist of custom-designed Schottky diode quadruplers (5% power efficiency in operation, 8%-9% peak), commercial heterostructure barrier varactor (HBV) triplers, and power amplifiers that are pumped by using a common dielectric resonator oscillator at 36.43 GHz. Measurements of the radiation pattern showed a symmetric main beam lobe with full width half maximum <5° and side lobe levels below -20 dB. Return loss of a prototype of the spline horn and lens was measured using a network analyzer and frequency extenders to 750-1100 GHz. Time-domain analysis of the reflection coefficients shows that the reflections are below -25 dB and are dominated by the external waveguide interface.

  7. CMOS-sensors for energy-resolved X-ray imaging

    International Nuclear Information System (INIS)

    Doering, D.; Amar-Youcef, S.; Deveaux, M.; Linnik, B.; Müntz, C.; Stroth, Joachim; Baudot, J.; Dulinski, W.; Kachel, M.

    2016-01-01

    Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ''color sensitive' X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors

  8. A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

    International Nuclear Information System (INIS)

    Guo Rui; Zhang Haiying

    2012-01-01

    A fully integrated multi-mode multi-band directed-conversion radio frequency (RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented. The front-end employs direct-conversion design, and consists of two differential tunable low noise amplifiers (LNA), a quadrature mixer, and two intermediate frequency (IF) amplifiers. The two independent tunable LNAs are used to cover all the four frequency bands, achieving sufficient low noise and high gain performance with low power consumption. Switched capacitor arrays perform a resonant frequency point calibration for the LNAs. The two LNAs are combined at the driver stage of the mixer, which employs a folded double balanced Gilbert structure, and utilizes PMOS transistors as local oscillator (LO) switches to reduce flicker noise. The front-end has three gain modes to obtain a higher dynamic range. Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface (SPI) module. The front-end is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm 2 . The measured double-sideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply. (semiconductor integrated circuits)

  9. A capacitor cross-coupled common-gate low-noise amplifier

    NARCIS (Netherlands)

    Zhuo, W.; Li, X.; Shekhar, S.; Embabi, S.H.K.; Pineda de Gyvez, J.; Allstot, D.J.; Sanchez-Sinencio, E.

    2005-01-01

    The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET fT, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated

  10. Design of low noise wind turbine blades using Betz and Joukowski concepts

    DEFF Research Database (Denmark)

    Shen, Wen Zhong; Hrgovan, Iva; Okulov, Valery

    2014-01-01

    This paper presents the aerodynamic design of low noise wind turbine blades using Betz and Joukowski concepts. The aerodynamic model is based on Blade Element Momentum theory whereas the aeroacoustic prediction model is based on the BPM model. The investigation is started with a 3MW baseline...

  11. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  12. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  13. Design of a 1 _s real-time low-noise data acquisition for power converters control loop

    CERN Document Server

    AUTHOR|(SzGeCERN)712364; Arpaia, Pasquale; Cerqueira Bastos, Miguel; Martino, Michele

    2015-01-01

    The proof of principle of a real-time data acquisition system to be integrated into a digital control loop for controlling the power converters of the Compact LInear Collider is presented. The system is based on an ultra low noise analogue front-end with 1:1 ppm RMS noise (referred to input), and about 1 _s of real-time delay. After the analogue conditioning, a fully-differential analogue-todigital converter is foreseen. The requirements of this system, directly derived from the accelerator performance, are discussed and translated into design specification. The results obtained by means of Pspice simulations are reported in order to prove that the design is feasible with the proposed architecture. Finally, the results of the experimental validation of the prototype, currently under design, will be included in the final paper.

  14. A 40 GHz fully integrated circuit with a vector network analyzer and a coplanar-line-based detection area for circulating tumor cell analysis using 65 nm CMOS technology

    Science.gov (United States)

    Nakanishi, Taiki; Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

    2018-03-01

    A 40-GHz fully integrated CMOS-based circuit for circulating tumor cells (CTC) analysis, consisting of an on-chip vector network analyzer (VNA) and a highly sensitive coplanar-line-based detection area is presented in this paper. In this work, we introduce a fully integrated architecture that eliminates unwanted parasitic effects. The proposed analyzer was designed using 65 nm CMOS technology, and SPICE and MWS simulations were used to validate its operation. The simulation confirmed that the proposed circuit can measure S-parameter shifts resulting from the addition of various types of tumor cells to the detection area, the data of which are provided in a previous study: the |S 21| values for HepG2, A549, and HEC-1-A cells are -0.683, -0.580, and -0.623 dB, respectively. Additionally, the measurement demonstrated an S-parameters reduction of -25.7% when a silicone resin was put on the circuit. Hence, the proposed system is expected to contribute to cancer diagnosis.

  15. Prevention of CMOS latch-up by gold doping

    International Nuclear Information System (INIS)

    Dawes, W.R.; Derbenwick, G.F.

    1976-01-01

    CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

  16. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  17. CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

    Science.gov (United States)

    Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

    2018-04-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  18. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

    2018-01-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  19. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  20. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  1. CMOS MEMS capacitive absolute pressure sensor

    International Nuclear Information System (INIS)

    Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

    2013-01-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

  2. A 7-13 GHz low-noise tuned optical front-end amplifier for heterodyne transmission system application

    DEFF Research Database (Denmark)

    Ebskamp, Frank; Schiellerup, Gert; Høgdal, Morten

    1991-01-01

    The authors present a 7-13 GHz low-noise bandpass tuned optical front-end amplifier, showing 46±1 dBΩ transimpedance, and a noise spectral density of about 12 pA/√Hz. This is the first time such a flat response and such low noise were obtained simultaneously at these frequencies, without any...

  3. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  4. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  5. Advancement of CMOS Doping Technology in an External Development Framework

    Science.gov (United States)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  6. Low-noise audio amplifiers and preamplifier for use with intrinsic thermocouples

    International Nuclear Information System (INIS)

    Langner, G.C.; Sachs, R.D.; Stewart, F.L.

    1979-03-01

    Two simple, low-noise audio amplifiers and one low-noise preamplifier for use with intrinsic thermocouples were designed, built, and tested. The amplifiers and the preamplifier have different front end designs. One amplifier uses ultralow-noise operational amplifiers; the other amplifier uses a hybrid component. The preamplifier uses ultralow-noise discrete components. The amplifiers' equivalent noise inputs, at maximum gain, are 4.09 nV and 50 nV; the preamplifier's input is 4.05 μV. Their bandwidths are 15 600 Hz, 550 Hz, and 174 kHz, respectively. the amplifiers' equivalent noise inputs were measured from approx. 0 to 100 Hz, whereas the preamplifier's equivalent noise input was measured from approx. 0 to 174 kHz

  7. Magnonic Crystal as a Delay Line for Low-Noise Auto-Oscillator

    Science.gov (United States)

    2015-05-12

    Magnonic crystal as a delay line for low-noise auto-oscillator Elena Bankowski and Thomas Meitzler U.S. Army TARDEC, Warren, Michigan 48397, USA...authors propose to use the magnonic crystal patterned on the YIG magnetic film as an efficient delay line in the feedback loop of tunable auto-oscillator...increasing the thickness of such delay line as compare to the YIG film with no pattern. In turn, use of this magnonic crystal opens a way to improve

  8. Note: A temperature-stable low-noise transimpedance amplifier for microcurrent measurement

    Science.gov (United States)

    Xie, Kai; Shi, Xueyou; Zhao, Kai; Guo, Lixin; Zhang, Hanlu

    2017-02-01

    Temperature stability and noise characteristics often run contradictory in microcurrent (e.g., pA-scale) measurement instruments because low-noise performance requires high-value resistors with relatively poor temperature coefficients. A low-noise transimpedance amplifier with high-temperature stability, which involves an active compensation mechanism to overcome the temperature drift mainly caused by high-value resistors, is presented. The implementation uses a specially designed R-2R compensating network to provide programmable current gain with extra-fine trimming resolution. The temperature drifts of all components (e.g., feedback resistors, operational amplifiers, and the R-2R network itself) are compensated simultaneously. Therefore, both low-temperature drift and ultra-low-noise performance can be achieved. With a current gain of 1011 V/A, the internal current noise density was about 0.4 fA/√Hz, and the average temperature coefficient was 4.3 ppm/K at 0-50 °C. The amplifier module maintains accuracy across a wide temperature range without additional thermal stabilization, and its compact size makes it especially suitable for high-precision, low-current measurement in outdoor environments for applications such as electrochemical emission supervision, air pollution particles analysis, radiation monitoring, and bioelectricity.

  9. A CMOS active pixel sensor system for laboratory- based x-ray diffraction studies of biological tissue

    International Nuclear Information System (INIS)

    Bohndiek, Sarah E; Cook, Emily J; Arvanitis, Costas D; Olivo, Alessandro; Royle, Gary J; Clark, Andy T; Prydderch, Mark L; Turchetta, Renato; Speller, Robert D

    2008-01-01

    X-ray diffraction studies give material-specific information about biological tissue. Ideally, a large area, low noise, wide dynamic range digital x-ray detector is required for laboratory-based x-ray diffraction studies. The goal of this work is to introduce a novel imaging technology, the CMOS active pixel sensor (APS) that has the potential to fulfil all these requirements, and demonstrate its feasibility for coherent scatter imaging. A prototype CMOS APS has been included in an x-ray diffraction demonstration system. An industrial x-ray source with appropriate beam filtration is used to perform angle dispersive x-ray diffraction (ADXRD). Optimization of the experimental set-up is detailed including collimator options and detector operating parameters. Scatter signatures are measured for 11 different materials, covering three medical applications: breast cancer diagnosis, kidney stone identification and bone mineral density calculations. Scatter signatures are also recorded for three mixed samples of known composition. Results are verified using two independent models for predicting the APS scatter signature: (1) a linear systems model of the APS and (2) a linear superposition integral combining known monochromatic scatter signatures with the input polychromatic spectrum used in this case. Cross validation of experimental, modelled and literature results proves that APS are able to record biologically relevant scatter signatures. Coherent scatter signatures are sensitive to multiple materials present in a sample and provide a means to quantify composition. In the future, production of a bespoke APS imager for x-ray diffraction studies could enable simultaneous collection of the transmitted beam and scattered radiation in a laboratory-based coherent scatter system, making clinical transfer of the technique attainable

  10. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation i...... for integration with existing insulator-metal-insu lator plasmonic waveguides as well as novel photonic/electronic hybrid circuits...

  11. CMOS serial link for fully duplexed data communication

    Science.gov (United States)

    Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

    1995-04-01

    This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

  12. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  13. Performance analysis of a low power low noise tunable band pass filter for multiband RF front end

    International Nuclear Information System (INIS)

    Manjula, J.; Malarvizhi, S.

    2014-01-01

    This paper presents a low power tunable active inductor and RF band pass filter suitable for multiband RF front end circuits. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator to reduce the noise voltage. Also, this structure provides possible negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The RF band pass filter is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multiband operation is achieved through the controllable current source. The designed active inductor and RF band pass filter are simulated in 180 nm and 45 nm CMOS process using the Synopsys HSPICE simulation tool and their performances are compared. The parameters, such as resonance frequency, tuning capability, noise and power dissipation, are analyzed for these CMOS technologies and discussed. The design of a third order band pass filter using an active inductor is also presented. (semiconductor integrated circuits)

  14. Low Noise Bias Current/Voltage References Based on Floating-Gate MOS Transistors

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    The exploitation of floating-gate MOS transistors as reference current and voltage sources is investigated. Test structures of common source and common drain floating-gate devices have been implemented in a commercially available 0.8 micron double-poly CMOS process. The measurements performed...

  15. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    Science.gov (United States)

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  16. Toward VIP-PIX: A Low Noise Readout ASIC for Pixelated CdTe Gamma-Ray Detectors for Use in the Next Generation of PET Scanners.

    Science.gov (United States)

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Puigdengoles, Carles; Lorenzo, Gianluca De; Martínez, Ricardo

    2013-08-01

    VIP-PIX will be a low noise and low power pixel readout electronics with digital output for pixelated Cadmium Telluride (CdTe) detectors. The proposed pixel will be part of a 2D pixel-array detector for various types of nuclear medicine imaging devices such as positron-emission tomography (PET) scanners, Compton gamma cameras, and positron-emission mammography (PEM) scanners. Each pixel will include a SAR ADC that provides the energy deposited with 10-bit resolution. Simultaneously, the self-triggered pixel which will be connected to a global time-to-digital converter (TDC) with 1 ns resolution will provide the event's time stamp. The analog part of the readout chain and the ADC have been fabricated with TSMC 0.25 μ m mixed-signal CMOS technology and characterized with an external test pulse. The power consumption of these parts is 200 μ W from a 2.5 V supply. It offers 4 switchable gains from ±10 mV/fC to ±40 mV/fC and an input charge dynamic range of up to ±70 fC for the minimum gain for both polarities. Based on noise measurements, the expected equivalent noise charge (ENC) is 65 e - RMS at room temperature.

  17. Low-Gain, Low-Noise Integrated Neuronal Amplifier for Implantable Artifact-Reduction Recording System

    OpenAIRE

    Zbrzeski, Adeline; Lewis, Noëlle; Rummens, Francois; Jung, Ranu; N'Kaoua, Gilles; Benazzouz, Abdelhamid; Renaud, Sylvie

    2013-01-01

    Brain neuroprostheses for neuromodulation are being designed to monitor the neural activity of the brain in the vicinity of the region being stimulated using a single macro-electrode. Using a single macro-electrode, recent neuromodulation studies show that recording systems with a low gain neuronal amplifier and successive amplifier stages can reduce or reject stimulation artifacts. These systems were made with off-the-shelf components that are not amendable for future implant design. A low-g...

  18. Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

    Science.gov (United States)

    Duong, Tuan A. (Inventor)

    2015-01-01

    A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

  19. Wideband pulse amplifier with 8 GHz GBW product in a 0.35 {mu}m CMOS technology for the integrated camera of the Cherenkov Telescope Array

    Energy Technology Data Exchange (ETDEWEB)

    Gascon, D; Sanuy, A; Ribo, M [Dept. AM i Dept.ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E; Glicenstein, J-F [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Sieiro, X [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Feinstein, F; Vorobiov, S [LPTA, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P, E-mail: gascon@ecm.ub.es [LPNHE, Universite Paris VI and IN2P3/CNRS, Paris (France)

    2010-12-15

    A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35{mu}m CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

  20. Wideband pulse amplifier with 8 GHz GBW product in a 0.35 μm CMOS technology for the integrated camera of the Cherenkov Telescope Array

    International Nuclear Information System (INIS)

    Gascon, D; Sanuy, A; Ribo, M; Delagnes, E; Glicenstein, J-F; Sieiro, X; Feinstein, F; Vorobiov, S; Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P

    2010-01-01

    A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35μm CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

  1. Low-power analog integrated circuits for wireless ECG acquisition systems.

    Science.gov (United States)

    Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

    2012-09-01

    This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

  2. Low noise wing slat system with rigid cove-filled slat

    Science.gov (United States)

    Shmilovich, Arvin (Inventor); Yadlin, Yoram (Inventor)

    2013-01-01

    Concepts and technologies described herein provide for a low noise aircraft wing slat system. According to one aspect of the disclosure provided herein, a cove-filled wing slat is used in conjunction with a moveable panel rotatably attached to the wing slat to provide a high lift system. The moveable panel rotates upward against the rear surface of the slat during deployment of the slat, and rotates downward to bridge a gap width between the stowed slat and the lower wing surface, completing the continuous outer mold line shape of the wing, when the cove-filled slat is retracted to the stowed position.

  3. LOW-NOISE PAVEMENT AS A WAY OF LIMITATION OF TRAFFIC NOISE LEVEL

    Directory of Open Access Journals (Sweden)

    Władysław Gardziejczyk

    2014-11-01

    Full Text Available Road surface can significantlyreduce the trafficnoise level. Depending on the characteristic of the upper surface layers the differences between the maximum rolling noise levels from passing vehicles to reach values about 10 dB (A. A special group is low-noise pavements characterized by the presence of voids above 15%. Application the porous asphalt layers or asphalt mixture type BBTM affects a significantreduction the width of land surrounded the roads where permissible equivalent sound level is exceeded. Such solutions in some cases can replace acoustic barriers. Road pavements with a higher content of voids require proper maintenance because their acoustic performances are reduced during operation.

  4. A Tunable Low Noise Active Bandpass Filter Using a Noise Canceling Technique

    OpenAIRE

    Soltani, N.

    2016-01-01

    A monolithic tunable low noise active bandpass filter is presented in this study. Biasing voltages can control the center frequency and quality factor. By keeping the gain constant, the center frequency shift is 300 MHz. The quality factor can range from 90 to 290 at the center frequency. By using a noise cancelling circuit, noise is kept lower than 2.8 dB. The proposed filter is designed using MMIC technology with a center frequency of 2.4 GHz and a power consumption of 180 mW. ED02AH techno...

  5. A Tunable Low Noise Active Bandpass Filter Using a Noise Canceling Technique

    Directory of Open Access Journals (Sweden)

    N. Soltani

    2016-12-01

    Full Text Available A monolithic tunable low noise active bandpass filter is presented in this study. Biasing voltages can control the center frequency and quality factor. By keeping the gain constant, the center frequency shift is 300 MHz. The quality factor can range from 90 to 290 at the center frequency. By using a noise cancelling circuit, noise is kept lower than 2.8 dB. The proposed filter is designed using MMIC technology with a center frequency of 2.4 GHz and a power consumption of 180 mW. ED02AH technology is used to simulate the circuit elements.

  6. Low noise buffer amplifiers and buffered phase comparators for precise time and frequency measurement and distribution

    Science.gov (United States)

    Eichinger, R. A.; Dachel, P.; Miller, W. H.; Ingold, J. S.

    1982-01-01

    Extremely low noise, high performance, wideband buffer amplifiers and buffered phase comparators were developed. These buffer amplifiers are designed to distribute reference frequencies from 30 KHz to 45 MHz from a hydrogen maser without degrading the hydrogen maser's performance. The buffered phase comparators are designed to intercompare the phase of state of the art hydrogen masers without adding any significant measurement system noise. These devices have a 27 femtosecond phase stability floor and are stable to better than one picosecond for long periods of time. Their temperature coefficient is less than one picosecond per degree C, and they have shown virtually no voltage coefficients.

  7. Structured Analog CMOS Design

    CERN Document Server

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  8. Radiation imaging detectors made by wafer post-processing of CMOS chips

    NARCIS (Netherlands)

    Blanco Carballo, V.M.

    2009-01-01

    In this thesis several wafer post-processing steps have been applied to CMOS chips. Amplification gas strucutures are built on top of the microchips. A complete radiation imaging detector is obtained this way. Integrated Micromegas-like and GEM-like structures were fabricated on top of Timepix CMOS

  9. Above-CMOS a-Si and CIGS Solar Cells for Powering Autonomous Microsystems

    NARCIS (Netherlands)

    Lu, J.; Liu, W.; van der Werf, C.H.M.; Kovalgin, A.Y.; Sun, Y.; Schropp, R.E.I.; Schmitz, J.

    2010-01-01

    Two types of solar cells are successfully grown on chips from two CMOS generations. The efficiency of amorphous-silicon (a-Si) solar cells reaches 5.2%, copperindium-gallium-selenide (CIGS) cells 7.1%. CMOS functionality is unaffected. The main integration issues: adhesion, surface topography, metal

  10. A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

    Science.gov (United States)

    Kim, Jungsuk

    2016-12-01

    This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

  11. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  12. A low power low noise analog front end for portable healthcare system

    International Nuclear Information System (INIS)

    Wang Yanchao; Ke Keren; Qin Wenhui; Qin Yajie; Yi Ting; Hong Zhiliang

    2015-01-01

    The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5–100 Hz) and the achieved noise efficient factor is 6.48. (paper)

  13. Low noise signal-to-noise ratio enhancing readout circuit for current-mediated active pixel sensors

    International Nuclear Information System (INIS)

    Ottaviani, Tony; Karim, Karim S.; Nathan, Arokia; Rowlands, John A.

    2006-01-01

    Diagnostic digital fluoroscopic applications continuously expose patients to low doses of x-ray radiation, posing a challenge to both the digital imaging pixel and readout electronics when amplifying small signal x-ray inputs. Traditional switch-based amorphous silicon imaging solutions, for instance, have produced poor signal-to-noise ratios (SNRs) at low exposure levels owing to noise sources from the pixel readout circuitry. Current-mediated amorphous silicon pixels are an improvement over conventional pixel amplifiers with an enhanced SNR across the same low-exposure range, but whose output also becomes nonlinear with increasing dosage. A low-noise SNR enhancing readout circuit has been developed that enhances the charge gain of the current-mediated active pixel sensor (C-APS). The solution takes advantage of the current-mediated approach, primarily integrating the signal input at the desired frequency necessary for large-area imaging, while adding minimal noise to the signal readout. Experimental data indicates that the readout circuit can detect pixel outputs over a large bandwidth suitable for real-time digital diagnostic x-ray fluoroscopy. Results from hardware testing indicate that the minimum achievable C-APS output current that can be discerned at the digital fluoroscopic output from the enhanced SNR readout circuit is 0.341 nA. The results serve to highlight the applicability of amorphous silicon current-mediated pixel amplifiers for large-area flat panel x-ray imagers

  14. A Ka-band low-noise amplifier with a coplanar waveguide (CPW) structure with 0.15-μm GaAs pHEMT technology

    International Nuclear Information System (INIS)

    Wu Chia-Song; Chang Chien-Huang; Liu Hsing-Chung; Lin Tah-Yeong; Wu Hsien-Ming

    2010-01-01

    This investigation explores a low-noise amplifier (LNA) with a coplanar waveguide (CPW) structure, in which a two-stage amplifier is associated with a cascade schematic circuit, implemented in 0.15-μm GaAs pseudomorphic high electron mobility transistor (pHEMT) technology in a Ka-band (26.5-40.0 GHz) microwave monolithic integrated circuit (MMIC). The experimental results demonstrate that the proposed LNA has a peak gain of 12.53 dB at 30 GHz and a minimum noise figure of 3.3 dB at 29.5 GHz, when biased at a V ds of 2 V and a V gs of -0.6 V with a drain current of 16 mA in the circuit. The results show that the millimeter-wave LNA with coplanar waveguide structure has a higher gain and wider bandwidth than a conventional circuit. Finally, the overall LNA characterization exhibits high gain and low noise, indicating that the LNA has a compact circuit and favorable RF characteristics. The strong RF character exhibited by the LNA circuit can be used in millimeter-wave circuit applications. (semiconductor integrated circuits)

  15. State-of-the-art photodetectors for optoelectronic integration at telecommunication wavelength

    Directory of Open Access Journals (Sweden)

    Eng Png Ching

    2015-01-01

    Full Text Available Photodetectors hold a critical position in optoelectronic integrated circuits, and they convert light into electricity. Over the past decades, high-performance photodetectors (PDs have been aggressively pursued to enable high-speed, large-bandwidth, and low-noise communication applications. Various material systems have been explored and different structures designed to improve photodetection capability as well as compatibility with CMOS circuits. In this paper, we review state-of-theart photodetection technologies in the telecommunications spectrum based on different material systems, including traditional semiconductors such as InGaAs, Si, Ge and HgCdTe, as well as recently developed systems such as low-dimensional materials (e.g. graphene, carbon nanotube, etc. and noble metal plasmons. The corresponding material properties, fundamental mechanisms, fabrication, theoretical modelling and performance of the typical PDs are presented, including the emerging directions and perspectives of the PDs for optoelectronic integration applications are discussed.

  16. A CMOS Morlet Wavelet Generator

    Directory of Open Access Journals (Sweden)

    A. I. Bautista-Castillo

    2017-04-01

    Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

  17. A Low-Noise Direct Incremental A/D Converter for FET-Based THz Imaging Detectors

    Directory of Open Access Journals (Sweden)

    Moustafa Khatib

    2018-06-01

    Full Text Available This paper presents the design, implementation and characterization results of a pixel-level readout chain integrated with a FET-based terahertz (THz detector for imaging applications. The readout chain is fabricated in a standard 150-nm CMOS technology and contains a cascade of a preamplification and noise reduction stage based on a parametric chopper amplifier and a direct analog-to-digital conversion by means of an incremental ΣΔ converter, performing a lock-in operation with modulated sources. The FET detector is integrated with an on-chip antenna operating in the frequency range of 325–375 GHz and compliant with all process design rules. The cascade of the FET THz detector and readout chain is evaluated in terms of responsivity and Noise Equivalent Power (NEP measurements. The measured readout input-referred noise of 1.6 μ V r m s allows preserving the FET detector sensitivity by achieving a minimum NEP of 376 pW/ Hz in the optimum bias condition, while directly providing a digital output. The integrated readout chain features 65-dB peak-SNR and 80-μ W power consumption from a 1.8-V supply. The area of the antenna-coupled FET detector and the readout chain fits a pixel pitch of 455 μm, which is suitable for pixel array implementation. The proposed THz pixel has been successfully applied for imaging of concealed objects in a paper envelope under continuous-wave illumination.

  18. Ultra-Low-Noise Sub-mm/Far-IR Detectors for Space-Based Telescopes

    Science.gov (United States)

    Rostem, Karwan

    The sub-mm and Far-IR spectrum is rich with information from a wide range of astrophysical sources, including exoplanet atmospheres and galaxies at the peak star formation. In the 10-400 μm range, the spectral lines of important chemical species such H2O, HD, and [OI] can be used to map the formation and evolution of planetary systems. Dust emission in this spectral range is also an important tool for characterizing the morphology of debris disks and interstellar magnetic fields. At larger scales, accessing the formation and distribution of luminous Far-IR and sub-mm galaxies is essential to understanding star formation triggers, as well as the last stages of reionization at z 6. Detector technology is essential to realizing the full science potential of a next-generation Far-IR space telescope (Far-IR Surveyor). The technology gap in large-format, low-noise and ultra-low-noise Far-IR direct detectors is specifically highlighted by NASA's Cosmic Origins Program, and prioritized for development now to enable a flagship mission such as the Far-IR Surveyor that will address the key Cosmic Origins science questions of the next two decades. The detector requirements for a mid-resolution spectrometer are as follows: (1) Highly sensitive detectors with performance approaching 10^-19 - 10^-20 WHz 1/2 for background- limited operation in telescopes with cold optics. (2) Detector time constant in the sub- millisecond range. (3) Scalable architecture to a kilo pixel array with uniform detector characteristics. (4) Compatibility with space operation in the presence of particle radiation. We propose phononic crystals to meet the requirements of ultra-low-noise thermal detectors. By design, a phononic crystal exhibits phonon bandgaps where heat transport is forbidden. The size and location of the bandgaps depend on the elastic properties of the dielectric and the geometry of the phononic unit cell. A wide-bandwidth low-pass thermal filter with a cut-off frequency of 1.5 GHz and

  19. A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...... of including good off-chip components in the design by use of innovative, inexpensive package technology.To achieve a higher level of integration, the project will use a novel codesign approach to the design strategy. Rather than making specifications based on a purely architectural approach, the work uses...

  20. Ultra low-noise differential ac-coupled photodetector for sensitive pulse detection applications

    International Nuclear Information System (INIS)

    Windpassinger, Patrick J; Boisen, Axel; Kjærgaard, Niels; Polzik, Eugene S; Müller, Jörg Helge; Kubasik, Marcin; Koschorreck, Marco

    2009-01-01

    We report on the performance of ultra low-noise differential photodetectors especially designed for probing of atomic ensembles with weak light pulses. The working principle of the detectors is described together with the analysis procedures employed to extract the photon shot noise of light pulses with ∼1 μs duration. As opposed to frequency response peaked detectors, our approach allows for broadband quantum noise measurements. The equivalent noise charge (ENC) for two different hardware approaches is evaluated to 280 and 340 electrons per pulse, respectively, which corresponds to a dark noise equivalent photon number of n 3dB = 0.8 × 10 5 and n 3dB = 1.2 × 10 5 in the two approaches. Finally, we discuss the possibility of removing classical correlations in the output signal caused by detector imperfection by using double-correlated sampling methods

  1. High-Tc Superconducting Bolometer Noise Measurement Using Low Noise Transformers - Theory and Optimization

    Science.gov (United States)

    Aslam, Shahid; Jones, Hollis H.

    2011-01-01

    Care must always be taken when performing noise measurements on high-Tc superconducting materials to ensure that the results are not from the measurement system itself. One situation likely to occur is with low noise transformers. One of the least understood devices, it provides voltage gain for low impedance inputs (< 100 ), e.g., YBaCuO and GdBaCuO thin films, with comparatively lower noise levels than other devices for instance field effect and bipolar junction transistors. An essential point made in this paper is that because of the complex relationships between the transformer ports, input impedance variance alters the transformer s transfer function in particular, the low frequency cutoff shift. The transfer of external and intrinsic transformer noise to the output along with optimization and precautions are treated; all the while, we will cohesively connect the transfer function shift, the load impedance, and the actual noise at the transformer output.

  2. Low-noise magnetic observatory variometer with race-track sensors

    International Nuclear Information System (INIS)

    Janošek, M; Petrucha, V; Vlk, M

    2016-01-01

    We present a low-noise, high-stability observatory magnetometer with race-track sensors, as developed by the Czech Technical University in Prague for National Observatory of Athens. As opposed to the standard instruments, we used our novel race-track fluxgate sensors with planar oval core which were cut by state-of-the art pico-second UV-laser. The noise performance of the complete electronics and sensor chain is below 6 pT/√Hz @ 1 Hz. The electronics uses 24-bit 200-Hz A/D converter with simultaneous sampling and all digital processing is done in FPGA. The variometer with the sensors mounted on a MACOR cube has been successfully calibrated by scalar method. (paper)

  3. Nb{sub 3}Al thin film deposition for low-noise terahertz electronics

    Energy Technology Data Exchange (ETDEWEB)

    Dochev, D; Pavolotsky, A B; Belitsky, V; Olofsson, H [Group for Advanced Receiver Development and Onsala Space Observatory, Department of Radio- and Space Science, Chalmers University of Technology, SE 412 96 Gothenburg (Sweden)], E-mail: dimitar.dochev@chalmers.se

    2008-02-01

    Higher energy gap superconducting materials were always interesting for low-noise mixer applications such as superconductor-insulator-superconductor tunnel junctions (SIS) and hot-electron bolometer (HEB) used in sub-millimeter and terahertz parts of electro-magnetic spectrum. Here, we report a novel approach for producing Nb{sub 3}Al thin film by co-sputtering from two confocally arranged Nb and Al dc-magnetrons onto substrate heated up to 830 deg. C. Characterization of the deposited films revealed presence of the A15 phase and measured critical temperature was up to 15.7 K with the transition width 0.2-0.3 K for a 300 nm thick film. We measured the film critical magnetic field and studied influence of annealing on the film properties. We have investigated compositional depth profile of the deposited films by spectroscopy of reflected electrons.

  4. Nb3Al thin film deposition for low-noise terahertz electronics

    International Nuclear Information System (INIS)

    Dochev, D; Pavolotsky, A B; Belitsky, V; Olofsson, H

    2008-01-01

    Higher energy gap superconducting materials were always interesting for low-noise mixer applications such as superconductor-insulator-superconductor tunnel junctions (SIS) and hot-electron bolometer (HEB) used in sub-millimeter and terahertz parts of electro-magnetic spectrum. Here, we report a novel approach for producing Nb 3 Al thin film by co-sputtering from two confocally arranged Nb and Al dc-magnetrons onto substrate heated up to 830 deg. C. Characterization of the deposited films revealed presence of the A15 phase and measured critical temperature was up to 15.7 K with the transition width 0.2-0.3 K for a 300 nm thick film. We measured the film critical magnetic field and studied influence of annealing on the film properties. We have investigated compositional depth profile of the deposited films by spectroscopy of reflected electrons

  5. Low-Noise Operation of All-Fiber Femtosecond Cherenkov Laser

    DEFF Research Database (Denmark)

    Liu, Xiaomin; Villanueva Ibáñez, Guillermo Eduardo; Lægsgaard, Jesper

    2013-01-01

    We investigate the noise properties of a femtosecond all-fiber Cherenkov radiation source with emission wavelength around 600 nm, based on an Yb-fiber laser and a highly-nonlinear photonic crystal fiber. A relative intensity noise as low as - 103 dBc/Hz, corresponding to 2.48 % pulse-to-pulse...... fluctuation in energy, was observed at the Cherenkov radiation output power of 4.3 mW, or 150 pJ pulse energy. This pulse-to-pulse fluctuation is at least 10.6 dB lower compared to spectrally-sliced supercontinuum sources traditionally used for ultrafast fiberbased generation at visible wavelengths. Low noise...... makes allfiber Cherenkov sources promising for biophotonics applications such as multi-photon microscopy, where minimum pulse-to-pulse energy fluctuation is required. We present the dependency of the noise figure on both the Cherenkov radiation output power and its spectrum....

  6. Low-noise analog readout channel for SDD in X-ray spectrometry

    Science.gov (United States)

    Atkin, E.; Gusev, A.; Krivchenko, A.; Levin, V.; Malankin, E.; Normanov, D.; Rotin, A.; Sagdiev, I.; Samsonov, V.

    2016-01-01

    A low-noise analog readout channel optimized for operation with the Silicon Drift Detectors (SDDs) with built-in JFET is presented. The Charge Sensitive Amplifier (CSA) operates in a pulse reset mode using the reset diode built-in the SDD detector. The shaper is a 6th order semi-Gaussian filter with switchable discrete shaping times. The readout channel provides the Equivalent Noise Charge (ENC) of 12e- (simulation) and input dynamic range of 30 keV . The measured energy resolution at the 5,89 keV line of a 55Fe X-ray source is 336 eV (FWHM). The channel was prototyped via Europractice in the AMS 350 nm process as miniASIC. The simulation and first measurement results are presented in the paper.

  7. Ultra-low noise TES bolometer arrays for SAFARI instrument on SPICA

    Science.gov (United States)

    Khosropanah, P.; Suzuki, T.; Ridder, M. L.; Hijmering, R. A.; Akamatsu, H.; Gottardi, L.; van der Kuur, J.; Gao, J. R.; Jackson, B. D.

    2016-07-01

    SRON is developing ultra-low noise Transition Edge Sensors (TESs) based on a superconducting Ti/Au bilayer on a suspended SiN island with SiN legs for the SAFARI instrument aboard the SPICA mission. We successfully fabricated TESs with very narrow (0.5-0.7 μm) and thin (0.25 μm) SiN legs on different sizes of SiN islands using deep reactiveion etching process. The pixel size is 840x840 μm2 and there are variety of designs with and without optical absorbers. For TESs without absorbers, we measured electrical NEPs as low as <1x10-19 W/√Hz with response time of 0.3 ms and reached the phonon noise limit. Using TESs with absorbers, we quantified the darkness of our setup and confirmed a photon noise level of 2x10-19 W/√Hz.

  8. Fabrication of Low-Noise TES Arrays for the SAFARI Instrument on SPICA

    Science.gov (United States)

    Ridder, M. L.; Khosropanah, P.; Hijmering, R. A.; Suzuki, T.; Bruijn, M. P.; Hoevers, H. F. C.; Gao, J. R.; Zuiddam, M. R.

    2016-07-01

    Ultra-low-noise transition edge sensors (TES) with noise equivalent power lower than 2 × 10^{-19} W/Hz^{1/2 } have been fabricated by SRON, which meet the sensitivity requirements for the far-infrared SAFARI instrument on space infrared telescope for cosmology and astrophysics. Our TES detector is based on a titanium/gold (Ti/Au) thermistor on a silicon nitride (SiN) island. The island is thermally linked with SiN legs to a silicon support structure at the bath temperature. The SiN legs are very thin (250 nm), narrow (500 nm), and long (above 300 {\\upmu } m); these dimensions are needed in leg-isolated bolometers to achieve the required level of sensitivity. In this paper, we describe the latest fabrication process for our TES bolometers with improved sensitivity.

  9. Low-noise, transformer-coupled resonant photodetector for squeezed state generation.

    Science.gov (United States)

    Chen, Chaoyong; Shi, Shaoping; Zheng, Yaohui

    2017-10-01

    In an actual setup of squeezed state generation, the stability of a squeezing factor is mainly limited by the performance of the servo-control system, which is mainly influenced by the shot noise and gain of a photodetector. We present a unique transformer-coupled LC resonant amplifier as a photodetector circuit to reduce the electronic noise and increase the gain of the photodetector. As a result, we obtain a low-noise, high gain photodetector with the gain of more than 1.8×10 5 V/A, and the input current noise of less than 4.7 pA/Hz. By adjusting the parameters of the transformer, the quality factor Q of the resonant circuit is close to 100 in the frequency range of more than 100 MHz, which meets the requirement for weak power detection in the application of squeezed state generation.

  10. Using the Moon As A Low-Noise Seismic Detector For Strange Quark Nuggets

    Science.gov (United States)

    Banerdt, W. Bruce; Chui, Talso; Griggs, Cornelius E.; Herrin, Eugene T.; Nakamura, Yosio; Paik, Ho Jung; Penanen, Konstantin; Rosenbaum, Doris; Teplitz, Vigdor L.; Young, Joseph

    2006-01-01

    Strange quark matter made of up, down and strange quarks has been postulated by Witten [1]. Strange quark matter would be nearly charge neutral and would have density of nuclear matter (10(exp 14) gm/cu cm). Witten also suggested that nuggets of strange quark matter, or strange quark nuggets (SQNs), could have formed shortly after the Big Bang, and that they would be viable candidates for cold dark matter. As suggested by de Rujula and Glashow [2], an SQN may pass through a celestial body releasing detectable seismic energy along a straight line. The Moon, being much quieter seismically than the Earth, would be a favorable place to search for such events. We review previous searches for SQNs to illustrate the parameter space explored by using the Moon as a low-noise detector of SQNs. We also discuss possible detection schemes using a single seismometer, and using an International Lunar Seismic Network.

  11. Linearizing of Low Noise Power Amplifier Using 5.8GHz Double Loop Feedforward Linearization Technique

    Directory of Open Access Journals (Sweden)

    Abdulkareem Mokif Obais

    2017-05-01

    Full Text Available In this paper, a double loop feedforward linearization technique is analyzed and built with a MMIC low noise amplifier “HMC753” as main amplifier and a two-stage class-A power amplifier as error amplifier. The system is operated with 5V DC supply at a center frequency of 5.8GHz and a bandwidth of 500MHz. The proposed technique, increases the linearity of the MMIC amplifier from 18dBm at 1dB compression point to more than 26dBm. In addition, the proposed system is tested with OFDM signal and it reveals good response in maximizing the linearity region and eliminating distortions. The proposed system is designed and simulated onAdvanced Wave Research-Microwave Office (AWR-MWO.

  12. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  13. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  14. Photon imaging using post-processed CMOS chips

    NARCIS (Netherlands)

    Melai, J.

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic

  15. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    Science.gov (United States)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  16. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  17. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  18. Large-area, low-noise, high-speed, photodiode-based fluorescence detectors with fast overdrive recovery

    International Nuclear Information System (INIS)

    Bickman, S.; DeMille, D.

    2005-01-01

    Two large-area, low-noise, high-speed fluorescence detectors have been built. One detector consists of a photodiode with an area of 28 mmx28 mm and a low-noise transimpedance amplifier. This detector has a input light-equivalent spectral noise density of less than 3 pW/√(Hz), can recover from a large scattered light pulse within 10 μs, and has a bandwidth of at least 900 kHz. The second detector consists of a 16-mm-diam avalanche photodiode and a low-noise transimpedance amplifier. This detector has an input light-equivalent spectral noise density of 0.08 pW/√(Hz), also can recover from a large scattered light pulse within 10 μs, and has a bandwidth of 1 MHz

  19. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    Directory of Open Access Journals (Sweden)

    Nan Guo

    2014-10-01

    Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  20. A low power low noise analog front end for portable healthcare system

    Science.gov (United States)

    Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

    2015-10-01

    The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

  1. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  2. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    Science.gov (United States)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  3. Modularly Integrated MEMS Technology

    National Research Council Canada - National Science Library

    Eyoum, Marie-Angie N

    2006-01-01

    Process design, development and integration to fabricate reliable MEMS devices on top of VLSI-CMOS electronics without damaging the underlying circuitry have been investigated throughout this dissertation...

  4. A piezoresistive cantilever for lateral force detection fabricated by a monolithic post-CMOS process

    International Nuclear Information System (INIS)

    Ji Xu; Li Zhihong; Li Juan; Wang Yangyuan; Xi Jianzhong

    2008-01-01

    This paper presents a post-CMOS process to monolithically integrate a piezoresistive cantilever for lateral force detection and signal processing circuitry. The fabrication process includes a standard CMOS process and one more lithography step to micromachine the cantilever structure in the post-CMOS process. The piezoresistors are doped in the CMOS process but defined in the post-CMOS micromachining process without any extra process required. A partially split cantilever configuration is developed for the lateral force detection. The piezoresistors are self-aligned to the split cantilever, and therefore the width of the beam is only limited by lithography. Consequently, this kind of cantilever potentially has a high resolution. The preliminary experimental results show expected performances of the fabricated piezoresistors and electronic circuits

  5. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  6. Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

    International Nuclear Information System (INIS)

    Cheng, Chao-Lin; Fang, Weileun; Tsai, Ming-Han

    2015-01-01

    Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli. (paper)

  7. EUDP project 'Low noise airfoil' - Final report

    Energy Technology Data Exchange (ETDEWEB)

    Bertagnolio, F. (ed.)

    2012-06-15

    This document summarizes the scientific results achieved during the EUDP-funded project 'Low-Noise Airfoil'. The goals of this project are, on one side to develop a measurement technique that permits the evaluation of trailing edge noise in a classical aerodynamic wind tunnel, and on the other side to develop and implement a design procedure to manufacture airfoil profiles with low noise emission. The project involved two experimental campaigns: one in the LM Wind Power wind tunnel, a classical aerodynamic wind tunnel, in Lunderskov (Denmark), the second one in the Virginia Tech Stability Wind Tunnel at the Aerospace and Ocean Engineering Department of Virginia Tech (Blacksburg, VA, USA), also a classical aerodynamic wind tunnel but equipped with an anechoic chamber that allow to perform acoustic measurements. On the theoretical side, the above experiments yield a series of model validations and improvements. In particular, the so-called TNO trailing edge noise model could be significantly improved by introducing turbulence anisotropy in its formulation, as well as the influence of the boundary layer mean pressure gradient. This two characteristics are inherent to airfoil flows but were neglected in the original approach. In addition, the experimental results are confronted to detailed Large Eddy Simulations of the airfoil flow giving more insight into the flow turbulence characteristics. The methodology which consists in measuring surface pressure spectra directly on the airfoil surface using flush-mounted microphones in order to evaluate far-field noise emission using additional theoretical results has been validated. This technique presents the advantage that it can easily be used in a classical aerodynamic wind tunnel and does not require the use of an anechoic facility. It was developed as a substitute to the original plan that consisted in measuring acoustic waves using hot-wire velocimetry. This last technique proved ineffective in the LM Wind

  8. A new CMOS Hall angular position sensor

    Energy Technology Data Exchange (ETDEWEB)

    Popovic, R.S.; Drljaca, P. [Swiss Federal Inst. of Tech., Lausanne (Switzerland); Schott, C.; Racz, R. [SENTRON AG, Zug (Switzerland)

    2001-06-01

    The new angular position sensor consists of a combination of a permanent magnet attached to a shaft and of a two-axis magnetic sensor. The permanent magnet produces a magnetic field parallel with the magnetic sensor plane. As the shaft rotates, the magnetic field also rotates. The magnetic sensor is an integrated combination of a CMOS Hall integrated circuit and a thin ferromagnetic disk. The CMOS part of the system contains two or more conventional Hall devices positioned under the periphery of the disk. The ferromagnetic disk converts locally a magnetic field parallel with the chip surface into a field perpendicular to the chip surface. Therefore, a conventional Hall element can detect an external magnetic field parallel with the chip surface. As the direction of the external magnetic field rotates in the chip plane, the output voltage of the Hall element varies as the cosine of the rotation angle. By placing the Hall elements at the appropriate places under the disk periphery, we may obtain the cosine signals shifted by 90 , 120 , or by any other angle. (orig.)

  9. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  10. Absorbed dose by a CMOS in radiotherapy

    International Nuclear Information System (INIS)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

    2011-10-01

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  11. A low noise clock generator for high-resolution time-to-digital convertors

    International Nuclear Information System (INIS)

    Prinzie, J.; Leroux, P.; Christiaensen, J.; Moreira, P.; Steyaert, M.

    2016-01-01

    A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS

  12. Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers.

    Science.gov (United States)

    Royo, Guillermo; Sánchez-Azqueta, Carlos; Gimeno, Cecilia; Aldea, Concepción; Celma, Santiago

    2016-12-30

    In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/ Hz at 50 kHz, which corresponds to 100 μg/ Hz .

  13. Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers

    Directory of Open Access Journals (Sweden)

    Guillermo Royo

    2016-12-01

    Full Text Available In this work, we present a capacitance-to-voltage converter (CVC for capacitive accelerometers based on microelectromechanical systems (MEMS. Based on a fully-differential transimpedance amplifier (TIA, it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/ Hz at 50 kHz, which corresponds to 100 μg/ Hz .

  14. NASA's Pursuit of Low-Noise Propulsion for Low-Boom Commercial Supersonic Vehicles

    Science.gov (United States)

    Bridges, James; Brown, Clifford A.; Seidel, Jonathan A.

    2018-01-01

    Since 2006, when the Fundamental Aeronautics Program was instituted within NASA's Aeronautics Mission Directorate, there has been a Project looking at the technical barriers to commercial supersonic flight. Among the barriers is the noise produced by aircraft during landing and takeoff. Over the years that followed, research was carried out at NASA aeronautics research centers, often in collaboration with academia and industry, addressing the problem. In 2013, a high-level milestone was established, described as a Technical Challenge, with the objective of demonstrating the feasibility of a low-boom supersonic airliner that could meet current airport noise regulations. The Technical Challenge was formally called "Low Noise Propulsion for Low Boom Aircraft", and was completed in late 2016. This paper reports the technical findings from this Technical Challenge, reaching back almost 10 years to review the technologies and tools that were developed along the way. It also discusses the final aircraft configuration and propulsion systems required for a supersonic civilian aircraft to meet noise regulations using the technologies available today. Finally, the paper documents the model-scale tests that validated the acoustic performance of the study aircraft.

  15. A low-noise MEMS accelerometer for unattended ground sensor applications

    Science.gov (United States)

    Speller, Kevin E.; Yu, Duli

    2004-09-01

    A low-noise micro-machined servo accelerometer has been developed for use in Unattended Ground Sensors (UGS). Compared to conventional coil-and-magnet based velocity transducers, this Micro-Electro-Mechanical System (MEMS) accelerometer offers several key benefits for battlefield monitoring. Many UGS require a compass to determine deployment orientation with respect to magnetic North. This orientation information is critical for determining the bearing of incoming signals. Conventional sensors with sensing technology based on a permanent magnet can cause interference with a compass when used in close proximity. This problem is solved with a MEMS accelerometer which does not require any magnetic materials. Frequency information below 10 Hz is valuable for identification of signal sources. Conventional seismometers used in UGS are typically limited in frequency response from 20 to 200 Hz. The MEMS accelerometer has a flat frequency response from DC to 5 kHz. The wider spectrum of signals received improves detection, classification and monitoring on the battlefield. The DC-coupled output of the MEMS accelerometer also has the added benefit of providing tilt orientation data for the deployed UGS. Other performance parameters of the MEMS accelerometer that are important to UGS such as size, weight, shock survivability, phase response, distortion, and cross-axis rejection will be discussed. Additionally, field test data from human footsteps recorded with the MEMS accelerometer will be presented.

  16. The Majorana Low-noise Low-background Front-end Electronics

    Science.gov (United States)

    Abgrall, N.; Aguayo, E.; Avignone, F. T.; Barabash, A. S.; Bertrand, F. E.; Boswell, M.; Brudanin, V.; Busch, M.; Byram, D.; Caldwell, A. S.; Chan, Y.-D.; Christofferson, C. D.; Combs, D. C.; Cuesta, C.; Detwiler, J. A.; Doe, P. J.; Efremenko, Yu.; Egorov, V.; Ejiri, H.; Elliott, S. R.; Fast, J. E.; Finnerty, P.; Fraenkle, F. M.; Galindo-Uribarri, A.; Giovanetti, G. K.; Goett, J.; Green, M. P.; Gruszko, J.; Guiseppe, V. E.; Gusev, K.; Hallin, A. L.; Hazama, R.; Hegai, A.; Henning, R.; Hoppe, E. W.; Howard, S.; Howe, M. A.; Keeter, K. J.; Kidd, M. F.; Kochetov, O.; Konovalov, S. I.; Kouzes, R. T.; LaFerriere, B. D.; Leon, J.; Leviner, L. E.; Loach, J. C.; MacMullin, J.; MacMullin, S.; Martin, R. D.; Meijer, S.; Mertens, S.; Nomachi, M.; Orrell, J. L.; O'Shaughnessy, C.; Overman, N. R.; Phillips, D. G.; Poon, A. W. P.; Pushkin, K.; Radford, D. C.; Rager, J.; Rielage, K.; Robertson, R. G. H.; Romero-Romero, E.; Ronquest, M. C.; Schubert, A. G.; Shanks, B.; Shima, T.; Shirchenko, M.; Snavely, K. J.; Snyder, N.; Suriano, A. M.; Thompson, J.; Timkin, V.; Tornow, W.; Trimble, J. E.; Varner, R. L.; Vasilyev, S.; Vetter, K.; Vorren, K.; White, B. R.; Wilkerson, J. F.; Wiseman, C.; Xu, W.; Yakushev, E.; Young, A. R.; Yu, C.-H.; Yumatov, V.

    The MAJORANA DEMONSTRATOR will search for the neutrinoless double beta decay (ββ(0ν)) of the isotope 76Ge with a mixed array of enriched and natural germanium detectors. In view of the next generation of tonne-scale germanium-based ββ(0ν)-decay searches, a major goal of the MAJORANA DEMONSTRATOR is to demonstrate a path forward to achieving a background rate at or below 1 cnt/(ROI-t-y) in the 4 keV region of interest (ROI) around the 2039-keV Q-value of the 76Ge ββ(0ν)-decay. Such a requirement on the background level significantly constrains the design of the readout electronics, which is further driven by noise and energy resolution performances. We present here the low-noise low- background front-end electronics developed for the low-capacitance p-type point contact (P-PC) germanium detectors of the MAJORANA DEMONSTRATOR. This resistive-feedback front-end, specifically designed to have low mass, is fabricated on a radioassayed fused-silica substrate where the feedback resistor consists of a sputtered thin film of high purity amorphous germanium and the feedback capacitor is based on the capacitance between gold conductive traces.

  17. Temperature characterization of deep and shallow defect centers of low noise silicon JFETs

    International Nuclear Information System (INIS)

    Arnaboldi, Claudio; Fascilla, Andrea; Lund, M.W.; Pessina, Gianluigi

    2004-01-01

    We have selected different low noise JFET processes that have shown outstanding dynamic and noise performance at both room temperature and low temperatures. We have studied JFETs made with a process optimized for cryogenic operation, testing several devices of varying capacitance. For most of them, we have been able to detect the presence of shallow individual traps at low temperature which create low frequency (LF) Generation-Recombination (G-R) noise. For one device type no evidence of traps has been observed at the optimum temperature of operation (around 100 K). It had a very small residual LF noise. This device has been cooled down to 14 K. From below 100 K down to 14 K the noise was observed to increase due to G-R noise originating from donor atoms (dopants) inside the channel. A very simple theoretical interpretation confirms the nature of G-R noise from these very shallow trapping centers. We also studied devices from a process optimized for room temperature operation and found noise corresponding to the presence of a single deep level trap. Even for this circumstance the theory was experimentally confirmed. The measurement approach we used allowed us to achieve a very high accuracy in the modeling of the measured G-R noise. The ratio of the density of the atoms responsible for G-R noise above the doping concentration, N T /N d , has been verified with a sensitivity around 10 -7

  18. Perancangan Low Noise Amplifier dengan Teknik Non Simultaneous Conjugate Match untuk Aplikasi Radar S-Band

    Directory of Open Access Journals (Sweden)

    Yana Taryana

    2016-06-01

    Full Text Available Radar merupakan sistem pemancar dan penerima gelombang elektromagnetik untuk mendeteksi, mengukur jarak dan membuat peta benda benda seperti pesawat terbang, kapal laut, kendaran bermotor dan informasi cuaca. Salah satu kendala yang dihadapi pada sistem radar adalah sinyal pantulan yang memiliki daya yang rendah sehingga kualitas penerimaan menjadi kurang baik. Untuk mengatasi kendala tersebut dibutuhkan penguat daya pada sistem penerima yaitu Low Noise Amplifier (LNA. Oleh karena itu, tulisan ini memaparkan perancangan LNA dengan menggunakan teknik Non Simultaneous Conjugate Match (NSCM untuk aplikasi radar S-Band. Teknik ini memberikan kemudahan dalam menentukan nilai trade off (TO untuk nilai gain, noise figure (NF dan Voltage Standing Wave Ratio (VSWR yang diinginkan. Dalam proses perancangannya, perangkat lunak Agilent Design System (ADS 2011 digunakan untuk mendapatkan hubungan antara lingkaran gain, lingkaran NF, lingkaran VSWR, dan lingkaran mismatch factor (M. Dari hubungan tersebut diperoleh nilai impedansi masukan dan keluaran dari komponen aktif. Dalam tulisan ini, LNA dirancang dua tingkat untuk mendapatkan penguatan yang tinggi. Masing-masing tingkat menggunakan komponen aktif BJT BFP420 dengan penguatan dirancang sebesar 13,50 dB untuk tingkat pertama dan kedua, dan M sebesar 0,98. Sedangkan untuk saluran penyesuai impedansinya menggunakan substrat teflon fiberglass DiClad527. Hasil simulasi menunjukkan karakteristik LNA pada frekuensi 3 GHz yaitu gain sebesar 28,80 dB, NF sebesar 2,80 dB, VSWRin sebesar 1,05 dan VSWRout sebesar 1,1.

  19. Fabrication of Low Noise Borosilicate Glass Nanopores for Single Molecule Sensing.

    Directory of Open Access Journals (Sweden)

    Jayesh A Bafna

    Full Text Available We show low-cost fabrication and characterization of borosilicate glass nanopores for single molecule sensing. Nanopores with diameters of ~100 nm were fabricated in borosilicate glass capillaries using laser assisted glass puller. We further achieve controlled reduction and nanometer-size control in pore diameter by sculpting them under constant electron beam exposure. We successfully fabricate pore diameters down to 6 nm. We next show electrical characterization and low-noise behavior of these borosilicate nanopores and compare their taper geometries. We show, for the first time, a comprehensive characterization of glass nanopore conductance across six-orders of magnitude (1M-1μM of salt conditions, highlighting the role of buffer conditions. Finally, we demonstrate single molecule sensing capabilities of these devices with real-time translocation experiments of individual λ-DNA molecules. We observe distinct current blockage signatures of linear as well as folded DNA molecules as they undergo voltage-driven translocation through the glass nanopores. We find increased signal to noise for single molecule detection for higher trans-nanopore driving voltages. We propose these nanopores will expand the realm of applications for nanopore platform.

  20. Updated design for a low-noise, wideband transimpedance photodiode amplifier

    International Nuclear Information System (INIS)

    Paul, S. F.; Marsala, R.

    2006-01-01

    The high-speed rotation diagnostic developed for Columbia's HBT-EP tokamak requires a high quantum efficiency, very low drift detector/amplifier combination. An updated version of the circuit developed originally for the beam emission spectroscopy experiment on TFTR is being used. A low dark current (2 nA at 15 V bias), low input source capacitance (2 pF) FFD-040 N-type Si photodiode is operated in photoconductive mode. It has a quantum efficiency of 40% at the 468.6 nm (He II line that is being observed). A low-noise field-effect transistor (InterFET IFN152 with e Na =1.2 nV/√Hz) is used to reduce the noise in the transimpedance preamplifier (A250 AMPTEK op-amp) and a very high speed (unity-gain bandwidth=200 MHz) voltage feedback amplifier (LM7171) is used to restore the frequency response up to 100 kHz. This type of detector/amplifier is photon-noise limited at this bandwidth for incident light with a power of >∼2 nW. The circuit has been optimized using SIMETRIX 4.0 SPICE software and a prototype circuit has been tested successfully. Though photomultipliers and avalanche photodiodes can detect much lower light levels, for light levels >2 nW and a 10 kHz bandwidth, this detector/amplifier combination is more sensitive because of the absence of excess (internally generated) noise

  1. Observation of Synchrotron Radiation Using Low Noise Block (LNB) at ANKA

    CERN Document Server

    Judin, V; Hofmann, A; Huttel, E; Kehrer, B; Klein, M; Marsching, S; Muller, A-S; Smale, N; Caspers, F

    2011-01-01

    Generally Coherent Synchrotron Radiation (CSR) is emitted for wavelengths longer than or equal the bunch length, so for CSR in the THz-range short bunches are required. There are two types of detectors in this range of the spectrum: slow detectors like a golay cell or pyrometric detectors (used for e.g. imaging, spectroscopy) and fast detectors like superconducting bolometer detector systems and Schottky Barrier diodes (used for e.g. the investigation of dynamic processes in accelerator physics). The hot electron bolometer (HEB) detector system is a member of second group. It is very fast and has broad spectral characteristics, but unfortunately very expensive and have to be cooled using liquid helium. If the broad spectral response is not important, it will be suitably to use a Schottky Barrier diode instead. These detectors are massively cheaper but also slower. As an alternative to a Schottky diode a LNB (Low Noise Block) can be also used. It is usually used in standard TV-SAT-receivers. Due to mass produc...

  2. A low noise preamplifier with optoelectronic overload protection for radioactivity measurement

    International Nuclear Information System (INIS)

    Sephton, J.P.; Williams, J.M.; Johansson, L.C.; Philips, H.C.

    2012-01-01

    Pulses from detectors used for radioactivity measurement can vary in size by several orders of magnitude. Large pulses will lead to saturation at the preamplifier output and extension of the pulse length. As a consequence, the dead time of the system increases and pulses may be lost. Electronic design techniques employed to protect against overloading tend to increase the amplifier noise level. However, an optoelectronic method of overload protection has been devised which has only a negligible effect on noise. An infrared light emitting diode interfaced to the output of the preamplifier is linked by fibre optic cable to an ultra-low leakage photodiode at the input. The conduction of the photodiode increases with the amplitude of the preamplifier output signal. Excess current is thereby prevented from entering the preamplifier and causing saturation. The preamplifier has been tested on 4π beta–gamma and gas counting systems and found to give good protection against overloading. - Highlights: ► A preamplifier for radioactivity measurements has been developed. ► Low noise. ► Current sensitive. ► Optoelectronic overload protection.

  3. Op-amp based low noise amplifier for magnetic particle spectroscopy

    Directory of Open Access Journals (Sweden)

    Malhotra Ankit

    2017-09-01

    Full Text Available Magnetic particle spectrometry (MPS is a novel technique used to measure the magnetization response of superparamagnetic iron oxide nanoparticles (SPIONs. Therefore, it is one of the most important tools for the characterization of the SPIONs for imaging modalities such as magnetic particle imaging (MPI and Magnetic Resonance Imaging (MRI. In MPS, change in the particle magnetization induces a voltage in a dedicated receive coil. The amplitude of the signal can be very low (ranging from a few nV to 100 μV depending upon the concentration of the nanoparticles. Hence, the received signal needs to be amplified with a low noise amplifier (LNA. LNA’s paramount task is to amplify the received signal while keeping the noise induced by its own circuitry minimum. In the current research, we purpose modeling, design, and development of a prototyped LNA for MPS. The designed prototype LNA is based on the parallelization technique of Op-amps. The prototyped LNA consists of 16 Op-amps in parallel and is manufactured on a printed circuit board (PCB, with a size of 110.38 mm × 59.46 mm and 234 components. The input noise of the amplifier is approx. 546 pV/√Hz with a noise figure (NF of approx. 1.4 dB with a receive coil termination. Furthermore, a comparison between the prototyped LNA and a commercially available amplifier is shown.

  4. Design and Characterization of Low-noise Dewar for High-sensitivity SQUID Operation

    International Nuclear Information System (INIS)

    Yu, K. K.; Lee, Y. H.; Kim, K.; Kwon, H.; Kim, J. M.

    2010-01-01

    We have fabricated the low noise liquid helium(LHe) dewar with a different shape of thermal shield to apply the 64-channel SQUID(Superconducting Quantum Interference Device) gradiometer. The first shape of thermal shield was made of an aluminum plate with a wide width of 100 mm slit and the other shape was modified with a narrow width of 20 mm slit. The two types of dewars were estimated by comparing the thermal noise and the signal-to-noise ratio(SNR) of magnetocardiography(MCG) using the 1st order SQUID gradiometer system cooled each dewar. The white noise was different as a point of the dewar. The noise was increased as close as the edge of dewar, and also increased at the thermal shield with the more wide width slit. The white noise of the dewar with thermal shield of 100 mm slit was 6.5 fT/Hz 1/2 at the center of dewar and 25 fT/Hz 1/2 at the edge, and the white noise of the other one was 3.5 - 7 fT/Hz 1/2 . We measured the MCG using 64-channel SQUID gradiometer cooled at each LHe dewar and compared the SNR of MCG signal. The SNR was improved of 10 times at the LHe dewar with a modified thermal shield.

  5. Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

    Science.gov (United States)

    Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

    2016-11-01

    Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

  6. The normalized interaural correlation : accounting for NoSp thresholds obtained with Gaussian and 'low-noise' masking noise

    NARCIS (Netherlands)

    Bernstein, L.R.; Par, van de S.L.J.D.E.; Trahiotis, C.T.

    1999-01-01

    Recently, [J. Acoust. Soc. Am. 103, 2578–2589 (1998)] and [J. Acoust. Soc. Am. 103, 2573–2577 (1998)] independently reported that greater masking of interaurally phase-reversed (Sp) tones was produced by diotic low-noise noise than by diotic Gaussian noise. Based on quantitative analyses, Eddins and

  7. Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

    Science.gov (United States)

    Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

    2017-12-01

    With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

  8. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

    2013-01-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  9. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  10. A 900 MHz RF energy harvesting system in 40 nm CMOS technology with efficiency peaking at 47% and higher than 30% over a 22dB wide input power range

    NARCIS (Netherlands)

    Wang, J.; Jiang, Y.; Dijkhuis, J.; Dolmans, G.; Gao, H.; Baltus, P.G.M.

    2017-01-01

    A 900 MHz RF energy harvesting system is proposed for a far-field wireless power transfer application. The topology of a single-stage CMOS rectifier loaded with an integrated boost DC-DC converter is implemented in a 40 nm CMOS technology. The co-design of a cross-coupled CMOS rectifier and an

  11. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  12. Post-CMOS FinFET integration of bismuth telluride and antimony telluride thin-film-based thermoelectric devices on SoI substrate

    KAUST Repository

    Aktakka, Ethem Erkan; Ghafouri, Niloufar; Smith, Casey; Peterson, Rebecca Lorenz; Hussain, Muhammad Mustafa; Najafi, Khalil

    2013-01-01

    This letter reports, for the first time, heterogeneous integration of bismuth telluride (Bi2Te3) and antimony telluride (Sb 2Te3) thin-film-based thermoelectric ffect transistors) via a characterized TE-film coevaporationand shadow-mask patterning

  13. Contact CMOS imaging of gaseous oxygen sensor array.

    Science.gov (United States)

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  14. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

    Science.gov (United States)

    Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

    2012-01-11

    Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

  15. Rapid manufacturing of low-noise membranes for nanopore sensors by trans-chip illumination lithography

    International Nuclear Information System (INIS)

    Janssen, Xander J A; Jonsson, Magnus P; Plesa, Calin; Soni, Gautam V; Dekker, Cees; Dekker, Nynke H

    2012-01-01

    In recent years, the concept of nanopore sensing has matured from a proof-of-principle method to a widespread, versatile technique for the study of biomolecular properties and interactions. While traditional nanopore devices based on a nanopore in a single layer membrane supported on a silicon chip can be rapidly fabricated using standard microfabrication methods, chips with additional insulating layers beyond the membrane region can provide significantly lower noise levels, but at the expense of requiring more costly and time-consuming fabrication steps. Here we present a novel fabrication protocol that overcomes this issue by enabling rapid and reproducible manufacturing of low-noise membranes for nanopore experiments. The fabrication protocol, termed trans-chip illumination lithography, is based on illuminating a membrane-containing wafer from its backside such that a photoresist (applied on the wafer’s top side) is exposed exclusively in the membrane regions. Trans-chip illumination lithography permits the local modification of membrane regions and hence the fabrication of nanopore chips containing locally patterned insulating layers. This is achieved while maintaining a well-defined area containing a single thin membrane for nanopore drilling. The trans-chip illumination lithography method achieves this without relying on separate masks, thereby eliminating time-consuming alignment steps as well as the need for a mask aligner. Using the presented approach, we demonstrate rapid and reproducible fabrication of nanopore chips that contain small (12 μm × 12 μm) free-standing silicon nitride membranes surrounded by insulating layers. The electrical noise characteristics of these nanopore chips are shown to be superior to those of simpler designs without insulating layers and comparable in quality to more complex designs that are more challenging to fabricate. (paper)

  16. Design of low noise airfoil with high aerodynamic performance for use on small wind turbines

    Institute of Scientific and Technical Information of China (English)

    Taehyung; KIM; Seungmin; LEE; Hogeon; KIM; Soogab; LEE

    2010-01-01

    Wind power is one of the most reliable renewable energy sources and internationally installed capacity is increasing radically every year.Although wind power has been favored by the public in general,the problem with the impact of wind turbine noise on people living in the vicinity of the turbines has been increased.Low noise wind turbine design is becoming more and more important as noise is spreading more adverse effect of wind turbine to public.This paper demonstrates the design of 10 kW class wind turbines,each of three blades,a rotor diameter 6.4 m,a rated rotating speed 200 r/min and a rated wind speed 10 m/s.The optimized airfoil is dedicated for the 75% spanwise position because the dominant source of a wind turbine blade is trailing edge noise from the outer 25% of the blade.Numerical computations are performed for incompressible flow and for Mach number at 0.145 and for Reynolds numbers at 1.02×106 with a lift performance,which is resistant to surface contamination and turbulence intensity.The objectives in the design process are to reduce noise emission,while sustaining high aerodynamic efficiency.Dominant broadband noise sources are predicted by semi-empirical formulas composed of the groundwork by Brooks et al.and Lowson associated with typical wind turbine operation conditions.During the airfoil redesign process,the aerodynamic performance is analyzed to reduce the wind turbine power loss.The results obtained from the design process show that the design method is capable of designing airfoils with reduced noise using a commercial 10 kW class wind turbine blade airfoil as a basis.Therefore,the new optimized airfoil showing 2.9 dB reductions of total sound pressure level(SPL) and higher aerodynamic performance are achieved.

  17. Seismic and resistivity anisotropy analysis at the Low-Noise Underground Laboratory (LSBB) of Rustrel (France)

    Science.gov (United States)

    Zeyen, H. J.; Bereš, J.; Gaffet, S.; Sénéchal, G.; Rousset, D.; Pessel, M.

    2011-12-01

    Many geological materials exhibit anisotropic behaviour. A limestone massif, especially if cracked with fractures and faults in a predominant orientation is expected to manifest seismic and electric resistivity anisotropy. Seismic velocity within air- or water-filled cracks is smaller than in the rock matrix. Therefore, the velocity parallel to fractures, controlled mainly by the rock matrix, is expected to be faster than perpendicular to the fractures, where waves have to cross fractures and rock matrix. Seismic and resistivity measurements were conducted in three underground galleries of the Low-Noise Underground Gallery (LSBB) in southern France forming a horse-shoe setting. The galleries are located inside a karstic limestone massif. Around 22500 first arrival travel-times were picked and different types of pole-pole and dipole-dipole resistivity measurement were carried out in parallel. Resistivities and velocities vary strongly with direction of observation. The direction of fast velocities is at right angle with the one of slow velocities, a typical sign for anisotropy. Observation of a system of subparallel fractures allows to approximate the actual rock anisotropy by a horizontal transverse isotropy model. The dataset was treated by different approaches, including simple cosine fit, inversion of average anisotropy parameters using a Monte-Carlo approach, isotropic and anisotropic tomography inversion. All of the above confirm the directions of fast and slow velocities (30°N and 120°N respectively) and an anisotropy of about 10%. Common measurements of seismic and resistivity data at different periods of the year will have the potential to determine quantitatively the fracture density and the free water content in this karst massif.

  18. CMOS latch-up analysis and prevention

    International Nuclear Information System (INIS)

    Shafer, B.D.

    1975-06-01

    An analytical model is presented which develops relationships between ionization rates, minority carrier lifetimes, and latch-up in bulk CMOS integrated circuits. The basic mechanism for latch-up is the SCR action reported by Gregory and Shafer. The SCR is composed of a vertical NPN transistor formed by the N-channel source diffusion, the P-Well, and the N-substrate. The second part of the SCR is the lateral PNP transistor made up of the P-channel source diffusion, the N-substrate, and P-Well. It is shown that the NPN transistor turns on due to photocurrent-induced lateral voltage drops in the base of the transistor. The gain of this double diffused transistor has been shown to be as high as 100. Therefore, the transistor action of this device produces a much larger current flow in the substrate. This transistor current adds to that produced by the P-Well diode photocurrent in the substrate. It is found that the combined flow of current in the substrate forward biases the base emitter junction of the PNP device long before this could occur due to the P-Well photocurrent alone. The analysis indicated that a CD4007A CMOS device biased in the normal mode of operation should latch at about 2 . 10 8 rads/sec. Experimental results produced latch-up at 1 to 3 . 10 8 rads/sec. (U.S.)

  19. Micromachined high-performance RF passives in CMOS substrate

    International Nuclear Information System (INIS)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-01-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

  20. Jet Propulsion Laboratory/NASA Lewis Research Center space qualified hybrid high temperature superconducting/semiconducting 7.4 GHz low-noise downconverter for NRL HTSSE-II program

    International Nuclear Information System (INIS)

    Javadi, H.H.S.; Bowen, J.G.; Rascoe, D.L.; Chorey, C.M.

    1996-01-01

    A deep space satellite downconverter receiver was proposed by Jet Propulsion Laboratory (JPL) and NASA Lewis Research Center (LeRC) for the Naval Research Laboratory's (NRL) high temperature superconductivity space experiment, phase-II (HTSSE-II) program. Space qualified low-noise cryogenic downconverter receivers utilizing thin-film high temperature superconducting (HTS) passive circuitry and semiconductor active devices were developed and delivered to NRL. The downconverter consists of an HTS preselect filter, a cryogenic low-noise amplifier, a cryogenic mixer, and a cryogenic oscillator with an HTS resonator. HTS components were inserted as the front-end filter and the local oscillator resonator for their superior 77 K performance over the conventional components. The semiconducting low noise amplifier also benefited from cooling to 77 K. The mixer was designed specifically for cryogenic applications and provided low conversion loss and low power consumption. In addition to an engineering model, two space qualified units (qualification, flight) were built and delivered to NRL. Manufacturing, integration and test of the space qualified downconverters adhered to the requirements of JPL class-D space instruments and partially to MIL-STD-883D specifications. The qualification unit has ∼50 K system noise temperature which is a factor of three better than a conventional downconverter at room temperature